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path: root/drivers/gpu/drm/nouveau/nvc0_graph.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nvc0_graph.c')
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_graph.c46
1 files changed, 21 insertions, 25 deletions
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.c b/drivers/gpu/drm/nouveau/nvc0_graph.c
index cf2f6aa920b4..5feacd5d5fa4 100644
--- a/drivers/gpu/drm/nouveau/nvc0_graph.c
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.c
@@ -244,7 +244,6 @@ nvc0_graph_load_context(struct nouveau_channel *chan)
if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
- printk(KERN_ERR "load_ctx 0x%08x\n", nv_rd32(dev, 0x409b00));
return 0;
}
@@ -334,8 +333,6 @@ nvc0_graph_create(struct drm_device *dev)
case 0xc0:
if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
priv->magic_not_rop_nr = 0x07;
- priv->magic419bd0 = 0x0a360000;
- priv->magic419be4 = 0x04c33a54;
/* filled values up to tp_total, the rest 0 */
priv->magicgpc980[0] = 0x22111000;
priv->magicgpc980[1] = 0x00000233;
@@ -345,8 +342,6 @@ nvc0_graph_create(struct drm_device *dev)
} else
if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
priv->magic_not_rop_nr = 0x05;
- priv->magic419bd0 = 0x043c0000;
- priv->magic419be4 = 0x09041208;
priv->magicgpc980[0] = 0x11110000;
priv->magicgpc980[1] = 0x00233222;
priv->magicgpc980[2] = 0x00000000;
@@ -355,8 +350,6 @@ nvc0_graph_create(struct drm_device *dev)
} else
if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
priv->magic_not_rop_nr = 0x06;
- priv->magic419bd0 = 0x023e0000;
- priv->magic419be4 = 0x10414104;
priv->magicgpc980[0] = 0x11110000;
priv->magicgpc980[1] = 0x03332222;
priv->magicgpc980[2] = 0x00000000;
@@ -366,8 +359,6 @@ nvc0_graph_create(struct drm_device *dev)
break;
case 0xc3: /* 450, 4/0/0/0, 2 */
priv->magic_not_rop_nr = 0x03;
- priv->magic419bd0 = 0x00500000;
- priv->magic419be4 = 0x00000000;
priv->magicgpc980[0] = 0x00003210;
priv->magicgpc980[1] = 0x00000000;
priv->magicgpc980[2] = 0x00000000;
@@ -376,8 +367,6 @@ nvc0_graph_create(struct drm_device *dev)
break;
case 0xc4: /* 460, 3/4/0/0, 4 */
priv->magic_not_rop_nr = 0x01;
- priv->magic419bd0 = 0x045c0000;
- priv->magic419be4 = 0x09041208;
priv->magicgpc980[0] = 0x02321100;
priv->magicgpc980[1] = 0x00000000;
priv->magicgpc980[2] = 0x00000000;
@@ -386,14 +375,12 @@ nvc0_graph_create(struct drm_device *dev)
break;
}
- if (!priv->magic419bd0) {
+ if (!priv->magic_not_rop_nr) {
NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
priv->tp_nr[3], priv->rop_nr);
/* use 0xc3's values... */
priv->magic_not_rop_nr = 0x03;
- priv->magic419bd0 = 0x00500000;
- priv->magic419be4 = 0x00000000;
priv->magicgpc980[0] = 0x00003210;
priv->magicgpc980[1] = 0x00000000;
priv->magicgpc980[2] = 0x00000000;
@@ -597,7 +584,7 @@ nvc0_graph_init_ctxctl(struct drm_device *dev)
r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
ret = nvc0_fuc_load_fw(dev, 0x409000, "fuc409c", "fuc409d");
if (ret == 0)
- nvc0_fuc_load_fw(dev, 0x41a000, "fuc41ac", "fuc41ad");
+ ret = nvc0_fuc_load_fw(dev, 0x41a000, "fuc41ac", "fuc41ad");
nv_wr32(dev, 0x000260, r000260);
if (ret)
@@ -699,18 +686,11 @@ nvc0_graph_init(struct drm_device *dev)
nv_wr32(dev, 0x400054, 0x34ce3464);
ret = nvc0_graph_init_ctxctl(dev);
- if (ret)
- return ret;
-
- dev_priv->engine.graph.accel_blocked = false;
+ if (ret == 0)
+ dev_priv->engine.graph.accel_blocked = false;
return 0;
}
-static struct nouveau_enum nvc0_graph_data_error[] = {
- { 5, "INVALID_ENUM" },
- {}
-};
-
static int
nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
{
@@ -753,9 +733,17 @@ nvc0_graph_isr(struct drm_device *dev)
stat &= ~0x00000010;
}
+ if (stat & 0x00000020) {
+ NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
+ "class 0x%04x mthd 0x%04x data 0x%08x\n",
+ chid, inst, subc, class, mthd, data);
+ nv_wr32(dev, 0x400100, 0x00000020);
+ stat &= ~0x00000020;
+ }
+
if (stat & 0x00100000) {
NV_INFO(dev, "PGRAPH: DATA_ERROR [");
- nouveau_enum_print(nvc0_graph_data_error, code);
+ nouveau_enum_print(nv50_data_error_names, code);
printk("] ch %d [0x%010llx] subc %d class 0x%04x "
"mthd 0x%04x data 0x%08x\n",
chid, inst, subc, class, mthd, data);
@@ -763,6 +751,14 @@ nvc0_graph_isr(struct drm_device *dev)
stat &= ~0x00100000;
}
+ if (stat & 0x00200000) {
+ u32 trap = nv_rd32(dev, 0x400108);
+ NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap);
+ nv_wr32(dev, 0x400108, trap);
+ nv_wr32(dev, 0x400100, 0x00200000);
+ stat &= ~0x00200000;
+ }
+
if (stat & 0x00080000) {
u32 ustat = nv_rd32(dev, 0x409c18);
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