diff options
Diffstat (limited to 'arch/sh/include/asm')
| -rw-r--r-- | arch/sh/include/asm/dma-sh.h | 87 | ||||
| -rw-r--r-- | arch/sh/include/asm/dma.h | 9 | ||||
| -rw-r--r-- | arch/sh/include/asm/fixmap.h | 2 | ||||
| -rw-r--r-- | arch/sh/include/asm/i2c-sh7760.h | 2 | ||||
| -rw-r--r-- | arch/sh/include/asm/io.h | 5 | ||||
| -rw-r--r-- | arch/sh/include/asm/io_noioport.h | 41 | ||||
| -rw-r--r-- | arch/sh/include/asm/irq.h | 13 | ||||
| -rw-r--r-- | arch/sh/include/asm/kdebug.h | 2 | ||||
| -rw-r--r-- | arch/sh/include/asm/kgdb.h | 30 | ||||
| -rw-r--r-- | arch/sh/include/asm/machvec.h | 1 | ||||
| -rw-r--r-- | arch/sh/include/asm/pgtable_64.h | 3 | ||||
| -rw-r--r-- | arch/sh/include/asm/processor.h | 10 | ||||
| -rw-r--r-- | arch/sh/include/asm/processor_64.h | 3 | ||||
| -rw-r--r-- | arch/sh/include/asm/stackprotector.h | 27 | ||||
| -rw-r--r-- | arch/sh/include/asm/thread_info.h | 57 | ||||
| -rw-r--r-- | arch/sh/include/asm/topology.h | 25 | ||||
| -rw-r--r-- | arch/sh/include/asm/traps_64.h | 14 |
17 files changed, 152 insertions, 179 deletions
diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h deleted file mode 100644 index f3acb8e34c6b..000000000000 --- a/arch/sh/include/asm/dma-sh.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * arch/sh/include/asm/dma-sh.h - * - * Copyright (C) 2000 Takashi YOSHII - * Copyright (C) 2003 Paul Mundt - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __DMA_SH_H -#define __DMA_SH_H - -#include <asm/dma-register.h> -#include <cpu/dma-register.h> -#include <cpu/dma.h> - -/* DMAOR contorl: The DMAOR access size is different by CPU.*/ -#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \ - defined(CONFIG_CPU_SUBTYPE_SH7724) || \ - defined(CONFIG_CPU_SUBTYPE_SH7780) || \ - defined(CONFIG_CPU_SUBTYPE_SH7785) -#define dmaor_read_reg(n) \ - (n ? __raw_readw(SH_DMAC_BASE1 + DMAOR) \ - : __raw_readw(SH_DMAC_BASE0 + DMAOR)) -#define dmaor_write_reg(n, data) \ - (n ? __raw_writew(data, SH_DMAC_BASE1 + DMAOR) \ - : __raw_writew(data, SH_DMAC_BASE0 + DMAOR)) -#else /* Other CPU */ -#define dmaor_read_reg(n) __raw_readw(SH_DMAC_BASE0 + DMAOR) -#define dmaor_write_reg(n, data) __raw_writew(data, SH_DMAC_BASE0 + DMAOR) -#endif - -static int dmte_irq_map[] __maybe_unused = { -#if (MAX_DMA_CHANNELS >= 4) - DMTE0_IRQ, - DMTE0_IRQ + 1, - DMTE0_IRQ + 2, - DMTE0_IRQ + 3, -#endif -#if (MAX_DMA_CHANNELS >= 6) - DMTE4_IRQ, - DMTE4_IRQ + 1, -#endif -#if (MAX_DMA_CHANNELS >= 8) - DMTE6_IRQ, - DMTE6_IRQ + 1, -#endif -#if (MAX_DMA_CHANNELS >= 12) - DMTE8_IRQ, - DMTE9_IRQ, - DMTE10_IRQ, - DMTE11_IRQ, -#endif -}; - -/* - * Define the default configuration for dual address memory-memory transfer. - * The 0x400 value represents auto-request, external->external. - */ -#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT)) - -/* DMA base address */ -static u32 dma_base_addr[] __maybe_unused = { -#if (MAX_DMA_CHANNELS >= 4) - SH_DMAC_BASE0 + 0x00, /* channel 0 */ - SH_DMAC_BASE0 + 0x10, - SH_DMAC_BASE0 + 0x20, - SH_DMAC_BASE0 + 0x30, -#endif -#if (MAX_DMA_CHANNELS >= 6) - SH_DMAC_BASE0 + 0x50, - SH_DMAC_BASE0 + 0x60, -#endif -#if (MAX_DMA_CHANNELS >= 8) - SH_DMAC_BASE1 + 0x00, - SH_DMAC_BASE1 + 0x10, -#endif -#if (MAX_DMA_CHANNELS >= 12) - SH_DMAC_BASE1 + 0x20, - SH_DMAC_BASE1 + 0x30, - SH_DMAC_BASE1 + 0x50, - SH_DMAC_BASE1 + 0x60, /* channel 11 */ -#endif -}; - -#endif /* __DMA_SH_H */ diff --git a/arch/sh/include/asm/dma.h b/arch/sh/include/asm/dma.h index 6aa2080c0065..fb6e4f7b00a2 100644 --- a/arch/sh/include/asm/dma.h +++ b/arch/sh/include/asm/dma.h @@ -15,17 +15,8 @@ #include <linux/wait.h> #include <linux/sched.h> #include <linux/device.h> -#include <cpu/dma.h> #include <asm-generic/dma.h> -#ifdef CONFIG_NR_DMA_CHANNELS -# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS) -#elif defined(CONFIG_NR_ONCHIP_DMA_CHANNELS) -# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS) -#else -# define MAX_DMA_CHANNELS 0 -#endif - /* * Read and write modes can mean drastically different things depending on the * channel configuration. Consult your DMAC documentation and module diff --git a/arch/sh/include/asm/fixmap.h b/arch/sh/include/asm/fixmap.h index bd7e79a12653..cbe0186b6794 100644 --- a/arch/sh/include/asm/fixmap.h +++ b/arch/sh/include/asm/fixmap.h @@ -96,7 +96,7 @@ extern void __clear_fixmap(enum fixed_addresses idx, pgprot_t flags); #ifdef CONFIG_SUPERH32 #define FIXADDR_TOP (P4SEG - PAGE_SIZE) #else -#define FIXADDR_TOP (0xff000000 - PAGE_SIZE) +#define FIXADDR_TOP ((unsigned long)(-PAGE_SIZE)) #endif #define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) diff --git a/arch/sh/include/asm/i2c-sh7760.h b/arch/sh/include/asm/i2c-sh7760.h index 24182116711f..69fee1239b03 100644 --- a/arch/sh/include/asm/i2c-sh7760.h +++ b/arch/sh/include/asm/i2c-sh7760.h @@ -9,11 +9,9 @@ #define SH7760_I2C0_MMIO 0xFE140000 #define SH7760_I2C0_MMIOEND 0xFE14003B -#define SH7760_I2C0_IRQ 62 #define SH7760_I2C1_MMIO 0xFE150000 #define SH7760_I2C1_MMIOEND 0xFE15003B -#define SH7760_I2C1_IRQ 63 struct sh7760_i2c_platdata { unsigned int speed_khz; diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h index ec464a6b95fe..0cf60a628814 100644 --- a/arch/sh/include/asm/io.h +++ b/arch/sh/include/asm/io.h @@ -218,8 +218,13 @@ __BUILD_IOPORT_STRING(w, u16) __BUILD_IOPORT_STRING(l, u32) __BUILD_IOPORT_STRING(q, u64) +#else /* !CONFIG_HAS_IOPORT */ + +#include <asm/io_noioport.h> + #endif + #define IO_SPACE_LIMIT 0xffffffff /* synco on SH-4A, otherwise a nop */ diff --git a/arch/sh/include/asm/io_noioport.h b/arch/sh/include/asm/io_noioport.h new file mode 100644 index 000000000000..e136d28d1d2e --- /dev/null +++ b/arch/sh/include/asm/io_noioport.h @@ -0,0 +1,41 @@ +#ifndef __ASM_SH_IO_NOIOPORT_H +#define __ASM_SH_IO_NOIOPORT_H + +static inline u8 inb(unsigned long addr) +{ + BUG(); + return -1; +} + +static inline u16 inw(unsigned long addr) +{ + BUG(); + return -1; +} + +static inline u32 inl(unsigned long addr) +{ + BUG(); + return -1; +} + +#define outb(x, y) BUG() +#define outw(x, y) BUG() +#define outl(x, y) BUG() + +#define inb_p(addr) inb(addr) +#define inw_p(addr) inw(addr) +#define inl_p(addr) inl(addr) +#define outb_p(x, addr) outb((x), (addr)) +#define outw_p(x, addr) outw((x), (addr)) +#define outl_p(x, addr) outl((x), (addr)) + +#define insb(a, b, c) BUG() +#define insw(a, b, c) BUG() +#define insl(a, b, c) BUG() + +#define outsb(a, b, c) BUG() +#define outsw(a, b, c) BUG() +#define outsl(a, b, c) BUG() + +#endif /* __ASM_SH_IO_NOIOPORT_H */ diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h index 2a62017eb275..0e4f532e4737 100644 --- a/arch/sh/include/asm/irq.h +++ b/arch/sh/include/asm/irq.h @@ -5,12 +5,15 @@ #include <asm/machvec.h> /* - * A sane default based on a reasonable vector table size, platforms are - * advised to cap this at the hard limit that they're interested in - * through the machvec. + * Only legacy non-sparseirq platforms have to set a reasonably sane + * value here. sparseirq platforms allocate their irq_descs on the fly, + * so will expand automatically based on the number of registered IRQs. */ -#define NR_IRQS 512 -#define NR_IRQS_LEGACY 8 /* Legacy external IRQ0-7 */ +#ifdef CONFIG_SPARSE_IRQ +# define NR_IRQS 8 +#else +# define NR_IRQS 512 +#endif /* * This is a special IRQ number for indicating that no IRQ has been diff --git a/arch/sh/include/asm/kdebug.h b/arch/sh/include/asm/kdebug.h index 5f6d2e9ccb7c..a6201f10c273 100644 --- a/arch/sh/include/asm/kdebug.h +++ b/arch/sh/include/asm/kdebug.h @@ -10,4 +10,6 @@ enum die_val { DIE_SSTEP, }; +extern void printk_address(unsigned long address, int reliable); + #endif /* __ASM_SH_KDEBUG_H */ diff --git a/arch/sh/include/asm/kgdb.h b/arch/sh/include/asm/kgdb.h index f3613952d1ae..9e7d2d1b03e0 100644 --- a/arch/sh/include/asm/kgdb.h +++ b/arch/sh/include/asm/kgdb.h @@ -4,18 +4,6 @@ #include <asm/cacheflush.h> #include <asm/ptrace.h> -/* Same as pt_regs but has vbr in place of syscall_nr */ -struct kgdb_regs { - unsigned long regs[16]; - unsigned long pc; - unsigned long pr; - unsigned long sr; - unsigned long gbr; - unsigned long mach; - unsigned long macl; - unsigned long vbr; -}; - enum regnames { GDB_R0, GDB_R1, GDB_R2, GDB_R3, GDB_R4, GDB_R5, GDB_R6, GDB_R7, GDB_R8, GDB_R9, GDB_R10, GDB_R11, GDB_R12, GDB_R13, GDB_R14, GDB_R15, @@ -23,17 +11,27 @@ enum regnames { GDB_PC, GDB_PR, GDB_SR, GDB_GBR, GDB_MACH, GDB_MACL, GDB_VBR, }; -#define NUMREGBYTES ((GDB_VBR + 1) * 4) +#define _GP_REGS 16 +#define _EXTRA_REGS 7 +#define GDB_SIZEOF_REG sizeof(u32) + +#define DBG_MAX_REG_NUM (_GP_REGS + _EXTRA_REGS) +#define NUMREGBYTES (DBG_MAX_REG_NUM * sizeof(GDB_SIZEOF_REG)) static inline void arch_kgdb_breakpoint(void) { __asm__ __volatile__ ("trapa #0x3c\n"); } -#define BUFMAX 2048 - -#define CACHE_FLUSH_IS_SAFE 1 #define BREAK_INSTR_SIZE 2 +#define BUFMAX 2048 + +#ifdef CONFIG_SMP +# define CACHE_FLUSH_IS_SAFE 0 +#else +# define CACHE_FLUSH_IS_SAFE 1 +#endif + #define GDB_ADJUSTS_BREAK_OFFSET #endif /* __ASM_SH_KGDB_H */ diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h index 57c5c3d0f39f..eb9c20d971dd 100644 --- a/arch/sh/include/asm/machvec.h +++ b/arch/sh/include/asm/machvec.h @@ -17,7 +17,6 @@ struct sh_machine_vector { void (*mv_setup)(char **cmdline_p); const char *mv_name; - int mv_nr_irqs; int (*mv_irq_demux)(int irq); void (*mv_init_irq)(void); diff --git a/arch/sh/include/asm/pgtable_64.h b/arch/sh/include/asm/pgtable_64.h index 42cb9dd52161..dda8c82601b9 100644 --- a/arch/sh/include/asm/pgtable_64.h +++ b/arch/sh/include/asm/pgtable_64.h @@ -87,9 +87,6 @@ static __inline__ void set_pte(pte_t *pteptr, pte_t pteval) #define pte_unmap(pte) do { } while (0) #ifndef __ASSEMBLY__ -#define IOBASE_VADDR 0xff000000 -#define IOBASE_END 0xffffffff - /* * PTEL coherent flags. * See Chapter 17 ST50 CPU Core Volume 1, Architecture. diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h index a229c393826a..3d14aeaef57c 100644 --- a/arch/sh/include/asm/processor.h +++ b/arch/sh/include/asm/processor.h @@ -18,7 +18,8 @@ enum cpu_type { CPU_SH7619, /* SH-2A types */ - CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG, + CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269, + CPU_MXG, /* SH-3 types */ CPU_SH7705, CPU_SH7706, CPU_SH7707, @@ -32,7 +33,7 @@ enum cpu_type { /* SH-4A types */ CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, - CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3, + CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SH7734, CPU_SHX3, /* SH4AL-DSP types */ CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372, @@ -85,10 +86,6 @@ struct sh_cpuinfo { struct tlb_info itlb; struct tlb_info dtlb; -#ifdef CONFIG_SMP - struct task_struct *idle; -#endif - unsigned int phys_bits; unsigned long flags; } __attribute__ ((aligned(L1_CACHE_BYTES))); @@ -102,7 +99,6 @@ extern struct sh_cpuinfo cpu_data[]; #define cpu_relax() barrier() void default_idle(void); -void cpu_idle_wait(void); void stop_this_cpu(void *); /* Forward decl */ diff --git a/arch/sh/include/asm/processor_64.h b/arch/sh/include/asm/processor_64.h index fe99afecfbc5..cd6029fb2c01 100644 --- a/arch/sh/include/asm/processor_64.h +++ b/arch/sh/include/asm/processor_64.h @@ -121,7 +121,6 @@ struct thread_struct { NULL for a kernel thread. */ struct pt_regs *uregs; - unsigned long trap_no, error_code; unsigned long address; /* Hardware debugging registers may come here */ @@ -138,8 +137,6 @@ struct thread_struct { .pc = 0, \ .kregs = &fake_swapper_regs, \ .uregs = NULL, \ - .trap_no = 0, \ - .error_code = 0, \ .address = 0, \ .flags = 0, \ } diff --git a/arch/sh/include/asm/stackprotector.h b/arch/sh/include/asm/stackprotector.h new file mode 100644 index 000000000000..d9df3a76847c --- /dev/null +++ b/arch/sh/include/asm/stackprotector.h @@ -0,0 +1,27 @@ +#ifndef __ASM_SH_STACKPROTECTOR_H +#define __ASM_SH_STACKPROTECTOR_H + +#include <linux/random.h> +#include <linux/version.h> + +extern unsigned long __stack_chk_guard; + +/* + * Initialize the stackprotector canary value. + * + * NOTE: this must only be called from functions that never return, + * and it must always be inlined. + */ +static __always_inline void boot_init_stack_canary(void) +{ + unsigned long canary; + + /* Try to get a semi random initial value. */ + get_random_bytes(&canary, sizeof(canary)); + canary ^= LINUX_VERSION_CODE; + + current->stack_canary = canary; + __stack_chk_guard = current->stack_canary; +} + +#endif /* __ASM_SH_STACKPROTECTOR_H */ diff --git a/arch/sh/include/asm/thread_info.h b/arch/sh/include/asm/thread_info.h index 20ee40af16e9..0c04ffc4f12c 100644 --- a/arch/sh/include/asm/thread_info.h +++ b/arch/sh/include/asm/thread_info.h @@ -10,8 +10,18 @@ * - Incorporating suggestions made by Linus Torvalds and Dave Miller */ #ifdef __KERNEL__ + #include <asm/page.h> +/* + * Page fault error code bits + */ +#define FAULT_CODE_WRITE (1 << 0) /* write access */ +#define FAULT_CODE_INITIAL (1 << 1) /* initial page write */ +#define FAULT_CODE_ITLB (1 << 2) /* ITLB miss */ +#define FAULT_CODE_PROT (1 << 3) /* protection fault */ +#define FAULT_CODE_USER (1 << 4) /* user-mode access */ + #ifndef __ASSEMBLY__ #include <asm/processor.h> @@ -88,29 +98,23 @@ static inline struct thread_info *current_thread_info(void) return ti; } -/* thread information allocation */ -#if THREAD_SHIFT >= PAGE_SHIFT - #define THREAD_SIZE_ORDER (THREAD_SHIFT - PAGE_SHIFT) -#endif - -extern struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node); -extern void free_thread_info(struct thread_info *ti); extern void arch_task_cache_init(void); -#define arch_task_cache_init arch_task_cache_init extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); +extern void arch_release_task_struct(struct task_struct *tsk); extern void init_thread_xstate(void); -#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR - #endif /* __ASSEMBLY__ */ /* - * thread information flags - * - these are process state flags that various assembly files may need to access - * - pending work-to-be-done flags are in LSW - * - other flags in MSW + * Thread information flags + * + * - Limited to 24 bits, upper byte used for fault code encoding. + * + * - _TIF_ALLWORK_MASK and _TIF_WORK_MASK need to fit within 2 bytes, or + * we blow the tst immediate size constraints and need to fix up + * arch/sh/kernel/entry-common.S. */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ #define TIF_SIGPENDING 1 /* signal pending */ @@ -133,12 +137,6 @@ extern void init_thread_xstate(void); #define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT) #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) -/* - * _TIF_ALLWORK_MASK and _TIF_WORK_MASK need to fit within 2 bytes, or we - * blow the tst immediate size constraints and need to fix up - * arch/sh/kernel/entry-common.S. - */ - /* work to do in syscall trace */ #define _TIF_WORK_SYSCALL_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \ _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \ @@ -165,6 +163,7 @@ extern void init_thread_xstate(void); #define TS_USEDFPU 0x0002 /* FPU used by this task this quantum */ #ifndef __ASSEMBLY__ + #define HAVE_SET_RESTORE_SIGMASK 1 static inline void set_restore_sigmask(void) { @@ -172,6 +171,24 @@ static inline void set_restore_sigmask(void) ti->status |= TS_RESTORE_SIGMASK; set_bit(TIF_SIGPENDING, (unsigned long *)&ti->flags); } + +#define TI_FLAG_FAULT_CODE_SHIFT 24 + +/* + * Additional thread flag encoding + */ +static inline void set_thread_fault_code(unsigned int val) +{ + struct thread_info *ti = current_thread_info(); + ti->flags = (ti->flags & (~0 >> (32 - TI_FLAG_FAULT_CODE_SHIFT))) + | (val << TI_FLAG_FAULT_CODE_SHIFT); +} + +static inline unsigned int get_thread_fault_code(void) +{ + struct thread_info *ti = current_thread_info(); + return ti->flags >> TI_FLAG_FAULT_CODE_SHIFT; +} #endif /* !__ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/arch/sh/include/asm/topology.h b/arch/sh/include/asm/topology.h index 88e734069fa6..b0a282d65f6a 100644 --- a/arch/sh/include/asm/topology.h +++ b/arch/sh/include/asm/topology.h @@ -3,31 +3,6 @@ #ifdef CONFIG_NUMA -/* sched_domains SD_NODE_INIT for sh machines */ -#define SD_NODE_INIT (struct sched_domain) { \ - .parent = NULL, \ - .child = NULL, \ - .groups = NULL, \ - .min_interval = 8, \ - .max_interval = 32, \ - .busy_factor = 32, \ - .imbalance_pct = 125, \ - .cache_nice_tries = 2, \ - .busy_idx = 3, \ - .idle_idx = 2, \ - .newidle_idx = 0, \ - .wake_idx = 0, \ - .forkexec_idx = 0, \ - .flags = SD_LOAD_BALANCE \ - | SD_BALANCE_FORK \ - | SD_BALANCE_EXEC \ - | SD_BALANCE_NEWIDLE \ - | SD_SERIALIZE, \ - .last_balance = jiffies, \ - .balance_interval = 1, \ - .nr_balance_failed = 0, \ -} - #define cpu_to_node(cpu) ((void)(cpu),0) #define parent_node(node) ((void)(node),0) diff --git a/arch/sh/include/asm/traps_64.h b/arch/sh/include/asm/traps_64.h index c52d7f9a06c1..ef5eff919449 100644 --- a/arch/sh/include/asm/traps_64.h +++ b/arch/sh/include/asm/traps_64.h @@ -10,8 +10,22 @@ #ifndef __ASM_SH_TRAPS_64_H #define __ASM_SH_TRAPS_64_H +#include <cpu/registers.h> + extern void phys_stext(void); +#define lookup_exception_vector() \ +({ \ + unsigned long _vec; \ + \ + __asm__ __volatile__ ( \ + "getcon " __EXPEVT ", %0\n\t" \ + : "=r" (_vec) \ + ); \ + \ + _vec; \ +}) + static inline void trigger_address_error(void) { phys_stext(); |
