diff options
Diffstat (limited to 'arch/sh/boards/renesas')
| -rw-r--r-- | arch/sh/boards/renesas/ap325rxa/Makefile | 1 | ||||
| -rw-r--r-- | arch/sh/boards/renesas/ap325rxa/setup.c | 313 | ||||
| -rw-r--r-- | arch/sh/boards/renesas/migor/Kconfig | 15 | ||||
| -rw-r--r-- | arch/sh/boards/renesas/migor/Makefile | 1 | ||||
| -rw-r--r-- | arch/sh/boards/renesas/migor/lcd_qvga.c | 165 | ||||
| -rw-r--r-- | arch/sh/boards/renesas/migor/setup.c | 276 | ||||
| -rw-r--r-- | arch/sh/boards/renesas/rsk7203/Makefile | 1 | ||||
| -rw-r--r-- | arch/sh/boards/renesas/rsk7203/setup.c | 126 | ||||
| -rw-r--r-- | arch/sh/boards/renesas/sh7763rdp/Makefile | 1 | ||||
| -rw-r--r-- | arch/sh/boards/renesas/sh7763rdp/irq.c | 45 | ||||
| -rw-r--r-- | arch/sh/boards/renesas/sh7763rdp/setup.c | 128 | ||||
| -rw-r--r-- | arch/sh/boards/renesas/sh7785lcr/Makefile | 1 | ||||
| -rw-r--r-- | arch/sh/boards/renesas/sh7785lcr/setup.c | 302 |
13 files changed, 1370 insertions, 5 deletions
diff --git a/arch/sh/boards/renesas/ap325rxa/Makefile b/arch/sh/boards/renesas/ap325rxa/Makefile new file mode 100644 index 000000000000..f663768429f0 --- /dev/null +++ b/arch/sh/boards/renesas/ap325rxa/Makefile @@ -0,0 +1 @@ +obj-y := setup.o diff --git a/arch/sh/boards/renesas/ap325rxa/setup.c b/arch/sh/boards/renesas/ap325rxa/setup.c new file mode 100644 index 000000000000..7fa74462bd9f --- /dev/null +++ b/arch/sh/boards/renesas/ap325rxa/setup.c @@ -0,0 +1,313 @@ +/* + * Renesas - AP-325RXA + * (Compatible with Algo System ., LTD. - AP-320A) + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Author : Yusuke Goda <goda.yuske@renesas.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/delay.h> +#include <linux/smc911x.h> +#include <media/soc_camera_platform.h> +#include <media/sh_mobile_ceu.h> +#include <asm/sh_mobile_lcdc.h> +#include <asm/io.h> +#include <asm/clock.h> + +static struct smc911x_platdata smc911x_info = { + .flags = SMC911X_USE_32BIT, + .irq_flags = IRQF_TRIGGER_LOW, +}; + +static struct resource smc9118_resources[] = { + [0] = { + .start = 0xb6080000, + .end = 0xb60fffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 35, + .end = 35, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device smc9118_device = { + .name = "smc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smc9118_resources), + .resource = smc9118_resources, + .dev = { + .platform_data = &smc911x_info, + }, +}; + +static struct mtd_partition ap325rxa_nor_flash_partitions[] = { + { + .name = "uboot", + .offset = 0, + .size = (1 * 1024 * 1024), + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = (2 * 1024 * 1024), + }, { + .name = "other", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data ap325rxa_nor_flash_data = { + .width = 2, + .parts = ap325rxa_nor_flash_partitions, + .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions), +}; + +static struct resource ap325rxa_nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0x00000000, + .end = 0x00ffffff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device ap325rxa_nor_flash_device = { + .name = "physmap-flash", + .resource = ap325rxa_nor_flash_resources, + .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources), + .dev = { + .platform_data = &ap325rxa_nor_flash_data, + }, +}; + +#define FPGA_LCDREG 0xB4100180 +#define FPGA_BKLREG 0xB4100212 +#define FPGA_LCDREG_VAL 0x0018 +#define PORT_PHCR 0xA405010E +#define PORT_PLCR 0xA4050114 +#define PORT_PMCR 0xA4050116 +#define PORT_PRCR 0xA405011C +#define PORT_PSCR 0xA405011E +#define PORT_PZCR 0xA405014C +#define PORT_HIZCRA 0xA4050158 +#define PORT_MSELCRB 0xA4050182 +#define PORT_PSDR 0xA405013E +#define PORT_PZDR 0xA405016C +#define PORT_PSELD 0xA4050154 + +static void ap320_wvga_power_on(void *board_data) +{ + msleep(100); + + /* ASD AP-320/325 LCD ON */ + ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG); + + /* backlight */ + ctrl_outw((ctrl_inw(PORT_PSCR) & ~0x00C0) | 0x40, PORT_PSCR); + ctrl_outb(ctrl_inb(PORT_PSDR) & ~0x08, PORT_PSDR); + ctrl_outw(0x100, FPGA_BKLREG); +} + +static struct sh_mobile_lcdc_info lcdc_info = { + .clock_source = LCDC_CLK_EXTERNAL, + .ch[0] = { + .chan = LCDC_CHAN_MAINLCD, + .bpp = 16, + .interface_type = RGB18, + .clock_divider = 1, + .lcd_cfg = { + .name = "LB070WV1", + .xres = 800, + .yres = 480, + .left_margin = 40, + .right_margin = 160, + .hsync_len = 8, + .upper_margin = 63, + .lower_margin = 80, + .vsync_len = 1, + .sync = 0, /* hsync and vsync are active low */ + }, + .board_cfg = { + .display_on = ap320_wvga_power_on, + }, + } +}; + +static struct resource lcdc_resources[] = { + [0] = { + .name = "LCDC", + .start = 0xfe940000, /* P4-only space */ + .end = 0xfe941fff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device lcdc_device = { + .name = "sh_mobile_lcdc_fb", + .num_resources = ARRAY_SIZE(lcdc_resources), + .resource = lcdc_resources, + .dev = { + .platform_data = &lcdc_info, + }, +}; + +static unsigned char camera_ncm03j_magic[] = +{ + 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8, + 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36, + 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F, + 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55, + 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12, + 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0, + 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F, + 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A, + 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A, + 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A, + 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56, + 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37, + 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A, + 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56, + 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC, + 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F, +}; + +static int camera_set_capture(struct soc_camera_platform_info *info, + int enable) +{ + struct i2c_adapter *a = i2c_get_adapter(0); + struct i2c_msg msg; + int ret = 0; + int i; + + if (!enable) + return 0; /* no disable for now */ + + for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) { + u_int8_t buf[8]; + + msg.addr = 0x6e; + msg.buf = buf; + msg.len = 2; + msg.flags = 0; + + buf[0] = camera_ncm03j_magic[i]; + buf[1] = camera_ncm03j_magic[i + 1]; + + ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1); + } + + return ret; +} + +static struct soc_camera_platform_info camera_info = { + .iface = 0, + .format_name = "UYVY", + .format_depth = 16, + .format = { + .pixelformat = V4L2_PIX_FMT_UYVY, + .colorspace = V4L2_COLORSPACE_SMPTE170M, + .width = 640, + .height = 480, + }, + .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | + SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8, + .set_capture = camera_set_capture, +}; + +static struct platform_device camera_device = { + .name = "soc_camera_platform", + .dev = { + .platform_data = &camera_info, + }, +}; + +static struct sh_mobile_ceu_info sh_mobile_ceu_info = { + .flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | + SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8, +}; + +static struct resource ceu_resources[] = { + [0] = { + .name = "CEU", + .start = 0xfe910000, + .end = 0xfe91009f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 52, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device ceu_device = { + .name = "sh_mobile_ceu", + .num_resources = ARRAY_SIZE(ceu_resources), + .resource = ceu_resources, + .dev = { + .platform_data = &sh_mobile_ceu_info, + }, +}; + +static struct platform_device *ap325rxa_devices[] __initdata = { + &smc9118_device, + &ap325rxa_nor_flash_device, + &lcdc_device, + &ceu_device, + &camera_device, +}; + +static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = { +}; + +static int __init ap325rxa_devices_setup(void) +{ + clk_always_enable("mstp200"); /* LCDC */ + clk_always_enable("mstp203"); /* CEU */ + + platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20); + + i2c_register_board_info(0, ap325rxa_i2c_devices, + ARRAY_SIZE(ap325rxa_i2c_devices)); + + return platform_add_devices(ap325rxa_devices, + ARRAY_SIZE(ap325rxa_devices)); +} +device_initcall(ap325rxa_devices_setup); + +static void __init ap325rxa_setup(char **cmdline_p) +{ + /* LCDC configuration */ + ctrl_outw(ctrl_inw(PORT_PHCR) & ~0xffff, PORT_PHCR); + ctrl_outw(ctrl_inw(PORT_PLCR) & ~0xffff, PORT_PLCR); + ctrl_outw(ctrl_inw(PORT_PMCR) & ~0xffff, PORT_PMCR); + ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x03ff, PORT_PRCR); + ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01C0, PORT_HIZCRA); + + /* CEU */ + ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB); + ctrl_outw(ctrl_inw(PORT_PSELD) & ~0x0003, PORT_PSELD); + ctrl_outw((ctrl_inw(PORT_PZCR) & ~0xff00) | 0x5500, PORT_PZCR); + ctrl_outb((ctrl_inb(PORT_PZDR) & ~0xf0) | 0x20, PORT_PZDR); +} + +static struct sh_machine_vector mv_ap325rxa __initmv = { + .mv_name = "AP-325RXA", + .mv_setup = ap325rxa_setup, +}; diff --git a/arch/sh/boards/renesas/migor/Kconfig b/arch/sh/boards/renesas/migor/Kconfig new file mode 100644 index 000000000000..a7b3b728ec3c --- /dev/null +++ b/arch/sh/boards/renesas/migor/Kconfig @@ -0,0 +1,15 @@ +if SH_MIGOR + +choice + prompt "Migo-R LCD Panel Board Selection" + default SH_MIGOR_QVGA + +config SH_MIGOR_QVGA + bool "QVGA (320x240)" + +config SH_MIGOR_RTA_WVGA + bool "RTA WVGA (800x480)" + +endchoice + +endif diff --git a/arch/sh/boards/renesas/migor/Makefile b/arch/sh/boards/renesas/migor/Makefile index 77037567633b..5f231dd25c0e 100644 --- a/arch/sh/boards/renesas/migor/Makefile +++ b/arch/sh/boards/renesas/migor/Makefile @@ -1 +1,2 @@ obj-y := setup.o +obj-$(CONFIG_SH_MIGOR_QVGA) += lcd_qvga.o diff --git a/arch/sh/boards/renesas/migor/lcd_qvga.c b/arch/sh/boards/renesas/migor/lcd_qvga.c new file mode 100644 index 000000000000..6e9609596448 --- /dev/null +++ b/arch/sh/boards/renesas/migor/lcd_qvga.c @@ -0,0 +1,165 @@ +/* + * Support for SuperH MigoR Quarter VGA LCD Panel + * + * Copyright (C) 2008 Magnus Damm + * + * Based on lcd_powertip.c from Kenati Technologies Pvt Ltd. + * Copyright (c) 2007 Ujjwal Pande <ujjwal@kenati.com>, + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/fb.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <asm/sh_mobile_lcdc.h> +#include <asm/migor.h> + +/* LCD Module is a PH240320T according to board schematics. This module + * is made up of a 240x320 LCD hooked up to a R61505U (or HX8347-A01?) + * Driver IC. This IC is connected to the SH7722 built-in LCDC using a + * SYS-80 interface configured in 16 bit mode. + * + * Index 0: "Device Code Read" returns 0x1505. + */ + +static void reset_lcd_module(void) +{ + ctrl_outb(ctrl_inb(PORT_PHDR) & ~0x04, PORT_PHDR); + mdelay(2); + ctrl_outb(ctrl_inb(PORT_PHDR) | 0x04, PORT_PHDR); + mdelay(1); +} + +/* DB0-DB7 are connected to D1-D8, and DB8-DB15 to D10-D17 */ + +static unsigned long adjust_reg18(unsigned short data) +{ + unsigned long tmp1, tmp2; + + tmp1 = (data<<1 | 0x00000001) & 0x000001FF; + tmp2 = (data<<2 | 0x00000200) & 0x0003FE00; + return tmp1 | tmp2; +} + +static void write_reg(void *sys_ops_handle, + struct sh_mobile_lcdc_sys_bus_ops *sys_ops, + unsigned short reg, unsigned short data) +{ + sys_ops->write_index(sys_ops_handle, adjust_reg18(reg << 8 | data)); +} + +static void write_reg16(void *sys_ops_handle, + struct sh_mobile_lcdc_sys_bus_ops *sys_ops, + unsigned short reg, unsigned short data) +{ + sys_ops->write_index(sys_ops_handle, adjust_reg18(reg)); + sys_ops->write_data(sys_ops_handle, adjust_reg18(data)); +} + +static unsigned long read_reg16(void *sys_ops_handle, + struct sh_mobile_lcdc_sys_bus_ops *sys_ops, + unsigned short reg) +{ + unsigned long data; + + sys_ops->write_index(sys_ops_handle, adjust_reg18(reg)); + data = sys_ops->read_data(sys_ops_handle); + return ((data >> 1) & 0xff) | ((data >> 2) & 0xff00); +} + +static void migor_lcd_qvga_seq(void *sys_ops_handle, + struct sh_mobile_lcdc_sys_bus_ops *sys_ops, + unsigned short const *data, int no_data) +{ + int i; + + for (i = 0; i < no_data; i += 2) + write_reg16(sys_ops_handle, sys_ops, data[i], data[i + 1]); +} + +static const unsigned short sync_data[] = { + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +}; + +static const unsigned short magic0_data[] = { + 0x0060, 0x2700, 0x0008, 0x0808, 0x0090, 0x001A, 0x0007, 0x0001, + 0x0017, 0x0001, 0x0019, 0x0000, 0x0010, 0x17B0, 0x0011, 0x0116, + 0x0012, 0x0198, 0x0013, 0x1400, 0x0029, 0x000C, 0x0012, 0x01B8, +}; + +static const unsigned short magic1_data[] = { + 0x0030, 0x0307, 0x0031, 0x0303, 0x0032, 0x0603, 0x0033, 0x0202, + 0x0034, 0x0202, 0x0035, 0x0202, 0x0036, 0x1F1F, 0x0037, 0x0303, + 0x0038, 0x0303, 0x0039, 0x0603, 0x003A, 0x0202, 0x003B, 0x0102, + 0x003C, 0x0204, 0x003D, 0x0000, 0x0001, 0x0100, 0x0002, 0x0300, + 0x0003, 0x5028, 0x0020, 0x00ef, 0x0021, 0x0000, 0x0004, 0x0000, + 0x0009, 0x0000, 0x000A, 0x0008, 0x000C, 0x0000, 0x000D, 0x0000, + 0x0015, 0x8000, +}; + +static const unsigned short magic2_data[] = { + 0x0061, 0x0001, 0x0092, 0x0100, 0x0093, 0x0001, 0x0007, 0x0021, +}; + +static const unsigned short magic3_data[] = { + 0x0010, 0x16B0, 0x0011, 0x0111, 0x0007, 0x0061, +}; + +int migor_lcd_qvga_setup(void *board_data, void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so) +{ + unsigned long xres = 320; + unsigned long yres = 240; + int k; + + reset_lcd_module(); + migor_lcd_qvga_seq(sohandle, so, sync_data, ARRAY_SIZE(sync_data)); + + if (read_reg16(sohandle, so, 0) != 0x1505) + return -ENODEV; + + pr_info("Migo-R QVGA LCD Module detected.\n"); + + migor_lcd_qvga_seq(sohandle, so, sync_data, ARRAY_SIZE(sync_data)); + write_reg16(sohandle, so, 0x00A4, 0x0001); + mdelay(10); + + migor_lcd_qvga_seq(sohandle, so, magic0_data, ARRAY_SIZE(magic0_data)); + mdelay(100); + + migor_lcd_qvga_seq(sohandle, so, magic1_data, ARRAY_SIZE(magic1_data)); + write_reg16(sohandle, so, 0x0050, 0xef - (yres - 1)); + write_reg16(sohandle, so, 0x0051, 0x00ef); + write_reg16(sohandle, so, 0x0052, 0x0000); + write_reg16(sohandle, so, 0x0053, xres - 1); + + migor_lcd_qvga_seq(sohandle, so, magic2_data, ARRAY_SIZE(magic2_data)); + mdelay(10); + + migor_lcd_qvga_seq(sohandle, so, magic3_data, ARRAY_SIZE(magic3_data)); + mdelay(40); + + /* clear GRAM to avoid displaying garbage */ + + write_reg16(sohandle, so, 0x0020, 0x0000); /* horiz addr */ + write_reg16(sohandle, so, 0x0021, 0x0000); /* vert addr */ + + for (k = 0; k < (xres * 256); k++) /* yes, 256 words per line */ + write_reg16(sohandle, so, 0x0022, 0x0000); + + write_reg16(sohandle, so, 0x0020, 0x0000); /* reset horiz addr */ + write_reg16(sohandle, so, 0x0021, 0x0000); /* reset vert addr */ + write_reg16(sohandle, so, 0x0007, 0x0173); + mdelay(40); + + /* enable display */ + write_reg(sohandle, so, 0x00, 0x22); + mdelay(100); + return 0; +} diff --git a/arch/sh/boards/renesas/migor/setup.c b/arch/sh/boards/renesas/migor/setup.c index 963c99322095..7bd365ad2d06 100644 --- a/arch/sh/boards/renesas/migor/setup.c +++ b/arch/sh/boards/renesas/migor/setup.c @@ -15,9 +15,15 @@ #include <linux/mtd/nand.h> #include <linux/i2c.h> #include <linux/smc91x.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <media/soc_camera_platform.h> +#include <media/sh_mobile_ceu.h> +#include <asm/clock.h> #include <asm/machvec.h> #include <asm/io.h> #include <asm/sh_keysc.h> +#include <asm/sh_mobile_lcdc.h> #include <asm/migor.h> /* Address IRQ Size Bus Description @@ -198,14 +204,237 @@ static struct platform_device migor_nand_flash_device = { } }; +static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = { +#ifdef CONFIG_SH_MIGOR_RTA_WVGA + .clock_source = LCDC_CLK_BUS, + .ch[0] = { + .chan = LCDC_CHAN_MAINLCD, + .bpp = 16, + .interface_type = RGB16, + .clock_divider = 2, + .lcd_cfg = { + .name = "LB070WV1", + .xres = 800, + .yres = 480, + .left_margin = 64, + .right_margin = 16, + .hsync_len = 120, + .upper_margin = 1, + .lower_margin = 17, + .vsync_len = 2, + .sync = 0, + }, + } +#endif +#ifdef CONFIG_SH_MIGOR_QVGA + .clock_source = LCDC_CLK_PERIPHERAL, + .ch[0] = { + .chan = LCDC_CHAN_MAINLCD, + .bpp = 16, + .interface_type = SYS16A, + .clock_divider = 10, + .lcd_cfg = { + .name = "PH240320T", + .xres = 320, + .yres = 240, + .left_margin = 0, + .right_margin = 16, + .hsync_len = 8, + .upper_margin = 1, + .lower_margin = 17, + .vsync_len = 2, + .sync = FB_SYNC_HOR_HIGH_ACT, + }, + .board_cfg = { + .setup_sys = migor_lcd_qvga_setup, + }, + .sys_bus_cfg = { + .ldmt2r = 0x06000a09, + .ldmt3r = 0x180e3418, + }, + } +#endif +}; + +static struct resource migor_lcdc_resources[] = { + [0] = { + .name = "LCDC", + .start = 0xfe940000, /* P4-only space */ + .end = 0xfe941fff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device migor_lcdc_device = { + .name = "sh_mobile_lcdc_fb", + .num_resources = ARRAY_SIZE(migor_lcdc_resources), + .resource = migor_lcdc_resources, + .dev = { + .platform_data = &sh_mobile_lcdc_info, + }, +}; + +static struct clk *camera_clk; + +static void camera_power_on(void) +{ + unsigned char value; + + camera_clk = clk_get(NULL, "video_clk"); + clk_set_rate(camera_clk, 24000000); + clk_enable(camera_clk); /* start VIO_CKO */ + + mdelay(10); + value = ctrl_inb(PORT_PTDR); + value &= ~0x09; +#ifndef CONFIG_SH_MIGOR_RTA_WVGA + value |= 0x01; +#endif + ctrl_outb(value, PORT_PTDR); + mdelay(10); + + ctrl_outb(value | 8, PORT_PTDR); +} + +static void camera_power_off(void) +{ + clk_disable(camera_clk); /* stop VIO_CKO */ + clk_put(camera_clk); + + ctrl_outb(ctrl_inb(PORT_PTDR) & ~0x08, PORT_PTDR); +} + +static unsigned char camera_ov772x_magic[] = +{ + 0x09, 0x01, 0x0c, 0x10, 0x0d, 0x41, 0x0e, 0x01, + 0x12, 0x00, 0x13, 0x8F, 0x14, 0x4A, 0x15, 0x00, + 0x16, 0x00, 0x17, 0x23, 0x18, 0xa0, 0x19, 0x07, + 0x1a, 0xf0, 0x1b, 0x40, 0x1f, 0x00, 0x20, 0x10, + 0x22, 0xff, 0x23, 0x01, 0x28, 0x00, 0x29, 0xa0, + 0x2a, 0x00, 0x2b, 0x00, 0x2c, 0xf0, 0x2d, 0x00, + 0x2e, 0x00, 0x30, 0x80, 0x31, 0x60, 0x32, 0x00, + 0x33, 0x00, 0x34, 0x00, 0x3d, 0x80, 0x3e, 0xe2, + 0x3f, 0x1f, 0x42, 0x80, 0x43, 0x80, 0x44, 0x80, + 0x45, 0x80, 0x46, 0x00, 0x47, 0x00, 0x48, 0x00, + 0x49, 0x50, 0x4a, 0x30, 0x4b, 0x50, 0x4c, 0x50, + 0x4d, 0x00, 0x4e, 0xef, 0x4f, 0x10, 0x50, 0x60, + 0x51, 0x00, 0x52, 0x00, 0x53, 0x24, 0x54, 0x7a, + 0x55, 0xfc, 0x62, 0xff, 0x63, 0xf0, 0x64, 0x1f, + 0x65, 0x00, 0x66, 0x10, 0x67, 0x00, 0x68, 0x00, + 0x69, 0x5c, 0x6a, 0x11, 0x6b, 0xa2, 0x6c, 0x01, + 0x6d, 0x50, 0x6e, 0x80, 0x6f, 0x80, 0x70, 0x0f, + 0x71, 0x00, 0x72, 0x00, 0x73, 0x0f, 0x74, 0x0f, + 0x75, 0xff, 0x78, 0x10, 0x79, 0x70, 0x7a, 0x70, + 0x7b, 0xf0, 0x7c, 0xf0, 0x7d, 0xf0, 0x7e, 0x0e, + 0x7f, 0x1a, 0x80, 0x31, 0x81, 0x5a, 0x82, 0x69, + 0x83, 0x75, 0x84, 0x7e, 0x85, 0x88, 0x86, 0x8f, + 0x87, 0x96, 0x88, 0xa3, 0x89, 0xaf, 0x8a, 0xc4, + 0x8b, 0xd7, 0x8c, 0xe8, 0x8d, 0x20, 0x8e, 0x00, + 0x8f, 0x00, 0x90, 0x08, 0x91, 0x10, 0x92, 0x1f, + 0x93, 0x01, 0x94, 0x2c, 0x95, 0x24, 0x96, 0x08, + 0x97, 0x14, 0x98, 0x24, 0x99, 0x38, 0x9a, 0x9e, + 0x9b, 0x00, 0x9c, 0x40, 0x9e, 0x11, 0x9f, 0x02, + 0xa0, 0x00, 0xa1, 0x40, 0xa2, 0x40, 0xa3, 0x06, + 0xa4, 0x00, 0xa6, 0x00, 0xa7, 0x40, 0xa8, 0x40, + 0xa9, 0x80, 0xaa, 0x80, 0xab, 0x06, 0xac, 0xff, + 0x12, 0x06, 0x64, 0x3f, 0x12, 0x46, 0x17, 0x3f, + 0x18, 0x50, 0x19, 0x03, 0x1a, 0x78, 0x29, 0x50, + 0x2c, 0x78, +}; + +static int ov772x_set_capture(struct soc_camera_platform_info *info, + int enable) +{ + struct i2c_adapter *a = i2c_get_adapter(0); + struct i2c_msg msg; + int ret = 0; + int i; + + if (!enable) + return 0; /* camera_power_off() is enough */ + + for (i = 0; i < ARRAY_SIZE(camera_ov772x_magic); i += 2) { + u_int8_t buf[8]; + + msg.addr = 0x21; + msg.buf = buf; + msg.len = 2; + msg.flags = 0; + + buf[0] = camera_ov772x_magic[i]; + buf[1] = camera_ov772x_magic[i + 1]; + + ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1); + } + + return ret; +} + +static struct soc_camera_platform_info ov772x_info = { + .iface = 0, + .format_name = "RGB565", + .format_depth = 16, + .format = { + .pixelformat = V4L2_PIX_FMT_RGB565, + .colorspace = V4L2_COLORSPACE_SRGB, + .width = 320, + .height = 240, + }, + .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | + SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8, + .set_capture = ov772x_set_capture, +}; + +static struct platform_device migor_camera_device = { + .name = "soc_camera_platform", + .dev = { + .platform_data = &ov772x_info, + }, +}; + +static struct sh_mobile_ceu_info sh_mobile_ceu_info = { + .flags = SOCAM_MASTER | SOCAM_DATAWIDTH_8 | SOCAM_PCLK_SAMPLE_RISING \ + | SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_VSYNC_ACTIVE_HIGH, + .enable_camera = camera_power_on, + .disable_camera = camera_power_off, +}; + +static struct resource migor_ceu_resources[] = { + [0] = { + .name = "CEU", + .start = 0xfe910000, + .end = 0xfe91009f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 52, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device migor_ceu_device = { + .name = "sh_mobile_ceu", + .num_resources = ARRAY_SIZE(migor_ceu_resources), + .resource = migor_ceu_resources, + .dev = { + .platform_data = &sh_mobile_ceu_info, + }, +}; + static struct platform_device *migor_devices[] __initdata = { &smc91x_eth_device, &sh_keysc_device, + &migor_lcdc_device, + &migor_ceu_device, + &migor_camera_device, &migor_nor_flash_device, &migor_nand_flash_device, }; -static struct i2c_board_info __initdata migor_i2c_devices[] = { +static struct i2c_board_info migor_i2c_devices[] = { { I2C_BOARD_INFO("rs5c372b", 0x32), }, @@ -217,6 +446,12 @@ static struct i2c_board_info __initdata migor_i2c_devices[] = { static int __init migor_devices_setup(void) { + clk_always_enable("mstp214"); /* KEYSC */ + clk_always_enable("mstp200"); /* LCDC */ + clk_always_enable("mstp203"); /* CEU */ + + platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20); + i2c_register_board_info(0, migor_i2c_devices, ARRAY_SIZE(migor_i2c_devices)); @@ -235,20 +470,51 @@ static void __init migor_setup(char **cmdline_p) ctrl_outw(ctrl_inw(PORT_PSELA) & ~0x4100, PORT_PSELA); ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA); ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC); - ctrl_outl(ctrl_inl(MSTPCR2) & ~0x00004000, MSTPCR2); /* NAND Flash */ ctrl_outw(ctrl_inw(PORT_PXCR) & 0x0fff, PORT_PXCR); ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x00000600) | 0x00000200, BSC_CS6ABCR); - /* I2C */ - ctrl_outl(ctrl_inl(MSTPCR1) & ~0x00000200, MSTPCR1); - /* Touch Panel - Enable IRQ6 */ ctrl_outw(ctrl_inw(PORT_PZCR) & ~0xc, PORT_PZCR); ctrl_outw((ctrl_inw(PORT_PSELA) | 0x8000), PORT_PSELA); ctrl_outw((ctrl_inw(PORT_HIZCRC) & ~0x4000), PORT_HIZCRC); + +#ifdef CONFIG_SH_MIGOR_RTA_WVGA + /* LCDC - WVGA - Enable RGB Interface signals */ + ctrl_outw(ctrl_inw(PORT_PACR) & ~0x0003, PORT_PACR); + ctrl_outw(0x0000, PORT_PHCR); + ctrl_outw(0x0000, PORT_PLCR); + ctrl_outw(0x0000, PORT_PMCR); + ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x000f, PORT_PRCR); + ctrl_outw((ctrl_inw(PORT_PSELD) & ~0x000d) | 0x0400, PORT_PSELD); + ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0100, PORT_MSELCRB); + ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01e0, PORT_HIZCRA); +#endif +#ifdef CONFIG_SH_MIGOR_QVGA + /* LCDC - QVGA - Enable SYS Interface signals */ + ctrl_outw(ctrl_inw(PORT_PACR) & ~0x0003, PORT_PACR); + ctrl_outw((ctrl_inw(PORT_PHCR) & ~0xcfff) | 0x0010, PORT_PHCR); + ctrl_outw(0x0000, PORT_PLCR); + ctrl_outw(0x0000, PORT_PMCR); + ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x030f, PORT_PRCR); + ctrl_outw((ctrl_inw(PORT_PSELD) & ~0x0001) | 0x0420, PORT_PSELD); + ctrl_outw(ctrl_inw(PORT_MSELCRB) | 0x0100, PORT_MSELCRB); + ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01e0, PORT_HIZCRA); +#endif + + /* CEU */ + ctrl_outw((ctrl_inw(PORT_PTCR) & ~0x03c3) | 0x0051, PORT_PTCR); + ctrl_outw(ctrl_inw(PORT_PUCR) & ~0x03ff, PORT_PUCR); + ctrl_outw(ctrl_inw(PORT_PVCR) & ~0x03ff, PORT_PVCR); + ctrl_outw(ctrl_inw(PORT_PWCR) & ~0x3c00, PORT_PWCR); + ctrl_outw(ctrl_inw(PORT_PSELC) | 0x0001, PORT_PSELC); + ctrl_outw(ctrl_inw(PORT_PSELD) & ~0x2000, PORT_PSELD); + ctrl_outw(ctrl_inw(PORT_PSELE) | 0x000f, PORT_PSELE); + ctrl_outw(ctrl_inw(PORT_MSELCRB) | 0x2200, PORT_MSELCRB); + ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x0a00, PORT_HIZCRA); + ctrl_outw(ctrl_inw(PORT_HIZCRB) & ~0x0003, PORT_HIZCRB); } static struct sh_machine_vector mv_migor __initmv = { diff --git a/arch/sh/boards/renesas/rsk7203/Makefile b/arch/sh/boards/renesas/rsk7203/Makefile new file mode 100644 index 000000000000..f663768429f0 --- /dev/null +++ b/arch/sh/boards/renesas/rsk7203/Makefile @@ -0,0 +1 @@ +obj-y := setup.o diff --git a/arch/sh/boards/renesas/rsk7203/setup.c b/arch/sh/boards/renesas/rsk7203/setup.c new file mode 100644 index 000000000000..0bbda04b03b9 --- /dev/null +++ b/arch/sh/boards/renesas/rsk7203/setup.c @@ -0,0 +1,126 @@ +/* + * Renesas Technology Europe RSK+ 7203 Support. + * + * Copyright (C) 2008 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/types.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/map.h> +#include <asm/machvec.h> +#include <asm/io.h> + +static struct resource smc911x_resources[] = { + [0] = { + .start = 0x24000000, + .end = 0x24000000 + 0x100, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 64, + .end = 64, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc911x_device = { + .name = "smc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smc911x_resources), + .resource = smc911x_resources, +}; + +static const char *probes[] = { "cmdlinepart", NULL }; + +static struct mtd_partition *parsed_partitions; + +static struct mtd_partition rsk7203_partitions[] = { + { + .name = "Bootloader", + .offset = 0x00000000, + .size = 0x00040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "Kernel", + .offset = MTDPART_OFS_NXTBLK, + .size = 0x001c0000, + }, { + .name = "Flash_FS", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct physmap_flash_data flash_data = { + .width = 2, +}; + +static struct resource flash_resource = { + .start = 0x20000000, + .end = 0x20400000, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device flash_device = { + .name = "physmap-flash", + .id = -1, + .resource = &flash_resource, + .num_resources = 1, + .dev = { + .platform_data = &flash_data, + }, +}; + +static struct mtd_info *flash_mtd; + +static struct map_info rsk7203_flash_map = { + .name = "RSK+ Flash", + .size = 0x400000, + .bankwidth = 2, +}; + +static void __init set_mtd_partitions(void) +{ + int nr_parts = 0; + + simple_map_init(&rsk7203_flash_map); + flash_mtd = do_map_probe("cfi_probe", &rsk7203_flash_map); + nr_parts = parse_mtd_partitions(flash_mtd, probes, + &parsed_partitions, 0); + /* If there is no partition table, used the hard coded table */ + if (nr_parts <= 0) { + flash_data.parts = rsk7203_partitions; + flash_data.nr_parts = ARRAY_SIZE(rsk7203_partitions); + } else { + flash_data.nr_parts = nr_parts; + flash_data.parts = parsed_partitions; + } +} + + +static struct platform_device *rsk7203_devices[] __initdata = { + &smc911x_device, + &flash_device, +}; + +static int __init rsk7203_devices_setup(void) +{ + set_mtd_partitions(); + return platform_add_devices(rsk7203_devices, + ARRAY_SIZE(rsk7203_devices)); +} +device_initcall(rsk7203_devices_setup); + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_rsk7203 __initmv = { + .mv_name = "RSK+7203", +}; diff --git a/arch/sh/boards/renesas/sh7763rdp/Makefile b/arch/sh/boards/renesas/sh7763rdp/Makefile new file mode 100644 index 000000000000..f6c0b55516d2 --- /dev/null +++ b/arch/sh/boards/renesas/sh7763rdp/Makefile @@ -0,0 +1 @@ +obj-y := setup.o irq.o diff --git a/arch/sh/boards/renesas/sh7763rdp/irq.c b/arch/sh/boards/renesas/sh7763rdp/irq.c new file mode 100644 index 000000000000..fd850bad2dec --- /dev/null +++ b/arch/sh/boards/renesas/sh7763rdp/irq.c @@ -0,0 +1,45 @@ +/* + * linux/arch/sh/boards/renesas/sh7763rdp/irq.c + * + * Renesas Solutions SH7763RDP Support. + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/irq.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/sh7763rdp.h> + +#define INTC_BASE (0xFFD00000) +#define INTC_INT2PRI7 (INTC_BASE+0x4001C) +#define INTC_INT2MSKCR (INTC_BASE+0x4003C) +#define INTC_INT2MSKCR1 (INTC_BASE+0x400D4) + +/* + * Initialize IRQ setting + */ +void __init init_sh7763rdp_IRQ(void) +{ + /* GPIO enabled */ + ctrl_outl(1 << 25, INTC_INT2MSKCR); + + /* enable GPIO interrupts */ + ctrl_outl((ctrl_inl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000, + INTC_INT2PRI7); + + /* USBH enabled */ + ctrl_outl(1 << 17, INTC_INT2MSKCR1); + + /* GETHER enabled */ + ctrl_outl(1 << 16, INTC_INT2MSKCR1); + + /* DMAC enabled */ + ctrl_outl(1 << 8, INTC_INT2MSKCR); +} diff --git a/arch/sh/boards/renesas/sh7763rdp/setup.c b/arch/sh/boards/renesas/sh7763rdp/setup.c new file mode 100644 index 000000000000..925f16af7121 --- /dev/null +++ b/arch/sh/boards/renesas/sh7763rdp/setup.c @@ -0,0 +1,128 @@ +/* + * linux/arch/sh/boards/renesas/sh7763rdp/setup.c + * + * Renesas Solutions sh7763rdp board + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/input.h> +#include <linux/mtd/physmap.h> +#include <asm/io.h> +#include <asm/sh7763rdp.h> + +/* NOR Flash */ +static struct mtd_partition sh7763rdp_nor_flash_partitions[] = { + { + .name = "U-Boot", + .offset = 0, + .size = (2 * 128 * 1024), + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, { + .name = "Linux-Kernel", + .offset = MTDPART_OFS_APPEND, + .size = (20 * 128 * 1024), + }, { + .name = "Root Filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data sh7763rdp_nor_flash_data = { + .width = 2, + .parts = sh7763rdp_nor_flash_partitions, + .nr_parts = ARRAY_SIZE(sh7763rdp_nor_flash_partitions), +}; + +static struct resource sh7763rdp_nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0, + .end = (64 * 1024 * 1024), + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device sh7763rdp_nor_flash_device = { + .name = "physmap-flash", + .resource = sh7763rdp_nor_flash_resources, + .num_resources = ARRAY_SIZE(sh7763rdp_nor_flash_resources), + .dev = { + .platform_data = &sh7763rdp_nor_flash_data, + }, +}; + +static struct platform_device *sh7763rdp_devices[] __initdata = { + &sh7763rdp_nor_flash_device, +}; + +static int __init sh7763rdp_devices_setup(void) +{ + return platform_add_devices(sh7763rdp_devices, + ARRAY_SIZE(sh7763rdp_devices)); +} +__initcall(sh7763rdp_devices_setup); + +static void __init sh7763rdp_setup(char **cmdline_p) +{ + /* Board version check */ + if (ctrl_inw(CPLD_BOARD_ID_ERV_REG) == 0xECB1) + printk(KERN_INFO "RTE Standard Configuration\n"); + else + printk(KERN_INFO "RTA Standard Configuration\n"); + + /* USB pin select bits (clear bit 5-2 to 0) */ + ctrl_outw((ctrl_inw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2); + /* USBH setup port I controls to other (clear bits 4-9 to 0) */ + ctrl_outw(ctrl_inw(PORT_PICR) & 0xFC0F, PORT_PICR); + + /* Select USB Host controller */ + ctrl_outw(0x00, USB_USBHSC); + + /* For LCD */ + /* set PTJ7-1, bits 15-2 of PJCR to 0 */ + ctrl_outw(ctrl_inw(PORT_PJCR) & 0x0003, PORT_PJCR); + /* set PTI5, bits 11-10 of PICR to 0 */ + ctrl_outw(ctrl_inw(PORT_PICR) & 0xF3FF, PORT_PICR); + ctrl_outw(0, PORT_PKCR); + ctrl_outw(0, PORT_PLCR); + /* set PSEL2 bits 14-8, 5-4, of PSEL2 to 0 */ + ctrl_outw((ctrl_inw(PORT_PSEL2) & 0x00C0), PORT_PSEL2); + /* set PSEL3 bits 14-12, 6-4, 2-0 of PSEL3 to 0 */ + ctrl_outw((ctrl_inw(PORT_PSEL3) & 0x0700), PORT_PSEL3); + + /* For HAC */ + /* bit3-0 0100:HAC & SSI1 enable */ + ctrl_outw((ctrl_inw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1); + /* bit14 1:SSI_HAC_CLK enable */ + ctrl_outw(ctrl_inw(PORT_PSEL4) | 0x4000, PORT_PSEL4); + + /* SH-Ether */ + ctrl_outw((ctrl_inw(PORT_PSEL1) & ~0xff00) | 0x2400, PORT_PSEL1); + ctrl_outw(0x0, PORT_PFCR); + ctrl_outw(0x0, PORT_PFCR); + ctrl_outw(0x0, PORT_PFCR); + + /* MMC */ + /*selects SCIF and MMC other functions */ + ctrl_outw(0x0001, PORT_PSEL0); + /* MMC clock operates */ + ctrl_outl(ctrl_inl(MSTPCR1) & ~0x8, MSTPCR1); + ctrl_outw(ctrl_inw(PORT_PACR) & ~0x3000, PORT_PACR); + ctrl_outw(ctrl_inw(PORT_PCCR) & ~0xCFC3, PORT_PCCR); +} + +static struct sh_machine_vector mv_sh7763rdp __initmv = { + .mv_name = "sh7763drp", + .mv_setup = sh7763rdp_setup, + .mv_nr_irqs = 112, + .mv_init_irq = init_sh7763rdp_IRQ, +}; diff --git a/arch/sh/boards/renesas/sh7785lcr/Makefile b/arch/sh/boards/renesas/sh7785lcr/Makefile new file mode 100644 index 000000000000..77037567633b --- /dev/null +++ b/arch/sh/boards/renesas/sh7785lcr/Makefile @@ -0,0 +1 @@ +obj-y := setup.o diff --git a/arch/sh/boards/renesas/sh7785lcr/setup.c b/arch/sh/boards/renesas/sh7785lcr/setup.c new file mode 100644 index 000000000000..b95d674ee704 --- /dev/null +++ b/arch/sh/boards/renesas/sh7785lcr/setup.c @@ -0,0 +1,302 @@ +/* + * Renesas Technology Corp. R0P7785LC0011RL Support. + * + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/sm501.h> +#include <linux/sm501-regs.h> +#include <linux/fb.h> +#include <linux/mtd/physmap.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/i2c-pca-platform.h> +#include <linux/i2c-algo-pca.h> +#include <asm/heartbeat.h> +#include <asm/sh7785lcr.h> + +/* + * NOTE: This board has 2 physical memory maps. + * Please look at include/asm-sh/sh7785lcr.h or hardware manual. + */ +static struct resource heartbeat_resources[] = { + [0] = { + .start = PLD_LEDCR, + .end = PLD_LEDCR, + .flags = IORESOURCE_MEM, + }, +}; + +static struct heartbeat_data heartbeat_data = { + .regsize = 8, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 4 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 4, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = NOR_FLASH_ADDR, + .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + +static struct resource r8a66597_usb_host_resources[] = { + [0] = { + .name = "r8a66597_hcd", + .start = R8A66597_ADDR, + .end = R8A66597_ADDR + R8A66597_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "r8a66597_hcd", + .start = 2, + .end = 2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device r8a66597_usb_host_device = { + .name = "r8a66597_hcd", + .id = -1, + .dev = { + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), + .resource = r8a66597_usb_host_resources, +}; + +static struct resource sm501_resources[] = { + [0] = { + .start = SM107_MEM_ADDR, + .end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = SM107_REG_ADDR, + .end = SM107_REG_ADDR + SM107_REG_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = 10, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fb_videomode sm501_default_mode_crt = { + .pixclock = 35714, /* 28MHz */ + .xres = 640, + .yres = 480, + .left_margin = 105, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 39, + .vsync_len = 2, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +}; + +static struct fb_videomode sm501_default_mode_pnl = { + .pixclock = 40000, /* 25MHz */ + .xres = 640, + .yres = 480, + .left_margin = 2, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 39, + .vsync_len = 2, + .sync = 0, +}; + +static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = { + .def_bpp = 16, + .def_mode = &sm501_default_mode_pnl, + .flags = SM501FB_FLAG_USE_INIT_MODE | + SM501FB_FLAG_USE_HWCURSOR | + SM501FB_FLAG_USE_HWACCEL | + SM501FB_FLAG_DISABLE_AT_EXIT | + SM501FB_FLAG_PANEL_NO_VBIASEN, +}; + +static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = { + .def_bpp = 16, + .def_mode = &sm501_default_mode_crt, + .flags = SM501FB_FLAG_USE_INIT_MODE | + SM501FB_FLAG_USE_HWCURSOR | + SM501FB_FLAG_USE_HWACCEL | + SM501FB_FLAG_DISABLE_AT_EXIT, +}; + +static struct sm501_platdata_fb sm501_fb_pdata = { + .fb_route = SM501_FB_OWN, + .fb_crt = &sm501_pdata_fbsub_crt, + .fb_pnl = &sm501_pdata_fbsub_pnl, +}; + +static struct sm501_initdata sm501_initdata = { + .gpio_high = { + .set = 0x00001fe0, + .mask = 0x0, + }, + .devices = 0, + .mclk = 84 * 1000000, + .m1xclk = 112 * 1000000, +}; + +static struct sm501_platdata sm501_platform_data = { + .init = &sm501_initdata, + .fb = &sm501_fb_pdata, +}; + +static struct platform_device sm501_device = { + .name = "sm501", + .id = -1, + .dev = { + .platform_data = &sm501_platform_data, + }, + .num_resources = ARRAY_SIZE(sm501_resources), + .resource = sm501_resources, +}; + +static struct resource i2c_resources[] = { + [0] = { + .start = PCA9564_ADDR, + .end = PCA9564_ADDR + PCA9564_SIZE - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, + }, + [1] = { + .start = 12, + .end = 12, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct i2c_pca9564_pf_platform_data i2c_platform_data = { + .gpio = 0, + .i2c_clock_speed = I2C_PCA_CON_330kHz, + .timeout = 100, +}; + +static struct platform_device i2c_device = { + .name = "i2c-pca-platform", + .id = -1, + .dev = { + .platform_data = &i2c_platform_data, + }, + .num_resources = ARRAY_SIZE(i2c_resources), + .resource = i2c_resources, +}; + +static struct platform_device *sh7785lcr_devices[] __initdata = { + &heartbeat_device, + &nor_flash_device, + &r8a66597_usb_host_device, + &sm501_device, + &i2c_device, +}; + +static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = { + { + I2C_BOARD_INFO("r2025sd", 0x32), + }, +}; + +static int __init sh7785lcr_devices_setup(void) +{ + i2c_register_board_info(0, sh7785lcr_i2c_devices, + ARRAY_SIZE(sh7785lcr_i2c_devices)); + + return platform_add_devices(sh7785lcr_devices, + ARRAY_SIZE(sh7785lcr_devices)); +} +__initcall(sh7785lcr_devices_setup); + +/* Initialize IRQ setting */ +void __init init_sh7785lcr_IRQ(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ7654); + plat_irq_setup_pins(IRQ_MODE_IRQ3210); +} + +static void sh7785lcr_power_off(void) +{ + ctrl_outb(0x01, P2SEGADDR(PLD_POFCR)); +} + +/* Initialize the board */ +static void __init sh7785lcr_setup(char **cmdline_p) +{ + void __iomem *sm501_reg; + + printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n"); + + pm_power_off = sh7785lcr_power_off; + + /* sm501 DRAM configuration */ + sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL; + writel(0x000307c2, sm501_reg); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_sh7785lcr __initmv = { + .mv_name = "SH7785LCR", + .mv_setup = sh7785lcr_setup, + .mv_init_irq = init_sh7785lcr_IRQ, +}; + |
