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-rw-r--r--arch/powerpc/sysdev/fsl_soc.c26
-rw-r--r--arch/powerpc/sysdev/mpic.c59
2 files changed, 81 insertions, 4 deletions
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 01b884b25696..26ecb96f9731 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -223,6 +223,8 @@ static int gfar_mdio_of_init_one(struct device_node *np)
if (ret)
return ret;
+ /* The gianfar device will try to use the same ID created below to find
+ * this bus, to coordinate register access (since they share). */
mdio_dev = platform_device_register_simple("fsl-gianfar_mdio",
res.start&0xfffff, &res, 1);
if (IS_ERR(mdio_dev))
@@ -394,6 +396,30 @@ static int __init gfar_of_init(void)
of_node_put(mdio);
}
+ /* Get MDIO bus controlled by this eTSEC, if any. Normally only
+ * eTSEC 1 will control an MDIO bus, not necessarily the same
+ * bus that its PHY is on ('mdio' above), so we can't just use
+ * that. What we do is look for a gianfar mdio device that has
+ * overlapping registers with this device. That's really the
+ * whole point, to find the device sharing our registers to
+ * coordinate access with it.
+ */
+ for_each_compatible_node(mdio, NULL, "fsl,gianfar-mdio") {
+ if (of_address_to_resource(mdio, 0, &res))
+ continue;
+
+ if (res.start >= r[0].start && res.end <= r[0].end) {
+ /* Get the ID the mdio bus platform device was
+ * registered with. gfar_data.bus_id is
+ * different because it's for finding a PHY,
+ * while this is for finding a MII bus.
+ */
+ gfar_data.mdio_bus = res.start&0xfffff;
+ of_node_put(mdio);
+ break;
+ }
+ }
+
ret =
platform_device_add_data(gfar_dev, &gfar_data,
sizeof(struct
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 8e3478c995ef..f6299cca7814 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -563,6 +563,51 @@ static void __init mpic_scan_ht_pics(struct mpic *mpic)
#endif /* CONFIG_MPIC_U3_HT_IRQS */
+#ifdef CONFIG_SMP
+static int irq_choose_cpu(unsigned int virt_irq)
+{
+ cpumask_t mask = irq_desc[virt_irq].affinity;
+ int cpuid;
+
+ if (cpus_equal(mask, CPU_MASK_ALL)) {
+ static int irq_rover;
+ static DEFINE_SPINLOCK(irq_rover_lock);
+ unsigned long flags;
+
+ /* Round-robin distribution... */
+ do_round_robin:
+ spin_lock_irqsave(&irq_rover_lock, flags);
+
+ while (!cpu_online(irq_rover)) {
+ if (++irq_rover >= NR_CPUS)
+ irq_rover = 0;
+ }
+ cpuid = irq_rover;
+ do {
+ if (++irq_rover >= NR_CPUS)
+ irq_rover = 0;
+ } while (!cpu_online(irq_rover));
+
+ spin_unlock_irqrestore(&irq_rover_lock, flags);
+ } else {
+ cpumask_t tmp;
+
+ cpus_and(tmp, cpu_online_map, mask);
+
+ if (cpus_empty(tmp))
+ goto do_round_robin;
+
+ cpuid = first_cpu(tmp);
+ }
+
+ return cpuid;
+}
+#else
+static int irq_choose_cpu(unsigned int virt_irq)
+{
+ return hard_smp_processor_id();
+}
+#endif
#define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
@@ -777,12 +822,18 @@ void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
struct mpic *mpic = mpic_from_irq(irq);
unsigned int src = mpic_irq_to_hw(irq);
- cpumask_t tmp;
+ if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
+ int cpuid = irq_choose_cpu(irq);
- cpus_and(tmp, cpumask, cpu_online_map);
+ mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
+ } else {
+ cpumask_t tmp;
- mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
- mpic_physmask(cpus_addr(tmp)[0]));
+ cpus_and(tmp, cpumask, cpu_online_map);
+
+ mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
+ mpic_physmask(cpus_addr(tmp)[0]));
+ }
}
static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
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