diff options
Diffstat (limited to 'arch/mips/momentum')
| -rw-r--r-- | arch/mips/momentum/jaguar_atx/prom.c | 2 | ||||
| -rw-r--r-- | arch/mips/momentum/jaguar_atx/reset.c | 2 | ||||
| -rw-r--r-- | arch/mips/momentum/jaguar_atx/setup.c | 7 | ||||
| -rw-r--r-- | arch/mips/momentum/ocelot_3/reset.c | 2 | ||||
| -rw-r--r-- | arch/mips/momentum/ocelot_c/irq.c | 2 | ||||
| -rw-r--r-- | arch/mips/momentum/ocelot_c/prom.c | 2 | ||||
| -rw-r--r-- | arch/mips/momentum/ocelot_c/reset.c | 2 | ||||
| -rw-r--r-- | arch/mips/momentum/ocelot_c/setup.c | 27 |
8 files changed, 24 insertions, 22 deletions
diff --git a/arch/mips/momentum/jaguar_atx/prom.c b/arch/mips/momentum/jaguar_atx/prom.c index aae7a802767a..1cadaa92946a 100644 --- a/arch/mips/momentum/jaguar_atx/prom.c +++ b/arch/mips/momentum/jaguar_atx/prom.c @@ -21,10 +21,10 @@ #include <linux/mm.h> #include <linux/sched.h> #include <linux/bootmem.h> +#include <linux/mv643xx.h> #include <asm/addrspace.h> #include <asm/bootinfo.h> -#include <asm/mv64340.h> #include <asm/pmon.h> #include "jaguar_atx_fpga.h" diff --git a/arch/mips/momentum/jaguar_atx/reset.c b/arch/mips/momentum/jaguar_atx/reset.c index c4236b1e59fa..ce9fb2e3d952 100644 --- a/arch/mips/momentum/jaguar_atx/reset.c +++ b/arch/mips/momentum/jaguar_atx/reset.c @@ -32,7 +32,7 @@ void momenco_jaguar_restart(char *command) #else void *nvram = (void*) 0xfc807000; #endif - /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ + /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ writeb(0x84, nvram + 0xff7); /* wait for the watchdog to go off */ diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c index 301d67226d72..3784c898db1a 100644 --- a/arch/mips/momentum/jaguar_atx/setup.c +++ b/arch/mips/momentum/jaguar_atx/setup.c @@ -2,7 +2,7 @@ * BRIEF MODULE DESCRIPTION * Momentum Computer Jaguar-ATX board dependent boot routines * - * Copyright (C) 1996, 1997, 2001, 2004 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 1996, 1997, 2001, 04, 06 Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2000 RidgeRun, Inc. * Copyright (C) 2001 Red Hat, Inc. * Copyright (C) 2002 Momentum Computer @@ -55,6 +55,8 @@ #include <linux/interrupt.h> #include <linux/timex.h> #include <linux/vmalloc.h> +#include <linux/mv643xx.h> + #include <asm/time.h> #include <asm/bootinfo.h> #include <asm/page.h> @@ -64,7 +66,6 @@ #include <asm/ptrace.h> #include <asm/reboot.h> #include <asm/tlbflush.h> -#include <asm/mv64340.h> #include "jaguar_atx_fpga.h" @@ -460,7 +461,7 @@ void __init plat_setup(void) unsigned int tbControl; tbControl = 0 << 26 | /* post trigger delay 0 */ - 0x2 << 16 | /* sequential trace mode */ + 0x2 << 16 | /* sequential trace mode */ // 0x0 << 16 | /* non-sequential trace mode */ // 0xf << 4 | /* watchpoints disabled */ 2 << 2 | /* armed */ diff --git a/arch/mips/momentum/ocelot_3/reset.c b/arch/mips/momentum/ocelot_3/reset.c index 72b4423c0864..9d86d2468376 100644 --- a/arch/mips/momentum/ocelot_3/reset.c +++ b/arch/mips/momentum/ocelot_3/reset.c @@ -34,7 +34,7 @@ void momenco_ocelot_restart(char *command) /* base address of timekeeper portion of part */ void *nvram = (void *) 0xfc807000L; - /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ + /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ writeb(0x84, nvram + 0xff7); /* wait for the watchdog to go off */ diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c index 300fe8e4fbe8..a5764bc20e36 100644 --- a/arch/mips/momentum/ocelot_c/irq.c +++ b/arch/mips/momentum/ocelot_c/irq.c @@ -41,11 +41,11 @@ #include <linux/slab.h> #include <linux/random.h> #include <linux/bitops.h> +#include <linux/mv643xx.h> #include <asm/bootinfo.h> #include <asm/io.h> #include <asm/irq_cpu.h> #include <asm/mipsregs.h> -#include <asm/mv64340.h> #include <asm/system.h> extern asmlinkage void ocelot_handle_int(void); diff --git a/arch/mips/momentum/ocelot_c/prom.c b/arch/mips/momentum/ocelot_c/prom.c index 5b6809724b15..e92364482c7b 100644 --- a/arch/mips/momentum/ocelot_c/prom.c +++ b/arch/mips/momentum/ocelot_c/prom.c @@ -19,10 +19,10 @@ #include <linux/mm.h> #include <linux/sched.h> #include <linux/bootmem.h> +#include <linux/mv643xx.h> #include <asm/addrspace.h> #include <asm/bootinfo.h> -#include <asm/mv64340.h> #include <asm/pmon.h> #include "ocelot_c_fpga.h" diff --git a/arch/mips/momentum/ocelot_c/reset.c b/arch/mips/momentum/ocelot_c/reset.c index 6a2489f3b9a0..9dcd154c7767 100644 --- a/arch/mips/momentum/ocelot_c/reset.c +++ b/arch/mips/momentum/ocelot_c/reset.c @@ -34,7 +34,7 @@ void momenco_ocelot_restart(char *command) 0xfc807000; #endif - /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ + /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ writeb(0x84, nvram + 0xff7); /* wait for the watchdog to go off */ diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c index 15998d8a9341..bd02e60d037a 100644 --- a/arch/mips/momentum/ocelot_c/setup.c +++ b/arch/mips/momentum/ocelot_c/setup.c @@ -54,6 +54,7 @@ #include <linux/pm.h> #include <linux/timex.h> #include <linux/vmalloc.h> +#include <linux/mv643xx.h> #include <asm/time.h> #include <asm/bootinfo.h> @@ -64,9 +65,9 @@ #include <asm/processor.h> #include <asm/ptrace.h> #include <asm/reboot.h> +#include <asm/marvell.h> #include <linux/bootmem.h> #include <linux/blkdev.h> -#include <asm/mv64340.h> #include "ocelot_c_fpga.h" unsigned long marvell_base; @@ -252,22 +253,22 @@ void __init plat_setup(void) /* shut down ethernet ports, just to be sure our memory doesn't get * corrupted by random ethernet traffic. */ - MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); - MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); + MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); + MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); + MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); + MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); do {} - while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); + while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); do {} - while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); + while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); do {} - while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); + while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); do {} - while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); - MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), - MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); - MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), - MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); + while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); + MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0), + MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); + MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1), + MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); /* Turn off the Bit-Error LED */ OCELOT_FPGA_WRITE(0x80, CLR); |
