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-rw-r--r--arch/m68k/include/asm/cacheflush_no.h4
-rw-r--r--arch/m68k/include/asm/m5407sim.h2
-rw-r--r--arch/m68k/include/asm/m54xxsim.h2
-rw-r--r--arch/m68k/include/asm/mcfcache.h2
4 files changed, 5 insertions, 5 deletions
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index e295923020d3..52b11ac9a30c 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -5,9 +5,7 @@
* (C) Copyright 2000-2004, Greg Ungerer <gerg@snapgear.com>
*/
#include <linux/mm.h>
-#if defined(CONFIG_M5407) || defined(CONFIG_M54xx)
-#include <asm/m54xxacr.h>
-#endif
+#include <asm/mcfsim.h>
#define flush_cache_all() __flush_cache_all()
#define flush_cache_mm(mm) do { } while (0)
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index ddfff88629fe..75f5c28a551d 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -17,6 +17,8 @@
#define CPU_NAME "COLDFIRE(m5407)"
#define CPU_INSTR_PER_JIFFY 3
+#include <asm/m54xxacr.h>
+
/*
* Define the 5407 SIM register set addresses.
*/
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index a08a7ae776b1..462ae5328441 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -8,6 +8,8 @@
#define CPU_NAME "COLDFIRE(m54xx)"
#define CPU_INSTR_PER_JIFFY 2
+#include <asm/m54xxacr.h>
+
#define MCFINT_VECBASE 64
/*
diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h
index 437686b62fea..2b3a6cfaaac0 100644
--- a/arch/m68k/include/asm/mcfcache.h
+++ b/arch/m68k/include/asm/mcfcache.h
@@ -109,8 +109,6 @@
#if defined(CONFIG_M5407) || defined(CONFIG_M54xx)
-#include <asm/m54xxacr.h>
-
.macro CACHE_ENABLE
/* invalidate whole cache */
movel #(CACR_DCINVA+CACR_BCINVA+CACR_ICINVA),%d0
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