diff options
Diffstat (limited to 'arch/m68k/include/asm')
| -rw-r--r-- | arch/m68k/include/asm/m5206sim.h | 13 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m5249sim.h | 6 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m5272sim.h | 5 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m5307sim.h | 6 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m5407sim.h | 5 |
5 files changed, 29 insertions, 6 deletions
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h index b50061aaf8f0..9c384e294af9 100644 --- a/arch/m68k/include/asm/m5206sim.h +++ b/arch/m68k/include/asm/m5206sim.h @@ -89,11 +89,18 @@ #define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */ /* + * Define system peripheral IRQ usage. + */ +#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ +#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ + +/* * Generic GPIO */ #define MCFGPIO_PIN_MAX 8 #define MCFGPIO_IRQ_VECBASE -1 #define MCFGPIO_IRQ_MAX -1 + /* * Some symbol defines for the Parallel Port Pin Assignment Register */ @@ -117,11 +124,5 @@ #define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */ #endif -/* - * Let the common interrupt handler code know that the ColdFire 5206* - * family of CPU's only has a 16bit sized IMR register. - */ -#define MCFSIM_IMR_IS_16BITS - /****************************************************************************/ #endif /* m5206sim_h */ diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index 36ed31bbf6cb..8d76a1930718 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -71,6 +71,12 @@ #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ /* + * Define system peripheral IRQ usage. + */ +#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ +#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ + +/* * General purpose IO registers (in MBAR2). */ #define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */ diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index 0665ba1a5d3c..469686ffc4af 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h @@ -73,6 +73,11 @@ #define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */ #define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */ +/* + * Define system peripheral IRQ usage. + */ +#define MCF_IRQ_TIMER 69 /* Timer0, Level 6 */ +#define MCF_IRQ_PROFILER 70 /* Timer1, Level 7 */ /* * Generic GPIO support diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 60946225699d..c6830e5b54ce 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -124,6 +124,7 @@ #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ + /* * Some symbol defines for the Parallel Port Pin Assignment Register */ @@ -139,6 +140,11 @@ #define IRQ3_LEVEL6 0x40 #define IRQ1_LEVEL2 0x20 +/* + * Define system peripheral IRQ usage. + */ +#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ +#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ /* * Define the Cache register flags. diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index 3c4bd5f08cde..c399abbf953c 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h @@ -111,6 +111,11 @@ #define IRQ3_LEVEL6 0x40 #define IRQ1_LEVEL2 0x20 +/* + * Define system peripheral IRQ usage. + */ +#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ +#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ /* * Define the Cache register flags. |
