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-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF544.h6
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF547.h6
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h6
3 files changed, 9 insertions, 9 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index f916c52a148a..e2771094de02 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -60,15 +60,15 @@
#define TWI1_REGBASE 0xffc02200
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index 72c343646b2a..3d131065f8e6 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -99,15 +99,15 @@
#define TWI1_REGBASE 0xffc02200
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 54143441af5e..01d52fade45e 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -105,15 +105,15 @@
#define TWI0_REGBASE 0xffc00700
#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */
+#define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */
#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */
#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTRL 0xffc00714 /* TWI Master Mode Control Register */
+#define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */
#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */
#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */
#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTRL 0xffc00728 /* TWI FIFO Control Register */
+#define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */
#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */
#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */
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