summaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-spear
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-spear')
-rw-r--r--arch/arm/plat-spear/clock.c5
-rw-r--r--arch/arm/plat-spear/include/plat/clock.h1
-rw-r--r--arch/arm/plat-spear/time.c16
3 files changed, 8 insertions, 14 deletions
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
index bdbd7ec9cb6b..6fa474cb398e 100644
--- a/arch/arm/plat-spear/clock.c
+++ b/arch/arm/plat-spear/clock.c
@@ -903,6 +903,11 @@ void recalc_root_clocks(void)
spin_unlock_irqrestore(&clocks_lock, flags);
}
+void __init clk_init(void)
+{
+ recalc_root_clocks();
+}
+
#ifdef CONFIG_DEBUG_FS
/*
* debugfs support to trace clock tree hierarchy and attributes
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
index fcc0d0ad4a1f..0062bafef12d 100644
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ b/arch/arm/plat-spear/include/plat/clock.h
@@ -224,6 +224,7 @@ struct clcd_rate_tbl {
};
/* platform specific clock functions */
+void __init clk_init(void);
void clk_register(struct clk_lookup *cl);
void recalc_root_clocks(void);
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index dbb6e4fff79d..0c77e4298675 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -70,19 +70,6 @@ static void clockevent_set_mode(enum clock_event_mode mode,
static int clockevent_next_event(unsigned long evt,
struct clock_event_device *clk_event_dev);
-static cycle_t clocksource_read_cycles(struct clocksource *cs)
-{
- return (cycle_t) readw(gpt_base + COUNT(CLKSRC));
-}
-
-static struct clocksource clksrc = {
- .name = "tmr1",
- .rating = 200, /* its a pretty decent clock */
- .read = clocksource_read_cycles,
- .mask = 0xFFFF, /* 16 bits */
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
static void spear_clocksource_init(void)
{
u32 tick_rate;
@@ -103,7 +90,8 @@ static void spear_clocksource_init(void)
writew(val, gpt_base + CR(CLKSRC));
/* register the clocksource */
- clocksource_register_hz(&clksrc, tick_rate);
+ clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,
+ 200, 16, clocksource_mmio_readw_up);
}
static struct clock_event_device clkevt = {
OpenPOWER on IntegriCloud