diff options
Diffstat (limited to 'arch/arm/plat-samsung/include')
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/clock-clksrc.h | 83 | ||||
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/clock.h | 152 | ||||
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/cpu-freq-core.h | 3 | ||||
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/pll.h | 323 | ||||
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/s5p-clock.h | 65 |
5 files changed, 0 insertions, 626 deletions
diff --git a/arch/arm/plat-samsung/include/plat/clock-clksrc.h b/arch/arm/plat-samsung/include/plat/clock-clksrc.h deleted file mode 100644 index 50a8ca7c3760..000000000000 --- a/arch/arm/plat-samsung/include/plat/clock-clksrc.h +++ /dev/null @@ -1,83 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/clock-clksrc.h - * - * Parts taken from arch/arm/plat-s3c64xx/clock.c - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Copyright 2009 Ben Dooks <ben-linux@fluff.org> - * Copyright 2009 Harald Welte - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/** - * struct clksrc_sources - list of sources for a given clock - * @sources: array of pointers to clocks - * @nr_sources: The size of @sources - */ -struct clksrc_sources { - unsigned int nr_sources; - struct clk **sources; -}; - -/** - * struct clksrc_reg - register definition for clock control bits - * @reg: pointer to the register in virtual memory. - * @shift: the shift in bits to where the bitfield is. - * @size: the size in bits of the bitfield. - * - * This specifies the size and position of the bits we are interested - * in within the register specified by @reg. - */ -struct clksrc_reg { - void __iomem *reg; - unsigned short shift; - unsigned short size; -}; - -/** - * struct clksrc_clk - class of clock for newer style samsung devices. - * @clk: the standard clock representation - * @sources: the sources for this clock - * @reg_src: the register definition for selecting the clock's source - * @reg_div: the register definition for the clock's output divisor - * - * This clock implements the features required by the newer SoCs where - * the standard clock block provides an input mux and a post-mux divisor - * to provide the periperhal's clock. - * - * The array of @sources provides the mapping of mux position to the - * clock, and @reg_src shows the code where to modify to change the mux - * position. The @reg_div defines how to change the divider settings on - * the output. - */ -struct clksrc_clk { - struct clk clk; - struct clksrc_sources *sources; - - struct clksrc_reg reg_src; - struct clksrc_reg reg_div; -}; - -/** - * s3c_set_clksrc() - setup the clock from the register settings - * @clk: The clock to setup. - * @announce: true to announce the setting to printk(). - * - * Setup the clock from the current register settings, for when the - * kernel boots or if it is resuming from a possibly unknown state. - */ -extern void s3c_set_clksrc(struct clksrc_clk *clk, bool announce); - -/** - * s3c_register_clksrc() register clocks from an array of clksrc clocks - * @srcs: The array of clocks to register - * @size: The size of the @srcs array. - * - * Initialise and register the array of clocks described by @srcs. - */ -extern void s3c_register_clksrc(struct clksrc_clk *srcs, int size); diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h deleted file mode 100644 index 63239f409807..000000000000 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ /dev/null @@ -1,152 +0,0 @@ -/* linux/arch/arm/plat-s3c/include/plat/clock.h - * - * Copyright (c) 2004-2005 Simtec Electronics - * http://www.simtec.co.uk/products/SWLINUX/ - * Written by Ben Dooks, <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_PLAT_CLOCK_H -#define __ASM_PLAT_CLOCK_H __FILE__ - -#include <linux/spinlock.h> -#include <linux/clkdev.h> - -struct clk; - -/** - * struct clk_ops - standard clock operations - * @set_rate: set the clock rate, see clk_set_rate(). - * @get_rate: get the clock rate, see clk_get_rate(). - * @round_rate: round a given clock rate, see clk_round_rate(). - * @set_parent: set the clock's parent, see clk_set_parent(). - * - * Group the common clock implementations together so that we - * don't have to keep setting the same fields again. We leave - * enable in struct clk. - * - * Adding an extra layer of indirection into the process should - * not be a problem as it is unlikely these operations are going - * to need to be called quickly. - */ -struct clk_ops { - int (*set_rate)(struct clk *c, unsigned long rate); - unsigned long (*get_rate)(struct clk *c); - unsigned long (*round_rate)(struct clk *c, unsigned long rate); - int (*set_parent)(struct clk *c, struct clk *parent); -}; - -struct clk { - struct list_head list; - struct module *owner; - struct clk *parent; - const char *name; - const char *devname; - int id; - int usage; - unsigned long rate; - unsigned long ctrlbit; - - struct clk_ops *ops; - int (*enable)(struct clk *, int enable); - struct clk_lookup lookup; -#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) - struct dentry *dent; /* For visible tree hierarchy */ -#endif -}; - -/* other clocks which may be registered by board support */ - -extern struct clk s3c24xx_dclk0; -extern struct clk s3c24xx_dclk1; -extern struct clk s3c24xx_clkout0; -extern struct clk s3c24xx_clkout1; -extern struct clk s3c24xx_uclk; - -extern struct clk clk_usb_bus; - -/* core clock support */ - -extern struct clk clk_f; -extern struct clk clk_h; -extern struct clk clk_p; -extern struct clk clk_mpll; -extern struct clk clk_upll; -extern struct clk clk_epll; -extern struct clk clk_xtal; -extern struct clk clk_ext; - -/* S3C2443/S3C2416 specific clocks */ -extern struct clksrc_clk clk_epllref; -extern struct clksrc_clk clk_esysclk; - -/* S3C24XX UART clocks */ -extern struct clk s3c24xx_clk_uart0; -extern struct clk s3c24xx_clk_uart1; -extern struct clk s3c24xx_clk_uart2; - -/* S3C64XX specific clocks */ -extern struct clk clk_h2; -extern struct clk clk_27m; -extern struct clk clk_48m; -extern struct clk clk_xusbxti; - -extern int clk_default_setrate(struct clk *clk, unsigned long rate); -extern struct clk_ops clk_ops_def_setrate; - -/* exports for arch/arm/mach-s3c2410 - * - * Please DO NOT use these outside of arch/arm/mach-s3c2410 -*/ - -extern spinlock_t clocks_lock; - -extern int s3c2410_clkcon_enable(struct clk *clk, int enable); - -extern int s3c24xx_register_clock(struct clk *clk); -extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); - -extern void s3c_register_clocks(struct clk *clk, int nr_clks); -extern void s3c_disable_clocks(struct clk *clkp, int nr_clks); - -extern int s3c24xx_register_baseclocks(unsigned long xtal); - -extern void s5p_register_clocks(unsigned long xtal_freq); - -extern void s3c24xx_setup_clocks(unsigned long fclk, - unsigned long hclk, - unsigned long pclk); - -extern void s3c2410_setup_clocks(void); -extern void s3c2412_setup_clocks(void); -extern void s3c244x_setup_clocks(void); - -/* S3C2410 specific clock functions */ - -extern int s3c2410_baseclk_add(void); - -/* S3C2443/S3C2416 specific clock functions */ - -typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base); - -extern void s3c2443_common_setup_clocks(pll_fn get_mpll); -extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, - unsigned int *divs, int nr_divs, - int divmask); - -extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable); -extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable); -extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable); - -/* S3C64XX specific functions and clocks */ - -extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable); - -/* Global watchdog clock used by arch_wtd_reset() callback */ - -extern struct clk *s3c2410_wdtclk; - -#endif /* __ASM_PLAT_CLOCK_H */ diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h index 72d4178ad23b..317c52303288 100644 --- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h +++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h @@ -140,7 +140,6 @@ struct s3c_cpufreq_config { * any frequency changes. This is really only need by devices like the * S3C2410 where there is no or limited divider between the PLL and the * ARMCLK. - * @resume_clocks: Update the clocks on resume. * @get_iotiming: Get the current IO timing data, mainly for use at start. * @set_iotiming: Update the IO timings from the cached copies calculated * from the @calc_iotiming entry when changing the frequency. @@ -169,8 +168,6 @@ struct s3c_cpufreq_info { /* driver routines */ - void (*resume_clocks)(void); - int (*get_iotiming)(struct s3c_cpufreq_config *cfg, struct s3c_iotimings *timings); diff --git a/arch/arm/plat-samsung/include/plat/pll.h b/arch/arm/plat-samsung/include/plat/pll.h deleted file mode 100644 index 357af7c1c664..000000000000 --- a/arch/arm/plat-samsung/include/plat/pll.h +++ /dev/null @@ -1,323 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/pll.h - * - * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Samsung PLL codes - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <asm/div64.h> - -#define S3C24XX_PLL_MDIV_MASK (0xFF) -#define S3C24XX_PLL_PDIV_MASK (0x1F) -#define S3C24XX_PLL_SDIV_MASK (0x3) -#define S3C24XX_PLL_MDIV_SHIFT (12) -#define S3C24XX_PLL_PDIV_SHIFT (4) -#define S3C24XX_PLL_SDIV_SHIFT (0) - -static inline unsigned int s3c24xx_get_pll(unsigned int pllval, - unsigned int baseclk) -{ - unsigned int mdiv, pdiv, sdiv; - uint64_t fvco; - - mdiv = (pllval >> S3C24XX_PLL_MDIV_SHIFT) & S3C24XX_PLL_MDIV_MASK; - pdiv = (pllval >> S3C24XX_PLL_PDIV_SHIFT) & S3C24XX_PLL_PDIV_MASK; - sdiv = (pllval >> S3C24XX_PLL_SDIV_SHIFT) & S3C24XX_PLL_SDIV_MASK; - - fvco = (uint64_t)baseclk * (mdiv + 8); - do_div(fvco, (pdiv + 2) << sdiv); - - return (unsigned int)fvco; -} - -#define S3C2416_PLL_MDIV_MASK (0x3FF) -#define S3C2416_PLL_PDIV_MASK (0x3F) -#define S3C2416_PLL_SDIV_MASK (0x7) -#define S3C2416_PLL_MDIV_SHIFT (14) -#define S3C2416_PLL_PDIV_SHIFT (5) -#define S3C2416_PLL_SDIV_SHIFT (0) - -static inline unsigned int s3c2416_get_pll(unsigned int pllval, - unsigned int baseclk) -{ - unsigned int mdiv, pdiv, sdiv; - uint64_t fvco; - - mdiv = (pllval >> S3C2416_PLL_MDIV_SHIFT) & S3C2416_PLL_MDIV_MASK; - pdiv = (pllval >> S3C2416_PLL_PDIV_SHIFT) & S3C2416_PLL_PDIV_MASK; - sdiv = (pllval >> S3C2416_PLL_SDIV_SHIFT) & S3C2416_PLL_SDIV_MASK; - - fvco = (uint64_t)baseclk * mdiv; - do_div(fvco, (pdiv << sdiv)); - - return (unsigned int)fvco; -} - -#define S3C6400_PLL_MDIV_MASK (0x3FF) -#define S3C6400_PLL_PDIV_MASK (0x3F) -#define S3C6400_PLL_SDIV_MASK (0x7) -#define S3C6400_PLL_MDIV_SHIFT (16) -#define S3C6400_PLL_PDIV_SHIFT (8) -#define S3C6400_PLL_SDIV_SHIFT (0) - -static inline unsigned long s3c6400_get_pll(unsigned long baseclk, - u32 pllcon) -{ - u32 mdiv, pdiv, sdiv; - u64 fvco = baseclk; - - mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK; - pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK; - sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK; - - fvco *= mdiv; - do_div(fvco, (pdiv << sdiv)); - - return (unsigned long)fvco; -} - -#define PLL6553X_MDIV_MASK (0x7F) -#define PLL6553X_PDIV_MASK (0x1F) -#define PLL6553X_SDIV_MASK (0x3) -#define PLL6553X_KDIV_MASK (0xFFFF) -#define PLL6553X_MDIV_SHIFT (16) -#define PLL6553X_PDIV_SHIFT (8) -#define PLL6553X_SDIV_SHIFT (0) - -static inline unsigned long s3c_get_pll6553x(unsigned long baseclk, - u32 pll_con0, u32 pll_con1) -{ - unsigned long result; - u32 mdiv, pdiv, sdiv, kdiv; - u64 tmp; - - mdiv = (pll_con0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK; - pdiv = (pll_con0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK; - sdiv = (pll_con0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK; - kdiv = pll_con1 & PLL6553X_KDIV_MASK; - - /* - * We need to multiple baseclk by mdiv (the integer part) and kdiv - * which is in 2^16ths, so shift mdiv up (does not overflow) and - * add kdiv before multiplying. The use of tmp is to avoid any - * overflows before shifting bac down into result when multipling - * by the mdiv and kdiv pair. - */ - - tmp = baseclk; - tmp *= (mdiv << 16) + kdiv; - do_div(tmp, (pdiv << sdiv)); - result = tmp >> 16; - - return result; -} - -#define PLL35XX_MDIV_MASK (0x3FF) -#define PLL35XX_PDIV_MASK (0x3F) -#define PLL35XX_SDIV_MASK (0x7) -#define PLL35XX_MDIV_SHIFT (16) -#define PLL35XX_PDIV_SHIFT (8) -#define PLL35XX_SDIV_SHIFT (0) - -static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con) -{ - u32 mdiv, pdiv, sdiv; - u64 fvco = baseclk; - - mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; - pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; - sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK; - - fvco *= mdiv; - do_div(fvco, (pdiv << sdiv)); - - return (unsigned long)fvco; -} - -#define PLL36XX_KDIV_MASK (0xFFFF) -#define PLL36XX_MDIV_MASK (0x1FF) -#define PLL36XX_PDIV_MASK (0x3F) -#define PLL36XX_SDIV_MASK (0x7) -#define PLL36XX_MDIV_SHIFT (16) -#define PLL36XX_PDIV_SHIFT (8) -#define PLL36XX_SDIV_SHIFT (0) - -static inline unsigned long s5p_get_pll36xx(unsigned long baseclk, - u32 pll_con0, u32 pll_con1) -{ - unsigned long result; - u32 mdiv, pdiv, sdiv, kdiv; - u64 tmp; - - mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; - pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; - sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK; - kdiv = pll_con1 & PLL36XX_KDIV_MASK; - - tmp = baseclk; - - tmp *= (mdiv << 16) + kdiv; - do_div(tmp, (pdiv << sdiv)); - result = tmp >> 16; - - return result; -} - -#define PLL45XX_MDIV_MASK (0x3FF) -#define PLL45XX_PDIV_MASK (0x3F) -#define PLL45XX_SDIV_MASK (0x7) -#define PLL45XX_MDIV_SHIFT (16) -#define PLL45XX_PDIV_SHIFT (8) -#define PLL45XX_SDIV_SHIFT (0) - -enum pll45xx_type_t { - pll_4500, - pll_4502, - pll_4508 -}; - -static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con, - enum pll45xx_type_t pll_type) -{ - u32 mdiv, pdiv, sdiv; - u64 fvco = baseclk; - - mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; - pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; - sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK; - - if (pll_type == pll_4508) - sdiv = sdiv - 1; - - fvco *= mdiv; - do_div(fvco, (pdiv << sdiv)); - - return (unsigned long)fvco; -} - -/* CON0 bit-fields */ -#define PLL46XX_MDIV_MASK (0x1FF) -#define PLL46XX_PDIV_MASK (0x3F) -#define PLL46XX_SDIV_MASK (0x7) -#define PLL46XX_LOCKED_SHIFT (29) -#define PLL46XX_MDIV_SHIFT (16) -#define PLL46XX_PDIV_SHIFT (8) -#define PLL46XX_SDIV_SHIFT (0) - -/* CON1 bit-fields */ -#define PLL46XX_MRR_MASK (0x1F) -#define PLL46XX_MFR_MASK (0x3F) -#define PLL46XX_KDIV_MASK (0xFFFF) -#define PLL4650C_KDIV_MASK (0xFFF) -#define PLL46XX_MRR_SHIFT (24) -#define PLL46XX_MFR_SHIFT (16) -#define PLL46XX_KDIV_SHIFT (0) - -enum pll46xx_type_t { - pll_4600, - pll_4650, - pll_4650c, -}; - -static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, - u32 pll_con0, u32 pll_con1, - enum pll46xx_type_t pll_type) -{ - unsigned long result; - u32 mdiv, pdiv, sdiv, kdiv; - u64 tmp; - - mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; - pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; - sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; - kdiv = pll_con1 & PLL46XX_KDIV_MASK; - - if (pll_type == pll_4650c) - kdiv = pll_con1 & PLL4650C_KDIV_MASK; - else - kdiv = pll_con1 & PLL46XX_KDIV_MASK; - - tmp = baseclk; - - if (pll_type == pll_4600) { - tmp *= (mdiv << 16) + kdiv; - do_div(tmp, (pdiv << sdiv)); - result = tmp >> 16; - } else { - tmp *= (mdiv << 10) + kdiv; - do_div(tmp, (pdiv << sdiv)); - result = tmp >> 10; - } - - return result; -} - -#define PLL90XX_MDIV_MASK (0xFF) -#define PLL90XX_PDIV_MASK (0x3F) -#define PLL90XX_SDIV_MASK (0x7) -#define PLL90XX_KDIV_MASK (0xffff) -#define PLL90XX_LOCKED_SHIFT (29) -#define PLL90XX_MDIV_SHIFT (16) -#define PLL90XX_PDIV_SHIFT (8) -#define PLL90XX_SDIV_SHIFT (0) -#define PLL90XX_KDIV_SHIFT (0) - -static inline unsigned long s5p_get_pll90xx(unsigned long baseclk, - u32 pll_con, u32 pll_conk) -{ - unsigned long result; - u32 mdiv, pdiv, sdiv, kdiv; - u64 tmp; - - mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK; - pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK; - sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK; - kdiv = pll_conk & PLL90XX_KDIV_MASK; - - /* - * We need to multiple baseclk by mdiv (the integer part) and kdiv - * which is in 2^16ths, so shift mdiv up (does not overflow) and - * add kdiv before multiplying. The use of tmp is to avoid any - * overflows before shifting bac down into result when multipling - * by the mdiv and kdiv pair. - */ - - tmp = baseclk; - tmp *= (mdiv << 16) + kdiv; - do_div(tmp, (pdiv << sdiv)); - result = tmp >> 16; - - return result; -} - -#define PLL65XX_MDIV_MASK (0x3FF) -#define PLL65XX_PDIV_MASK (0x3F) -#define PLL65XX_SDIV_MASK (0x7) -#define PLL65XX_MDIV_SHIFT (16) -#define PLL65XX_PDIV_SHIFT (8) -#define PLL65XX_SDIV_SHIFT (0) - -static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con) -{ - u32 mdiv, pdiv, sdiv; - u64 fvco = baseclk; - - mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK; - pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK; - sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK; - - fvco *= mdiv; - do_div(fvco, (pdiv << sdiv)); - - return (unsigned long)fvco; -} diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h deleted file mode 100644 index acacc4b88a39..000000000000 --- a/arch/arm/plat-samsung/include/plat/s5p-clock.h +++ /dev/null @@ -1,65 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/s5p-clock.h - * - * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Header file for s5p clock support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_PLAT_S5P_CLOCK_H -#define __ASM_PLAT_S5P_CLOCK_H __FILE__ - -#include <linux/clk.h> - -#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) - -#define clk_fin_apll clk_ext_xtal_mux -#define clk_fin_bpll clk_ext_xtal_mux -#define clk_fin_cpll clk_ext_xtal_mux -#define clk_fin_mpll clk_ext_xtal_mux -#define clk_fin_epll clk_ext_xtal_mux -#define clk_fin_dpll clk_ext_xtal_mux -#define clk_fin_vpll clk_ext_xtal_mux -#define clk_fin_hpll clk_ext_xtal_mux - -extern struct clk clk_ext_xtal_mux; -extern struct clk clk_xusbxti; -extern struct clk clk_48m; -extern struct clk s5p_clk_27m; -extern struct clk clk_fout_apll; -extern struct clk clk_fout_bpll; -extern struct clk clk_fout_bpll_div2; -extern struct clk clk_fout_cpll; -extern struct clk clk_fout_mpll; -extern struct clk clk_fout_mpll_div2; -extern struct clk clk_fout_epll; -extern struct clk clk_fout_dpll; -extern struct clk clk_fout_vpll; -extern struct clk clk_arm; -extern struct clk clk_vpll; - -extern struct clksrc_sources clk_src_apll; -extern struct clksrc_sources clk_src_bpll; -extern struct clksrc_sources clk_src_bpll_fout; -extern struct clksrc_sources clk_src_cpll; -extern struct clksrc_sources clk_src_mpll; -extern struct clksrc_sources clk_src_mpll_fout; -extern struct clksrc_sources clk_src_epll; -extern struct clksrc_sources clk_src_dpll; - -extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable); - -/* Common EPLL operations for S5P platform */ -extern int s5p_epll_enable(struct clk *clk, int enable); -extern unsigned long s5p_epll_get_rate(struct clk *clk); - -/* SPDIF clk operations common for S5PV210/C110 and Exynos4 */ -extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate); -extern unsigned long s5p_spdif_get_rate(struct clk *clk); - -extern struct clk_ops s5p_sclk_spdif_ops; -#endif /* __ASM_PLAT_S5P_CLOCK_H */ |
