diff options
Diffstat (limited to 'arch/arm/plat-s3c/include')
| -rw-r--r-- | arch/arm/plat-s3c/include/plat/adc.h | 10 | ||||
| -rw-r--r-- | arch/arm/plat-s3c/include/plat/clock.h | 1 | ||||
| -rw-r--r-- | arch/arm/plat-s3c/include/plat/cpu.h | 3 | ||||
| -rw-r--r-- | arch/arm/plat-s3c/include/plat/devs.h | 6 | ||||
| -rw-r--r-- | arch/arm/plat-s3c/include/plat/dma-core.h | 22 | ||||
| -rw-r--r-- | arch/arm/plat-s3c/include/plat/dma.h | 127 | ||||
| -rw-r--r-- | arch/arm/plat-s3c/include/plat/gpio-core.h | 30 | ||||
| -rw-r--r-- | arch/arm/plat-s3c/include/plat/pm.h | 15 | ||||
| -rw-r--r-- | arch/arm/plat-s3c/include/plat/regs-serial.h | 5 | ||||
| -rw-r--r-- | arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h | 50 | ||||
| -rw-r--r-- | arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h | 377 | ||||
| -rw-r--r-- | arch/arm/plat-s3c/include/plat/sdhci.h | 50 | ||||
| -rw-r--r-- | arch/arm/plat-s3c/include/plat/udc-hs.h | 29 | ||||
| -rw-r--r-- | arch/arm/plat-s3c/include/plat/watchdog-reset.h | 49 |
14 files changed, 764 insertions, 10 deletions
diff --git a/arch/arm/plat-s3c/include/plat/adc.h b/arch/arm/plat-s3c/include/plat/adc.h index 43df2a404b0b..d847bd476b6c 100644 --- a/arch/arm/plat-s3c/include/plat/adc.h +++ b/arch/arm/plat-s3c/include/plat/adc.h @@ -19,10 +19,12 @@ struct s3c_adc_client; extern int s3c_adc_start(struct s3c_adc_client *client, unsigned int channel, unsigned int nr_samples); -extern struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, - void (*select)(unsigned selected), - void (*conv)(unsigned d0, unsigned d1), - unsigned int is_ts); +extern struct s3c_adc_client * + s3c_adc_register(struct platform_device *pdev, + void (*select)(unsigned selected), + void (*conv)(unsigned d0, unsigned d1, + unsigned *samples_left), + unsigned int is_ts); extern void s3c_adc_release(struct s3c_adc_client *client); diff --git a/arch/arm/plat-s3c/include/plat/clock.h b/arch/arm/plat-s3c/include/plat/clock.h index a10622eed43a..d86af84b5b8c 100644 --- a/arch/arm/plat-s3c/include/plat/clock.h +++ b/arch/arm/plat-s3c/include/plat/clock.h @@ -50,6 +50,7 @@ extern struct clk clk_xtal; extern struct clk clk_ext; /* S3C64XX specific clocks */ +extern struct clk clk_h2; extern struct clk clk_27m; extern struct clk clk_48m; diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h index e62ae0fcfe56..be541cbba070 100644 --- a/arch/arm/plat-s3c/include/plat/cpu.h +++ b/arch/arm/plat-s3c/include/plat/cpu.h @@ -69,3 +69,6 @@ extern struct sysdev_class s3c2412_sysclass; extern struct sysdev_class s3c2440_sysclass; extern struct sysdev_class s3c2442_sysclass; extern struct sysdev_class s3c2443_sysclass; +extern struct sysdev_class s3c6410_sysclass; +extern struct sysdev_class s3c64xx_sysclass; + diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index 26f0cec3ac04..b5b9c4d46e9a 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h @@ -24,13 +24,16 @@ extern struct platform_device *s3c24xx_uart_src[]; extern struct platform_device s3c_device_timer[]; +extern struct platform_device s3c64xx_device_iis0; +extern struct platform_device s3c64xx_device_iis1; +extern struct platform_device s3c64xx_device_iisv4; + extern struct platform_device s3c_device_fb; extern struct platform_device s3c_device_usb; extern struct platform_device s3c_device_lcd; extern struct platform_device s3c_device_wdt; extern struct platform_device s3c_device_i2c0; extern struct platform_device s3c_device_i2c1; -extern struct platform_device s3c_device_iis; extern struct platform_device s3c_device_rtc; extern struct platform_device s3c_device_adc; extern struct platform_device s3c_device_sdi; @@ -45,6 +48,7 @@ extern struct platform_device s3c_device_spi1; extern struct platform_device s3c_device_nand; extern struct platform_device s3c_device_usbgadget; +extern struct platform_device s3c_device_usb_hsotg; /* s3c2440 specific devices */ diff --git a/arch/arm/plat-s3c/include/plat/dma-core.h b/arch/arm/plat-s3c/include/plat/dma-core.h new file mode 100644 index 000000000000..32ff2a92cb3c --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/dma-core.h @@ -0,0 +1,22 @@ +/* arch/arm/plat-s3c/include/plat/dma.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Samsung S3C DMA core support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel); + +extern struct s3c2410_dma_chan *s3c_dma_chan_map[]; + +/* the currently allocated channel information */ +extern struct s3c2410_dma_chan s3c2410_chans[]; + + diff --git a/arch/arm/plat-s3c/include/plat/dma.h b/arch/arm/plat-s3c/include/plat/dma.h new file mode 100644 index 000000000000..34dba98f08e1 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/dma.h @@ -0,0 +1,127 @@ +/* arch/arm/plat-s3c/include/plat/dma.h + * + * Copyright (C) 2003,2004,2006 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * Samsung S3C DMA support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +enum s3c2410_dma_buffresult { + S3C2410_RES_OK, + S3C2410_RES_ERR, + S3C2410_RES_ABORT +}; + +enum s3c2410_dmasrc { + S3C2410_DMASRC_HW, /* source is memory */ + S3C2410_DMASRC_MEM /* source is hardware */ +}; + +/* enum s3c2410_chan_op + * + * operation codes passed to the DMA code by the user, and also used + * to inform the current channel owner of any changes to the system state +*/ + +enum s3c2410_chan_op { + S3C2410_DMAOP_START, + S3C2410_DMAOP_STOP, + S3C2410_DMAOP_PAUSE, + S3C2410_DMAOP_RESUME, + S3C2410_DMAOP_FLUSH, + S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */ + S3C2410_DMAOP_STARTED, /* indicate channel started */ +}; + +struct s3c2410_dma_client { + char *name; +}; + +struct s3c2410_dma_chan; + +/* s3c2410_dma_cbfn_t + * + * buffer callback routine type +*/ + +typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *, + void *buf, int size, + enum s3c2410_dma_buffresult result); + +typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *, + enum s3c2410_chan_op ); + + + +/* s3c2410_dma_request + * + * request a dma channel exclusivley +*/ + +extern int s3c2410_dma_request(unsigned int channel, + struct s3c2410_dma_client *, void *dev); + + +/* s3c2410_dma_ctrl + * + * change the state of the dma channel +*/ + +extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op); + +/* s3c2410_dma_setflags + * + * set the channel's flags to a given state +*/ + +extern int s3c2410_dma_setflags(unsigned int channel, + unsigned int flags); + +/* s3c2410_dma_free + * + * free the dma channel (will also abort any outstanding operations) +*/ + +extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *); + +/* s3c2410_dma_enqueue + * + * place the given buffer onto the queue of operations for the channel. + * The buffer must be allocated from dma coherent memory, or the Dcache/WB + * drained before the buffer is given to the DMA system. +*/ + +extern int s3c2410_dma_enqueue(unsigned int channel, void *id, + dma_addr_t data, int size); + +/* s3c2410_dma_config + * + * configure the dma channel +*/ + +extern int s3c2410_dma_config(unsigned int channel, int xferunit); + +/* s3c2410_dma_devconfig + * + * configure the device we're talking to +*/ + +extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source, + unsigned long devaddr); + +/* s3c2410_dma_getposition + * + * get the position that the dma transfer is currently at +*/ + +extern int s3c2410_dma_getposition(unsigned int channel, + dma_addr_t *src, dma_addr_t *dest); + +extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn); +extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn); + + diff --git a/arch/arm/plat-s3c/include/plat/gpio-core.h b/arch/arm/plat-s3c/include/plat/gpio-core.h index 2fc60a580ac8..32af612767aa 100644 --- a/arch/arm/plat-s3c/include/plat/gpio-core.h +++ b/arch/arm/plat-s3c/include/plat/gpio-core.h @@ -20,6 +20,18 @@ * specific code. */ +struct s3c_gpio_chip; + +/** + * struct s3c_gpio_pm - power management (suspend/resume) information + * @save: Routine to save the state of the GPIO block + * @resume: Routine to resume the GPIO block. + */ +struct s3c_gpio_pm { + void (*save)(struct s3c_gpio_chip *chip); + void (*resume)(struct s3c_gpio_chip *chip); +}; + struct s3c_gpio_cfg; /** @@ -27,6 +39,7 @@ struct s3c_gpio_cfg; * @chip: The chip structure to be exported via gpiolib. * @base: The base pointer to the gpio configuration registers. * @config: special function and pull-resistor control information. + * @pm_save: Save information for suspend/resume support. * * This wrapper provides the necessary information for the Samsung * specific gpios being registered with gpiolib. @@ -34,7 +47,11 @@ struct s3c_gpio_cfg; struct s3c_gpio_chip { struct gpio_chip chip; struct s3c_gpio_cfg *config; + struct s3c_gpio_pm *pm; void __iomem *base; +#ifdef CONFIG_PM + u32 pm_save[4]; +#endif }; static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc) @@ -75,3 +92,16 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip) static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } #endif + +#ifdef CONFIG_PM +extern struct s3c_gpio_pm s3c_gpio_pm_1bit; +extern struct s3c_gpio_pm s3c_gpio_pm_2bit; +extern struct s3c_gpio_pm s3c_gpio_pm_4bit; +#define __gpio_pm(x) x +#else +#define s3c_gpio_pm_1bit NULL +#define s3c_gpio_pm_2bit NULL +#define s3c_gpio_pm_4bit NULL +#define __gpio_pm(x) NULL + +#endif /* CONFIG_PM */ diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h index 3779775133a9..7a797192fcf3 100644 --- a/arch/arm/plat-s3c/include/plat/pm.h +++ b/arch/arm/plat-s3c/include/plat/pm.h @@ -44,6 +44,8 @@ extern void (*pm_cpu_sleep)(void); extern unsigned long s3c_pm_flags; +extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */ + /* from sleep.S */ extern int s3c_cpu_save(unsigned long *saveblk); @@ -88,6 +90,7 @@ struct pm_uart_save { u32 ufcon; u32 umcon; u32 ubrdiv; + u32 udivslot; }; /* helper functions to save/restore lists of registers. */ @@ -124,6 +127,18 @@ extern void s3c_pm_dbg(const char *msg, ...); #define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt) #endif +#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK +/** + * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs + * @set: set bits for the state of the LEDs + * @clear: clear bits for the state of the LEDs. + */ +extern void s3c_pm_debug_smdkled(u32 set, u32 clear); + +#else +static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { } +#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */ + /* suspend memory checking */ #ifdef CONFIG_S3C2410_PM_CHECK diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h index 487d7d2a7e1d..66af75a5cdd1 100644 --- a/arch/arm/plat-s3c/include/plat/regs-serial.h +++ b/arch/arm/plat-s3c/include/plat/regs-serial.h @@ -189,6 +189,11 @@ #define S3C2443_DIVSLOT (0x2C) +/* S3C64XX interrupt registers. */ +#define S3C64XX_UINTP 0x30 +#define S3C64XX_UINTSP 0x34 +#define S3C64XX_UINTM 0x38 + #ifndef __ASSEMBLY__ /* struct s3c24xx_uart_clksrc diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h new file mode 100644 index 000000000000..36a85f5000c8 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h @@ -0,0 +1,50 @@ +/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C - USB2.0 Highspeed/OtG device PHY registers + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* Note, this is a seperate header file as some of the clock framework + * needs to touch this if the clk_48m is used as the USB OHCI or other + * peripheral source. +*/ + +#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H +#define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__ + +/* S3C64XX_PA_USB_HSPHY */ + +#define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY) + +#define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00) +#define SRC_PHYPWR_OTG_DISABLE (1 << 4) +#define SRC_PHYPWR_ANALOG_POWERDOWN (1 << 3) +#define SRC_PHYPWR_FORCE_SUSPEND (1 << 1) + +#define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04) +#define S3C_PHYCLK_MODE_USB11 (1 << 6) +#define S3C_PHYCLK_EXT_OSC (1 << 5) +#define S3C_PHYCLK_CLK_FORCE (1 << 4) +#define S3C_PHYCLK_ID_PULL (1 << 2) +#define S3C_PHYCLK_CLKSEL_MASK (0x3 << 0) +#define S3C_PHYCLK_CLKSEL_SHIFT (0) +#define S3C_PHYCLK_CLKSEL_48M (0x0 << 0) +#define S3C_PHYCLK_CLKSEL_12M (0x2 << 0) +#define S3C_PHYCLK_CLKSEL_24M (0x3 << 0) + +#define S3C_RSTCON S3C_HSOTG_PHYREG(0x08) +#define S3C_RSTCON_PHYCLK (1 << 2) +#define S3C_RSTCON_HCLK (1 << 2) +#define S3C_RSTCON_PHY (1 << 0) + +#define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20) + +#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */ diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h new file mode 100644 index 000000000000..8d18d9d4d148 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h @@ -0,0 +1,377 @@ +/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C - USB2.0 Highspeed/OtG device block registers + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H +#define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__ + +#define S3C_HSOTG_REG(x) (x) + +#define S3C_GOTGCTL S3C_HSOTG_REG(0x000) +#define S3C_GOTGCTL_BSESVLD (1 << 19) +#define S3C_GOTGCTL_ASESVLD (1 << 18) +#define S3C_GOTGCTL_DBNC_SHORT (1 << 17) +#define S3C_GOTGCTL_CONID_B (1 << 16) +#define S3C_GOTGCTL_DEVHNPEN (1 << 11) +#define S3C_GOTGCTL_HSSETHNPEN (1 << 10) +#define S3C_GOTGCTL_HNPREQ (1 << 9) +#define S3C_GOTGCTL_HSTNEGSCS (1 << 8) +#define S3C_GOTGCTL_SESREQ (1 << 1) +#define S3C_GOTGCTL_SESREQSCS (1 << 0) + +#define S3C_GOTGINT S3C_HSOTG_REG(0x004) +#define S3C_GOTGINT_DbnceDone (1 << 19) +#define S3C_GOTGINT_ADevTOUTChg (1 << 18) +#define S3C_GOTGINT_HstNegDet (1 << 17) +#define S3C_GOTGINT_HstnegSucStsChng (1 << 9) +#define S3C_GOTGINT_SesReqSucStsChng (1 << 8) +#define S3C_GOTGINT_SesEndDet (1 << 2) + +#define S3C_GAHBCFG S3C_HSOTG_REG(0x008) +#define S3C_GAHBCFG_PTxFEmpLvl (1 << 8) +#define S3C_GAHBCFG_NPTxFEmpLvl (1 << 7) +#define S3C_GAHBCFG_DMAEn (1 << 5) +#define S3C_GAHBCFG_HBstLen_MASK (0xf << 1) +#define S3C_GAHBCFG_HBstLen_SHIFT (1) +#define S3C_GAHBCFG_HBstLen_Single (0x0 << 1) +#define S3C_GAHBCFG_HBstLen_Incr (0x1 << 1) +#define S3C_GAHBCFG_HBstLen_Incr4 (0x3 << 1) +#define S3C_GAHBCFG_HBstLen_Incr8 (0x5 << 1) +#define S3C_GAHBCFG_HBstLen_Incr16 (0x7 << 1) +#define S3C_GAHBCFG_GlblIntrEn (1 << 0) + +#define S3C_GUSBCFG S3C_HSOTG_REG(0x00C) +#define S3C_GUSBCFG_PHYLPClkSel (1 << 15) +#define S3C_GUSBCFG_HNPCap (1 << 9) +#define S3C_GUSBCFG_SRPCap (1 << 8) +#define S3C_GUSBCFG_PHYIf16 (1 << 3) +#define S3C_GUSBCFG_TOutCal_MASK (0x7 << 0) +#define S3C_GUSBCFG_TOutCal_SHIFT (0) +#define S3C_GUSBCFG_TOutCal_LIMIT (0x7) +#define S3C_GUSBCFG_TOutCal(_x) ((_x) << 0) + +#define S3C_GRSTCTL S3C_HSOTG_REG(0x010) + +#define S3C_GRSTCTL_AHBIdle (1 << 31) +#define S3C_GRSTCTL_DMAReq (1 << 30) +#define S3C_GRSTCTL_TxFNum_MASK (0x1f << 6) +#define S3C_GRSTCTL_TxFNum_SHIFT (6) +#define S3C_GRSTCTL_TxFNum_LIMIT (0x1f) +#define S3C_GRSTCTL_TxFNum(_x) ((_x) << 6) +#define S3C_GRSTCTL_TxFFlsh (1 << 5) +#define S3C_GRSTCTL_RxFFlsh (1 << 4) +#define S3C_GRSTCTL_INTknQFlsh (1 << 3) +#define S3C_GRSTCTL_FrmCntrRst (1 << 2) +#define S3C_GRSTCTL_HSftRst (1 << 1) +#define S3C_GRSTCTL_CSftRst (1 << 0) + +#define S3C_GINTSTS S3C_HSOTG_REG(0x014) +#define S3C_GINTMSK S3C_HSOTG_REG(0x018) + +#define S3C_GINTSTS_WkUpInt (1 << 31) +#define S3C_GINTSTS_SessReqInt (1 << 30) +#define S3C_GINTSTS_DisconnInt (1 << 29) +#define S3C_GINTSTS_ConIDStsChng (1 << 28) +#define S3C_GINTSTS_PTxFEmp (1 << 26) +#define S3C_GINTSTS_HChInt (1 << 25) +#define S3C_GINTSTS_PrtInt (1 << 24) +#define S3C_GINTSTS_FetSusp (1 << 22) +#define S3C_GINTSTS_incompIP (1 << 21) +#define S3C_GINTSTS_IncomplSOIN (1 << 20) +#define S3C_GINTSTS_OEPInt (1 << 19) +#define S3C_GINTSTS_IEPInt (1 << 18) +#define S3C_GINTSTS_EPMis (1 << 17) +#define S3C_GINTSTS_EOPF (1 << 15) +#define S3C_GINTSTS_ISOutDrop (1 << 14) +#define S3C_GINTSTS_EnumDone (1 << 13) +#define S3C_GINTSTS_USBRst (1 << 12) +#define S3C_GINTSTS_USBSusp (1 << 11) +#define S3C_GINTSTS_ErlySusp (1 << 10) +#define S3C_GINTSTS_GOUTNakEff (1 << 7) +#define S3C_GINTSTS_GINNakEff (1 << 6) +#define S3C_GINTSTS_NPTxFEmp (1 << 5) +#define S3C_GINTSTS_RxFLvl (1 << 4) +#define S3C_GINTSTS_SOF (1 << 3) +#define S3C_GINTSTS_OTGInt (1 << 2) +#define S3C_GINTSTS_ModeMis (1 << 1) +#define S3C_GINTSTS_CurMod_Host (1 << 0) + +#define S3C_GRXSTSR S3C_HSOTG_REG(0x01C) +#define S3C_GRXSTSP S3C_HSOTG_REG(0x020) + +#define S3C_GRXSTS_FN_MASK (0x7f << 25) +#define S3C_GRXSTS_FN_SHIFT (25) + +#define S3C_GRXSTS_PktSts_MASK (0xf << 17) +#define S3C_GRXSTS_PktSts_SHIFT (17) +#define S3C_GRXSTS_PktSts_GlobalOutNAK (0x1 << 17) +#define S3C_GRXSTS_PktSts_OutRX (0x2 << 17) +#define S3C_GRXSTS_PktSts_OutDone (0x3 << 17) +#define S3C_GRXSTS_PktSts_SetupDone (0x4 << 17) +#define S3C_GRXSTS_PktSts_SetupRX (0x6 << 17) + +#define S3C_GRXSTS_DPID_MASK (0x3 << 15) +#define S3C_GRXSTS_DPID_SHIFT (15) +#define S3C_GRXSTS_ByteCnt_MASK (0x7ff << 4) +#define S3C_GRXSTS_ByteCnt_SHIFT (4) +#define S3C_GRXSTS_EPNum_MASK (0xf << 0) +#define S3C_GRXSTS_EPNum_SHIFT (0) + +#define S3C_GRXFSIZ S3C_HSOTG_REG(0x024) + +#define S3C_GNPTXFSIZ S3C_HSOTG_REG(0x028) + +#define S3C_GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16) +#define S3C_GNPTXFSIZ_NPTxFDep_SHIFT (16) +#define S3C_GNPTXFSIZ_NPTxFDep_LIMIT (0xffff) +#define S3C_GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16) +#define S3C_GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0) +#define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT (0) +#define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff) +#define S3C_GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0) + +#define S3C_GNPTXSTS S3C_HSOTG_REG(0x02C) + +#define S3C_GNPTXSTS_NPtxQTop_MASK (0x7f << 24) +#define S3C_GNPTXSTS_NPtxQTop_SHIFT (24) + +#define S3C_GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16) +#define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT (16) +#define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff) + +#define S3C_GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0) +#define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT (0) +#define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff) + + +#define S3C_HPTXFSIZ S3C_HSOTG_REG(0x100) + +#define S3C_DPTXFSIZn(_a) S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4)) + +#define S3C_DPTXFSIZn_DPTxFSize_MASK (0xffff << 16) +#define S3C_DPTXFSIZn_DPTxFSize_SHIFT (16) +#define S3C_DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff) +#define S3C_DPTXFSIZn_DPTxFSize_LIMIT (0xffff) +#define S3C_DPTXFSIZn_DPTxFSize(_x) ((_x) << 16) + +#define S3C_DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0) +#define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT (0) + +/* Device mode registers */ +#define S3C_DCFG S3C_HSOTG_REG(0x800) + +#define S3C_DCFG_EPMisCnt_MASK (0x1f << 18) +#define S3C_DCFG_EPMisCnt_SHIFT (18) +#define S3C_DCFG_EPMisCnt_LIMIT (0x1f) +#define S3C_DCFG_EPMisCnt(_x) ((_x) << 18) + +#define S3C_DCFG_PerFrInt_MASK (0x3 << 11) +#define S3C_DCFG_PerFrInt_SHIFT (11) +#define S3C_DCFG_PerFrInt_LIMIT (0x3) +#define S3C_DCFG_PerFrInt(_x) ((_x) << 11) + +#define S3C_DCFG_DevAddr_MASK (0x7f << 4) +#define S3C_DCFG_DevAddr_SHIFT (4) +#define S3C_DCFG_DevAddr_LIMIT (0x7f) +#define S3C_DCFG_DevAddr(_x) ((_x) << 4) + +#define S3C_DCFG_NZStsOUTHShk (1 << 2) + +#define S3C_DCFG_DevSpd_MASK (0x3 << 0) +#define S3C_DCFG_DevSpd_SHIFT (0) +#define S3C_DCFG_DevSpd_HS (0x0 << 0) +#define S3C_DCFG_DevSpd_FS (0x1 << 0) +#define S3C_DCFG_DevSpd_LS (0x2 << 0) +#define S3C_DCFG_DevSpd_FS48 (0x3 << 0) + +#define S3C_DCTL S3C_HSOTG_REG(0x804) + +#define S3C_DCTL_PWROnPrgDone (1 << 11) +#define S3C_DCTL_CGOUTNak (1 << 10) +#define S3C_DCTL_SGOUTNak (1 << 9) +#define S3C_DCTL_CGNPInNAK (1 << 8) +#define S3C_DCTL_SGNPInNAK (1 << 7) +#define S3C_DCTL_TstCtl_MASK (0x7 << 4) +#define S3C_DCTL_TstCtl_SHIFT (4) +#define S3C_DCTL_GOUTNakSts (1 << 3) +#define S3C_DCTL_GNPINNakSts (1 << 2) +#define S3C_DCTL_SftDiscon (1 << 1) +#define S3C_DCTL_RmtWkUpSig (1 << 0) + +#define S3C_DSTS S3C_HSOTG_REG(0x808) + +#define S3C_DSTS_SOFFN_MASK (0x3fff << 8) +#define S3C_DSTS_SOFFN_SHIFT (8) +#define S3C_DSTS_SOFFN_LIMIT (0x3fff) +#define S3C_DSTS_SOFFN(_x) ((_x) << 8) +#define S3C_DSTS_ErraticErr (1 << 3) +#define S3C_DSTS_EnumSpd_MASK (0x3 << 1) +#define S3C_DSTS_EnumSpd_SHIFT (1) +#define S3C_DSTS_EnumSpd_HS (0x0 << 1) +#define S3C_DSTS_EnumSpd_FS (0x1 << 1) +#define S3C_DSTS_EnumSpd_LS (0x2 << 1) +#define S3C_DSTS_EnumSpd_FS48 (0x3 << 1) + +#define S3C_DSTS_SuspSts (1 << 0) + +#define S3C_DIEPMSK S3C_HSOTG_REG(0x810) + +#define S3C_DIEPMSK_INEPNakEffMsk (1 << 6) +#define S3C_DIEPMSK_INTknEPMisMsk (1 << 5) +#define S3C_DIEPMSK_INTknTXFEmpMsk (1 << 4) +#define S3C_DIEPMSK_TimeOUTMsk (1 << 3) +#define S3C_DIEPMSK_AHBErrMsk (1 << 2) +#define S3C_DIEPMSK_EPDisbldMsk (1 << 1) +#define S3C_DIEPMSK_XferComplMsk (1 << 0) + +#define S3C_DOEPMSK S3C_HSOTG_REG(0x814) + +#define S3C_DOEPMSK_Back2BackSetup (1 << 6) +#define S3C_DOEPMSK_OUTTknEPdisMsk (1 << 4) +#define S3C_DOEPMSK_SetupMsk (1 << 3) +#define S3C_DOEPMSK_AHBErrMsk (1 << 2) +#define S3C_DOEPMSK_EPDisbldMsk (1 << 1) +#define S3C_DOEPMSK_XferComplMsk (1 << 0) + +#define S3C_DAINT S3C_HSOTG_REG(0x818) +#define S3C_DAINTMSK S3C_HSOTG_REG(0x81C) + +#define S3C_DAINT_OutEP_SHIFT (16) +#define S3C_DAINT_OutEP(x) (1 << ((x) + 16)) +#define S3C_DAINT_InEP(x) (1 << (x)) + +#define S3C_DTKNQR1 S3C_HSOTG_REG(0x820) +#define S3C_DTKNQR2 S3C_HSOTG_REG(0x824) +#define S3C_DTKNQR3 S3C_HSOTG_REG(0x830) +#define S3C_DTKNQR4 S3C_HSOTG_REG(0x834) + +#define S3C_DVBUSDIS S3C_HSOTG_REG(0x828) +#define S3C_DVBUSPULSE S3C_HSOTG_REG(0x82C) + +#define S3C_DIEPCTL0 S3C_HSOTG_REG(0x900) +#define S3C_DOEPCTL0 S3C_HSOTG_REG(0xB00) +#define S3C_DIEPCTL(_a) S3C_HSOTG_REG(0x900 + ((_a) * 0x20)) +#define S3C_DOEPCTL(_a) S3C_HSOTG_REG(0xB00 + ((_a) * 0x20)) + +/* EP0 specialness: + * bits[29..28] - reserved (no SetD0PID, SetD1PID) + * bits[25..22] - should always be zero, this isn't a periodic endpoint + * bits[10..0] - MPS setting differenct for EP0 +*/ +#define S3C_D0EPCTL_MPS_MASK (0x3 << 0) +#define S3C_D0EPCTL_MPS_SHIFT (0) +#define S3C_D0EPCTL_MPS_64 (0x0 << 0) +#define S3C_D0EPCTL_MPS_32 (0x1 << 0) +#define S3C_D0EPCTL_MPS_16 (0x2 << 0) +#define S3C_D0EPCTL_MPS_8 (0x3 << 0) + +#define S3C_DxEPCTL_EPEna (1 << 31) +#define S3C_DxEPCTL_EPDis (1 << 30) +#define S3C_DxEPCTL_SetD1PID (1 << 29) +#define S3C_DxEPCTL_SetOddFr (1 << 29) +#define S3C_DxEPCTL_SetD0PID (1 << 28) +#define S3C_DxEPCTL_SetEvenFr (1 << 28) +#define S3C_DxEPCTL_SNAK (1 << 27) +#define S3C_DxEPCTL_CNAK (1 << 26) +#define S3C_DxEPCTL_TxFNum_MASK (0xf << 22) +#define S3C_DxEPCTL_TxFNum_SHIFT (22) +#define S3C_DxEPCTL_TxFNum_LIMIT (0xf) +#define S3C_DxEPCTL_TxFNum(_x) ((_x) << 22) + +#define S3C_DxEPCTL_Stall (1 << 21) +#define S3C_DxEPCTL_Snp (1 << 20) +#define S3C_DxEPCTL_EPType_MASK (0x3 << 18) +#define S3C_DxEPCTL_EPType_SHIFT (18) +#define S3C_DxEPCTL_EPType_Control (0x0 << 18) +#define S3C_DxEPCTL_EPType_Iso (0x1 << 18) +#define S3C_DxEPCTL_EPType_Bulk (0x2 << 18) +#define S3C_DxEPCTL_EPType_Intterupt (0x3 << 18) + +#define S3C_DxEPCTL_NAKsts (1 << 17) +#define S3C_DxEPCTL_DPID (1 << 16) +#define S3C_DxEPCTL_EOFrNum (1 << 16) +#define S3C_DxEPCTL_USBActEp (1 << 15) +#define S3C_DxEPCTL_NextEp_MASK (0xf << 11) +#define S3C_DxEPCTL_NextEp_SHIFT (11) +#define S3C_DxEPCTL_NextEp_LIMIT (0xf) +#define S3C_DxEPCTL_NextEp(_x) ((_x) << 11) + +#define S3C_DxEPCTL_MPS_MASK (0x7ff << 0) +#define S3C_DxEPCTL_MPS_SHIFT (0) +#define S3C_DxEPCTL_MPS_LIMIT (0x7ff) +#define S3C_DxEPCTL_MPS(_x) ((_x) << 0) + +#define S3C_DIEPINT(_a) S3C_HSOTG_REG(0x908 + ((_a) * 0x20)) +#define S3C_DOEPINT(_a) S3C_HSOTG_REG(0xB08 + ((_a) * 0x20)) + +#define S3C_DxEPINT_INEPNakEff (1 << 6) +#define S3C_DxEPINT_Back2BackSetup (1 << 6) +#define S3C_DxEPINT_INTknEPMis (1 << 5) +#define S3C_DxEPINT_INTknTXFEmp (1 << 4) +#define S3C_DxEPINT_OUTTknEPdis (1 << 4) +#define S3C_DxEPINT_Timeout (1 << 3) +#define S3C_DxEPINT_Setup (1 << 3) +#define S3C_DxEPINT_AHBErr (1 << 2) +#define S3C_DxEPINT_EPDisbld (1 << 1) +#define S3C_DxEPINT_XferCompl (1 << 0) + +#define S3C_DIEPTSIZ0 S3C_HSOTG_REG(0x910) + +#define S3C_DIEPTSIZ0_PktCnt_MASK (0x3 << 19) +#define S3C_DIEPTSIZ0_PktCnt_SHIFT (19) +#define S3C_DIEPTSIZ0_PktCnt_LIMIT (0x3) +#define S3C_DIEPTSIZ0_PktCnt(_x) ((_x) << 19) + +#define S3C_DIEPTSIZ0_XferSize_MASK (0x7f << 0) +#define S3C_DIEPTSIZ0_XferSize_SHIFT (0) +#define S3C_DIEPTSIZ0_XferSize_LIMIT (0x7f) +#define S3C_DIEPTSIZ0_XferSize(_x) ((_x) << 0) + + +#define DOEPTSIZ0 S3C_HSOTG_REG(0xB10) +#define S3C_DOEPTSIZ0_SUPCnt_MASK (0x3 << 29) +#define S3C_DOEPTSIZ0_SUPCnt_SHIFT (29) +#define S3C_DOEPTSIZ0_SUPCnt_LIMIT (0x3) +#define S3C_DOEPTSIZ0_SUPCnt(_x) ((_x) << 29) + +#define S3C_DOEPTSIZ0_PktCnt (1 << 19) +#define S3C_DOEPTSIZ0_XferSize_MASK (0x7f << 0) +#define S3C_DOEPTSIZ0_XferSize_SHIFT (0) + +#define S3C_DIEPTSIZ(_a) S3C_HSOTG_REG(0x910 + ((_a) * 0x20)) +#define S3C_DOEPTSIZ(_a) S3C_HSOTG_REG(0xB10 + ((_a) * 0x20)) + +#define S3C_DxEPTSIZ_MC_MASK (0x3 << 29) +#define S3C_DxEPTSIZ_MC_SHIFT (29) +#define S3C_DxEPTSIZ_MC_LIMIT (0x3) +#define S3C_DxEPTSIZ_MC(_x) ((_x) << 29) + +#define S3C_DxEPTSIZ_PktCnt_MASK (0x3ff << 19) +#define S3C_DxEPTSIZ_PktCnt_SHIFT (19) +#define S3C_DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff) +#define S3C_DxEPTSIZ_PktCnt_LIMIT (0x3ff) +#define S3C_DxEPTSIZ_PktCnt(_x) ((_x) << 19) + +#define S3C_DxEPTSIZ_XferSize_MASK (0x7ffff << 0) +#define S3C_DxEPTSIZ_XferSize_SHIFT (0) +#define S3C_DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff) +#define S3C_DxEPTSIZ_XferSize_LIMIT (0x7ffff) +#define S3C_DxEPTSIZ_XferSize(_x) ((_x) << 0) + + +#define S3C_DIEPDMA(_a) S3C_HSOTG_REG(0x914 + ((_a) * 0x20)) +#define S3C_DOEPDMA(_a) S3C_HSOTG_REG(0xB14 + ((_a) * 0x20)) + +#define S3C_EPFIFO(_a) S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000)) + +#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */ diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-s3c/include/plat/sdhci.h index c4ca3920ca4b..f615308ccdfb 100644 --- a/arch/arm/plat-s3c/include/plat/sdhci.h +++ b/arch/arm/plat-s3c/include/plat/sdhci.h @@ -67,12 +67,52 @@ extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata; /* Helper function availablity */ +extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w); +extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w); + +/* S3C6400 SDHCI setup */ + +#ifdef CONFIG_S3C6400_SETUP_SDHCI +extern char *s3c6400_hsmmc_clksrcs[4]; + +#ifdef CONFIG_S3C_DEV_HSMMC +extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card); + +static inline void s3c6400_default_sdhci0(void) +{ + s3c_hsmmc0_def_platdata.clocks = s3c6400_hsmmc_clksrcs; + s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; + s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; +} + +#else +static inline void s3c6400_default_sdhci0(void) { } +#endif /* CONFIG_S3C_DEV_HSMMC */ + +#ifdef CONFIG_S3C_DEV_HSMMC1 +static inline void s3c6400_default_sdhci1(void) +{ + s3c_hsmmc1_def_platdata.clocks = s3c6400_hsmmc_clksrcs; + s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; + s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; +} +#else +static inline void s3c6400_default_sdhci1(void) { } +#endif /* CONFIG_S3C_DEV_HSMMC1 */ + +#else +static inline void s3c6400_default_sdhci0(void) { } +static inline void s3c6400_default_sdhci1(void) { } +#endif /* CONFIG_S3C6400_SETUP_SDHCI */ + +/* S3C6410 SDHCI setup */ + #ifdef CONFIG_S3C6410_SETUP_SDHCI extern char *s3c6410_hsmmc_clksrcs[4]; -extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w); -extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w); - extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, void __iomem *r, struct mmc_ios *ios, @@ -82,7 +122,7 @@ extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, static inline void s3c6410_default_sdhci0(void) { s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs; - s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio; + s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; } #else @@ -93,7 +133,7 @@ static inline void s3c6410_default_sdhci0(void) { } static inline void s3c6410_default_sdhci1(void) { s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs; - s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio; + s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; } #else diff --git a/arch/arm/plat-s3c/include/plat/udc-hs.h b/arch/arm/plat-s3c/include/plat/udc-hs.h new file mode 100644 index 000000000000..dd04db043109 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/udc-hs.h @@ -0,0 +1,29 @@ +/* arch/arm/plat-s3c/include/plat/udc-hs.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C USB2.0 High-speed / OtG platform information + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +enum s3c_hostg_dmamode { + S3C_HSOTG_DMA_NONE, /* do not use DMA at-all */ + S3C_HSOTG_DMA_ONLY, /* always use DMA */ + S3C_HSOTG_DMA_DRV, /* DMA is chosen by driver */ +}; + +/** + * struct s3c_hsotg_plat - platform data for high-speed otg/udc + * @dma: Whether to use DMA or not. + * @is_osc: The clock source is an oscillator, not a crystal + */ +struct s3c_hsotg_plat { + enum s3c_hostg_dmamode dma; + unsigned int is_osc : 1; +}; diff --git a/arch/arm/plat-s3c/include/plat/watchdog-reset.h b/arch/arm/plat-s3c/include/plat/watchdog-reset.h new file mode 100644 index 000000000000..54b762acb5a0 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/watchdog-reset.h @@ -0,0 +1,49 @@ +/* arch/arm/plat-s3c/include/plat/watchdog-reset.h + * + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S3C2410 - System define for arch_reset() function + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <plat/regs-watchdog.h> +#include <mach/map.h> + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> + +static inline void arch_wdt_reset(void) +{ + struct clk *wdtclk; + + printk("arch_reset: attempting watchdog reset\n"); + + __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ + + wdtclk = clk_get(NULL, "watchdog"); + if (!IS_ERR(wdtclk)) { + clk_enable(wdtclk); + } else + printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); + + /* put initial values into count and data */ + __raw_writel(0x80, S3C2410_WTCNT); + __raw_writel(0x80, S3C2410_WTDAT); + + /* set the watchdog to go and reset... */ + __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | + S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); + + /* wait for reset to assert... */ + mdelay(500); + + printk(KERN_ERR "Watchdog reset failed to assert reset\n"); + + /* delay to allow the serial port to show the message */ + mdelay(50); +} |
