diff options
Diffstat (limited to 'arch/arm/mach-ux500')
35 files changed, 635 insertions, 568 deletions
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 4210cb434dbc..a3e0c8692f0d 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -6,6 +6,7 @@ config UX500_SOC_COMMON select ARM_GIC select HAS_MTU select ARM_ERRATA_753970 + select ARM_ERRATA_754322 menu "Ux500 SoC" diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 1694916e6822..6bd2f451c185 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -3,7 +3,8 @@ # obj-y := clock.o cpu.o devices.o devices-common.o \ - id.o usb.o + id.o usb.o timer.o +obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \ diff --git a/arch/arm/mach-ux500/Makefile.boot b/arch/arm/mach-ux500/Makefile.boot index c7e75acfe6c9..ff0a4b5b0a82 100644 --- a/arch/arm/mach-ux500/Makefile.boot +++ b/arch/arm/mach-ux500/Makefile.boot @@ -1,4 +1,4 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index f26fd76f72b4..74bfcff2bdf3 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -6,10 +6,10 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/gpio.h> #include <asm/mach-types.h> #include <plat/pincfg.h> +#include <plat/gpio-nomadik.h> #include <mach/hardware.h> #include "pins-db8500.h" @@ -153,7 +153,7 @@ static pin_cfg_t mop500_pins_default[] = { GPIO7_U1_RTSn | PIN_OUTPUT_HIGH, }; -static pin_cfg_t mop500_pins_hrefv60[] = { +static pin_cfg_t hrefv60_pins[] = { /* WLAN */ GPIO4_GPIO | PIN_INPUT_PULLUP,/* WLAN_IRQ */ GPIO85_GPIO | PIN_OUTPUT_LOW,/* WLAN_ENA */ @@ -279,14 +279,26 @@ static pin_cfg_t snowball_pins[] = { void __init mop500_pins_init(void) { nmk_config_pins(mop500_pins_common, - ARRAY_SIZE(mop500_pins_common)); - if (machine_is_hrefv60()) - nmk_config_pins(mop500_pins_hrefv60, - ARRAY_SIZE(mop500_pins_hrefv60)); - else if (machine_is_snowball()) - nmk_config_pins(snowball_pins, - ARRAY_SIZE(snowball_pins)); - else - nmk_config_pins(mop500_pins_default, - ARRAY_SIZE(mop500_pins_default)); + ARRAY_SIZE(mop500_pins_common)); + + nmk_config_pins(mop500_pins_default, + ARRAY_SIZE(mop500_pins_default)); +} + +void __init snowball_pins_init(void) +{ + nmk_config_pins(mop500_pins_common, + ARRAY_SIZE(mop500_pins_common)); + + nmk_config_pins(snowball_pins, + ARRAY_SIZE(snowball_pins)); +} + +void __init hrefv60_pins_init(void) +{ + nmk_config_pins(mop500_pins_common, + ARRAY_SIZE(mop500_pins_common)); + + nmk_config_pins(hrefv60_pins, + ARRAY_SIZE(hrefv60_pins)); } diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index d0cb9e5eb87c..23be34b3bb6e 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -22,6 +22,12 @@ #include "ste-dma40-db8500.h" /* + * v2 has a new version of this block that need to be forced, the number found + * in hardware is incorrect + */ +#define U8500_SDI_V2_PERIPHID 0x10480180 + +/* * SDI 0 (MicroSD slot) */ @@ -117,10 +123,7 @@ static void sdi0_configure(void) gpio_direction_output(sdi0_en, 1); /* Add the device, force v2 to subrevision 1 */ - if (cpu_is_u8500v2()) - db8500_add_sdi0(&mop500_sdi0_data, 0x10480180); - else - db8500_add_sdi0(&mop500_sdi0_data, 0); + db8500_add_sdi0(&mop500_sdi0_data, U8500_SDI_V2_PERIPHID); } void mop500_sdi_tc35892_init(void) @@ -132,6 +135,42 @@ void mop500_sdi_tc35892_init(void) } /* + * SDI1 (SDIO WLAN) + */ +#ifdef CONFIG_STE_DMA40 +static struct stedma40_chan_cfg sdi1_dma_cfg_rx = { + .mode = STEDMA40_MODE_LOGICAL, + .dir = STEDMA40_PERIPH_TO_MEM, + .src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX, + .dst_dev_type = STEDMA40_DEV_DST_MEMORY, + .src_info.data_width = STEDMA40_WORD_WIDTH, + .dst_info.data_width = STEDMA40_WORD_WIDTH, +}; + +static struct stedma40_chan_cfg sdi1_dma_cfg_tx = { + .mode = STEDMA40_MODE_LOGICAL, + .dir = STEDMA40_MEM_TO_PERIPH, + .src_dev_type = STEDMA40_DEV_SRC_MEMORY, + .dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX, + .src_info.data_width = STEDMA40_WORD_WIDTH, + .dst_info.data_width = STEDMA40_WORD_WIDTH, +}; +#endif + +static struct mmci_platform_data mop500_sdi1_data = { + .ocr_mask = MMC_VDD_29_30, + .f_max = 50000000, + .capabilities = MMC_CAP_4_BIT_DATA, + .gpio_cd = -1, + .gpio_wp = -1, +#ifdef CONFIG_STE_DMA40 + .dma_filter = stedma40_filter, + .dma_rx_param = &sdi1_dma_cfg_rx, + .dma_tx_param = &sdi1_dma_cfg_tx, +#endif +}; + +/* * SDI 2 (POP eMMC, not on DB8500ed) */ @@ -158,7 +197,8 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = { static struct mmci_platform_data mop500_sdi2_data = { .ocr_mask = MMC_VDD_165_195, .f_max = 50000000, - .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED, .gpio_cd = -1, .gpio_wp = -1, #ifdef CONFIG_STE_DMA40 @@ -208,38 +248,40 @@ static struct mmci_platform_data mop500_sdi4_data = { void __init mop500_sdi_init(void) { - u32 periphid = 0; - - /* v2 has a new version of this block that need to be forced */ - if (cpu_is_u8500v2()) - periphid = 0x10480180; - /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */ - if (!cpu_is_u8500v10()) - mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; - /* sdi2 on snowball is in ATL_B mode for FSMC (LAN) */ - if (!machine_is_snowball()) - db8500_add_sdi2(&mop500_sdi2_data, periphid); - + /* PoP:ed eMMC */ + db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID); /* On-board eMMC */ - db8500_add_sdi4(&mop500_sdi4_data, periphid); - - if (machine_is_hrefv60() || machine_is_snowball()) { - if (machine_is_hrefv60()) { - mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; - sdi0_en = HREFV60_SDMMC_EN_GPIO; - sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO; - } else if (machine_is_snowball()) { - mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; - mop500_sdi0_data.cd_invert = true; - sdi0_en = SNOWBALL_SDMMC_EN_GPIO; - sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO; - } - sdi0_configure(); - } - + db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); /* * On boards with the TC35892 GPIO expander, sdi0 will finally * be added when the TC35892 initializes and calls * mop500_sdi_tc35892_init() above. */ } + +void __init snowball_sdi_init(void) +{ + /* On-board eMMC */ + db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); + /* External Micro SD slot */ + mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; + mop500_sdi0_data.cd_invert = true; + sdi0_en = SNOWBALL_SDMMC_EN_GPIO; + sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO; + sdi0_configure(); +} + +void __init hrefv60_sdi_init(void) +{ + /* PoP:ed eMMC */ + db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID); + /* On-board eMMC */ + db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); + /* External Micro SD slot */ + mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; + sdi0_en = HREFV60_SDMMC_EN_GPIO; + sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO; + sdi0_configure(); + /* WLAN SDIO channel */ + db8500_add_sdi1(&mop500_sdi1_data, U8500_SDI_V2_PERIPHID); +} diff --git a/arch/arm/mach-ux500/board-mop500-u8500uib.c b/arch/arm/mach-ux500/board-mop500-u8500uib.c index 8ce46c0fdfd5..feb5744d98b7 100644 --- a/arch/arm/mach-ux500/board-mop500-u8500uib.c +++ b/arch/arm/mach-ux500/board-mop500-u8500uib.c @@ -4,7 +4,7 @@ * Board data for the U8500 UIB, also known as the New UIB * License terms: GNU General Public License (GPL), version 2 */ - +#include <linux/gpio.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/i2c.h> @@ -13,7 +13,6 @@ #include <linux/mfd/tc3589x.h> #include <linux/input/matrix_keypad.h> -#include <mach/gpio.h> #include <mach/irqs.h> #include "board-mop500.h" diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index cd54abaccd96..5c00712907d1 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -19,11 +19,11 @@ #include <linux/amba/pl022.h> #include <linux/amba/serial.h> #include <linux/spi/spi.h> -#include <linux/mfd/ab8500.h> +#include <linux/mfd/abx500/ab8500.h> #include <linux/regulator/ab8500.h> #include <linux/mfd/tc3589x.h> #include <linux/mfd/tps6105x.h> -#include <linux/mfd/ab8500/gpio.h> +#include <linux/mfd/abx500/ab8500-gpio.h> #include <linux/leds-lp5521.h> #include <linux/input.h> #include <linux/smsc911x.h> @@ -33,10 +33,12 @@ #include <linux/leds.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> +#include <asm/hardware/gic.h> #include <plat/i2c.h> #include <plat/ste_dma40.h> #include <plat/pincfg.h> +#include <plat/gpio-nomadik.h> #include <mach/hardware.h> #include <mach/setup.h> @@ -603,37 +605,81 @@ static void __init mop500_init_machine(void) { int i2c0_devs; + mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; + + u8500_init_devices(); + + mop500_pins_init(); + + platform_add_devices(mop500_platform_devs, + ARRAY_SIZE(mop500_platform_devs)); + + mop500_i2c_init(); + mop500_sdi_init(); + mop500_spi_init(); + mop500_uart_init(); + + i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); + + i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); + i2c_register_board_info(2, mop500_i2c2_devices, + ARRAY_SIZE(mop500_i2c2_devices)); + + /* This board has full regulator constraints */ + regulator_has_full_constraints(); +} + +static void __init snowball_init_machine(void) +{ + int i2c0_devs; + + u8500_init_devices(); + + snowball_pins_init(); + + platform_add_devices(snowball_platform_devs, + ARRAY_SIZE(snowball_platform_devs)); + + mop500_i2c_init(); + snowball_sdi_init(); + mop500_spi_init(); + mop500_uart_init(); + + i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); + i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); + i2c_register_board_info(2, mop500_i2c2_devices, + ARRAY_SIZE(mop500_i2c2_devices)); + + /* This board has full regulator constraints */ + regulator_has_full_constraints(); +} + +static void __init hrefv60_init_machine(void) +{ + int i2c0_devs; + /* * The HREFv60 board removed a GPIO expander and routed * all these GPIO pins to the internal GPIO controller * instead. */ - if (!machine_is_snowball()) { - if (machine_is_hrefv60()) - mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; - else - mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; - } + mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; u8500_init_devices(); - mop500_pins_init(); + hrefv60_pins_init(); - if (machine_is_snowball()) - platform_add_devices(snowball_platform_devs, - ARRAY_SIZE(snowball_platform_devs)); - else - platform_add_devices(mop500_platform_devs, - ARRAY_SIZE(mop500_platform_devs)); + platform_add_devices(mop500_platform_devs, + ARRAY_SIZE(mop500_platform_devs)); mop500_i2c_init(); - mop500_sdi_init(); + hrefv60_sdi_init(); mop500_spi_init(); mop500_uart_init(); i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); - if (machine_is_hrefv60()) - i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; + + i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); i2c_register_board_info(2, mop500_i2c2_devices, @@ -645,27 +691,30 @@ static void __init mop500_init_machine(void) MACHINE_START(U8500, "ST-Ericsson MOP500 platform") /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */ - .boot_params = 0x100, + .atag_offset = 0x100, .map_io = u8500_map_io, .init_irq = ux500_init_irq, /* we re-use nomadik timer here */ .timer = &ux500_timer, + .handle_irq = gic_handle_irq, .init_machine = mop500_init_machine, MACHINE_END MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+") - .boot_params = 0x100, + .atag_offset = 0x100, .map_io = u8500_map_io, .init_irq = ux500_init_irq, .timer = &ux500_timer, - .init_machine = mop500_init_machine, + .handle_irq = gic_handle_irq, + .init_machine = hrefv60_init_machine, MACHINE_END MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") - .boot_params = 0x100, + .atag_offset = 0x100, .map_io = u8500_map_io, .init_irq = ux500_init_irq, /* we re-use nomadik timer here */ .timer = &ux500_timer, - .init_machine = mop500_init_machine, + .handle_irq = gic_handle_irq, + .init_machine = snowball_init_machine, MACHINE_END diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index ee77a8970c33..f926d3db6207 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -7,43 +7,83 @@ #ifndef __BOARD_MOP500_H #define __BOARD_MOP500_H -/* snowball GPIO for MMC card */ -#define SNOWBALL_SDMMC_EN_GPIO 217 -#define SNOWBALL_SDMMC_1V8_3V_GPIO 228 -#define SNOWBALL_SDMMC_CD_GPIO 218 +/* Snowball specific GPIO assignments, this board has no GPIO expander */ +#define SNOWBALL_ACCEL_INT1_GPIO 163 +#define SNOWBALL_ACCEL_INT2_GPIO 164 +#define SNOWBALL_MAGNET_DRDY_GPIO 165 +#define SNOWBALL_SDMMC_EN_GPIO 217 +#define SNOWBALL_SDMMC_1V8_3V_GPIO 228 +#define SNOWBALL_SDMMC_CD_GPIO 218 /* HREFv60-specific GPIO assignments, this board has no GPIO expander */ -#define HREFV60_TOUCH_RST_GPIO 143 -#define HREFV60_PROX_SENSE_GPIO 217 -#define HREFV60_HAL_SW_GPIO 145 -#define HREFV60_SDMMC_EN_GPIO 169 #define HREFV60_SDMMC_1V8_3V_GPIO 5 -#define HREFV60_SDMMC_CD_GPIO 95 -#define HREFV60_ACCEL_INT1_GPIO 82 -#define HREFV60_ACCEL_INT2_GPIO 83 +#define HREFV60_CAMERA_FLASH_ENABLE 21 #define HREFV60_MAGNET_DRDY_GPIO 32 #define HREFV60_DISP1_RST_GPIO 65 #define HREFV60_DISP2_RST_GPIO 66 +#define HREFV60_ACCEL_INT1_GPIO 82 +#define HREFV60_ACCEL_INT2_GPIO 83 +#define HREFV60_SDMMC_CD_GPIO 95 +#define HREFV60_XSHUTDOWN_SECONDARY_SENSOR 140 +#define HREFV60_TOUCH_RST_GPIO 143 +#define HREFV60_HAL_SW_GPIO 145 +#define HREFV60_SDMMC_EN_GPIO 169 +#define HREFV60_MMIO_XENON_CHARGE 170 +#define HREFV60_PROX_SENSE_GPIO 217 + +/* MOP500 generic GPIOs */ +#define CAMERA_FLASH_INT_PIN 7 +#define CYPRESS_TOUCH_INT_PIN 84 +#define XSHUTDOWN_PRIMARY_SENSOR 141 +#define XSHUTDOWN_SECONDARY_SENSOR 142 +#define CYPRESS_TOUCH_RST_GPIO 143 +#define MOP500_HDMI_RST_GPIO 196 +#define CYPRESS_SLAVE_SELECT_GPIO 216 /* GPIOs on the TC35892 expander */ #define MOP500_EGPIO(x) (NOMADIK_NR_GPIO + (x)) +#define GPIO_MAGNET_DRDY MOP500_EGPIO(1) #define GPIO_SDMMC_CD MOP500_EGPIO(3) +#define GPIO_CAMERA_FLASH_ENABLE MOP500_EGPIO(4) +#define GPIO_MMIO_XENON_CHARGE MOP500_EGPIO(5) #define GPIO_PROX_SENSOR MOP500_EGPIO(7) +#define GPIO_HAL_SENSOR MOP500_EGPIO(8) +#define GPIO_ACCEL_INT1 MOP500_EGPIO(10) +#define GPIO_ACCEL_INT2 MOP500_EGPIO(11) #define GPIO_BU21013_CS MOP500_EGPIO(13) +#define MOP500_DISP2_RST_GPIO MOP500_EGPIO(14) +#define MOP500_DISP1_RST_GPIO MOP500_EGPIO(15) #define GPIO_SDMMC_EN MOP500_EGPIO(17) #define GPIO_SDMMC_1V8_3V_SEL MOP500_EGPIO(18) #define MOP500_EGPIO_END MOP500_EGPIO(24) -/* GPIOs on the AB8500 mixed-signals circuit */ -#define MOP500_AB8500_GPIO(x) (MOP500_EGPIO_END + (x)) +/* + * GPIOs on the AB8500 mixed-signals circuit + * Notice that we subtract 1 from the number passed into the macro, this is + * because the AB8500 GPIO pins are enumbered starting from 1, so the value in + * parens matches the GPIO pin number in the data sheet. + */ +#define MOP500_AB8500_GPIO(x) (MOP500_EGPIO_END + (x) - 1) +/*Snowball AB8500 GPIO */ +#define SNOWBALL_VSMPS2_1V8_GPIO MOP500_AB8500_PIN_GPIO(1) /* SYSCLKREQ2/GPIO1 */ +#define SNOWBALL_PM_GPIO1_GPIO MOP500_AB8500_PIN_GPIO(2) /* SYSCLKREQ3/GPIO2 */ +#define SNOWBALL_WLAN_CLK_REQ_GPIO MOP500_AB8500_PIN_GPIO(3) /* SYSCLKREQ4/GPIO3 */ +#define SNOWBALL_PM_GPIO4_GPIO MOP500_AB8500_PIN_GPIO(4) /* SYSCLKREQ6/GPIO4 */ +#define SNOWBALL_EN_3V6_GPIO MOP500_AB8500_PIN_GPIO(16) /* PWMOUT3/GPIO16 */ +#define SNOWBALL_PME_ETH_GPIO MOP500_AB8500_PIN_GPIO(24) /* SYSCLKREQ7/GPIO24 */ +#define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */ struct i2c_board_info; extern void mop500_sdi_init(void); +extern void snowball_sdi_init(void); +extern void hrefv60_sdi_init(void); extern void mop500_sdi_tc35892_init(void); void __init mop500_u8500uib_init(void); void __init mop500_stuib_init(void); void __init mop500_pins_init(void); +void __init hrefv60_pins_init(void); +void __init snowball_pins_init(void); void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, unsigned n); diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c index 739fb4c5b160..63c3f8058ffc 100644 --- a/arch/arm/mach-ux500/board-u5500-sdi.c +++ b/arch/arm/mach-ux500/board-u5500-sdi.c @@ -7,9 +7,9 @@ #include <linux/amba/mmci.h> #include <linux/mmc/host.h> -#include <linux/gpio.h> #include <plat/pincfg.h> +#include <plat/gpio-nomadik.h> #include <mach/db5500-regs.h> #include <plat/ste_dma40.h> diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c index e58f0f562426..9de9e9c4dbbb 100644 --- a/arch/arm/mach-ux500/board-u5500.c +++ b/arch/arm/mach-ux500/board-u5500.c @@ -8,15 +8,17 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/amba/bus.h> -#include <linux/gpio.h> #include <linux/irq.h> #include <linux/i2c.h> +#include <linux/mfd/abx500/ab5500.h> +#include <asm/hardware/gic.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <plat/pincfg.h> #include <plat/i2c.h> +#include <plat/gpio-nomadik.h> #include <mach/hardware.h> #include <mach/devices.h> @@ -87,7 +89,6 @@ static struct lm3530_platform_data u5500_als_platform_data = { .brt_val = 0x7F, /* Max brightness */ }; - static struct i2c_board_info __initdata u5500_i2c2_devices[] = { { /* Backlight */ @@ -101,6 +102,30 @@ static void __init u5500_i2c_init(void) db5500_add_i2c2(&u5500_i2c2_data); i2c_register_board_info(2, ARRAY_AND_SIZE(u5500_i2c2_devices)); } + +static struct ab5500_platform_data ab5500_plf_data = { + .irq = { + .base = 0, + .count = 0, + }, + .init_settings = NULL, + .init_settings_sz = 0, + .pm_power_off = false, +}; + +static struct platform_device ab5500_device = { + .name = "ab5500-core", + .id = 0, + .dev = { + .platform_data = &ab5500_plf_data, + }, + .num_resources = 0, +}; + +static struct platform_device *u5500_platform_devices[] __initdata = { + &ab5500_device, +}; + static void __init u5500_uart_init(void) { db5500_add_uart0(NULL); @@ -115,12 +140,16 @@ static void __init u5500_init_machine(void) u5500_i2c_init(); u5500_sdi_init(); u5500_uart_init(); + + platform_add_devices(u5500_platform_devices, + ARRAY_SIZE(u5500_platform_devices)); } MACHINE_START(U5500, "ST-Ericsson U5500 Platform") - .boot_params = 0x00000100, + .atag_offset = 0x100, .map_io = u5500_map_io, .init_irq = ux500_init_irq, .timer = &ux500_timer, + .handle_irq = gic_handle_irq, .init_machine = u5500_init_machine, MACHINE_END diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c new file mode 100644 index 000000000000..122ddde00ba7 --- /dev/null +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -0,0 +1,95 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/io.h> +#include <asm/cacheflush.h> +#include <asm/hardware/cache-l2x0.h> +#include <mach/hardware.h> +#include <mach/id.h> + +static void __iomem *l2x0_base; + +static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask) +{ + /* wait for the operation to complete */ + while (readl_relaxed(reg) & mask) + cpu_relax(); +} + +static inline void ux500_cache_sync(void) +{ + writel_relaxed(0, l2x0_base + L2X0_CACHE_SYNC); + ux500_cache_wait(l2x0_base + L2X0_CACHE_SYNC, 1); +} + +/* + * The L2 cache cannot be turned off in the non-secure world. + * Dummy until a secure service is in place. + */ +static void ux500_l2x0_disable(void) +{ +} + +/* + * This is only called when doing a kexec, just after turning off the L2 + * and L1 cache, and it is surrounded by a spinlock in the generic version. + * However, we're not really turning off the L2 cache right now and the + * PL310 does not support exclusive accesses (used to implement the spinlock). + * So, the invalidation needs to be done without the spinlock. + */ +static void ux500_l2x0_inv_all(void) +{ + uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */ + + /* invalidate all ways */ + writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); + ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); + ux500_cache_sync(); +} + +static int __init ux500_l2x0_unlock(void) +{ + int i; + + /* + * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions + * apparently locks both caches before jumping to the kernel. The + * l2x0 core will not touch the unlock registers if the l2x0 is + * already enabled, so we do it right here instead. The PL310 has + * 8 sets of registers, one per possible CPU. + */ + for (i = 0; i < 8; i++) { + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE + + i * L2X0_LOCKDOWN_STRIDE); + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE + + i * L2X0_LOCKDOWN_STRIDE); + } + return 0; +} + +static int __init ux500_l2x0_init(void) +{ + if (cpu_is_u5500()) + l2x0_base = __io_address(U5500_L2CC_BASE); + else if (cpu_is_u8500()) + l2x0_base = __io_address(U8500_L2CC_BASE); + else + ux500_unknown_soc(); + + /* Unlock before init */ + ux500_l2x0_unlock(); + + /* 64KB way size, 8 way associativity, force WA */ + l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); + + /* Override invalidate function */ + outer_cache.disable = ux500_l2x0_disable; + outer_cache.inv_all = ux500_l2x0_inv_all; + + return 0; +} + +early_initcall(ux500_l2x0_init); diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index e832664d1bd9..737907537004 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@ -239,23 +239,6 @@ static void clk_prcmu_disable(struct clk *clk) writel(1 << clk->prcmu_cg_bit, cg_clr_reg); } -/* ED doesn't have the combined set/clr registers */ -static void clk_prcmu_ed_enable(struct clk *clk) -{ - void __iomem *addr = __io_address(U8500_PRCMU_BASE) - + clk->prcmu_cg_mgt; - - writel(readl(addr) | PRCM_MGT_ENABLE, addr); -} - -static void clk_prcmu_ed_disable(struct clk *clk) -{ - void __iomem *addr = __io_address(U8500_PRCMU_BASE) - + clk->prcmu_cg_mgt; - - writel(readl(addr) & ~PRCM_MGT_ENABLE, addr); -} - static struct clkops clk_prcmu_ops = { .enable = clk_prcmu_enable, .disable = clk_prcmu_disable, @@ -267,7 +250,6 @@ static unsigned int clkrst_base[] = { [3] = U8500_CLKRST3_BASE, [5] = U8500_CLKRST5_BASE, [6] = U8500_CLKRST6_BASE, - [7] = U8500_CLKRST7_BASE_ED, }; static void clk_prcc_enable(struct clk *clk) @@ -321,7 +303,6 @@ static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK); static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK); static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK); static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000); -static DEFINE_PRCMU_CLK_RATE(per7clk, 0x0, 16, PER7CLK, 100000000); static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK); static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK); static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK); @@ -351,44 +332,28 @@ static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */ static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); -static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL); -static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL); +static DEFINE_PRCC_CLK(1, spi3, 7, -1, NULL); static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk); -static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk); +static DEFINE_PRCC_CLK(1, msp1, 4, 4, &clk_msp1clk); static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); /* Peripheral Cluster #2 */ - -static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL); -static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL); -static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL); -static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL); -static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk); -static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL); -static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL); -static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL); -static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk); - -static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL); -static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL); -static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL); -static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL); -static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk); -static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL); -static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL); -static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL); -static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk); +static DEFINE_PRCC_CLK(2, gpio1, 11, -1, NULL); +static DEFINE_PRCC_CLK(2, ssitx, 10, 7, NULL); +static DEFINE_PRCC_CLK(2, ssirx, 9, 6, NULL); +static DEFINE_PRCC_CLK(2, spi0, 8, -1, NULL); +static DEFINE_PRCC_CLK(2, sdi3, 7, 5, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, sdi1, 6, 4, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, msp2, 5, 3, &clk_msp02clk); +static DEFINE_PRCC_CLK(2, sdi4, 4, 2, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, pwl, 3, 1, NULL); +static DEFINE_PRCC_CLK(2, spi1, 2, -1, NULL); +static DEFINE_PRCC_CLK(2, spi2, 1, -1, NULL); +static DEFINE_PRCC_CLK(2, i2c3, 0, 0, &clk_i2cclk); /* Peripheral Cluster #3 */ static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); @@ -397,49 +362,34 @@ static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); -static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk); -static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk); -static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk); -static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk); +static DEFINE_PRCC_CLK(3, ssp1, 2, 2, &clk_sspclk); +static DEFINE_PRCC_CLK(3, ssp0, 1, 1, &clk_sspclk); static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); /* Peripheral Cluster #4 is in the always on domain */ /* Peripheral Cluster #5 */ static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); -static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk); -static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL); +static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL); /* Peripheral Cluster #6 */ /* MTU ID in data */ -static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1); -static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0); -static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); -static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL); +static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 8, -1, NULL, clk_mtu_get_rate, 1); +static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 7, -1, NULL, clk_mtu_get_rate, 0); +static DEFINE_PRCC_CLK(6, cfgreg, 6, 6, NULL); static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); -static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk); -static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL); +static DEFINE_PRCC_CLK(6, unipro, 4, 1, &clk_uniproclk); static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); -static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk); -static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk); - -/* Peripheral Cluster #7 */ - -static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL); -/* MTU ID in data */ -static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1); -static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0); -static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); -static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); +static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk); static struct clk clk_dummy_apb_pclk = { .name = "apb_pclk", }; -static struct clk_lookup u8500_common_clks[] = { +static struct clk_lookup u8500_clks[] = { CLK(dummy_apb_pclk, NULL, "apb_pclk"), /* Peripheral Cluster #1 */ @@ -494,83 +444,41 @@ static struct clk_lookup u8500_common_clks[] = { CLK(dmaclk, "dma40.0", NULL), CLK(b2r2clk, "b2r2", NULL), CLK(tvclk, "tv", NULL), -}; -static struct clk_lookup u8500_ed_clks[] = { - /* Peripheral Cluster #1 */ - CLK(spi3_ed, "spi3", NULL), - CLK(msp1_ed, "msp1", NULL), - - /* Peripheral Cluster #2 */ - CLK(gpio1_ed, "gpio.6", NULL), - CLK(gpio1_ed, "gpio.7", NULL), - CLK(ssitx_ed, "ssitx", NULL), - CLK(ssirx_ed, "ssirx", NULL), - CLK(spi0_ed, "spi0", NULL), - CLK(sdi3_ed, "sdi3", NULL), - CLK(sdi1_ed, "sdi1", NULL), - CLK(msp2_ed, "msp2", NULL), - CLK(sdi4_ed, "sdi4", NULL), - CLK(pwl_ed, "pwl", NULL), - CLK(spi1_ed, "spi1", NULL), - CLK(spi2_ed, "spi2", NULL), - CLK(i2c3_ed, "nmk-i2c.3", NULL), - - /* Peripheral Cluster #3 */ - CLK(ssp1_ed, "ssp1", NULL), - CLK(ssp0_ed, "ssp0", NULL), - - /* Peripheral Cluster #5 */ - CLK(usb_ed, "musb-ux500.0", "usb"), - - /* Peripheral Cluster #6 */ - CLK(dmc_ed, "dmc", NULL), - CLK(cryp1_ed, "cryp1", NULL), - CLK(rng_ed, "rng", NULL), - - /* Peripheral Cluster #7 */ - CLK(tzpc0_ed, "tzpc0", NULL), - CLK(mtu1_ed, "mtu1", NULL), - CLK(mtu0_ed, "mtu0", NULL), - CLK(wdg_ed, "wdg", NULL), - CLK(cfgreg_ed, "cfgreg", NULL), -}; - -static struct clk_lookup u8500_v1_clks[] = { /* Peripheral Cluster #1 */ CLK(i2c4, "nmk-i2c.4", NULL), - CLK(spi3_v1, "spi3", NULL), - CLK(msp1_v1, "msp1", NULL), + CLK(spi3, "spi3", NULL), + CLK(msp1, "msp1", NULL), /* Peripheral Cluster #2 */ - CLK(gpio1_v1, "gpio.6", NULL), - CLK(gpio1_v1, "gpio.7", NULL), - CLK(ssitx_v1, "ssitx", NULL), - CLK(ssirx_v1, "ssirx", NULL), - CLK(spi0_v1, "spi0", NULL), - CLK(sdi3_v1, "sdi3", NULL), - CLK(sdi1_v1, "sdi1", NULL), - CLK(msp2_v1, "msp2", NULL), - CLK(sdi4_v1, "sdi4", NULL), - CLK(pwl_v1, "pwl", NULL), - CLK(spi1_v1, "spi1", NULL), - CLK(spi2_v1, "spi2", NULL), - CLK(i2c3_v1, "nmk-i2c.3", NULL), + CLK(gpio1, "gpio.6", NULL), + CLK(gpio1, "gpio.7", NULL), + CLK(ssitx, "ssitx", NULL), + CLK(ssirx, "ssirx", NULL), + CLK(spi0, "spi0", NULL), + CLK(sdi3, "sdi3", NULL), + CLK(sdi1, "sdi1", NULL), + CLK(msp2, "msp2", NULL), + CLK(sdi4, "sdi4", NULL), + CLK(pwl, "pwl", NULL), + CLK(spi1, "spi1", NULL), + CLK(spi2, "spi2", NULL), + CLK(i2c3, "nmk-i2c.3", NULL), /* Peripheral Cluster #3 */ - CLK(ssp1_v1, "ssp1", NULL), - CLK(ssp0_v1, "ssp0", NULL), + CLK(ssp1, "ssp1", NULL), + CLK(ssp0, "ssp0", NULL), /* Peripheral Cluster #5 */ - CLK(usb_v1, "musb-ux500.0", "usb"), + CLK(usb, "musb-ux500.0", "usb"), /* Peripheral Cluster #6 */ - CLK(mtu1_v1, "mtu1", NULL), - CLK(mtu0_v1, "mtu0", NULL), - CLK(cfgreg_v1, "cfgreg", NULL), + CLK(mtu1, "mtu1", NULL), + CLK(mtu0, "mtu0", NULL), + CLK(cfgreg, "cfgreg", NULL), CLK(hash1, "hash1", NULL), - CLK(unipro_v1, "unipro", NULL), - CLK(rng_v1, "rng", NULL), + CLK(unipro, "unipro", NULL), + CLK(rng, "rng", NULL), /* PRCMU level clock gating */ @@ -743,7 +651,7 @@ err_out: late_initcall(clk_debugfs_init); #endif /* defined(CONFIG_DEBUG_FS) */ -unsigned long clk_smp_twd_rate = 400000000; +unsigned long clk_smp_twd_rate = 500000000; unsigned long clk_smp_twd_get_rate(struct clk *clk) { @@ -769,7 +677,7 @@ static int clk_twd_cpufreq_transition(struct notifier_block *nb, if (state == CPUFREQ_PRECHANGE) { /* Save frequency in simple Hz */ - clk_smp_twd_rate = f->new * 1000; + clk_smp_twd_rate = (f->new * 1000) / 2; } return NOTIFY_OK; @@ -790,11 +698,7 @@ late_initcall(clk_init_smp_twd_cpufreq); int __init clk_init(void) { - if (cpu_is_u8500ed()) { - clk_prcmu_ops.enable = clk_prcmu_ed_enable; - clk_prcmu_ops.disable = clk_prcmu_ed_disable; - clk_per6clk.rate = 100000000; - } else if (cpu_is_u5500()) { + if (cpu_is_u5500()) { /* Clock tree for U5500 not implemented yet */ clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; @@ -802,20 +706,11 @@ int __init clk_init(void) clk_sdmmcclk.rate = 99900000; } - clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); - if (cpu_is_u8500ed()) - clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks)); - else - clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); - + clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); clkdev_add(&clk_smp_twd_lookup); #ifdef CONFIG_DEBUG_FS - clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); - if (cpu_is_u8500ed()) - clk_debugfs_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks)); - else - clk_debugfs_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); + clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); #endif return 0; } diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c index 22705d246fc7..18aa5c05c69e 100644 --- a/arch/arm/mach-ux500/cpu-db5500.c +++ b/arch/arm/mach-ux500/cpu-db5500.c @@ -13,7 +13,7 @@ #include <asm/mach/map.h> #include <asm/pmu.h> -#include <plat/gpio.h> +#include <plat/gpio-nomadik.h> #include <mach/hardware.h> #include <mach/devices.h> @@ -30,12 +30,11 @@ static struct map_desc u5500_uart_io_desc[] __initdata = { }; static struct map_desc u5500_io_desc[] __initdata = { - __IO_DEV_DESC(U5500_GIC_CPU_BASE, SZ_4K), + /* SCU base also covers GIC CPU BASE and TWD with its 4K page */ + __IO_DEV_DESC(U5500_SCU_BASE, SZ_4K), __IO_DEV_DESC(U5500_GIC_DIST_BASE, SZ_4K), __IO_DEV_DESC(U5500_L2CC_BASE, SZ_4K), - __IO_DEV_DESC(U5500_TWD_BASE, SZ_4K), __IO_DEV_DESC(U5500_MTU0_BASE, SZ_4K), - __IO_DEV_DESC(U5500_SCU_BASE, SZ_4K), __IO_DEV_DESC(U5500_BACKUPRAM0_BASE, SZ_8K), __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K), @@ -47,26 +46,6 @@ static struct map_desc u5500_io_desc[] __initdata = { __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K), }; -static struct resource db5500_pmu_resources[] = { - [0] = { - .start = IRQ_DB5500_PMU0, - .end = IRQ_DB5500_PMU0, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = IRQ_DB5500_PMU1, - .end = IRQ_DB5500_PMU1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device db5500_pmu_device = { - .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, - .num_resources = ARRAY_SIZE(db5500_pmu_resources), - .resource = db5500_pmu_resources, -}; - static struct resource mbox0_resources[] = { { .name = "mbox_peer", @@ -152,7 +131,6 @@ static struct platform_device mbox2_device = { }; static struct platform_device *db5500_platform_devs[] __initdata = { - &db5500_pmu_device, &mbox0_device, &mbox1_device, &mbox2_device, @@ -193,6 +171,25 @@ void __init u5500_map_io(void) _PRCMU_BASE = __io_address(U5500_PRCMU_BASE); } +static void __init db5500_pmu_init(void) +{ + struct resource res[] = { + [0] = { + .start = IRQ_DB5500_PMU0, + .end = IRQ_DB5500_PMU0, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = IRQ_DB5500_PMU1, + .end = IRQ_DB5500_PMU1, + .flags = IORESOURCE_IRQ, + }, + }; + + platform_device_register_simple("arm-pmu", ARM_PMU_DEVICE_CPU, + res, ARRAY_SIZE(res)); +} + static int usb_db5500_rx_dma_cfg[] = { DB5500_DMA_DEV4_USB_OTG_IEP_1_9, DB5500_DMA_DEV5_USB_OTG_IEP_2_10, @@ -218,6 +215,7 @@ static int usb_db5500_tx_dma_cfg[] = { void __init u5500_init_devices(void) { db5500_add_gpios(); + db5500_pmu_init(); db5500_dma_init(); db5500_add_rtc(); db5500_add_usb(usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg); diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 4598b06c8c55..7176ee7491ab 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008-2009 ST-Ericsson + * Copyright (C) 2008-2009 ST-Ericsson SA * * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> * @@ -14,12 +14,12 @@ #include <linux/amba/bus.h> #include <linux/interrupt.h> #include <linux/irq.h> -#include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/io.h> #include <asm/mach/map.h> #include <asm/pmu.h> +#include <plat/gpio-nomadik.h> #include <mach/hardware.h> #include <mach/setup.h> #include <mach/devices.h> @@ -35,12 +35,11 @@ static struct map_desc u8500_uart_io_desc[] __initdata = { }; static struct map_desc u8500_io_desc[] __initdata = { - __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K), + /* SCU base also covers GIC CPU BASE and TWD with its 4K page */ + __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K), __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K), - __IO_DEV_DESC(U8500_TWD_BASE, SZ_4K), __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), - __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K), __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K), __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K), @@ -54,19 +53,6 @@ static struct map_desc u8500_io_desc[] __initdata = { __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), -}; - -static struct map_desc u8500_ed_io_desc[] __initdata = { - __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K), - __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K), -}; - -static struct map_desc u8500_v1_io_desc[] __initdata = { - __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), - __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K), -}; - -static struct map_desc u8500_v2_io_desc[] __initdata = { __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), }; @@ -81,13 +67,6 @@ void __init u8500_map_io(void) iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); - if (cpu_is_u8500ed()) - iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc)); - else if (cpu_is_u8500v1()) - iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc)); - else if (cpu_is_u8500v2()) - iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc)); - _PRCMU_BASE = __io_address(U8500_PRCMU_BASE); } @@ -156,12 +135,9 @@ static resource_size_t __initdata db8500_gpio_base[] = { static void __init db8500_add_gpios(void) { struct nmk_gpio_platform_data pdata = { - /* No custom data yet */ + .supports_sleepmode = true, }; - if (cpu_is_u8500v2()) - pdata.supports_sleepmode = true; - dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base), IRQ_DB8500_GPIO0, &pdata); } @@ -193,9 +169,6 @@ static int usb_db8500_tx_dma_cfg[] = { */ void __init u8500_init_devices(void) { - if (cpu_is_u8500ed()) - dma40_u8500ed_fixup(); - db8500_add_rtc(); db8500_add_gpios(); db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 1da23bb87c16..f41857494375 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -10,14 +10,12 @@ #include <linux/clk.h> #include <linux/mfd/db8500-prcmu.h> #include <linux/mfd/db5500-prcmu.h> +#include <linux/clksrc-dbx500-prcmu.h> -#include <asm/cacheflush.h> -#include <asm/hardware/cache-l2x0.h> #include <asm/hardware/gic.h> #include <asm/mach/map.h> #include <asm/localtimer.h> -#include <plat/mtu.h> #include <mach/hardware.h> #include <mach/setup.h> #include <mach/devices.h> @@ -26,10 +24,6 @@ void __iomem *_PRCMU_BASE; -#ifdef CONFIG_CACHE_L2X0 -static void __iomem *l2x0_base; -#endif - void __init ux500_init_irq(void) { void __iomem *dist_base; @@ -53,96 +47,6 @@ void __init ux500_init_irq(void) if (cpu_is_u5500()) db5500_prcmu_early_init(); if (cpu_is_u8500()) - prcmu_early_init(); + db8500_prcmu_early_init(); clk_init(); } - -#ifdef CONFIG_CACHE_L2X0 -static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask) -{ - /* wait for the operation to complete */ - while (readl_relaxed(reg) & mask) - ; -} - -static inline void ux500_cache_sync(void) -{ - void __iomem *base = l2x0_base; - - writel_relaxed(0, base + L2X0_CACHE_SYNC); - ux500_cache_wait(base + L2X0_CACHE_SYNC, 1); -} - -/* - * The L2 cache cannot be turned off in the non-secure world. - * Dummy until a secure service is in place. - */ -static void ux500_l2x0_disable(void) -{ -} - -/* - * This is only called when doing a kexec, just after turning off the L2 - * and L1 cache, and it is surrounded by a spinlock in the generic version. - * However, we're not really turning off the L2 cache right now and the - * PL310 does not support exclusive accesses (used to implement the spinlock). - * So, the invalidation needs to be done without the spinlock. - */ -static void ux500_l2x0_inv_all(void) -{ - void __iomem *base = l2x0_base; - uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */ - - /* invalidate all ways */ - writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY); - ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask); - ux500_cache_sync(); -} - -static int ux500_l2x0_init(void) -{ - if (cpu_is_u5500()) - l2x0_base = __io_address(U5500_L2CC_BASE); - else if (cpu_is_u8500()) - l2x0_base = __io_address(U8500_L2CC_BASE); - else - ux500_unknown_soc(); - - /* 64KB way size, 8 way associativity, force WA */ - l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); - - /* Override invalidate function */ - outer_cache.disable = ux500_l2x0_disable; - outer_cache.inv_all = ux500_l2x0_inv_all; - - return 0; -} -early_initcall(ux500_l2x0_init); -#endif - -static void __init ux500_timer_init(void) -{ -#ifdef CONFIG_LOCAL_TIMERS - /* Setup the local timer base */ - if (cpu_is_u5500()) - twd_base = __io_address(U5500_TWD_BASE); - else if (cpu_is_u8500()) - twd_base = __io_address(U8500_TWD_BASE); - else - ux500_unknown_soc(); -#endif - if (cpu_is_u5500()) - mtu_base = __io_address(U5500_MTU0_BASE); - else if (cpu_is_u8500ed()) - mtu_base = __io_address(U8500_MTU0_BASE_ED); - else if (cpu_is_u8500()) - mtu_base = __io_address(U8500_MTU0_BASE); - else - ux500_unknown_soc(); - - nmdk_timer_init(); -} - -struct sys_timer ux500_timer = { - .init = ux500_timer_init, -}; diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c index 13a4ce046ae5..c563e5418d80 100644 --- a/arch/arm/mach-ux500/devices-common.c +++ b/arch/arm/mach-ux500/devices-common.c @@ -13,7 +13,7 @@ #include <linux/platform_device.h> #include <linux/amba/bus.h> -#include <plat/gpio.h> +#include <plat/gpio-nomadik.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 73b17404b194..a7c6cdc9b11e 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -166,16 +166,6 @@ struct platform_device u8500_dma40_device = { .resource = dma40_resources }; -void dma40_u8500ed_fixup(void) -{ - dma40_plat_data.memcpy = NULL; - dma40_plat_data.memcpy_len = 0; - dma40_resources[0].start = U8500_DMA_BASE_ED; - dma40_resources[0].end = U8500_DMA_BASE_ED + SZ_4K - 1; - dma40_resources[1].start = U8500_DMA_LCPA_BASE_ED; - dma40_resources[1].end = U8500_DMA_LCPA_BASE_ED + 2 * SZ_1K - 1; -} - struct resource keypad_resources[] = { [0] = { .start = U8500_SKE_BASE, diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c index dd8037ebccf8..572015e57cd9 100644 --- a/arch/arm/mach-ux500/hotplug.c +++ b/arch/arm/mach-ux500/hotplug.c @@ -24,7 +24,7 @@ static inline void platform_do_lowpower(unsigned int cpu) for (;;) { __asm__ __volatile__("dsb\n\t" "wfi\n\t" : : : "memory"); - if (pen_release == cpu) { + if (pen_release == cpu_logical_map(cpu)) { /* * OK, proper wakeup, we're done */ diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c index d35122ebc67b..15a0f63b2e2b 100644 --- a/arch/arm/mach-ux500/id.c +++ b/arch/arm/mach-ux500/id.c @@ -65,6 +65,7 @@ static unsigned int partnumber(unsigned int asicid) * DB8500v1 0x411fc091 0x9001FFF4 0x008500A0 * DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1 * DB8500v2 0x412fc091 0x9001DBF4 0x008500B0 + * DB8520v2.2 0x412fc091 0x9001DBF4 0x008500B2 * DB5500v1 0x412fc091 0x9001FFF4 0x005500A0 */ @@ -80,9 +81,10 @@ void __init ux500_map_io(void) addr = 0x9001FFF4; break; - case 0x412fc091: /* DB8500v2 / DB5500v1 */ + case 0x412fc091: /* DB8520 / DB8500v2 / DB5500v1 */ asicid = ux500_read_asicid(0x9001DBF4); - if (partnumber(asicid) == 0x8500) + if (partnumber(asicid) == 0x8500 || + partnumber(asicid) == 0x8520) /* DB8500v2 */ break; diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h index 6ad983294103..8e714bcb099f 100644 --- a/arch/arm/mach-ux500/include/mach/db5500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h @@ -61,10 +61,15 @@ #define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000) #define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000) #define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000) +#define U5500_PRCMU_TIMER_3_BASE (U5500_PER4_BASE + 0x07338) +#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450) #define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) #define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) +#define U5500_MTIMER_BASE (U5500_PER4_BASE + 0xC000) #define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) #define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000) +#define U5500_PRCMU_TCPM_BASE (U5500_PER4_BASE + 0x10000) +#define U5500_TPIU_BASE (U5500_PER4_BASE + 0x50000) #define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000) #define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000) @@ -123,6 +128,7 @@ #define U5500_ACCCON_BASE (0xBFFF1000) #define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020) #define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC) +#define U5500_INTCON_MBOX1_INT_RESET_ADDR (0xBFFD31A4) #define U5500_ESRAM_BASE 0x40000000 #define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000 diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h index 049997109cf9..80e10f50282e 100644 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h @@ -22,7 +22,9 @@ #define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000 #define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET) -#define U8500_DMA_LCPA_BASE_ED (U8500_ESRAM_BANK4 + 0x4000) + +/* This address fulfills the 256k alignment requirement of the lcla base */ +#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4 #define U8500_PER3_BASE 0x80000000 #define U8500_STM_BASE 0x80100000 @@ -40,15 +42,14 @@ #define U8500_ASIC_ID_BASE 0x9001D000 #define U8500_PER6_BASE 0xa03c0000 +#define U8500_PER7_BASE 0xa03d0000 #define U8500_PER5_BASE 0xa03e0000 -#define U8500_PER7_BASE_ED 0xa03d0000 #define U8500_SVA_BASE 0xa0100000 #define U8500_SIA_BASE 0xa0200000 #define U8500_SGA_BASE 0xa0300000 #define U8500_MCDE_BASE 0xa0350000 -#define U8500_DMA_BASE_ED 0xa0362000 #define U8500_DMA_BASE 0x801C0000 /* v1 */ #define U8500_SBAG_BASE 0xa0390000 @@ -66,13 +67,6 @@ #define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) #define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) -/* per7 base addresses */ -#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000) -#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000) -#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000) -#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000) -#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE_ED + 0xf000) - #define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) #define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) @@ -102,9 +96,10 @@ #define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) #define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) -#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000) #define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) #define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) +#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338) +#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450) /* per3 base addresses */ #define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S index 700fb05ee815..8d74d927d4e2 100644 --- a/arch/arm/mach-ux500/include/mach/debug-macro.S +++ b/arch/arm/mach-ux500/include/mach/debug-macro.S @@ -35,7 +35,7 @@ #define UX500_UART(n) __UX500_UART(n) #define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART) - .macro addruart, rp, rv + .macro addruart, rp, rv, tmp ldr \rp, =UART_BASE @ no, physical address ldr \rv, =IO_ADDRESS(UART_BASE) @ yes, virtual address .endm diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h index 020b6369a30a..5f6cb71fc62d 100644 --- a/arch/arm/mach-ux500/include/mach/devices.h +++ b/arch/arm/mach-ux500/include/mach/devices.h @@ -18,6 +18,4 @@ extern struct amba_device ux500_pl031_device; extern struct platform_device u8500_dma40_device; extern struct platform_device ux500_ske_keypad_device; -void dma40_u8500ed_fixup(void); - #endif diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S index 071bba94f727..e16299e1020a 100644 --- a/arch/arm/mach-ux500/include/mach/entry-macro.S +++ b/arch/arm/mach-ux500/include/mach/entry-macro.S @@ -10,8 +10,6 @@ * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include <mach/hardware.h> -#include <asm/hardware/entry-macro-gic.S> .macro disable_fiq .endm diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h index 3c4cd31ad9f7..c01ef66537f3 100644 --- a/arch/arm/mach-ux500/include/mach/gpio.h +++ b/arch/arm/mach-ux500/include/mach/gpio.h @@ -1,12 +1,5 @@ #ifndef __ASM_ARCH_GPIO_H #define __ASM_ARCH_GPIO_H -/* - * 288 (#267 is the highest one actually hooked up) onchip GPIOs, plus enough - * room for a couple of GPIO expanders. - */ -#define ARCH_NR_GPIOS 350 - -#include <plat/gpio.h> #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h index 470ac52663d6..b6ba26a1367d 100644 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ b/arch/arm/mach-ux500/include/mach/hardware.h @@ -10,20 +10,21 @@ #ifndef __MACH_HARDWARE_H #define __MACH_HARDWARE_H -/* macros to get at IO space when running virtually +/* + * Macros to get at IO space when running virtually * We dont map all the peripherals, let ioremap do * this for us. We map only very basic peripherals here. */ #define U8500_IO_VIRTUAL 0xf0000000 #define U8500_IO_PHYSICAL 0xa0000000 -/* this macro is used in assembly, so no cast */ +/* This macro is used in assembly, so no cast */ #define IO_ADDRESS(x) \ (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL) /* typesafe io address */ #define __io_address(n) __io(IO_ADDRESS(n)) -/* used by some plat-nomadik code */ +/* Used by some plat-nomadik code */ #define io_p2v(n) __io_address(n) #include <mach/db8500-regs.h> @@ -36,6 +37,5 @@ extern void __iomem *_PRCMU_BASE; #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) -#endif - +#endif /* __ASSEMBLY__ */ #endif /* __MACH_HARDWARE_H */ diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h index 02b541a37ee5..833d6a6edc9b 100644 --- a/arch/arm/mach-ux500/include/mach/id.h +++ b/arch/arm/mach-ux500/include/mach/id.h @@ -47,6 +47,30 @@ static inline bool __attribute_const__ cpu_is_u5500(void) } /* + * 5500 revisions + */ + +static inline bool __attribute_const__ cpu_is_u5500v1(void) +{ + return cpu_is_u5500() && (dbx500_revision() & 0xf0) == 0xA0; +} + +static inline bool __attribute_const__ cpu_is_u5500v2(void) +{ + return (dbx500_id.revision & 0xf0) == 0xB0; +} + +static inline bool __attribute_const__ cpu_is_u5500v20(void) +{ + return cpu_is_u5500() && ((dbx500_revision() & 0xf0) == 0xB0); +} + +static inline bool __attribute_const__ cpu_is_u5500v21(void) +{ + return cpu_is_u5500() && (dbx500_revision() == 0xB1); +} + +/* * 8500 revisions */ diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h index 47969909836c..d2d4131435a6 100644 --- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h +++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h @@ -9,7 +9,7 @@ #define __MACH_IRQS_BOARD_MOP500_H /* Number of AB8500 irqs is taken from header file */ -#include <linux/mfd/ab8500.h> +#include <linux/mfd/abx500/ab8500.h> #define MOP500_AB8500_IRQ_BASE IRQ_BOARD_START #define MOP500_AB8500_IRQ_END (MOP500_AB8500_IRQ_BASE \ diff --git a/arch/arm/mach-ux500/include/mach/memory.h b/arch/arm/mach-ux500/include/mach/memory.h deleted file mode 100644 index 2ef697a67006..000000000000 --- a/arch/arm/mach-ux500/include/mach/memory.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Physical DRAM offset. - */ -#define PLAT_PHYS_OFFSET UL(0x00000000) -#define BUS_OFFSET UL(0x00000000) - -#endif diff --git a/arch/arm/mach-ux500/include/mach/system.h b/arch/arm/mach-ux500/include/mach/system.h index c0cd8006f1a2..258e5c919c24 100644 --- a/arch/arm/mach-ux500/include/mach/system.h +++ b/arch/arm/mach-ux500/include/mach/system.h @@ -17,9 +17,4 @@ static inline void arch_idle(void) cpu_do_idle(); } -static inline void arch_reset(char mode, const char *cmd) -{ - /* yet to be implemented - TODO */ -} - #endif diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h index 7dd08074c37b..6fb3c4b0105d 100644 --- a/arch/arm/mach-ux500/include/mach/uncompress.h +++ b/arch/arm/mach-ux500/include/mach/uncompress.h @@ -51,15 +51,9 @@ static void flush(void) static inline void arch_decomp_setup(void) { /* Check in run time if we run on an U8500 or U5500 */ - if (machine_is_u8500() || - machine_is_svp8500v1() || - machine_is_svp8500v2() || - machine_is_hrefv60() || - machine_is_snowball()) - ux500_uart_base = U8500_UART2_BASE; - else if (machine_is_u5500()) + if (machine_is_u5500()) ux500_uart_base = U5500_UART0_BASE; - else /* not much can be done to help here */ + else ux500_uart_base = U8500_UART2_BASE; } diff --git a/arch/arm/mach-ux500/include/mach/vmalloc.h b/arch/arm/mach-ux500/include/mach/vmalloc.h deleted file mode 100644 index a4945cb41172..000000000000 --- a/arch/arm/mach-ux500/include/mach/vmalloc.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define VMALLOC_END 0xf0000000UL diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h index f923764ee16c..8b1d1a7a679e 100644 --- a/arch/arm/mach-ux500/pins-db8500.h +++ b/arch/arm/mach-ux500/pins-db8500.h @@ -35,40 +35,40 @@ #define GPIO4_GPIO PIN_CFG(4, GPIO) #define GPIO4_U1_RXD PIN_CFG(4, ALT_A) -#define GPIO4_I2C4_SCL PIN_CFG_PULL(4, ALT_B, UP) +#define GPIO4_I2C4_SCL PIN_CFG_INPUT(4, ALT_B, PULLUP) #define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C) #define GPIO5_GPIO PIN_CFG(5, GPIO) #define GPIO5_U1_TXD PIN_CFG(5, ALT_A) -#define GPIO5_I2C4_SDA PIN_CFG_PULL(5, ALT_B, UP) +#define GPIO5_I2C4_SDA PIN_CFG_INPUT(5, ALT_B, PULLUP) #define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C) #define GPIO6_GPIO PIN_CFG(6, GPIO) #define GPIO6_U1_CTSn PIN_CFG(6, ALT_A) -#define GPIO6_I2C1_SCL PIN_CFG_PULL(6, ALT_B, UP) +#define GPIO6_I2C1_SCL PIN_CFG_INPUT(6, ALT_B, PULLUP) #define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C) #define GPIO7_GPIO PIN_CFG(7, GPIO) #define GPIO7_U1_RTSn PIN_CFG(7, ALT_A) -#define GPIO7_I2C1_SDA PIN_CFG_PULL(7, ALT_B, UP) +#define GPIO7_I2C1_SDA PIN_CFG_INPUT(7, ALT_B, PULLUP) #define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C) #define GPIO8_GPIO PIN_CFG(8, GPIO) -#define GPIO8_IPI2C_SDA PIN_CFG_PULL(8, ALT_A, UP) -#define GPIO8_I2C2_SDA PIN_CFG_PULL(8, ALT_B, UP) +#define GPIO8_IPI2C_SDA PIN_CFG_INPUT(8, ALT_A, PULLUP) +#define GPIO8_I2C2_SDA PIN_CFG_INPUT(8, ALT_B, PULLUP) #define GPIO9_GPIO PIN_CFG(9, GPIO) -#define GPIO9_IPI2C_SCL PIN_CFG_PULL(9, ALT_A, UP) -#define GPIO9_I2C2_SCL PIN_CFG_PULL(9, ALT_B, UP) +#define GPIO9_IPI2C_SCL PIN_CFG_INPUT(9, ALT_A, PULLUP) +#define GPIO9_I2C2_SCL PIN_CFG_INPUT(9, ALT_B, PULLUP) #define GPIO10_GPIO PIN_CFG(10, GPIO) -#define GPIO10_IPI2C_SDA PIN_CFG_PULL(10, ALT_A, UP) -#define GPIO10_I2C2_SDA PIN_CFG_PULL(10, ALT_B, UP) +#define GPIO10_IPI2C_SDA PIN_CFG_INPUT(10, ALT_A, PULLUP) +#define GPIO10_I2C2_SDA PIN_CFG_INPUT(10, ALT_B, PULLUP) #define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C) #define GPIO11_GPIO PIN_CFG(11, GPIO) -#define GPIO11_IPI2C_SCL PIN_CFG_PULL(11, ALT_A, UP) -#define GPIO11_I2C2_SCL PIN_CFG_PULL(11, ALT_B, UP) +#define GPIO11_IPI2C_SCL PIN_CFG_INPUT(11, ALT_A, PULLUP) +#define GPIO11_I2C2_SCL PIN_CFG_INPUT(11, ALT_B, PULLUP) #define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C) #define GPIO12_GPIO PIN_CFG(12, GPIO) @@ -87,66 +87,66 @@ #define GPIO16_GPIO PIN_CFG(16, GPIO) #define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A) -#define GPIO16_I2C1_SCL PIN_CFG_PULL(16, ALT_B, UP) +#define GPIO16_I2C1_SCL PIN_CFG_INPUT(16, ALT_B, PULLUP) #define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C) #define GPIO17_GPIO PIN_CFG(17, GPIO) #define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A) -#define GPIO17_I2C1_SDA PIN_CFG_PULL(17, ALT_B, UP) +#define GPIO17_I2C1_SDA PIN_CFG_INPUT(17, ALT_B, PULLUP) #define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) #define GPIO18_GPIO PIN_CFG(18, GPIO) -#define GPIO18_MC0_CMDDIR PIN_CFG_PULL(18, ALT_A, UP) +#define GPIO18_MC0_CMDDIR PIN_CFG_INPUT(18, ALT_A, PULLUP) #define GPIO18_U2_RXD PIN_CFG(18, ALT_B) #define GPIO18_MS_IEP PIN_CFG(18, ALT_C) #define GPIO19_GPIO PIN_CFG(19, GPIO) -#define GPIO19_MC0_DAT0DIR PIN_CFG_PULL(19, ALT_A, UP) +#define GPIO19_MC0_DAT0DIR PIN_CFG_INPUT(19, ALT_A, PULLUP) #define GPIO19_U2_TXD PIN_CFG(19, ALT_B) #define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C) #define GPIO20_GPIO PIN_CFG(20, GPIO) -#define GPIO20_MC0_DAT2DIR PIN_CFG_PULL(20, ALT_A, UP) +#define GPIO20_MC0_DAT2DIR PIN_CFG_INPUT(20, ALT_A, PULLUP) #define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B) #define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C) #define GPIO21_GPIO PIN_CFG(21, GPIO) -#define GPIO21_MC0_DAT31DIR PIN_CFG_PULL(21, ALT_A, UP) +#define GPIO21_MC0_DAT31DIR PIN_CFG_INPUT(21, ALT_A, PULLUP) #define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B) #define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C) #define GPIO22_GPIO PIN_CFG(22, GPIO) -#define GPIO22_MC0_FBCLK PIN_CFG_PULL(22, ALT_A, UP) +#define GPIO22_MC0_FBCLK PIN_CFG_INPUT(22, ALT_A, PULLUP) #define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B) #define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C) #define GPIO23_GPIO PIN_CFG(23, GPIO) -#define GPIO23_MC0_CLK PIN_CFG_PULL(23, ALT_A, UP) +#define GPIO23_MC0_CLK PIN_CFG_INPUT(23, ALT_A, PULLUP) #define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B) #define GPIO23_MS_CLK PIN_CFG(23, ALT_C) #define GPIO24_GPIO PIN_CFG(24, GPIO) -#define GPIO24_MC0_CMD PIN_CFG_PULL(24, ALT_A, UP) +#define GPIO24_MC0_CMD PIN_CFG_INPUT(24, ALT_A, PULLUP) #define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B) #define GPIO24_MS_BS PIN_CFG(24, ALT_C) #define GPIO25_GPIO PIN_CFG(25, GPIO) -#define GPIO25_MC0_DAT0 PIN_CFG_PULL(25, ALT_A, UP) +#define GPIO25_MC0_DAT0 PIN_CFG_INPUT(25, ALT_A, PULLUP) #define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B) #define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C) #define GPIO26_GPIO PIN_CFG(26, GPIO) -#define GPIO26_MC0_DAT1 PIN_CFG_PULL(26, ALT_A, UP) +#define GPIO26_MC0_DAT1 PIN_CFG_INPUT(26, ALT_A, PULLUP) #define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B) #define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C) #define GPIO27_GPIO PIN_CFG(27, GPIO) -#define GPIO27_MC0_DAT2 PIN_CFG_PULL(27, ALT_A, UP) +#define GPIO27_MC0_DAT2 PIN_CFG_INPUT(27, ALT_A, PULLUP) #define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B) #define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C) #define GPIO28_GPIO PIN_CFG(28, GPIO) -#define GPIO28_MC0_DAT3 PIN_CFG_PULL(28, ALT_A, UP) +#define GPIO28_MC0_DAT3 PIN_CFG_INPUT(28, ALT_A, PULLUP) #define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B) #define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C) @@ -357,48 +357,48 @@ #define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C) #define GPIO128_GPIO PIN_CFG(128, GPIO) -#define GPIO128_MC2_CLK PIN_CFG_PULL(128, ALT_A, UP) +#define GPIO128_MC2_CLK PIN_CFG_INPUT(128, ALT_A, PULLUP) #define GPIO128_SM_CKO PIN_CFG(128, ALT_B) #define GPIO129_GPIO PIN_CFG(129, GPIO) -#define GPIO129_MC2_CMD PIN_CFG_PULL(129, ALT_A, UP) +#define GPIO129_MC2_CMD PIN_CFG_INPUT(129, ALT_A, PULLUP) #define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B) #define GPIO130_GPIO PIN_CFG(130, GPIO) -#define GPIO130_MC2_FBCLK PIN_CFG_PULL(130, ALT_A, UP) +#define GPIO130_MC2_FBCLK PIN_CFG_INPUT(130, ALT_A, PULLUP) #define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B) #define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C) #define GPIO131_GPIO PIN_CFG(131, GPIO) -#define GPIO131_MC2_DAT0 PIN_CFG_PULL(131, ALT_A, UP) +#define GPIO131_MC2_DAT0 PIN_CFG_INPUT(131, ALT_A, PULLUP) #define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B) #define GPIO132_GPIO PIN_CFG(132, GPIO) -#define GPIO132_MC2_DAT1 PIN_CFG_PULL(132, ALT_A, UP) +#define GPIO132_MC2_DAT1 PIN_CFG_INPUT(132, ALT_A, PULLUP) #define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B) #define GPIO133_GPIO PIN_CFG(133, GPIO) -#define GPIO133_MC2_DAT2 PIN_CFG_PULL(133, ALT_A, UP) +#define GPIO133_MC2_DAT2 PIN_CFG_INPUT(133, ALT_A, PULLUP) #define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B) #define GPIO134_GPIO PIN_CFG(134, GPIO) -#define GPIO134_MC2_DAT3 PIN_CFG_PULL(134, ALT_A, UP) +#define GPIO134_MC2_DAT3 PIN_CFG_INPUT(134, ALT_A, PULLUP) #define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B) #define GPIO135_GPIO PIN_CFG(135, GPIO) -#define GPIO135_MC2_DAT4 PIN_CFG_PULL(135, ALT_A, UP) +#define GPIO135_MC2_DAT4 PIN_CFG_INPUT(135, ALT_A, PULLUP) #define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B) #define GPIO136_GPIO PIN_CFG(136, GPIO) -#define GPIO136_MC2_DAT5 PIN_CFG_PULL(136, ALT_A, UP) +#define GPIO136_MC2_DAT5 PIN_CFG_INPUT(136, ALT_A, PULLUP) #define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B) #define GPIO137_GPIO PIN_CFG(137, GPIO) -#define GPIO137_MC2_DAT6 PIN_CFG_PULL(137, ALT_A, UP) +#define GPIO137_MC2_DAT6 PIN_CFG_INPUT(137, ALT_A, PULLUP) #define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B) #define GPIO138_GPIO PIN_CFG(138, GPIO) -#define GPIO138_MC2_DAT7 PIN_CFG_PULL(138, ALT_A, UP) +#define GPIO138_MC2_DAT7 PIN_CFG_INPUT(138, ALT_A, PULLUP) #define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B) #define GPIO139_GPIO PIN_CFG(139, GPIO) @@ -434,10 +434,10 @@ #define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A) #define GPIO147_GPIO PIN_CFG(147, GPIO) -#define GPIO147_I2C0_SCL PIN_CFG_PULL(147, ALT_A, UP) +#define GPIO147_I2C0_SCL PIN_CFG_INPUT(147, ALT_A, PULLUP) #define GPIO148_GPIO PIN_CFG(148, GPIO) -#define GPIO148_I2C0_SDA PIN_CFG_PULL(148, ALT_A, UP) +#define GPIO148_I2C0_SDA PIN_CFG_INPUT(148, ALT_A, PULLUP) #define GPIO149_GPIO PIN_CFG(149, GPIO) #define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A) @@ -459,82 +459,82 @@ #define GPIO152_KP_O9 PIN_CFG(152, ALT_C) #define GPIO153_GPIO PIN_CFG(153, GPIO) -#define GPIO153_KP_I7 PIN_CFG_PULL(153, ALT_A, DOWN) +#define GPIO153_KP_I7 PIN_CFG_INPUT(153, ALT_A, PULLDOWN) #define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) #define GPIO153_U2_RXD PIN_CFG(153, ALT_C) #define GPIO154_GPIO PIN_CFG(154, GPIO) -#define GPIO154_KP_I6 PIN_CFG_PULL(154, ALT_A, DOWN) +#define GPIO154_KP_I6 PIN_CFG_INPUT(154, ALT_A, PULLDOWN) #define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) #define GPIO154_U2_TXD PIN_CFG(154, ALT_C) #define GPIO155_GPIO PIN_CFG(155, GPIO) -#define GPIO155_KP_I5 PIN_CFG_PULL(155, ALT_A, DOWN) +#define GPIO155_KP_I5 PIN_CFG_INPUT(155, ALT_A, PULLDOWN) #define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) #define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) #define GPIO156_GPIO PIN_CFG(156, GPIO) -#define GPIO156_KP_I4 PIN_CFG_PULL(156, ALT_A, DOWN) +#define GPIO156_KP_I4 PIN_CFG_INPUT(156, ALT_A, PULLDOWN) #define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) #define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) #define GPIO157_GPIO PIN_CFG(157, GPIO) -#define GPIO157_KP_O7 PIN_CFG_PULL(157, ALT_A, UP) +#define GPIO157_KP_O7 PIN_CFG_INPUT(157, ALT_A, PULLUP) #define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) #define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) #define GPIO158_GPIO PIN_CFG(158, GPIO) -#define GPIO158_KP_O6 PIN_CFG_PULL(158, ALT_A, UP) +#define GPIO158_KP_O6 PIN_CFG_INPUT(158, ALT_A, PULLUP) #define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) #define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) #define GPIO159_GPIO PIN_CFG(159, GPIO) -#define GPIO159_KP_O5 PIN_CFG_PULL(159, ALT_A, UP) +#define GPIO159_KP_O5 PIN_CFG_INPUT(159, ALT_A, PULLUP) #define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) #define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) #define GPIO160_GPIO PIN_CFG(160, GPIO) -#define GPIO160_KP_O4 PIN_CFG_PULL(160, ALT_A, UP) +#define GPIO160_KP_O4 PIN_CFG_INPUT(160, ALT_A, PULLUP) #define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) #define GPIO160_NONE PIN_CFG(160, ALT_C) #define GPIO161_GPIO PIN_CFG(161, GPIO) -#define GPIO161_KP_I3 PIN_CFG_PULL(161, ALT_A, DOWN) +#define GPIO161_KP_I3 PIN_CFG_INPUT(161, ALT_A, PULLDOWN) #define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) #define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) #define GPIO162_GPIO PIN_CFG(162, GPIO) -#define GPIO162_KP_I2 PIN_CFG_PULL(162, ALT_A, DOWN) +#define GPIO162_KP_I2 PIN_CFG_INPUT(162, ALT_A, PULLDOWN) #define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) #define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) #define GPIO163_GPIO PIN_CFG(163, GPIO) -#define GPIO163_KP_I1 PIN_CFG_PULL(163, ALT_A, DOWN) +#define GPIO163_KP_I1 PIN_CFG_INPUT(163, ALT_A, PULLDOWN) #define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) #define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) #define GPIO164_GPIO PIN_CFG(164, GPIO) -#define GPIO164_KP_I0 PIN_CFG_PULL(164, ALT_A, UP) +#define GPIO164_KP_I0 PIN_CFG_INPUT(164, ALT_A, PULLUP) #define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) #define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) #define GPIO165_GPIO PIN_CFG(165, GPIO) -#define GPIO165_KP_O3 PIN_CFG_PULL(165, ALT_A, UP) +#define GPIO165_KP_O3 PIN_CFG_INPUT(165, ALT_A, PULLUP) #define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) #define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) #define GPIO166_GPIO PIN_CFG(166, GPIO) -#define GPIO166_KP_O2 PIN_CFG_PULL(166, ALT_A, UP) +#define GPIO166_KP_O2 PIN_CFG_INPUT(166, ALT_A, PULLUP) #define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) #define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) #define GPIO167_GPIO PIN_CFG(167, GPIO) -#define GPIO167_KP_O1 PIN_CFG_PULL(167, ALT_A, UP) +#define GPIO167_KP_O1 PIN_CFG_INPUT(167, ALT_A, PULLUP) #define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) #define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) #define GPIO168_GPIO PIN_CFG(168, GPIO) -#define GPIO168_KP_O0 PIN_CFG_PULL(168, ALT_A, UP) +#define GPIO168_KP_O0 PIN_CFG_INPUT(168, ALT_A, PULLUP) #define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) #define GPIO168_NONE PIN_CFG(168, ALT_C) @@ -569,39 +569,39 @@ #define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A) #define GPIO197_GPIO PIN_CFG(197, GPIO) -#define GPIO197_MC4_DAT3 PIN_CFG_PULL(197, ALT_A, UP) +#define GPIO197_MC4_DAT3 PIN_CFG_INPUT(197, ALT_A, PULLUP) #define GPIO198_GPIO PIN_CFG(198, GPIO) -#define GPIO198_MC4_DAT2 PIN_CFG_PULL(198, ALT_A, UP) +#define GPIO198_MC4_DAT2 PIN_CFG_INPUT(198, ALT_A, PULLUP) #define GPIO199_GPIO PIN_CFG(199, GPIO) -#define GPIO199_MC4_DAT1 PIN_CFG_PULL(199, ALT_A, UP) +#define GPIO199_MC4_DAT1 PIN_CFG_INPUT(199, ALT_A, PULLUP) #define GPIO200_GPIO PIN_CFG(200, GPIO) -#define GPIO200_MC4_DAT0 PIN_CFG_PULL(200, ALT_A, UP) +#define GPIO200_MC4_DAT0 PIN_CFG_INPUT(200, ALT_A, PULLUP) #define GPIO201_GPIO PIN_CFG(201, GPIO) -#define GPIO201_MC4_CMD PIN_CFG_PULL(201, ALT_A, UP) +#define GPIO201_MC4_CMD PIN_CFG_INPUT(201, ALT_A, PULLUP) #define GPIO202_GPIO PIN_CFG(202, GPIO) -#define GPIO202_MC4_FBCLK PIN_CFG_PULL(202, ALT_A, UP) +#define GPIO202_MC4_FBCLK PIN_CFG_INPUT(202, ALT_A, PULLUP) #define GPIO202_PWL PIN_CFG(202, ALT_B) #define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C) #define GPIO203_GPIO PIN_CFG(203, GPIO) -#define GPIO203_MC4_CLK PIN_CFG_PULL(203, ALT_A, UP) +#define GPIO203_MC4_CLK PIN_CFG_INPUT(203, ALT_A, PULLUP) #define GPIO204_GPIO PIN_CFG(204, GPIO) -#define GPIO204_MC4_DAT7 PIN_CFG_PULL(204, ALT_A, UP) +#define GPIO204_MC4_DAT7 PIN_CFG_INPUT(204, ALT_A, PULLUP) #define GPIO205_GPIO PIN_CFG(205, GPIO) -#define GPIO205_MC4_DAT6 PIN_CFG_PULL(205, ALT_A, UP) +#define GPIO205_MC4_DAT6 PIN_CFG_INPUT(205, ALT_A, PULLUP) #define GPIO206_GPIO PIN_CFG(206, GPIO) -#define GPIO206_MC4_DAT5 PIN_CFG_PULL(206, ALT_A, UP) +#define GPIO206_MC4_DAT5 PIN_CFG_INPUT(206, ALT_A, PULLUP) #define GPIO207_GPIO PIN_CFG(207, GPIO) -#define GPIO207_MC4_DAT4 PIN_CFG_PULL(207, ALT_A, UP) +#define GPIO207_MC4_DAT4 PIN_CFG_INPUT(207, ALT_A, PULLUP) #define GPIO208_GPIO PIN_CFG(208, GPIO) #define GPIO208_MC1_CLK PIN_CFG(208, ALT_A) @@ -632,21 +632,25 @@ #define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A) #define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B) #define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C) +#define GPIO215_SPI2_TXD PIN_CFG(215, ALT_C) #define GPIO216_GPIO PIN_CFG(216, GPIO) #define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A) #define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B) -#define GPIO216_I2C3_SDA PIN_CFG_PULL(216, ALT_C, UP) +#define GPIO216_I2C3_SDA PIN_CFG_INPUT(216, ALT_C, PULLUP) +#define GPIO216_SPI2_FRM PIN_CFG(216, ALT_C) #define GPIO217_GPIO PIN_CFG(217, GPIO) #define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A) #define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B) #define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C) +#define GPIO217_SPI2_CLK PIN_CFG(217, ALT_C) #define GPIO218_GPIO PIN_CFG(218, GPIO) #define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A) #define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B) -#define GPIO218_I2C3_SCL PIN_CFG_PULL(218, ALT_C, UP) +#define GPIO218_I2C3_SCL PIN_CFG_INPUT(218, ALT_C, PULLUP) +#define GPIO218_SPI2_RXD PIN_CFG(218, ALT_C) #define GPIO219_GPIO PIN_CFG(219, GPIO) #define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A) @@ -694,12 +698,12 @@ #define GPIO229_GPIO PIN_CFG(229, GPIO) #define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A) #define GPIO229_PWL PIN_CFG(229, ALT_B) -#define GPIO229_I2C3_SDA PIN_CFG_PULL(229, ALT_C, UP) +#define GPIO229_I2C3_SDA PIN_CFG_INPUT(229, ALT_C, PULLUP) #define GPIO230_GPIO PIN_CFG(230, GPIO) #define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A) #define GPIO230_PWL PIN_CFG(230, ALT_B) -#define GPIO230_I2C3_SCL PIN_CFG_PULL(230, ALT_C, UP) +#define GPIO230_I2C3_SCL PIN_CFG_INPUT(230, ALT_C, PULLUP) #define GPIO256_GPIO PIN_CFG(256, GPIO) #define GPIO256_USB_NXT PIN_CFG(256, ALT_A) diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index a33df5f4c27a..a19e398dade3 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -96,7 +96,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * the holding pen - release it, then wait for it to flag * that it has been released by resetting pen_release. */ - write_pen_release(cpu); + write_pen_release(cpu_logical_map(cpu)); gic_raise_softirq(cpumask_of(cpu), 1); @@ -156,12 +156,10 @@ void __init smp_init_cpus(void) ncores = scu_base ? scu_get_core_count(scu_base) : 1; /* sanity check */ - if (ncores > NR_CPUS) { - printk(KERN_WARNING - "U8500: no. of cores (%d) greater than configured " - "maximum of %d - clipping\n", - ncores, NR_CPUS); - ncores = NR_CPUS; + if (ncores > nr_cpu_ids) { + pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", + ncores, nr_cpu_ids); + ncores = nr_cpu_ids; } for (i = 0; i < ncores; i++) diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c new file mode 100644 index 000000000000..aea467d04ff7 --- /dev/null +++ b/arch/arm/mach-ux500/timer.c @@ -0,0 +1,68 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * + * License Terms: GNU General Public License v2 + * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson + */ +#include <linux/io.h> +#include <linux/errno.h> +#include <linux/clksrc-dbx500-prcmu.h> + +#include <asm/localtimer.h> + +#include <plat/mtu.h> + +#include <mach/setup.h> +#include <mach/hardware.h> + +static void __init ux500_timer_init(void) +{ + void __iomem *prcmu_timer_base; + + if (cpu_is_u5500()) { +#ifdef CONFIG_LOCAL_TIMERS + twd_base = __io_address(U5500_TWD_BASE); +#endif + mtu_base = __io_address(U5500_MTU0_BASE); + prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE); + } else if (cpu_is_u8500()) { +#ifdef CONFIG_LOCAL_TIMERS + twd_base = __io_address(U8500_TWD_BASE); +#endif + mtu_base = __io_address(U8500_MTU0_BASE); + prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); + } else { + ux500_unknown_soc(); + } + + /* + * Here we register the timerblocks active in the system. + * Localtimers (twd) is started when both cpu is up and running. + * MTU register a clocksource, clockevent and sched_clock. + * Since the MTU is located in the VAPE power domain + * it will be cleared in sleep which makes it unsuitable. + * We however need it as a timer tick (clockevent) + * during boot to calibrate delay until twd is started. + * RTC-RTT have problems as timer tick during boot since it is + * depending on delay which is not yet calibrated. RTC-RTT is in the + * always-on powerdomain and is used as clockevent instead of twd when + * sleeping. + * The PRCMU timer 4(3 for DB5500) register a clocksource and + * sched_clock with higher rating then MTU since is always-on. + * + */ + + nmdk_timer_init(); + clksrc_dbx500_prcmu_init(prcmu_timer_base); +} + +static void ux500_timer_reset(void) +{ + nmdk_clkevt_reset(); + nmdk_clksrc_reset(); +} + +struct sys_timer ux500_timer = { + .init = ux500_timer_init, + .resume = ux500_timer_reset, +}; |
