diff options
Diffstat (limited to 'arch/arm/mach-omap2')
154 files changed, 17959 insertions, 5164 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index ab784bfde908..1a2cf6226a55 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -15,7 +15,7 @@ config ARCH_OMAP2PLUS_TYPICAL select SERIAL_OMAP_CONSOLE select I2C select I2C_OMAP - select MFD + select MFD_SUPPORT select MENELAUS if ARCH_OMAP2 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 @@ -35,6 +35,8 @@ config ARCH_OMAP3 select CPU_V7 select USB_ARCH_HAS_EHCI select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 + select ARCH_HAS_OPP + select PM_OPP if PM config ARCH_OMAP4 bool "TI OMAP4" @@ -44,6 +46,9 @@ config ARCH_OMAP4 select ARM_GIC select PL310_ERRATA_588369 select ARM_ERRATA_720789 + select ARCH_HAS_OPP + select PM_OPP if PM + select USB_ARCH_HAS_EHCI comment "OMAP Core Type" depends on ARCH_OMAP2 @@ -85,6 +90,12 @@ config OMAP_PACKAGE_CUS config OMAP_PACKAGE_CBP bool +config OMAP_PACKAGE_CBL + bool + +config OMAP_PACKAGE_CBS + bool + comment "OMAP Board Type" depends on ARCH_OMAP2PLUS @@ -128,7 +139,6 @@ config MACH_DEVKIT8000 depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CUS - select OMAP_MUX config MACH_OMAP_LDP bool "OMAP3 LDP board" @@ -174,11 +184,17 @@ config MACH_OMAP3517EVM default y select OMAP_PACKAGE_CBB +config MACH_CRANEBOARD + bool "AM3517/05 CRANE board" + depends on ARCH_OMAP3 + select OMAP_PACKAGE_CBB + config MACH_OMAP3_PANDORA bool "OMAP3 Pandora" depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CBB + select REGULATOR_FIXED_VOLTAGE config MACH_OMAP3_TOUCHBOOK bool "OMAP3 Touch Book" @@ -210,6 +226,12 @@ config MACH_NOKIA_N8X0 select MACH_NOKIA_N810 select MACH_NOKIA_N810_WIMAX +config MACH_NOKIA_RM680 + bool "Nokia RM-680 board" + depends on ARCH_OMAP3 + default y + select OMAP_PACKAGE_CBB + config MACH_NOKIA_RX51 bool "Nokia RX-51 board" depends on ARCH_OMAP3 @@ -224,6 +246,7 @@ config MACH_OMAP_ZOOM2 select SERIAL_8250 select SERIAL_CORE_CONSOLE select SERIAL_8250_CONSOLE + select REGULATOR_FIXED_VOLTAGE config MACH_OMAP_ZOOM3 bool "OMAP3630 Zoom3 board" @@ -233,20 +256,19 @@ config MACH_OMAP_ZOOM3 select SERIAL_8250 select SERIAL_CORE_CONSOLE select SERIAL_8250_CONSOLE + select REGULATOR_FIXED_VOLTAGE config MACH_CM_T35 bool "CompuLab CM-T35 module" depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CUS - select OMAP_MUX config MACH_CM_T3517 bool "CompuLab CM-T3517 module" depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CBB - select OMAP_MUX config MACH_IGEP0020 bool "IGEP v2 board" @@ -265,7 +287,6 @@ config MACH_SBC3530 depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CUS - select OMAP_MUX config MACH_OMAP_3630SDP bool "OMAP3630 SDP board" @@ -277,11 +298,15 @@ config MACH_OMAP_4430SDP bool "OMAP 4430 SDP board" default y depends on ARCH_OMAP4 + select OMAP_PACKAGE_CBL + select OMAP_PACKAGE_CBS config MACH_OMAP4_PANDA bool "OMAP4 Panda Board" default y depends on ARCH_OMAP4 + select OMAP_PACKAGE_CBL + select OMAP_PACKAGE_CBS config OMAP3_EMU bool "OMAP3 debugging peripherals" diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 60e51bcf53bd..cd7332f50b2d 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -4,30 +4,31 @@ # Common support obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \ - common.o + common.o gpio.o dma.o wd_timer.o -omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o +omap-2-3-common = irq.o sdrc.o hwmod-common = omap_hwmod.o \ omap_hwmod_common_data.o -prcm-common = prcm.o powerdomain.o clock-common = clock.o clock_common_data.o \ - clockdomain.o clkt_dpll.o \ - clkt_clksel.o + clkt_dpll.o clkt_clksel.o -obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) -obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) -obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) prm44xx.o $(hwmod-common) +obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) +obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) +obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o +obj-$(CONFIG_TWL4030_CORE) += omap_twl.o + # SMP support ONLY available for OMAP4 obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o -AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a -AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a +plus_sec := $(call as-instr,.arch_extension sec,+sec) +AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) +AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a$(plus_sec) # Functions loaded to SRAM obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o @@ -42,18 +43,29 @@ AFLAGS_sram34xx.o :=-Wa,-march=armv7-a obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o +obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o # SMS/SDRC obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o +# OPP table initialization +ifeq ($(CONFIG_PM_OPP),y) +obj-y += opp.o +obj-$(CONFIG_ARCH_OMAP3) += opp3xxx_data.o +obj-$(CONFIG_ARCH_OMAP4) += opp4xxx_data.o +endif + # Power Management ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o -obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o -obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o pm_bus.o -obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o +obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o voltage.o +obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o voltage.o \ + cpuidle34xx.o pm_bus.o +obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o voltage.o pm_bus.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o +obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o +obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a @@ -65,10 +77,36 @@ endif endif # PRCM -obj-$(CONFIG_ARCH_OMAP2) += cm.o -obj-$(CONFIG_ARCH_OMAP3) += cm.o -obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o - +obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o +obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o +# XXX The presence of cm2xxx_3xxx.o on the line below is temporary and +# will be removed once the OMAP4 part of the codebase is converted to +# use OMAP4-specific PRCM functions. +obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \ + cm44xx.o prcm_mpu44xx.o \ + prminst44xx.o + +# OMAP powerdomain framework +powerdomain-common += powerdomain.o powerdomain-common.o +obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common) \ + powerdomain2xxx_3xxx.o \ + powerdomains2xxx_data.o \ + powerdomains2xxx_3xxx_data.o +obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common) \ + powerdomain2xxx_3xxx.o \ + powerdomains3xxx_data.o \ + powerdomains2xxx_3xxx_data.o +obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \ + powerdomain44xx.o \ + powerdomains44xx_data.o + +# PRCM clockdomain control +obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \ + clockdomains2xxx_3xxx_data.o +obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \ + clockdomains2xxx_3xxx_data.o +obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \ + clockdomains44xx_data.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \ clkt2xxx_sys.o \ @@ -139,17 +177,20 @@ obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \ hsmmc.o \ board-flash.o obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o +obj-$(CONFIG_MACH_NOKIA_RM680) += board-rm680.o \ + sdram-nokia.o \ + hsmmc.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ - board-rx51-sdram.o \ + sdram-nokia.o \ board-rx51-peripherals.o \ board-rx51-video.o \ hsmmc.o -obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ +obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom.o \ board-zoom-peripherals.o \ board-flash.o \ hsmmc.o \ board-zoom-debugboard.o -obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom3.o \ +obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom.o \ board-zoom-peripherals.o \ board-flash.o \ hsmmc.o \ @@ -168,12 +209,16 @@ obj-$(CONFIG_MACH_IGEP0030) += board-igep0030.o \ obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ - hsmmc.o + hsmmc.o \ + omap_phy_internal.o obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \ - hsmmc.o + hsmmc.o \ + omap_phy_internal.o obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o +obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o + obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \ hsmmc.o # Platform specific device init code diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index b527f8d187ad..e0661777f599 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -135,7 +135,7 @@ static inline void board_smc91x_init(void) #endif -static struct omap_board_config_kernel sdp2430_config[] = { +static struct omap_board_config_kernel sdp2430_config[] __initdata = { {OMAP_TAG_LCD, &sdp2430_lcd_config}, }; @@ -143,9 +143,9 @@ static void __init omap_2430sdp_init_irq(void) { omap_board_config = sdp2430_config; omap_board_config_size = ARRAY_SIZE(sdp2430_config); - omap2_init_common_hw(NULL, NULL); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); omap_init_irq(); - omap_gpio_init(); } static struct twl4030_gpio_platform_data sdp2430_gpio_data = { @@ -218,8 +218,6 @@ static struct omap_usb_config sdp2430_usb_config __initdata = { static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif static void __init omap_2430sdp_init(void) diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 4e3742c512b8..3b39ef1a680a 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -326,9 +326,9 @@ static void __init omap_3430sdp_init_irq(void) omap_board_config = sdp3430_config; omap_board_config_size = ARRAY_SIZE(sdp3430_config); omap3_pm_init_cpuidle(omap3_cpuidle_params_table); - omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL); + omap2_init_common_infrastructure(); + omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL); omap_init_irq(); - omap_gpio_init(); } static int sdp3430_batt_table[] = { @@ -663,8 +663,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif /* diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index bbcf580fa097..5d41dbe059a3 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -73,18 +73,16 @@ static void __init omap_sdp_init_irq(void) { omap_board_config = sdp_config; omap_board_config_size = ARRAY_SIZE(sdp_config); - omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params, - h8mbx00u0mer0em_sdrc_params); + omap2_init_common_infrastructure(); + omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params, + h8mbx00u0mer0em_sdrc_params); omap_init_irq(); - omap_gpio_init(); } #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif /* diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index df5a425a49d1..a70bdf28e2bc 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -23,6 +23,7 @@ #include <linux/gpio_keys.h> #include <linux/regulator/machine.h> #include <linux/leds.h> +#include <linux/leds_pwm.h> #include <mach/hardware.h> #include <mach/omap4-common.h> @@ -35,6 +36,7 @@ #include <plat/usb.h> #include <plat/mmc.h> +#include "mux.h" #include "hsmmc.h" #include "timer-gp.h" #include "control.h" @@ -42,6 +44,7 @@ #define ETH_KS8851_IRQ 34 #define ETH_KS8851_POWER_ON 48 #define ETH_KS8851_QUART 138 +#define OMAP4SDP_MDM_PWR_EN_GPIO 157 #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 #define OMAP4_SFH7741_ENABLE_GPIO 188 @@ -96,6 +99,28 @@ static struct gpio_led_platform_data sdp4430_led_data = { .num_leds = ARRAY_SIZE(sdp4430_gpio_leds), }; +static struct led_pwm sdp4430_pwm_leds[] = { + { + .name = "omap4:green:chrg", + .pwm_id = 1, + .max_brightness = 255, + .pwm_period_ns = 7812500, + }, +}; + +static struct led_pwm_platform_data sdp4430_pwm_data = { + .num_leds = ARRAY_SIZE(sdp4430_pwm_leds), + .leds = sdp4430_pwm_leds, +}; + +static struct platform_device sdp4430_leds_pwm = { + .name = "leds_pwm", + .id = -1, + .dev = { + .platform_data = &sdp4430_pwm_data, + }, +}; + static int omap_prox_activate(struct device *dev) { gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1); @@ -203,6 +228,7 @@ static struct platform_device *sdp4430_devices[] __initdata = { &sdp4430_lcd_device, &sdp4430_gpio_keys_device, &sdp4430_leds_gpio, + &sdp4430_leds_pwm, }; static struct omap_lcd_config sdp4430_lcd_config __initdata = { @@ -217,20 +243,37 @@ static void __init omap_4430sdp_init_irq(void) { omap_board_config = sdp4430_config; omap_board_config_size = ARRAY_SIZE(sdp4430_config); - omap2_init_common_hw(NULL, NULL); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(1); #endif gic_init_irq(); - omap_gpio_init(); } +static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { + .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, + .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .phy_reset = false, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL, +}; + static struct omap_musb_board_data musb_board_data = { .interface_type = MUSB_INTERFACE_UTMI, - .mode = MUSB_PERIPHERAL, + .mode = MUSB_OTG, .power = 100, }; +static struct twl4030_usb_data omap4_usbphy_data = { + .phy_init = omap4430_phy_init, + .phy_exit = omap4430_phy_exit, + .phy_power = omap4430_phy_power, + .phy_set_clock = omap4430_phy_set_clk, +}; + static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, @@ -450,6 +493,7 @@ static struct twl4030_platform_data sdp4430_twldata = { .vaux1 = &sdp4430_vaux1, .vaux2 = &sdp4430_vaux2, .vaux3 = &sdp4430_vaux3, + .usb = &omap4_usbphy_data }; static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = { @@ -464,6 +508,9 @@ static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = { { I2C_BOARD_INFO("tmp105", 0x48), }, + { + I2C_BOARD_INFO("bh1780", 0x29), + }, }; static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = { { @@ -505,20 +552,37 @@ static void __init omap_sfh7741prox_init(void) } } +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + static void __init omap_4430sdp_init(void) { int status; + int package = OMAP_PACKAGE_CBS; + + if (omap_rev() == OMAP4430_REV_ES1_0) + package = OMAP_PACKAGE_CBL; + omap4_mux_init(board_mux, package); omap4_i2c_init(); omap_sfh7741prox_init(); platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); - /* OMAP4 SDP uses internal transceiver so register nop transceiver */ - usb_nop_xceiv_register(); - /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ - if (!cpu_is_omap44xx()) - usb_musb_init(&musb_board_data); + + /* Power on the ULPI PHY */ + if (gpio_is_valid(OMAP4SDP_MDM_PWR_EN_GPIO)) { + /* FIXME: Assumes pad is already muxed for GPIO mode */ + gpio_request(OMAP4SDP_MDM_PWR_EN_GPIO, "USBB1 PHY VMDM_3V3"); + gpio_direction_output(OMAP4SDP_MDM_PWR_EN_GPIO, 1); + } + usb_ehci_init(&ehci_pdata); + usb_musb_init(&musb_board_data); status = omap_ethernet_init(); if (status) { diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c new file mode 100644 index 000000000000..71acb5ab281c --- /dev/null +++ b/arch/arm/mach-omap2/board-am3517crane.c @@ -0,0 +1,116 @@ +/* + * Support for AM3517/05 Craneboard + * http://www.mistralsolutions.com/products/craneboard.php + * + * Copyright (C) 2010 Mistral Solutions Pvt Ltd. <www.mistralsolutions.com> + * Author: R.Srinath <srinath@mistralsolutions.com> + * + * Based on mach-omap2/board-am3517evm.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, + * whether express or implied; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/gpio.h> + +#include <mach/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <plat/board.h> +#include <plat/common.h> +#include <plat/usb.h> + +#include "mux.h" +#include "control.h" + +#define GPIO_USB_POWER 35 +#define GPIO_USB_NRESET 38 + + +/* Board initialization */ +static struct omap_board_config_kernel am3517_crane_config[] __initdata = { +}; + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + +static void __init am3517_crane_init_irq(void) +{ + omap_board_config = am3517_crane_config; + omap_board_config_size = ARRAY_SIZE(am3517_crane_config); + + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); + omap_init_irq(); +} + +static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { + .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, + .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + + .phy_reset = true, + .reset_gpio_port[0] = GPIO_USB_NRESET, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL +}; + +static void __init am3517_crane_init(void) +{ + int ret; + + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap_serial_init(); + + /* Configure GPIO for EHCI port */ + if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) { + pr_err("Can not configure mux for GPIO_USB_NRESET %d\n", + GPIO_USB_NRESET); + return; + } + + if (omap_mux_init_gpio(GPIO_USB_POWER, OMAP_PIN_OUTPUT)) { + pr_err("Can not configure mux for GPIO_USB_POWER %d\n", + GPIO_USB_POWER); + return; + } + + ret = gpio_request(GPIO_USB_POWER, "usb_ehci_enable"); + if (ret < 0) { + pr_err("Can not request GPIO %d\n", GPIO_USB_POWER); + return; + } + + ret = gpio_direction_output(GPIO_USB_POWER, 1); + if (ret < 0) { + gpio_free(GPIO_USB_POWER); + pr_err("Unable to initialize EHCI power\n"); + return; + } + + usb_ehci_init(&ehci_pdata); +} + +MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") + .boot_params = 0x80000100, + .map_io = omap3_map_io, + .reserve = omap_reserve, + .init_irq = am3517_crane_init_irq, + .init_machine = am3517_crane_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 07399505312b..bc1562648020 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -389,10 +389,9 @@ static void __init am3517_evm_init_irq(void) { omap_board_config = am3517_evm_config; omap_board_config_size = ARRAY_SIZE(am3517_evm_config); - - omap2_init_common_hw(NULL, NULL); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); omap_init_irq(); - omap_gpio_init(); } static struct omap_musb_board_data musb_board_data = { @@ -442,8 +441,6 @@ static struct omap_board_mux board_mux[] __initdata = { OMAP3_MUX(SAD2D_MCAD23, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 2c6db1aaeb29..9f55b68687f7 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -270,7 +270,7 @@ static struct omap_lcd_config apollon_lcd_config __initdata = { .ctrl_name = "internal", }; -static struct omap_board_config_kernel apollon_config[] = { +static struct omap_board_config_kernel apollon_config[] __initdata = { { OMAP_TAG_LCD, &apollon_lcd_config }, }; @@ -278,10 +278,9 @@ static void __init omap_apollon_init_irq(void) { omap_board_config = apollon_config; omap_board_config_size = ARRAY_SIZE(apollon_config); - omap2_init_common_hw(NULL, NULL); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); omap_init_irq(); - omap_gpio_init(); - apollon_init_smc91x(); } static void __init apollon_led_init(void) @@ -314,8 +313,6 @@ static void __init apollon_usb_init(void) static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif static void __init omap_apollon_init(void) @@ -324,6 +321,7 @@ static void __init omap_apollon_init(void) omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); + apollon_init_smc91x(); apollon_led_init(); apollon_flash_init(); apollon_usb_init(); diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 63f764e2af3f..486a3de5f401 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -600,8 +600,8 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, .phy_reset = true, - .reset_gpio_port[0] = -EINVAL, - .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[0] = OMAP_MAX_GPIO_LINES + 6, + .reset_gpio_port[1] = OMAP_MAX_GPIO_LINES + 7, .reset_gpio_port[2] = -EINVAL }; @@ -630,12 +630,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio, cm_t35_vmmc1_supply.dev = mmc[0].dev; cm_t35_vsim_supply.dev = mmc[0].dev; - /* setup USB with proper PHY reset GPIOs */ - ehci_pdata.reset_gpio_port[0] = gpio + 6; - ehci_pdata.reset_gpio_port[1] = gpio + 7; - - usb_ehci_init(&ehci_pdata); - return 0; } @@ -683,10 +677,10 @@ static void __init cm_t35_init_irq(void) omap_board_config = cm_t35_config; omap_board_config_size = ARRAY_SIZE(cm_t35_config); - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); omap_init_irq(); - omap_gpio_init(); } static struct omap_board_mux board_mux[] __initdata = { @@ -805,6 +799,7 @@ static void __init cm_t35_init(void) cm_t35_init_display(); usb_musb_init(&musb_board_data); + usb_ehci_init(&ehci_pdata); } MACHINE_START(CM_T35, "Compulab CM-T35") diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 1dd303e9a267..5b0c77732dfc 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -248,9 +248,9 @@ static void __init cm_t3517_init_irq(void) omap_board_config = cm_t3517_config; omap_board_config_size = ARRAY_SIZE(cm_t3517_config); - omap2_init_common_hw(NULL, NULL); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); omap_init_irq(); - omap_gpio_init(); } static struct omap_board_mux board_mux[] __initdata = { diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 53ac762518bd..451e7ff08b18 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -118,27 +118,27 @@ static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev) twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0); if (gpio_is_valid(dssdev->reset_gpio)) - gpio_set_value(dssdev->reset_gpio, 1); + gpio_set_value_cansleep(dssdev->reset_gpio, 1); return 0; } static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev) { if (gpio_is_valid(dssdev->reset_gpio)) - gpio_set_value(dssdev->reset_gpio, 0); + gpio_set_value_cansleep(dssdev->reset_gpio, 0); } static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev) { if (gpio_is_valid(dssdev->reset_gpio)) - gpio_set_value(dssdev->reset_gpio, 1); + gpio_set_value_cansleep(dssdev->reset_gpio, 1); return 0; } static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev) { if (gpio_is_valid(dssdev->reset_gpio)) - gpio_set_value(dssdev->reset_gpio, 0); + gpio_set_value_cansleep(dssdev->reset_gpio, 0); } static struct regulator_consumer_supply devkit8000_vmmc1_supply = @@ -444,13 +444,13 @@ static struct platform_device keys_gpio = { static void __init devkit8000_init_irq(void) { - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); omap_init_irq(); #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); #endif - omap_gpio_init(); } static void __init devkit8000_ads7846_init(void) diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index b1c2c9a11c38..0e3d81e09f89 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -37,7 +37,8 @@ static void __init omap_generic_init_irq(void) { omap_board_config = generic_config; omap_board_config_size = ARRAY_SIZE(generic_config); - omap2_init_common_hw(NULL, NULL); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); omap_init_irq(); } diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 929993b4bf26..25cc9dad4b02 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -51,38 +51,37 @@ static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 }; static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 }; -static int h4_keymap[] = { +static const unsigned int h4_keymap[] = { KEY(0, 0, KEY_LEFT), - KEY(0, 1, KEY_RIGHT), - KEY(0, 2, KEY_A), - KEY(0, 3, KEY_B), - KEY(0, 4, KEY_C), - KEY(1, 0, KEY_DOWN), + KEY(1, 0, KEY_RIGHT), + KEY(2, 0, KEY_A), + KEY(3, 0, KEY_B), + KEY(4, 0, KEY_C), + KEY(0, 1, KEY_DOWN), KEY(1, 1, KEY_UP), - KEY(1, 2, KEY_E), - KEY(1, 3, KEY_F), - KEY(1, 4, KEY_G), - KEY(2, 0, KEY_ENTER), - KEY(2, 1, KEY_I), + KEY(2, 1, KEY_E), + KEY(3, 1, KEY_F), + KEY(4, 1, KEY_G), + KEY(0, 2, KEY_ENTER), + KEY(1, 2, KEY_I), KEY(2, 2, KEY_J), - KEY(2, 3, KEY_K), - KEY(2, 4, KEY_3), - KEY(3, 0, KEY_M), - KEY(3, 1, KEY_N), - KEY(3, 2, KEY_O), + KEY(3, 2, KEY_K), + KEY(4, 2, KEY_3), + KEY(0, 3, KEY_M), + KEY(1, 3, KEY_N), + KEY(2, 3, KEY_O), KEY(3, 3, KEY_P), - KEY(3, 4, KEY_Q), - KEY(4, 0, KEY_R), - KEY(4, 1, KEY_4), - KEY(4, 2, KEY_T), - KEY(4, 3, KEY_U), + KEY(4, 3, KEY_Q), + KEY(0, 4, KEY_R), + KEY(1, 4, KEY_4), + KEY(2, 4, KEY_T), + KEY(3, 4, KEY_U), KEY(4, 4, KEY_ENTER), - KEY(5, 0, KEY_V), - KEY(5, 1, KEY_W), - KEY(5, 2, KEY_L), - KEY(5, 3, KEY_S), - KEY(5, 4, KEY_ENTER), - 0 + KEY(0, 5, KEY_V), + KEY(1, 5, KEY_W), + KEY(2, 5, KEY_L), + KEY(3, 5, KEY_S), + KEY(4, 5, KEY_ENTER), }; static struct mtd_partition h4_partitions[] = { @@ -136,12 +135,16 @@ static struct platform_device h4_flash_device = { .resource = &h4_flash_resource, }; +static const struct matrix_keymap_data h4_keymap_data = { + .keymap = h4_keymap, + .keymap_size = ARRAY_SIZE(h4_keymap), +}; + static struct omap_kp_platform_data h4_kp_data = { .rows = 6, .cols = 7, - .keymap = h4_keymap, - .keymapsize = ARRAY_SIZE(h4_keymap), - .rep = 1, + .keymap_data = &h4_keymap_data, + .rep = true, .row_gpios = row_gpios, .col_gpios = col_gpios, }; @@ -283,7 +286,7 @@ static struct omap_usb_config h4_usb_config __initdata = { .hmc_mode = 0x00, /* 0:dev|otg 1:disable 2:disable */ }; -static struct omap_board_config_kernel h4_config[] = { +static struct omap_board_config_kernel h4_config[] __initdata = { { OMAP_TAG_LCD, &h4_lcd_config }, }; @@ -291,9 +294,9 @@ static void __init omap_h4_init_irq(void) { omap_board_config = h4_config; omap_board_config_size = ARRAY_SIZE(h4_config); - omap2_init_common_hw(NULL, NULL); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); omap_init_irq(); - omap_gpio_init(); h4_init_flash(); } @@ -321,8 +324,6 @@ static struct i2c_board_info __initdata h4_i2c_board_info[] = { static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif static void __init omap_h4_init(void) diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 5e035a58b809..0afa3011db0f 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -19,6 +19,7 @@ #include <linux/interrupt.h> #include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> #include <linux/i2c/twl.h> #include <linux/mmc/host.h> @@ -136,16 +137,9 @@ static struct mtd_partition igep2_onenand_partitions[] = { }, }; -static int igep2_onenand_setup(void __iomem *onenand_base, int freq) -{ - /* nothing is required to be setup for onenand as of now */ - return 0; -} - static struct omap_onenand_platform_data igep2_onenand_data = { .parts = igep2_onenand_partitions, .nr_parts = ARRAY_SIZE(igep2_onenand_partitions), - .onenand_setup = igep2_onenand_setup, .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ }; @@ -159,35 +153,34 @@ static struct platform_device igep2_onenand_device = { static void __init igep2_flash_init(void) { - u8 cs = 0; - u8 onenandcs = GPMC_CS_NUM + 1; + u8 cs = 0; + u8 onenandcs = GPMC_CS_NUM + 1; - while (cs < GPMC_CS_NUM) { - u32 ret = 0; + for (cs = 0; cs < GPMC_CS_NUM; cs++) { + u32 ret; ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); /* Check if NAND/oneNAND is configured */ if ((ret & 0xC00) == 0x800) /* NAND found */ - pr_err("IGEP v2: Unsupported NAND found\n"); + pr_err("IGEP2: Unsupported NAND found\n"); else { ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); if ((ret & 0x3F) == (ONENAND_MAP >> 24)) /* ONENAND found */ onenandcs = cs; } - cs++; } + if (onenandcs > GPMC_CS_NUM) { - pr_err("IGEP v2: Unable to find configuration in GPMC\n"); + pr_err("IGEP2: Unable to find configuration in GPMC\n"); return; } - if (onenandcs < GPMC_CS_NUM) { - igep2_onenand_data.cs = onenandcs; - if (platform_device_register(&igep2_onenand_device) < 0) - pr_err("IGEP v2: Unable to register OneNAND device\n"); - } + igep2_onenand_data.cs = onenandcs; + + if (platform_device_register(&igep2_onenand_device) < 0) + pr_err("IGEP2: Unable to register OneNAND device\n"); } #else @@ -254,12 +247,8 @@ static inline void __init igep2_init_smsc911x(void) static inline void __init igep2_init_smsc911x(void) { } #endif -static struct omap_board_config_kernel igep2_config[] __initdata = { -}; - -static struct regulator_consumer_supply igep2_vmmc1_supply = { - .supply = "vmmc", -}; +static struct regulator_consumer_supply igep2_vmmc1_supply = + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ static struct regulator_init_data igep2_vmmc1 = { @@ -276,6 +265,52 @@ static struct regulator_init_data igep2_vmmc1 = { .consumer_supplies = &igep2_vmmc1_supply, }; +static struct regulator_consumer_supply igep2_vio_supply = + REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); + +static struct regulator_init_data igep2_vio = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &igep2_vio_supply, +}; + +static struct regulator_consumer_supply igep2_vmmc2_supply = + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); + +static struct regulator_init_data igep2_vmmc2 = { + .constraints = { + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .always_on = 1, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &igep2_vmmc2_supply, +}; + +static struct fixed_voltage_config igep2_vwlan = { + .supply_name = "vwlan", + .microvolts = 3300000, + .gpio = -EINVAL, + .enabled_at_boot = 1, + .init_data = &igep2_vmmc2, +}; + +static struct platform_device igep2_vwlan_device = { + .name = "reg-fixed-voltage", + .id = 0, + .dev = { + .platform_data = &igep2_vwlan, + }, +}; + static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, @@ -317,6 +352,7 @@ static struct gpio_led igep2_gpio_leds[] = { .name = "gpio-led:green:d1", .default_trigger = "heartbeat", .gpio = -EINVAL, /* gets replaced */ + .active_low = 1, }, }; @@ -342,24 +378,21 @@ static void __init igep2_leds_init(void) static inline void igep2_leds_init(void) { if ((gpio_request(IGEP2_GPIO_LED0_RED, "gpio-led:red:d0") == 0) && - (gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) { + (gpio_direction_output(IGEP2_GPIO_LED0_RED, 0) == 0)) gpio_export(IGEP2_GPIO_LED0_RED, 0); - gpio_set_value(IGEP2_GPIO_LED0_RED, 0); - } else + else pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n"); if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) && - (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) { + (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 0) == 0)) gpio_export(IGEP2_GPIO_LED0_GREEN, 0); - gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0); - } else + else pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n"); if ((gpio_request(IGEP2_GPIO_LED1_RED, "gpio-led:red:d1") == 0) && - (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) { + (gpio_direction_output(IGEP2_GPIO_LED1_RED, 0) == 0)) gpio_export(IGEP2_GPIO_LED1_RED, 0); - gpio_set_value(IGEP2_GPIO_LED1_RED, 0); - } else + else pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n"); } @@ -373,12 +406,6 @@ static int igep2_twl_gpio_setup(struct device *dev, omap2_hsmmc_init(mmc); /* - * link regulators to MMC adapters ... we "know" the - * regulators will be set up only *after* we return. - */ - igep2_vmmc1_supply.dev = mmc[0].dev; - - /* * REVISIT: need ehci-omap hooks for external VBUS * power switch and overcurrent detect */ @@ -397,10 +424,9 @@ static int igep2_twl_gpio_setup(struct device *dev, /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ #if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0) - && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) { + && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0); - gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0); - } else + else pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_GREEN\n"); #else igep2_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1; @@ -489,15 +515,15 @@ static void __init igep2_display_init(void) static struct platform_device *igep2_devices[] __initdata = { &igep2_dss_device, + &igep2_vwlan_device, }; static void __init igep2_init_irq(void) { - omap_board_config = igep2_config; - omap_board_config_size = ARRAY_SIZE(igep2_config); - omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); + omap2_init_common_infrastructure(); + omap2_init_common_devices(m65kxxxxam_sdrc_params, + m65kxxxxam_sdrc_params); omap_init_irq(); - omap_gpio_init(); } static struct twl4030_codec_audio_data igep2_audio_data = { @@ -519,7 +545,7 @@ static struct twl4030_platform_data igep2_twldata = { .gpio = &igep2_twl4030_gpio_pdata, .vmmc1 = &igep2_vmmc1, .vpll2 = &igep2_vpll2, - + .vio = &igep2_vio, }; static struct i2c_board_info __initdata igep2_i2c1_boardinfo[] = { @@ -577,8 +603,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif #if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c index 22b0b253e16b..bcccd68f1856 100644 --- a/arch/arm/mach-omap2/board-igep0030.c +++ b/arch/arm/mach-omap2/board-igep0030.c @@ -289,9 +289,10 @@ static struct twl4030_usb_data igep3_twl4030_usb_data = { static void __init igep3_init_irq(void) { - omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); + omap2_init_common_infrastructure(); + omap2_init_common_devices(m65kxxxxam_sdrc_params, + m65kxxxxam_sdrc_params); omap_init_irq(); - omap_gpio_init(); } static struct twl4030_platform_data igep3_twl4030_pdata = { @@ -366,8 +367,6 @@ void __init igep3_wifi_bt_init(void) {} static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif static void __init igep3_init(void) diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 001fd9713f39..e5dc74875f9d 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -292,10 +292,9 @@ static void __init omap_ldp_init_irq(void) { omap_board_config = ldp_config; omap_board_config_size = ARRAY_SIZE(ldp_config); - omap2_init_common_hw(NULL, NULL); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); omap_init_irq(); - omap_gpio_init(); - ldp_init_smsc911x(); } static struct twl4030_usb_data ldp_usb_data = { @@ -381,8 +380,6 @@ static struct platform_device *ldp_devices[] __initdata = { static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif static struct omap_musb_board_data musb_board_data = { @@ -426,6 +423,7 @@ static struct mtd_partition ldp_nand_partitions[] = { static void __init omap_ldp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + ldp_init_smsc911x(); omap_i2c_init(); platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); ts_gpio = 54; diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index e823c7042ab3..f396756872b7 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -46,8 +46,7 @@ static struct device *mmc_device; #define TUSB6010_GPIO_ENABLE 0 #define TUSB6010_DMACHAN 0x3f -#if defined(CONFIG_USB_TUSB6010) || \ - defined(CONFIG_USB_TUSB6010_MODULE) +#ifdef CONFIG_USB_MUSB_TUSB6010 /* * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and * 1.5 V voltage regulators of PM companion chip. Companion chip will then @@ -134,7 +133,7 @@ err: static void __init n8x0_usb_init(void) {} -#endif /*CONFIG_USB_TUSB6010 */ +#endif /*CONFIG_USB_MUSB_TUSB6010 */ static struct omap2_mcspi_device_config p54spi_mcspi_config = { @@ -184,23 +183,15 @@ static struct mtd_partition onenand_partitions[] = { }, }; -static struct omap_onenand_platform_data board_onenand_data = { - .cs = 0, - .gpio_irq = 26, - .parts = onenand_partitions, - .nr_parts = ARRAY_SIZE(onenand_partitions), - .flags = ONENAND_SYNC_READ, +static struct omap_onenand_platform_data board_onenand_data[] = { + { + .cs = 0, + .gpio_irq = 26, + .parts = onenand_partitions, + .nr_parts = ARRAY_SIZE(onenand_partitions), + .flags = ONENAND_SYNC_READ, + } }; - -static void __init n8x0_onenand_init(void) -{ - gpmc_onenand_init(&board_onenand_data); -} - -#else - -static void __init n8x0_onenand_init(void) {} - #endif #if defined(CONFIG_MENELAUS) && \ @@ -639,9 +630,9 @@ static void __init n8x0_map_io(void) static void __init n8x0_init_irq(void) { - omap2_init_common_hw(NULL, NULL); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); omap_init_irq(); - omap_gpio_init(); } #ifdef CONFIG_OMAP_MUX @@ -653,8 +644,43 @@ static struct omap_board_mux board_mux[] __initdata = { OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), { .reg_offset = OMAP_MUX_TERMINATOR }, }; + +static struct omap_device_pad serial2_pads[] __initdata = { + { + .name = "uart3_rx_irrx.uart3_rx_irrx", + .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, + .enable = OMAP_MUX_MODE0, + .idle = OMAP_MUX_MODE3 /* Mux as GPIO for idle */ + }, +}; + +static inline void board_serial_init(void) +{ + struct omap_board_data bdata; + + bdata.flags = 0; + bdata.pads = NULL; + bdata.pads_cnt = 0; + + bdata.id = 0; + omap_serial_init_port(&bdata); + + bdata.id = 1; + omap_serial_init_port(&bdata); + + bdata.id = 2; + bdata.pads = serial2_pads; + bdata.pads_cnt = ARRAY_SIZE(serial2_pads); + omap_serial_init_port(&bdata); +} + #else -#define board_mux NULL + +static inline void board_serial_init(void) +{ + omap_serial_init(); +} + #endif static void __init n8x0_init_machine(void) @@ -669,9 +695,8 @@ static void __init n8x0_init_machine(void) if (machine_is_nokia_n810()) i2c_register_board_info(2, n810_i2c_board_info_2, ARRAY_SIZE(n810_i2c_board_info_2)); - - omap_serial_init(); - n8x0_onenand_init(); + board_serial_init(); + gpmc_onenand_init(board_onenand_data); n8x0_mmc_init(); n8x0_usb_init(); } diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 14f42240ae79..6c127605942f 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -484,13 +484,13 @@ static struct platform_device keys_gpio = { static void __init omap3_beagle_init_irq(void) { - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); omap_init_irq(); #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); #endif - omap_gpio_init(); } static struct platform_device *omap3_beagle_devices[] __initdata = { @@ -548,8 +548,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif static struct omap_musb_board_data musb_board_data = { diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index b04365c6bb10..3de8d9b8ec76 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -623,9 +623,9 @@ static void __init omap3_evm_init_irq(void) { omap_board_config = omap3_evm_config; omap_board_config_size = ARRAY_SIZE(omap3_evm_config); - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL); + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); omap_init_irq(); - omap_gpio_init(); } static struct platform_device *omap3_evm_devices[] __initdata = { @@ -654,8 +654,6 @@ static struct omap_board_mux board_mux[] __initdata = { OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW), { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif static struct omap_musb_board_data musb_board_data = { diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index 5f7d2c1e7ef5..15e4b08e99ba 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c @@ -197,17 +197,15 @@ static inline void __init board_smsc911x_init(void) static void __init omap3logic_init_irq(void) { - omap2_init_common_hw(NULL, NULL); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); omap_init_irq(); - omap_gpio_init(); } #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif static void __init omap3logic_init(void) diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 8be261506056..0b34beded11f 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -293,7 +293,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = { }, { .mmc = 3, - .caps = MMC_CAP_4_BIT_DATA, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .init_card = pandora_wl1251_init_card, @@ -636,10 +636,10 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = { static void __init omap3pandora_init_irq(void) { - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); omap_init_irq(); - omap_gpio_init(); } static void __init pandora_wl1251_init(void) @@ -697,8 +697,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif static struct omap_musb_board_data musb_board_data = { diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index f25272125413..9df9d9367608 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -584,12 +584,12 @@ static void __init omap3_stalker_init_irq(void) { omap_board_config = omap3_stalker_config; omap_board_config_size = ARRAY_SIZE(omap3_stalker_config); - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL); + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); omap_init_irq(); #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); #endif - omap_gpio_init(); } static struct platform_device *omap3_stalker_devices[] __initdata = { @@ -616,8 +616,6 @@ static struct omap_board_mux board_mux[] __initdata = { OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE), {.reg_offset = OMAP_MUX_TERMINATOR}, }; -#else -#define board_mux NULL #endif static struct omap_musb_board_data musb_board_data = { diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 41104bb8774c..db1f74fe6c4f 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -413,8 +413,6 @@ static struct omap_board_config_kernel omap3_touchbook_config[] __initdata = { static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif static void __init omap3_touchbook_init_irq(void) @@ -422,13 +420,13 @@ static void __init omap3_touchbook_init_irq(void) omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_board_config = omap3_touchbook_config; omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config); - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); omap_init_irq(); #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); #endif - omap_gpio_init(); } static struct platform_device *omap3_touchbook_devices[] __initdata = { diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 1ecd0a6cefb7..3094e2007844 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -40,6 +40,7 @@ #include "hsmmc.h" #include "control.h" +#include "mux.h" #define GPIO_HUB_POWER 1 #define GPIO_HUB_NRESET 62 @@ -76,9 +77,9 @@ static struct platform_device *panda_devices[] __initdata = { static void __init omap4_panda_init_irq(void) { - omap2_init_common_hw(NULL, NULL); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); gic_init_irq(); - omap_gpio_init(); } static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { @@ -133,15 +134,23 @@ error1: static struct omap_musb_board_data musb_board_data = { .interface_type = MUSB_INTERFACE_UTMI, - .mode = MUSB_PERIPHERAL, + .mode = MUSB_OTG, .power = 100, }; +static struct twl4030_usb_data omap4_usbphy_data = { + .phy_init = omap4430_phy_init, + .phy_exit = omap4430_phy_exit, + .phy_power = omap4430_phy_power, + .phy_set_clock = omap4430_phy_set_clk, +}; + static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_wp = -EINVAL, + .gpio_cd = -EINVAL, }, {} /* Terminator */ }; @@ -345,6 +354,7 @@ static struct twl4030_platform_data omap4_panda_twldata = { .vaux1 = &omap4_panda_vaux1, .vaux2 = &omap4_panda_vaux2, .vaux3 = &omap4_panda_vaux3, + .usb = &omap4_usbphy_data, }; static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = { @@ -368,8 +378,23 @@ static int __init omap4_panda_i2c_init(void) omap_register_i2c_bus(4, 400, NULL, 0); return 0; } + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + static void __init omap4_panda_init(void) { + int package = OMAP_PACKAGE_CBS; + + if (omap_rev() == OMAP4430_REV_ES1_0) + package = OMAP_PACKAGE_CBL; + omap4_mux_init(board_mux, package); + omap4_panda_i2c_init(); platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); omap_serial_init(); @@ -377,9 +402,7 @@ static void __init omap4_panda_init(void) /* OMAP4 Panda uses internal transceiver so register nop transceiver */ usb_nop_xceiv_register(); omap4_ehci_init(); - /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ - if (!cpu_is_omap44xx()) - usb_musb_init(&musb_board_data); + usb_musb_init(&musb_board_data); } static void __init omap4_panda_map_io(void) @@ -391,6 +414,7 @@ static void __init omap4_panda_map_io(void) MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") /* Maintainer: David Anders - Texas Instruments Inc */ .boot_params = 0x80000100, + .reserve = omap_reserve, .map_io = omap4_panda_map_io, .init_irq = omap4_panda_init_irq, .init_machine = omap4_panda_init, diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 7053bc0b46db..cb26e5d8268d 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -413,10 +413,10 @@ static void __init overo_init_irq(void) { omap_board_config = overo_config; omap_board_config_size = ARRAY_SIZE(overo_config); - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); omap_init_irq(); - omap_gpio_init(); } static struct platform_device *overo_devices[] __initdata = { @@ -438,8 +438,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif static struct omap_musb_board_data musb_board_data = { diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c new file mode 100644 index 000000000000..cb77be7ac44f --- /dev/null +++ b/arch/arm/mach-omap2/board-rm680.c @@ -0,0 +1,187 @@ +/* + * Board support file for Nokia RM-680. + * + * Copyright (C) 2010 Nokia + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/io.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/i2c/twl.h> +#include <linux/platform_device.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/consumer.h> + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> + +#include <plat/i2c.h> +#include <plat/mmc.h> +#include <plat/usb.h> +#include <plat/gpmc.h> +#include <plat/common.h> +#include <plat/onenand.h> + +#include "mux.h" +#include "hsmmc.h" +#include "sdram-nokia.h" + +static struct regulator_consumer_supply rm680_vemmc_consumers[] = { + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), +}; + +/* Fixed regulator for internal eMMC */ +static struct regulator_init_data rm680_vemmc = { + .constraints = { + .name = "rm680_vemmc", + .min_uV = 2900000, + .max_uV = 2900000, + .apply_uV = 1, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_STATUS + | REGULATOR_CHANGE_MODE, + }, + .num_consumer_supplies = ARRAY_SIZE(rm680_vemmc_consumers), + .consumer_supplies = rm680_vemmc_consumers, +}; + +static struct fixed_voltage_config rm680_vemmc_config = { + .supply_name = "VEMMC", + .microvolts = 2900000, + .gpio = 157, + .startup_delay = 150, + .enable_high = 1, + .init_data = &rm680_vemmc, +}; + +static struct platform_device rm680_vemmc_device = { + .name = "reg-fixed-voltage", + .dev = { + .platform_data = &rm680_vemmc_config, + }, +}; + +static struct platform_device *rm680_peripherals_devices[] __initdata = { + &rm680_vemmc_device, +}; + +/* TWL */ +static struct twl4030_gpio_platform_data rm680_gpio_data = { + .gpio_base = OMAP_MAX_GPIO_LINES, + .irq_base = TWL4030_GPIO_IRQ_BASE, + .irq_end = TWL4030_GPIO_IRQ_END, + .pullups = BIT(0), + .pulldowns = BIT(1) | BIT(2) | BIT(8) | BIT(15), +}; + +static struct twl4030_usb_data rm680_usb_data = { + .usb_mode = T2_USB_MODE_ULPI, +}; + +static struct twl4030_platform_data rm680_twl_data = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, + .gpio = &rm680_gpio_data, + .usb = &rm680_usb_data, + /* add rest of the children here */ +}; + +static struct i2c_board_info __initdata rm680_twl_i2c_board_info[] = { + { + I2C_BOARD_INFO("twl5031", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = INT_34XX_SYS_NIRQ, + .platform_data = &rm680_twl_data, + }, +}; + +static void __init rm680_i2c_init(void) +{ + omap_register_i2c_bus(1, 2900, rm680_twl_i2c_board_info, + ARRAY_SIZE(rm680_twl_i2c_board_info)); + omap_register_i2c_bus(2, 400, NULL, 0); + omap_register_i2c_bus(3, 400, NULL, 0); +} + +#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) +static struct omap_onenand_platform_data board_onenand_data[] = { + { + .gpio_irq = 65, + .flags = ONENAND_SYNC_READWRITE, + } +}; +#endif + +/* eMMC */ +static struct omap2_hsmmc_info mmc[] __initdata = { + { + .name = "internal", + .mmc = 2, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + }, + { /* Terminator */ } +}; + +static void __init rm680_peripherals_init(void) +{ + platform_add_devices(rm680_peripherals_devices, + ARRAY_SIZE(rm680_peripherals_devices)); + rm680_i2c_init(); + gpmc_onenand_init(board_onenand_data); + omap2_hsmmc_init(mmc); +} + +static void __init rm680_init_irq(void) +{ + struct omap_sdrc_params *sdrc_params; + + omap2_init_common_infrastructure(); + sdrc_params = nokia_get_sdram_timings(); + omap2_init_common_devices(sdrc_params, sdrc_params); + omap_init_irq(); +} + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#endif + +static struct omap_musb_board_data rm680_musb_data = { + .interface_type = MUSB_INTERFACE_ULPI, + .mode = MUSB_PERIPHERAL, + .power = 100, +}; + +static void __init rm680_init(void) +{ + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap_serial_init(); + usb_musb_init(&rm680_musb_data); + rm680_peripherals_init(); +} + +static void __init rm680_map_io(void) +{ + omap2_set_globals_3xxx(); + omap34xx_map_common_io(); +} + +MACHINE_START(NOKIA_RM680, "Nokia RM-680 board") + .boot_params = 0x80000100, + .map_io = rm680_map_io, + .reserve = omap_reserve, + .init_irq = rm680_init_irq, + .init_machine = rm680_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 3fec4d62a91a..e75e240cad67 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -23,7 +23,6 @@ #include <linux/gpio.h> #include <linux/gpio_keys.h> #include <linux/mmc/host.h> -#include <sound/tlv320aic3x.h> #include <plat/mcspi.h> #include <plat/board.h> @@ -293,6 +292,8 @@ static struct omap_board_mux rx51_mmc2_off_mux[] = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; +static struct omap_mux_partition *partition; + /* * Current flows to eMMC when eMMC is off and the data lines are pulled up, * so pull them down. N.B. we pull 8 lines because we are using 8 lines. @@ -300,9 +301,9 @@ static struct omap_board_mux rx51_mmc2_off_mux[] = { static void rx51_mmc2_remux(struct device *dev, int slot, int power_on) { if (power_on) - omap_mux_write_array(rx51_mmc2_on_mux); + omap_mux_write_array(partition, rx51_mmc2_on_mux); else - omap_mux_write_array(rx51_mmc2_off_mux); + omap_mux_write_array(partition, rx51_mmc2_off_mux); } static struct omap2_hsmmc_info mmc[] __initdata = { @@ -342,6 +343,8 @@ static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { /* tlv320aic3x analog supplies */ REGULATOR_SUPPLY("AVDD", "2-0018"), REGULATOR_SUPPLY("DRVDD", "2-0018"), + REGULATOR_SUPPLY("AVDD", "2-0019"), + REGULATOR_SUPPLY("DRVDD", "2-0019"), /* tpa6130a2 */ REGULATOR_SUPPLY("Vdd", "2-0060"), /* Keep vmmc as last item. It is not iterated for newer boards */ @@ -352,19 +355,16 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = { /* tlv320aic3x digital supplies */ REGULATOR_SUPPLY("IOVDD", "2-0018"), REGULATOR_SUPPLY("DVDD", "2-0018"), + REGULATOR_SUPPLY("IOVDD", "2-0019"), + REGULATOR_SUPPLY("DVDD", "2-0019"), }; -#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) -extern struct platform_device rx51_display_device; -#endif - static struct regulator_consumer_supply rx51_vaux1_consumers[] = { -#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) - { - .supply = "vdds_sdi", - .dev = &rx51_display_device.dev, - }, -#endif + REGULATOR_SUPPLY("vdds_sdi", "omapdss"), +}; + +static struct regulator_consumer_supply rx51_vdac_supply[] = { + REGULATOR_SUPPLY("vdda_dac", "omapdss"), }; static struct regulator_init_data rx51_vaux1 = { @@ -484,14 +484,17 @@ static struct regulator_init_data rx51_vsim = { static struct regulator_init_data rx51_vdac = { .constraints = { + .name = "VDAC", .min_uV = 1800000, .max_uV = 1800000, + .apply_uV = true, .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE + .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, + .num_consumer_supplies = 1, + .consumer_supplies = rx51_vdac_supply, }; static struct regulator_init_data rx51_vio = { @@ -717,7 +720,7 @@ static struct twl4030_platform_data rx51_twldata __initdata = { .vio = &rx51_vio, }; -static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = { +static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata_or_module = { .id = TPA6130A2, .power_gpio = 98, }; @@ -742,11 +745,19 @@ static struct aic3x_pdata rx51_aic3x_data = { .gpio_reset = 60, }; +static struct aic3x_pdata rx51_aic3x_data2 = { + .gpio_reset = 60, +}; + static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = { { I2C_BOARD_INFO("tlv320aic3x", 0x18), .platform_data = &rx51_aic3x_data, }, + { + I2C_BOARD_INFO("tlv320aic3x", 0x19), + .platform_data = &rx51_aic3x_data2, + }, #if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE) { I2C_BOARD_INFO("tsl2563", 0x29), @@ -815,25 +826,15 @@ static struct mtd_partition onenand_partitions[] = { }, }; -static struct omap_onenand_platform_data board_onenand_data = { - .cs = 0, - .gpio_irq = 65, - .parts = onenand_partitions, - .nr_parts = ARRAY_SIZE(onenand_partitions), - .flags = ONENAND_SYNC_READWRITE, +static struct omap_onenand_platform_data board_onenand_data[] = { + { + .cs = 0, + .gpio_irq = 65, + .parts = onenand_partitions, + .nr_parts = ARRAY_SIZE(onenand_partitions), + .flags = ONENAND_SYNC_READWRITE, + } }; - -static void __init board_onenand_init(void) -{ - gpmc_onenand_init(&board_onenand_data); -} - -#else - -static inline void board_onenand_init(void) -{ -} - #endif #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) @@ -916,13 +917,17 @@ error: void __init rx51_peripherals_init(void) { rx51_i2c_init(); - board_onenand_init(); + gpmc_onenand_init(board_onenand_data); board_smc91x_init(); rx51_add_gpio_keys(); rx51_init_wl1251(); spi_register_board_info(rx51_peripherals_spi_board_info, ARRAY_SIZE(rx51_peripherals_spi_board_info)); - omap2_hsmmc_init(mmc); + + partition = omap_mux_get("core"); + if (partition) + omap2_hsmmc_init(mmc); + platform_device_register(&rx51_charger_device); } diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c index 85503fed4e13..acd670054d9a 100644 --- a/arch/arm/mach-omap2/board-rx51-video.c +++ b/arch/arm/mach-omap2/board-rx51-video.c @@ -14,7 +14,6 @@ #include <linux/gpio.h> #include <linux/spi/spi.h> #include <linux/mm.h> - #include <asm/mach-types.h> #include <plat/display.h> #include <plat/vram.h> @@ -49,8 +48,16 @@ static struct omap_dss_device rx51_lcd_device = { .platform_disable = rx51_lcd_disable, }; +static struct omap_dss_device rx51_tv_device = { + .name = "tv", + .type = OMAP_DISPLAY_TYPE_VENC, + .driver_name = "venc", + .phy.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE, +}; + static struct omap_dss_device *rx51_dss_devices[] = { &rx51_lcd_device, + &rx51_tv_device, }; static struct omap_dss_board_info rx51_dss_board_info = { diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 36f2cf4efd57..f53fc551c58f 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -32,10 +32,10 @@ #include "mux.h" #include "pm.h" +#include "sdram-nokia.h" #define RX51_GPIO_SLEEP_IND 162 -struct omap_sdrc_params *rx51_get_sdram_timings(void); extern void rx51_video_mem_init(void); static struct gpio_led gpio_leds[] = { @@ -105,10 +105,10 @@ static void __init rx51_init_irq(void) omap_board_config = rx51_config; omap_board_config_size = ARRAY_SIZE(rx51_config); omap3_pm_init_cpuidle(rx51_cpuidle_params); - sdrc_params = rx51_get_sdram_timings(); - omap2_init_common_hw(sdrc_params, sdrc_params); + omap2_init_common_infrastructure(); + sdrc_params = nokia_get_sdram_timings(); + omap2_init_common_devices(sdrc_params, sdrc_params); omap_init_irq(); - omap_gpio_init(); } extern void __init rx51_peripherals_init(void); @@ -117,8 +117,6 @@ extern void __init rx51_peripherals_init(void); static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -#else -#define board_mux NULL #endif static struct omap_musb_board_data musb_board_data = { diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 9db9203667df..3fbd0edd712e 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -196,7 +196,7 @@ struct wl12xx_platform_data omap_zoom_wlan_data __initdata = { .board_ref_clock = 1, }; -static struct omap2_hsmmc_info mmc[] __initdata = { +static struct omap2_hsmmc_info mmc[] = { { .name = "external", .mmc = 1, diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom.c index 5adde12c0395..e041c537ea37 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom.c @@ -1,6 +1,9 @@ /* - * Copyright (C) 2009 Texas Instruments Inc. + * Copyright (C) 2009-2010 Texas Instruments Inc. + * Mikkel Christensen <mlc@ti.com> + * Felipe Balbi <balbi@ti.com> * + * Modified from mach-omap2/board-ldp.c * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -12,22 +15,55 @@ #include <linux/platform_device.h> #include <linux/input.h> #include <linux/gpio.h> +#include <linux/i2c/twl.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <mach/board-zoom.h> - #include <plat/common.h> #include <plat/board.h> #include <plat/usb.h> +#include <mach/board-zoom.h> + #include "board-flash.h" #include "mux.h" +#include "sdram-micron-mt46h32m32lf-6.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" -static struct omap_board_config_kernel zoom_config[] __initdata = { +#define ZOOM3_EHCI_RESET_GPIO 64 + +static void __init omap_zoom_init_irq(void) +{ + omap2_init_common_infrastructure(); + if (machine_is_omap_zoom2()) + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); + else if (machine_is_omap_zoom3()) + omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params, + h8mbx00u0mer0em_sdrc_params); + + omap_init_irq(); +} + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + /* WLAN IRQ - GPIO 162 */ + OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), + /* WLAN POWER ENABLE - GPIO 101 */ + OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* WLAN SDIO: MMC3 CMD */ + OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 CLK */ + OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 DAT[0-3] */ + OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + { .reg_offset = OMAP_MUX_TERMINATOR }, }; +#endif static struct mtd_partition zoom_nand_partitions[] = { /* All the partition sizes are listed in terms of NAND block size */ @@ -70,59 +106,41 @@ static struct mtd_partition zoom_nand_partitions[] = { }, }; -static void __init omap_zoom_init_irq(void) -{ - omap_board_config = zoom_config; - omap_board_config_size = ARRAY_SIZE(zoom_config); - omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params, - h8mbx00u0mer0em_sdrc_params); - omap_init_irq(); - omap_gpio_init(); -} - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - /* WLAN IRQ - GPIO 162 */ - OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), - /* WLAN POWER ENABLE - GPIO 101 */ - OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), - /* WLAN SDIO: MMC3 CMD */ - OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), - /* WLAN SDIO: MMC3 CLK */ - OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - /* WLAN SDIO: MMC3 DAT[0-3] */ - OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, - .reset_gpio_port[1] = 64, + .reset_gpio_port[1] = ZOOM3_EHCI_RESET_GPIO, .reset_gpio_port[2] = -EINVAL, }; static void __init omap_zoom_init(void) { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); - zoom_peripherals_init(); + if (machine_is_omap_zoom2()) { + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + } else if (machine_is_omap_zoom3()) { + omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); + omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT); + usb_ehci_init(&ehci_pdata); + } + board_nand_init(zoom_nand_partitions, - ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); + ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); zoom_debugboard_init(); - - omap_mux_init_gpio(64, OMAP_PIN_OUTPUT); - usb_ehci_init(&ehci_pdata); + zoom_peripherals_init(); } +MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") + .boot_params = 0x80000100, + .map_io = omap3_map_io, + .reserve = omap_reserve, + .init_irq = omap_zoom_init_irq, + .init_machine = omap_zoom_init, + .timer = &omap_timer, +MACHINE_END + MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") .boot_params = 0x80000100, .map_io = omap3_map_io, diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c deleted file mode 100644 index 2992a9f3a585..000000000000 --- a/arch/arm/mach-omap2/board-zoom2.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Inc. - * Mikkel Christensen <mlc@ti.com> - * - * Modified from mach-omap2/board-ldp.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/input.h> -#include <linux/gpio.h> -#include <linux/i2c/twl.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <plat/common.h> -#include <plat/board.h> - -#include <mach/board-zoom.h> - -#include "board-flash.h" -#include "mux.h" -#include "sdram-micron-mt46h32m32lf-6.h" - -static void __init omap_zoom2_init_irq(void) -{ - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); - omap_init_irq(); - omap_gpio_init(); -} - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - /* WLAN IRQ - GPIO 162 */ - OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), - /* WLAN POWER ENABLE - GPIO 101 */ - OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), - /* WLAN SDIO: MMC3 CMD */ - OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), - /* WLAN SDIO: MMC3 CLK */ - OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - /* WLAN SDIO: MMC3 DAT[0-3] */ - OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - -static struct mtd_partition zoom_nand_partitions[] = { - /* All the partition sizes are listed in terms of NAND block size */ - { - .name = "X-Loader-NAND", - .offset = 0, - .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "U-Boot-NAND", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ - .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "Boot Env-NAND", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ - .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ - }, - { - .name = "Kernel-NAND", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ - .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ - }, - { - .name = "system", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ - .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */ - }, - { - .name = "userdata", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/ - .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ - }, - { - .name = "cache", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/ - .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ - }, -}; - -static void __init omap_zoom2_init(void) -{ - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - zoom_peripherals_init(); - board_nand_init(zoom_nand_partitions, - ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); - zoom_debugboard_init(); -} - -MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") - .boot_params = 0x80000100, - .map_io = omap3_map_io, - .reserve = omap_reserve, - .init_irq = omap_zoom2_init_irq, - .init_machine = omap_zoom2_init, - .timer = &omap_timer, -MACHINE_END diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index 66e01acfd585..f51cffd1fc53 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -26,7 +26,7 @@ #include "clock.h" #include "clock2xxx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ @@ -49,14 +49,14 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) apll_mask = EN_APLL_LOCKED << clk->enable_bit; - cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); + cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); if ((cval & apll_mask) == apll_mask) return 0; /* apll already enabled */ cval &= ~apll_mask; cval |= apll_mask; - cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); + omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); omap2_cm_wait_idlest(cm_idlest_pll, status_mask, OMAP24XX_CM_IDLEST_VAL, clk->name); @@ -83,9 +83,9 @@ static void omap2_clk_apll_disable(struct clk *clk) { u32 cval; - cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); + cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); cval &= ~(EN_APLL_LOCKED << clk->enable_bit); - cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); + omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); } /* Public data */ @@ -106,7 +106,7 @@ u32 omap2xxx_get_apll_clkin(void) { u32 aplls, srate = 0; - aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); + aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); aplls &= OMAP24XX_APLLS_CLKIN_MASK; aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 019048434f13..4ae439222085 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -32,7 +32,7 @@ #include "clock.h" #include "clock2xxx.h" #include "opp2xxx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ @@ -54,7 +54,7 @@ unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) core_clk = omap2_get_dpll_rate(clk); - v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); v &= OMAP24XX_CORE_CLK_SRC_MASK; if (v == CORE_CLK_SRC_32K) @@ -73,7 +73,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) { u32 high, low, core_clk_src; - core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ @@ -111,7 +111,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) const struct dpll_data *dd; cur_rate = omap2xxx_clk_get_core_rate(dclk); - mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); mult &= OMAP24XX_CORE_CLK_SRC_MASK; if ((rate == (cur_rate / 2)) && (mult == 2)) { @@ -136,7 +136,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) tmpset.cm_clksel1_pll &= ~(dd->mult_mask | dd->div1_mask); div = ((curr_prcm_set->xtal_speed / 1000000) - 1); - tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; if (rate > low) { tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c index 2167be84a5bc..df7b80506483 100644 --- a/arch/arm/mach-omap2/clkt2xxx_osc.c +++ b/arch/arm/mach-omap2/clkt2xxx_osc.c @@ -27,7 +27,7 @@ #include "clock.h" #include "clock2xxx.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" static int omap2_enable_osc_ck(struct clk *clk) diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c index 822b5a79f457..8693cfdac49a 100644 --- a/arch/arm/mach-omap2/clkt2xxx_sys.c +++ b/arch/arm/mach-omap2/clkt2xxx_sys.c @@ -26,7 +26,7 @@ #include "clock.h" #include "clock2xxx.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" void __iomem *prcm_clksrc_ctrl; diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index aef62918aaf0..39f9d5a58d0c 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -40,7 +40,7 @@ #include "clock.h" #include "clock2xxx.h" #include "opp2xxx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" const struct prcm_config *curr_prcm_set; @@ -133,21 +133,21 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) done_rate = CORE_CLK_SRC_DPLL; /* MPU divider */ - cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); + omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); /* dsp + iva1 div(2420), iva2.1(2430) */ - cm_write_mod_reg(prcm->cm_clksel_dsp, + omap2_cm_write_mod_reg(prcm->cm_clksel_dsp, OMAP24XX_DSP_MOD, CM_CLKSEL); - cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); + omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); /* Major subsystem dividers */ - tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; - cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, + tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; + omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1); if (cpu_is_omap2430()) - cm_write_mod_reg(prcm->cm_clksel_mdm, + omap2_cm_write_mod_reg(prcm->cm_clksel_mdm, OMAP2430_MDM_MOD, CM_CLKSEL); /* x2 to enter omap2xxx_sdrc_init_params() */ diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 6ce512e902c6..337392c3f549 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -24,7 +24,6 @@ #include <plat/clock.h> #include "clock.h" -#include "cm.h" #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index b5babf5440e4..2a2f15213add 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -24,14 +24,12 @@ #include <linux/bitops.h> #include <plat/clock.h> -#include <plat/clockdomain.h> +#include "clockdomain.h" #include <plat/cpu.h> #include <plat/prcm.h> #include "clock.h" -#include "prm.h" -#include "prm-regbits-24xx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index a535c7a2a62a..896584e3c4ab 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -49,7 +49,6 @@ /* DPLL Type and DCO Selection Flags */ #define DPLL_J_TYPE 0x1 -#define DPLL_NO_DCO_SEL 0x2 int omap2_clk_enable(struct clk *clk); void omap2_clk_disable(struct clk *clk); diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 21f856252ad8..0a992bc8d0d8 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -22,8 +22,8 @@ #include "clock.h" #include "clock2xxx.h" #include "opp2xxx.h" -#include "prm.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" #include "sdrc.h" @@ -812,7 +812,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, .clksel = dss2_fck_clksel, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, }; static struct clk dss_54m_fck = { /* Alt clk used in power management */ @@ -1862,10 +1862,10 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "eac_fck", &eac_fck, CK_242X), CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X), - CLK("i2c_omap.1", "ick", &i2c1_ick, CK_242X), - CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), - CLK("i2c_omap.2", "ick", &i2c2_ick, CK_242X), - CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), + CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), + CLK("omap_i2c.1", "fck", &i2c1_fck, CK_242X), + CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), + CLK("omap_i2c.2", "fck", &i2c2_fck, CK_242X), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), @@ -1877,7 +1877,7 @@ static struct omap_clk omap2420_clks[] = { CLK("omap-aes", "ick", &aes_ick, CK_242X), CLK(NULL, "pka_ick", &pka_ick, CK_242X), CLK(NULL, "usb_fck", &usb_fck, CK_242X), - CLK("musb_hdrc", "fck", &osc_ck, CK_242X), + CLK("musb-hdrc", "fck", &osc_ck, CK_242X), }; /* diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c index 44d0cccc51a9..d87bc9cb2a36 100644 --- a/arch/arm/mach-omap2/clock2430.c +++ b/arch/arm/mach-omap2/clock2430.c @@ -25,7 +25,7 @@ #include "clock.h" #include "clock2xxx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" /** diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index e32afcbdfb88..c047dcd007e5 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -22,8 +22,8 @@ #include "clock.h" #include "clock2xxx.h" #include "opp2xxx.h" -#include "prm.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" #include "sdrc.h" @@ -800,7 +800,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, .clksel = dss2_fck_clksel, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, }; static struct clk dss_54m_fck = { /* Alt clk used in power management */ @@ -1969,10 +1969,10 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "fac_fck", &fac_fck, CK_243X), CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), - CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X), - CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), - CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X), - CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), + CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), + CLK("omap_i2c.1", "fck", &i2chs1_fck, CK_243X), + CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), + CLK("omap_i2c.2", "fck", &i2chs2_fck, CK_243X), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), @@ -1983,7 +1983,7 @@ static struct omap_clk omap2430_clks[] = { CLK("omap-aes", "ick", &aes_ick, CK_243X), CLK(NULL, "pka_ick", &pka_ick, CK_243X), CLK(NULL, "usb_fck", &usb_fck, CK_243X), - CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), + CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 6febd5f11e85..287abc480924 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -25,7 +25,7 @@ #include "clock.h" #include "clock34xx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" /** diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c index b496a9305e1c..74116a3cf099 100644 --- a/arch/arm/mach-omap2/clock3517.c +++ b/arch/arm/mach-omap2/clock3517.c @@ -25,7 +25,7 @@ #include "clock.h" #include "clock3517.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" /* diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index a447c4d2c28a..e9f66b6dec18 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -25,9 +25,9 @@ #include "clock.h" #include "clock3xxx.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-34xx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" /* @@ -94,7 +94,7 @@ static int __init omap3xxx_clk_arch_init(void) ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck"); if (!ret) - omap2_clk_print_new_rates("osc_sys_ck", "arm_fck", "core_ck"); + omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck"); return ret; } diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index d85ecd5aebfd..d3ab1c9e50b0 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -28,9 +28,9 @@ #include "clock36xx.h" #include "clock3517.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-34xx.h" #include "control.h" @@ -120,7 +120,7 @@ static const struct clksel_rate osc_sys_13m_rates[] = { }; static const struct clksel_rate osc_sys_16_8m_rates[] = { - { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS }, + { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 0 } }; @@ -452,35 +452,35 @@ static struct clk dpll3_x2_ck = { static const struct clksel_rate div31_dpll3_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, - { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS }, - { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS }, - { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS }, - { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS }, - { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS }, - { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS }, - { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS }, - { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS }, - { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS }, - { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS }, - { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS }, - { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS }, - { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS }, - { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS }, - { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS }, - { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS }, - { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS }, - { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS }, - { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS }, - { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS }, - { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS }, - { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS }, - { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS }, - { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS }, - { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS }, - { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS }, - { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS }, - { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS }, - { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS }, + { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX }, + { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 0 }, }; @@ -602,6 +602,8 @@ static struct dpll_data dpll4_dd_3630 __initdata = { .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, + .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK, + .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK, .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, @@ -1558,6 +1560,7 @@ static struct clk mcspi4_fck = { .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, .recalc = &followparent_recalc, + .clkdm_name = "core_l4_clkdm", }; static struct clk mcspi3_fck = { @@ -1567,6 +1570,7 @@ static struct clk mcspi3_fck = { .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, .recalc = &followparent_recalc, + .clkdm_name = "core_l4_clkdm", }; static struct clk mcspi2_fck = { @@ -1576,6 +1580,7 @@ static struct clk mcspi2_fck = { .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, .recalc = &followparent_recalc, + .clkdm_name = "core_l4_clkdm", }; static struct clk mcspi1_fck = { @@ -1585,6 +1590,7 @@ static struct clk mcspi1_fck = { .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, .recalc = &followparent_recalc, + .clkdm_name = "core_l4_clkdm", }; static struct clk uart2_fck = { @@ -3044,6 +3050,7 @@ static struct clk sr1_fck = { .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_SR1_SHIFT, + .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -3054,6 +3061,7 @@ static struct clk sr2_fck = { .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_SR2_SHIFT, + .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -3201,7 +3209,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), - CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX), + CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX), CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX), CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), @@ -3218,8 +3226,8 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), - CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), - CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), + CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX), + CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX), CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), CLK(NULL, "core_ck", &core_ck, CK_3XXX), CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), @@ -3248,8 +3256,8 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), - CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_AM35XX), - CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_AM35XX), + CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), @@ -3257,8 +3265,8 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), - CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), - CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), + CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX), + CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX), CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), @@ -3267,27 +3275,28 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), - CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517), - CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517), + CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX), + CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX), CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), - CLK(NULL, "modem_fck", &modem_fck, CK_343X), - CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), - CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), + CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX), + CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX), + CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX), CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), - CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX), - CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX), - CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX), + CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("ehci-omap.0", "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX), CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), - CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX), + CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), - CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), + CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX), - CLK("i2c_omap.3", "fck", &i2c3_fck, CK_3XXX), - CLK("i2c_omap.2", "fck", &i2c2_fck, CK_3XXX), - CLK("i2c_omap.1", "fck", &i2c1_fck, CK_3XXX), + CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX), + CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX), + CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX), CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX), CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX), CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), @@ -3301,34 +3310,35 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), - CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2), + CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX), CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), - CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2), + CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX), CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), - CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), - CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2), + CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), + CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), - CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), - CLK(NULL, "pka_ick", &pka_ick, CK_343X), + CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX), + CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX), CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), - CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX), - CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX), - CLK(NULL, "icr_ick", &icr_ick, CK_343X), - CLK("omap-aes", "ick", &aes2_ick, CK_343X), - CLK("omap-sham", "ick", &sha12_ick, CK_343X), - CLK(NULL, "des2_ick", &des2_ick, CK_343X), + CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), + CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), + CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), + CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), - CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), + CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), - CLK("i2c_omap.3", "ick", &i2c3_ick, CK_3XXX), - CLK("i2c_omap.2", "ick", &i2c2_ick, CK_3XXX), - CLK("i2c_omap.1", "ick", &i2c1_ick, CK_3XXX), + CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX), + CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX), + CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX), CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), @@ -3336,37 +3346,40 @@ static struct omap_clk omap3xxx_clks[] = { CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), - CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX), CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX), CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), - CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2), + CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX), CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), - CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), - CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), - CLK("omap_rng", "ick", &rng_ick, CK_343X), - CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), - CLK(NULL, "des1_ick", &des1_ick, CK_343X), + CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX), + CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX), + CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), + CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), + CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), - CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX), + CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX), CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX), CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX), CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), - CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_AM35XX), - CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), - CLK(NULL, "cam_ick", &cam_ick, CK_343X), - CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), - CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX), - CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX), - CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX), - CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), + CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), + CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), + CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), + CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("ehci-omap.0", "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("ehci-omap.0", "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("ehci-omap.0", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX), CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX), - CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), - CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), + CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX), + CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX), CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), @@ -3424,9 +3437,9 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX), CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX), CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX), - CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), - CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), - CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), + CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX), + CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX), + CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX), CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), @@ -3437,8 +3450,8 @@ static struct omap_clk omap3xxx_clks[] = { CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX), CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), - CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), - CLK("musb_hdrc", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), + CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), + CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), }; @@ -3447,38 +3460,37 @@ static struct omap_clk omap3xxx_clks[] = { int __init omap3xxx_clk_init(void) { struct omap_clk *c; - u32 cpu_clkflg = CK_3XXX; + u32 cpu_clkflg = 0; if (cpu_is_omap3517()) { - cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; - cpu_clkflg |= CK_3517; + cpu_mask = RATE_IN_34XX; + cpu_clkflg = CK_3517; } else if (cpu_is_omap3505()) { - cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; - cpu_clkflg |= CK_3505; + cpu_mask = RATE_IN_34XX; + cpu_clkflg = CK_3505; + } else if (cpu_is_omap3630()) { + cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); + cpu_clkflg = CK_36XX; } else if (cpu_is_omap34xx()) { - cpu_mask = RATE_IN_3XXX; - cpu_clkflg |= CK_343X; - - /* - * Update this if there are further clock changes between ES2 - * and production parts - */ if (omap_rev() == OMAP3430_REV_ES1_0) { - /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ - cpu_clkflg |= CK_3430ES1; + cpu_mask = RATE_IN_3430ES1; + cpu_clkflg = CK_3430ES1; } else { - cpu_mask |= RATE_IN_3430ES2PLUS; - cpu_clkflg |= CK_3430ES2; + /* + * Assume that anything that we haven't matched yet + * has 3430ES2-type clocks. + */ + cpu_mask = RATE_IN_3430ES2PLUS; + cpu_clkflg = CK_3430ES2PLUS; } + } else { + WARN(1, "clock: could not identify OMAP3 variant\n"); } if (omap3_has_192mhz_clk()) omap_96m_alwon_fck = omap_96m_alwon_fck_3630; if (cpu_is_omap3630()) { - cpu_mask |= RATE_IN_36XX; - cpu_clkflg |= CK_36XX; - /* * XXX This type of dynamic rewriting of the clock tree is * deprecated and should be revised soon. @@ -3525,10 +3537,9 @@ int __init omap3xxx_clk_init(void) recalculate_root_clocks(); - printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " - "%ld.%01ld/%ld/%ld MHz\n", - (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, - (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); + pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", + (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, + (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); /* * Only enable those clocks we will need, let the drivers diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 1599836ba3d9..e8cb32fd7f13 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -30,11 +30,18 @@ #include "clock.h" #include "clock44xx.h" -#include "cm.h" +#include "cm1_44xx.h" +#include "cm2_44xx.h" #include "cm-regbits-44xx.h" -#include "prm.h" +#include "prm44xx.h" +#include "prm44xx.h" #include "prm-regbits-44xx.h" #include "control.h" +#include "scrm44xx.h" + +/* OMAP4 modulemode control */ +#define OMAP4430_MODULEMODE_HWCTRL 0 +#define OMAP4430_MODULEMODE_SWCTRL 1 /* Root clocks */ @@ -47,7 +54,9 @@ static struct clk extalt_clkin_ck = { static struct clk pad_clks_ck = { .name = "pad_clks_ck", .rate = 12000000, - .ops = &clkops_null, + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_CLKSEL_ABE, + .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, }; static struct clk pad_slimbus_core_clks_ck = { @@ -65,7 +74,9 @@ static struct clk secure_32k_clk_src_ck = { static struct clk slimbus_clk = { .name = "slimbus_clk", .rate = 12000000, - .ops = &clkops_null, + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_CLKSEL_ABE, + .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, }; static struct clk sys_32k_ck = { @@ -265,18 +276,71 @@ static struct clk dpll_abe_ck = { .set_rate = &omap3_noncore_dpll_set_rate, }; +static struct clk dpll_abe_x2_ck = { + .name = "dpll_abe_x2_ck", + .parent = &dpll_abe_ck, + .ops = &clkops_null, + .recalc = &omap3_clkoutx2_recalc, +}; + +static const struct clksel_rate div31_1to31_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_4430 }, + { .div = 2, .val = 2, .flags = RATE_IN_4430 }, + { .div = 3, .val = 3, .flags = RATE_IN_4430 }, + { .div = 4, .val = 4, .flags = RATE_IN_4430 }, + { .div = 5, .val = 5, .flags = RATE_IN_4430 }, + { .div = 6, .val = 6, .flags = RATE_IN_4430 }, + { .div = 7, .val = 7, .flags = RATE_IN_4430 }, + { .div = 8, .val = 8, .flags = RATE_IN_4430 }, + { .div = 9, .val = 9, .flags = RATE_IN_4430 }, + { .div = 10, .val = 10, .flags = RATE_IN_4430 }, + { .div = 11, .val = 11, .flags = RATE_IN_4430 }, + { .div = 12, .val = 12, .flags = RATE_IN_4430 }, + { .div = 13, .val = 13, .flags = RATE_IN_4430 }, + { .div = 14, .val = 14, .flags = RATE_IN_4430 }, + { .div = 15, .val = 15, .flags = RATE_IN_4430 }, + { .div = 16, .val = 16, .flags = RATE_IN_4430 }, + { .div = 17, .val = 17, .flags = RATE_IN_4430 }, + { .div = 18, .val = 18, .flags = RATE_IN_4430 }, + { .div = 19, .val = 19, .flags = RATE_IN_4430 }, + { .div = 20, .val = 20, .flags = RATE_IN_4430 }, + { .div = 21, .val = 21, .flags = RATE_IN_4430 }, + { .div = 22, .val = 22, .flags = RATE_IN_4430 }, + { .div = 23, .val = 23, .flags = RATE_IN_4430 }, + { .div = 24, .val = 24, .flags = RATE_IN_4430 }, + { .div = 25, .val = 25, .flags = RATE_IN_4430 }, + { .div = 26, .val = 26, .flags = RATE_IN_4430 }, + { .div = 27, .val = 27, .flags = RATE_IN_4430 }, + { .div = 28, .val = 28, .flags = RATE_IN_4430 }, + { .div = 29, .val = 29, .flags = RATE_IN_4430 }, + { .div = 30, .val = 30, .flags = RATE_IN_4430 }, + { .div = 31, .val = 31, .flags = RATE_IN_4430 }, + { .div = 0 }, +}; + +static const struct clksel dpll_abe_m2x2_div[] = { + { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + static struct clk dpll_abe_m2x2_ck = { .name = "dpll_abe_m2x2_ck", - .parent = &dpll_abe_ck, + .parent = &dpll_abe_x2_ck, + .clksel = dpll_abe_m2x2_div, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, + .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, .ops = &clkops_null, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, }; static struct clk abe_24m_fclk = { .name = "abe_24m_fclk", .parent = &dpll_abe_m2x2_ck, .ops = &clkops_null, - .recalc = &followparent_recalc, + .fixed_div = 8, + .recalc = &omap_fixed_divisor_recalc, }; static const struct clksel_rate div3_1to4_rates[] = { @@ -326,50 +390,10 @@ static struct clk aess_fclk = { .set_rate = &omap2_clksel_set_rate, }; -static const struct clksel_rate div31_1to31_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_4430 }, - { .div = 2, .val = 2, .flags = RATE_IN_4430 }, - { .div = 3, .val = 3, .flags = RATE_IN_4430 }, - { .div = 4, .val = 4, .flags = RATE_IN_4430 }, - { .div = 5, .val = 5, .flags = RATE_IN_4430 }, - { .div = 6, .val = 6, .flags = RATE_IN_4430 }, - { .div = 7, .val = 7, .flags = RATE_IN_4430 }, - { .div = 8, .val = 8, .flags = RATE_IN_4430 }, - { .div = 9, .val = 9, .flags = RATE_IN_4430 }, - { .div = 10, .val = 10, .flags = RATE_IN_4430 }, - { .div = 11, .val = 11, .flags = RATE_IN_4430 }, - { .div = 12, .val = 12, .flags = RATE_IN_4430 }, - { .div = 13, .val = 13, .flags = RATE_IN_4430 }, - { .div = 14, .val = 14, .flags = RATE_IN_4430 }, - { .div = 15, .val = 15, .flags = RATE_IN_4430 }, - { .div = 16, .val = 16, .flags = RATE_IN_4430 }, - { .div = 17, .val = 17, .flags = RATE_IN_4430 }, - { .div = 18, .val = 18, .flags = RATE_IN_4430 }, - { .div = 19, .val = 19, .flags = RATE_IN_4430 }, - { .div = 20, .val = 20, .flags = RATE_IN_4430 }, - { .div = 21, .val = 21, .flags = RATE_IN_4430 }, - { .div = 22, .val = 22, .flags = RATE_IN_4430 }, - { .div = 23, .val = 23, .flags = RATE_IN_4430 }, - { .div = 24, .val = 24, .flags = RATE_IN_4430 }, - { .div = 25, .val = 25, .flags = RATE_IN_4430 }, - { .div = 26, .val = 26, .flags = RATE_IN_4430 }, - { .div = 27, .val = 27, .flags = RATE_IN_4430 }, - { .div = 28, .val = 28, .flags = RATE_IN_4430 }, - { .div = 29, .val = 29, .flags = RATE_IN_4430 }, - { .div = 30, .val = 30, .flags = RATE_IN_4430 }, - { .div = 31, .val = 31, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel dpll_abe_m3_div[] = { - { .parent = &dpll_abe_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_abe_m3_ck = { - .name = "dpll_abe_m3_ck", - .parent = &dpll_abe_ck, - .clksel = dpll_abe_m3_div, +static struct clk dpll_abe_m3x2_ck = { + .name = "dpll_abe_m3x2_ck", + .parent = &dpll_abe_x2_ck, + .clksel = dpll_abe_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, .ops = &clkops_null, @@ -380,7 +404,7 @@ static struct clk dpll_abe_m3_ck = { static const struct clksel core_hsd_byp_clk_mux_sel[] = { { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates }, + { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; @@ -424,15 +448,22 @@ static struct clk dpll_core_ck = { .recalc = &omap3_dpll_recalc, }; -static const struct clksel dpll_core_m6_div[] = { - { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, +static struct clk dpll_core_x2_ck = { + .name = "dpll_core_x2_ck", + .parent = &dpll_core_ck, + .ops = &clkops_null, + .recalc = &omap3_clkoutx2_recalc, +}; + +static const struct clksel dpll_core_m6x2_div[] = { + { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, { .parent = NULL }, }; -static struct clk dpll_core_m6_ck = { - .name = "dpll_core_m6_ck", - .parent = &dpll_core_ck, - .clksel = dpll_core_m6_div, +static struct clk dpll_core_m6x2_ck = { + .name = "dpll_core_m6x2_ck", + .parent = &dpll_core_x2_ck, + .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, .ops = &clkops_null, @@ -443,7 +474,7 @@ static struct clk dpll_core_m6_ck = { static const struct clksel dbgclk_mux_sel[] = { { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, + { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; @@ -454,10 +485,15 @@ static struct clk dbgclk_mux_ck = { .recalc = &followparent_recalc, }; +static const struct clksel dpll_core_m2_div[] = { + { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + static struct clk dpll_core_m2_ck = { .name = "dpll_core_m2_ck", .parent = &dpll_core_ck, - .clksel = dpll_core_m6_div, + .clksel = dpll_core_m2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, .ops = &clkops_null, @@ -470,13 +506,14 @@ static struct clk ddrphy_ck = { .name = "ddrphy_ck", .parent = &dpll_core_m2_ck, .ops = &clkops_null, - .recalc = &followparent_recalc, + .fixed_div = 2, + .recalc = &omap_fixed_divisor_recalc, }; -static struct clk dpll_core_m5_ck = { - .name = "dpll_core_m5_ck", - .parent = &dpll_core_ck, - .clksel = dpll_core_m6_div, +static struct clk dpll_core_m5x2_ck = { + .name = "dpll_core_m5x2_ck", + .parent = &dpll_core_x2_ck, + .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, .ops = &clkops_null, @@ -486,13 +523,13 @@ static struct clk dpll_core_m5_ck = { }; static const struct clksel div_core_div[] = { - { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates }, + { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates }, { .parent = NULL }, }; static struct clk div_core_ck = { .name = "div_core_ck", - .parent = &dpll_core_m5_ck, + .parent = &dpll_core_m5x2_ck, .clksel = div_core_div, .clksel_reg = OMAP4430_CM_CLKSEL_CORE, .clksel_mask = OMAP4430_CLKSEL_CORE_MASK, @@ -511,13 +548,13 @@ static const struct clksel_rate div4_1to8_rates[] = { }; static const struct clksel div_iva_hs_clk_div[] = { - { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates }, + { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates }, { .parent = NULL }, }; static struct clk div_iva_hs_clk = { .name = "div_iva_hs_clk", - .parent = &dpll_core_m5_ck, + .parent = &dpll_core_m5x2_ck, .clksel = div_iva_hs_clk_div, .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA, .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, @@ -529,7 +566,7 @@ static struct clk div_iva_hs_clk = { static struct clk div_mpu_hs_clk = { .name = "div_mpu_hs_clk", - .parent = &dpll_core_m5_ck, + .parent = &dpll_core_m5x2_ck, .clksel = div_iva_hs_clk_div, .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU, .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, @@ -539,10 +576,10 @@ static struct clk div_mpu_hs_clk = { .set_rate = &omap2_clksel_set_rate, }; -static struct clk dpll_core_m4_ck = { - .name = "dpll_core_m4_ck", - .parent = &dpll_core_ck, - .clksel = dpll_core_m6_div, +static struct clk dpll_core_m4x2_ck = { + .name = "dpll_core_m4x2_ck", + .parent = &dpll_core_x2_ck, + .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, .ops = &clkops_null, @@ -553,15 +590,21 @@ static struct clk dpll_core_m4_ck = { static struct clk dll_clk_div_ck = { .name = "dll_clk_div_ck", - .parent = &dpll_core_m4_ck, + .parent = &dpll_core_m4x2_ck, .ops = &clkops_null, - .recalc = &followparent_recalc, + .fixed_div = 2, + .recalc = &omap_fixed_divisor_recalc, +}; + +static const struct clksel dpll_abe_m2_div[] = { + { .parent = &dpll_abe_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, }; static struct clk dpll_abe_m2_ck = { .name = "dpll_abe_m2_ck", .parent = &dpll_abe_ck, - .clksel = dpll_abe_m3_div, + .clksel = dpll_abe_m2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, .ops = &clkops_null, @@ -570,22 +613,24 @@ static struct clk dpll_abe_m2_ck = { .set_rate = &omap2_clksel_set_rate, }; -static struct clk dpll_core_m3_ck = { - .name = "dpll_core_m3_ck", - .parent = &dpll_core_ck, - .clksel = dpll_core_m6_div, +static struct clk dpll_core_m3x2_ck = { + .name = "dpll_core_m3x2_ck", + .parent = &dpll_core_x2_ck, + .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, + .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, }; -static struct clk dpll_core_m7_ck = { - .name = "dpll_core_m7_ck", - .parent = &dpll_core_ck, - .clksel = dpll_core_m6_div, +static struct clk dpll_core_m7x2_ck = { + .name = "dpll_core_m7x2_ck", + .parent = &dpll_core_x2_ck, + .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, .ops = &clkops_null, @@ -603,8 +648,12 @@ static const struct clksel iva_hsd_byp_clk_mux_sel[] = { static struct clk iva_hsd_byp_clk_mux_ck = { .name = "iva_hsd_byp_clk_mux_ck", .parent = &sys_clkin_ck, + .clksel = iva_hsd_byp_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, + .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, .ops = &clkops_null, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, }; /* DPLL_IVA */ @@ -638,15 +687,22 @@ static struct clk dpll_iva_ck = { .set_rate = &omap3_noncore_dpll_set_rate, }; -static const struct clksel dpll_iva_m4_div[] = { - { .parent = &dpll_iva_ck, .rates = div31_1to31_rates }, +static struct clk dpll_iva_x2_ck = { + .name = "dpll_iva_x2_ck", + .parent = &dpll_iva_ck, + .ops = &clkops_null, + .recalc = &omap3_clkoutx2_recalc, +}; + +static const struct clksel dpll_iva_m4x2_div[] = { + { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates }, { .parent = NULL }, }; -static struct clk dpll_iva_m4_ck = { - .name = "dpll_iva_m4_ck", - .parent = &dpll_iva_ck, - .clksel = dpll_iva_m4_div, +static struct clk dpll_iva_m4x2_ck = { + .name = "dpll_iva_m4x2_ck", + .parent = &dpll_iva_x2_ck, + .clksel = dpll_iva_m4x2_div, .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, .ops = &clkops_null, @@ -655,10 +711,10 @@ static struct clk dpll_iva_m4_ck = { .set_rate = &omap2_clksel_set_rate, }; -static struct clk dpll_iva_m5_ck = { - .name = "dpll_iva_m5_ck", - .parent = &dpll_iva_ck, - .clksel = dpll_iva_m4_div, +static struct clk dpll_iva_m5x2_ck = { + .name = "dpll_iva_m5x2_ck", + .parent = &dpll_iva_x2_ck, + .clksel = dpll_iva_m4x2_div, .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, .ops = &clkops_null, @@ -717,9 +773,10 @@ static struct clk dpll_mpu_m2_ck = { static struct clk per_hs_clk_div_ck = { .name = "per_hs_clk_div_ck", - .parent = &dpll_abe_m3_ck, + .parent = &dpll_abe_m3x2_ck, .ops = &clkops_null, - .recalc = &followparent_recalc, + .fixed_div = 2, + .recalc = &omap_fixed_divisor_recalc, }; static const struct clksel per_hsd_byp_clk_mux_sel[] = { @@ -787,29 +844,48 @@ static struct clk dpll_per_m2_ck = { .set_rate = &omap2_clksel_set_rate, }; +static struct clk dpll_per_x2_ck = { + .name = "dpll_per_x2_ck", + .parent = &dpll_per_ck, + .ops = &clkops_null, + .recalc = &omap3_clkoutx2_recalc, +}; + +static const struct clksel dpll_per_m2x2_div[] = { + { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + static struct clk dpll_per_m2x2_ck = { .name = "dpll_per_m2x2_ck", - .parent = &dpll_per_ck, + .parent = &dpll_per_x2_ck, + .clksel = dpll_per_m2x2_div, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, + .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, .ops = &clkops_null, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, }; -static struct clk dpll_per_m3_ck = { - .name = "dpll_per_m3_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, +static struct clk dpll_per_m3x2_ck = { + .name = "dpll_per_m3x2_ck", + .parent = &dpll_per_x2_ck, + .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER, + .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, }; -static struct clk dpll_per_m4_ck = { - .name = "dpll_per_m4_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, +static struct clk dpll_per_m4x2_ck = { + .name = "dpll_per_m4x2_ck", + .parent = &dpll_per_x2_ck, + .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, .ops = &clkops_null, @@ -818,10 +894,10 @@ static struct clk dpll_per_m4_ck = { .set_rate = &omap2_clksel_set_rate, }; -static struct clk dpll_per_m5_ck = { - .name = "dpll_per_m5_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, +static struct clk dpll_per_m5x2_ck = { + .name = "dpll_per_m5x2_ck", + .parent = &dpll_per_x2_ck, + .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, .ops = &clkops_null, @@ -830,10 +906,10 @@ static struct clk dpll_per_m5_ck = { .set_rate = &omap2_clksel_set_rate, }; -static struct clk dpll_per_m6_ck = { - .name = "dpll_per_m6_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, +static struct clk dpll_per_m6x2_ck = { + .name = "dpll_per_m6x2_ck", + .parent = &dpll_per_x2_ck, + .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, .ops = &clkops_null, @@ -842,10 +918,10 @@ static struct clk dpll_per_m6_ck = { .set_rate = &omap2_clksel_set_rate, }; -static struct clk dpll_per_m7_ck = { - .name = "dpll_per_m7_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, +static struct clk dpll_per_m7x2_ck = { + .name = "dpll_per_m7x2_ck", + .parent = &dpll_per_x2_ck, + .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, .ops = &clkops_null, @@ -868,6 +944,7 @@ static struct dpll_data dpll_unipro_dd = { .enable_mask = OMAP4430_DPLL_EN_MASK, .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, .max_multiplier = OMAP4430_MAX_DPLL_MULT, .max_divider = OMAP4430_MAX_DPLL_DIV, .min_divider = 1, @@ -885,14 +962,21 @@ static struct clk dpll_unipro_ck = { .set_rate = &omap3_noncore_dpll_set_rate, }; +static struct clk dpll_unipro_x2_ck = { + .name = "dpll_unipro_x2_ck", + .parent = &dpll_unipro_ck, + .ops = &clkops_null, + .recalc = &omap3_clkoutx2_recalc, +}; + static const struct clksel dpll_unipro_m2x2_div[] = { - { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates }, + { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates }, { .parent = NULL }, }; static struct clk dpll_unipro_m2x2_ck = { .name = "dpll_unipro_m2x2_ck", - .parent = &dpll_unipro_ck, + .parent = &dpll_unipro_x2_ck, .clksel = dpll_unipro_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, @@ -904,16 +988,17 @@ static struct clk dpll_unipro_m2x2_ck = { static struct clk usb_hs_clk_div_ck = { .name = "usb_hs_clk_div_ck", - .parent = &dpll_abe_m3_ck, + .parent = &dpll_abe_m3x2_ck, .ops = &clkops_null, - .recalc = &followparent_recalc, + .fixed_div = 3, + .recalc = &omap_fixed_divisor_recalc, }; /* DPLL_USB */ static struct dpll_data dpll_usb_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, .clk_bypass = &usb_hs_clk_div_ck, - .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL, + .flags = DPLL_J_TYPE, .clk_ref = &sys_clkin_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), @@ -967,7 +1052,7 @@ static struct clk dpll_usb_m2_ck = { static const struct clksel ducati_clk_mux_sel[] = { { .parent = &div_core_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates }, + { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; @@ -986,21 +1071,24 @@ static struct clk func_12m_fclk = { .name = "func_12m_fclk", .parent = &dpll_per_m2x2_ck, .ops = &clkops_null, - .recalc = &followparent_recalc, + .fixed_div = 16, + .recalc = &omap_fixed_divisor_recalc, }; static struct clk func_24m_clk = { .name = "func_24m_clk", .parent = &dpll_per_m2_ck, .ops = &clkops_null, - .recalc = &followparent_recalc, + .fixed_div = 4, + .recalc = &omap_fixed_divisor_recalc, }; static struct clk func_24mc_fclk = { .name = "func_24mc_fclk", .parent = &dpll_per_m2x2_ck, .ops = &clkops_null, - .recalc = &followparent_recalc, + .fixed_div = 8, + .recalc = &omap_fixed_divisor_recalc, }; static const struct clksel_rate div2_4to8_rates[] = { @@ -1030,7 +1118,8 @@ static struct clk func_48mc_fclk = { .name = "func_48mc_fclk", .parent = &dpll_per_m2x2_ck, .ops = &clkops_null, - .recalc = &followparent_recalc, + .fixed_div = 4, + .recalc = &omap_fixed_divisor_recalc, }; static const struct clksel_rate div2_2to4_rates[] = { @@ -1040,13 +1129,13 @@ static const struct clksel_rate div2_2to4_rates[] = { }; static const struct clksel func_64m_fclk_div[] = { - { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates }, + { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates }, { .parent = NULL }, }; static struct clk func_64m_fclk = { .name = "func_64m_fclk", - .parent = &dpll_per_m4_ck, + .parent = &dpll_per_m4x2_ck, .clksel = func_64m_fclk_div, .clksel_reg = OMAP4430_CM_SCALE_FCLK, .clksel_mask = OMAP4430_SCALE_FCLK_MASK, @@ -1147,7 +1236,8 @@ static struct clk lp_clk_div_ck = { .name = "lp_clk_div_ck", .parent = &dpll_abe_m2x2_ck, .ops = &clkops_null, - .recalc = &followparent_recalc, + .fixed_div = 16, + .recalc = &omap_fixed_divisor_recalc, }; static const struct clksel l4_wkup_clk_mux_sel[] = { @@ -1215,12 +1305,13 @@ static struct clk per_abe_24m_fclk = { .name = "per_abe_24m_fclk", .parent = &dpll_abe_m2_ck, .ops = &clkops_null, - .recalc = &followparent_recalc, + .fixed_div = 4, + .recalc = &omap_fixed_divisor_recalc, }; static const struct clksel pmd_stm_clock_mux_sel[] = { { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, + { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, { .parent = NULL }, }; @@ -1354,7 +1445,7 @@ static struct clk dsp_fck = { .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "tesla_clkdm", - .parent = &dpll_iva_m4_ck, + .parent = &dpll_iva_m4x2_ck, .recalc = &followparent_recalc, }; @@ -1384,7 +1475,7 @@ static struct clk dss_dss_clk = { .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, .clkdm_name = "l3_dss_clkdm", - .parent = &dpll_per_m5_ck, + .parent = &dpll_per_m5x2_ck, .recalc = &followparent_recalc, }; @@ -1441,14 +1532,14 @@ static struct clk emif2_fck = { }; static const struct clksel fdif_fclk_div[] = { - { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates }, + { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates }, { .parent = NULL }, }; /* Merged fdif_fclk into fdif */ static struct clk fdif_fck = { .name = "fdif_fck", - .parent = &dpll_per_m4_ck, + .parent = &dpll_per_m4x2_ck, .clksel = fdif_fclk_div, .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, @@ -1602,15 +1693,15 @@ static struct clk gpmc_ick = { }; static const struct clksel sgx_clk_mux_sel[] = { - { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates }, + { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, + { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; /* Merged sgx_clk_mux into gpu */ static struct clk gpu_fck = { .name = "gpu_fck", - .parent = &dpll_core_m7_ck, + .parent = &dpll_core_m7x2_ck, .clksel = sgx_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, @@ -1729,7 +1820,7 @@ static struct clk iva_fck = { .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "ivahd_clkdm", - .parent = &dpll_iva_m5_ck, + .parent = &dpll_iva_m5x2_ck, .recalc = &followparent_recalc, }; @@ -1749,6 +1840,7 @@ static struct clk l3_instr_ick = { .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_instr_clkdm", + .flags = ENABLE_ON_INIT, .parent = &l3_div_ck, .recalc = &followparent_recalc, }; @@ -1759,6 +1851,7 @@ static struct clk l3_main_3_ick = { .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_instr_clkdm", + .flags = ENABLE_ON_INIT, .parent = &l3_div_ck, .recalc = &followparent_recalc, }; @@ -2063,6 +2156,7 @@ static struct clk ocp_wp_noc_ick = { .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_instr_clkdm", + .flags = ENABLE_ON_INIT, .parent = &l3_div_ck, .recalc = &followparent_recalc, }; @@ -2093,7 +2187,7 @@ static struct clk sl2if_ick = { .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "ivahd_clkdm", - .parent = &dpll_iva_m5_ck, + .parent = &dpll_iva_m5x2_ck, .recalc = &followparent_recalc, }; @@ -2438,36 +2532,6 @@ static struct clk usb_host_fs_fck = { .recalc = &followparent_recalc, }; -static struct clk usb_host_hs_utmi_p3_clk = { - .name = "usb_host_hs_utmi_p3_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_hsic60m_p1_clk = { - .name = "usb_host_hs_hsic60m_p1_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_hsic60m_p2_clk = { - .name = "usb_host_hs_hsic60m_p2_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - static const struct clksel utmi_p1_gfclk_sel[] = { { .parent = &init_60m_fclk, .rates = div_1_0_rates }, { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, @@ -2522,6 +2586,16 @@ static struct clk usb_host_hs_utmi_p2_clk = { .recalc = &followparent_recalc, }; +static struct clk usb_host_hs_utmi_p3_clk = { + .name = "usb_host_hs_utmi_p3_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &init_60m_fclk, + .recalc = &followparent_recalc, +}; + static struct clk usb_host_hs_hsic480m_p1_clk = { .name = "usb_host_hs_hsic480m_p1_clk", .ops = &clkops_omap2_dflt, @@ -2532,6 +2606,26 @@ static struct clk usb_host_hs_hsic480m_p1_clk = { .recalc = &followparent_recalc, }; +static struct clk usb_host_hs_hsic60m_p1_clk = { + .name = "usb_host_hs_hsic60m_p1_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &init_60m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk usb_host_hs_hsic60m_p2_clk = { + .name = "usb_host_hs_hsic60m_p2_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &init_60m_fclk, + .recalc = &followparent_recalc, +}; + static struct clk usb_host_hs_hsic480m_p2_clk = { .name = "usb_host_hs_hsic480m_p2_clk", .ops = &clkops_omap2_dflt, @@ -2656,13 +2750,13 @@ static const struct clksel_rate div2_14to18_rates[] = { }; static const struct clksel usim_fclk_div[] = { - { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates }, + { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates }, { .parent = NULL }, }; static struct clk usim_ck = { .name = "usim_ck", - .parent = &dpll_per_m4_ck, + .parent = &dpll_per_m4x2_ck, .clksel = usim_fclk_div, .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_DIV_MASK, @@ -2747,6 +2841,168 @@ static struct clk trace_clk_div_ck = { .set_rate = &omap2_clksel_set_rate, }; +/* SCRM aux clk nodes */ + +static const struct clksel auxclk_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, + { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static struct clk auxclk0_ck = { + .name = "auxclk0_ck", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_omap2_dflt, + .clksel = auxclk_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK0, + .clksel_mask = OMAP4_SRCSELECT_MASK, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4_SCRM_AUXCLK0, + .enable_bit = OMAP4_ENABLE_SHIFT, +}; + +static struct clk auxclk1_ck = { + .name = "auxclk1_ck", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_omap2_dflt, + .clksel = auxclk_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK1, + .clksel_mask = OMAP4_SRCSELECT_MASK, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4_SCRM_AUXCLK1, + .enable_bit = OMAP4_ENABLE_SHIFT, +}; + +static struct clk auxclk2_ck = { + .name = "auxclk2_ck", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_omap2_dflt, + .clksel = auxclk_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK2, + .clksel_mask = OMAP4_SRCSELECT_MASK, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4_SCRM_AUXCLK2, + .enable_bit = OMAP4_ENABLE_SHIFT, +}; +static struct clk auxclk3_ck = { + .name = "auxclk3_ck", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_omap2_dflt, + .clksel = auxclk_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK3, + .clksel_mask = OMAP4_SRCSELECT_MASK, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4_SCRM_AUXCLK3, + .enable_bit = OMAP4_ENABLE_SHIFT, +}; + +static struct clk auxclk4_ck = { + .name = "auxclk4_ck", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_omap2_dflt, + .clksel = auxclk_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK4, + .clksel_mask = OMAP4_SRCSELECT_MASK, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4_SCRM_AUXCLK4, + .enable_bit = OMAP4_ENABLE_SHIFT, +}; + +static struct clk auxclk5_ck = { + .name = "auxclk5_ck", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_omap2_dflt, + .clksel = auxclk_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK5, + .clksel_mask = OMAP4_SRCSELECT_MASK, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4_SCRM_AUXCLK5, + .enable_bit = OMAP4_ENABLE_SHIFT, +}; + +static const struct clksel auxclkreq_sel[] = { + { .parent = &auxclk0_ck, .rates = div_1_0_rates }, + { .parent = &auxclk1_ck, .rates = div_1_1_rates }, + { .parent = &auxclk2_ck, .rates = div_1_2_rates }, + { .parent = &auxclk3_ck, .rates = div_1_3_rates }, + { .parent = &auxclk4_ck, .rates = div_1_4_rates }, + { .parent = &auxclk5_ck, .rates = div_1_5_rates }, + { .parent = NULL }, +}; + +static struct clk auxclkreq0_ck = { + .name = "auxclkreq0_ck", + .parent = &auxclk0_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_null, + .clksel = auxclkreq_sel, + .clksel_reg = OMAP4_SCRM_AUXCLKREQ0, + .clksel_mask = OMAP4_MAPPING_MASK, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk auxclkreq1_ck = { + .name = "auxclkreq1_ck", + .parent = &auxclk1_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_null, + .clksel = auxclkreq_sel, + .clksel_reg = OMAP4_SCRM_AUXCLKREQ1, + .clksel_mask = OMAP4_MAPPING_MASK, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk auxclkreq2_ck = { + .name = "auxclkreq2_ck", + .parent = &auxclk2_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_null, + .clksel = auxclkreq_sel, + .clksel_reg = OMAP4_SCRM_AUXCLKREQ2, + .clksel_mask = OMAP4_MAPPING_MASK, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk auxclkreq3_ck = { + .name = "auxclkreq3_ck", + .parent = &auxclk3_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_null, + .clksel = auxclkreq_sel, + .clksel_reg = OMAP4_SCRM_AUXCLKREQ3, + .clksel_mask = OMAP4_MAPPING_MASK, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk auxclkreq4_ck = { + .name = "auxclkreq4_ck", + .parent = &auxclk4_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_null, + .clksel = auxclkreq_sel, + .clksel_reg = OMAP4_SCRM_AUXCLKREQ4, + .clksel_mask = OMAP4_MAPPING_MASK, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk auxclkreq5_ck = { + .name = "auxclkreq5_ck", + .parent = &auxclk5_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_null, + .clksel = auxclkreq_sel, + .clksel_reg = OMAP4_SCRM_AUXCLKREQ5, + .clksel_mask = OMAP4_MAPPING_MASK, + .recalc = &omap2_clksel_recalc, +}; + /* * clkdev */ @@ -2774,43 +3030,48 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), + CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), CLK(NULL, "abe_clk", &abe_clk, CK_443X), CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), - CLK(NULL, "dpll_abe_m3_ck", &dpll_abe_m3_ck, CK_443X), + CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), - CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_443X), + CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), + CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), - CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_443X), + CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), - CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_443X), + CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), - CLK(NULL, "dpll_core_m3_ck", &dpll_core_m3_ck, CK_443X), - CLK(NULL, "dpll_core_m7_ck", &dpll_core_m7_ck, CK_443X), + CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), + CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), - CLK(NULL, "dpll_iva_m4_ck", &dpll_iva_m4_ck, CK_443X), - CLK(NULL, "dpll_iva_m5_ck", &dpll_iva_m5_ck, CK_443X), + CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), + CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), + CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), + CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), - CLK(NULL, "dpll_per_m3_ck", &dpll_per_m3_ck, CK_443X), - CLK(NULL, "dpll_per_m4_ck", &dpll_per_m4_ck, CK_443X), - CLK(NULL, "dpll_per_m5_ck", &dpll_per_m5_ck, CK_443X), - CLK(NULL, "dpll_per_m6_ck", &dpll_per_m6_ck, CK_443X), - CLK(NULL, "dpll_per_m7_ck", &dpll_per_m7_ck, CK_443X), + CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), + CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), + CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), + CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), + CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X), + CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X), CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X), CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), @@ -2856,26 +3117,26 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), - CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X), + CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), - CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X), + CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), - CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X), + CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), - CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X), + CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), - CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X), + CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), - CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X), + CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), - CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X), - CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X), - CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X), - CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X), + CLK("omap_i2c.1", "fck", &i2c1_fck, CK_443X), + CLK("omap_i2c.2", "fck", &i2c2_fck, CK_443X), + CLK("omap_i2c.3", "fck", &i2c3_fck, CK_443X), + CLK("omap_i2c.4", "fck", &i2c4_fck, CK_443X), CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), CLK(NULL, "iss_fck", &iss_fck, CK_443X), @@ -2937,29 +3198,35 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), + CLK("ehci-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X), CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), + CLK("ehci-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X), + CLK("ehci-omap.0", "usbhost_ick", &dummy_ck, CK_443X), CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), - CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X), + CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), + CLK("ehci-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X), + CLK("ehci-omap.0", "usbtll_fck", &dummy_ck, CK_443X), CLK(NULL, "usim_ck", &usim_ck, CK_443X), CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), CLK(NULL, "usim_fck", &usim_fck, CK_443X), CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), + CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), @@ -2975,10 +3242,10 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X), CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X), CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X), - CLK("i2c_omap.1", "ick", &dummy_ck, CK_443X), - CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X), - CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X), - CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), @@ -2997,6 +3264,18 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), CLK("omap_wdt", "ick", &dummy_ck, CK_443X), + CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), + CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), + CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), + CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), + CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), + CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), + CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), + CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), + CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), + CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), + CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), + CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), }; int __init omap4xxx_clk_init(void) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 6fb61b1a0d46..e20b98636ab4 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -13,7 +13,6 @@ */ #undef DEBUG -#include <linux/module.h> #include <linux/kernel.h> #include <linux/device.h> #include <linux/list.h> @@ -27,13 +26,16 @@ #include <linux/bitops.h> -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" +#include "cm-regbits-24xx.h" +#include "cminst44xx.h" +#include "prcm44xx.h" #include <plat/clock.h> -#include <plat/powerdomain.h> -#include <plat/clockdomain.h> +#include "powerdomain.h" +#include "clockdomain.h" #include <plat/prcm.h> /* clkdm_list contains all registered struct clockdomains */ @@ -141,6 +143,9 @@ static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm, * clockdomain is in hardware-supervised mode. Meant to be called * once at clockdomain layer initialization, since these should remain * fixed for a particular architecture. No return value. + * + * XXX autodeps are deprecated and should be removed at the earliest + * opportunity */ static void _autodep_lookup(struct clkdm_autodep *autodep) { @@ -168,6 +173,9 @@ static void _autodep_lookup(struct clkdm_autodep *autodep) * Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm' * in hardware-supervised mode. Meant to be called from clock framework * when a clock inside clockdomain 'clkdm' is enabled. No return value. + * + * XXX autodeps are deprecated and should be removed at the earliest + * opportunity */ static void _clkdm_add_autodeps(struct clockdomain *clkdm) { @@ -199,6 +207,9 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm) * Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm' * in hardware-supervised mode. Meant to be called from clock framework * when a clock inside clockdomain 'clkdm' is disabled. No return value. + * + * XXX autodeps are deprecated and should be removed at the earliest + * opportunity */ static void _clkdm_del_autodeps(struct clockdomain *clkdm) { @@ -223,39 +234,56 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm) } } -/* - * _omap2_clkdm_set_hwsup - set the hwsup idle transition bit +/** + * _enable_hwsup - place a clockdomain into hardware-supervised idle * @clkdm: struct clockdomain * - * @enable: int 0 to disable, 1 to enable * - * Internal helper for actually switching the bit that controls hwsup - * idle transitions for clkdm. + * Place the clockdomain into hardware-supervised idle mode. No return + * value. + * + * XXX Should this return an error if the clockdomain does not support + * hardware-supervised idle mode? */ -static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable) +static void _enable_hwsup(struct clockdomain *clkdm) { - u32 bits, v; - - if (cpu_is_omap24xx()) { - if (enable) - bits = OMAP24XX_CLKSTCTRL_ENABLE_AUTO; - else - bits = OMAP24XX_CLKSTCTRL_DISABLE_AUTO; - } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { - if (enable) - bits = OMAP34XX_CLKSTCTRL_ENABLE_AUTO; - else - bits = OMAP34XX_CLKSTCTRL_DISABLE_AUTO; - } else { + if (cpu_is_omap24xx()) + omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + else if (cpu_is_omap34xx()) + omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + else if (cpu_is_omap44xx()) + return omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, + clkdm->cm_inst, + clkdm->clkdm_offs); + else BUG(); - } - - bits = bits << __ffs(clkdm->clktrctrl_mask); - - v = __raw_readl(clkdm->clkstctrl_reg); - v &= ~(clkdm->clktrctrl_mask); - v |= bits; - __raw_writel(v, clkdm->clkstctrl_reg); +} +/** + * _disable_hwsup - place a clockdomain into software-supervised idle + * @clkdm: struct clockdomain * + * + * Place the clockdomain @clkdm into software-supervised idle mode. + * No return value. + * + * XXX Should this return an error if the clockdomain does not support + * software-supervised idle mode? + */ +static void _disable_hwsup(struct clockdomain *clkdm) +{ + if (cpu_is_omap24xx()) + omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + else if (cpu_is_omap34xx()) + omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + else if (cpu_is_omap44xx()) + return omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition, + clkdm->cm_inst, + clkdm->clkdm_offs); + else + BUG(); } /* Public functions */ @@ -409,7 +437,7 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) pr_debug("clockdomain: hardware will wake up %s when %s wakes " "up\n", clkdm1->name, clkdm2->name); - prm_set_mod_reg_bits((1 << clkdm2->dep_bit), + omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit), clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); } @@ -444,7 +472,7 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) pr_debug("clockdomain: hardware will no longer wake up %s " "after %s wakes up\n", clkdm1->name, clkdm2->name); - prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), + omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); } @@ -480,7 +508,7 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) } /* XXX It's faster to return the atomic wkdep_usecount */ - return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP, + return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP, (1 << clkdm2->dep_bit)); } @@ -514,7 +542,7 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) atomic_set(&cd->wkdep_usecount, 0); } - prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP); + omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP); return 0; } @@ -553,7 +581,7 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) pr_debug("clockdomain: will prevent %s from sleeping if %s " "is active\n", clkdm1->name, clkdm2->name); - cm_set_mod_reg_bits((1 << clkdm2->dep_bit), + omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit), clkdm1->pwrdm.ptr->prcm_offs, OMAP3430_CM_SLEEPDEP); } @@ -596,7 +624,7 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) "sleeping if %s is active\n", clkdm1->name, clkdm2->name); - cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), + omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), clkdm1->pwrdm.ptr->prcm_offs, OMAP3430_CM_SLEEPDEP); } @@ -639,7 +667,7 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) } /* XXX It's faster to return the atomic sleepdep_usecount */ - return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, + return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit)); } @@ -677,35 +705,13 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) atomic_set(&cd->sleepdep_usecount, 0); } - prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, + omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, OMAP3430_CM_SLEEPDEP); return 0; } /** - * omap2_clkdm_clktrctrl_read - read the clkdm's current state transition mode - * @clkdm: struct clkdm * of a clockdomain - * - * Return the clockdomain @clkdm current state transition mode from the - * corresponding domain CM_CLKSTCTRL register. Returns -EINVAL if @clkdm - * is NULL or the current mode upon success. - */ -static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm) -{ - u32 v; - - if (!clkdm) - return -EINVAL; - - v = __raw_readl(clkdm->clkstctrl_reg); - v &= clkdm->clktrctrl_mask; - v >>= __ffs(clkdm->clktrctrl_mask); - - return v; -} - -/** * omap2_clkdm_sleep - force clockdomain sleep transition * @clkdm: struct clockdomain * * @@ -729,18 +735,19 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) if (cpu_is_omap24xx()) { - cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, + omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); - } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { + } else if (cpu_is_omap34xx()) { + + omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); - u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP << - __ffs(clkdm->clktrctrl_mask)); + } else if (cpu_is_omap44xx()) { - u32 v = __raw_readl(clkdm->clkstctrl_reg); - v &= ~(clkdm->clktrctrl_mask); - v |= bits; - __raw_writel(v, clkdm->clkstctrl_reg); + omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition, + clkdm->cm_inst, + clkdm->clkdm_offs); } else { BUG(); @@ -773,18 +780,19 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) if (cpu_is_omap24xx()) { - cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, + omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); - } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { + } else if (cpu_is_omap34xx()) { - u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP << - __ffs(clkdm->clktrctrl_mask)); + omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); - u32 v = __raw_readl(clkdm->clkstctrl_reg); - v &= ~(clkdm->clktrctrl_mask); - v |= bits; - __raw_writel(v, clkdm->clkstctrl_reg); + } else if (cpu_is_omap44xx()) { + + omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition, + clkdm->cm_inst, + clkdm->clkdm_offs); } else { BUG(); @@ -829,7 +837,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm) _clkdm_add_autodeps(clkdm); } - _omap2_clkdm_set_hwsup(clkdm, 1); + _enable_hwsup(clkdm); pwrdm_clkdm_state_switch(clkdm); } @@ -857,7 +865,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm) pr_debug("clockdomain: disabling automatic idle transitions for %s\n", clkdm->name); - _omap2_clkdm_set_hwsup(clkdm, 0); + _disable_hwsup(clkdm); /* * XXX This should be removed once TI adds wakeup/sleep @@ -891,7 +899,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm) */ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) { - int v; + bool hwsup = false; /* * XXX Rewrite this code to maintain a list of enabled @@ -909,17 +917,27 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name, clk->name); - if (!clkdm->clkstctrl_reg) - return 0; + if (cpu_is_omap24xx() || cpu_is_omap34xx()) { - v = omap2_clkdm_clktrctrl_read(clkdm); + if (!clkdm->clktrctrl_mask) + return 0; - if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) || - (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) { + hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + + } else if (cpu_is_omap44xx()) { + + hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, + clkdm->cm_inst, + clkdm->clkdm_offs); + + } + + if (hwsup) { /* Disable HW transitions when we are changing deps */ - _omap2_clkdm_set_hwsup(clkdm, 0); + _disable_hwsup(clkdm); _clkdm_add_autodeps(clkdm); - _omap2_clkdm_set_hwsup(clkdm, 1); + _enable_hwsup(clkdm); } else { omap2_clkdm_wakeup(clkdm); } @@ -946,7 +964,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) */ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) { - int v; + bool hwsup = false; /* * XXX Rewrite this code to maintain a list of enabled @@ -971,17 +989,27 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name, clk->name); - if (!clkdm->clkstctrl_reg) - return 0; + if (cpu_is_omap24xx() || cpu_is_omap34xx()) { - v = omap2_clkdm_clktrctrl_read(clkdm); + if (!clkdm->clktrctrl_mask) + return 0; + + hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + + } else if (cpu_is_omap44xx()) { + + hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, + clkdm->cm_inst, + clkdm->clkdm_offs); + + } - if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) || - (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) { + if (hwsup) { /* Disable HW transitions when we are changing deps */ - _omap2_clkdm_set_hwsup(clkdm, 0); + _disable_hwsup(clkdm); _clkdm_del_autodeps(clkdm); - _omap2_clkdm_set_hwsup(clkdm, 1); + _enable_hwsup(clkdm); } else { omap2_clkdm_sleep(clkdm); } diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h new file mode 100644 index 000000000000..de3faa20b46b --- /dev/null +++ b/arch/arm/mach-omap2/clockdomain.h @@ -0,0 +1,149 @@ +/* + * arch/arm/plat-omap/include/mach/clockdomain.h + * + * OMAP2/3 clockdomain framework functions + * + * Copyright (C) 2008 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation + * + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H +#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H + +#include <linux/init.h> + +#include "powerdomain.h" +#include <plat/clock.h> +#include <plat/cpu.h> + +/* Clockdomain capability flags */ +#define CLKDM_CAN_FORCE_SLEEP (1 << 0) +#define CLKDM_CAN_FORCE_WAKEUP (1 << 1) +#define CLKDM_CAN_ENABLE_AUTO (1 << 2) +#define CLKDM_CAN_DISABLE_AUTO (1 << 3) + +#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) +#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) +#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP) + +/** + * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode + * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only + * @omap_chip: OMAP chip types that this autodep is valid on + * + * A clockdomain that should have wkdeps and sleepdeps added when a + * clockdomain should stay active in hwsup mode; and conversely, + * removed when the clockdomain should be allowed to go inactive in + * hwsup mode. + * + * Autodeps are deprecated and should be removed after + * omap_hwmod-based fine-grained module idle control is added. + */ +struct clkdm_autodep { + union { + const char *name; + struct clockdomain *ptr; + } clkdm; + const struct omap_chip_id omap_chip; +}; + +/** + * struct clkdm_dep - encode dependencies between clockdomains + * @clkdm_name: clockdomain name + * @clkdm: pointer to the struct clockdomain of @clkdm_name + * @omap_chip: OMAP chip types that this dependency is valid on + * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake + * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle + * + * Statically defined. @clkdm is resolved from @clkdm_name at runtime and + * should not be pre-initialized. + * + * XXX Should also include hardware (fixed) dependencies. + */ +struct clkdm_dep { + const char *clkdm_name; + struct clockdomain *clkdm; + atomic_t wkdep_usecount; + atomic_t sleepdep_usecount; + const struct omap_chip_id omap_chip; +}; + +/** + * struct clockdomain - OMAP clockdomain + * @name: clockdomain name + * @pwrdm: powerdomain containing this clockdomain + * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain + * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg + * @flags: Clockdomain capability flags + * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit + * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers + * @cm_inst: (OMAP4 only) CM instance register offset + * @clkdm_offs: (OMAP4 only) CM clockdomain register offset + * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up + * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact + * @omap_chip: OMAP chip types that this clockdomain is valid on + * @usecount: Usecount tracking + * @node: list_head to link all clockdomains together + * + * @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only) + * @cm_inst should be a macro ending in _INST from the OMAP4 CM instance + * definitions (OMAP4 only) + * @clkdm_offs should be a macro ending in _CDOFFS from the OMAP4 CM instance + * definitions (OMAP4 only) + */ +struct clockdomain { + const char *name; + union { + const char *name; + struct powerdomain *ptr; + } pwrdm; +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) + const u16 clktrctrl_mask; +#endif + const u8 flags; + const u8 dep_bit; + const u8 prcm_partition; + const s16 cm_inst; + const u16 clkdm_offs; + struct clkdm_dep *wkdep_srcs; + struct clkdm_dep *sleepdep_srcs; + const struct omap_chip_id omap_chip; + atomic_t usecount; + struct list_head node; +}; + +void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps); +struct clockdomain *clkdm_lookup(const char *name); + +int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), + void *user); +struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm); + +int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_clear_all_wkdeps(struct clockdomain *clkdm); +int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); + +void omap2_clkdm_allow_idle(struct clockdomain *clkdm); +void omap2_clkdm_deny_idle(struct clockdomain *clkdm); + +int omap2_clkdm_wakeup(struct clockdomain *clkdm); +int omap2_clkdm_sleep(struct clockdomain *clkdm); + +int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); +int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); + +extern void __init omap2_clockdomains_init(void); +extern void __init omap44xx_clockdomains_init(void); + +#endif diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c index 8fc19ff2cd89..e4a7133ea3b3 100644 --- a/arch/arm/mach-omap2/clockdomains.h +++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c @@ -4,7 +4,7 @@ * Copyright (C) 2008-2009 Texas Instruments, Inc. * Copyright (C) 2008-2010 Nokia Corporation * - * Written by Paul Walmsley and Jouni Högander + * Paul Walmsley, Jouni Högander * * This file contains clockdomains and clockdomain wakeup/sleep * dependencies for the OMAP2/3 chips. Some notes: @@ -32,12 +32,17 @@ * from the Power domain framework */ -#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H -#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H +#include <linux/kernel.h> +#include <linux/io.h> -#include <plat/clockdomain.h> -#include "cm.h" -#include "prm.h" +#include "clockdomain.h" +#include "prm2xxx_3xxx.h" +#include "cm2xxx_3xxx.h" +#include "cm-regbits-24xx.h" +#include "cm-regbits-34xx.h" +#include "cm-regbits-44xx.h" +#include "prm-regbits-24xx.h" +#include "prm-regbits-34xx.h" /* * Clockdomain dependencies for wkdeps/sleepdeps @@ -84,8 +89,6 @@ static struct clkdm_dep gfx_sgx_wkdeps[] = { /* 24XX-specific possible dependencies */ -#ifdef CONFIG_ARCH_OMAP2 - /* Wakeup dependency source arrays */ /* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */ @@ -165,8 +168,6 @@ static struct clkdm_dep core_24xx_wkdeps[] = { { NULL }, }; -#endif - /* 2430-specific possible wakeup dependencies */ @@ -425,8 +426,6 @@ static struct clkdm_dep gfx_sgx_sleepdeps[] = { * sys_clkout/sys_clkout2. */ -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - /* This is an implicit clockdomain - it is never defined as such in TRM */ static struct clockdomain wkup_clkdm = { .name = "wkup_clkdm", @@ -447,8 +446,6 @@ static struct clockdomain cm_clkdm = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), }; -#endif - /* * 2420-only clockdomains */ @@ -459,7 +456,6 @@ static struct clockdomain mpu_2420_clkdm = { .name = "mpu_clkdm", .pwrdm = { .name = "mpu_pwrdm" }, .flags = CLKDM_CAN_HWSUP, - .clkstctrl_reg = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL), .wkdep_srcs = mpu_24xx_wkdeps, .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), @@ -469,8 +465,6 @@ static struct clockdomain iva1_2420_clkdm = { .name = "iva1_clkdm", .pwrdm = { .name = "dsp_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD, - OMAP2_CM_CLKSTCTRL), .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, .wkdep_srcs = dsp_24xx_wkdeps, .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, @@ -481,8 +475,6 @@ static struct clockdomain dsp_2420_clkdm = { .name = "dsp_clkdm", .pwrdm = { .name = "dsp_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD, - OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; @@ -491,7 +483,6 @@ static struct clockdomain gfx_2420_clkdm = { .name = "gfx_clkdm", .pwrdm = { .name = "gfx_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), .wkdep_srcs = gfx_sgx_wkdeps, .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), @@ -501,7 +492,6 @@ static struct clockdomain core_l3_2420_clkdm = { .name = "core_l3_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, - .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .wkdep_srcs = core_24xx_wkdeps, .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), @@ -511,7 +501,6 @@ static struct clockdomain core_l4_2420_clkdm = { .name = "core_l4_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, - .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .wkdep_srcs = core_24xx_wkdeps, .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), @@ -521,7 +510,6 @@ static struct clockdomain dss_2420_clkdm = { .name = "dss_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, - .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; @@ -539,8 +527,6 @@ static struct clockdomain mpu_2430_clkdm = { .name = "mpu_clkdm", .pwrdm = { .name = "mpu_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP2430_CM_REGADDR(MPU_MOD, - OMAP2_CM_CLKSTCTRL), .wkdep_srcs = mpu_24xx_wkdeps, .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), @@ -551,8 +537,6 @@ static struct clockdomain mdm_clkdm = { .name = "mdm_clkdm", .pwrdm = { .name = "mdm_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD, - OMAP2_CM_CLKSTCTRL), .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT, .wkdep_srcs = mdm_2430_wkdeps, .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, @@ -563,8 +547,6 @@ static struct clockdomain dsp_2430_clkdm = { .name = "dsp_clkdm", .pwrdm = { .name = "dsp_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD, - OMAP2_CM_CLKSTCTRL), .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, .wkdep_srcs = dsp_24xx_wkdeps, .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, @@ -575,7 +557,6 @@ static struct clockdomain gfx_2430_clkdm = { .name = "gfx_clkdm", .pwrdm = { .name = "gfx_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), .wkdep_srcs = gfx_sgx_wkdeps, .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), @@ -590,7 +571,6 @@ static struct clockdomain core_l3_2430_clkdm = { .name = "core_l3_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, - .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .dep_bit = OMAP24XX_EN_CORE_SHIFT, .wkdep_srcs = core_24xx_wkdeps, .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, @@ -606,7 +586,6 @@ static struct clockdomain core_l4_2430_clkdm = { .name = "core_l4_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, - .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .dep_bit = OMAP24XX_EN_CORE_SHIFT, .wkdep_srcs = core_24xx_wkdeps, .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, @@ -617,7 +596,6 @@ static struct clockdomain dss_2430_clkdm = { .name = "dss_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, - .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; @@ -635,7 +613,6 @@ static struct clockdomain mpu_3xxx_clkdm = { .name = "mpu_clkdm", .pwrdm = { .name = "mpu_pwrdm" }, .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, - .clkstctrl_reg = OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL), .dep_bit = OMAP3430_EN_MPU_SHIFT, .wkdep_srcs = mpu_3xxx_wkdeps, .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, @@ -646,8 +623,6 @@ static struct clockdomain neon_clkdm = { .name = "neon_clkdm", .pwrdm = { .name = "neon_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD, - OMAP2_CM_CLKSTCTRL), .wkdep_srcs = neon_wkdeps, .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), @@ -657,8 +632,6 @@ static struct clockdomain iva2_clkdm = { .name = "iva2_clkdm", .pwrdm = { .name = "iva2_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, - OMAP2_CM_CLKSTCTRL), .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT, .wkdep_srcs = iva2_wkdeps, .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, @@ -669,7 +642,6 @@ static struct clockdomain gfx_3430es1_clkdm = { .name = "gfx_clkdm", .pwrdm = { .name = "gfx_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), .wkdep_srcs = gfx_sgx_wkdeps, .sleepdep_srcs = gfx_sgx_sleepdeps, .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, @@ -680,8 +652,6 @@ static struct clockdomain sgx_clkdm = { .name = "sgx_clkdm", .pwrdm = { .name = "sgx_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, - OMAP2_CM_CLKSTCTRL), .wkdep_srcs = gfx_sgx_wkdeps, .sleepdep_srcs = gfx_sgx_sleepdeps, .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, @@ -699,7 +669,6 @@ static struct clockdomain d2d_clkdm = { .name = "d2d_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -713,7 +682,6 @@ static struct clockdomain core_l3_3xxx_clkdm = { .name = "core_l3_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, - .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .dep_bit = OMAP3430_EN_CORE_SHIFT, .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), @@ -728,7 +696,6 @@ static struct clockdomain core_l4_3xxx_clkdm = { .name = "core_l4_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, - .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .dep_bit = OMAP3430_EN_CORE_SHIFT, .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), @@ -739,8 +706,6 @@ static struct clockdomain dss_3xxx_clkdm = { .name = "dss_clkdm", .pwrdm = { .name = "dss_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, - OMAP2_CM_CLKSTCTRL), .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, .wkdep_srcs = dss_wkdeps, .sleepdep_srcs = dss_sleepdeps, @@ -752,8 +717,6 @@ static struct clockdomain cam_clkdm = { .name = "cam_clkdm", .pwrdm = { .name = "cam_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, - OMAP2_CM_CLKSTCTRL), .wkdep_srcs = cam_wkdeps, .sleepdep_srcs = cam_sleepdeps, .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, @@ -764,8 +727,6 @@ static struct clockdomain usbhost_clkdm = { .name = "usbhost_clkdm", .pwrdm = { .name = "usbhost_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, - OMAP2_CM_CLKSTCTRL), .wkdep_srcs = usbhost_wkdeps, .sleepdep_srcs = usbhost_sleepdeps, .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, @@ -776,8 +737,6 @@ static struct clockdomain per_clkdm = { .name = "per_clkdm", .pwrdm = { .name = "per_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, - .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, - OMAP2_CM_CLKSTCTRL), .dep_bit = OMAP3430_EN_PER_SHIFT, .wkdep_srcs = per_wkdeps, .sleepdep_srcs = per_sleepdeps, @@ -793,8 +752,6 @@ static struct clockdomain emu_clkdm = { .name = "emu_clkdm", .pwrdm = { .name = "emu_pwrdm" }, .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, - .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, - OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -831,8 +788,6 @@ static struct clockdomain dpll5_clkdm = { #endif /* CONFIG_ARCH_OMAP3 */ -#include "clockdomains44xx.h" - /* * Clockdomain hwsup dependencies (OMAP3 only) */ @@ -851,17 +806,10 @@ static struct clkdm_autodep clkdm_autodeps[] = { } }; -/* - * List of clockdomain pointers per platform - */ - -static struct clockdomain *clockdomains_omap[] = { - -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +static struct clockdomain *clockdomains_omap2[] __initdata = { &wkup_clkdm, &cm_clkdm, &prm_clkdm, -#endif #ifdef CONFIG_ARCH_OMAP2420 &mpu_2420_clkdm, @@ -903,35 +851,10 @@ static struct clockdomain *clockdomains_omap[] = { &dpll4_clkdm, &dpll5_clkdm, #endif - -#ifdef CONFIG_ARCH_OMAP4 - &l4_cefuse_44xx_clkdm, - &l4_cfg_44xx_clkdm, - &tesla_44xx_clkdm, - &l3_gfx_44xx_clkdm, - &ivahd_44xx_clkdm, - &l4_secure_44xx_clkdm, - &l4_per_44xx_clkdm, - &abe_44xx_clkdm, - &l3_instr_44xx_clkdm, - &l3_init_44xx_clkdm, - &mpuss_44xx_clkdm, - &mpu0_44xx_clkdm, - &mpu1_44xx_clkdm, - &l3_emif_44xx_clkdm, - &l4_ao_44xx_clkdm, - &ducati_44xx_clkdm, - &l3_2_44xx_clkdm, - &l3_1_44xx_clkdm, - &l3_d2d_44xx_clkdm, - &iss_44xx_clkdm, - &l3_dss_44xx_clkdm, - &l4_wkup_44xx_clkdm, - &emu_sys_44xx_clkdm, - &l3_dma_44xx_clkdm, -#endif - NULL, }; -#endif +void __init omap2_clockdomains_init(void) +{ + clkdm_init(clockdomains_omap2, clkdm_autodeps); +} diff --git a/arch/arm/mach-omap2/clockdomains44xx.h b/arch/arm/mach-omap2/clockdomains44xx_data.c index 7e5ba0f67925..51920fc7fc52 100644 --- a/arch/arm/mach-omap2/clockdomains44xx.h +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -23,18 +23,27 @@ * -> Populate the Sleep/Wakeup dependencies for the domains */ -#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H -#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H +#include <linux/kernel.h> +#include <linux/io.h> -#include <plat/clockdomain.h> +#include "clockdomain.h" +#include "cm1_44xx.h" +#include "cm2_44xx.h" + +#include "cm1_44xx.h" +#include "cm2_44xx.h" +#include "cm-regbits-44xx.h" +#include "prm44xx.h" +#include "prcm44xx.h" +#include "prcm_mpu44xx.h" -#if defined(CONFIG_ARCH_OMAP4) static struct clockdomain l4_cefuse_44xx_clkdm = { .name = "l4_cefuse_clkdm", .pwrdm = { .name = "cefuse_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_CEFUSE_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_CEFUSE_INST, + .clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -42,8 +51,9 @@ static struct clockdomain l4_cefuse_44xx_clkdm = { static struct clockdomain l4_cfg_44xx_clkdm = { .name = "l4_cfg_clkdm", .pwrdm = { .name = "core_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_L4CFG_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_CORE_INST, + .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS, .flags = CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -51,8 +61,9 @@ static struct clockdomain l4_cfg_44xx_clkdm = { static struct clockdomain tesla_44xx_clkdm = { .name = "tesla_clkdm", .pwrdm = { .name = "tesla_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_TESLA_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM1_PARTITION, + .cm_inst = OMAP4430_CM1_TESLA_INST, + .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -60,8 +71,9 @@ static struct clockdomain tesla_44xx_clkdm = { static struct clockdomain l3_gfx_44xx_clkdm = { .name = "l3_gfx_clkdm", .pwrdm = { .name = "gfx_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_GFX_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_GFX_INST, + .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -69,8 +81,9 @@ static struct clockdomain l3_gfx_44xx_clkdm = { static struct clockdomain ivahd_44xx_clkdm = { .name = "ivahd_clkdm", .pwrdm = { .name = "ivahd_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_IVAHD_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_IVAHD_INST, + .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -78,8 +91,9 @@ static struct clockdomain ivahd_44xx_clkdm = { static struct clockdomain l4_secure_44xx_clkdm = { .name = "l4_secure_clkdm", .pwrdm = { .name = "l4per_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_L4SEC_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_L4PER_INST, + .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -87,8 +101,9 @@ static struct clockdomain l4_secure_44xx_clkdm = { static struct clockdomain l4_per_44xx_clkdm = { .name = "l4_per_clkdm", .pwrdm = { .name = "l4per_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_L4PER_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_L4PER_INST, + .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -96,8 +111,9 @@ static struct clockdomain l4_per_44xx_clkdm = { static struct clockdomain abe_44xx_clkdm = { .name = "abe_clkdm", .pwrdm = { .name = "abe_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM1_ABE_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM1_PARTITION, + .cm_inst = OMAP4430_CM1_ABE_INST, + .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -105,16 +121,18 @@ static struct clockdomain abe_44xx_clkdm = { static struct clockdomain l3_instr_44xx_clkdm = { .name = "l3_instr_clkdm", .pwrdm = { .name = "core_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_L3INSTR_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_CORE_INST, + .clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain l3_init_44xx_clkdm = { .name = "l3_init_clkdm", .pwrdm = { .name = "l3init_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_L3INIT_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_L3INIT_INST, + .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -122,8 +140,9 @@ static struct clockdomain l3_init_44xx_clkdm = { static struct clockdomain mpuss_44xx_clkdm = { .name = "mpuss_clkdm", .pwrdm = { .name = "mpu_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_MPU_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM1_PARTITION, + .cm_inst = OMAP4430_CM1_MPU_INST, + .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -131,8 +150,9 @@ static struct clockdomain mpuss_44xx_clkdm = { static struct clockdomain mpu0_44xx_clkdm = { .name = "mpu0_clkdm", .pwrdm = { .name = "cpu0_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_CPU0_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, + .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST, + .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -140,8 +160,9 @@ static struct clockdomain mpu0_44xx_clkdm = { static struct clockdomain mpu1_44xx_clkdm = { .name = "mpu1_clkdm", .pwrdm = { .name = "cpu1_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_CPU1_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, + .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST, + .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -149,8 +170,9 @@ static struct clockdomain mpu1_44xx_clkdm = { static struct clockdomain l3_emif_44xx_clkdm = { .name = "l3_emif_clkdm", .pwrdm = { .name = "core_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_MEMIF_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_CORE_INST, + .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -158,8 +180,9 @@ static struct clockdomain l3_emif_44xx_clkdm = { static struct clockdomain l4_ao_44xx_clkdm = { .name = "l4_ao_clkdm", .pwrdm = { .name = "always_on_core_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_ALWON_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_ALWAYS_ON_INST, + .clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -167,8 +190,9 @@ static struct clockdomain l4_ao_44xx_clkdm = { static struct clockdomain ducati_44xx_clkdm = { .name = "ducati_clkdm", .pwrdm = { .name = "core_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_DUCATI_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_CORE_INST, + .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -176,8 +200,9 @@ static struct clockdomain ducati_44xx_clkdm = { static struct clockdomain l3_2_44xx_clkdm = { .name = "l3_2_clkdm", .pwrdm = { .name = "core_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_L3_2_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_CORE_INST, + .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS, .flags = CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -185,8 +210,9 @@ static struct clockdomain l3_2_44xx_clkdm = { static struct clockdomain l3_1_44xx_clkdm = { .name = "l3_1_clkdm", .pwrdm = { .name = "core_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_L3_1_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_CORE_INST, + .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS, .flags = CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -194,8 +220,9 @@ static struct clockdomain l3_1_44xx_clkdm = { static struct clockdomain l3_d2d_44xx_clkdm = { .name = "l3_d2d_clkdm", .pwrdm = { .name = "core_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_D2D_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_CORE_INST, + .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -203,8 +230,9 @@ static struct clockdomain l3_d2d_44xx_clkdm = { static struct clockdomain iss_44xx_clkdm = { .name = "iss_clkdm", .pwrdm = { .name = "cam_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_CAM_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_CAM_INST, + .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -212,8 +240,9 @@ static struct clockdomain iss_44xx_clkdm = { static struct clockdomain l3_dss_44xx_clkdm = { .name = "l3_dss_clkdm", .pwrdm = { .name = "dss_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_DSS_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_DSS_INST, + .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -221,8 +250,9 @@ static struct clockdomain l3_dss_44xx_clkdm = { static struct clockdomain l4_wkup_44xx_clkdm = { .name = "l4_wkup_clkdm", .pwrdm = { .name = "wkup_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_WKUP_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_PRM_PARTITION, + .cm_inst = OMAP4430_PRM_WKUP_CM_INST, + .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, .flags = CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -230,8 +260,9 @@ static struct clockdomain l4_wkup_44xx_clkdm = { static struct clockdomain emu_sys_44xx_clkdm = { .name = "emu_sys_clkdm", .pwrdm = { .name = "emu_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_EMU_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_PRM_PARTITION, + .cm_inst = OMAP4430_PRM_EMU_CM_INST, + .clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS, .flags = CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -239,12 +270,42 @@ static struct clockdomain emu_sys_44xx_clkdm = { static struct clockdomain l3_dma_44xx_clkdm = { .name = "l3_dma_clkdm", .pwrdm = { .name = "core_pwrdm" }, - .clkstctrl_reg = OMAP4430_CM_SDMA_CLKSTCTRL, - .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .prcm_partition = OMAP4430_CM2_PARTITION, + .cm_inst = OMAP4430_CM2_CORE_INST, + .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; -#endif +static struct clockdomain *clockdomains_omap44xx[] __initdata = { + &l4_cefuse_44xx_clkdm, + &l4_cfg_44xx_clkdm, + &tesla_44xx_clkdm, + &l3_gfx_44xx_clkdm, + &ivahd_44xx_clkdm, + &l4_secure_44xx_clkdm, + &l4_per_44xx_clkdm, + &abe_44xx_clkdm, + &l3_instr_44xx_clkdm, + &l3_init_44xx_clkdm, + &mpuss_44xx_clkdm, + &mpu0_44xx_clkdm, + &mpu1_44xx_clkdm, + &l3_emif_44xx_clkdm, + &l4_ao_44xx_clkdm, + &ducati_44xx_clkdm, + &l3_2_44xx_clkdm, + &l3_1_44xx_clkdm, + &l3_d2d_44xx_clkdm, + &iss_44xx_clkdm, + &l3_dss_44xx_clkdm, + &l4_wkup_44xx_clkdm, + &emu_sys_44xx_clkdm, + &l3_dma_44xx_clkdm, + NULL, +}; -#endif +void __init omap44xx_clockdomains_init(void) +{ + clkdm_init(clockdomains_omap44xx, NULL); +} diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index da51cc3ed7eb..d70660e82fe6 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -14,8 +14,6 @@ * published by the Free Software Foundation. */ -#include "cm.h" - /* Bits shared between registers */ /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ @@ -126,8 +124,12 @@ #define OMAP24XX_ST_HDQ_MASK (1 << 23) #define OMAP2420_ST_I2C2_SHIFT 20 #define OMAP2420_ST_I2C2_MASK (1 << 20) +#define OMAP2430_ST_I2CHS1_SHIFT 19 +#define OMAP2430_ST_I2CHS1_MASK (1 << 19) #define OMAP2420_ST_I2C1_SHIFT 19 #define OMAP2420_ST_I2C1_MASK (1 << 19) +#define OMAP2430_ST_I2CHS2_SHIFT 20 +#define OMAP2430_ST_I2CHS2_MASK (1 << 20) #define OMAP24XX_ST_MCBSP2_SHIFT 16 #define OMAP24XX_ST_MCBSP2_MASK (1 << 16) #define OMAP24XX_ST_MCBSP1_SHIFT 15 @@ -432,4 +434,9 @@ #define OMAP2430_AUTOSTATE_MDM_SHIFT 0 #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0) +/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */ +#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 +#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 + + #endif diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 4f959a7d881c..b91275908f33 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -14,8 +14,6 @@ * published by the Free Software Foundation. */ -#include "cm.h" - /* Bits shared between registers */ /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ @@ -800,4 +798,15 @@ #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) +/* + * + */ + +/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */ +#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 +#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 +#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 +#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 + + #endif diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h index 0b72be433776..9d47a05b17b4 100644 --- a/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h @@ -22,9 +22,6 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H -#include "cm.h" - - /* * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, * CM_TESLA_DYNAMICDEP diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c deleted file mode 100644 index 721c3b66740a..000000000000 --- a/arch/arm/mach-omap2/cm.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * OMAP2/3 CM module functions - * - * Copyright (C) 2009 Nokia Corporation - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/types.h> -#include <linux/delay.h> -#include <linux/spinlock.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/io.h> - -#include <asm/atomic.h> - -#include <plat/common.h> - -#include "cm.h" -#include "cm-regbits-24xx.h" -#include "cm-regbits-34xx.h" - -static const u8 cm_idlest_offs[] = { - CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 -}; - -/** - * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby - * @prcm_mod: PRCM module offset - * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) - * @idlest_shift: shift of the bit in the CM_IDLEST* register to check - * - * XXX document - */ -int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) -{ - int ena = 0, i = 0; - u8 cm_idlest_reg; - u32 mask; - - if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs))) - return -EINVAL; - - cm_idlest_reg = cm_idlest_offs[idlest_id - 1]; - - mask = 1 << idlest_shift; - - if (cpu_is_omap24xx()) - ena = mask; - else if (cpu_is_omap34xx()) - ena = 0; - else - BUG(); - - /* XXX should be OMAP2 CM */ - omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), - MAX_MODULE_READY_TIME, i); - - return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; -} - diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index a02ca30423dc..a7bc096bd407 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -1,8 +1,5 @@ -#ifndef __ARCH_ASM_MACH_OMAP2_CM_H -#define __ARCH_ASM_MACH_OMAP2_CM_H - /* - * OMAP2/3 Clock Management (CM) register definitions + * OMAP2+ Clock Management prototypes * * Copyright (C) 2007-2009 Texas Instruments, Inc. * Copyright (C) 2007-2009 Nokia Corporation @@ -13,136 +10,8 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ - -#include "prcm-common.h" - -#define OMAP2420_CM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) -#define OMAP2430_CM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) -#define OMAP34XX_CM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) -#define OMAP44XX_CM1_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg)) -#define OMAP44XX_CM2_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg)) - -#include "cm44xx.h" - -/* - * Architecture-specific global CM registers - * Use cm_{read,write}_reg() with these registers. - * These registers appear once per CM module. - */ - -#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) -#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) -#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c) - -#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 -#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) - -/* - * Module specific CM registers from CM_BASE + domain offset - * Use cm_{read,write}_mod_reg() with these registers. - * These register offsets generally appear in more than one PRCM submodule. - */ - -/* Common between 24xx and 34xx */ - -#define CM_FCLKEN 0x0000 -#define CM_FCLKEN1 CM_FCLKEN -#define CM_CLKEN CM_FCLKEN -#define CM_ICLKEN 0x0010 -#define CM_ICLKEN1 CM_ICLKEN -#define CM_ICLKEN2 0x0014 -#define CM_ICLKEN3 0x0018 -#define CM_IDLEST 0x0020 -#define CM_IDLEST1 CM_IDLEST -#define CM_IDLEST2 0x0024 -#define CM_AUTOIDLE 0x0030 -#define CM_AUTOIDLE1 CM_AUTOIDLE -#define CM_AUTOIDLE2 0x0034 -#define CM_AUTOIDLE3 0x0038 -#define CM_CLKSEL 0x0040 -#define CM_CLKSEL1 CM_CLKSEL -#define CM_CLKSEL2 0x0044 -#define OMAP2_CM_CLKSTCTRL 0x0048 -#define OMAP4_CM_CLKSTCTRL 0x0000 - - -/* Architecture-specific registers */ - -#define OMAP24XX_CM_FCLKEN2 0x0004 -#define OMAP24XX_CM_ICLKEN4 0x001c -#define OMAP24XX_CM_AUTOIDLE4 0x003c - -#define OMAP2430_CM_IDLEST3 0x0028 - -#define OMAP3430_CM_CLKEN_PLL 0x0004 -#define OMAP3430ES2_CM_CLKEN2 0x0004 -#define OMAP3430ES2_CM_FCLKEN3 0x0008 -#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 -#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 -#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2 -#define OMAP3430_CM_CLKSEL1 CM_CLKSEL -#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL -#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 -#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 -#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL -#define OMAP3430_CM_CLKSTST 0x004c -#define OMAP3430ES2_CM_CLKSEL4 0x004c -#define OMAP3430ES2_CM_CLKSEL5 0x0050 -#define OMAP3430_CM_CLKSEL2_EMU 0x0050 -#define OMAP3430_CM_CLKSEL3_EMU 0x0054 - -/* CM2.CEFUSE_CM2 register offsets */ - -/* OMAP4 modulemode control */ -#define OMAP4430_MODULEMODE_HWCTRL 0 -#define OMAP4430_MODULEMODE_SWCTRL 1 - -/* Clock management domain register get/set */ - -#ifndef __ASSEMBLER__ - -extern u32 cm_read_mod_reg(s16 module, u16 idx); -extern void cm_write_mod_reg(u32 val, s16 module, u16 idx); -extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); - -extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, - u8 idlest_shift); -extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg); - -static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) -{ - return cm_rmw_mod_reg_bits(bits, bits, module, idx); -} - -static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) -{ - return cm_rmw_mod_reg_bits(bits, 0x0, module, idx); -} - -#endif - -/* CM register bits shared between 24XX and 3430 */ - -/* CM_CLKSEL_GFX */ -#define OMAP_CLKSEL_GFX_SHIFT 0 -#define OMAP_CLKSEL_GFX_MASK (0x7 << 0) - -/* CM_ICLKEN_GFX */ -#define OMAP_EN_GFX_SHIFT 0 -#define OMAP_EN_GFX_MASK (1 << 0) - -/* CM_IDLEST_GFX */ -#define OMAP_ST_GFX_MASK (1 << 0) - - -/* CM_IDLEST indicator */ -#define OMAP24XX_CM_IDLEST_VAL 0 -#define OMAP34XX_CM_IDLEST_VAL 1 +#ifndef __ARCH_ASM_MACH_OMAP2_CM_H +#define __ARCH_ASM_MACH_OMAP2_CM_H /* * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h new file mode 100644 index 000000000000..e2d7a56b2ad6 --- /dev/null +++ b/arch/arm/mach-omap2/cm1_44xx.h @@ -0,0 +1,261 @@ +/* + * OMAP44xx CM1 instance offset macros + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", + * or "OMAP4430". + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H + +/* CM1 base address */ +#define OMAP4430_CM1_BASE 0x4a004000 + +#define OMAP44XX_CM1_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg)) + +/* CM1 instances */ +#define OMAP4430_CM1_OCP_SOCKET_INST 0x0000 +#define OMAP4430_CM1_CKGEN_INST 0x0100 +#define OMAP4430_CM1_MPU_INST 0x0300 +#define OMAP4430_CM1_TESLA_INST 0x0400 +#define OMAP4430_CM1_ABE_INST 0x0500 +#define OMAP4430_CM1_RESTORE_INST 0x0e00 +#define OMAP4430_CM1_INSTR_INST 0x0f00 + +/* CM1 clockdomain register offsets (from instance start) */ +#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 +#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 +#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 + +/* CM1 */ + +/* CM1.OCP_SOCKET_CM1 register offsets */ +#define OMAP4_REVISION_CM1_OFFSET 0x0000 +#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000) +#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 +#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040) + +/* CM1.CKGEN_CM1 register offsets */ +#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 +#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000) +#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 +#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008) +#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 +#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010) +#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 +#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020) +#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 +#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024) +#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 +#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028) +#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c +#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c) +#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 +#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030) +#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 +#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034) +#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 +#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038) +#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c +#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c) +#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 +#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040) +#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 +#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) +#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET 0x004c +#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) +#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 +#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) +#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 +#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060) +#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 +#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064) +#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 +#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068) +#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c +#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c) +#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 +#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) +#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET 0x008c +#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) +#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c +#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) +#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 +#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0) +#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 +#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4) +#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 +#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8) +#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac +#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac) +#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 +#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8) +#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc +#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) +#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET 0x00cc +#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) +#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc +#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) +#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 +#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0) +#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 +#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4) +#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 +#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8) +#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec +#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec) +#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 +#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0) +#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 +#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) +#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET 0x010c +#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) +#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 +#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) +#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 +#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124) +#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 +#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128) +#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c +#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c) +#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 +#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130) +#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 +#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138) +#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c +#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c) +#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 +#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) +#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET 0x014c +#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) +#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 +#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) +#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 +#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164) +#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 +#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170) +#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 +#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180) + +/* CM1.MPU_CM1 register offsets */ +#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 +#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000) +#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 +#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004) +#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 +#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008) +#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 +#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020) + +/* CM1.TESLA_CM1 register offsets */ +#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 +#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000) +#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 +#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004) +#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 +#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008) +#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 +#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020) + +/* CM1.ABE_CM1 register offsets */ +#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 +#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000) +#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 +#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020) +#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 +#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028) +#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 +#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030) +#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 +#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038) +#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 +#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040) +#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 +#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048) +#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 +#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050) +#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 +#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058) +#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 +#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060) +#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 +#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068) +#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 +#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070) +#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 +#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078) +#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 +#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080) +#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 +#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) + +/* CM1.RESTORE_CM1 register offsets */ +#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000 +#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000) +#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004 +#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004) +#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008 +#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008) +#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c +#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c) +#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010 +#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010) +#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014 +#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014) +#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018 +#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018) +#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c +#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020) +#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024 +#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024) +#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028 +#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028) +#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c +#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c) +#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030 +#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030) +#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034 +#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034) +#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038 +#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038) +#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c +#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c) +#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040 +#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040) + +/* Function prototypes */ +extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx); +extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx); +extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); + +#endif diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h new file mode 100644 index 000000000000..aa4745044065 --- /dev/null +++ b/arch/arm/mach-omap2/cm2_44xx.h @@ -0,0 +1,508 @@ +/* + * OMAP44xx CM2 instance offset macros + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", + * or "OMAP4430". + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H + +/* CM2 base address */ +#define OMAP4430_CM2_BASE 0x4a008000 + +#define OMAP44XX_CM2_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg)) + +/* CM2 instances */ +#define OMAP4430_CM2_OCP_SOCKET_INST 0x0000 +#define OMAP4430_CM2_CKGEN_INST 0x0100 +#define OMAP4430_CM2_ALWAYS_ON_INST 0x0600 +#define OMAP4430_CM2_CORE_INST 0x0700 +#define OMAP4430_CM2_IVAHD_INST 0x0f00 +#define OMAP4430_CM2_CAM_INST 0x1000 +#define OMAP4430_CM2_DSS_INST 0x1100 +#define OMAP4430_CM2_GFX_INST 0x1200 +#define OMAP4430_CM2_L3INIT_INST 0x1300 +#define OMAP4430_CM2_L4PER_INST 0x1400 +#define OMAP4430_CM2_CEFUSE_INST 0x1600 +#define OMAP4430_CM2_RESTORE_INST 0x1e00 +#define OMAP4430_CM2_INSTR_INST 0x1f00 + +/* CM2 clockdomain register offsets (from instance start) */ +#define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000 +#define OMAP4430_CM2_CORE_L3_1_CDOFFS 0x0000 +#define OMAP4430_CM2_CORE_L3_2_CDOFFS 0x0100 +#define OMAP4430_CM2_CORE_DUCATI_CDOFFS 0x0200 +#define OMAP4430_CM2_CORE_SDMA_CDOFFS 0x0300 +#define OMAP4430_CM2_CORE_MEMIF_CDOFFS 0x0400 +#define OMAP4430_CM2_CORE_D2D_CDOFFS 0x0500 +#define OMAP4430_CM2_CORE_L4CFG_CDOFFS 0x0600 +#define OMAP4430_CM2_CORE_L3INSTR_CDOFFS 0x0700 +#define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS 0x0000 +#define OMAP4430_CM2_CAM_CAM_CDOFFS 0x0000 +#define OMAP4430_CM2_DSS_DSS_CDOFFS 0x0000 +#define OMAP4430_CM2_GFX_GFX_CDOFFS 0x0000 +#define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS 0x0000 +#define OMAP4430_CM2_L4PER_L4PER_CDOFFS 0x0000 +#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 +#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 + + +/* CM2 */ + +/* CM2.OCP_SOCKET_CM2 register offsets */ +#define OMAP4_REVISION_CM2_OFFSET 0x0000 +#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000) +#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040 +#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040) + +/* CM2.CKGEN_CM2 register offsets */ +#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000 +#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000) +#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 +#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004) +#define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008 +#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008) +#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010 +#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010) +#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014 +#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014) +#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018 +#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018) +#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c +#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c) +#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024 +#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024) +#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028 +#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028) +#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c +#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c) +#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030 +#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030) +#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038 +#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038) +#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 +#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040) +#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044 +#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044) +#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 +#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048) +#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c +#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c) +#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 +#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050) +#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 +#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054) +#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058 +#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058) +#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c +#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c) +#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060 +#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060) +#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064 +#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068) +#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET 0x006c +#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c) +#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 +#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080) +#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 +#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084) +#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 +#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088) +#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c +#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c) +#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 +#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8) +#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET 0x00ac +#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac) +#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 +#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4) +#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 +#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0) +#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4 +#define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4) +#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8 +#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8) +#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc +#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc) +#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0 +#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8) +#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec +#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec) + +/* CM2.ALWAYS_ON_CM2 register offsets */ +#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 +#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000) +#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020 +#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020) +#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028 +#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028) +#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030 +#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030) +#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 +#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038) +#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 +#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040) + +/* CM2.CORE_CM2 register offsets */ +#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 +#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000) +#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008 +#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008) +#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020 +#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020) +#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100 +#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100) +#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108 +#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108) +#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120 +#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120) +#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128 +#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128) +#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 +#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130) +#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200 +#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200) +#define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204 +#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204) +#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208 +#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208) +#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220 +#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220) +#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300 +#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300) +#define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304 +#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304) +#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308 +#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308) +#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320 +#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320) +#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400 +#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400) +#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420 +#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420) +#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428 +#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428) +#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430 +#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430) +#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438 +#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438) +#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440 +#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440) +#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450 +#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450) +#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458 +#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458) +#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460 +#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460) +#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500 +#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500) +#define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504 +#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504) +#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508 +#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508) +#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 +#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520) +#define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET 0x0528 +#define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528) +#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 +#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530) +#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 +#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600) +#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 +#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608) +#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 +#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620) +#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628 +#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628) +#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 +#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630) +#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 +#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638) +#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 +#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700) +#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720 +#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720) +#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 +#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728) +#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740 +#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740) + +/* CM2.IVAHD_CM2 register offsets */ +#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000 +#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000) +#define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004 +#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004) +#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008 +#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008) +#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020 +#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020) +#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028 +#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028) + +/* CM2.CAM_CM2 register offsets */ +#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000 +#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000) +#define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004 +#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004) +#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008 +#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008) +#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 +#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020) +#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 +#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028) + +/* CM2.DSS_CM2 register offsets */ +#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000 +#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000) +#define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004 +#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004) +#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008 +#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008) +#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 +#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020) +#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028 +#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028) + +/* CM2.GFX_CM2 register offsets */ +#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000 +#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000) +#define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004 +#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004) +#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008 +#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008) +#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 +#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020) + +/* CM2.L3INIT_CM2 register offsets */ +#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 +#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000) +#define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004 +#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004) +#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 +#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008) +#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 +#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028) +#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 +#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030) +#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 +#define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038) +#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040 +#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040) +#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058 +#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058) +#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060 +#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060) +#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068 +#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068) +#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078 +#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078) +#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080 +#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080) +#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 +#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088) +#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090 +#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090) +#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098 +#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098) +#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8 +#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8) +#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0 +#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0) +#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8 +#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8) +#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0 +#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0) +#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0 +#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0) + +/* CM2.L4PER_CM2 register offsets */ +#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 +#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000) +#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 +#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008) +#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020 +#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020) +#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028 +#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028) +#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030 +#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030) +#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038 +#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038) +#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040 +#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040) +#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048 +#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048) +#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050 +#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050) +#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 +#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058) +#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 +#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060) +#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 +#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068) +#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 +#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070) +#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 +#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078) +#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 +#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080) +#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 +#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088) +#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090 +#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090) +#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098 +#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098) +#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 +#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0) +#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 +#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8) +#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 +#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0) +#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 +#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8) +#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0 +#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0) +#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0 +#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0) +#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8 +#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8) +#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0 +#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0) +#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8 +#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8) +#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 +#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0) +#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 +#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8) +#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 +#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100) +#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 +#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108) +#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120 +#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120) +#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128 +#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128) +#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130 +#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130) +#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138 +#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138) +#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 +#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140) +#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 +#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148) +#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 +#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150) +#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 +#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158) +#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160 +#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160) +#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168 +#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168) +#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 +#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180) +#define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184 +#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184) +#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 +#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188) +#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 +#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0) +#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 +#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8) +#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 +#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0) +#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8 +#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8) +#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 +#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0) +#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 +#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8) +#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8 +#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8) + +/* CM2.CEFUSE_CM2 register offsets */ +#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 +#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000) +#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 +#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) + +/* CM2.RESTORE_CM2 register offsets */ +#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000 +#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0000) +#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004 +#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0004) +#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008 +#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0008) +#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c +#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x000c) +#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010 +#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0010) +#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014 +#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0014) +#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018 +#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0018) +#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c +#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x001c) +#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020 +#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0020) +#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024 +#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0024) +#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028 +#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0028) +#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c +#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x002c) +#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030 +#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0030) +#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034 +#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0034) +#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038 +#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0038) +#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c +#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x003c) +#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040 +#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0040) +#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044 +#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0044) +#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048 +#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0048) +#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c +#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x004c) +#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050 +#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0050) +#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054 +#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0054) +#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058 +#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0058) +#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c +#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x005c) + +/* Function prototypes */ +extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx); +extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx); +extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); + +#endif diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c new file mode 100644 index 000000000000..96954aa48671 --- /dev/null +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c @@ -0,0 +1,471 @@ +/* + * OMAP2/3 CM module functions + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/delay.h> +#include <linux/spinlock.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/io.h> + +#include <plat/common.h> + +#include "cm.h" +#include "cm2xxx_3xxx.h" +#include "cm-regbits-24xx.h" +#include "cm-regbits-34xx.h" + +static const u8 cm_idlest_offs[] = { + CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 +}; + +u32 omap2_cm_read_mod_reg(s16 module, u16 idx) +{ + return __raw_readl(cm_base + module + idx); +} + +void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) +{ + __raw_writel(val, cm_base + module + idx); +} + +/* Read-modify-write a register in a CM module. Caller must lock */ +u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) +{ + u32 v; + + v = omap2_cm_read_mod_reg(module, idx); + v &= ~mask; + v |= bits; + omap2_cm_write_mod_reg(v, module, idx); + + return v; +} + +u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) +{ + return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx); +} + +u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) +{ + return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx); +} + +/* + * + */ + +static void _write_clktrctrl(u8 c, s16 module, u32 mask) +{ + u32 v; + + v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); + v &= ~mask; + v |= c << __ffs(mask); + omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL); +} + +bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask) +{ + u32 v; + bool ret = 0; + + BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx()); + + v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); + v &= mask; + v >>= __ffs(mask); + + if (cpu_is_omap24xx()) + ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; + else + ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; + + return ret; +} + +void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) +{ + _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask); +} + +void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask) +{ + _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask); +} + +void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) +{ + _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask); +} + +void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask) +{ + _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask); +} + +void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask) +{ + _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask); +} + +void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask) +{ + _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask); +} + + +/* + * + */ + +/** + * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby + * @prcm_mod: PRCM module offset + * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) + * @idlest_shift: shift of the bit in the CM_IDLEST* register to check + * + * XXX document + */ +int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) +{ + int ena = 0, i = 0; + u8 cm_idlest_reg; + u32 mask; + + if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs))) + return -EINVAL; + + cm_idlest_reg = cm_idlest_offs[idlest_id - 1]; + + mask = 1 << idlest_shift; + + if (cpu_is_omap24xx()) + ena = mask; + else if (cpu_is_omap34xx()) + ena = 0; + else + BUG(); + + omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), + MAX_MODULE_READY_TIME, i); + + return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; +} + +/* + * Context save/restore code - OMAP3 only + */ +#ifdef CONFIG_ARCH_OMAP3 +struct omap3_cm_regs { + u32 iva2_cm_clksel1; + u32 iva2_cm_clksel2; + u32 cm_sysconfig; + u32 sgx_cm_clksel; + u32 dss_cm_clksel; + u32 cam_cm_clksel; + u32 per_cm_clksel; + u32 emu_cm_clksel; + u32 emu_cm_clkstctrl; + u32 pll_cm_autoidle2; + u32 pll_cm_clksel4; + u32 pll_cm_clksel5; + u32 pll_cm_clken2; + u32 cm_polctrl; + u32 iva2_cm_fclken; + u32 iva2_cm_clken_pll; + u32 core_cm_fclken1; + u32 core_cm_fclken3; + u32 sgx_cm_fclken; + u32 wkup_cm_fclken; + u32 dss_cm_fclken; + u32 cam_cm_fclken; + u32 per_cm_fclken; + u32 usbhost_cm_fclken; + u32 core_cm_iclken1; + u32 core_cm_iclken2; + u32 core_cm_iclken3; + u32 sgx_cm_iclken; + u32 wkup_cm_iclken; + u32 dss_cm_iclken; + u32 cam_cm_iclken; + u32 per_cm_iclken; + u32 usbhost_cm_iclken; + u32 iva2_cm_autoidle2; + u32 mpu_cm_autoidle2; + u32 iva2_cm_clkstctrl; + u32 mpu_cm_clkstctrl; + u32 core_cm_clkstctrl; + u32 sgx_cm_clkstctrl; + u32 dss_cm_clkstctrl; + u32 cam_cm_clkstctrl; + u32 per_cm_clkstctrl; + u32 neon_cm_clkstctrl; + u32 usbhost_cm_clkstctrl; + u32 core_cm_autoidle1; + u32 core_cm_autoidle2; + u32 core_cm_autoidle3; + u32 wkup_cm_autoidle; + u32 dss_cm_autoidle; + u32 cam_cm_autoidle; + u32 per_cm_autoidle; + u32 usbhost_cm_autoidle; + u32 sgx_cm_sleepdep; + u32 dss_cm_sleepdep; + u32 cam_cm_sleepdep; + u32 per_cm_sleepdep; + u32 usbhost_cm_sleepdep; + u32 cm_clkout_ctrl; +}; + +static struct omap3_cm_regs cm_context; + +void omap3_cm_save_context(void) +{ + cm_context.iva2_cm_clksel1 = + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); + cm_context.iva2_cm_clksel2 = + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); + cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); + cm_context.sgx_cm_clksel = + omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); + cm_context.dss_cm_clksel = + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); + cm_context.cam_cm_clksel = + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); + cm_context.per_cm_clksel = + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); + cm_context.emu_cm_clksel = + omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); + cm_context.emu_cm_clkstctrl = + omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); + cm_context.pll_cm_autoidle2 = + omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); + cm_context.pll_cm_clksel4 = + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); + cm_context.pll_cm_clksel5 = + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); + cm_context.pll_cm_clken2 = + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); + cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); + cm_context.iva2_cm_fclken = + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); + cm_context.iva2_cm_clken_pll = + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL); + cm_context.core_cm_fclken1 = + omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + cm_context.core_cm_fclken3 = + omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); + cm_context.sgx_cm_fclken = + omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); + cm_context.wkup_cm_fclken = + omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); + cm_context.dss_cm_fclken = + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); + cm_context.cam_cm_fclken = + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); + cm_context.per_cm_fclken = + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); + cm_context.usbhost_cm_fclken = + omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); + cm_context.core_cm_iclken1 = + omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); + cm_context.core_cm_iclken2 = + omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); + cm_context.core_cm_iclken3 = + omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); + cm_context.sgx_cm_iclken = + omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); + cm_context.wkup_cm_iclken = + omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); + cm_context.dss_cm_iclken = + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); + cm_context.cam_cm_iclken = + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); + cm_context.per_cm_iclken = + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); + cm_context.usbhost_cm_iclken = + omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); + cm_context.iva2_cm_autoidle2 = + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); + cm_context.mpu_cm_autoidle2 = + omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); + cm_context.iva2_cm_clkstctrl = + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); + cm_context.mpu_cm_clkstctrl = + omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); + cm_context.core_cm_clkstctrl = + omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); + cm_context.sgx_cm_clkstctrl = + omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL); + cm_context.dss_cm_clkstctrl = + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); + cm_context.cam_cm_clkstctrl = + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); + cm_context.per_cm_clkstctrl = + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); + cm_context.neon_cm_clkstctrl = + omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); + cm_context.usbhost_cm_clkstctrl = + omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, + OMAP2_CM_CLKSTCTRL); + cm_context.core_cm_autoidle1 = + omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); + cm_context.core_cm_autoidle2 = + omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); + cm_context.core_cm_autoidle3 = + omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); + cm_context.wkup_cm_autoidle = + omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); + cm_context.dss_cm_autoidle = + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); + cm_context.cam_cm_autoidle = + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); + cm_context.per_cm_autoidle = + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); + cm_context.usbhost_cm_autoidle = + omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); + cm_context.sgx_cm_sleepdep = + omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, + OMAP3430_CM_SLEEPDEP); + cm_context.dss_cm_sleepdep = + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); + cm_context.cam_cm_sleepdep = + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); + cm_context.per_cm_sleepdep = + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); + cm_context.usbhost_cm_sleepdep = + omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, + OMAP3430_CM_SLEEPDEP); + cm_context.cm_clkout_ctrl = + omap2_cm_read_mod_reg(OMAP3430_CCR_MOD, + OMAP3_CM_CLKOUT_CTRL_OFFSET); +} + +void omap3_cm_restore_context(void) +{ + omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, + CM_CLKSEL1); + omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, + CM_CLKSEL2); + __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); + omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, + CM_CLKSEL); + omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD, + CM_CLKSEL); + omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD, + CM_CLKSEL); + omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD, + CM_CLKSEL); + omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD, + CM_CLKSEL1); + omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD, + CM_AUTOIDLE2); + omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD, + OMAP3430ES2_CM_CLKSEL4); + omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD, + OMAP3430ES2_CM_CLKSEL5); + omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD, + OMAP3430ES2_CM_CLKEN2); + __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL); + omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, + CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, + OMAP3430_CM_CLKEN_PLL); + omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, + CM_FCLKEN1); + omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD, + OMAP3430ES2_CM_FCLKEN3); + omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, + CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD, + CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD, + CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD, + CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken, + OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD, + CM_ICLKEN1); + omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD, + CM_ICLKEN2); + omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD, + CM_ICLKEN3); + omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, + CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD, + CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD, + CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD, + CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken, + OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD, + CM_AUTOIDLE2); + omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD, + CM_AUTOIDLE2); + omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl, + OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD, + CM_AUTOIDLE1); + omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD, + CM_AUTOIDLE2); + omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD, + CM_AUTOIDLE3); + omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD, + CM_AUTOIDLE); + omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, + CM_AUTOIDLE); + omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, + CM_AUTOIDLE); + omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD, + CM_AUTOIDLE); + omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle, + OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); + omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, + OMAP3430_CM_SLEEPDEP); + omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, + OMAP3430_CM_SLEEPDEP); + omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, + OMAP3430_CM_SLEEPDEP); + omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD, + OMAP3430_CM_SLEEPDEP); + omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep, + OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); + omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, + OMAP3_CM_CLKOUT_CTRL_OFFSET); +} +#endif diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h new file mode 100644 index 000000000000..5e9ea5bd60b9 --- /dev/null +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h @@ -0,0 +1,147 @@ +/* + * OMAP2/3 Clock Management (CM) register definitions + * + * Copyright (C) 2007-2009 Texas Instruments, Inc. + * Copyright (C) 2007-2010 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * The CM hardware modules on the OMAP2/3 are quite similar to each + * other. The CM modules/instances on OMAP4 are quite different, so + * they are handled in a separate file. + */ +#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H +#define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H + +#include "prcm-common.h" + +#define OMAP2420_CM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) +#define OMAP2430_CM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) +#define OMAP34XX_CM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) + + +/* + * OMAP3-specific global CM registers + * Use cm_{read,write}_reg() with these registers. + * These registers appear once per CM module. + */ + +#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) +#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) +#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c) + +#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 +#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) + +/* + * Module specific CM register offsets from CM_BASE + domain offset + * Use cm_{read,write}_mod_reg() with these registers. + * These register offsets generally appear in more than one PRCM submodule. + */ + +/* Common between OMAP2 and OMAP3 */ + +#define CM_FCLKEN 0x0000 +#define CM_FCLKEN1 CM_FCLKEN +#define CM_CLKEN CM_FCLKEN +#define CM_ICLKEN 0x0010 +#define CM_ICLKEN1 CM_ICLKEN +#define CM_ICLKEN2 0x0014 +#define CM_ICLKEN3 0x0018 +#define CM_IDLEST 0x0020 +#define CM_IDLEST1 CM_IDLEST +#define CM_IDLEST2 0x0024 +#define CM_AUTOIDLE 0x0030 +#define CM_AUTOIDLE1 CM_AUTOIDLE +#define CM_AUTOIDLE2 0x0034 +#define CM_AUTOIDLE3 0x0038 +#define CM_CLKSEL 0x0040 +#define CM_CLKSEL1 CM_CLKSEL +#define CM_CLKSEL2 0x0044 +#define OMAP2_CM_CLKSTCTRL 0x0048 + +/* OMAP2-specific register offsets */ + +#define OMAP24XX_CM_FCLKEN2 0x0004 +#define OMAP24XX_CM_ICLKEN4 0x001c +#define OMAP24XX_CM_AUTOIDLE4 0x003c + +#define OMAP2430_CM_IDLEST3 0x0028 + +/* OMAP3-specific register offsets */ + +#define OMAP3430_CM_CLKEN_PLL 0x0004 +#define OMAP3430ES2_CM_CLKEN2 0x0004 +#define OMAP3430ES2_CM_FCLKEN3 0x0008 +#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 +#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 +#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2 +#define OMAP3430_CM_CLKSEL1 CM_CLKSEL +#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL +#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 +#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 +#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL +#define OMAP3430_CM_CLKSTST 0x004c +#define OMAP3430ES2_CM_CLKSEL4 0x004c +#define OMAP3430ES2_CM_CLKSEL5 0x0050 +#define OMAP3430_CM_CLKSEL2_EMU 0x0050 +#define OMAP3430_CM_CLKSEL3_EMU 0x0054 + + +/* CM_IDLEST bit field values to indicate deasserted IdleReq */ + +#define OMAP24XX_CM_IDLEST_VAL 0 +#define OMAP34XX_CM_IDLEST_VAL 1 + + +/* Clock management domain register get/set */ + +#ifndef __ASSEMBLER__ + +extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx); +extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx); +extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); + +extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, + u8 idlest_shift); +extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); +extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); + +extern bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask); +extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask); +extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask); + +extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask); +extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask); +extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask); +extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask); + +#endif + +/* CM register bits shared between 24XX and 3430 */ + +/* CM_CLKSEL_GFX */ +#define OMAP_CLKSEL_GFX_SHIFT 0 +#define OMAP_CLKSEL_GFX_MASK (0x7 << 0) + +/* CM_ICLKEN_GFX */ +#define OMAP_EN_GFX_SHIFT 0 +#define OMAP_EN_GFX_MASK (1 << 0) + +/* CM_IDLEST_GFX */ +#define OMAP_ST_GFX_MASK (1 << 0) + + +/* Function prototypes */ +# ifndef __ASSEMBLER__ +extern void omap3_cm_save_context(void); +extern void omap3_cm_restore_context(void); +# endif + +#endif diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c new file mode 100644 index 000000000000..e96f53ea01a1 --- /dev/null +++ b/arch/arm/mach-omap2/cm44xx.c @@ -0,0 +1,52 @@ +/* + * OMAP4 CM1, CM2 module low-level functions + * + * Copyright (C) 2010 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * These functions are intended to be used only by the cminst44xx.c file. + * XXX Perhaps we should just move them there and make them static. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/io.h> + +#include <plat/common.h> + +#include "cm.h" +#include "cm1_44xx.h" +#include "cm2_44xx.h" +#include "cm-regbits-44xx.h" + +/* CM1 hardware module low-level functions */ + +/* Read a register in CM1 */ +u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg) +{ + return __raw_readl(OMAP44XX_CM1_REGADDR(inst, reg)); +} + +/* Write into a register in CM1 */ +void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 reg) +{ + __raw_writel(val, OMAP44XX_CM1_REGADDR(inst, reg)); +} + +/* Read a register in CM2 */ +u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg) +{ + return __raw_readl(OMAP44XX_CM2_REGADDR(inst, reg)); +} + +/* Write into a register in CM2 */ +void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 reg) +{ + __raw_writel(val, OMAP44XX_CM2_REGADDR(inst, reg)); +} diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h index 3c35a87cb90c..48fc3f426fbd 100644 --- a/arch/arm/mach-omap2/cm44xx.h +++ b/arch/arm/mach-omap2/cm44xx.h @@ -1,667 +1,31 @@ /* - * OMAP44xx CM1 & CM2 instance offset macros + * OMAP4 Clock Management (CM) definitions * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * Copyright (C) 2009-2010 Nokia Corporation + * Copyright (C) 2007-2009 Texas Instruments, Inc. + * Copyright (C) 2007-2009 Nokia Corporation * - * Paul Walmsley (paul@pwsan.com) - * Rajendra Nayak (rnayak@ti.com) - * Benoit Cousson (b-cousson@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. + * Written by Paul Walmsley * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. + * + * OMAP4 has two separate CM blocks, CM1 and CM2. This file contains + * macros and function prototypes that are applicable to both. */ +#ifndef __ARCH_ASM_MACH_OMAP2_CM44XX_H +#define __ARCH_ASM_MACH_OMAP2_CM44XX_H -#ifndef __ARCH_ARM_MACH_OMAP2_CM44XX_H -#define __ARCH_ARM_MACH_OMAP2_CM44XX_H - - -/* CM1 */ - -/* CM1.OCP_SOCKET_CM1 register offsets */ -#define OMAP4_REVISION_CM1_OFFSET 0x0000 -#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000) -#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040) - -/* CM1.CKGEN_CM1 register offsets */ -#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 -#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000) -#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 -#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008) -#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 -#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010) -#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 -#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020) -#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 -#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024) -#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 -#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028) -#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c -#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c) -#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 -#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030) -#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 -#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034) -#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 -#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038) -#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c -#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c) -#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 -#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040) -#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 -#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c) -#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 -#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050) -#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 -#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060) -#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 -#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064) -#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 -#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068) -#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c -#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c) -#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 -#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c) -#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c -#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c) -#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 -#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0) -#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 -#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4) -#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 -#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8) -#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac -#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac) -#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 -#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8) -#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc -#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc) -#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc -#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc) -#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 -#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0) -#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 -#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4) -#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 -#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8) -#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec -#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec) -#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 -#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0) -#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 -#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c) -#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 -#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120) -#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 -#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124) -#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 -#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128) -#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c -#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c) -#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 -#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130) -#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 -#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138) -#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c -#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c) -#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 -#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c) -#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 -#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160) -#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 -#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164) -#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 -#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170) -#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 -#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180) - -/* CM1.MPU_CM1 register offsets */ -#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000) -#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004) -#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008) -#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020) - -/* CM1.TESLA_CM1 register offsets */ -#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000) -#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004) -#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008) -#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020) - -/* CM1.ABE_CM1 register offsets */ -#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000) -#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020) -#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028) -#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 -#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030) -#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 -#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038) -#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040) -#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 -#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048) -#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 -#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050) -#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 -#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058) -#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 -#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060) -#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 -#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068) -#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 -#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070) -#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 -#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078) -#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 -#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080) -#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 -#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088) - -/* CM1.RESTORE_CM1 register offsets */ -#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000 -#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000) -#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004 -#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004) -#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008 -#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008) -#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c -#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c) -#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010 -#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010) -#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014 -#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014) -#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018 -#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018) -#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c -#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024 -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024) -#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028 -#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028) -#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c -#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c) -#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030 -#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030) -#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034 -#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034) -#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038 -#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038) -#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c -#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c) -#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040 -#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040) - -/* CM2 */ - -/* CM2.OCP_SOCKET_CM2 register offsets */ -#define OMAP4_REVISION_CM2_OFFSET 0x0000 -#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000) -#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040) - -/* CM2.CKGEN_CM2 register offsets */ -#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000 -#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000) -#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 -#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004) -#define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008 -#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008) -#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010 -#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010) -#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014 -#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014) -#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018 -#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018) -#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c -#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c) -#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024 -#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024) -#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028 -#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028) -#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c -#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c) -#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030 -#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030) -#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038 -#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038) -#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 -#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040) -#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044 -#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044) -#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 -#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048) -#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c -#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c) -#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 -#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050) -#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 -#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054) -#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058 -#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058) -#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c -#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c) -#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060 -#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060) -#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064 -#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c) -#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 -#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080) -#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 -#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084) -#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 -#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088) -#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c -#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c) -#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 -#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac) -#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 -#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4) -#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 -#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0) -#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4 -#define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4) -#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8 -#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8) -#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc -#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc) -#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0 -#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec) - -/* CM2.ALWAYS_ON_CM2 register offsets */ -#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000) -#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020) -#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028) -#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030 -#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030) -#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 -#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038) -#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040) - -/* CM2.CORE_CM2 register offsets */ -#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000) -#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008) -#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020) -#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100 -#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100) -#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108 -#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108) -#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120 -#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120) -#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128 -#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128) -#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 -#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130) -#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200 -#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200) -#define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204 -#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204) -#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208 -#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208) -#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220 -#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220) -#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300 -#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300) -#define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304 -#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304) -#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308 -#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308) -#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320 -#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320) -#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400 -#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400) -#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420 -#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420) -#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428 -#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428) -#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430 -#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430) -#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438 -#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438) -#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440 -#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440) -#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450 -#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450) -#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458 -#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458) -#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460 -#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460) -#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500 -#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500) -#define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504 -#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504) -#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508 -#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508) -#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 -#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520) -#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528 -#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528) -#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 -#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530) -#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 -#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600) -#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 -#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608) -#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 -#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620) -#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628 -#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628) -#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 -#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630) -#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 -#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638) -#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 -#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700) -#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720 -#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720) -#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 -#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728) -#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740 -#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740) - -/* CM2.IVAHD_CM2 register offsets */ -#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000) -#define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004) -#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008) -#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020) -#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028) - -/* CM2.CAM_CM2 register offsets */ -#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000) -#define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004) -#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008) -#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020) -#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028) - -/* CM2.DSS_CM2 register offsets */ -#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000) -#define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004) -#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008) -#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020) -#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028) -/* CM2.GFX_CM2 register offsets */ -#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000) -#define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004) -#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008) -#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020) +#include "prcm-common.h" +#include "cm.h" -/* CM2.L3INIT_CM2 register offsets */ -#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000) -#define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004) -#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008) -#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028) -#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 -#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030) -#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 -#define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038) -#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040) -#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058 -#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058) -#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060 -#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060) -#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068 -#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068) -#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078 -#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078) -#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080 -#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080) -#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 -#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088) -#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090 -#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090) -#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098 -#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098) -#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8 -#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8) -#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0 -#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0) -#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8 -#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8) -#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0 -#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0) -#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0 -#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0) +#define OMAP4_CM_CLKSTCTRL 0x0000 -/* CM2.L4PER_CM2 register offsets */ -#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000) -#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008) -#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020) -#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028) -#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030 -#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030) -#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038 -#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038) -#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040) -#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048 -#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048) -#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050 -#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050) -#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 -#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058) -#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 -#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060) -#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 -#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068) -#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 -#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070) -#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 -#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078) -#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 -#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080) -#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 -#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088) -#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090 -#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090) -#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098 -#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098) -#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 -#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0) -#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 -#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8) -#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 -#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0) -#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 -#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8) -#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0 -#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0) -#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0 -#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0) -#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8 -#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8) -#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0 -#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0) -#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8 -#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8) -#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 -#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0) -#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 -#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8) -#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 -#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100) -#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 -#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108) -#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120 -#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120) -#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128 -#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128) -#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130 -#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130) -#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138 -#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138) -#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 -#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140) -#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 -#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148) -#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 -#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150) -#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 -#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158) -#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160 -#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160) -#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168 -#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168) -#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 -#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180) -#define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184 -#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184) -#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 -#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188) -#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 -#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0) -#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 -#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8) -#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 -#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0) -#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8 -#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8) -#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 -#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0) -#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 -#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8) -#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8 -#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8) +/* Function prototypes */ +# ifndef __ASSEMBLER__ -/* CM2.CEFUSE_CM2 register offsets */ -#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000) -#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020) +extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg); -/* CM2.RESTORE_CM2 register offsets */ -#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000 -#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000) -#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004 -#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004) -#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008 -#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008) -#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c -#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c) -#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010 -#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010) -#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014 -#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014) -#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018 -#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018) -#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c -#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c) -#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020 -#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020) -#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024 -#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024) -#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028 -#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028) -#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c -#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c) -#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030 -#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030) -#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034 -#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034) -#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038 -#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038) -#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c -#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c) -#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040 -#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040) -#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044 -#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044) -#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048 -#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048) -#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c -#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c) -#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050 -#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050) -#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054 -#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054) -#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058 -#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058) -#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c -#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c) +# endif #endif diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c deleted file mode 100644 index f8a660a1a4a6..000000000000 --- a/arch/arm/mach-omap2/cm4xxx.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * OMAP4 CM module functions - * - * Copyright (C) 2009 Nokia Corporation - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/types.h> -#include <linux/delay.h> -#include <linux/spinlock.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/io.h> - -#include <asm/atomic.h> - -#include <plat/common.h> - -#include "cm.h" -#include "cm-regbits-44xx.h" - -/** - * omap4_cm_wait_module_ready - wait for a module to be in 'func' state - * @clkctrl_reg: CLKCTRL module address - * - * Wait for the module IDLEST to be functional. If the idle state is in any - * the non functional state (trans, idle or disabled), module and thus the - * sysconfig cannot be accessed and will probably lead to an "imprecise - * external abort" - * - * Module idle state: - * 0x0 func: Module is fully functional, including OCP - * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep - * abortion - * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if - * using separate functional clock - * 0x3 disabled: Module is disabled and cannot be accessed - * - */ -int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg) -{ - int i = 0; - - if (!clkctrl_reg) - return 0; - - omap_test_timeout(( - ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) || - (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >> - OMAP4430_IDLEST_SHIFT) == 0x2)), - MAX_MODULE_READY_TIME, i); - - return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; -} - diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c new file mode 100644 index 000000000000..c04bbbea17a5 --- /dev/null +++ b/arch/arm/mach-omap2/cminst44xx.c @@ -0,0 +1,214 @@ +/* + * OMAP4 CM instance functions + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1, + * or CM2 hardware modules. For example, the EMU_CM CM instance is in + * the PRM hardware module. What a mess... + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/io.h> + +#include <plat/common.h> + +#include "cm.h" +#include "cm1_44xx.h" +#include "cm2_44xx.h" +#include "cm44xx.h" +#include "cminst44xx.h" +#include "cm-regbits-34xx.h" +#include "cm-regbits-44xx.h" +#include "prcm44xx.h" +#include "prm44xx.h" +#include "prcm_mpu44xx.h" + +static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = { + [OMAP4430_INVALID_PRCM_PARTITION] = 0, + [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE, + [OMAP4430_CM1_PARTITION] = OMAP4430_CM1_BASE, + [OMAP4430_CM2_PARTITION] = OMAP4430_CM2_BASE, + [OMAP4430_SCRM_PARTITION] = 0, + [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE, +}; + +/* Read a register in a CM instance */ +u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx) +{ + BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || + part == OMAP4430_INVALID_PRCM_PARTITION || + !_cm_bases[part]); + return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx)); +} + +/* Write into a register in a CM instance */ +void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) +{ + BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || + part == OMAP4430_INVALID_PRCM_PARTITION || + !_cm_bases[part]); + __raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx)); +} + +/* Read-modify-write a register in CM1. Caller must lock */ +u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, + s16 idx) +{ + u32 v; + + v = omap4_cminst_read_inst_reg(part, inst, idx); + v &= ~mask; + v |= bits; + omap4_cminst_write_inst_reg(v, part, inst, idx); + + return v; +} + +/* + * + */ + +/** + * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield + * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) + * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * + * @c must be the unshifted value for CLKTRCTRL - i.e., this function + * will handle the shift itself. + */ +static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs) +{ + u32 v; + + v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); + v &= ~OMAP4430_CLKTRCTRL_MASK; + v |= c << OMAP4430_CLKTRCTRL_SHIFT; + omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); +} + +/** + * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? + * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * + * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) + * is in hardware-supervised idle mode, or 0 otherwise. + */ +bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs) +{ + u32 v; + + v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); + v &= OMAP4430_CLKTRCTRL_MASK; + v >>= OMAP4430_CLKTRCTRL_SHIFT; + + return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; +} + +/** + * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode + * @part: PRCM partition ID that the clockdomain registers exist in + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * + * Put a clockdomain referred to by (@part, @inst, @cdoffs) into + * hardware-supervised idle mode. No return value. + */ +void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs) +{ + _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); +} + +/** + * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode + * @part: PRCM partition ID that the clockdomain registers exist in + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * + * Put a clockdomain referred to by (@part, @inst, @cdoffs) into + * software-supervised idle mode, i.e., controlled manually by the + * Linux OMAP clockdomain code. No return value. + */ +void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs) +{ + _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); +} + +/** + * omap4_cminst_clkdm_force_sleep - try to put a clockdomain into idle + * @part: PRCM partition ID that the clockdomain registers exist in + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * + * Put a clockdomain referred to by (@part, @inst, @cdoffs) into idle + * No return value. + */ +void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs) +{ + _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); +} + +/** + * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle + * @part: PRCM partition ID that the clockdomain registers exist in + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * + * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, + * waking it up. No return value. + */ +void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs) +{ + _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); +} + +/* + * + */ + +/** + * omap4_cm_wait_module_ready - wait for a module to be in 'func' state + * @clkctrl_reg: CLKCTRL module address + * + * Wait for the module IDLEST to be functional. If the idle state is in any + * the non functional state (trans, idle or disabled), module and thus the + * sysconfig cannot be accessed and will probably lead to an "imprecise + * external abort" + * + * Module idle state: + * 0x0 func: Module is fully functional, including OCP + * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep + * abortion + * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if + * using separate functional clock + * 0x3 disabled: Module is disabled and cannot be accessed + * + */ +int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg) +{ + int i = 0; + + if (!clkctrl_reg) + return 0; + + omap_test_timeout(( + ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) || + (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >> + OMAP4430_IDLEST_SHIFT) == 0x2)), + MAX_MODULE_READY_TIME, i); + + return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; +} + diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h new file mode 100644 index 000000000000..a6abd0a8cb82 --- /dev/null +++ b/arch/arm/mach-omap2/cminst44xx.h @@ -0,0 +1,31 @@ +/* + * OMAP4 Clock Management (CM) function prototypes + * + * Copyright (C) 2010 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H +#define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H + +extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs); +extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs); +extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs); +extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs); +extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs); + +/* + * In an ideal world, we would not export these low-level functions, + * but this will probably take some time to fix properly + */ +extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx); +extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx); +extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, + s16 inst, s16 idx); + +extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg); + +#endif diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 1fa3294b6048..695279419020 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -20,12 +20,16 @@ #include "cm-regbits-34xx.h" #include "prm-regbits-34xx.h" -#include "cm.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" +#include "cm2xxx_3xxx.h" #include "sdrc.h" #include "pm.h" #include "control.h" +/* Used by omap3_ctrl_save_padconf() */ +#define START_PADCONF_SAVE 0x2 +#define PADCONF_SAVE_DONE 0x1 + static void __iomem *omap2_ctrl_base; static void __iomem *omap4_ctrl_pad_base; @@ -134,6 +138,7 @@ struct omap3_control_regs { u32 sramldo4; u32 sramldo5; u32 csi; + u32 padconf_sys_nirq; }; static struct omap3_control_regs control_context; @@ -209,6 +214,37 @@ void omap4_ctrl_pad_writel(u32 val, u16 offset) __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset)); } +#ifdef CONFIG_ARCH_OMAP3 + +/** + * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot + * @bootmode: 8-bit value to pass to some boot code + * + * Set the bootmode in the scratchpad RAM. This is used after the + * system restarts. Not sure what actually uses this - it may be the + * bootloader, rather than the boot ROM - contrary to the preserved + * comment below. No return value. + */ +void omap3_ctrl_write_boot_mode(u8 bootmode) +{ + u32 l; + + l = ('B' << 24) | ('M' << 16) | bootmode; + + /* + * Reserve the first word in scratchpad for communicating + * with the boot ROM. A pointer to a data structure + * describing the boot process can be stored there, + * cf. OMAP34xx TRM, Initialization / Software Booting + * Configuration. + * + * XXX This should use some omap_ctrl_writel()-type function + */ + __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); +} + +#endif + #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) /* * Clears the scratchpad contents in case of cold boot- @@ -220,13 +256,13 @@ void omap3_clear_scratchpad_contents(void) void __iomem *v_addr; u32 offset = 0; v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); - if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & + if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & OMAP3430_GLOBAL_COLD_RST_MASK) { for ( ; offset <= max_offset; offset += 0x4) __raw_writel(0x0, (v_addr + offset)); - prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, - OMAP3430_GR_MOD, - OMAP3_PRM_RSTST_OFFSET); + omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, + OMAP3430_GR_MOD, + OMAP3_PRM_RSTST_OFFSET); } } @@ -239,9 +275,19 @@ void omap3_save_scratchpad_contents(void) struct omap3_scratchpad_prcm_block prcm_block_contents; struct omap3_scratchpad_sdrc_block sdrc_block_contents; - /* Populate the Scratchpad contents */ + /* + * Populate the Scratchpad contents + * + * The "get_*restore_pointer" functions are used to provide a + * physical restore address where the ROM code jumps while waking + * up from MPU OFF/OSWR state. + * The restore pointer is stored into the scratchpad. + */ scratchpad_contents.boot_config_ptr = 0x0; - if (omap_rev() != OMAP3430_REV_ES3_0 && + if (cpu_is_omap3630()) + scratchpad_contents.public_restore_ptr = + virt_to_phys(get_omap3630_restore_pointer()); + else if (omap_rev() != OMAP3430_REV_ES3_0 && omap_rev() != OMAP3430_REV_ES3_1) scratchpad_contents.public_restore_ptr = virt_to_phys(get_restore_pointer()); @@ -258,32 +304,34 @@ void omap3_save_scratchpad_contents(void) scratchpad_contents.sdrc_block_offset = 0x64; /* Populate the PRCM block contents */ - prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD, - OMAP3_PRM_CLKSRC_CTRL_OFFSET); - prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD, - OMAP3_PRM_CLKSEL_OFFSET); + prcm_block_contents.prm_clksrc_ctrl = + omap2_prm_read_mod_reg(OMAP3430_GR_MOD, + OMAP3_PRM_CLKSRC_CTRL_OFFSET); + prcm_block_contents.prm_clksel = + omap2_prm_read_mod_reg(OMAP3430_CCR_MOD, + OMAP3_PRM_CLKSEL_OFFSET); prcm_block_contents.cm_clksel_core = - cm_read_mod_reg(CORE_MOD, CM_CLKSEL); + omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL); prcm_block_contents.cm_clksel_wkup = - cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); + omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); prcm_block_contents.cm_clken_pll = - cm_read_mod_reg(PLL_MOD, CM_CLKEN); + omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); prcm_block_contents.cm_autoidle_pll = - cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); prcm_block_contents.cm_clksel1_pll = - cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); prcm_block_contents.cm_clksel2_pll = - cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); prcm_block_contents.cm_clksel3_pll = - cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); prcm_block_contents.cm_clken_pll_mpu = - cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); prcm_block_contents.cm_autoidle_pll_mpu = - cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); prcm_block_contents.cm_clksel1_pll_mpu = - cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); prcm_block_contents.cm_clksel2_pll_mpu = - cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); prcm_block_contents.prcm_block_size = 0x0; /* Populate the SDRC block contents */ @@ -416,6 +464,8 @@ void omap3_control_save_context(void) control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); + control_context.padconf_sys_nirq = + omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); return; } @@ -472,6 +522,43 @@ void omap3_control_restore_context(void) omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); + omap_ctrl_writel(control_context.padconf_sys_nirq, + OMAP343X_CONTROL_PADCONF_SYSNIRQ); return; } + +void omap3630_ctrl_disable_rta(void) +{ + if (!cpu_is_omap3630()) + return; + omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL); +} + +/** + * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM + * + * Tell the SCM to start saving the padconf registers, then wait for + * the process to complete. Returns 0 unconditionally, although it + * should also eventually be able to return -ETIMEDOUT, if the save + * does not complete. + * + * XXX This function is missing a timeout. What should it be? + */ +int omap3_ctrl_save_padconf(void) +{ + u32 cpo; + + /* Save the padconf registers */ + cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); + cpo |= START_PADCONF_SAVE; + omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF); + + /* wait for the save to complete */ + while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) + & PADCONF_SAVE_DONE)) + udelay(1); + + return 0; +} + #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index b6c6b7c450b3..f0629ae04102 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -148,6 +148,15 @@ #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) +#define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) +#define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) +#define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) +#define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c) +#define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) +#define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124) +#define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) +#define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c) +#define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130) #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ @@ -164,6 +173,26 @@ #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) +/* OMAP3630 only CONTROL_GENERAL register offsets */ +#define OMAP3630_CONTROL_FUSE_OPP1G_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) +#define OMAP3630_CONTROL_FUSE_OPP50_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) +#define OMAP3630_CONTROL_FUSE_OPP100_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) +#define OMAP3630_CONTROL_FUSE_OPP120_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) +#define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) +#define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C) + +/* OMAP44xx control efuse offsets */ +#define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C +#define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F +#define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO 0x232 +#define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO 0x235 +#define OMAP44XX_CONTROL_FUSE_MPU_OPP50 0x240 +#define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243 +#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246 +#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249 +#define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254 +#define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257 + /* AM35XX only CONTROL_GENERAL register offsets */ #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) @@ -204,6 +233,10 @@ #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) +/* 36xx-only RTA - Retention till Accesss control registers and bits */ +#define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C +#define OMAP36XX_RTA_DISABLE 0x0 + /* 34xx D2D idle-related pins, handled by PM core */ #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 @@ -270,6 +303,8 @@ #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C +#define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\ + OMAP343X_SCRATCHPAD + reg) /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 @@ -309,7 +344,7 @@ #define FEAT_SGX_NONE 2 #define OMAP3_IVA_SHIFT 12 -#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT) +#define OMAP3_IVA_MASK (1 << OMAP3_IVA_SHIFT) #define FEAT_IVA 0 #define FEAT_IVA_NONE 1 @@ -347,10 +382,13 @@ extern void omap3_save_scratchpad_contents(void); extern void omap3_clear_scratchpad_contents(void); extern u32 *get_restore_pointer(void); extern u32 *get_es3_restore_pointer(void); +extern u32 *get_omap3630_restore_pointer(void); extern u32 omap3_arm_context[128]; extern void omap3_control_save_context(void); extern void omap3_control_restore_context(void); - +extern void omap3_ctrl_write_boot_mode(u8 bootmode); +extern void omap3630_ctrl_disable_rta(void); +extern int omap3_ctrl_save_padconf(void); #else #define omap_ctrl_base_get() 0 #define omap_ctrl_readb(x) 0 diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 0d50b45d041c..f3e043fe5eb8 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -27,8 +27,8 @@ #include <plat/prcm.h> #include <plat/irqs.h> -#include <plat/powerdomain.h> -#include <plat/clockdomain.h> +#include "powerdomain.h" +#include "clockdomain.h" #include <plat/serial.h> #include "pm.h" @@ -293,25 +293,26 @@ select_state: DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); /** - * omap3_cpuidle_update_states - Update the cpuidle states. + * omap3_cpuidle_update_states() - Update the cpuidle states + * @mpu_deepest_state: Enable states upto and including this for mpu domain + * @core_deepest_state: Enable states upto and including this for core domain * - * Currently, this function toggles the validity of idle states based upon - * the flag 'enable_off_mode'. When the flag is set all states are valid. - * Else, states leading to OFF state set to be invalid. + * This goes through the list of states available and enables and disables the + * validity of C states based on deepest state that can be achieved for the + * variable domain */ -void omap3_cpuidle_update_states(void) +void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state) { int i; for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) { struct omap3_processor_cx *cx = &omap3_power_states[i]; - if (enable_off_mode) { + if ((cx->mpu_state >= mpu_deepest_state) && + (cx->core_state >= core_deepest_state)) { cx->valid = 1; } else { - if ((cx->mpu_state == PWRDM_POWER_OFF) || - (cx->core_state == PWRDM_POWER_OFF)) - cx->valid = 0; + cx->valid = 0; } } } @@ -452,6 +453,18 @@ void omap_init_power_states(void) omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF; omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_CHECK_BM; + + /* + * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot + * enable OFF mode in a stable form for previous revisions. + * we disable C7 state as a result. + */ + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) { + omap3_power_states[OMAP3_STATE_C7].valid = 0; + cpuidle_params_table[OMAP3_STATE_C7].valid = 0; + WARN_ONCE(1, "%s: core off state C7 disabled due to i583\n", + __func__); + } } struct cpuidle_driver omap3_idle_driver = { @@ -504,7 +517,10 @@ int __init omap3_idle_init(void) return -EINVAL; dev->state_count = count; - omap3_cpuidle_update_states(); + if (enable_off_mode) + omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF); + else + omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET); if (cpuidle_register_device(dev)) { printk(KERN_ERR "%s: CPUidle register device failed\n", diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 5a0c148e23bc..381f4eb92352 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -638,6 +638,7 @@ static struct platform_device dummy_pdev = { static void __init omap_hsmmc_reset(void) { u32 i, nr_controllers; + struct clk *iclk, *fclk; if (cpu_is_omap242x()) return; @@ -647,7 +648,6 @@ static void __init omap_hsmmc_reset(void) for (i = 0; i < nr_controllers; i++) { u32 v, base = 0; - struct clk *iclk, *fclk; struct device *dev = &dummy_pdev.dev; switch (i) { @@ -678,19 +678,16 @@ static void __init omap_hsmmc_reset(void) dummy_pdev.id = i; dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); iclk = clk_get(dev, "ick"); - if (iclk && clk_enable(iclk)) - iclk = NULL; + if (IS_ERR(iclk)) + goto err1; + if (clk_enable(iclk)) + goto err2; fclk = clk_get(dev, "fck"); - if (fclk && clk_enable(fclk)) - fclk = NULL; - - if (!iclk || !fclk) { - printk(KERN_WARNING - "%s: Unable to enable clocks for MMC%d, " - "cannot reset.\n", __func__, i); - break; - } + if (IS_ERR(fclk)) + goto err3; + if (clk_enable(fclk)) + goto err4; omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG); v = omap_readl(base + MMCHS_SYSSTATUS); @@ -698,15 +695,22 @@ static void __init omap_hsmmc_reset(void) MMCHS_SYSSTATUS_RESETDONE)) cpu_relax(); - if (fclk) { - clk_disable(fclk); - clk_put(fclk); - } - if (iclk) { - clk_disable(iclk); - clk_put(iclk); - } + clk_disable(fclk); + clk_put(fclk); + clk_disable(iclk); + clk_put(iclk); } + return; + +err4: + clk_put(fclk); +err3: + clk_disable(iclk); +err2: + clk_put(iclk); +err1: + printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, " + "cannot reset.\n", __func__, i); } #else static inline void omap_hsmmc_reset(void) {} @@ -951,72 +955,12 @@ static inline void omap_init_vout(void) {} /*-------------------------------------------------------------------------*/ -/* - * Inorder to avoid any assumptions from bootloader regarding WDT - * settings, WDT module is reset during init. This enables the watchdog - * timer. Hence it is required to disable the watchdog after the WDT reset - * during init. Otherwise the system would reboot as per the default - * watchdog timer registers settings. - */ -#define OMAP_WDT_WPS (0x34) -#define OMAP_WDT_SPR (0x48) - -static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused) -{ - void __iomem *base; - int ret; - - if (!oh) { - pr_err("%s: Could not look up wdtimer_hwmod\n", __func__); - return -EINVAL; - } - - base = omap_hwmod_get_mpu_rt_va(oh); - if (!base) { - pr_err("%s: Could not get the base address for %s\n", - oh->name, __func__); - return -EINVAL; - } - - /* Enable the clocks before accessing the WDT registers */ - ret = omap_hwmod_enable(oh); - if (ret) { - pr_err("%s: Could not enable clocks for %s\n", - oh->name, __func__); - return ret; - } - - /* sequence required to disable watchdog */ - __raw_writel(0xAAAA, base + OMAP_WDT_SPR); - while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) - cpu_relax(); - - __raw_writel(0x5555, base + OMAP_WDT_SPR); - while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) - cpu_relax(); - - ret = omap_hwmod_idle(oh); - if (ret) - pr_err("%s: Could not disable clocks for %s\n", - oh->name, __func__); - - return ret; -} - -static void __init omap_disable_wdt(void) -{ - if (cpu_class_is_omap2()) - omap_hwmod_for_each_by_class("wd_timer", - omap2_disable_wdt, NULL); - return; -} - static int __init omap2_init_devices(void) { - /* please keep these calls, and their implementations above, + /* + * please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. */ - omap_disable_wdt(); omap_hsmmc_reset(); omap_init_audio(); omap_init_camera(); diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c new file mode 100644 index 000000000000..d2f15f5cfd36 --- /dev/null +++ b/arch/arm/mach-omap2/dma.c @@ -0,0 +1,297 @@ +/* + * OMAP2+ DMA driver + * + * Copyright (C) 2003 - 2008 Nokia Corporation + * Author: Juha Yrjölä <juha.yrjola@nokia.com> + * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> + * Graphics DMA and LCD DMA graphics tranformations + * by Imre Deak <imre.deak@nokia.com> + * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. + * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. + * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Converted DMA library into platform driver + * - G, Manjunath Kondaiah <manjugk@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/device.h> + +#include <plat/omap_hwmod.h> +#include <plat/omap_device.h> +#include <plat/dma.h> + +#define OMAP2_DMA_STRIDE 0x60 + +static u32 errata; +static u8 dma_stride; + +static struct omap_dma_dev_attr *d; + +static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end; + +static u16 reg_map[] = { + [REVISION] = 0x00, + [GCR] = 0x78, + [IRQSTATUS_L0] = 0x08, + [IRQSTATUS_L1] = 0x0c, + [IRQSTATUS_L2] = 0x10, + [IRQSTATUS_L3] = 0x14, + [IRQENABLE_L0] = 0x18, + [IRQENABLE_L1] = 0x1c, + [IRQENABLE_L2] = 0x20, + [IRQENABLE_L3] = 0x24, + [SYSSTATUS] = 0x28, + [OCP_SYSCONFIG] = 0x2c, + [CAPS_0] = 0x64, + [CAPS_2] = 0x6c, + [CAPS_3] = 0x70, + [CAPS_4] = 0x74, + + /* Common register offsets */ + [CCR] = 0x80, + [CLNK_CTRL] = 0x84, + [CICR] = 0x88, + [CSR] = 0x8c, + [CSDP] = 0x90, + [CEN] = 0x94, + [CFN] = 0x98, + [CSEI] = 0xa4, + [CSFI] = 0xa8, + [CDEI] = 0xac, + [CDFI] = 0xb0, + [CSAC] = 0xb4, + [CDAC] = 0xb8, + + /* Channel specific register offsets */ + [CSSA] = 0x9c, + [CDSA] = 0xa0, + [CCEN] = 0xbc, + [CCFN] = 0xc0, + [COLOR] = 0xc4, + + /* OMAP4 specific registers */ + [CDP] = 0xd0, + [CNDP] = 0xd4, + [CCDN] = 0xd8, +}; + +static struct omap_device_pm_latency omap2_dma_latency[] = { + { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; + +static void __iomem *dma_base; +static inline void dma_write(u32 val, int reg, int lch) +{ + u8 stride; + u32 offset; + + stride = (reg >= dma_common_ch_start) ? dma_stride : 0; + offset = reg_map[reg] + (stride * lch); + __raw_writel(val, dma_base + offset); +} + +static inline u32 dma_read(int reg, int lch) +{ + u8 stride; + u32 offset, val; + + stride = (reg >= dma_common_ch_start) ? dma_stride : 0; + offset = reg_map[reg] + (stride * lch); + val = __raw_readl(dma_base + offset); + return val; +} + +static inline void omap2_disable_irq_lch(int lch) +{ + u32 val; + + val = dma_read(IRQENABLE_L0, lch); + val &= ~(1 << lch); + dma_write(val, IRQENABLE_L0, lch); +} + +static void omap2_clear_dma(int lch) +{ + int i = dma_common_ch_start; + + for (; i <= dma_common_ch_end; i += 1) + dma_write(0, i, lch); +} + +static void omap2_show_dma_caps(void) +{ + u8 revision = dma_read(REVISION, 0) & 0xff; + printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", + revision >> 4, revision & 0xf); + return; +} + +static u32 configure_dma_errata(void) +{ + + /* + * Errata applicable for OMAP2430ES1.0 and all omap2420 + * + * I. + * Erratum ID: Not Available + * Inter Frame DMA buffering issue DMA will wrongly + * buffer elements if packing and bursting is enabled. This might + * result in data gets stalled in FIFO at the end of the block. + * Workaround: DMA channels must have BUFFERING_DISABLED bit set to + * guarantee no data will stay in the DMA FIFO in case inter frame + * buffering occurs + * + * II. + * Erratum ID: Not Available + * DMA may hang when several channels are used in parallel + * In the following configuration, DMA channel hanging can occur: + * a. Channel i, hardware synchronized, is enabled + * b. Another channel (Channel x), software synchronized, is enabled. + * c. Channel i is disabled before end of transfer + * d. Channel i is reenabled. + * e. Steps 1 to 4 are repeated a certain number of times. + * f. A third channel (Channel y), software synchronized, is enabled. + * Channel x and Channel y may hang immediately after step 'f'. + * Workaround: + * For any channel used - make sure NextLCH_ID is set to the value j. + */ + if (cpu_is_omap2420() || (cpu_is_omap2430() && + (omap_type() == OMAP2430_REV_ES1_0))) { + + SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING); + SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS); + } + + /* + * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled + * after a transaction error. + * Workaround: SW should explicitely disable the channel. + */ + if (cpu_class_is_omap2()) + SET_DMA_ERRATA(DMA_ERRATA_i378); + + /* + * Erratum ID: i541: sDMA FIFO draining does not finish + * If sDMA channel is disabled on the fly, sDMA enters standby even + * through FIFO Drain is still in progress + * Workaround: Put sDMA in NoStandby more before a logical channel is + * disabled, then put it back to SmartStandby right after the channel + * finishes FIFO draining. + */ + if (cpu_is_omap34xx()) + SET_DMA_ERRATA(DMA_ERRATA_i541); + + /* + * Erratum ID: i88 : Special programming model needed to disable DMA + * before end of block. + * Workaround: software must ensure that the DMA is configured in No + * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01") + */ + if (omap_type() == OMAP3430_REV_ES1_0) + SET_DMA_ERRATA(DMA_ERRATA_i88); + + /* + * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is + * read before the DMA controller finished disabling the channel. + */ + SET_DMA_ERRATA(DMA_ERRATA_3_3); + + /* + * Erratum ID: Not Available + * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared + * after secure sram context save and restore. + * Work around: Hence we need to manually clear those IRQs to avoid + * spurious interrupts. This affects only secure devices. + */ + if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) + SET_DMA_ERRATA(DMA_ROMCODE_BUG); + + return errata; +} + +/* One time initializations */ +static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) +{ + struct omap_device *od; + struct omap_system_dma_plat_info *p; + struct resource *mem; + char *name = "omap_dma_system"; + + dma_stride = OMAP2_DMA_STRIDE; + dma_common_ch_start = CSDP; + if (cpu_is_omap3630() || cpu_is_omap4430()) + dma_common_ch_end = CCDN; + else + dma_common_ch_end = CCFN; + + p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL); + if (!p) { + pr_err("%s: Unable to allocate pdata for %s:%s\n", + __func__, name, oh->name); + return -ENOMEM; + } + + p->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr; + p->disable_irq_lch = omap2_disable_irq_lch; + p->show_dma_caps = omap2_show_dma_caps; + p->clear_dma = omap2_clear_dma; + p->dma_write = dma_write; + p->dma_read = dma_read; + + p->clear_lch_regs = NULL; + + p->errata = configure_dma_errata(); + + od = omap_device_build(name, 0, oh, p, sizeof(*p), + omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0); + kfree(p); + if (IS_ERR(od)) { + pr_err("%s: Cant build omap_device for %s:%s.\n", + __func__, name, oh->name); + return IS_ERR(od); + } + + mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__); + return -EINVAL; + } + dma_base = ioremap(mem->start, resource_size(mem)); + if (!dma_base) { + dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__); + return -ENOMEM; + } + + d = oh->dev_attr; + d->chan = kzalloc(sizeof(struct omap_dma_lch) * + (d->lch_count), GFP_KERNEL); + + if (!d->chan) { + dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__); + return -ENOMEM; + } + return 0; +} + +static int __init omap2_system_dma_init(void) +{ + return omap_hwmod_for_each_by_class("dma", + omap2_system_dma_init_dev, NULL); +} +arch_initcall(omap2_system_dma_init); diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index ebb888f59365..f77022be783d 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -32,9 +32,7 @@ #include <plat/clock.h> #include "clock.h" -#include "prm.h" -#include "prm-regbits-34xx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ @@ -225,10 +223,9 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) } /** - * lookup_dco_sddiv - Set j-type DPLL4 compensation variables + * _lookup_dco - Lookup DCO used by j-type DPLL * @clk: pointer to a DPLL struct clk * @dco: digital control oscillator selector - * @sd_div: target sigma-delta divider * @m: DPLL multiplier to set * @n: DPLL divider to set * @@ -237,11 +234,9 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) * XXX This code is not needed for 3430/AM35xx; can it be optimized * out in non-multi-OMAP builds for those chips? */ -static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m, - u8 n) +static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) { - unsigned long fint, clkinp, sd; /* watch out for overflow */ - int mod1, mod2; + unsigned long fint, clkinp; /* watch out for overflow */ clkinp = clk->parent->rate; fint = (clkinp / n) * m; @@ -250,6 +245,27 @@ static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m, *dco = 2; else *dco = 4; +} + +/** + * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL + * @clk: pointer to a DPLL struct clk + * @sd_div: target sigma-delta divider + * @m: DPLL multiplier to set + * @n: DPLL divider to set + * + * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" + * + * XXX This code is not needed for 3430/AM35xx; can it be optimized + * out in non-multi-OMAP builds for those chips? + */ +static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) +{ + unsigned long clkinp, sd; /* watch out for overflow */ + int mod1, mod2; + + clkinp = clk->parent->rate; + /* * target sigma-delta to near 250MHz * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] @@ -278,6 +294,7 @@ static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m, static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) { struct dpll_data *dd = clk->dpll_data; + u8 dco, sd_div; u32 v; /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ @@ -300,18 +317,16 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) v |= m << __ffs(dd->mult_mask); v |= (n - 1) << __ffs(dd->div1_mask); - /* - * XXX This code is not needed for 3430/AM35XX; can it be optimized - * out in non-multi-OMAP builds for those chips? - */ - if ((dd->flags & DPLL_J_TYPE) && !(dd->flags & DPLL_NO_DCO_SEL)) { - u8 dco, sd_div; - lookup_dco_sddiv(clk, &dco, &sd_div, m, n); - /* XXX This probably will need revision for OMAP4 */ - v &= ~(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK - | OMAP3630_PERIPH_DPLL_SD_DIV_MASK); - v |= dco << __ffs(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK); - v |= sd_div << __ffs(OMAP3630_PERIPH_DPLL_SD_DIV_MASK); + /* Configure dco and sd_div for dplls that have these fields */ + if (dd->dco_mask) { + _lookup_dco(clk, &dco, m, n); + v &= ~(dd->dco_mask); + v |= dco << __ffs(dd->dco_mask); + } + if (dd->sddiv_mask) { + _lookup_sddiv(clk, &sd_div, m, n); + v &= ~(dd->sddiv_mask); + v |= sd_div << __ffs(dd->sddiv_mask); } __raw_writel(v, dd->mult_div1_reg); diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c index 6feeeae6c21b..911cd2e68d46 100644 --- a/arch/arm/mach-omap2/dsp.c +++ b/arch/arm/mach-omap2/dsp.c @@ -11,9 +11,16 @@ * published by the Free Software Foundation. */ +/* + * XXX The function pointers to the PRM/CM functions are incorrect and + * should be removed. No device driver should be changing PRM/CM bits + * directly; that's a layering violation -- those bits are the responsibility + * of the OMAP PM core code. + */ + #include <linux/platform_device.h> -#include "prm.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" +#include "prm2xxx_3xxx.h" #ifdef CONFIG_BRIDGE_DVFS #include <plat/omap-pm.h> #endif @@ -31,12 +38,12 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { .cpu_set_freq = omap_pm_cpu_set_freq, .cpu_get_freq = omap_pm_cpu_get_freq, #endif - .dsp_prm_read = prm_read_mod_reg, - .dsp_prm_write = prm_write_mod_reg, - .dsp_prm_rmw_bits = prm_rmw_mod_reg_bits, - .dsp_cm_read = cm_read_mod_reg, - .dsp_cm_write = cm_write_mod_reg, - .dsp_cm_rmw_bits = cm_rmw_mod_reg_bits, + .dsp_prm_read = omap2_prm_read_mod_reg, + .dsp_prm_write = omap2_prm_write_mod_reg, + .dsp_prm_rmw_bits = omap2_prm_rmw_mod_reg_bits, + .dsp_cm_read = omap2_cm_read_mod_reg, + .dsp_cm_write = omap2_cm_write_mod_reg, + .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits, }; static int __init omap_dsp_init(void) diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c new file mode 100644 index 000000000000..413de18c1d2b --- /dev/null +++ b/arch/arm/mach-omap2/gpio.c @@ -0,0 +1,104 @@ +/* + * OMAP2+ specific gpio initialization + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Author: + * Charulatha V <charu@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/gpio.h> +#include <linux/err.h> +#include <linux/slab.h> +#include <linux/interrupt.h> + +#include <plat/omap_hwmod.h> +#include <plat/omap_device.h> + +static struct omap_device_pm_latency omap_gpio_latency[] = { + [0] = { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; + +static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) +{ + struct omap_device *od; + struct omap_gpio_platform_data *pdata; + struct omap_gpio_dev_attr *dev_attr; + char *name = "omap_gpio"; + int id; + + /* + * extract the device id from name field available in the + * hwmod database and use the same for constructing ids for + * gpio devices. + * CAUTION: Make sure the name in the hwmod database does + * not change. If changed, make corresponding change here + * or make use of static variable mechanism to handle this. + */ + sscanf(oh->name, "gpio%d", &id); + + pdata = kzalloc(sizeof(struct omap_gpio_platform_data), GFP_KERNEL); + if (!pdata) { + pr_err("gpio%d: Memory allocation failed\n", id); + return -ENOMEM; + } + + dev_attr = (struct omap_gpio_dev_attr *)oh->dev_attr; + pdata->bank_width = dev_attr->bank_width; + pdata->dbck_flag = dev_attr->dbck_flag; + pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1); + + switch (oh->class->rev) { + case 0: + case 1: + pdata->bank_type = METHOD_GPIO_24XX; + break; + case 2: + pdata->bank_type = METHOD_GPIO_44XX; + break; + default: + WARN(1, "Invalid gpio bank_type\n"); + kfree(pdata); + return -EINVAL; + } + + od = omap_device_build(name, id - 1, oh, pdata, + sizeof(*pdata), omap_gpio_latency, + ARRAY_SIZE(omap_gpio_latency), + false); + kfree(pdata); + + if (IS_ERR(od)) { + WARN(1, "Cant build omap_device for %s:%s.\n", + name, oh->name); + return PTR_ERR(od); + } + + gpio_bank_count++; + return 0; +} + +/* + * gpio_init needs to be done before + * machine_init functions access gpio APIs. + * Hence gpio_init is a postcore_initcall. + */ +static int __init omap2_gpio_init(void) +{ + return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init, + NULL); +} +postcore_initcall(omap2_gpio_init); diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 722209601927..2bb29c160702 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -41,7 +41,7 @@ static int omap2_nand_gpmc_retime(void) return 0; memset(&t, 0, sizeof(t)); - t.sync_clk = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->sync_clk); + t.sync_clk = gpmc_nand_data->gpmc_t->sync_clk; t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on); t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on); diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 7bb69220adfa..3a7d25fb00ef 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -173,8 +173,17 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, } switch (freq) { + case 104: + min_gpmc_clk_period = 9600; /* 104 MHz */ + t_ces = 3; + t_avds = 4; + t_avdh = 2; + t_ach = 3; + t_aavdh = 6; + t_rdyo = 9; + break; case 83: - min_gpmc_clk_period = 12; /* 83 MHz */ + min_gpmc_clk_period = 12000; /* 83 MHz */ t_ces = 5; t_avds = 4; t_avdh = 2; @@ -183,7 +192,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, t_rdyo = 9; break; case 66: - min_gpmc_clk_period = 15; /* 66 MHz */ + min_gpmc_clk_period = 15000; /* 66 MHz */ t_ces = 6; t_avds = 5; t_avdh = 2; @@ -192,7 +201,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, t_rdyo = 11; break; default: - min_gpmc_clk_period = 18; /* 54 MHz */ + min_gpmc_clk_period = 18500; /* 54 MHz */ t_ces = 7; t_avds = 7; t_avdh = 7; @@ -271,8 +280,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, t.wr_cycle = t.rd_cycle; if (cpu_is_omap34xx()) { t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset + - gpmc_ns_to_ticks(min_gpmc_clk_period + - t_rdyo)); + gpmc_ps_to_ticks(min_gpmc_clk_period + + t_rdyo * 1000)); t.wr_access = t.access; } } else { diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index f46933bc9373..1b7b3e7d02f7 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -168,6 +168,16 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns) return (time_ns * 1000 + tick_ps - 1) / tick_ps; } +unsigned int gpmc_ps_to_ticks(unsigned int time_ps) +{ + unsigned long tick_ps; + + /* Calculate in picosecs to yield more exact results */ + tick_ps = gpmc_get_fclk_period(); + + return (time_ps + tick_ps - 1) / tick_ps; +} + unsigned int gpmc_ticks_to_ns(unsigned int ticks) { return ticks * gpmc_get_fclk_period() / 1000; @@ -235,7 +245,7 @@ int gpmc_cs_calc_divider(int cs, unsigned int sync_clk) int div; u32 l; - l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1); + l = sync_clk + (gpmc_get_fclk_period() - 1); div = l / gpmc_get_fclk_period(); if (div > 4) return -1; diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index d54c4f89a8bd..befa321c4c13 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S @@ -38,41 +38,27 @@ */ #ifdef MULTI_OMAP2 + +/* + * We use __glue to avoid errors with multiple definitions of + * .globl omap_irq_base as it's included from entry-armv.S but not + * from entry-common.S. + */ +#ifdef __glue .pushsection .data -omap_irq_base: .word 0 + .globl omap_irq_base +omap_irq_base: + .word 0 .popsection +#endif - /* Configure the interrupt base on the first interrupt */ + /* + * Configure the interrupt base on the first interrupt. + * See also omap_irq_base_init for setting omap_irq_base. + */ .macro get_irqnr_preamble, base, tmp -9: ldr \base, =omap_irq_base @ irq base address ldr \base, [\base, #0] @ irq base value - cmp \base, #0 @ already configured? - bne 9997f @ nothing to do - - mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision - and \tmp, \tmp, #0x000f0000 @ only check architecture - cmp \tmp, #0x00070000 @ is v6? - beq 2400f @ found v6 so it's omap24xx - mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision - and \tmp, \tmp, #0x000000f0 @ check cortex 8 or 9 - cmp \tmp, #0x00000080 @ cortex A-8? - beq 3400f @ found A-8 so it's omap34xx - cmp \tmp, #0x00000090 @ cortex A-9? - beq 4400f @ found A-9 so it's omap44xx -2400: ldr \base, =OMAP2_IRQ_BASE - ldr \tmp, =omap_irq_base - str \base, [\tmp, #0] - b 9b -3400: ldr \base, =OMAP3_IRQ_BASE - ldr \tmp, =omap_irq_base - str \base, [\tmp, #0] - b 9b -4400: ldr \base, =OMAP4_IRQ_BASE - ldr \tmp, =omap_irq_base - str \base, [\tmp, #0] - b 9b -9997: .endm /* Check the pending interrupts. Note that base already set */ diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index a1939b1e6f82..e66687b0b9de 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -39,13 +39,11 @@ #include "io.h" #include <plat/omap-pm.h> -#include <plat/powerdomain.h> -#include "powerdomains.h" - -#include <plat/clockdomain.h> -#include "clockdomains.h" +#include "powerdomain.h" +#include "clockdomain.h" #include <plat/omap_hwmod.h> +#include <plat/multi.h> /* * The machine specific code may provide the extra mapping besides the @@ -311,24 +309,81 @@ static int __init _omap2_init_reprogram_sdrc(void) return v; } -void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, - struct omap_sdrc_params *sdrc_cs1) +static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) +{ + return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); +} + +/* + * Initialize asm_irq_base for entry-macro.S + */ +static inline void omap_irq_base_init(void) +{ + extern void __iomem *omap_irq_base; + +#ifdef MULTI_OMAP2 + if (cpu_is_omap24xx()) + omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE); + else if (cpu_is_omap34xx()) + omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE); + else if (cpu_is_omap44xx()) + omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE); + else + pr_err("Could not initialize omap_irq_base\n"); +#endif +} + +void __init omap2_init_common_infrastructure(void) { - u8 skip_setup_idle = 0; + u8 postsetup_state; - pwrdm_init(powerdomains_omap); - clkdm_init(clockdomains_omap, clkdm_autodeps); - if (cpu_is_omap242x()) + if (cpu_is_omap242x()) { + omap2xxx_powerdomains_init(); + omap2_clockdomains_init(); omap2420_hwmod_init(); - else if (cpu_is_omap243x()) + } else if (cpu_is_omap243x()) { + omap2xxx_powerdomains_init(); + omap2_clockdomains_init(); omap2430_hwmod_init(); - else if (cpu_is_omap34xx()) + } else if (cpu_is_omap34xx()) { + omap3xxx_powerdomains_init(); + omap2_clockdomains_init(); omap3xxx_hwmod_init(); - else if (cpu_is_omap44xx()) + } else if (cpu_is_omap44xx()) { + omap44xx_powerdomains_init(); + omap44xx_clockdomains_init(); omap44xx_hwmod_init(); + } else { + pr_err("Could not init hwmod data - unknown SoC\n"); + } + + /* Set the default postsetup state for all hwmods */ +#ifdef CONFIG_PM_RUNTIME + postsetup_state = _HWMOD_STATE_IDLE; +#else + postsetup_state = _HWMOD_STATE_ENABLED; +#endif + omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); + + /* + * Set the default postsetup state for unusual modules (like + * MPU WDT). + * + * The postsetup_state is not actually used until + * omap_hwmod_late_init(), so boards that desire full watchdog + * coverage of kernel initialization can reprogram the + * postsetup_state between the calls to + * omap2_init_common_infra() and omap2_init_common_devices(). + * + * XXX ideally we could detect whether the MPU WDT was currently + * enabled here and make this conditional + */ + postsetup_state = _HWMOD_STATE_DISABLED; + omap_hwmod_for_each_by_class("wd_timer", + _set_hwmod_postsetup_state, + &postsetup_state); - /* The OPP tables have to be registered before a clk init */ - omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); + omap_pm_if_early_init(); if (cpu_is_omap2420()) omap2420_clk_init(); @@ -339,17 +394,61 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, else if (cpu_is_omap44xx()) omap4xxx_clk_init(); else - pr_err("Could not init clock framework - unknown CPU\n"); + pr_err("Could not init clock framework - unknown SoC\n"); +} +void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, + struct omap_sdrc_params *sdrc_cs1) +{ omap_serial_early_init(); -#ifndef CONFIG_PM_RUNTIME - skip_setup_idle = 1; -#endif - omap_hwmod_late_init(skip_setup_idle); + omap_hwmod_late_init(); + if (cpu_is_omap24xx() || cpu_is_omap34xx()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); } gpmc_init(); + + omap_irq_base_init(); +} + +/* + * NOTE: Please use ioremap + __raw_read/write where possible instead of these + */ + +u8 omap_readb(u32 pa) +{ + return __raw_readb(OMAP2_L4_IO_ADDRESS(pa)); +} +EXPORT_SYMBOL(omap_readb); + +u16 omap_readw(u32 pa) +{ + return __raw_readw(OMAP2_L4_IO_ADDRESS(pa)); +} +EXPORT_SYMBOL(omap_readw); + +u32 omap_readl(u32 pa) +{ + return __raw_readl(OMAP2_L4_IO_ADDRESS(pa)); +} +EXPORT_SYMBOL(omap_readl); + +void omap_writeb(u8 v, u32 pa) +{ + __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa)); +} +EXPORT_SYMBOL(omap_writeb); + +void omap_writew(u16 v, u32 pa) +{ + __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa)); +} +EXPORT_SYMBOL(omap_writew); + +void omap_writel(u32 v, u32 pa) +{ + __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa)); } +EXPORT_SYMBOL(omap_writel); diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 32eeabe9d2ab..85bf8ca95fd3 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -284,7 +284,10 @@ void omap3_intc_suspend(void) void omap3_intc_prepare_idle(void) { - /* Disable autoidle as it can stall interrupt controller */ + /* + * Disable autoidle as it can stall interrupt controller, + * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) + */ intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG); } diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 40ddecab93a9..394413dc7deb 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -281,7 +281,7 @@ static struct omap_mbox_ops omap2_mbox_ops = { /* FIXME: the following structs should be filled automatically by the user id */ -#if defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_ARCH_OMAP2420) +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2) /* DSP */ static struct omap_mbox2_priv omap2_mbox_dsp_priv = { .tx_fifo = { @@ -306,7 +306,7 @@ struct omap_mbox mbox_dsp_info = { }; #endif -#if defined(CONFIG_ARCH_OMAP3430) +#if defined(CONFIG_ARCH_OMAP3) struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL }; #endif @@ -394,15 +394,19 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev) if (false) ; -#if defined(CONFIG_ARCH_OMAP3430) - else if (cpu_is_omap3430()) { +#if defined(CONFIG_ARCH_OMAP3) + else if (cpu_is_omap34xx()) { list = omap3_mboxes; list[0]->irq = platform_get_irq_byname(pdev, "dsp"); } #endif -#if defined(CONFIG_ARCH_OMAP2420) - else if (cpu_is_omap2420()) { +#if defined(CONFIG_ARCH_OMAP2) + else if (cpu_is_omap2430()) { + list = omap2_mboxes; + + list[0]->irq = platform_get_irq_byname(pdev, "dsp"); + } else if (cpu_is_omap2420()) { list = omap2_mboxes; list[0]->irq = platform_get_irq_byname(pdev, "dsp"); @@ -432,9 +436,8 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev) iounmap(mbox_base); return ret; } - return 0; - return ret; + return 0; } static int __devexit omap2_mbox_remove(struct platform_device *pdev) diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 074536ae401f..17bd6394d224 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -1,9 +1,9 @@ /* * linux/arch/arm/mach-omap2/mux.c * - * OMAP2 and OMAP3 pin multiplexing configurations + * OMAP2, OMAP3 and OMAP4 pin multiplexing configurations * - * Copyright (C) 2004 - 2008 Texas Instruments Inc. + * Copyright (C) 2004 - 2010 Texas Instruments Inc. * Copyright (C) 2003 - 2008 Nokia Corporation * * Written by Tony Lindgren @@ -35,65 +35,79 @@ #include <asm/system.h> +#include <plat/omap_hwmod.h> + #include "control.h" #include "mux.h" #define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ #define OMAP_MUX_BASE_SZ 0x5ca -#define MUXABLE_GPIO_MODE3 BIT(0) struct omap_mux_entry { struct omap_mux mux; struct list_head node; }; -static unsigned long mux_phys; -static void __iomem *mux_base; -static u8 omap_mux_flags; +static LIST_HEAD(mux_partitions); +static DEFINE_MUTEX(muxmode_mutex); + +struct omap_mux_partition *omap_mux_get(const char *name) +{ + struct omap_mux_partition *partition; + + list_for_each_entry(partition, &mux_partitions, node) { + if (!strcmp(name, partition->name)) + return partition; + } + + return NULL; +} -u16 omap_mux_read(u16 reg) +u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg) { - if (cpu_is_omap24xx()) - return __raw_readb(mux_base + reg); + if (partition->flags & OMAP_MUX_REG_8BIT) + return __raw_readb(partition->base + reg); else - return __raw_readw(mux_base + reg); + return __raw_readw(partition->base + reg); } -void omap_mux_write(u16 val, u16 reg) +void omap_mux_write(struct omap_mux_partition *partition, u16 val, + u16 reg) { - if (cpu_is_omap24xx()) - __raw_writeb(val, mux_base + reg); + if (partition->flags & OMAP_MUX_REG_8BIT) + __raw_writeb(val, partition->base + reg); else - __raw_writew(val, mux_base + reg); + __raw_writew(val, partition->base + reg); } -void omap_mux_write_array(struct omap_board_mux *board_mux) +void omap_mux_write_array(struct omap_mux_partition *partition, + struct omap_board_mux *board_mux) { - while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) { - omap_mux_write(board_mux->value, board_mux->reg_offset); + while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) { + omap_mux_write(partition, board_mux->value, + board_mux->reg_offset); board_mux++; } } -static LIST_HEAD(muxmodes); -static DEFINE_MUTEX(muxmode_mutex); - #ifdef CONFIG_OMAP_MUX static char *omap_mux_options; -int __init omap_mux_init_gpio(int gpio, int val) +static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition, + int gpio, int val) { struct omap_mux_entry *e; struct omap_mux *gpio_mux = NULL; u16 old_mode; u16 mux_mode; int found = 0; + struct list_head *muxmodes = &partition->muxmodes; if (!gpio) return -EINVAL; - list_for_each_entry(e, &muxmodes, node) { + list_for_each_entry(e, muxmodes, node) { struct omap_mux *m = &e->mux; if (gpio == m->gpio) { gpio_mux = m; @@ -102,34 +116,52 @@ int __init omap_mux_init_gpio(int gpio, int val) } if (found == 0) { - printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); + pr_err("%s: Could not set gpio%i\n", __func__, gpio); return -ENODEV; } if (found > 1) { - printk(KERN_INFO "mux: Multiple gpio paths (%d) for gpio%i\n", - found, gpio); + pr_info("%s: Multiple gpio paths (%d) for gpio%i\n", __func__, + found, gpio); return -EINVAL; } - old_mode = omap_mux_read(gpio_mux->reg_offset); + old_mode = omap_mux_read(partition, gpio_mux->reg_offset); mux_mode = val & ~(OMAP_MUX_NR_MODES - 1); - if (omap_mux_flags & MUXABLE_GPIO_MODE3) + if (partition->flags & OMAP_MUX_GPIO_IN_MODE3) mux_mode |= OMAP_MUX_MODE3; else mux_mode |= OMAP_MUX_MODE4; - printk(KERN_DEBUG "mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", - gpio_mux->muxnames[0], gpio, old_mode, mux_mode); - omap_mux_write(mux_mode, gpio_mux->reg_offset); + pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__, + gpio_mux->muxnames[0], gpio, old_mode, mux_mode); + omap_mux_write(partition, mux_mode, gpio_mux->reg_offset); return 0; } -int __init omap_mux_init_signal(const char *muxname, int val) +int __init omap_mux_init_gpio(int gpio, int val) +{ + struct omap_mux_partition *partition; + int ret; + + list_for_each_entry(partition, &mux_partitions, node) { + ret = _omap_mux_init_gpio(partition, gpio, val); + if (!ret) + return ret; + } + + return -ENODEV; +} + +static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition, + const char *muxname, + struct omap_mux **found_mux) { + struct omap_mux *mux = NULL; struct omap_mux_entry *e; const char *mode_name; - int found = 0, mode0_len = 0; + int found = 0, found_mode, mode0_len = 0; + struct list_head *muxmodes = &partition->muxmodes; mode_name = strchr(muxname, '.'); if (mode_name) { @@ -139,51 +171,200 @@ int __init omap_mux_init_signal(const char *muxname, int val) mode_name = muxname; } - list_for_each_entry(e, &muxmodes, node) { - struct omap_mux *m = &e->mux; - char *m0_entry = m->muxnames[0]; + list_for_each_entry(e, muxmodes, node) { + char *m0_entry; int i; + mux = &e->mux; + m0_entry = mux->muxnames[0]; + /* First check for full name in mode0.muxmode format */ if (mode0_len && strncmp(muxname, m0_entry, mode0_len)) continue; /* Then check for muxmode only */ for (i = 0; i < OMAP_MUX_NR_MODES; i++) { - char *mode_cur = m->muxnames[i]; + char *mode_cur = mux->muxnames[i]; if (!mode_cur) continue; if (!strcmp(mode_name, mode_cur)) { - u16 old_mode; - u16 mux_mode; - - old_mode = omap_mux_read(m->reg_offset); - mux_mode = val | i; - printk(KERN_DEBUG "mux: Setting signal " - "%s.%s 0x%04x -> 0x%04x\n", - m0_entry, muxname, old_mode, mux_mode); - omap_mux_write(mux_mode, m->reg_offset); + *found_mux = mux; found++; + found_mode = i; } } } - if (found == 1) - return 0; + if (found == 1) { + return found_mode; + } if (found > 1) { - printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n", - found, muxname); + pr_err("%s: Multiple signal paths (%i) for %s\n", __func__, + found, muxname); return -EINVAL; } - printk(KERN_ERR "mux: Could not set signal %s\n", muxname); + pr_err("%s: Could not find signal %s\n", __func__, muxname); return -ENODEV; } +static int __init +omap_mux_get_by_name(const char *muxname, + struct omap_mux_partition **found_partition, + struct omap_mux **found_mux) +{ + struct omap_mux_partition *partition; + + list_for_each_entry(partition, &mux_partitions, node) { + struct omap_mux *mux = NULL; + int mux_mode = _omap_mux_get_by_name(partition, muxname, &mux); + if (mux_mode < 0) + continue; + + *found_partition = partition; + *found_mux = mux; + + return mux_mode; + } + + return -ENODEV; +} + +int __init omap_mux_init_signal(const char *muxname, int val) +{ + struct omap_mux_partition *partition = NULL; + struct omap_mux *mux = NULL; + u16 old_mode; + int mux_mode; + + mux_mode = omap_mux_get_by_name(muxname, &partition, &mux); + if (mux_mode < 0) + return mux_mode; + + old_mode = omap_mux_read(partition, mux->reg_offset); + mux_mode |= val; + pr_debug("%s: Setting signal %s 0x%04x -> 0x%04x\n", + __func__, muxname, old_mode, mux_mode); + omap_mux_write(partition, mux_mode, mux->reg_offset); + + return 0; +} + +struct omap_hwmod_mux_info * __init +omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads) +{ + struct omap_hwmod_mux_info *hmux; + int i; + + if (!bpads || nr_pads < 1) + return NULL; + + hmux = kzalloc(sizeof(struct omap_hwmod_mux_info), GFP_KERNEL); + if (!hmux) + goto err1; + + hmux->nr_pads = nr_pads; + + hmux->pads = kzalloc(sizeof(struct omap_device_pad) * + nr_pads, GFP_KERNEL); + if (!hmux->pads) + goto err2; + + for (i = 0; i < hmux->nr_pads; i++) { + struct omap_mux_partition *partition; + struct omap_device_pad *bpad = &bpads[i], *pad = &hmux->pads[i]; + struct omap_mux *mux; + int mux_mode; + + mux_mode = omap_mux_get_by_name(bpad->name, &partition, &mux); + if (mux_mode < 0) + goto err3; + if (!pad->partition) + pad->partition = partition; + if (!pad->mux) + pad->mux = mux; + + pad->name = kzalloc(strlen(bpad->name) + 1, GFP_KERNEL); + if (!pad->name) { + int j; + + for (j = i - 1; j >= 0; j--) + kfree(hmux->pads[j].name); + goto err3; + } + strcpy(pad->name, bpad->name); + + pad->flags = bpad->flags; + pad->enable = bpad->enable; + pad->idle = bpad->idle; + pad->off = bpad->off; + pr_debug("%s: Initialized %s\n", __func__, pad->name); + } + + return hmux; + +err3: + kfree(hmux->pads); +err2: + kfree(hmux); +err1: + pr_err("%s: Could not allocate device mux entry\n", __func__); + + return NULL; +} + +/* Assumes the calling function takes care of locking */ +void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state) +{ + int i; + + for (i = 0; i < hmux->nr_pads; i++) { + struct omap_device_pad *pad = &hmux->pads[i]; + int flags, val = -EINVAL; + + flags = pad->flags; + + switch (state) { + case _HWMOD_STATE_ENABLED: + if (flags & OMAP_DEVICE_PAD_ENABLED) + break; + flags |= OMAP_DEVICE_PAD_ENABLED; + val = pad->enable; + pr_debug("%s: Enabling %s %x\n", __func__, + pad->name, val); + break; + case _HWMOD_STATE_IDLE: + if (!(flags & OMAP_DEVICE_PAD_REMUX)) + break; + flags &= ~OMAP_DEVICE_PAD_ENABLED; + val = pad->idle; + pr_debug("%s: Idling %s %x\n", __func__, + pad->name, val); + break; + case _HWMOD_STATE_DISABLED: + default: + /* Use safe mode unless OMAP_DEVICE_PAD_REMUX */ + if (flags & OMAP_DEVICE_PAD_REMUX) + val = pad->off; + else + val = OMAP_MUX_MODE7; + flags &= ~OMAP_DEVICE_PAD_ENABLED; + pr_debug("%s: Disabling %s %x\n", __func__, + pad->name, val); + }; + + if (val >= 0) { + omap_mux_write(pad->partition, val, + pad->mux->reg_offset); + pad->flags = flags; + } + } +} + #ifdef CONFIG_DEBUG_FS #define OMAP_MUX_MAX_NR_FLAGS 10 @@ -248,13 +429,15 @@ static inline void omap_mux_decode(struct seq_file *s, u16 val) } while (i-- > 0); } -#define OMAP_MUX_DEFNAME_LEN 16 +#define OMAP_MUX_DEFNAME_LEN 32 static int omap_mux_dbg_board_show(struct seq_file *s, void *unused) { + struct omap_mux_partition *partition = s->private; struct omap_mux_entry *e; + u8 omap_gen = omap_rev() >> 28; - list_for_each_entry(e, &muxmodes, node) { + list_for_each_entry(e, &partition->muxmodes, node) { struct omap_mux *m = &e->mux; char m0_def[OMAP_MUX_DEFNAME_LEN]; char *m0_name = m->muxnames[0]; @@ -272,11 +455,16 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused) } m0_def[i] = toupper(m0_name[i]); } - val = omap_mux_read(m->reg_offset); + val = omap_mux_read(partition, m->reg_offset); mode = val & OMAP_MUX_MODE7; - - seq_printf(s, "OMAP%i_MUX(%s, ", - cpu_is_omap34xx() ? 3 : 0, m0_def); + if (mode != 0) + seq_printf(s, "/* %s */\n", m->muxnames[mode]); + + /* + * XXX: Might be revisited to support differences accross + * same OMAP generation. + */ + seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def); omap_mux_decode(s, val); seq_printf(s, "),\n"); } @@ -286,7 +474,7 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused) static int omap_mux_dbg_board_open(struct inode *inode, struct file *file) { - return single_open(file, omap_mux_dbg_board_show, &inode->i_private); + return single_open(file, omap_mux_dbg_board_show, inode->i_private); } static const struct file_operations omap_mux_dbg_board_fops = { @@ -296,19 +484,43 @@ static const struct file_operations omap_mux_dbg_board_fops = { .release = single_release, }; +static struct omap_mux_partition *omap_mux_get_partition(struct omap_mux *mux) +{ + struct omap_mux_partition *partition; + + list_for_each_entry(partition, &mux_partitions, node) { + struct list_head *muxmodes = &partition->muxmodes; + struct omap_mux_entry *e; + + list_for_each_entry(e, muxmodes, node) { + struct omap_mux *m = &e->mux; + + if (m == mux) + return partition; + } + } + + return NULL; +} + static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused) { struct omap_mux *m = s->private; + struct omap_mux_partition *partition; const char *none = "NA"; u16 val; int mode; - val = omap_mux_read(m->reg_offset); + partition = omap_mux_get_partition(m); + if (!partition) + return 0; + + val = omap_mux_read(partition, m->reg_offset); mode = val & OMAP_MUX_MODE7; - seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n", + seq_printf(s, "name: %s.%s (0x%08x/0x%03x = 0x%04x), b %s, t %s\n", m->muxnames[0], m->muxnames[mode], - mux_phys + m->reg_offset, m->reg_offset, val, + partition->phys + m->reg_offset, m->reg_offset, val, m->balls[0] ? m->balls[0] : none, m->balls[1] ? m->balls[1] : none); seq_printf(s, "mode: "); @@ -330,14 +542,15 @@ static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused) #define OMAP_MUX_MAX_ARG_CHAR 7 static ssize_t omap_mux_dbg_signal_write(struct file *file, - const char __user *user_buf, - size_t count, loff_t *ppos) + const char __user *user_buf, + size_t count, loff_t *ppos) { char buf[OMAP_MUX_MAX_ARG_CHAR]; struct seq_file *seqf; struct omap_mux *m; unsigned long val; int buf_size, ret; + struct omap_mux_partition *partition; if (count > OMAP_MUX_MAX_ARG_CHAR) return -EINVAL; @@ -358,7 +571,11 @@ static ssize_t omap_mux_dbg_signal_write(struct file *file, seqf = file->private_data; m = seqf->private; - omap_mux_write((u16)val, m->reg_offset); + partition = omap_mux_get_partition(m); + if (!partition) + return -ENODEV; + + omap_mux_write(partition, (u16)val, m->reg_offset); *ppos += count; return count; @@ -379,22 +596,38 @@ static const struct file_operations omap_mux_dbg_signal_fops = { static struct dentry *mux_dbg_dir; -static void __init omap_mux_dbg_init(void) +static void __init omap_mux_dbg_create_entry( + struct omap_mux_partition *partition, + struct dentry *mux_dbg_dir) { struct omap_mux_entry *e; + list_for_each_entry(e, &partition->muxmodes, node) { + struct omap_mux *m = &e->mux; + + (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir, + m, &omap_mux_dbg_signal_fops); + } +} + +static void __init omap_mux_dbg_init(void) +{ + struct omap_mux_partition *partition; + static struct dentry *mux_dbg_board_dir; + mux_dbg_dir = debugfs_create_dir("omap_mux", NULL); if (!mux_dbg_dir) return; - (void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir, - NULL, &omap_mux_dbg_board_fops); - - list_for_each_entry(e, &muxmodes, node) { - struct omap_mux *m = &e->mux; + mux_dbg_board_dir = debugfs_create_dir("board", mux_dbg_dir); + if (!mux_dbg_board_dir) + return; - (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir, - m, &omap_mux_dbg_signal_fops); + list_for_each_entry(partition, &mux_partitions, node) { + omap_mux_dbg_create_entry(partition, mux_dbg_dir); + (void)debugfs_create_file(partition->name, S_IRUGO, + mux_dbg_board_dir, partition, + &omap_mux_dbg_board_fops); } } @@ -421,23 +654,25 @@ static void __init omap_mux_free_names(struct omap_mux *m) /* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */ static int __init omap_mux_late_init(void) { - struct omap_mux_entry *e, *tmp; + struct omap_mux_partition *partition; - list_for_each_entry_safe(e, tmp, &muxmodes, node) { - struct omap_mux *m = &e->mux; - u16 mode = omap_mux_read(m->reg_offset); + list_for_each_entry(partition, &mux_partitions, node) { + struct omap_mux_entry *e, *tmp; + list_for_each_entry_safe(e, tmp, &partition->muxmodes, node) { + struct omap_mux *m = &e->mux; + u16 mode = omap_mux_read(partition, m->reg_offset); - if (OMAP_MODE_GPIO(mode)) - continue; + if (OMAP_MODE_GPIO(mode)) + continue; #ifndef CONFIG_DEBUG_FS - mutex_lock(&muxmode_mutex); - list_del(&e->node); - mutex_unlock(&muxmode_mutex); - omap_mux_free_names(m); - kfree(m); + mutex_lock(&muxmode_mutex); + list_del(&e->node); + mutex_unlock(&muxmode_mutex); + omap_mux_free_names(m); + kfree(m); #endif - + } } omap_mux_dbg_init(); @@ -462,8 +697,8 @@ static void __init omap_mux_package_fixup(struct omap_mux *p, s++; } if (!found) - printk(KERN_ERR "mux: Unknown entry offset 0x%x\n", - p->reg_offset); + pr_err("%s: Unknown entry offset 0x%x\n", __func__, + p->reg_offset); p++; } } @@ -487,8 +722,8 @@ static void __init omap_mux_package_init_balls(struct omap_ball *b, s++; } if (!found) - printk(KERN_ERR "mux: Unknown ball offset 0x%x\n", - b->reg_offset); + pr_err("%s: Unknown ball offset 0x%x\n", __func__, + b->reg_offset); b++; } } @@ -554,7 +789,7 @@ static void __init omap_mux_set_cmdline_signals(void) } static int __init omap_mux_copy_names(struct omap_mux *src, - struct omap_mux *dst) + struct omap_mux *dst) { int i; @@ -592,51 +827,63 @@ free: #endif /* CONFIG_OMAP_MUX */ -static u16 omap_mux_get_by_gpio(int gpio) +static struct omap_mux *omap_mux_get_by_gpio( + struct omap_mux_partition *partition, + int gpio) { struct omap_mux_entry *e; - u16 offset = OMAP_MUX_TERMINATOR; + struct omap_mux *ret = NULL; - list_for_each_entry(e, &muxmodes, node) { + list_for_each_entry(e, &partition->muxmodes, node) { struct omap_mux *m = &e->mux; if (m->gpio == gpio) { - offset = m->reg_offset; + ret = m; break; } } - return offset; + return ret; } /* Needed for dynamic muxing of GPIO pins for off-idle */ u16 omap_mux_get_gpio(int gpio) { - u16 offset; + struct omap_mux_partition *partition; + struct omap_mux *m; - offset = omap_mux_get_by_gpio(gpio); - if (offset == OMAP_MUX_TERMINATOR) { - printk(KERN_ERR "mux: Could not get gpio%i\n", gpio); - return offset; + list_for_each_entry(partition, &mux_partitions, node) { + m = omap_mux_get_by_gpio(partition, gpio); + if (m) + return omap_mux_read(partition, m->reg_offset); } - return omap_mux_read(offset); + if (!m || m->reg_offset == OMAP_MUX_TERMINATOR) + pr_err("%s: Could not get gpio%i\n", __func__, gpio); + + return OMAP_MUX_TERMINATOR; } /* Needed for dynamic muxing of GPIO pins for off-idle */ void omap_mux_set_gpio(u16 val, int gpio) { - u16 offset; + struct omap_mux_partition *partition; + struct omap_mux *m = NULL; - offset = omap_mux_get_by_gpio(gpio); - if (offset == OMAP_MUX_TERMINATOR) { - printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); - return; + list_for_each_entry(partition, &mux_partitions, node) { + m = omap_mux_get_by_gpio(partition, gpio); + if (m) { + omap_mux_write(partition, val, m->reg_offset); + return; + } } - omap_mux_write(val, offset); + if (!m || m->reg_offset == OMAP_MUX_TERMINATOR) + pr_err("%s: Could not set gpio%i\n", __func__, gpio); } -static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src) +static struct omap_mux * __init omap_mux_list_add( + struct omap_mux_partition *partition, + struct omap_mux *src) { struct omap_mux_entry *entry; struct omap_mux *m; @@ -656,7 +903,7 @@ static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src) #endif mutex_lock(&muxmode_mutex); - list_add_tail(&entry->node, &muxmodes); + list_add_tail(&entry->node, &partition->muxmodes); mutex_unlock(&muxmode_mutex); return m; @@ -667,7 +914,8 @@ static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src) * the GPIO to mux offset mapping that is needed for dynamic muxing * of GPIO pins for off-idle. */ -static void __init omap_mux_init_list(struct omap_mux *superset) +static void __init omap_mux_init_list(struct omap_mux_partition *partition, + struct omap_mux *superset) { while (superset->reg_offset != OMAP_MUX_TERMINATOR) { struct omap_mux *entry; @@ -679,15 +927,16 @@ static void __init omap_mux_init_list(struct omap_mux *superset) } #else /* Skip pins that are not muxed as GPIO by bootloader */ - if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) { + if (!OMAP_MODE_GPIO(omap_mux_read(partition, + superset->reg_offset))) { superset++; continue; } #endif - entry = omap_mux_list_add(superset); + entry = omap_mux_list_add(partition, superset); if (!entry) { - printk(KERN_ERR "mux: Could not add entry\n"); + pr_err("%s: Could not add entry\n", __func__); return; } superset++; @@ -706,10 +955,11 @@ static void omap_mux_init_package(struct omap_mux *superset, omap_mux_package_init_balls(package_balls, superset); } -static void omap_mux_init_signals(struct omap_board_mux *board_mux) +static void omap_mux_init_signals(struct omap_mux_partition *partition, + struct omap_board_mux *board_mux) { omap_mux_set_cmdline_signals(); - omap_mux_write_array(board_mux); + omap_mux_write_array(partition, board_mux); } #else @@ -720,34 +970,49 @@ static void omap_mux_init_package(struct omap_mux *superset, { } -static void omap_mux_init_signals(struct omap_board_mux *board_mux) +static void omap_mux_init_signals(struct omap_mux_partition *partition, + struct omap_board_mux *board_mux) { } #endif -int __init omap_mux_init(u32 mux_pbase, u32 mux_size, - struct omap_mux *superset, - struct omap_mux *package_subset, - struct omap_board_mux *board_mux, - struct omap_ball *package_balls) -{ - if (mux_base) - return -EBUSY; +static u32 mux_partitions_cnt; - mux_phys = mux_pbase; - mux_base = ioremap(mux_pbase, mux_size); - if (!mux_base) { - printk(KERN_ERR "mux: Could not ioremap\n"); +int __init omap_mux_init(const char *name, u32 flags, + u32 mux_pbase, u32 mux_size, + struct omap_mux *superset, + struct omap_mux *package_subset, + struct omap_board_mux *board_mux, + struct omap_ball *package_balls) +{ + struct omap_mux_partition *partition; + + partition = kzalloc(sizeof(struct omap_mux_partition), GFP_KERNEL); + if (!partition) + return -ENOMEM; + + partition->name = name; + partition->flags = flags; + partition->size = mux_size; + partition->phys = mux_pbase; + partition->base = ioremap(mux_pbase, mux_size); + if (!partition->base) { + pr_err("%s: Could not ioremap mux partition at 0x%08x\n", + __func__, partition->phys); return -ENODEV; } - if (cpu_is_omap24xx()) - omap_mux_flags = MUXABLE_GPIO_MODE3; + INIT_LIST_HEAD(&partition->muxmodes); + + list_add_tail(&partition->node, &mux_partitions); + mux_partitions_cnt++; + pr_info("%s: Add partition: #%d: %s, flags: %x\n", __func__, + mux_partitions_cnt, partition->name, partition->flags); omap_mux_init_package(superset, package_subset, package_balls); - omap_mux_init_list(superset); - omap_mux_init_signals(board_mux); + omap_mux_init_list(partition, superset); + omap_mux_init_signals(partition, board_mux); return 0; } diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index 350c04f27383..a4ab17a737a6 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2009 Nokia - * Copyright (C) 2009 Texas Instruments + * Copyright (C) 2009-2010 Texas Instruments * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -10,6 +10,7 @@ #include "mux2420.h" #include "mux2430.h" #include "mux34xx.h" +#include "mux44xx.h" #define OMAP_MUX_TERMINATOR 0xffff @@ -37,6 +38,9 @@ #define OMAP_OFF_PULL_UP (1 << 13) #define OMAP_WAKEUP_EN (1 << 14) +/* 44xx specific mux bit defines */ +#define OMAP_WAKEUP_EVENT (1 << 15) + /* Active pin states */ #define OMAP_PIN_OUTPUT 0 #define OMAP_PIN_INPUT OMAP_INPUT_EN @@ -56,8 +60,10 @@ #define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4) -/* Flags for omap_mux_init */ +/* Flags for omapX_mux_init */ #define OMAP_PACKAGE_MASK 0xffff +#define OMAP_PACKAGE_CBS 8 /* 547-pin 0.40 0.40 */ +#define OMAP_PACKAGE_CBL 7 /* 547-pin 0.40 0.40 */ #define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */ #define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ #define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */ @@ -66,14 +72,61 @@ #define OMAP_PACKAGE_ZAF 1 /* 2420 447-pin SIP */ -#define OMAP_MUX_NR_MODES 8 /* Available modes */ -#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */ +#define OMAP_MUX_NR_MODES 8 /* Available modes */ +#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */ + +/* + * omap_mux_init flags definition: + * + * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits. + * The default value is 16 bits. + * OMAP_MUX_GPIO_IN_MODE3: The GPIO is selected in mode3. + * The default is mode4. + */ +#define OMAP_MUX_REG_8BIT (1 << 0) +#define OMAP_MUX_GPIO_IN_MODE3 (1 << 1) + +/** + * struct omap_board_data - board specific device data + * @id: instance id + * @flags: additional flags for platform init code + * @pads: array of device specific pads + * @pads_cnt: ARRAY_SIZE() of pads + */ +struct omap_board_data { + int id; + u32 flags; + struct omap_device_pad *pads; + int pads_cnt; +}; + +/** + * struct mux_partition - contain partition related information + * @name: name of the current partition + * @flags: flags specific to this partition + * @phys: physical address + * @size: partition size + * @base: virtual address after ioremap + * @muxmodes: list of nodes that belong to a partition + * @node: list node for the partitions linked list + */ +struct omap_mux_partition { + const char *name; + u32 flags; + u32 phys; + u32 size; + void __iomem *base; + struct list_head muxmodes; + struct list_head node; +}; /** * struct omap_mux - data for omap mux register offset and it's value * @reg_offset: mux register offset from the mux base * @gpio: GPIO number * @muxnames: available signal modes for a ball + * @balls: available balls on the package + * @partition: mux partition */ struct omap_mux { u16 reg_offset; @@ -106,6 +159,34 @@ struct omap_board_mux { u16 value; }; +#define OMAP_DEVICE_PAD_ENABLED BIT(7) /* Not needed for board-*.c */ +#define OMAP_DEVICE_PAD_REMUX BIT(1) /* Dynamically remux a pad, + needs enable, idle and off + values */ +#define OMAP_DEVICE_PAD_WAKEUP BIT(0) /* Pad is wake-up capable */ + +/** + * struct omap_device_pad - device specific pad configuration + * @name: signal name + * @flags: pad specific runtime flags + * @enable: runtime value for a pad + * @idle: idle value for a pad + * @off: off value for a pad, defaults to safe mode + * @partition: mux partition + * @mux: mux register + */ +struct omap_device_pad { + char *name; + u8 flags; + u16 enable; + u16 idle; + u16 off; + struct omap_mux_partition *partition; + struct omap_mux *mux; +}; + +struct omap_hwmod_mux_info; + #if defined(CONFIG_OMAP_MUX) /** @@ -122,6 +203,23 @@ int omap_mux_init_gpio(int gpio, int val); */ int omap_mux_init_signal(const char *muxname, int val); +/** + * omap_hwmod_mux_init - initialize hwmod specific mux data + * @bpads: Board specific device signal names + * @nr_pads: Number of signal names for the device + */ +extern struct omap_hwmod_mux_info * +omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads); + +/** + * omap_hwmod_mux - omap hwmod specific pin muxing + * @hmux: Pads for a hwmod + * @state: Desired _HWMOD_STATE + * + * Called only from omap_hwmod.c, do not use. + */ +void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state); + #else static inline int omap_mux_init_gpio(int gpio, int val) @@ -133,6 +231,18 @@ static inline int omap_mux_init_signal(char *muxname, int val) return 0; } +static inline struct omap_hwmod_mux_info * +omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads) +{ + return NULL; +} + +static inline void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state) +{ +} + +static struct omap_board_mux *board_mux __initdata __maybe_unused; + #endif /** @@ -151,28 +261,39 @@ u16 omap_mux_get_gpio(int gpio); void omap_mux_set_gpio(u16 val, int gpio); /** + * omap_mux_get() - get a mux partition by name + * @name: Name of the mux partition + * + */ +struct omap_mux_partition *omap_mux_get(const char *name); + +/** * omap_mux_read() - read mux register + * @partition: Mux partition * @mux_offset: Offset of the mux register * */ -u16 omap_mux_read(u16 mux_offset); +u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset); /** * omap_mux_write() - write mux register + * @partition: Mux partition * @val: New mux register value * @mux_offset: Offset of the mux register * * This should be only needed for dynamic remuxing of non-gpio signals. */ -void omap_mux_write(u16 val, u16 mux_offset); +void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset); /** * omap_mux_write_array() - write an array of mux registers + * @partition: Mux partition * @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR * * This should be only needed for dynamic remuxing of non-gpio signals. */ -void omap_mux_write_array(struct omap_board_mux *board_mux); +void omap_mux_write_array(struct omap_mux_partition *p, + struct omap_board_mux *board_mux); /** * omap2420_mux_init() - initialize mux system with board specific set @@ -196,10 +317,19 @@ int omap2430_mux_init(struct omap_board_mux *board_mux, int flags); int omap3_mux_init(struct omap_board_mux *board_mux, int flags); /** + * omap4_mux_init() - initialize mux system with board specific set + * @board_mux: Board specific mux table + * @flags: OMAP package type used for the board + */ +int omap4_mux_init(struct omap_board_mux *board_mux, int flags); + +/** * omap_mux_init - private mux init function, do not call */ -int omap_mux_init(u32 mux_pbase, u32 mux_size, - struct omap_mux *superset, - struct omap_mux *package_subset, - struct omap_board_mux *board_mux, - struct omap_ball *package_balls); +int omap_mux_init(const char *name, u32 flags, + u32 mux_pbase, u32 mux_size, + struct omap_mux *superset, + struct omap_mux *package_subset, + struct omap_board_mux *board_mux, + struct omap_ball *package_balls); + diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c index 414af5434456..cf6de0971c6c 100644 --- a/arch/arm/mach-omap2/mux2420.c +++ b/arch/arm/mach-omap2/mux2420.c @@ -678,11 +678,13 @@ int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags) case OMAP_PACKAGE_ZAF: /* REVISIT: Please add data */ default: - pr_warning("mux: No ball data available for omap2420 package\n"); + pr_warning("%s: No ball data available for omap2420 package\n", + __func__); } - return omap_mux_init(OMAP2420_CONTROL_PADCONF_MUX_PBASE, + return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3, + OMAP2420_CONTROL_PADCONF_MUX_PBASE, OMAP2420_CONTROL_PADCONF_MUX_SIZE, - omap2420_muxmodes, NULL, board_subset, - package_balls); + omap2420_muxmodes, NULL, board_subset, + package_balls); } diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c index 84d2c5a7ecd7..4185f92553db 100644 --- a/arch/arm/mach-omap2/mux2430.c +++ b/arch/arm/mach-omap2/mux2430.c @@ -781,11 +781,13 @@ int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags) package_balls = omap2430_pop_ball; break; default: - pr_warning("mux: No ball data available for omap2420 package\n"); + pr_warning("%s: No ball data available for omap2420 package\n", + __func__); } - return omap_mux_init(OMAP2430_CONTROL_PADCONF_MUX_PBASE, + return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3, + OMAP2430_CONTROL_PADCONF_MUX_PBASE, OMAP2430_CONTROL_PADCONF_MUX_SIZE, - omap2430_muxmodes, NULL, board_subset, - package_balls); + omap2430_muxmodes, NULL, board_subset, + package_balls); } diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c index 574e54ea3ab7..440c98e9a510 100644 --- a/arch/arm/mach-omap2/mux34xx.c +++ b/arch/arm/mach-omap2/mux34xx.c @@ -2049,12 +2049,13 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags) package_balls = omap36xx_cbp_ball; break; default: - printk(KERN_ERR "mux: Unknown omap package, mux disabled\n"); + pr_err("%s Unknown omap package, mux disabled\n", __func__); return -EINVAL; } - return omap_mux_init(OMAP3_CONTROL_PADCONF_MUX_PBASE, + return omap_mux_init("core", 0, + OMAP3_CONTROL_PADCONF_MUX_PBASE, OMAP3_CONTROL_PADCONF_MUX_SIZE, - omap3_muxmodes, package_subset, board_subset, - package_balls); + omap3_muxmodes, package_subset, board_subset, + package_balls); } diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c new file mode 100644 index 000000000000..980f11d45c79 --- /dev/null +++ b/arch/arm/mach-omap2/mux44xx.c @@ -0,0 +1,1625 @@ +/* + * OMAP44xx ES1.0 pin mux definition + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * + * - Based on mux34xx.c done by Tony Lindgren <tony@atomide.com> + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/init.h> + +#include "mux.h" + +#ifdef CONFIG_OMAP_MUX + +#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ +{ \ + .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ + .gpio = (g), \ + .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ +} + +#else + +#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ +{ \ + .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ + .gpio = (g), \ +} + +#endif + +#define _OMAP4_BALLENTRY(M0, bb, bt) \ +{ \ + .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ + .balls = { bb, bt }, \ +} + +/* + * Superset of all mux modes for omap4 ES1.0 + */ +static struct omap_mux __initdata omap4_core_muxmodes[] = { + _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4", + "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5", + "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6", + "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7", + "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15", + "gpio_32", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14", + "gpio_33", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13", + "gpio_34", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12", + "gpio_35", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11", + "gpio_36", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10", + "gpio_37", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9", + "gpio_38", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8", + "gpio_39", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0", + "gpio_40", "venc_656_data0", NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1", + "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2", + "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3", + "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4", + "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5", + "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6", + "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7", + "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0", + "gpio_48", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1", + "gpio_49", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50", + "sys_ndmareq0", NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6", + "gpio_51", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7", + "gpio_52", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir", + "c2c_dataout4", "gpio_53", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54", + "sys_ndmareq1", NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55", + "sys_ndmareq2", NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL, + "gpio_56", "sys_ndmareq3", NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL, + "gpio_59", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5", + "gpio_60", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL, + "gpio_61", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2", + "gpio_62", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen", + "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0", + "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1", + "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0", + "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1", + "c2c_dataout1", "gpio_104", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL, + "gpio_65", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL, + "gpio_66", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL, + "gpio_83", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk", + "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk", + NULL, "hw_dbg20", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp", + "hsi1_cadata", "mcbsp4_clkr", "gpio_85", + "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir", + "hsi1_caflag", "mcbsp4_fsr", "gpio_86", + "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt", + "hsi1_acready", "mcbsp4_fsx", "gpio_87", + "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0", + "hsi1_acwake", "mcbsp4_clkx", "gpio_88", + "usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1", + "hsi1_acdata", "mcbsp4_dx", "gpio_89", + "usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2", + "hsi1_acflag", "mcbsp4_dr", "gpio_90", + "usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3", + "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3", + "usbb1_mm_txen", "hw_dbg27", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4", + "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92", + "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5", + "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93", + "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6", + "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94", + "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7", + "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95", + "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL, + "gpio_96", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL, + NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL, + "gpio_98", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL, + "gpio_99", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19", + "gpio_100", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx", + "gpio_101", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18", + "gpio_102", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17", + "gpio_103", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16", + "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15", + "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL, + "gpio_106", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL, + "gpio_107", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL, + "gpio_108", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL, + "gpio_109", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk", + "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm", + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi", + "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo", + "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0", + "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx", + "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr", + "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2", + "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3", + "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data", + "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data", + "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx", + NULL, NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx", + NULL, NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL, + "gpio_119", "usbb2_mm_txse0", NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL, + "gpio_120", "usbb2_mm_txdat", NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock", + NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data", + "abe_dmic_clk2", "gpio_122", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL, + "gpio_123", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL, + "gpio_124", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL, + "gpio_125", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL, + "gpio_126", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb", + "gpio_127", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL, + "gpio_128", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL, + "gpio_129", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL, + "gpio_135", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL, + "gpio_136", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL, + "gpio_138", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts", + "slimbus2_clock", "gpio_139", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts", + "slimbus2_data", "gpio_140", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx", + NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL, + "gpio_142", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx", + "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx", + "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk", + "usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo", + "usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi", + "usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL, + "usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL, + "gpio_149", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL, + "gpio_150", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL, + "gpio_151", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL, + "gpio_152", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL, + "gpio_153", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL, + "gpio_154", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL, + "gpio_155", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL, + "gpio_156", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk", + "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157", + "hsi2_cawake", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp", + "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158", + "hsi2_cadata", "dispc2_data23", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir", + "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159", + "hsi2_caflag", "dispc2_data22", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt", + "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160", + "hsi2_acready", "dispc2_data21", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0", + "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161", + "hsi2_acwake", "dispc2_data20", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1", + "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162", + "hsi2_acdata", "dispc2_data19", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2", + "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163", + "hsi2_acflag", "dispc2_data18", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3", + "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164", + "hsi2_caready", "dispc2_data15", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4", + "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165", + "mcspi3_somi", "dispc2_data14", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5", + "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166", + "mcspi3_cs0", "dispc2_data13", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6", + "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167", + "mcspi3_simo", "dispc2_data12", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7", + "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168", + "mcspi3_clk", "dispc2_data11", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL, + "gpio_169", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL, + NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL, + "gpio_171", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL, + "gpio_172", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL, + "gpio_173", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL, + "gpio_174", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL, + "gpio_0", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL, + "gpio_1", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL, + "gpi_175", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL, + "gpi_176", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL, + "gpi_177", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL, + "gpi_178", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL, + "gpi_2", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL, + "gpi_3", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx", + "uart2_rx", "gpio_179", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx", + "uart2_tx", "gpio_180", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL, + "gpio_181", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL, + "gpio_182", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL, + NULL, "hw_dbg0", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL, + NULL, "hw_dbg1", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL, + "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL, + "gpio_14", NULL, "dispc2_data10", "hw_dbg3", + "reserved"), + _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL, + "gpio_15", NULL, "dispc2_data9", "hw_dbg4", + "reserved"), + _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL, + "gpio_16", "rfbi_te_vsync0", "dispc2_data16", + "hw_dbg5", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0", + "uart3_tx_irtx", "gpio_17", "rfbi_hsync0", + "dispc2_data17", "hw_dbg6", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1", + "uart3_rx_irrx", "gpio_18", "rfbi_cs0", + "dispc2_hsync", "hw_dbg7", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2", + "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk", + "hw_dbg8", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3", + "uart3_cts_rctx", "gpio_20", "rfbi_we", + "dispc2_vsync", "hw_dbg9", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4", + NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10", + "reserved"), + _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5", + NULL, "gpio_22", "rfbi_data8", "dispc2_data8", + "hw_dbg11", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6", + NULL, "gpio_23", "rfbi_data7", "dispc2_data7", + "hw_dbg12", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7", + NULL, "gpio_24", "rfbi_data6", "dispc2_data6", + "hw_dbg13", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure", + "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5", + "hw_dbg14", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator", + NULL, "gpio_26", "rfbi_data4", "dispc2_data4", + "hw_dbg15", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt", + "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3", + "hw_dbg16", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt", + "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2", + "hw_dbg17", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt", + "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1", + "hw_dbg18", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt", + "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0", + "hw_dbg19", "reserved"), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +/* + * Balls for 44XX CBL package + * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), + * 0.40mm Ball Pitch (Bottom) + */ +#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ + && defined(CONFIG_OMAP_PACKAGE_CBL) +struct omap_ball __initdata omap4_core_cbl_ball[] = { + _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL), + _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL), + _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL), + _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL), + _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL), + _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL), + _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL), + _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL), + _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL), + _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL), + _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL), + _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL), + _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL), + _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL), + _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL), + _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL), + _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL), + _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL), + _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL), + _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL), + _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL), + _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL), + _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL), + _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL), + _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL), + _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL), + _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL), + _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL), + _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL), + _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL), + _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL), + _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL), + _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL), + _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL), + _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL), + _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL), + _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL), + _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL), + _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL), + _OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL), + _OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL), + _OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL), + _OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL), + _OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL), + _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL), + _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL), + _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL), + _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL), + _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL), + _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL), + _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL), + _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL), + _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL), + _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL), + _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL), + _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL), + _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL), + _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL), + _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL), + _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL), + _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL), + _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL), + _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL), + _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL), + _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL), + _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL), + _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL), + _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL), + _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL), + _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL), + _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL), + _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL), + _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL), + _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL), + _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL), + _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL), + _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL), + _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL), + _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL), + _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL), + _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL), + _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL), + _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL), + _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL), + _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL), + _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL), + _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL), + _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL), + _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL), + _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL), + _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL), + _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL), + _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL), + _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL), + _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL), + _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL), + _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL), + _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL), + _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL), + _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL), + _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL), + _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL), + _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL), + _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL), + _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL), + _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL), + _OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL), + _OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL), + _OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL), + _OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL), + _OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL), + _OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL), + _OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL), + _OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL), + _OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL), + _OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL), + _OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL), + _OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL), + _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL), + _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL), + _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL), + _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL), + _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL), + _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL), + _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL), + _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL), + _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL), + _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL), + _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL), + _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL), + _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL), + _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL), + _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL), + _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL), + _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL), + _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL), + _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL), + _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL), + _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL), + _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL), + _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL), + _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL), + _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL), + _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL), + _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL), + _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL), + _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL), + _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL), + _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL), + _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL), + _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define omap4_core_cbl_ball NULL +#endif + +/* + * Superset of all mux modes for omap4 ES2.0 + */ +static struct omap_mux __initdata omap4_es2_core_muxmodes[] = { + _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4", + "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5", + "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6", + "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7", + "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15", + "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14", + "gpio_33", NULL, "sdmmc1_dat1", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13", + "gpio_34", NULL, "sdmmc1_dat2", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12", + "gpio_35", NULL, "sdmmc1_dat3", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11", + "gpio_36", NULL, "sdmmc1_dat4", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10", + "gpio_37", NULL, "sdmmc1_dat5", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9", + "gpio_38", NULL, "sdmmc1_dat6", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8", + "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0", + "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1", + "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2", + "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3", + "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4", + "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5", + "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6", + "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7", + "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0", + "gpio_48", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1", + "gpio_49", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50", + "sys_ndmareq0", NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6", + "gpio_51", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8", + "c2c_dataout7", "gpio_52", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir", + "c2c_dataout4", "gpio_53", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54", + "sys_ndmareq1", NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55", + "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL, + "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL, + "gpio_59", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5", + "gpio_60", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL, + "gpio_61", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2", + "gpio_62", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen", + "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS4, 101, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0", + "gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS5, 102, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1", + "gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS6, 103, "gpmc_ncs6", "dsi2_te0", + "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1", + "c2c_dataout1", "gpio_104", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL, + "gpio_65", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL, + "gpio_66", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL, + "gpio_83", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk", + "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk", + NULL, "hw_dbg20", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp", + "hsi1_cadata", "mcbsp4_clkr", "gpio_85", + "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir", + "hsi1_caflag", "mcbsp4_fsr", "gpio_86", + "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt", + "hsi1_acready", "mcbsp4_fsx", "gpio_87", + "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0", + "hsi1_acwake", "mcbsp4_clkx", "gpio_88", + "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1", + "hsi1_acdata", "mcbsp4_dx", "gpio_89", + "usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2", + "hsi1_acflag", "mcbsp4_dr", "gpio_90", + "usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3", + "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3", + "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4", + "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92", + "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5", + "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93", + "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6", + "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94", + "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7", + "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95", + "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL, + "gpio_96", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL, + NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL, + "gpio_98", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL, + "gpio_99", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19", + "gpio_100", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx", + "gpio_101", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18", + "gpio_102", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17", + "gpio_103", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16", + "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15", + "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL, + "gpio_106", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL, + "gpio_107", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL, + "gpio_108", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL, + "gpio_109", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk", + "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm", + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi", + "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo", + "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0", + "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx", + "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr", + "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2", + "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3", + "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data", + "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data", + "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx", + NULL, NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx", + NULL, NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL, + "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL, + "gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock", + "abe_mcasp_axr", "gpio_121", NULL, + "dmtimer11_pwm_evt", NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data", + "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt", + NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL, + "gpio_123", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL, + "gpio_124", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL, + "gpio_125", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL, + "gpio_126", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb", + "gpio_127", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL, + "gpio_128", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL, + "gpio_129", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL, + "gpio_135", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL, + "gpio_136", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL, + "gpio_138", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts", + "slimbus2_clock", "gpio_139", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts", + "slimbus2_data", "gpio_140", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx", + NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL, + "gpio_142", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx", + "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx", + "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk", + "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk", + NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo", + "usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd", + NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi", + "usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0", + NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL, + "usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1", + NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL, + "gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL, + "gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", + "kpd_col6", "gpio_151", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", + "kpd_col7", "gpio_152", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", + "kpd_row6", "gpio_153", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", + "kpd_row7", "gpio_154", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", "kpd_row8", + "gpio_155", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8", + "gpio_156", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk", + "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157", + "hsi2_cawake", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp", + "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158", + "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir", + "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159", + "hsi2_caflag", "dispc2_data22", NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt", + "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160", + "hsi2_acready", "dispc2_data21", NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0", + "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161", + "hsi2_acwake", "dispc2_data20", "usbb2_mm_txen", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1", + "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162", + "hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2", + "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163", + "hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3", + "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164", + "hsi2_caready", "dispc2_data15", "rfbi_data15", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4", + "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165", + "mcspi3_somi", "dispc2_data14", "rfbi_data14", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5", + "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166", + "mcspi3_cs0", "dispc2_data13", "rfbi_data13", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6", + "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167", + "mcspi3_simo", "dispc2_data12", "rfbi_data12", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7", + "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168", + "mcspi3_clk", "dispc2_data11", "rfbi_data11", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL, + "gpio_169", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL, + NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL, + "gpio_171", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL, + "gpio_172", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_COL5, 173, "kpd_col5", "kpd_col2", NULL, + "gpio_173", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_COL0, 174, "kpd_col0", "kpd_col3", NULL, + "gpio_174", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_COL1, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_COL2, 1, "kpd_col2", "kpd_col5", NULL, "gpio_1", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_ROW3, 175, "kpd_row3", "kpd_row0", NULL, + "gpio_175", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_ROW4, 176, "kpd_row4", "kpd_row1", NULL, + "gpio_176", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_ROW5, 177, "kpd_row5", "kpd_row2", NULL, + "gpio_177", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_ROW0, 178, "kpd_row0", "kpd_row3", NULL, + "gpio_178", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_ROW1, 2, "kpd_row1", "kpd_row4", NULL, "gpio_2", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx", + "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx", + "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL, + "gpio_181", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL, + "gpio_182", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL, + NULL, "hw_dbg0", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL, + NULL, "hw_dbg1", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL, + "gpio_13", NULL, "dispc2_fid", "hw_dbg2", + "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL, + "gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3", + "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL, + "gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4", + "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL, + "gpio_16", "rfbi_te_vsync0", "dispc2_data16", + "hw_dbg5", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0", + "uart3_tx_irtx", "gpio_17", "rfbi_hsync0", + "dispc2_data17", "hw_dbg6", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1", + "uart3_rx_irrx", "gpio_18", "rfbi_cs0", + "dispc2_hsync", "hw_dbg7", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2", + "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk", + "hw_dbg8", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3", + "uart3_cts_rctx", "gpio_20", "rfbi_we", + "dispc2_vsync", "hw_dbg9", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4", + NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10", + "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5", + NULL, "gpio_22", "rfbi_data8", "dispc2_data8", + "hw_dbg11", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6", + NULL, "gpio_23", "rfbi_data7", "dispc2_data7", + "hw_dbg12", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7", + NULL, "gpio_24", "rfbi_data6", "dispc2_data6", + "hw_dbg13", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure", + "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5", + "hw_dbg14", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator", + NULL, "gpio_26", "rfbi_data4", "dispc2_data4", + "hw_dbg15", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt", + "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3", + "hw_dbg16", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt", + "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2", + "hw_dbg17", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt", + "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1", + "hw_dbg18", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt", + "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0", + "hw_dbg19", "safe_mode"), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +/* + * Balls for 44XX CBS package + * 547-pin CBL ES2.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), + * 0.40mm Ball Pitch (Bottom) + */ +#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ + && defined(CONFIG_OMAP_PACKAGE_CBS) +struct omap_ball __initdata omap4_core_cbs_ball[] = { + _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL), + _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL), + _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL), + _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL), + _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL), + _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL), + _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL), + _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL), + _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL), + _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL), + _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL), + _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL), + _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL), + _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL), + _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL), + _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL), + _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL), + _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL), + _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL), + _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL), + _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL), + _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL), + _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL), + _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL), + _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL), + _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL), + _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL), + _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL), + _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL), + _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL), + _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL), + _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL), + _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL), + _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL), + _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL), + _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL), + _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL), + _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL), + _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL), + _OMAP4_BALLENTRY(GPMC_WAIT2, "d23", NULL), + _OMAP4_BALLENTRY(GPMC_NCS4, "a24", NULL), + _OMAP4_BALLENTRY(GPMC_NCS5, "b24", NULL), + _OMAP4_BALLENTRY(GPMC_NCS6, "c24", NULL), + _OMAP4_BALLENTRY(GPMC_NCS7, "d24", NULL), + _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL), + _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL), + _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL), + _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL), + _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL), + _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL), + _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL), + _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL), + _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL), + _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL), + _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL), + _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL), + _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL), + _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL), + _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL), + _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL), + _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL), + _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL), + _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL), + _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL), + _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL), + _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL), + _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL), + _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL), + _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL), + _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL), + _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL), + _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL), + _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL), + _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL), + _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL), + _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL), + _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL), + _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL), + _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL), + _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL), + _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL), + _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL), + _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL), + _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL), + _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL), + _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL), + _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL), + _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL), + _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL), + _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL), + _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL), + _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL), + _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL), + _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL), + _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL), + _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL), + _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL), + _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL), + _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL), + _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL), + _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL), + _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL), + _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL), + _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL), + _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL), + _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL), + _OMAP4_BALLENTRY(KPD_COL3, "g26", NULL), + _OMAP4_BALLENTRY(KPD_COL4, "g25", NULL), + _OMAP4_BALLENTRY(KPD_COL5, "h26", NULL), + _OMAP4_BALLENTRY(KPD_COL0, "h25", NULL), + _OMAP4_BALLENTRY(KPD_COL1, "j27", NULL), + _OMAP4_BALLENTRY(KPD_COL2, "h27", NULL), + _OMAP4_BALLENTRY(KPD_ROW3, "j26", NULL), + _OMAP4_BALLENTRY(KPD_ROW4, "j25", NULL), + _OMAP4_BALLENTRY(KPD_ROW5, "k26", NULL), + _OMAP4_BALLENTRY(KPD_ROW0, "k25", NULL), + _OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL), + _OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL), + _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL), + _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL), + _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL), + _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL), + _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL), + _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL), + _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL), + _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL), + _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL), + _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL), + _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL), + _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL), + _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL), + _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL), + _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL), + _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL), + _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL), + _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL), + _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL), + _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL), + _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL), + _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL), + _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL), + _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL), + _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL), + _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL), + _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL), + _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL), + _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL), + _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL), + _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL), + _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL), + _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define omap4_core_cbs_ball NULL +#endif + +/* + * Superset of all mux modes for omap4 + */ +static struct omap_mux __initdata omap4_wkup_muxmodes[] = { + _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL, + "c2c_wakereqin", NULL, NULL, NULL), + _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL, + "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req", + "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req", + "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req", + "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout", + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out", + NULL, "gpio_wk7", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL, + "gpio_wk8", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL, + NULL, NULL, NULL), + _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL, + NULL, "gpio_wk29", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL, + "gpio_wk9", "c2c_wakereqout", NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL, + "gpio_wk10", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL, + NULL, NULL, NULL), + _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL, + NULL, NULL, NULL), + _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL, + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +/* + * Balls for 44XX CBL & CBS package - wakeup partition + * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), + * 0.40mm Ball Pitch (Bottom) + */ +#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ + && defined(CONFIG_OMAP_PACKAGE_CBL) +struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = { + _OMAP4_BALLENTRY(SIM_IO, "h4", NULL), + _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL), + _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL), + _OMAP4_BALLENTRY(SIM_CD, "j1", NULL), + _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL), + _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL), + _OMAP4_BALLENTRY(SR_SDA, "af9", NULL), + _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL), + _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL), + _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL), + _OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL), + _OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL), + _OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL), + _OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL), + _OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL), + _OMAP4_BALLENTRY(SYS_32K, "ag7", NULL), + _OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL), + _OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL), + _OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL), + _OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL), + _OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL), + _OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL), + _OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL), + _OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL), + _OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL), + _OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL), + _OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL), + _OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define omap4_wkup_cbl_cbs_ball NULL +#endif + +int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags) +{ + struct omap_ball *package_balls_core; + struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball; + struct omap_mux *core_muxmodes; + int ret; + + switch (flags & OMAP_PACKAGE_MASK) { + case OMAP_PACKAGE_CBL: + pr_debug("%s: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n", __func__); + package_balls_core = omap4_core_cbl_ball; + core_muxmodes = omap4_core_muxmodes; + break; + case OMAP_PACKAGE_CBS: + pr_debug("%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__); + package_balls_core = omap4_core_cbs_ball; + core_muxmodes = omap4_es2_core_muxmodes; + break; + default: + pr_err("%s: Unknown omap package, mux disabled\n", __func__); + return -EINVAL; + } + + ret = omap_mux_init("core", + OMAP_MUX_GPIO_IN_MODE3, + OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE, + OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE, + core_muxmodes, NULL, board_subset, + package_balls_core); + if (ret) + return ret; + + ret = omap_mux_init("wkup", + OMAP_MUX_GPIO_IN_MODE3, + OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE, + OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE, + omap4_wkup_muxmodes, NULL, board_subset, + package_balls_wkup); + + return ret; +} + diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h new file mode 100644 index 000000000000..c635026cd7e9 --- /dev/null +++ b/arch/arm/mach-omap2/mux44xx.h @@ -0,0 +1,298 @@ +/* + * OMAP44xx MUX registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H +#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H + +#define OMAP4_MUX(M0, mux_value) \ +{ \ + .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ + .value = (mux_value), \ +} + +/* ctrl_module_pad_core base address */ +#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE 0x4a100000 + +/* ctrl_module_pad_core registers offset */ +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET 0x0040 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET 0x0042 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET 0x0044 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET 0x0046 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET 0x0048 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET 0x004a +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET 0x004c +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET 0x004e +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET 0x0050 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET 0x0052 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET 0x0054 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET 0x0056 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET 0x0058 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET 0x005a +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET 0x005c +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET 0x005e +#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET 0x0060 +#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET 0x0062 +#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET 0x0064 +#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET 0x0066 +#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET 0x0068 +#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET 0x006a +#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET 0x006c +#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET 0x006e +#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET 0x0070 +#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET 0x0072 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET 0x0074 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET 0x0076 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET 0x0078 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET 0x007a +#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET 0x007c +#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET 0x007e +#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET 0x0080 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET 0x0082 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET 0x0084 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET 0x0086 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET 0x0088 +#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET 0x008a +#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET 0x008c +#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET 0x008e +#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET 0x0090 +#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET 0x0092 +#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET 0x0094 +#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET 0x0096 +#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET 0x0098 +#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET 0x009a +#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET 0x009c +#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET 0x009e +#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET 0x00a0 +#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET 0x00a2 +#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET 0x00a4 +#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET 0x00a6 +#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET 0x00a8 +#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET 0x00aa +#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET 0x00ac +#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET 0x00ae +#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET 0x00b0 +#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET 0x00b2 +#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET 0x00b4 +#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET 0x00b6 +#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET 0x00b8 +#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET 0x00ba +#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET 0x00bc +#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET 0x00be +#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET 0x00c0 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET 0x00c2 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET 0x00c4 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET 0x00c6 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET 0x00c8 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET 0x00ca +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET 0x00cc +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET 0x00ce +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET 0x00d0 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET 0x00d2 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET 0x00d4 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET 0x00d6 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET 0x00d8 +#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET 0x00da +#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET 0x00dc +#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET 0x00de +#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET 0x00e0 +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET 0x00e2 +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET 0x00e4 +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET 0x00e6 +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET 0x00e8 +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET 0x00ea +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET 0x00ec +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET 0x00ee +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET 0x00f0 +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET 0x00f2 +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET 0x00f4 +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET 0x00f6 +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET 0x00f8 +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET 0x00fa +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET 0x00fc +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET 0x00fe +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET 0x0100 +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET 0x0102 +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET 0x0104 +#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET 0x0106 +#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET 0x0108 +#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET 0x010a +#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET 0x010c +#define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET 0x010e +#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET 0x0110 +#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET 0x0112 +#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET 0x0114 +#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET 0x0116 +#define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET 0x0118 +#define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET 0x011a +#define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET 0x011c +#define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET 0x011e +#define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET 0x0120 +#define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET 0x0122 +#define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET 0x0124 +#define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET 0x0126 +#define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET 0x0128 +#define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET 0x012a +#define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET 0x012c +#define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET 0x012e +#define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET 0x0130 +#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET 0x0132 +#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET 0x0134 +#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET 0x0136 +#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET 0x0138 +#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET 0x013a +#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET 0x013c +#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET 0x013e +#define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET 0x0140 +#define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET 0x0142 +#define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET 0x0144 +#define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET 0x0146 +#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET 0x0148 +#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET 0x014a +#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET 0x014c +#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET 0x014e +#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET 0x0150 +#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET 0x0152 +#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET 0x0154 +#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET 0x0156 +#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET 0x0158 +#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET 0x015a +#define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET 0x015c +#define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET 0x015e +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET 0x0160 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET 0x0162 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET 0x0164 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET 0x0166 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET 0x0168 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET 0x016a +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET 0x016c +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET 0x016e +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET 0x0170 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET 0x0172 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET 0x0174 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET 0x0176 +#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET 0x0178 +#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET 0x017a +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET 0x017c +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET 0x017e +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET 0x0180 +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET 0x0182 +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET 0x0184 +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET 0x0186 +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET 0x0188 +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET 0x018a +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET 0x018c +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET 0x018e +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET 0x0190 +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET 0x0192 +#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET 0x0194 +#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET 0x0196 +#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET 0x0198 +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET 0x019a +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET 0x019c +#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET 0x019e +#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET 0x01a0 +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET 0x01a2 +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET 0x01a4 +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET 0x01a6 +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET 0x01a8 +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET 0x01aa +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET 0x01ac +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET 0x01ae +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET 0x01b0 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET 0x01b2 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET 0x01b4 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET 0x01b6 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET 0x01b8 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET 0x01ba +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET 0x01bc +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET 0x01be +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET 0x01c0 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET 0x01c2 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET 0x01c4 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET 0x01c6 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET 0x01c8 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET 0x01ca +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET 0x01cc +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET 0x01ce +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET 0x01d0 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET 0x01d2 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET 0x01d4 + +/* ES2.0 only */ +#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET 0x008e +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET 0x0090 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET 0x0092 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET 0x0094 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET 0x0096 + +#define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET 0x017c +#define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET 0x017e +#define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET 0x0180 +#define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET 0x0182 +#define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET 0x0184 +#define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET 0x0186 +#define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET 0x0188 +#define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET 0x018a +#define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET 0x018c +#define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET 0x018e +#define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET 0x0190 +#define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET 0x0192 + + +#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE \ + (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET \ + - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2) + +/* ctrl_module_pad_wkup base address */ +#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE 0x4a31e000 + +/* ctrl_module_pad_wkup registers offset */ +#define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET 0x0040 +#define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET 0x0042 +#define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET 0x0044 +#define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET 0x0046 +#define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET 0x0048 +#define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET 0x004a +#define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET 0x004c +#define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET 0x004e +#define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET 0x0050 +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET 0x0052 +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET 0x0054 +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET 0x0056 +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET 0x0058 +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET 0x005a +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET 0x005c +#define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET 0x005e +#define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET 0x0060 +#define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET 0x0062 +#define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET 0x0064 +#define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET 0x0066 +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET 0x0068 +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET 0x006a +#define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET 0x006c +#define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET 0x006e +#define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET 0x0070 +#define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET 0x0072 +#define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET 0x0074 +#define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET 0x0076 + +#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE \ + (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET \ + - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2) + +#endif diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index f5a1aad1a5c0..3fc5dc7233da 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -33,9 +33,11 @@ static struct iommu_device omap3_devices[] = { .name = "isp", .nr_tlb_entries = 8, .clk_name = "cam_ick", + .da_start = 0x0, + .da_end = 0xFFFFF000, }, }, -#if defined(CONFIG_MPU_BRIDGE_IOMMU) +#if defined(CONFIG_OMAP_IOMMU_IVA2) { .base = 0x5d000000, .irq = 28, @@ -43,6 +45,8 @@ static struct iommu_device omap3_devices[] = { .name = "iva2", .nr_tlb_entries = 32, .clk_name = "iva2_ck", + .da_start = 0x11000000, + .da_end = 0xFFFFF000, }, }, #endif @@ -64,6 +68,8 @@ static struct iommu_device omap4_devices[] = { .name = "ducati", .nr_tlb_entries = 32, .clk_name = "ducati_ick", + .da_start = 0x0, + .da_end = 0xFFFFF000, }, }, #if defined(CONFIG_MPU_TESLA_IOMMU) @@ -74,6 +80,8 @@ static struct iommu_device omap4_devices[] = { .name = "tesla", .nr_tlb_entries = 32, .clk_name = "tesla_ick", + .da_start = 0x0, + .da_end = 0xFFFFF000, }, }, #endif diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 666e852988d5..19268647ce36 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -54,6 +54,8 @@ static void omap4_l2x0_disable(void) static int __init omap_l2_cache_init(void) { + u32 aux_ctrl = 0; + /* * To avoid code running on other OMAPs in * multi-omap builds @@ -65,18 +67,32 @@ static int __init omap_l2_cache_init(void) l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); BUG_ON(!l2cache_base); - /* Enable PL310 L2 Cache controller */ - omap_smc1(0x102, 0x1); - /* * 16-way associativity, parity disabled * Way size - 32KB (es1.0) * Way size - 64KB (es2.0 +) */ - if (omap_rev() == OMAP4430_REV_ES1_0) - l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); - else - l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff); + aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | + (0x1 << 25) | + (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) | + (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT)); + + if (omap_rev() == OMAP4430_REV_ES1_0) { + aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT; + } else { + aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | + (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | + (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | + (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | + (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)); + } + if (omap_rev() != OMAP4430_REV_ES1_0) + omap_smc1(0x109, aux_ctrl); + + /* Enable PL310 L2 Cache controller */ + omap_smc1(0x102, 0x1); + + l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); /* * Override default outer_cache.disable with a OMAP4 diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 5a30658444d0..e282e35769fd 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -116,7 +116,6 @@ * - Open Core Protocol Specification 2.2 * * To do: - * - pin mux handling * - handle IO mapping * - bus throughput & module latency measurement code * @@ -135,17 +134,21 @@ #include <linux/err.h> #include <linux/list.h> #include <linux/mutex.h> +#include <linux/spinlock.h> #include <plat/common.h> #include <plat/cpu.h> -#include <plat/clockdomain.h> -#include <plat/powerdomain.h> +#include "clockdomain.h" +#include "powerdomain.h" #include <plat/clock.h> #include <plat/omap_hwmod.h> #include <plat/prcm.h> -#include "cm.h" -#include "prm.h" +#include "cm2xxx_3xxx.h" +#include "cm44xx.h" +#include "prm2xxx_3xxx.h" +#include "prm44xx.h" +#include "mux.h" /* Maximum microseconds to wait for OMAP module to softreset */ #define MAX_MODULE_SOFTRESET_WAIT 10000 @@ -156,8 +159,6 @@ /* omap_hwmod_list contains all registered struct omap_hwmods */ static LIST_HEAD(omap_hwmod_list); -static DEFINE_MUTEX(omap_hwmod_mutex); - /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ static struct omap_hwmod *mpu_oh; @@ -209,10 +210,9 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh) /* XXX ensure module interface clock is up */ - if (oh->_sysc_cache != v) { - oh->_sysc_cache = v; - omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); - } + /* Module might have lost context, always update cache and register */ + oh->_sysc_cache = v; + omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); } /** @@ -388,12 +388,13 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, * Allow the hardware module @oh to send wakeups. Returns -EINVAL * upon error or 0 upon success. */ -static int _enable_wakeup(struct omap_hwmod *oh) +static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) { - u32 v, wakeup_mask; + u32 wakeup_mask; if (!oh->class->sysc || - !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) + !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || + (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP))) return -EINVAL; if (!oh->class->sysc->sysc_fields) { @@ -403,9 +404,10 @@ static int _enable_wakeup(struct omap_hwmod *oh) wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); - v = oh->_sysc_cache; - v |= wakeup_mask; - _write_sysconfig(v, oh); + *v |= wakeup_mask; + + if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) + _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); /* XXX test pwrdm_get_wken for this hwmod's subsystem */ @@ -421,12 +423,13 @@ static int _enable_wakeup(struct omap_hwmod *oh) * Prevent the hardware module @oh to send wakeups. Returns -EINVAL * upon error or 0 upon success. */ -static int _disable_wakeup(struct omap_hwmod *oh) +static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) { - u32 v, wakeup_mask; + u32 wakeup_mask; if (!oh->class->sysc || - !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) + !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || + (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP))) return -EINVAL; if (!oh->class->sysc->sysc_fields) { @@ -436,9 +439,10 @@ static int _disable_wakeup(struct omap_hwmod *oh) wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); - v = oh->_sysc_cache; - v &= ~wakeup_mask; - _write_sysconfig(v, oh); + *v &= ~wakeup_mask; + + if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) + _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); /* XXX test pwrdm_get_wken for this hwmod's subsystem */ @@ -675,7 +679,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh) * Returns the array index of the OCP slave port that the MPU * addresses the device on, or -EINVAL upon error or not found. */ -static int _find_mpu_port_index(struct omap_hwmod *oh) +static int __init _find_mpu_port_index(struct omap_hwmod *oh) { int i; int found = 0; @@ -709,7 +713,7 @@ static int _find_mpu_port_index(struct omap_hwmod *oh) * Return the virtual address of the base of the register target of * device @oh, or NULL on error. */ -static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) +static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index) { struct omap_hwmod_ocp_if *os; struct omap_hwmod_addr_space *mem; @@ -786,11 +790,11 @@ static void _enable_sysc(struct omap_hwmod *oh) (sf & SYSC_HAS_CLOCKACTIVITY)) _set_clockactivity(oh, oh->class->sysc->clockact, &v); - _write_sysconfig(v, oh); - /* If slave is in SMARTIDLE, also enable wakeup */ if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) - _enable_wakeup(oh); + _enable_wakeup(oh, &v); + + _write_sysconfig(v, oh); /* * Set the autoidle bit only after setting the smartidle bit @@ -836,6 +840,10 @@ static void _idle_sysc(struct omap_hwmod *oh) _set_master_standbymode(oh, idlemode, &v); } + /* If slave is in SMARTIDLE, also enable wakeup */ + if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) + _enable_wakeup(oh, &v); + _write_sysconfig(v, oh); } @@ -874,7 +882,6 @@ static void _shutdown_sysc(struct omap_hwmod *oh) * @name: find an omap_hwmod by name * * Return a pointer to an omap_hwmod by name, or NULL if not found. - * Caller must hold omap_hwmod_mutex. */ static struct omap_hwmod *_lookup(const char *name) { @@ -1089,7 +1096,7 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name) } /** - * _reset - reset an omap_hwmod + * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit * @oh: struct omap_hwmod * * * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be @@ -1098,12 +1105,13 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name) * the module did not reset in time, or 0 upon success. * * In OMAP3 a specific SYSSTATUS register is used to get the reset status. - * Starting in OMAP4, some IPs does not have SYSSTATUS register and instead + * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead * use the SYSCONFIG softreset bit to provide the status. * - * Note that some IP like McBSP does have a reset control but no reset status. + * Note that some IP like McBSP do have reset control but don't have + * reset status. */ -static int _reset(struct omap_hwmod *oh) +static int _ocp_softreset(struct omap_hwmod *oh) { u32 v; int c = 0; @@ -1124,7 +1132,7 @@ static int _reset(struct omap_hwmod *oh) if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) _enable_optional_clocks(oh); - pr_debug("omap_hwmod: %s: resetting\n", oh->name); + pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); v = oh->_sysc_cache; ret = _set_softreset(oh, &v); @@ -1164,17 +1172,41 @@ dis_opt_clks: } /** - * _omap_hwmod_enable - enable an omap_hwmod + * _reset - reset an omap_hwmod + * @oh: struct omap_hwmod * + * + * Resets an omap_hwmod @oh. The default software reset mechanism for + * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET + * bit. However, some hwmods cannot be reset via this method: some + * are not targets and therefore have no OCP header registers to + * access; others (like the IVA) have idiosyncratic reset sequences. + * So for these relatively rare cases, custom reset code can be + * supplied in the struct omap_hwmod_class .reset function pointer. + * Passes along the return value from either _reset() or the custom + * reset function - these must return -EINVAL if the hwmod cannot be + * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if + * the module did not reset in time, or 0 upon success. + */ +static int _reset(struct omap_hwmod *oh) +{ + int ret; + + pr_debug("omap_hwmod: %s: resetting\n", oh->name); + + ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh); + + return ret; +} + +/** + * _enable - enable an omap_hwmod * @oh: struct omap_hwmod * * * Enables an omap_hwmod @oh such that the MPU can access the hwmod's - * register target. (This function has a full name -- - * _omap_hwmod_enable() rather than simply _enable() -- because it is - * currently required by the pm34xx.c idle loop.) Returns -EINVAL if - * the hwmod is in the wrong state or passes along the return value of - * _wait_target_ready(). + * register target. Returns -EINVAL if the hwmod is in the wrong + * state or passes along the return value of _wait_target_ready(). */ -int _omap_hwmod_enable(struct omap_hwmod *oh) +static int _enable(struct omap_hwmod *oh) { int r; @@ -1197,7 +1229,9 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) _deassert_hardreset(oh, oh->rst_lines[0].name); - /* XXX mux balls */ + /* Mux pins for device runtime if populated */ + if (oh->mux) + omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); _add_initiator_dep(oh, mpu_oh); _enable_clocks(oh); @@ -1213,6 +1247,7 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) _enable_sysc(oh); } } else { + _disable_clocks(oh); pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", oh->name, r); } @@ -1221,16 +1256,14 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) } /** - * _omap_hwmod_idle - idle an omap_hwmod + * _idle - idle an omap_hwmod * @oh: struct omap_hwmod * * * Idles an omap_hwmod @oh. This should be called once the hwmod has - * no further work. (This function has a full name -- - * _omap_hwmod_idle() rather than simply _idle() -- because it is - * currently required by the pm34xx.c idle loop.) Returns -EINVAL if - * the hwmod is in the wrong state or returns 0. + * no further work. Returns -EINVAL if the hwmod is in the wrong + * state or returns 0. */ -int _omap_hwmod_idle(struct omap_hwmod *oh) +static int _idle(struct omap_hwmod *oh) { if (oh->_state != _HWMOD_STATE_ENABLED) { WARN(1, "omap_hwmod: %s: idle state can only be entered from " @@ -1245,6 +1278,10 @@ int _omap_hwmod_idle(struct omap_hwmod *oh) _del_initiator_dep(oh, mpu_oh); _disable_clocks(oh); + /* Mux pins for device idle if populated */ + if (oh->mux) + omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); + oh->_state = _HWMOD_STATE_IDLE; return 0; @@ -1261,6 +1298,9 @@ int _omap_hwmod_idle(struct omap_hwmod *oh) */ static int _shutdown(struct omap_hwmod *oh) { + int ret; + u8 prev_state; + if (oh->_state != _HWMOD_STATE_IDLE && oh->_state != _HWMOD_STATE_ENABLED) { WARN(1, "omap_hwmod: %s: disabled state can only be entered " @@ -1270,6 +1310,18 @@ static int _shutdown(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: disabling\n", oh->name); + if (oh->class->pre_shutdown) { + prev_state = oh->_state; + if (oh->_state == _HWMOD_STATE_IDLE) + _enable(oh); + ret = oh->class->pre_shutdown(oh); + if (ret) { + if (prev_state == _HWMOD_STATE_IDLE) + _idle(oh); + return ret; + } + } + if (oh->class->sysc) _shutdown_sysc(oh); @@ -1288,7 +1340,9 @@ static int _shutdown(struct omap_hwmod *oh) } /* XXX Should this code also force-disable the optional clocks? */ - /* XXX mux any associated balls to safe mode */ + /* Mux pins to safe mode or use populated off mode values */ + if (oh->mux) + omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); oh->_state = _HWMOD_STATE_DISABLED; @@ -1298,23 +1352,15 @@ static int _shutdown(struct omap_hwmod *oh) /** * _setup - do initial configuration of omap_hwmod * @oh: struct omap_hwmod * - * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1 * * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh - * OCP_SYSCONFIG register. @skip_setup_idle is intended to be used on - * a system that will not call omap_hwmod_enable() to enable devices - * (e.g., a system without PM runtime). Returns -EINVAL if the hwmod - * is in the wrong state or returns 0. + * OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the + * wrong state or returns 0. */ static int _setup(struct omap_hwmod *oh, void *data) { int i, r; - u8 skip_setup_idle; - - if (!oh || !data) - return -EINVAL; - - skip_setup_idle = *(u8 *)data; + u8 postsetup_state; /* Set iclk autoidle mode */ if (oh->slaves_cnt > 0) { @@ -1334,7 +1380,6 @@ static int _setup(struct omap_hwmod *oh, void *data) } } - mutex_init(&oh->_mutex); oh->_state = _HWMOD_STATE_INITIALIZED; /* @@ -1347,7 +1392,7 @@ static int _setup(struct omap_hwmod *oh, void *data) if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) return 0; - r = _omap_hwmod_enable(oh); + r = _enable(oh); if (r) { pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", oh->name, oh->_state); @@ -1359,7 +1404,7 @@ static int _setup(struct omap_hwmod *oh, void *data) /* * OCP_SYSCONFIG bits need to be reprogrammed after a softreset. - * The _omap_hwmod_enable() function should be split to + * The _enable() function should be split to * avoid the rewrite of the OCP_SYSCONFIG register. */ if (oh->class->sysc) { @@ -1368,12 +1413,77 @@ static int _setup(struct omap_hwmod *oh, void *data) } } - if (!(oh->flags & HWMOD_INIT_NO_IDLE) && !skip_setup_idle) - _omap_hwmod_idle(oh); + postsetup_state = oh->_postsetup_state; + if (postsetup_state == _HWMOD_STATE_UNKNOWN) + postsetup_state = _HWMOD_STATE_ENABLED; + + /* + * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - + * it should be set by the core code as a runtime flag during startup + */ + if ((oh->flags & HWMOD_INIT_NO_IDLE) && + (postsetup_state == _HWMOD_STATE_IDLE)) + postsetup_state = _HWMOD_STATE_ENABLED; + + if (postsetup_state == _HWMOD_STATE_IDLE) + _idle(oh); + else if (postsetup_state == _HWMOD_STATE_DISABLED) + _shutdown(oh); + else if (postsetup_state != _HWMOD_STATE_ENABLED) + WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", + oh->name, postsetup_state); return 0; } +/** + * _register - register a struct omap_hwmod + * @oh: struct omap_hwmod * + * + * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod + * already has been registered by the same name; -EINVAL if the + * omap_hwmod is in the wrong state, if @oh is NULL, if the + * omap_hwmod's class field is NULL; if the omap_hwmod is missing a + * name, or if the omap_hwmod's class is missing a name; or 0 upon + * success. + * + * XXX The data should be copied into bootmem, so the original data + * should be marked __initdata and freed after init. This would allow + * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note + * that the copy process would be relatively complex due to the large number + * of substructures. + */ +static int __init _register(struct omap_hwmod *oh) +{ + int ret, ms_id; + + if (!oh || !oh->name || !oh->class || !oh->class->name || + (oh->_state != _HWMOD_STATE_UNKNOWN)) + return -EINVAL; + + pr_debug("omap_hwmod: %s: registering\n", oh->name); + + if (_lookup(oh->name)) + return -EEXIST; + + ms_id = _find_mpu_port_index(oh); + if (!IS_ERR_VALUE(ms_id)) { + oh->_mpu_port_index = ms_id; + oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); + } else { + oh->_int_flags |= _HWMOD_NO_MPU_PORT; + } + + list_add_tail(&oh->node, &omap_hwmod_list); + + spin_lock_init(&oh->_lock); + + oh->_state = _HWMOD_STATE_REGISTERED; + + ret = 0; + + return ret; +} /* Public functions */ @@ -1427,59 +1537,6 @@ int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) } /** - * omap_hwmod_register - register a struct omap_hwmod - * @oh: struct omap_hwmod * - * - * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod - * already has been registered by the same name; -EINVAL if the - * omap_hwmod is in the wrong state, if @oh is NULL, if the - * omap_hwmod's class field is NULL; if the omap_hwmod is missing a - * name, or if the omap_hwmod's class is missing a name; or 0 upon - * success. - * - * XXX The data should be copied into bootmem, so the original data - * should be marked __initdata and freed after init. This would allow - * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note - * that the copy process would be relatively complex due to the large number - * of substructures. - */ -int omap_hwmod_register(struct omap_hwmod *oh) -{ - int ret, ms_id; - - if (!oh || !oh->name || !oh->class || !oh->class->name || - (oh->_state != _HWMOD_STATE_UNKNOWN)) - return -EINVAL; - - mutex_lock(&omap_hwmod_mutex); - - pr_debug("omap_hwmod: %s: registering\n", oh->name); - - if (_lookup(oh->name)) { - ret = -EEXIST; - goto ohr_unlock; - } - - ms_id = _find_mpu_port_index(oh); - if (!IS_ERR_VALUE(ms_id)) { - oh->_mpu_port_index = ms_id; - oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); - } else { - oh->_int_flags |= _HWMOD_NO_MPU_PORT; - } - - list_add_tail(&oh->node, &omap_hwmod_list); - - oh->_state = _HWMOD_STATE_REGISTERED; - - ret = 0; - -ohr_unlock: - mutex_unlock(&omap_hwmod_mutex); - return ret; -} - -/** * omap_hwmod_lookup - look up a registered omap_hwmod by name * @name: name of the omap_hwmod to look up * @@ -1493,9 +1550,7 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name) if (!name) return NULL; - mutex_lock(&omap_hwmod_mutex); oh = _lookup(name); - mutex_unlock(&omap_hwmod_mutex); return oh; } @@ -1521,13 +1576,11 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), if (!fn) return -EINVAL; - mutex_lock(&omap_hwmod_mutex); list_for_each_entry(temp_oh, &omap_hwmod_list, node) { ret = (*fn)(temp_oh, data); if (ret) break; } - mutex_unlock(&omap_hwmod_mutex); return ret; } @@ -1542,7 +1595,7 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), * listed in @ohs that are valid for this chip. Returns -EINVAL if * omap_hwmod_init() has already been called or 0 otherwise. */ -int omap_hwmod_init(struct omap_hwmod **ohs) +int __init omap_hwmod_init(struct omap_hwmod **ohs) { struct omap_hwmod *oh; int r; @@ -1558,8 +1611,8 @@ int omap_hwmod_init(struct omap_hwmod **ohs) oh = *ohs; while (oh) { if (omap_chip_is(oh->omap_chip)) { - r = omap_hwmod_register(oh); - WARN(r, "omap_hwmod: %s: omap_hwmod_register returned " + r = _register(oh); + WARN(r, "omap_hwmod: %s: _register returned " "%d\n", oh->name, r); } oh = *++ohs; @@ -1570,13 +1623,12 @@ int omap_hwmod_init(struct omap_hwmod **ohs) /** * omap_hwmod_late_init - do some post-clock framework initialization - * @skip_setup_idle: if 1, do not idle hwmods in _setup() * * Must be called after omap2_clk_init(). Resolves the struct clk names * to struct clk pointers for each registered omap_hwmod. Also calls * _setup() on each hwmod. Returns 0. */ -int omap_hwmod_late_init(u8 skip_setup_idle) +int omap_hwmod_late_init(void) { int r; @@ -1588,36 +1640,7 @@ int omap_hwmod_late_init(u8 skip_setup_idle) WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", MPU_INITIATOR_NAME); - if (skip_setup_idle) - pr_debug("omap_hwmod: will leave hwmods enabled during setup\n"); - - omap_hwmod_for_each(_setup, &skip_setup_idle); - - return 0; -} - -/** - * omap_hwmod_unregister - unregister an omap_hwmod - * @oh: struct omap_hwmod * - * - * Unregisters a previously-registered omap_hwmod @oh. There's probably - * no use case for this, so it is likely to be removed in a later version. - * - * XXX Free all of the bootmem-allocated structures here when that is - * implemented. Make it clear that core code is the only code that is - * expected to unregister modules. - */ -int omap_hwmod_unregister(struct omap_hwmod *oh) -{ - if (!oh) - return -EINVAL; - - pr_debug("omap_hwmod: %s: unregistering\n", oh->name); - - mutex_lock(&omap_hwmod_mutex); - iounmap(oh->_mpu_rt_va); - list_del(&oh->node); - mutex_unlock(&omap_hwmod_mutex); + omap_hwmod_for_each(_setup, NULL); return 0; } @@ -1632,18 +1655,18 @@ int omap_hwmod_unregister(struct omap_hwmod *oh) int omap_hwmod_enable(struct omap_hwmod *oh) { int r; + unsigned long flags; if (!oh) return -EINVAL; - mutex_lock(&oh->_mutex); - r = _omap_hwmod_enable(oh); - mutex_unlock(&oh->_mutex); + spin_lock_irqsave(&oh->_lock, flags); + r = _enable(oh); + spin_unlock_irqrestore(&oh->_lock, flags); return r; } - /** * omap_hwmod_idle - idle an omap_hwmod * @oh: struct omap_hwmod * @@ -1653,12 +1676,14 @@ int omap_hwmod_enable(struct omap_hwmod *oh) */ int omap_hwmod_idle(struct omap_hwmod *oh) { + unsigned long flags; + if (!oh) return -EINVAL; - mutex_lock(&oh->_mutex); - _omap_hwmod_idle(oh); - mutex_unlock(&oh->_mutex); + spin_lock_irqsave(&oh->_lock, flags); + _idle(oh); + spin_unlock_irqrestore(&oh->_lock, flags); return 0; } @@ -1673,12 +1698,14 @@ int omap_hwmod_idle(struct omap_hwmod *oh) */ int omap_hwmod_shutdown(struct omap_hwmod *oh) { + unsigned long flags; + if (!oh) return -EINVAL; - mutex_lock(&oh->_mutex); + spin_lock_irqsave(&oh->_lock, flags); _shutdown(oh); - mutex_unlock(&oh->_mutex); + spin_unlock_irqrestore(&oh->_lock, flags); return 0; } @@ -1691,9 +1718,11 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh) */ int omap_hwmod_enable_clocks(struct omap_hwmod *oh) { - mutex_lock(&oh->_mutex); + unsigned long flags; + + spin_lock_irqsave(&oh->_lock, flags); _enable_clocks(oh); - mutex_unlock(&oh->_mutex); + spin_unlock_irqrestore(&oh->_lock, flags); return 0; } @@ -1706,9 +1735,11 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh) */ int omap_hwmod_disable_clocks(struct omap_hwmod *oh) { - mutex_lock(&oh->_mutex); + unsigned long flags; + + spin_lock_irqsave(&oh->_lock, flags); _disable_clocks(oh); - mutex_unlock(&oh->_mutex); + spin_unlock_irqrestore(&oh->_lock, flags); return 0; } @@ -1752,13 +1783,14 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) int omap_hwmod_reset(struct omap_hwmod *oh) { int r; + unsigned long flags; if (!oh) return -EINVAL; - mutex_lock(&oh->_mutex); + spin_lock_irqsave(&oh->_lock, flags); r = _reset(oh); - mutex_unlock(&oh->_mutex); + spin_unlock_irqrestore(&oh->_lock, flags); return r; } @@ -1955,13 +1987,18 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, */ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) { + unsigned long flags; + u32 v; + if (!oh->class->sysc || !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) return -EINVAL; - mutex_lock(&oh->_mutex); - _enable_wakeup(oh); - mutex_unlock(&oh->_mutex); + spin_lock_irqsave(&oh->_lock, flags); + v = oh->_sysc_cache; + _enable_wakeup(oh, &v); + _write_sysconfig(v, oh); + spin_unlock_irqrestore(&oh->_lock, flags); return 0; } @@ -1980,13 +2017,18 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) */ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) { + unsigned long flags; + u32 v; + if (!oh->class->sysc || !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) return -EINVAL; - mutex_lock(&oh->_mutex); - _disable_wakeup(oh); - mutex_unlock(&oh->_mutex); + spin_lock_irqsave(&oh->_lock, flags); + v = oh->_sysc_cache; + _disable_wakeup(oh, &v); + _write_sysconfig(v, oh); + spin_unlock_irqrestore(&oh->_lock, flags); return 0; } @@ -2006,13 +2048,14 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) { int ret; + unsigned long flags; if (!oh) return -EINVAL; - mutex_lock(&oh->_mutex); + spin_lock_irqsave(&oh->_lock, flags); ret = _assert_hardreset(oh, name); - mutex_unlock(&oh->_mutex); + spin_unlock_irqrestore(&oh->_lock, flags); return ret; } @@ -2032,13 +2075,14 @@ int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) { int ret; + unsigned long flags; if (!oh) return -EINVAL; - mutex_lock(&oh->_mutex); + spin_lock_irqsave(&oh->_lock, flags); ret = _deassert_hardreset(oh, name); - mutex_unlock(&oh->_mutex); + spin_unlock_irqrestore(&oh->_lock, flags); return ret; } @@ -2057,13 +2101,14 @@ int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) { int ret; + unsigned long flags; if (!oh) return -EINVAL; - mutex_lock(&oh->_mutex); + spin_lock_irqsave(&oh->_lock, flags); ret = _read_hardreset(oh, name); - mutex_unlock(&oh->_mutex); + spin_unlock_irqrestore(&oh->_lock, flags); return ret; } @@ -2075,9 +2120,8 @@ int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) * @fn: callback function pointer to call for each hwmod in class @classname * @user: arbitrary context data to pass to the callback function * - * For each omap_hwmod of class @classname, call @fn. Takes - * omap_hwmod_mutex to prevent the hwmod list from changing during the - * iteration. If the callback function returns something other than + * For each omap_hwmod of class @classname, call @fn. + * If the callback function returns something other than * zero, the iterator is terminated, and the callback function's return * value is passed back to the caller. Returns 0 upon success, -EINVAL * if @classname or @fn are NULL, or passes back the error code from @fn. @@ -2096,8 +2140,6 @@ int omap_hwmod_for_each_by_class(const char *classname, pr_debug("omap_hwmod: %s: looking for modules of class %s\n", __func__, classname); - mutex_lock(&omap_hwmod_mutex); - list_for_each_entry(temp_oh, &omap_hwmod_list, node) { if (!strcmp(temp_oh->class->name, classname)) { pr_debug("omap_hwmod: %s: %s: calling callback fn\n", @@ -2108,8 +2150,6 @@ int omap_hwmod_for_each_by_class(const char *classname, } } - mutex_unlock(&omap_hwmod_mutex); - if (ret) pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", __func__, ret); @@ -2117,3 +2157,64 @@ int omap_hwmod_for_each_by_class(const char *classname, return ret; } +/** + * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod + * @oh: struct omap_hwmod * + * @state: state that _setup() should leave the hwmod in + * + * Sets the hwmod state that @oh will enter at the end of _setup() (called by + * omap_hwmod_late_init()). Only valid to call between calls to + * omap_hwmod_init() and omap_hwmod_late_init(). Returns 0 upon success or + * -EINVAL if there is a problem with the arguments or if the hwmod is + * in the wrong state. + */ +int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) +{ + int ret; + unsigned long flags; + + if (!oh) + return -EINVAL; + + if (state != _HWMOD_STATE_DISABLED && + state != _HWMOD_STATE_ENABLED && + state != _HWMOD_STATE_IDLE) + return -EINVAL; + + spin_lock_irqsave(&oh->_lock, flags); + + if (oh->_state != _HWMOD_STATE_REGISTERED) { + ret = -EINVAL; + goto ohsps_unlock; + } + + oh->_postsetup_state = state; + ret = 0; + +ohsps_unlock: + spin_unlock_irqrestore(&oh->_lock, flags); + + return ret; +} + +/** + * omap_hwmod_get_context_loss_count - get lost context count + * @oh: struct omap_hwmod * + * + * Query the powerdomain of of @oh to get the context loss + * count for this device. + * + * Returns the context loss count of the powerdomain assocated with @oh + * upon success, or zero if no powerdomain exists for @oh. + */ +u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) +{ + struct powerdomain *pwrdm; + int ret = 0; + + pwrdm = omap_hwmod_get_pwrdm(oh); + if (pwrdm) + ret = pwrdm_get_context_loss_count(pwrdm); + + return ret; +} diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index adf6e3632a2b..b85c630b64d6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -16,11 +16,14 @@ #include <plat/cpu.h> #include <plat/dma.h> #include <plat/serial.h> +#include <plat/i2c.h> +#include <plat/gpio.h> #include "omap_hwmod_common_data.h" -#include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" +#include "prm-regbits-24xx.h" +#include "wd_timer.h" /* * OMAP2420 hardware module integration data @@ -36,6 +39,11 @@ static struct omap_hwmod omap2420_iva_hwmod; static struct omap_hwmod omap2420_l3_main_hwmod; static struct omap_hwmod omap2420_l4_core_hwmod; static struct omap_hwmod omap2420_wd_timer2_hwmod; +static struct omap_hwmod omap2420_gpio1_hwmod; +static struct omap_hwmod omap2420_gpio2_hwmod; +static struct omap_hwmod omap2420_gpio3_hwmod; +static struct omap_hwmod omap2420_gpio4_hwmod; +static struct omap_hwmod omap2420_dma_system_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { @@ -77,6 +85,8 @@ static struct omap_hwmod omap2420_l4_wkup_hwmod; static struct omap_hwmod omap2420_uart1_hwmod; static struct omap_hwmod omap2420_uart2_hwmod; static struct omap_hwmod omap2420_uart3_hwmod; +static struct omap_hwmod omap2420_i2c1_hwmod; +static struct omap_hwmod omap2420_i2c2_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { @@ -139,6 +149,45 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* I2C IP block address space length (in bytes) */ +#define OMAP2_I2C_AS_LEN 128 + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = { + { + .pa_start = 0x48070000, + .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2420_i2c1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = { + { + .pa_start = 0x48072000, + .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2420_i2c2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { &omap2420_l3_main__l4_core, @@ -150,6 +199,8 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { &omap2_l4_core__uart1, &omap2_l4_core__uart2, &omap2_l4_core__uart3, + &omap2420_l4_core__i2c1, + &omap2420_l4_core__i2c2 }; /* L4 CORE */ @@ -262,8 +313,9 @@ static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = { }; static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = { - .name = "wd_timer", - .sysc = &omap2420_wd_timer_sysc, + .name = "wd_timer", + .sysc = &omap2420_wd_timer_sysc, + .pre_shutdown = &omap2_wd_timer_disable }; /* wd_timer2 */ @@ -418,6 +470,400 @@ static struct omap_hwmod omap2420_uart3_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = SYSC_HAS_SOFTRESET, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, +}; + +static struct omap_i2c_dev_attr i2c_dev_attr; + +/* I2C1 */ + +static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { + { .irq = INT_24XX_I2C1_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, +}; + +static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { + &omap2420_l4_core__i2c1, +}; + +static struct omap_hwmod omap2420_i2c1_hwmod = { + .name = "i2c1", + .mpu_irqs = i2c1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), + .sdma_reqs = i2c1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), + .main_clk = "i2c1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2420_EN_I2C1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, + }, + }, + .slaves = omap2420_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_16BIT_REG, +}; + +/* I2C2 */ + +static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { + { .irq = INT_24XX_I2C2_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, +}; + +static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { + &omap2420_l4_core__i2c2, +}; + +static struct omap_hwmod omap2420_i2c2_hwmod = { + .name = "i2c2", + .mpu_irqs = i2c2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), + .sdma_reqs = i2c2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), + .main_clk = "i2c2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2420_EN_I2C2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, + }, + }, + .slaves = omap2420_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_16BIT_REG, +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { + { + .pa_start = 0x48018000, + .pa_end = 0x480181ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio1_hwmod, + .clk = "gpios_ick", + .addr = omap2420_gpio1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio2 */ +static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { + { + .pa_start = 0x4801a000, + .pa_end = 0x4801a1ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio2_hwmod, + .clk = "gpios_ick", + .addr = omap2420_gpio2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio3 */ +static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { + { + .pa_start = 0x4801c000, + .pa_end = 0x4801c1ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio3_hwmod, + .clk = "gpios_ick", + .addr = omap2420_gpio3_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio4 */ +static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { + { + .pa_start = 0x4801e000, + .pa_end = 0x4801e1ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gpio4_hwmod, + .clk = "gpios_ick", + .addr = omap2420_gpio4_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio dev_attr */ +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = false, +}; + +static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +/* + * 'gpio' class + * general purpose io module + */ +static struct omap_hwmod_class omap242x_gpio_hwmod_class = { + .name = "gpio", + .sysc = &omap242x_gpio_sysc, + .rev = 0, +}; + +/* gpio1 */ +static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = { + { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ +}; + +static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { + &omap2420_l4_wkup__gpio1, +}; + +static struct omap_hwmod omap2420_gpio1_hwmod = { + .name = "gpio1", + .mpu_irqs = omap242x_gpio1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2420_gpio1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), + .class = &omap242x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* gpio2 */ +static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = { + { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ +}; + +static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { + &omap2420_l4_wkup__gpio2, +}; + +static struct omap_hwmod omap2420_gpio2_hwmod = { + .name = "gpio2", + .mpu_irqs = omap242x_gpio2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2420_gpio2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), + .class = &omap242x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* gpio3 */ +static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = { + { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ +}; + +static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { + &omap2420_l4_wkup__gpio3, +}; + +static struct omap_hwmod omap2420_gpio3_hwmod = { + .name = "gpio3", + .mpu_irqs = omap242x_gpio3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2420_gpio3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), + .class = &omap242x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* gpio4 */ +static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = { + { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ +}; + +static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { + &omap2420_l4_wkup__gpio4, +}; + +static struct omap_hwmod omap2420_gpio4_hwmod = { + .name = "gpio4", + .mpu_irqs = omap242x_gpio4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2420_gpio4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), + .class = &omap242x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* system dma */ +static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x002c, + .syss_offs = 0x0028, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | + SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | + SYSC_HAS_AUTOIDLE), + .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_dma_hwmod_class = { + .name = "dma", + .sysc = &omap2420_dma_sysc, +}; + +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32, + .lch_count = 32, +}; + +static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = { + { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ + { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ + { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ + { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ +}; + +static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = { + { + .pa_start = 0x48056000, + .pa_end = 0x4a0560ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { + .master = &omap2420_dma_system_hwmod, + .slave = &omap2420_l3_main_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system master ports */ +static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = { + &omap2420_dma_system__l3, +}; + +/* l4_core -> dma_system */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dma_system_hwmod, + .clk = "sdma_ick", + .addr = omap2420_dma_system_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system slave ports */ +static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { + &omap2420_l4_core__dma_system, +}; + +static struct omap_hwmod omap2420_dma_system_hwmod = { + .name = "dma", + .class = &omap2420_dma_hwmod_class, + .mpu_irqs = omap2420_dma_system_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs), + .main_clk = "core_l3_ck", + .slaves = omap2420_dma_system_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), + .masters = omap2420_dma_system_masters, + .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), + .dev_attr = &dma_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_NO_IDLEST, +}; + static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l3_main_hwmod, &omap2420_l4_core_hwmod, @@ -428,6 +874,17 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_uart1_hwmod, &omap2420_uart2_hwmod, &omap2420_uart3_hwmod, + &omap2420_i2c1_hwmod, + &omap2420_i2c2_hwmod, + + /* gpio class */ + &omap2420_gpio1_hwmod, + &omap2420_gpio2_hwmod, + &omap2420_gpio3_hwmod, + &omap2420_gpio4_hwmod, + + /* dma_system class*/ + &omap2420_dma_system_hwmod, NULL, }; @@ -435,5 +892,3 @@ int __init omap2420_hwmod_init(void) { return omap_hwmod_init(omap2420_hwmods); } - - diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 12d939e456cf..8ecfbcde13ba 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -16,11 +16,14 @@ #include <plat/cpu.h> #include <plat/dma.h> #include <plat/serial.h> +#include <plat/i2c.h> +#include <plat/gpio.h> #include "omap_hwmod_common_data.h" #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" +#include "wd_timer.h" /* * OMAP2430 hardware module integration data @@ -36,6 +39,12 @@ static struct omap_hwmod omap2430_iva_hwmod; static struct omap_hwmod omap2430_l3_main_hwmod; static struct omap_hwmod omap2430_l4_core_hwmod; static struct omap_hwmod omap2430_wd_timer2_hwmod; +static struct omap_hwmod omap2430_gpio1_hwmod; +static struct omap_hwmod omap2430_gpio2_hwmod; +static struct omap_hwmod omap2430_gpio3_hwmod; +static struct omap_hwmod omap2430_gpio4_hwmod; +static struct omap_hwmod omap2430_gpio5_hwmod; +static struct omap_hwmod omap2430_dma_system_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { @@ -77,6 +86,47 @@ static struct omap_hwmod omap2430_l4_wkup_hwmod; static struct omap_hwmod omap2430_uart1_hwmod; static struct omap_hwmod omap2430_uart2_hwmod; static struct omap_hwmod omap2430_uart3_hwmod; +static struct omap_hwmod omap2430_i2c1_hwmod; +static struct omap_hwmod omap2430_i2c2_hwmod; + +/* I2C IP block address space length (in bytes) */ +#define OMAP2_I2C_AS_LEN 128 + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = { + { + .pa_start = 0x48070000, + .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2430_i2c1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = { + { + .pa_start = 0x48072000, + .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2430_i2c2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { @@ -262,8 +312,9 @@ static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { }; static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { - .name = "wd_timer", - .sysc = &omap2430_wd_timer_sysc, + .name = "wd_timer", + .sysc = &omap2430_wd_timer_sysc, + .pre_shutdown = &omap2_wd_timer_disable }; /* wd_timer2 */ @@ -418,6 +469,456 @@ static struct omap_hwmod omap2430_uart3_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, +}; + +static struct omap_i2c_dev_attr i2c_dev_attr = { + .fifo_depth = 8, /* bytes */ +}; + +/* I2C1 */ + +static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { + { .irq = INT_24XX_I2C1_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, +}; + +static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { + &omap2430_l4_core__i2c1, +}; + +static struct omap_hwmod omap2430_i2c1_hwmod = { + .name = "i2c1", + .mpu_irqs = i2c1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), + .sdma_reqs = i2c1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), + .main_clk = "i2chs1_fck", + .prcm = { + .omap2 = { + /* + * NOTE: The CM_FCLKEN* and CM_ICLKEN* for + * I2CHS IP's do not follow the usual pattern. + * prcm_reg_id alone cannot be used to program + * the iclk and fclk. Needs to be handled using + * additonal flags when clk handling is moved + * to hwmod framework. + */ + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_I2CHS1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, + }, + }, + .slaves = omap2430_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* I2C2 */ + +static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { + { .irq = INT_24XX_I2C2_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, +}; + +static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { + &omap2430_l4_core__i2c2, +}; + +static struct omap_hwmod omap2430_i2c2_hwmod = { + .name = "i2c2", + .mpu_irqs = i2c2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), + .sdma_reqs = i2c2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), + .main_clk = "i2chs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_I2CHS2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, + }, + }, + .slaves = omap2430_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { + { + .pa_start = 0x4900C000, + .pa_end = 0x4900C1ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio1_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio2 */ +static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { + { + .pa_start = 0x4900E000, + .pa_end = 0x4900E1ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio2_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio3 */ +static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { + { + .pa_start = 0x49010000, + .pa_end = 0x490101ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio3_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio3_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio4 */ +static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { + { + .pa_start = 0x49012000, + .pa_end = 0x490121ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio4_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio4_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> gpio5 */ +static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { + { + .pa_start = 0x480B6000, + .pa_end = 0x480B61ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gpio5_hwmod, + .clk = "gpio5_ick", + .addr = omap2430_gpio5_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio dev_attr */ +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = false, +}; + +static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +/* + * 'gpio' class + * general purpose io module + */ +static struct omap_hwmod_class omap243x_gpio_hwmod_class = { + .name = "gpio", + .sysc = &omap243x_gpio_sysc, + .rev = 0, +}; + +/* gpio1 */ +static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = { + { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { + &omap2430_l4_wkup__gpio1, +}; + +static struct omap_hwmod omap2430_gpio1_hwmod = { + .name = "gpio1", + .mpu_irqs = omap243x_gpio1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), + .class = &omap243x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* gpio2 */ +static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = { + { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { + &omap2430_l4_wkup__gpio2, +}; + +static struct omap_hwmod omap2430_gpio2_hwmod = { + .name = "gpio2", + .mpu_irqs = omap243x_gpio2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), + .class = &omap243x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* gpio3 */ +static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = { + { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { + &omap2430_l4_wkup__gpio3, +}; + +static struct omap_hwmod omap2430_gpio3_hwmod = { + .name = "gpio3", + .mpu_irqs = omap243x_gpio3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), + .class = &omap243x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* gpio4 */ +static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = { + { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { + &omap2430_l4_wkup__gpio4, +}; + +static struct omap_hwmod omap2430_gpio4_hwmod = { + .name = "gpio4", + .mpu_irqs = omap243x_gpio4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), + .class = &omap243x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* gpio5 */ +static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { + { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { + &omap2430_l4_core__gpio5, +}; + +static struct omap_hwmod omap2430_gpio5_hwmod = { + .name = "gpio5", + .mpu_irqs = omap243x_gpio5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), + .main_clk = "gpio5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_GPIO5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, + }, + }, + .slaves = omap2430_gpio5_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), + .class = &omap243x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* dma_system */ +static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x002c, + .syss_offs = 0x0028, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | + SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | + SYSC_HAS_AUTOIDLE), + .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_dma_hwmod_class = { + .name = "dma", + .sysc = &omap2430_dma_sysc, +}; + +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, + .lch_count = 32, +}; + +static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { + { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ + { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ + { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ + { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ +}; + +static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { + { + .pa_start = 0x48056000, + .pa_end = 0x4a0560ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { + .master = &omap2430_dma_system_hwmod, + .slave = &omap2430_l3_main_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system master ports */ +static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { + &omap2430_dma_system__l3, +}; + +/* l4_core -> dma_system */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dma_system_hwmod, + .clk = "sdma_ick", + .addr = omap2430_dma_system_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { + &omap2430_l4_core__dma_system, +}; + +static struct omap_hwmod omap2430_dma_system_hwmod = { + .name = "dma", + .class = &omap2430_dma_hwmod_class, + .mpu_irqs = omap2430_dma_system_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs), + .main_clk = "core_l3_ck", + .slaves = omap2430_dma_system_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), + .masters = omap2430_dma_system_masters, + .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), + .dev_attr = &dma_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, +}; + static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_main_hwmod, &omap2430_l4_core_hwmod, @@ -428,6 +929,18 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_uart1_hwmod, &omap2430_uart2_hwmod, &omap2430_uart3_hwmod, + &omap2430_i2c1_hwmod, + &omap2430_i2c2_hwmod, + + /* gpio class */ + &omap2430_gpio1_hwmod, + &omap2430_gpio2_hwmod, + &omap2430_gpio3_hwmod, + &omap2430_gpio4_hwmod, + &omap2430_gpio5_hwmod, + + /* dma_system class*/ + &omap2430_dma_system_hwmod, NULL, }; @@ -435,5 +948,3 @@ int __init omap2430_hwmod_init(void) { return omap_hwmod_init(omap2430_hwmods); } - - diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index cb97ecf0a3f6..8d8181334f86 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -18,11 +18,16 @@ #include <plat/cpu.h> #include <plat/dma.h> #include <plat/serial.h> +#include <plat/l4_3xxx.h> +#include <plat/i2c.h> +#include <plat/gpio.h> +#include <plat/smartreflex.h> #include "omap_hwmod_common_data.h" #include "prm-regbits-34xx.h" #include "cm-regbits-34xx.h" +#include "wd_timer.h" /* * OMAP3xxx hardware module integration data @@ -39,6 +44,19 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod; static struct omap_hwmod omap3xxx_l4_core_hwmod; static struct omap_hwmod omap3xxx_l4_per_hwmod; static struct omap_hwmod omap3xxx_wd_timer2_hwmod; +static struct omap_hwmod omap3xxx_i2c1_hwmod; +static struct omap_hwmod omap3xxx_i2c2_hwmod; +static struct omap_hwmod omap3xxx_i2c3_hwmod; +static struct omap_hwmod omap3xxx_gpio1_hwmod; +static struct omap_hwmod omap3xxx_gpio2_hwmod; +static struct omap_hwmod omap3xxx_gpio3_hwmod; +static struct omap_hwmod omap3xxx_gpio4_hwmod; +static struct omap_hwmod omap3xxx_gpio5_hwmod; +static struct omap_hwmod omap3xxx_gpio6_hwmod; +static struct omap_hwmod omap34xx_sr1_hwmod; +static struct omap_hwmod omap34xx_sr2_hwmod; + +static struct omap_hwmod omap3xxx_dma_system_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { @@ -169,9 +187,125 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* I2C IP block address space length (in bytes) */ +#define OMAP2_I2C_AS_LEN 128 + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = { + { + .pa_start = 0x48070000, + .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap3xxx_i2c1_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = { + { + .pa_start = 0x48072000, + .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap3xxx_i2c2_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C3 interface */ +static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { + { + .pa_start = 0x48060000, + .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c3_hwmod, + .clk = "i2c3_ick", + .addr = omap3xxx_i2c3_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> SR1 interface */ +static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { + { + .pa_start = OMAP34XX_SR1_BASE, + .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_sr1_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr1_addr_space, + .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space), + .user = OCP_USER_MPU, +}; + +/* L4 CORE -> SR1 interface */ +static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { + { + .pa_start = OMAP34XX_SR2_BASE, + .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_sr2_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr2_addr_space, + .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space), + .user = OCP_USER_MPU, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { &omap3xxx_l3_main__l4_core, + &omap3_l4_core__sr1, + &omap3_l4_core__sr2, }; /* Master interfaces on the L4_CORE interconnect */ @@ -179,6 +313,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { &omap3xxx_l4_core__l4_wkup, &omap3_l4_core__uart1, &omap3_l4_core__uart2, + &omap3_l4_core__i2c1, + &omap3_l4_core__i2c2, + &omap3_l4_core__i2c3, }; /* L4 CORE */ @@ -315,9 +452,22 @@ static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { .sysc_fields = &omap_hwmod_sysc_type1, }; +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { - .name = "wd_timer", - .sysc = &omap3xxx_wd_timer_sysc, + .name = "wd_timer", + .sysc = &omap3xxx_wd_timer_sysc, + .pre_shutdown = &omap2_wd_timer_disable }; /* wd_timer2 */ @@ -509,6 +659,703 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), }; +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, +}; + +/* I2C1 */ + +static struct omap_i2c_dev_attr i2c1_dev_attr = { + .fifo_depth = 8, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { + { .irq = INT_24XX_I2C1_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { + &omap3_l4_core__i2c1, +}; + +static struct omap_hwmod omap3xxx_i2c1_hwmod = { + .name = "i2c1", + .mpu_irqs = i2c1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), + .sdma_reqs = i2c1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), + .main_clk = "i2c1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_I2C1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, + }, + }, + .slaves = omap3xxx_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves), + .class = &i2c_class, + .dev_attr = &i2c1_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* I2C2 */ + +static struct omap_i2c_dev_attr i2c2_dev_attr = { + .fifo_depth = 8, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { + { .irq = INT_24XX_I2C2_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { + &omap3_l4_core__i2c2, +}; + +static struct omap_hwmod omap3xxx_i2c2_hwmod = { + .name = "i2c2", + .mpu_irqs = i2c2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), + .sdma_reqs = i2c2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), + .main_clk = "i2c2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_I2C2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, + }, + }, + .slaves = omap3xxx_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves), + .class = &i2c_class, + .dev_attr = &i2c2_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* I2C3 */ + +static struct omap_i2c_dev_attr i2c3_dev_attr = { + .fifo_depth = 64, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { + { .irq = INT_34XX_I2C3_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, + { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { + &omap3_l4_core__i2c3, +}; + +static struct omap_hwmod omap3xxx_i2c3_hwmod = { + .name = "i2c3", + .mpu_irqs = i2c3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs), + .sdma_reqs = i2c3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs), + .main_clk = "i2c3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_I2C3_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, + }, + }, + .slaves = omap3xxx_i2c3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves), + .class = &i2c_class, + .dev_attr = &i2c3_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { + { + .pa_start = 0x48310000, + .pa_end = 0x483101ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_gpio1_hwmod, + .addr = omap3xxx_gpio1_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio2 */ +static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { + { + .pa_start = 0x49050000, + .pa_end = 0x490501ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio2_hwmod, + .addr = omap3xxx_gpio2_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio3 */ +static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { + { + .pa_start = 0x49052000, + .pa_end = 0x490521ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio3_hwmod, + .addr = omap3xxx_gpio3_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio4 */ +static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { + { + .pa_start = 0x49054000, + .pa_end = 0x490541ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio4_hwmod, + .addr = omap3xxx_gpio4_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio5 */ +static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { + { + .pa_start = 0x49056000, + .pa_end = 0x490561ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio5_hwmod, + .addr = omap3xxx_gpio5_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio6 */ +static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { + { + .pa_start = 0x49058000, + .pa_end = 0x490581ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio6_hwmod, + .addr = omap3xxx_gpio6_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* + * 'gpio' class + * general purpose io module + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { + .name = "gpio", + .sysc = &omap3xxx_gpio_sysc, + .rev = 1, +}; + +/* gpio_dev_attr*/ +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = true, +}; + +/* gpio1 */ +static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = { + { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */ +}; + +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { + { .role = "dbclk", .clk = "gpio1_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { + &omap3xxx_l4_wkup__gpio1, +}; + +static struct omap_hwmod omap3xxx_gpio1_hwmod = { + .name = "gpio1", + .mpu_irqs = omap3xxx_gpio1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs), + .main_clk = "gpio1_ick", + .opt_clks = gpio1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, + }, + }, + .slaves = omap3xxx_gpio1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* gpio2 */ +static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = { + { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */ +}; + +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { + { .role = "dbclk", .clk = "gpio2_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { + &omap3xxx_l4_per__gpio2, +}; + +static struct omap_hwmod omap3xxx_gpio2_hwmod = { + .name = "gpio2", + .mpu_irqs = omap3xxx_gpio2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs), + .main_clk = "gpio2_ick", + .opt_clks = gpio2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, + }, + }, + .slaves = omap3xxx_gpio2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* gpio3 */ +static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = { + { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */ +}; + +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { + { .role = "dbclk", .clk = "gpio3_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { + &omap3xxx_l4_per__gpio3, +}; + +static struct omap_hwmod omap3xxx_gpio3_hwmod = { + .name = "gpio3", + .mpu_irqs = omap3xxx_gpio3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs), + .main_clk = "gpio3_ick", + .opt_clks = gpio3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, + }, + }, + .slaves = omap3xxx_gpio3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* gpio4 */ +static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = { + { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */ +}; + +static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { + { .role = "dbclk", .clk = "gpio4_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { + &omap3xxx_l4_per__gpio4, +}; + +static struct omap_hwmod omap3xxx_gpio4_hwmod = { + .name = "gpio4", + .mpu_irqs = omap3xxx_gpio4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs), + .main_clk = "gpio4_ick", + .opt_clks = gpio4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO4_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, + }, + }, + .slaves = omap3xxx_gpio4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* gpio5 */ +static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { + { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ +}; + +static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { + { .role = "dbclk", .clk = "gpio5_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { + &omap3xxx_l4_per__gpio5, +}; + +static struct omap_hwmod omap3xxx_gpio5_hwmod = { + .name = "gpio5", + .mpu_irqs = omap3xxx_gpio5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs), + .main_clk = "gpio5_ick", + .opt_clks = gpio5_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO5_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, + }, + }, + .slaves = omap3xxx_gpio5_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* gpio6 */ +static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { + { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ +}; + +static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { + { .role = "dbclk", .clk = "gpio6_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { + &omap3xxx_l4_per__gpio6, +}; + +static struct omap_hwmod omap3xxx_gpio6_hwmod = { + .name = "gpio6", + .mpu_irqs = omap3xxx_gpio6_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs), + .main_clk = "gpio6_ick", + .opt_clks = gpio6_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO6_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, + }, + }, + .slaves = omap3xxx_gpio6_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { + .master = &omap3xxx_dma_system_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, + .lch_count = 32, +}; + +static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x002c, + .syss_offs = 0x0028, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { + .name = "dma", + .sysc = &omap3xxx_dma_sysc, +}; + +/* dma_system */ +static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = { + { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ + { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ + { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ + { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ +}; + +static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { + { + .pa_start = 0x48056000, + .pa_end = 0x4a0560ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* dma_system master ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = { + &omap3xxx_dma_system__l3, +}; + +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dma_system_hwmod, + .clk = "core_l4_ick", + .addr = omap3xxx_dma_system_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = { + &omap3xxx_l4_core__dma_system, +}; + +static struct omap_hwmod omap3xxx_dma_system_hwmod = { + .name = "dma", + .class = &omap3xxx_dma_hwmod_class, + .mpu_irqs = omap3xxx_dma_system_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs), + .main_clk = "core_l3_ick", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_ST_SDMA_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, + }, + }, + .slaves = omap3xxx_dma_system_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves), + .masters = omap3xxx_dma_system_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), + .dev_attr = &dma_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .flags = HWMOD_NO_IDLEST, +}; + +/* SR common */ +static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { + .clkact_shift = 20, +}; + +static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { + .sysc_offs = 0x24, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), + .clockact = CLOCKACT_TEST_ICLK, + .sysc_fields = &omap34xx_sr_sysc_fields, +}; + +static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { + .name = "smartreflex", + .sysc = &omap34xx_sr_sysc, + .rev = 1, +}; + +static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { + .sidle_shift = 24, + .enwkup_shift = 26 +}; + +static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { + .sysc_offs = 0x38, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_NO_CACHE), + .sysc_fields = &omap36xx_sr_sysc_fields, +}; + +static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { + .name = "smartreflex", + .sysc = &omap36xx_sr_sysc, + .rev = 2, +}; + +/* SR1 */ +static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { + &omap3_l4_core__sr1, +}; + +static struct omap_hwmod omap34xx_sr1_hwmod = { + .name = "sr1_hwmod", + .class = &omap34xx_smartreflex_hwmod_class, + .main_clk = "sr1_fck", + .vdd_name = "mpu", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SR1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, + }, + }, + .slaves = omap3_sr1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 | + CHIP_IS_OMAP3430ES3_0 | + CHIP_IS_OMAP3430ES3_1), + .flags = HWMOD_SET_DEFAULT_CLOCKACT, +}; + +static struct omap_hwmod omap36xx_sr1_hwmod = { + .name = "sr1_hwmod", + .class = &omap36xx_smartreflex_hwmod_class, + .main_clk = "sr1_fck", + .vdd_name = "mpu", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SR1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, + }, + }, + .slaves = omap3_sr1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), +}; + +/* SR2 */ +static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { + &omap3_l4_core__sr2, +}; + +static struct omap_hwmod omap34xx_sr2_hwmod = { + .name = "sr2_hwmod", + .class = &omap34xx_smartreflex_hwmod_class, + .main_clk = "sr2_fck", + .vdd_name = "core", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SR2_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, + }, + }, + .slaves = omap3_sr2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 | + CHIP_IS_OMAP3430ES3_0 | + CHIP_IS_OMAP3430ES3_1), + .flags = HWMOD_SET_DEFAULT_CLOCKACT, +}; + +static struct omap_hwmod omap36xx_sr2_hwmod = { + .name = "sr2_hwmod", + .class = &omap36xx_smartreflex_hwmod_class, + .main_clk = "sr2_fck", + .vdd_name = "core", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SR2_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, + }, + }, + .slaves = omap3_sr2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, @@ -521,6 +1368,25 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_uart2_hwmod, &omap3xxx_uart3_hwmod, &omap3xxx_uart4_hwmod, + &omap3xxx_i2c1_hwmod, + &omap3xxx_i2c2_hwmod, + &omap3xxx_i2c3_hwmod, + &omap34xx_sr1_hwmod, + &omap34xx_sr2_hwmod, + &omap36xx_sr1_hwmod, + &omap36xx_sr2_hwmod, + + + /* gpio class */ + &omap3xxx_gpio1_hwmod, + &omap3xxx_gpio2_hwmod, + &omap3xxx_gpio3_hwmod, + &omap3xxx_gpio4_hwmod, + &omap3xxx_gpio5_hwmod, + &omap3xxx_gpio6_hwmod, + + /* dma_system class*/ + &omap3xxx_dma_system_hwmod, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 7274db4de487..c2806bd11fbf 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -22,11 +22,16 @@ #include <plat/omap_hwmod.h> #include <plat/cpu.h> +#include <plat/gpio.h> +#include <plat/dma.h> #include "omap_hwmod_common_data.h" -#include "cm.h" +#include "cm1_44xx.h" +#include "cm2_44xx.h" +#include "prm44xx.h" #include "prm-regbits-44xx.h" +#include "wd_timer.h" /* Base offset for all OMAP4 interrupts external to MPUSS */ #define OMAP44XX_IRQ_GIC_START 32 @@ -35,8 +40,11 @@ #define OMAP44XX_DMA_REQ_START 1 /* Backward references (IPs with Bus Master capability) */ +static struct omap_hwmod omap44xx_dma_system_hwmod; static struct omap_hwmod omap44xx_dmm_hwmod; +static struct omap_hwmod omap44xx_dsp_hwmod; static struct omap_hwmod omap44xx_emif_fw_hwmod; +static struct omap_hwmod omap44xx_iva_hwmod; static struct omap_hwmod omap44xx_l3_instr_hwmod; static struct omap_hwmod omap44xx_l3_main_1_hwmod; static struct omap_hwmod omap44xx_l3_main_2_hwmod; @@ -58,7 +66,7 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod; * instance(s): dmm */ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { - .name = "dmm", + .name = "dmm", }; /* dmm interface data */ @@ -67,7 +75,15 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { .master = &omap44xx_l3_main_1_hwmod, .slave = &omap44xx_dmm_hwmod, .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { + { + .pa_start = 0x4e000000, + .pa_end = 0x4e0007ff, + .flags = ADDR_TYPE_RT + }, }; /* mpu -> dmm */ @@ -75,7 +91,9 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { .master = &omap44xx_mpu_hwmod, .slave = &omap44xx_dmm_hwmod, .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, + .addr = omap44xx_dmm_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs), + .user = OCP_USER_MPU, }; /* dmm slave ports */ @@ -103,7 +121,7 @@ static struct omap_hwmod omap44xx_dmm_hwmod = { * instance(s): emif_fw */ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { - .name = "emif_fw", + .name = "emif_fw", }; /* emif_fw interface data */ @@ -115,12 +133,22 @@ static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { + { + .pa_start = 0x4a20c000, + .pa_end = 0x4a20c0ff, + .flags = ADDR_TYPE_RT + }, +}; + /* l4_cfg -> emif_fw */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_emif_fw_hwmod, .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, + .addr = omap44xx_emif_fw_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs), + .user = OCP_USER_MPU, }; /* emif_fw slave ports */ @@ -142,10 +170,18 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = { * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 */ static struct omap_hwmod_class omap44xx_l3_hwmod_class = { - .name = "l3", + .name = "l3", }; /* l3_instr interface data */ +/* iva -> l3_instr */ +static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { + .master = &omap44xx_iva_hwmod, + .slave = &omap44xx_l3_instr_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_3 -> l3_instr */ static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { .master = &omap44xx_l3_main_3_hwmod, @@ -156,6 +192,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { /* l3_instr slave ports */ static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { + &omap44xx_iva__l3_instr, &omap44xx_l3_main_3__l3_instr, }; @@ -167,6 +204,15 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* l3_main_1 interface data */ +/* dsp -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_2 -> l3_main_1 */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { .master = &omap44xx_l3_main_2_hwmod, @@ -193,6 +239,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { /* l3_main_1 slave ports */ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { + &omap44xx_dsp__l3_main_1, &omap44xx_l3_main_2__l3_main_1, &omap44xx_l4_cfg__l3_main_1, &omap44xx_mpu__l3_main_1, @@ -207,6 +254,22 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = { }; /* l3_main_2 interface data */ +/* dma_system -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { + .master = &omap44xx_dma_system_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* iva -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { + .master = &omap44xx_iva_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_1 -> l3_main_2 */ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { .master = &omap44xx_l3_main_1_hwmod, @@ -225,6 +288,8 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { /* l3_main_2 slave ports */ static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { + &omap44xx_dma_system__l3_main_2, + &omap44xx_iva__l3_main_2, &omap44xx_l3_main_1__l3_main_2, &omap44xx_l4_cfg__l3_main_2, }; @@ -282,10 +347,18 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = { * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup */ static struct omap_hwmod_class omap44xx_l4_hwmod_class = { - .name = "l4", + .name = "l4", }; /* l4_abe interface data */ +/* dsp -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_1 -> l4_abe */ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { .master = &omap44xx_l3_main_1_hwmod, @@ -304,6 +377,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { /* l4_abe slave ports */ static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { + &omap44xx_dsp__l4_abe, &omap44xx_l3_main_1__l4_abe, &omap44xx_mpu__l4_abe, }; @@ -387,7 +461,7 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = { * instance(s): mpu_private */ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { - .name = "mpu_bus", + .name = "mpu_bus", }; /* mpu_private interface data */ @@ -413,12 +487,960 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { }; /* + * Modules omap_hwmod structures + * + * The following IPs are excluded for the moment because: + * - They do not need an explicit SW control using omap_hwmod API. + * - They still need to be validated with the driver + * properly adapted to omap_hwmod / omap_device + * + * aess + * bandgap + * c2c + * c2c_target_fw + * cm_core + * cm_core_aon + * counter_32k + * ctrl_module_core + * ctrl_module_pad_core + * ctrl_module_pad_wkup + * ctrl_module_wkup + * debugss + * dmic + * dss + * dss_dispc + * dss_dsi1 + * dss_dsi2 + * dss_hdmi + * dss_rfbi + * dss_venc + * efuse_ctrl_cust + * efuse_ctrl_std + * elm + * emif1 + * emif2 + * fdif + * gpmc + * gpu + * hdq1w + * hsi + * ipu + * iss + * kbd + * mailbox + * mcasp + * mcbsp1 + * mcbsp2 + * mcbsp3 + * mcbsp4 + * mcpdm + * mcspi1 + * mcspi2 + * mcspi3 + * mcspi4 + * mmc1 + * mmc2 + * mmc3 + * mmc4 + * mmc5 + * mpu_c0 + * mpu_c1 + * ocmc_ram + * ocp2scp_usb_phy + * ocp_wp_noc + * prcm + * prcm_mpu + * prm + * scrm + * sl2if + * slimbus1 + * slimbus2 + * spinlock + * timer1 + * timer10 + * timer11 + * timer2 + * timer3 + * timer4 + * timer5 + * timer6 + * timer7 + * timer8 + * timer9 + * usb_host_fs + * usb_host_hs + * usb_otg_hs + * usb_phy_cm + * usb_tll_hs + * usim + */ + +/* + * 'dma' class + * dma controller for data exchange between memory to memory (i.e. internal or + * external memory) and gp peripherals to memory or memory to gp peripherals + */ + +static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x002c, + .syss_offs = 0x0028, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_dma_hwmod_class = { + .name = "dma", + .sysc = &omap44xx_dma_sysc, +}; + +/* dma dev_attr */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, + .lch_count = 32, +}; + +/* dma_system */ +static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { + { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, + { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, + { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, + { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, +}; + +/* dma_system master ports */ +static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = { + &omap44xx_dma_system__l3_main_2, +}; + +static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { + { + .pa_start = 0x4a056000, + .pa_end = 0x4a0560ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_dma_system_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dma_system_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = { + &omap44xx_l4_cfg__dma_system, +}; + +static struct omap_hwmod omap44xx_dma_system_hwmod = { + .name = "dma_system", + .class = &omap44xx_dma_hwmod_class, + .mpu_irqs = omap44xx_dma_system_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs), + .main_clk = "l3_div_ck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL, + }, + }, + .dev_attr = &dma_dev_attr, + .slaves = omap44xx_dma_system_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves), + .masters = omap44xx_dma_system_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'dsp' class + * dsp sub-system + */ + +static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { + .name = "dsp", +}; + +/* dsp */ +static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { + { .irq = 28 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { + { .name = "mmu_cache", .rst_shift = 1 }, +}; + +static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = { + { .name = "dsp", .rst_shift = 0 }, +}; + +/* dsp -> iva */ +static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_iva_hwmod, + .clk = "dpll_iva_m5x2_ck", +}; + +/* dsp master ports */ +static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = { + &omap44xx_dsp__l3_main_1, + &omap44xx_dsp__l4_abe, + &omap44xx_dsp__iva, +}; + +/* l4_cfg -> dsp */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_dsp_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dsp slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = { + &omap44xx_l4_cfg__dsp, +}; + +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod omap44xx_dsp_c0_hwmod = { + .name = "dsp_c0", + .class = &omap44xx_dsp_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, + .rst_lines = omap44xx_dsp_c0_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets), + .prcm = { + .omap4 = { + .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL, + }, + }, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct omap_hwmod omap44xx_dsp_hwmod = { + .name = "dsp", + .class = &omap44xx_dsp_hwmod_class, + .mpu_irqs = omap44xx_dsp_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs), + .rst_lines = omap44xx_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), + .main_clk = "dsp_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, + .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL, + }, + }, + .slaves = omap44xx_dsp_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves), + .masters = omap44xx_dsp_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'gpio' class + * general purpose io module + */ + +static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0114, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { + .name = "gpio", + .sysc = &omap44xx_gpio_sysc, + .rev = 2, +}; + +/* gpio dev_attr */ +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = true, +}; + +/* gpio1 */ +static struct omap_hwmod omap44xx_gpio1_hwmod; +static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { + { .irq = 29 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { + { + .pa_start = 0x4a310000, + .pa_end = 0x4a3101ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_gpio1_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_gpio1_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { + &omap44xx_l4_wkup__gpio1, +}; + +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { + { .role = "dbclk", .clk = "gpio1_dbclk" }, +}; + +static struct omap_hwmod omap44xx_gpio1_hwmod = { + .name = "gpio1", + .class = &omap44xx_gpio_hwmod_class, + .mpu_irqs = omap44xx_gpio1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs), + .main_clk = "gpio1_ick", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, + }, + }, + .opt_clks = gpio1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), + .dev_attr = &gpio_dev_attr, + .slaves = omap44xx_gpio1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* gpio2 */ +static struct omap_hwmod omap44xx_gpio2_hwmod; +static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { + { .irq = 30 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { + { + .pa_start = 0x48055000, + .pa_end = 0x480551ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> gpio2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { + &omap44xx_l4_per__gpio2, +}; + +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { + { .role = "dbclk", .clk = "gpio2_dbclk" }, +}; + +static struct omap_hwmod omap44xx_gpio2_hwmod = { + .name = "gpio2", + .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap44xx_gpio2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs), + .main_clk = "gpio2_ick", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, + }, + }, + .opt_clks = gpio2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), + .dev_attr = &gpio_dev_attr, + .slaves = omap44xx_gpio2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* gpio3 */ +static struct omap_hwmod omap44xx_gpio3_hwmod; +static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { + { .irq = 31 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { + { + .pa_start = 0x48057000, + .pa_end = 0x480571ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> gpio3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio3_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { + &omap44xx_l4_per__gpio3, +}; + +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { + { .role = "dbclk", .clk = "gpio3_dbclk" }, +}; + +static struct omap_hwmod omap44xx_gpio3_hwmod = { + .name = "gpio3", + .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap44xx_gpio3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs), + .main_clk = "gpio3_ick", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, + }, + }, + .opt_clks = gpio3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), + .dev_attr = &gpio_dev_attr, + .slaves = omap44xx_gpio3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* gpio4 */ +static struct omap_hwmod omap44xx_gpio4_hwmod; +static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { + { .irq = 32 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { + { + .pa_start = 0x48059000, + .pa_end = 0x480591ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> gpio4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio4_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { + &omap44xx_l4_per__gpio4, +}; + +static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { + { .role = "dbclk", .clk = "gpio4_dbclk" }, +}; + +static struct omap_hwmod omap44xx_gpio4_hwmod = { + .name = "gpio4", + .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap44xx_gpio4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs), + .main_clk = "gpio4_ick", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, + }, + }, + .opt_clks = gpio4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), + .dev_attr = &gpio_dev_attr, + .slaves = omap44xx_gpio4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* gpio5 */ +static struct omap_hwmod omap44xx_gpio5_hwmod; +static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { + { .irq = 33 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { + { + .pa_start = 0x4805b000, + .pa_end = 0x4805b1ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> gpio5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio5_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio5_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio5 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { + &omap44xx_l4_per__gpio5, +}; + +static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { + { .role = "dbclk", .clk = "gpio5_dbclk" }, +}; + +static struct omap_hwmod omap44xx_gpio5_hwmod = { + .name = "gpio5", + .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap44xx_gpio5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs), + .main_clk = "gpio5_ick", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, + }, + }, + .opt_clks = gpio5_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), + .dev_attr = &gpio_dev_attr, + .slaves = omap44xx_gpio5_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* gpio6 */ +static struct omap_hwmod omap44xx_gpio6_hwmod; +static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { + { .irq = 34 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { + { + .pa_start = 0x4805d000, + .pa_end = 0x4805d1ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> gpio6 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio6_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio6_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio6 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { + &omap44xx_l4_per__gpio6, +}; + +static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { + { .role = "dbclk", .clk = "gpio6_dbclk" }, +}; + +static struct omap_hwmod omap44xx_gpio6_hwmod = { + .name = "gpio6", + .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap44xx_gpio6_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs), + .main_clk = "gpio6_ick", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, + }, + }, + .opt_clks = gpio6_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), + .dev_attr = &gpio_dev_attr, + .slaves = omap44xx_gpio6_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'i2c' class + * multimaster high-speed i2c controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { + .sysc_offs = 0x0010, + .syss_offs = 0x0090, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { + .name = "i2c", + .sysc = &omap44xx_i2c_sysc, +}; + +/* i2c1 */ +static struct omap_hwmod omap44xx_i2c1_hwmod; +static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { + { .irq = 56 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { + { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { + { + .pa_start = 0x48070000, + .pa_end = 0x480700ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> i2c1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c1_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* i2c1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { + &omap44xx_l4_per__i2c1, +}; + +static struct omap_hwmod omap44xx_i2c1_hwmod = { + .name = "i2c1", + .class = &omap44xx_i2c_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, + .mpu_irqs = omap44xx_i2c1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs), + .sdma_reqs = omap44xx_i2c1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs), + .main_clk = "i2c1_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, + }, + }, + .slaves = omap44xx_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* i2c2 */ +static struct omap_hwmod omap44xx_i2c2_hwmod; +static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { + { .irq = 57 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { + { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { + { + .pa_start = 0x48072000, + .pa_end = 0x480720ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> i2c2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* i2c2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { + &omap44xx_l4_per__i2c2, +}; + +static struct omap_hwmod omap44xx_i2c2_hwmod = { + .name = "i2c2", + .class = &omap44xx_i2c_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, + .mpu_irqs = omap44xx_i2c2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs), + .sdma_reqs = omap44xx_i2c2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs), + .main_clk = "i2c2_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, + }, + }, + .slaves = omap44xx_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* i2c3 */ +static struct omap_hwmod omap44xx_i2c3_hwmod; +static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { + { .irq = 61 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { + { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { + { + .pa_start = 0x48060000, + .pa_end = 0x480600ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> i2c3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c3_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* i2c3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { + &omap44xx_l4_per__i2c3, +}; + +static struct omap_hwmod omap44xx_i2c3_hwmod = { + .name = "i2c3", + .class = &omap44xx_i2c_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, + .mpu_irqs = omap44xx_i2c3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs), + .sdma_reqs = omap44xx_i2c3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs), + .main_clk = "i2c3_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, + }, + }, + .slaves = omap44xx_i2c3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* i2c4 */ +static struct omap_hwmod omap44xx_i2c4_hwmod; +static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { + { .irq = 62 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { + { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { + { + .pa_start = 0x48350000, + .pa_end = 0x483500ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> i2c4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c4_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* i2c4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { + &omap44xx_l4_per__i2c4, +}; + +static struct omap_hwmod omap44xx_i2c4_hwmod = { + .name = "i2c4", + .class = &omap44xx_i2c_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, + .mpu_irqs = omap44xx_i2c4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs), + .sdma_reqs = omap44xx_i2c4_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs), + .main_clk = "i2c4_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, + }, + }, + .slaves = omap44xx_i2c4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'iva' class + * multi-standard video encoder/decoder hardware accelerator + */ + +static struct omap_hwmod_class omap44xx_iva_hwmod_class = { + .name = "iva", +}; + +/* iva */ +static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { + { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, + { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, + { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { + { .name = "logic", .rst_shift = 2 }, +}; + +static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = { + { .name = "seq0", .rst_shift = 0 }, +}; + +static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = { + { .name = "seq1", .rst_shift = 1 }, +}; + +/* iva master ports */ +static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = { + &omap44xx_iva__l3_main_2, + &omap44xx_iva__l3_instr, +}; + +static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { + { + .pa_start = 0x5a000000, + .pa_end = 0x5a07ffff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l3_main_2 -> iva */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_iva_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_iva_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs), + .user = OCP_USER_MPU, +}; + +/* iva slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = { + &omap44xx_dsp__iva, + &omap44xx_l3_main_2__iva, +}; + +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod omap44xx_iva_seq0_hwmod = { + .name = "iva_seq0", + .class = &omap44xx_iva_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, + .rst_lines = omap44xx_iva_seq0_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets), + .prcm = { + .omap4 = { + .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, + }, + }, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod omap44xx_iva_seq1_hwmod = { + .name = "iva_seq1", + .class = &omap44xx_iva_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, + .rst_lines = omap44xx_iva_seq1_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets), + .prcm = { + .omap4 = { + .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, + }, + }, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct omap_hwmod omap44xx_iva_hwmod = { + .name = "iva", + .class = &omap44xx_iva_hwmod_class, + .mpu_irqs = omap44xx_iva_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs), + .rst_lines = omap44xx_iva_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), + .main_clk = "iva_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, + .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, + }, + }, + .slaves = omap44xx_iva_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves), + .masters = omap44xx_iva_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* * 'mpu' class * mpu sub-system */ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { - .name = "mpu", + .name = "mpu", }; /* mpu */ @@ -453,58 +1475,189 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { }; /* - * 'wd_timer' class - * 32-bit watchdog upward counter that generates a pulse on the reset pin on - * overflow condition + * 'smartreflex' class + * smartreflex module (monitor silicon performance and outputs a measure of + * performance error) */ -static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | - SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +/* The IP is not compliant to type1 / type2 scheme */ +static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { + .sidle_shift = 24, + .enwkup_shift = 26, }; -/* - * 'uart' class - * universal asynchronous receiver/transmitter (uart) - */ +static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { + .sysc_offs = 0x0038, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type_smartreflex, +}; -static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { - .rev_offs = 0x0050, - .sysc_offs = 0x0054, - .syss_offs = 0x0058, - .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { + .name = "smartreflex", + .sysc = &omap44xx_smartreflex_sysc, + .rev = 2, }; -static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { - .name = "wd_timer", - .sysc = &omap44xx_wd_timer_sysc, +/* smartreflex_core */ +static struct omap_hwmod omap44xx_smartreflex_core_hwmod; +static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { + { .irq = 19 + OMAP44XX_IRQ_GIC_START }, }; -/* wd_timer2 */ -static struct omap_hwmod omap44xx_wd_timer2_hwmod; -static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { - { .irq = 80 + OMAP44XX_IRQ_GIC_START }, +static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { + { + .pa_start = 0x4a0dd000, + .pa_end = 0x4a0dd03f, + .flags = ADDR_TYPE_RT + }, }; -static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { +/* l4_cfg -> smartreflex_core */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_smartreflex_core_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_smartreflex_core_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* smartreflex_core slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { + &omap44xx_l4_cfg__smartreflex_core, +}; + +static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { + .name = "smartreflex_core", + .class = &omap44xx_smartreflex_hwmod_class, + .mpu_irqs = omap44xx_smartreflex_core_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs), + .main_clk = "smartreflex_core_fck", + .vdd_name = "core", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, + }, + }, + .slaves = omap44xx_smartreflex_core_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* smartreflex_iva */ +static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; +static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { + { .irq = 102 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { { - .pa_start = 0x4a314000, - .pa_end = 0x4a31407f, + .pa_start = 0x4a0db000, + .pa_end = 0x4a0db03f, .flags = ADDR_TYPE_RT }, }; +/* l4_cfg -> smartreflex_iva */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_smartreflex_iva_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_smartreflex_iva_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* smartreflex_iva slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = { + &omap44xx_l4_cfg__smartreflex_iva, +}; + +static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { + .name = "smartreflex_iva", + .class = &omap44xx_smartreflex_hwmod_class, + .mpu_irqs = omap44xx_smartreflex_iva_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs), + .main_clk = "smartreflex_iva_fck", + .vdd_name = "iva", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, + }, + }, + .slaves = omap44xx_smartreflex_iva_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* smartreflex_mpu */ +static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; +static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { + { .irq = 18 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { + { + .pa_start = 0x4a0d9000, + .pa_end = 0x4a0d903f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_cfg -> smartreflex_mpu */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_smartreflex_mpu_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_smartreflex_mpu_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* smartreflex_mpu slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = { + &omap44xx_l4_cfg__smartreflex_mpu, +}; + +static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { + .name = "smartreflex_mpu", + .class = &omap44xx_smartreflex_hwmod_class, + .mpu_irqs = omap44xx_smartreflex_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs), + .main_clk = "smartreflex_mpu_fck", + .vdd_name = "mpu", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, + }, + }, + .slaves = omap44xx_smartreflex_mpu_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'uart' class + * universal asynchronous receiver/transmitter (uart) + */ + +static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { + .rev_offs = 0x0050, + .sysc_offs = 0x0054, + .syss_offs = 0x0058, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + static struct omap_hwmod_class omap44xx_uart_hwmod_class = { - .name = "uart", - .sysc = &omap44xx_uart_sysc, + .name = "uart", + .sysc = &omap44xx_uart_sysc, }; /* uart1 */ @@ -578,51 +1731,6 @@ static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { }, }; -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_wd_timer2_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_wd_timer2_addrs, - .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* wd_timer2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { - &omap44xx_l4_wkup__wd_timer2, -}; - -static struct omap_hwmod omap44xx_wd_timer2_hwmod = { - .name = "wd_timer2", - .class = &omap44xx_wd_timer_hwmod_class, - .mpu_irqs = omap44xx_wd_timer2_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs), - .main_clk = "wd_timer2_fck", - .prcm = { - .omap4 = { - .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, - }, - }, - .slaves = omap44xx_wd_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - -/* wd_timer3 */ -static struct omap_hwmod omap44xx_wd_timer3_hwmod; -static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { - { .irq = 36 + OMAP44XX_IRQ_GIC_START }, -}; - -static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { - { - .pa_start = 0x40130000, - .pa_end = 0x4013007f, - .flags = ADDR_TYPE_RT - }, -}; - /* l4_per -> uart2 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { .master = &omap44xx_l4_per_hwmod, @@ -675,25 +1783,6 @@ static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { }, }; -/* l4_abe -> wd_timer3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_wd_timer3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_wd_timer3_addrs, - .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs), - .user = OCP_USER_MPU, -}; - -/* l4_abe -> wd_timer3 (dma) */ -static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { - { - .pa_start = 0x49030000, - .pa_end = 0x4903007f, - .flags = ADDR_TYPE_RT - }, -}; - /* l4_per -> uart3 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { .master = &omap44xx_l4_per_hwmod, @@ -747,37 +1836,6 @@ static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { }, }; -static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_wd_timer3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_wd_timer3_dma_addrs, - .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs), - .user = OCP_USER_SDMA, -}; - -/* wd_timer3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { - &omap44xx_l4_abe__wd_timer3, - &omap44xx_l4_abe__wd_timer3_dma, -}; - -static struct omap_hwmod omap44xx_wd_timer3_hwmod = { - .name = "wd_timer3", - .class = &omap44xx_wd_timer_hwmod_class, - .mpu_irqs = omap44xx_wd_timer3_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs), - .main_clk = "wd_timer3_fck", - .prcm = { - .omap4 = { - .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, - }, - }, - .slaves = omap44xx_wd_timer3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -}; - /* l4_per -> uart4 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { .master = &omap44xx_l4_per_hwmod, @@ -811,35 +1869,205 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition + */ + +static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &omap44xx_wd_timer_sysc, + .pre_shutdown = &omap2_wd_timer_disable, +}; + +/* wd_timer2 */ +static struct omap_hwmod omap44xx_wd_timer2_hwmod; +static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { + { .irq = 80 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { + { + .pa_start = 0x4a314000, + .pa_end = 0x4a31407f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_wd_timer2_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_wd_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* wd_timer2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { + &omap44xx_l4_wkup__wd_timer2, +}; + +static struct omap_hwmod omap44xx_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap44xx_wd_timer_hwmod_class, + .mpu_irqs = omap44xx_wd_timer2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs), + .main_clk = "wd_timer2_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, + }, + }, + .slaves = omap44xx_wd_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* wd_timer3 */ +static struct omap_hwmod omap44xx_wd_timer3_hwmod; +static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { + { .irq = 36 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { + { + .pa_start = 0x40130000, + .pa_end = 0x4013007f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> wd_timer3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_wd_timer3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_wd_timer3_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { + { + .pa_start = 0x49030000, + .pa_end = 0x4903007f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> wd_timer3 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_wd_timer3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_wd_timer3_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* wd_timer3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { + &omap44xx_l4_abe__wd_timer3, + &omap44xx_l4_abe__wd_timer3_dma, +}; + +static struct omap_hwmod omap44xx_wd_timer3_hwmod = { + .name = "wd_timer3", + .class = &omap44xx_wd_timer_hwmod_class, + .mpu_irqs = omap44xx_wd_timer3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs), + .main_clk = "wd_timer3_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, + }, + }, + .slaves = omap44xx_wd_timer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + static __initdata struct omap_hwmod *omap44xx_hwmods[] = { + /* dmm class */ &omap44xx_dmm_hwmod, + /* emif_fw class */ &omap44xx_emif_fw_hwmod, + /* l3 class */ &omap44xx_l3_instr_hwmod, &omap44xx_l3_main_1_hwmod, &omap44xx_l3_main_2_hwmod, &omap44xx_l3_main_3_hwmod, + /* l4 class */ &omap44xx_l4_abe_hwmod, &omap44xx_l4_cfg_hwmod, &omap44xx_l4_per_hwmod, &omap44xx_l4_wkup_hwmod, + /* mpu_bus class */ &omap44xx_mpu_private_hwmod, + /* dma class */ + &omap44xx_dma_system_hwmod, + + /* dsp class */ + &omap44xx_dsp_hwmod, + &omap44xx_dsp_c0_hwmod, + + /* gpio class */ + &omap44xx_gpio1_hwmod, + &omap44xx_gpio2_hwmod, + &omap44xx_gpio3_hwmod, + &omap44xx_gpio4_hwmod, + &omap44xx_gpio5_hwmod, + &omap44xx_gpio6_hwmod, + + /* i2c class */ + &omap44xx_i2c1_hwmod, + &omap44xx_i2c2_hwmod, + &omap44xx_i2c3_hwmod, + &omap44xx_i2c4_hwmod, + + /* iva class */ + &omap44xx_iva_hwmod, + &omap44xx_iva_seq0_hwmod, + &omap44xx_iva_seq1_hwmod, + /* mpu class */ &omap44xx_mpu_hwmod, - /* wd_timer class */ - &omap44xx_wd_timer2_hwmod, - &omap44xx_wd_timer3_hwmod, + + /* smartreflex class */ + &omap44xx_smartreflex_core_hwmod, + &omap44xx_smartreflex_iva_hwmod, + &omap44xx_smartreflex_mpu_hwmod, /* uart class */ &omap44xx_uart1_hwmod, &omap44xx_uart2_hwmod, &omap44xx_uart3_hwmod, &omap44xx_uart4_hwmod, + + /* wd_timer class */ + &omap44xx_wd_timer2_hwmod, + &omap44xx_wd_timer3_hwmod, + NULL, }; diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h new file mode 100644 index 000000000000..46ac27dd6c84 --- /dev/null +++ b/arch/arm/mach-omap2/omap_opp_data.h @@ -0,0 +1,72 @@ +/* + * OMAP SoC specific OPP Data helpers + * + * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/ + * Nishanth Menon + * Kevin Hilman + * Copyright (C) 2010 Nokia Corporation. + * Eduardo Valentin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H +#define __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H + +#include <plat/omap_hwmod.h> + +/* + * *BIG FAT WARNING*: + * USE the following ONLY in opp data initialization common to an SoC. + * DO NOT USE these in board files/pm core etc. + */ + +/** + * struct omap_opp_def - OMAP OPP Definition + * @hwmod_name: Name of the hwmod for this domain + * @freq: Frequency in hertz corresponding to this OPP + * @u_volt: Nominal voltage in microvolts corresponding to this OPP + * @default_available: True/false - is this OPP available by default + * + * OMAP SOCs have a standard set of tuples consisting of frequency and voltage + * pairs that the device will support per voltage domain. This is called + * Operating Points or OPP. The actual definitions of OMAP Operating Points + * varies over silicon within the same family of devices. For a specific + * domain, you can have a set of {frequency, voltage} pairs and this is denoted + * by an array of omap_opp_def. As the kernel boots and more information is + * available, a set of these are activated based on the precise nature of + * device the kernel boots up on. It is interesting to remember that each IP + * which belongs to a voltage domain may define their own set of OPPs on top + * of this - but this is handled by the appropriate driver. + */ +struct omap_opp_def { + char *hwmod_name; + + unsigned long freq; + unsigned long u_volt; + + bool default_available; +}; + +/* + * Initialization wrapper used to define an OPP for OMAP variants. + */ +#define OPP_INITIALIZER(_hwmod_name, _enabled, _freq, _uv) \ +{ \ + .hwmod_name = _hwmod_name, \ + .default_available = _enabled, \ + .freq = _freq, \ + .u_volt = _uv, \ +} + +/* Use this to initialize the default table */ +extern int __init omap_init_opp_table(struct omap_opp_def *opp_def, + u32 opp_def_size); + +#endif /* __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H */ diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c new file mode 100644 index 000000000000..745252c60e32 --- /dev/null +++ b/arch/arm/mach-omap2/omap_phy_internal.c @@ -0,0 +1,149 @@ +/* + * This file configures the internal USB PHY in OMAP4430. Used + * with TWL6030 transceiver and MUSB on OMAP4430. + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Author: Hema HK <hemahk@ti.com> + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/types.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/usb.h> + +#include <plat/usb.h> + +/* OMAP control module register for UTMI PHY */ +#define CONTROL_DEV_CONF 0x300 +#define PHY_PD 0x1 + +#define USBOTGHS_CONTROL 0x33c +#define AVALID BIT(0) +#define BVALID BIT(1) +#define VBUSVALID BIT(2) +#define SESSEND BIT(3) +#define IDDIG BIT(4) + +static struct clk *phyclk, *clk48m, *clk32k; +static void __iomem *ctrl_base; + +int omap4430_phy_init(struct device *dev) +{ + ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K); + if (!ctrl_base) { + dev_err(dev, "control module ioremap failed\n"); + return -ENOMEM; + } + /* Power down the phy */ + __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF); + phyclk = clk_get(dev, "ocp2scp_usb_phy_ick"); + + if (IS_ERR(phyclk)) { + dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n"); + iounmap(ctrl_base); + return PTR_ERR(phyclk); + } + + clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m"); + if (IS_ERR(clk48m)) { + dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n"); + clk_put(phyclk); + iounmap(ctrl_base); + return PTR_ERR(clk48m); + } + + clk32k = clk_get(dev, "usb_phy_cm_clk32k"); + if (IS_ERR(clk32k)) { + dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n"); + clk_put(phyclk); + clk_put(clk48m); + iounmap(ctrl_base); + return PTR_ERR(clk32k); + } + return 0; +} + +int omap4430_phy_set_clk(struct device *dev, int on) +{ + static int state; + + if (on && !state) { + /* Enable the phy clocks */ + clk_enable(phyclk); + clk_enable(clk48m); + clk_enable(clk32k); + state = 1; + } else if (state) { + /* Disable the phy clocks */ + clk_disable(phyclk); + clk_disable(clk48m); + clk_disable(clk32k); + state = 0; + } + return 0; +} + +int omap4430_phy_power(struct device *dev, int ID, int on) +{ + if (on) { + /* enabled the clocks */ + omap4430_phy_set_clk(dev, 1); + /* power on the phy */ + if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) { + __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF); + mdelay(200); + } + if (ID) + /* enable VBUS valid, IDDIG groung */ + __raw_writel(AVALID | VBUSVALID, ctrl_base + + USBOTGHS_CONTROL); + else + /* + * Enable VBUS Valid, AValid and IDDIG + * high impedence + */ + __raw_writel(IDDIG | AVALID | VBUSVALID, + ctrl_base + USBOTGHS_CONTROL); + } else { + /* Enable session END and IDIG to high impedence. */ + __raw_writel(SESSEND | IDDIG, ctrl_base + + USBOTGHS_CONTROL); + /* Disable the clocks */ + omap4430_phy_set_clk(dev, 0); + /* Power down the phy */ + __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF); + } + + return 0; +} + +int omap4430_phy_exit(struct device *dev) +{ + if (ctrl_base) + iounmap(ctrl_base); + if (phyclk) + clk_put(phyclk); + if (clk48m) + clk_put(clk48m); + if (clk32k) + clk_put(clk32k); + + return 0; +} diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c new file mode 100644 index 000000000000..15f8c6c1bb0f --- /dev/null +++ b/arch/arm/mach-omap2/omap_twl.c @@ -0,0 +1,277 @@ +/** + * OMAP and TWL PMIC specific intializations. + * + * Copyright (C) 2010 Texas Instruments Incorporated. + * Thara Gopinath + * Copyright (C) 2009 Texas Instruments Incorporated. + * Nishanth Menon + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/i2c/twl.h> + +#include <plat/voltage.h> + +#define OMAP3_SRI2C_SLAVE_ADDR 0x12 +#define OMAP3_VDD_MPU_SR_CONTROL_REG 0x00 +#define OMAP3_VDD_CORE_SR_CONTROL_REG 0x01 +#define OMAP3_VP_CONFIG_ERROROFFSET 0x00 +#define OMAP3_VP_VSTEPMIN_VSTEPMIN 0x1 +#define OMAP3_VP_VSTEPMAX_VSTEPMAX 0x04 +#define OMAP3_VP_VLIMITTO_TIMEOUT_US 200 + +#define OMAP3430_VP1_VLIMITTO_VDDMIN 0x14 +#define OMAP3430_VP1_VLIMITTO_VDDMAX 0x42 +#define OMAP3430_VP2_VLIMITTO_VDDMIN 0x18 +#define OMAP3430_VP2_VLIMITTO_VDDMAX 0x2c + +#define OMAP3630_VP1_VLIMITTO_VDDMIN 0x18 +#define OMAP3630_VP1_VLIMITTO_VDDMAX 0x3c +#define OMAP3630_VP2_VLIMITTO_VDDMIN 0x18 +#define OMAP3630_VP2_VLIMITTO_VDDMAX 0x30 + +#define OMAP4_SRI2C_SLAVE_ADDR 0x12 +#define OMAP4_VDD_MPU_SR_VOLT_REG 0x55 +#define OMAP4_VDD_IVA_SR_VOLT_REG 0x5B +#define OMAP4_VDD_CORE_SR_VOLT_REG 0x61 + +#define OMAP4_VP_CONFIG_ERROROFFSET 0x00 +#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01 +#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04 +#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200 + +#define OMAP4_VP_MPU_VLIMITTO_VDDMIN 0xA +#define OMAP4_VP_MPU_VLIMITTO_VDDMAX 0x39 +#define OMAP4_VP_IVA_VLIMITTO_VDDMIN 0xA +#define OMAP4_VP_IVA_VLIMITTO_VDDMAX 0x2D +#define OMAP4_VP_CORE_VLIMITTO_VDDMIN 0xA +#define OMAP4_VP_CORE_VLIMITTO_VDDMAX 0x28 + +static bool is_offset_valid; +static u8 smps_offset; + +#define REG_SMPS_OFFSET 0xE0 + +unsigned long twl4030_vsel_to_uv(const u8 vsel) +{ + return (((vsel * 125) + 6000)) * 100; +} + +u8 twl4030_uv_to_vsel(unsigned long uv) +{ + return DIV_ROUND_UP(uv - 600000, 12500); +} + +unsigned long twl6030_vsel_to_uv(const u8 vsel) +{ + /* + * In TWL6030 depending on the value of SMPS_OFFSET + * efuse register the voltage range supported in + * standard mode can be either between 0.6V - 1.3V or + * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse + * is programmed to all 0's where as starting from + * TWL6030 ES1.1 the efuse is programmed to 1 + */ + if (!is_offset_valid) { + twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset, + REG_SMPS_OFFSET); + is_offset_valid = true; + } + + /* + * There is no specific formula for voltage to vsel + * conversion above 1.3V. There are special hardcoded + * values for voltages above 1.3V. Currently we are + * hardcoding only for 1.35 V which is used for 1GH OPP for + * OMAP4430. + */ + if (vsel == 0x3A) + return 1350000; + + if (smps_offset & 0x8) + return ((((vsel - 1) * 125) + 7000)) * 100; + else + return ((((vsel - 1) * 125) + 6000)) * 100; +} + +u8 twl6030_uv_to_vsel(unsigned long uv) +{ + /* + * In TWL6030 depending on the value of SMPS_OFFSET + * efuse register the voltage range supported in + * standard mode can be either between 0.6V - 1.3V or + * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse + * is programmed to all 0's where as starting from + * TWL6030 ES1.1 the efuse is programmed to 1 + */ + if (!is_offset_valid) { + twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset, + REG_SMPS_OFFSET); + is_offset_valid = true; + } + + /* + * There is no specific formula for voltage to vsel + * conversion above 1.3V. There are special hardcoded + * values for voltages above 1.3V. Currently we are + * hardcoding only for 1.35 V which is used for 1GH OPP for + * OMAP4430. + */ + if (uv == 1350000) + return 0x3A; + + if (smps_offset & 0x8) + return DIV_ROUND_UP(uv - 700000, 12500) + 1; + else + return DIV_ROUND_UP(uv - 600000, 12500) + 1; +} + +static struct omap_volt_pmic_info omap3_mpu_volt_info = { + .slew_rate = 4000, + .step_size = 12500, + .on_volt = 1200000, + .onlp_volt = 1000000, + .ret_volt = 975000, + .off_volt = 600000, + .volt_setup_time = 0xfff, + .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET, + .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN, + .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX, + .vp_vddmin = OMAP3430_VP1_VLIMITTO_VDDMIN, + .vp_vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX, + .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US, + .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR, + .pmic_reg = OMAP3_VDD_MPU_SR_CONTROL_REG, + .vsel_to_uv = twl4030_vsel_to_uv, + .uv_to_vsel = twl4030_uv_to_vsel, +}; + +static struct omap_volt_pmic_info omap3_core_volt_info = { + .slew_rate = 4000, + .step_size = 12500, + .on_volt = 1200000, + .onlp_volt = 1000000, + .ret_volt = 975000, + .off_volt = 600000, + .volt_setup_time = 0xfff, + .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET, + .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN, + .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX, + .vp_vddmin = OMAP3430_VP2_VLIMITTO_VDDMIN, + .vp_vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX, + .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US, + .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR, + .pmic_reg = OMAP3_VDD_CORE_SR_CONTROL_REG, + .vsel_to_uv = twl4030_vsel_to_uv, + .uv_to_vsel = twl4030_uv_to_vsel, +}; + +static struct omap_volt_pmic_info omap4_mpu_volt_info = { + .slew_rate = 4000, + .step_size = 12500, + .on_volt = 1350000, + .onlp_volt = 1350000, + .ret_volt = 837500, + .off_volt = 600000, + .volt_setup_time = 0, + .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, + .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, + .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, + .vp_vddmin = OMAP4_VP_MPU_VLIMITTO_VDDMIN, + .vp_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX, + .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, + .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, + .pmic_reg = OMAP4_VDD_MPU_SR_VOLT_REG, + .vsel_to_uv = twl6030_vsel_to_uv, + .uv_to_vsel = twl6030_uv_to_vsel, +}; + +static struct omap_volt_pmic_info omap4_iva_volt_info = { + .slew_rate = 4000, + .step_size = 12500, + .on_volt = 1100000, + .onlp_volt = 1100000, + .ret_volt = 837500, + .off_volt = 600000, + .volt_setup_time = 0, + .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, + .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, + .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, + .vp_vddmin = OMAP4_VP_IVA_VLIMITTO_VDDMIN, + .vp_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX, + .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, + .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, + .pmic_reg = OMAP4_VDD_IVA_SR_VOLT_REG, + .vsel_to_uv = twl6030_vsel_to_uv, + .uv_to_vsel = twl6030_uv_to_vsel, +}; + +static struct omap_volt_pmic_info omap4_core_volt_info = { + .slew_rate = 4000, + .step_size = 12500, + .on_volt = 1100000, + .onlp_volt = 1100000, + .ret_volt = 837500, + .off_volt = 600000, + .volt_setup_time = 0, + .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, + .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, + .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, + .vp_vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN, + .vp_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX, + .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, + .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, + .pmic_reg = OMAP4_VDD_CORE_SR_VOLT_REG, + .vsel_to_uv = twl6030_vsel_to_uv, + .uv_to_vsel = twl6030_uv_to_vsel, +}; + +int __init omap4_twl_init(void) +{ + struct voltagedomain *voltdm; + + if (!cpu_is_omap44xx()) + return -ENODEV; + + voltdm = omap_voltage_domain_lookup("mpu"); + omap_voltage_register_pmic(voltdm, &omap4_mpu_volt_info); + + voltdm = omap_voltage_domain_lookup("iva"); + omap_voltage_register_pmic(voltdm, &omap4_iva_volt_info); + + voltdm = omap_voltage_domain_lookup("core"); + omap_voltage_register_pmic(voltdm, &omap4_core_volt_info); + + return 0; +} + +int __init omap3_twl_init(void) +{ + struct voltagedomain *voltdm; + + if (!cpu_is_omap34xx()) + return -ENODEV; + + if (cpu_is_omap3630()) { + omap3_mpu_volt_info.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN; + omap3_mpu_volt_info.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX; + omap3_core_volt_info.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN; + omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX; + } + + voltdm = omap_voltage_domain_lookup("mpu"); + omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info); + + voltdm = omap_voltage_domain_lookup("core"); + omap_voltage_register_pmic(voltdm, &omap3_core_volt_info); + + return 0; +} diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c new file mode 100644 index 000000000000..ab8b35b780b5 --- /dev/null +++ b/arch/arm/mach-omap2/opp.c @@ -0,0 +1,93 @@ +/* + * OMAP SoC specific OPP wrapper function + * + * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/ + * Nishanth Menon + * Kevin Hilman + * Copyright (C) 2010 Nokia Corporation. + * Eduardo Valentin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/module.h> +#include <linux/opp.h> + +#include <plat/omap_device.h> + +#include "omap_opp_data.h" + +/* Temp variable to allow multiple calls */ +static u8 __initdata omap_table_init; + +/** + * omap_init_opp_table() - Initialize opp table as per the CPU type + * @opp_def: opp default list for this silicon + * @opp_def_size: number of opp entries for this silicon + * + * Register the initial OPP table with the OPP library based on the CPU + * type. This is meant to be used only by SoC specific registration. + */ +int __init omap_init_opp_table(struct omap_opp_def *opp_def, + u32 opp_def_size) +{ + int i, r; + + if (!opp_def || !opp_def_size) { + pr_err("%s: invalid params!\n", __func__); + return -EINVAL; + } + + /* + * Initialize only if not already initialized even if the previous + * call failed, because, no reason we'd succeed again. + */ + if (omap_table_init) + return -EEXIST; + omap_table_init = 1; + + /* Lets now register with OPP library */ + for (i = 0; i < opp_def_size; i++) { + struct omap_hwmod *oh; + struct device *dev; + + if (!opp_def->hwmod_name) { + pr_err("%s: NULL name of omap_hwmod, failing [%d].\n", + __func__, i); + return -EINVAL; + } + oh = omap_hwmod_lookup(opp_def->hwmod_name); + if (!oh || !oh->od) { + pr_warn("%s: no hwmod or odev for %s, [%d] " + "cannot add OPPs.\n", __func__, + opp_def->hwmod_name, i); + return -EINVAL; + } + dev = &oh->od->pdev.dev; + + r = opp_add(dev, opp_def->freq, opp_def->u_volt); + if (r) { + dev_err(dev, "%s: add OPP %ld failed for %s [%d] " + "result=%d\n", + __func__, opp_def->freq, + opp_def->hwmod_name, i, r); + } else { + if (!opp_def->default_available) + r = opp_disable(dev, opp_def->freq); + if (r) + dev_err(dev, "%s: disable %ld failed for %s " + "[%d] result=%d\n", + __func__, opp_def->freq, + opp_def->hwmod_name, i, r); + } + opp_def++; + } + + return 0; +} diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c new file mode 100644 index 000000000000..0486fce8a92c --- /dev/null +++ b/arch/arm/mach-omap2/opp3xxx_data.c @@ -0,0 +1,107 @@ +/* + * OMAP3 OPP table definitions. + * + * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/ + * Nishanth Menon + * Kevin Hilman + * Copyright (C) 2010 Nokia Corporation. + * Eduardo Valentin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/module.h> + +#include <plat/cpu.h> + +#include "omap_opp_data.h" + +static struct omap_opp_def __initdata omap34xx_opp_def_list[] = { + /* MPU OPP1 */ + OPP_INITIALIZER("mpu", true, 125000000, 975000), + /* MPU OPP2 */ + OPP_INITIALIZER("mpu", true, 250000000, 1075000), + /* MPU OPP3 */ + OPP_INITIALIZER("mpu", true, 500000000, 1200000), + /* MPU OPP4 */ + OPP_INITIALIZER("mpu", true, 550000000, 1270000), + /* MPU OPP5 */ + OPP_INITIALIZER("mpu", true, 600000000, 1350000), + + /* + * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is + * almost the same than the one at 83MHz thus providing very little + * gain for the power point of view. In term of energy it will even + * increase the consumption due to the very negative performance + * impact that frequency will do to the MPU and the whole system in + * general. + */ + OPP_INITIALIZER("l3_main", false, 41500000, 975000), + /* L3 OPP2 */ + OPP_INITIALIZER("l3_main", true, 83000000, 1050000), + /* L3 OPP3 */ + OPP_INITIALIZER("l3_main", true, 166000000, 1150000), + + /* DSP OPP1 */ + OPP_INITIALIZER("iva", true, 90000000, 975000), + /* DSP OPP2 */ + OPP_INITIALIZER("iva", true, 180000000, 1075000), + /* DSP OPP3 */ + OPP_INITIALIZER("iva", true, 360000000, 1200000), + /* DSP OPP4 */ + OPP_INITIALIZER("iva", true, 400000000, 1270000), + /* DSP OPP5 */ + OPP_INITIALIZER("iva", true, 430000000, 1350000), +}; + +static struct omap_opp_def __initdata omap36xx_opp_def_list[] = { + /* MPU OPP1 - OPP50 */ + OPP_INITIALIZER("mpu", true, 300000000, 1012500), + /* MPU OPP2 - OPP100 */ + OPP_INITIALIZER("mpu", true, 600000000, 1200000), + /* MPU OPP3 - OPP-Turbo */ + OPP_INITIALIZER("mpu", false, 800000000, 1325000), + /* MPU OPP4 - OPP-SB */ + OPP_INITIALIZER("mpu", false, 1000000000, 1375000), + + /* L3 OPP1 - OPP50 */ + OPP_INITIALIZER("l3_main", true, 100000000, 1000000), + /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */ + OPP_INITIALIZER("l3_main", true, 200000000, 1200000), + + /* DSP OPP1 - OPP50 */ + OPP_INITIALIZER("iva", true, 260000000, 1012500), + /* DSP OPP2 - OPP100 */ + OPP_INITIALIZER("iva", true, 520000000, 1200000), + /* DSP OPP3 - OPP-Turbo */ + OPP_INITIALIZER("iva", false, 660000000, 1325000), + /* DSP OPP4 - OPP-SB */ + OPP_INITIALIZER("iva", false, 800000000, 1375000), +}; + +/** + * omap3_opp_init() - initialize omap3 opp table + */ +static int __init omap3_opp_init(void) +{ + int r = -ENODEV; + + if (!cpu_is_omap34xx()) + return r; + + if (cpu_is_omap3630()) + r = omap_init_opp_table(omap36xx_opp_def_list, + ARRAY_SIZE(omap36xx_opp_def_list)); + else + r = omap_init_opp_table(omap34xx_opp_def_list, + ARRAY_SIZE(omap34xx_opp_def_list)); + + return r; +} +device_initcall(omap3_opp_init); diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c new file mode 100644 index 000000000000..a11fa566d8ee --- /dev/null +++ b/arch/arm/mach-omap2/opp4xxx_data.c @@ -0,0 +1,57 @@ +/* + * OMAP4 OPP table definitions. + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Nishanth Menon + * Kevin Hilman + * Thara Gopinath + * Copyright (C) 2010 Nokia Corporation. + * Eduardo Valentin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/module.h> + +#include <plat/cpu.h> + +#include "omap_opp_data.h" + +static struct omap_opp_def __initdata omap44xx_opp_def_list[] = { + /* MPU OPP1 - OPP50 */ + OPP_INITIALIZER("mpu", true, 300000000, 1100000), + /* MPU OPP2 - OPP100 */ + OPP_INITIALIZER("mpu", true, 600000000, 1200000), + /* MPU OPP3 - OPP-Turbo */ + OPP_INITIALIZER("mpu", false, 800000000, 1260000), + /* MPU OPP4 - OPP-SB */ + OPP_INITIALIZER("mpu", false, 1008000000, 1350000), + /* L3 OPP1 - OPP50 */ + OPP_INITIALIZER("l3_main_1", true, 100000000, 930000), + /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */ + OPP_INITIALIZER("l3_main_1", true, 200000000, 1100000), + /* TODO: add IVA, DSP, aess, fdif, gpu */ +}; + +/** + * omap4_opp_init() - initialize omap4 opp table + */ +static int __init omap4_opp_init(void) +{ + int r = -ENODEV; + + if (!cpu_is_omap44xx()) + return r; + + r = omap_init_opp_table(omap44xx_opp_def_list, + ARRAY_SIZE(omap44xx_opp_def_list)); + + return r; +} +device_initcall(omap4_opp_init); diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index a8afb610c7d8..125f56591fb5 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -29,12 +29,13 @@ #include <plat/clock.h> #include <plat/board.h> -#include <plat/powerdomain.h> -#include <plat/clockdomain.h> +#include "powerdomain.h" +#include "clockdomain.h" #include <plat/dmtimer.h> +#include <plat/omap-pm.h> -#include "prm.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" +#include "prm2xxx_3xxx.h" #include "pm.h" int omap2_pm_debug; @@ -45,10 +46,10 @@ u32 wakeup_timer_milliseconds; #define DUMP_PRM_MOD_REG(mod, reg) \ regs[reg_count].name = #mod "." #reg; \ - regs[reg_count++].val = prm_read_mod_reg(mod, reg) + regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg) #define DUMP_CM_MOD_REG(mod, reg) \ regs[reg_count].name = #mod "." #reg; \ - regs[reg_count++].val = cm_read_mod_reg(mod, reg) + regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg) #define DUMP_PRM_REG(reg) \ regs[reg_count].name = #reg; \ regs[reg_count++].val = __raw_readl(reg) @@ -328,10 +329,10 @@ static void pm_dbg_regset_store(u32 *ptr) for (j = pm_dbg_reg_modules[i].low; j <= pm_dbg_reg_modules[i].high; j += 4) { if (pm_dbg_reg_modules[i].type == MOD_CM) - val = cm_read_mod_reg( + val = omap2_cm_read_mod_reg( pm_dbg_reg_modules[i].offset, j); else - val = prm_read_mod_reg( + val = omap2_prm_read_mod_reg( pm_dbg_reg_modules[i].offset, j); *(ptr++) = val; } @@ -581,6 +582,10 @@ static int option_set(void *data, u64 val) *option = val; if (option == &enable_off_mode) { + if (val) + omap_pm_enable_off_mode(); + else + omap_pm_disable_off_mode(); if (cpu_is_omap34xx()) omap3_pm_off_mode_enable(val); } diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 59ca03b0e691..d5a102c71989 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -13,13 +13,16 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/err.h> +#include <linux/opp.h> #include <plat/omap-pm.h> #include <plat/omap_device.h> #include <plat/common.h> +#include <plat/voltage.h> -#include <plat/powerdomain.h> -#include <plat/clockdomain.h> +#include "powerdomain.h" +#include "clockdomain.h" +#include "pm.h" static struct omap_device_pm_latency *pm_lats; @@ -89,10 +92,13 @@ static void omap2_init_processor_devices(void) } } +/* Types of sleep_switch used in omap_set_pwrdm_state */ +#define FORCEWAKEUP_SWITCH 0 +#define LOWPOWERSTATE_SWITCH 1 + /* * This sets pwrdm state (other than mpu & core. Currently only ON & - * RET are supported. Function is assuming that clkdm doesn't have - * hw_sup mode enabled. + * RET are supported. */ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) { @@ -114,9 +120,14 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) return ret; if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { - omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); - sleep_switch = 1; - pwrdm_wait_transition(pwrdm); + if ((pwrdm_read_pwrst(pwrdm) > state) && + (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) { + sleep_switch = LOWPOWERSTATE_SWITCH; + } else { + omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); + pwrdm_wait_transition(pwrdm); + sleep_switch = FORCEWAKEUP_SWITCH; + } } ret = pwrdm_set_next_pwrst(pwrdm, state); @@ -126,16 +137,106 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) goto err; } - if (sleep_switch) { - omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); - pwrdm_wait_transition(pwrdm); - pwrdm_state_switch(pwrdm); + switch (sleep_switch) { + case FORCEWAKEUP_SWITCH: + if (pwrdm->pwrdm_clkdms[0]->flags & CLKDM_CAN_ENABLE_AUTO) + omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); + else + omap2_clkdm_sleep(pwrdm->pwrdm_clkdms[0]); + break; + case LOWPOWERSTATE_SWITCH: + pwrdm_set_lowpwrstchange(pwrdm); + break; + default: + return ret; } + pwrdm_wait_transition(pwrdm); + pwrdm_state_switch(pwrdm); err: return ret; } +/* + * This API is to be called during init to put the various voltage + * domains to the voltage as per the opp table. Typically we boot up + * at the nominal voltage. So this function finds out the rate of + * the clock associated with the voltage domain, finds out the correct + * opp entry and puts the voltage domain to the voltage specifies + * in the opp entry + */ +static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, + struct device *dev) +{ + struct voltagedomain *voltdm; + struct clk *clk; + struct opp *opp; + unsigned long freq, bootup_volt; + + if (!vdd_name || !clk_name || !dev) { + printk(KERN_ERR "%s: Invalid parameters!\n", __func__); + goto exit; + } + + voltdm = omap_voltage_domain_lookup(vdd_name); + if (IS_ERR(voltdm)) { + printk(KERN_ERR "%s: Unable to get vdd pointer for vdd_%s\n", + __func__, vdd_name); + goto exit; + } + + clk = clk_get(NULL, clk_name); + if (IS_ERR(clk)) { + printk(KERN_ERR "%s: unable to get clk %s\n", + __func__, clk_name); + goto exit; + } + + freq = clk->rate; + clk_put(clk); + + opp = opp_find_freq_ceil(dev, &freq); + if (IS_ERR(opp)) { + printk(KERN_ERR "%s: unable to find boot up OPP for vdd_%s\n", + __func__, vdd_name); + goto exit; + } + + bootup_volt = opp_get_voltage(opp); + if (!bootup_volt) { + printk(KERN_ERR "%s: unable to find voltage corresponding" + "to the bootup OPP for vdd_%s\n", __func__, vdd_name); + goto exit; + } + + omap_voltage_scale_vdd(voltdm, bootup_volt); + return 0; + +exit: + printk(KERN_ERR "%s: Unable to put vdd_%s to its init voltage\n\n", + __func__, vdd_name); + return -EINVAL; +} + +static void __init omap3_init_voltages(void) +{ + if (!cpu_is_omap34xx()) + return; + + omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev); + omap2_set_init_voltage("core", "l3_ick", l3_dev); +} + +static void __init omap4_init_voltages(void) +{ + if (!cpu_is_omap44xx()) + return; + + omap2_set_init_voltage("mpu", "dpll_mpu_ck", mpu_dev); + omap2_set_init_voltage("core", "l3_div_ck", l3_dev); + omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", iva_dev); +} + static int __init omap2_common_pm_init(void) { omap2_init_processor_devices(); @@ -143,5 +244,24 @@ static int __init omap2_common_pm_init(void) return 0; } -device_initcall(omap2_common_pm_init); +postcore_initcall(omap2_common_pm_init); + +static int __init omap2_common_pm_late_init(void) +{ + /* Init the OMAP TWL parameters */ + omap3_twl_init(); + omap4_twl_init(); + + /* Init the voltage layer */ + omap_voltage_late_init(); + /* Initialize the voltages */ + omap3_init_voltages(); + omap4_init_voltages(); + + /* Smartreflex device init */ + omap_devinit_smartreflex(); + + return 0; +} +late_initcall(omap2_common_pm_late_init); diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 0d75bfd1fdbe..1c1b0ab5b978 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -11,7 +11,9 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PM_H #define __ARCH_ARM_MACH_OMAP2_PM_H -#include <plat/powerdomain.h> +#include <linux/err.h> + +#include "powerdomain.h" extern void *omap3_secure_ram_storage; extern void omap3_pm_off_mode_enable(int); @@ -20,6 +22,20 @@ extern int omap3_can_sleep(void); extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); extern int omap3_idle_init(void); +#if defined(CONFIG_PM_OPP) +extern int omap3_opp_init(void); +extern int omap4_opp_init(void); +#else +static inline int omap3_opp_init(void) +{ + return -EINVAL; +} +static inline int omap4_opp_init(void) +{ + return -EINVAL; +} +#endif + struct cpuidle_params { u8 valid; u32 sleep_latency; @@ -58,7 +74,7 @@ extern u32 sleep_while_idle; #endif #if defined(CONFIG_CPU_IDLE) -extern void omap3_cpuidle_update_states(void); +extern void omap3_cpuidle_update_states(u32, u32); #endif #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) @@ -80,9 +96,46 @@ extern void save_secure_ram_context(u32 *addr); extern void omap3_save_scratchpad_contents(void); extern unsigned int omap24xx_idle_loop_suspend_sz; -extern unsigned int omap34xx_suspend_sz; extern unsigned int save_secure_ram_context_sz; extern unsigned int omap24xx_cpu_suspend_sz; extern unsigned int omap34xx_cpu_suspend_sz; +#define PM_RTA_ERRATUM_i608 (1 << 0) +#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1) + +#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) +extern u16 pm34xx_errata; +#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id)) +extern void enable_omap3630_toggle_l2_on_restore(void); +#else +#define IS_PM34XX_ERRATUM(id) 0 +static inline void enable_omap3630_toggle_l2_on_restore(void) { } +#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */ + +#ifdef CONFIG_OMAP_SMARTREFLEX +extern int omap_devinit_smartreflex(void); +extern void omap_enable_smartreflex_on_init(void); +#else +static inline int omap_devinit_smartreflex(void) +{ + return -EINVAL; +} + +static inline void omap_enable_smartreflex_on_init(void) {} +#endif + +#ifdef CONFIG_TWL4030_CORE +extern int omap3_twl_init(void); +extern int omap4_twl_init(void); +#else +static inline int omap3_twl_init(void) +{ + return -EINVAL; +} +static inline int omap4_twl_init(void) +{ + return -EINVAL; +} +#endif + #endif diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index aaeea49b9bdd..dac2d1d9987d 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -42,16 +42,16 @@ #include <plat/dma.h> #include <plat/board.h> -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" #include "sdrc.h" #include "pm.h" #include "control.h" -#include <plat/powerdomain.h> -#include <plat/clockdomain.h> +#include "powerdomain.h" +#include "clockdomain.h" #ifdef CONFIG_SUSPEND static suspend_state_t suspend_state = PM_SUSPEND_ON; @@ -79,8 +79,8 @@ static int omap2_fclks_active(void) { u32 f1, f2; - f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); + f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); /* Ignore UART clocks. These are handled by UART core (serial.c) */ f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK); @@ -105,9 +105,9 @@ static void omap2_enter_full_retention(void) /* Clear old wake-up events */ /* REVISIT: These write to reserved bits? */ - prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); /* * Set MPU powerdomain's next power state to RETENTION; @@ -120,7 +120,7 @@ static void omap2_enter_full_retention(void) l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); - omap2_gpio_prepare_for_idle(PWRDM_POWER_RET); + omap2_gpio_prepare_for_idle(0); if (omap2_pm_debug) { omap2_pm_dump(0, 0, 0); @@ -167,30 +167,30 @@ no_sleep: clk_enable(osc_ck); /* clear CORE wake-up events */ - prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ - prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); + omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); /* MPU domain wake events */ - l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); + l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); if (l & 0x01) - prm_write_mod_reg(0x01, OCP_MOD, + omap2_prm_write_mod_reg(0x01, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); if (l & 0x20) - prm_write_mod_reg(0x20, OCP_MOD, + omap2_prm_write_mod_reg(0x20, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); /* Mask future PRCM-to-MPU interrupts */ - prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); + omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); } static int omap2_i2c_active(void) { u32 l; - l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK); } @@ -201,13 +201,13 @@ static int omap2_allow_mpu_retention(void) u32 l; /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ - l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK | OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK | OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK)) return 0; /* Check for UART3. */ - l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); + l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); if (l & OMAP24XX_EN_UART3_MASK) return 0; if (sti_console_enabled) @@ -230,18 +230,18 @@ static void omap2_enter_mpu_retention(void) * it is in retention mode. */ if (omap2_allow_mpu_retention()) { /* REVISIT: These write to reserved bits? */ - prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); /* Try to enter MPU retention */ - prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | + omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE_MASK, MPU_MOD, OMAP2_PM_PWSTCTRL); } else { /* Block MPU retention */ - prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, + omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, OMAP2_PM_PWSTCTRL); only_idle = 1; } @@ -299,16 +299,11 @@ out: local_irq_enable(); } +#ifdef CONFIG_SUSPEND static int omap2_pm_begin(suspend_state_t state) { - suspend_state = state; - return 0; -} - -static int omap2_pm_prepare(void) -{ - /* We cannot sleep in idle until we have resumed */ disable_hlt(); + suspend_state = state; return 0; } @@ -316,9 +311,9 @@ static int omap2_pm_suspend(void) { u32 wken_wkup, mir1; - wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN); + wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); wken_wkup &= ~OMAP24XX_EN_GPT1_MASK; - prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); + omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); /* Mask GPT1 */ mir1 = omap_readl(0x480fe0a4); @@ -328,7 +323,7 @@ static int omap2_pm_suspend(void) omap2_enter_full_retention(); omap_writel(mir1, 0x480fe0a4); - prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); + omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); return 0; } @@ -349,24 +344,21 @@ static int omap2_pm_enter(suspend_state_t state) return ret; } -static void omap2_pm_finish(void) -{ - enable_hlt(); -} - static void omap2_pm_end(void) { suspend_state = PM_SUSPEND_ON; + enable_hlt(); } static struct platform_suspend_ops omap_pm_ops = { .begin = omap2_pm_begin, - .prepare = omap2_pm_prepare, .enter = omap2_pm_enter, - .finish = omap2_pm_finish, .end = omap2_pm_end, .valid = suspend_valid_only_mem, }; +#else +static const struct platform_suspend_ops __initdata omap_pm_ops; +#endif /* CONFIG_SUSPEND */ /* XXX This function should be shareable between OMAP2xxx and OMAP3 */ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) @@ -388,7 +380,7 @@ static void __init prcm_setup_regs(void) struct powerdomain *pwrdm; /* Enable autoidle */ - prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, + omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, OMAP2_PRCM_SYSCONFIG_OFFSET); /* @@ -427,87 +419,87 @@ static void __init prcm_setup_regs(void) clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); /* Enable clock autoidle for all domains */ - cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK | - OMAP24XX_AUTO_MAILBOXES_MASK | - OMAP24XX_AUTO_WDT4_MASK | - OMAP2420_AUTO_WDT3_MASK | - OMAP24XX_AUTO_MSPRO_MASK | - OMAP2420_AUTO_MMC_MASK | - OMAP24XX_AUTO_FAC_MASK | - OMAP2420_AUTO_EAC_MASK | - OMAP24XX_AUTO_HDQ_MASK | - OMAP24XX_AUTO_UART2_MASK | - OMAP24XX_AUTO_UART1_MASK | - OMAP24XX_AUTO_I2C2_MASK | - OMAP24XX_AUTO_I2C1_MASK | - OMAP24XX_AUTO_MCSPI2_MASK | - OMAP24XX_AUTO_MCSPI1_MASK | - OMAP24XX_AUTO_MCBSP2_MASK | - OMAP24XX_AUTO_MCBSP1_MASK | - OMAP24XX_AUTO_GPT12_MASK | - OMAP24XX_AUTO_GPT11_MASK | - OMAP24XX_AUTO_GPT10_MASK | - OMAP24XX_AUTO_GPT9_MASK | - OMAP24XX_AUTO_GPT8_MASK | - OMAP24XX_AUTO_GPT7_MASK | - OMAP24XX_AUTO_GPT6_MASK | - OMAP24XX_AUTO_GPT5_MASK | - OMAP24XX_AUTO_GPT4_MASK | - OMAP24XX_AUTO_GPT3_MASK | - OMAP24XX_AUTO_GPT2_MASK | - OMAP2420_AUTO_VLYNQ_MASK | - OMAP24XX_AUTO_DSS_MASK, - CORE_MOD, CM_AUTOIDLE1); - cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK | - OMAP24XX_AUTO_SSI_MASK | - OMAP24XX_AUTO_USB_MASK, - CORE_MOD, CM_AUTOIDLE2); - cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK | - OMAP24XX_AUTO_GPMC_MASK | - OMAP24XX_AUTO_SDMA_MASK, - CORE_MOD, CM_AUTOIDLE3); - cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK | - OMAP24XX_AUTO_AES_MASK | - OMAP24XX_AUTO_RNG_MASK | - OMAP24XX_AUTO_SHA_MASK | - OMAP24XX_AUTO_DES_MASK, - CORE_MOD, OMAP24XX_CM_AUTOIDLE4); - - cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, - CM_AUTOIDLE); + omap2_cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK | + OMAP24XX_AUTO_MAILBOXES_MASK | + OMAP24XX_AUTO_WDT4_MASK | + OMAP2420_AUTO_WDT3_MASK | + OMAP24XX_AUTO_MSPRO_MASK | + OMAP2420_AUTO_MMC_MASK | + OMAP24XX_AUTO_FAC_MASK | + OMAP2420_AUTO_EAC_MASK | + OMAP24XX_AUTO_HDQ_MASK | + OMAP24XX_AUTO_UART2_MASK | + OMAP24XX_AUTO_UART1_MASK | + OMAP24XX_AUTO_I2C2_MASK | + OMAP24XX_AUTO_I2C1_MASK | + OMAP24XX_AUTO_MCSPI2_MASK | + OMAP24XX_AUTO_MCSPI1_MASK | + OMAP24XX_AUTO_MCBSP2_MASK | + OMAP24XX_AUTO_MCBSP1_MASK | + OMAP24XX_AUTO_GPT12_MASK | + OMAP24XX_AUTO_GPT11_MASK | + OMAP24XX_AUTO_GPT10_MASK | + OMAP24XX_AUTO_GPT9_MASK | + OMAP24XX_AUTO_GPT8_MASK | + OMAP24XX_AUTO_GPT7_MASK | + OMAP24XX_AUTO_GPT6_MASK | + OMAP24XX_AUTO_GPT5_MASK | + OMAP24XX_AUTO_GPT4_MASK | + OMAP24XX_AUTO_GPT3_MASK | + OMAP24XX_AUTO_GPT2_MASK | + OMAP2420_AUTO_VLYNQ_MASK | + OMAP24XX_AUTO_DSS_MASK, + CORE_MOD, CM_AUTOIDLE1); + omap2_cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK | + OMAP24XX_AUTO_SSI_MASK | + OMAP24XX_AUTO_USB_MASK, + CORE_MOD, CM_AUTOIDLE2); + omap2_cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK | + OMAP24XX_AUTO_GPMC_MASK | + OMAP24XX_AUTO_SDMA_MASK, + CORE_MOD, CM_AUTOIDLE3); + omap2_cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK | + OMAP24XX_AUTO_AES_MASK | + OMAP24XX_AUTO_RNG_MASK | + OMAP24XX_AUTO_SHA_MASK | + OMAP24XX_AUTO_DES_MASK, + CORE_MOD, OMAP24XX_CM_AUTOIDLE4); + + omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, + CM_AUTOIDLE); /* Put DPLL and both APLLs into autoidle mode */ - cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | - (0x03 << OMAP24XX_AUTO_96M_SHIFT) | - (0x03 << OMAP24XX_AUTO_54M_SHIFT), - PLL_MOD, CM_AUTOIDLE); - - cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | - OMAP24XX_AUTO_WDT1_MASK | - OMAP24XX_AUTO_MPU_WDT_MASK | - OMAP24XX_AUTO_GPIOS_MASK | - OMAP24XX_AUTO_32KSYNC_MASK | - OMAP24XX_AUTO_GPT1_MASK, - WKUP_MOD, CM_AUTOIDLE); + omap2_cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | + (0x03 << OMAP24XX_AUTO_96M_SHIFT) | + (0x03 << OMAP24XX_AUTO_54M_SHIFT), + PLL_MOD, CM_AUTOIDLE); + + omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | + OMAP24XX_AUTO_WDT1_MASK | + OMAP24XX_AUTO_MPU_WDT_MASK | + OMAP24XX_AUTO_GPIOS_MASK | + OMAP24XX_AUTO_32KSYNC_MASK | + OMAP24XX_AUTO_GPT1_MASK, + WKUP_MOD, CM_AUTOIDLE); /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk * stabilisation */ - prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, - OMAP2_PRCM_CLKSSETUP_OFFSET); + omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, + OMAP2_PRCM_CLKSSETUP_OFFSET); /* Configure automatic voltage transition */ - prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, - OMAP2_PRCM_VOLTSETUP_OFFSET); - prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | - (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | - OMAP24XX_MEMRETCTRL_MASK | - (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | - (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), - OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); + omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, + OMAP2_PRCM_VOLTSETUP_OFFSET); + omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | + (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | + OMAP24XX_MEMRETCTRL_MASK | + (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | + (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), + OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); /* Enable wake-up events */ - prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, - WKUP_MOD, PM_WKEN); + omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, + WKUP_MOD, PM_WKEN); } static int __init omap2_pm_init(void) @@ -518,7 +510,7 @@ static int __init omap2_pm_init(void) return -ENODEV; printk(KERN_INFO "Power Management for OMAP2 initializing\n"); - l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); + l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); /* Look up important powerdomains */ diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 648b8c50d024..5b323f28da2d 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -31,8 +31,8 @@ #include <linux/console.h> #include <plat/sram.h> -#include <plat/clockdomain.h> -#include <plat/powerdomain.h> +#include "clockdomain.h" +#include "powerdomain.h" #include <plat/serial.h> #include <plat/sdrc.h> #include <plat/prcm.h> @@ -41,11 +41,11 @@ #include <asm/tlbflush.h> -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" #include "prm-regbits-34xx.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "pm.h" #include "sdrc.h" #include "control.h" @@ -68,6 +68,9 @@ static inline bool is_suspending(void) #define OMAP343X_TABLE_VALUE_OFFSET 0xc0 #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 +/* pm34xx errata defined in pm.h */ +u16 pm34xx_errata; + struct power_state { struct powerdomain *pwrdm; u32 next_state; @@ -102,12 +105,12 @@ static void omap3_enable_io_chain(void) int timeout = 0; if (omap_rev() >= OMAP3430_REV_ES3_1) { - prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, + omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, PM_WKEN); /* Do a readback to assure write has been done */ - prm_read_mod_reg(WKUP_MOD, PM_WKEN); + omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); - while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) & + while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & OMAP3430_ST_IO_CHAIN_MASK)) { timeout++; if (timeout > 1000) { @@ -115,7 +118,7 @@ static void omap3_enable_io_chain(void) "activation failed.\n"); return; } - prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, + omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD, PM_WKEN); } } @@ -124,26 +127,17 @@ static void omap3_enable_io_chain(void) static void omap3_disable_io_chain(void) { if (omap_rev() >= OMAP3430_REV_ES3_1) - prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, + omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, PM_WKEN); } static void omap3_core_save_context(void) { - u32 control_padconf_off; - - /* Save the padconf registers */ - control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); - control_padconf_off |= START_PADCONF_SAVE; - omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF); - /* wait for the save to complete */ - while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) - & PADCONF_SAVE_DONE)) - udelay(1); + omap3_ctrl_save_padconf(); /* * Force write last pad into memory, as this can fail in some - * cases according to erratas 1.157, 1.185 + * cases according to errata 1.157, 1.185 */ omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), OMAP343X_CONTROL_MEM_WKUP + 0x2a0); @@ -218,27 +212,27 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs) OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; int c = 0; - wkst = prm_read_mod_reg(module, wkst_off); - wkst &= prm_read_mod_reg(module, grpsel_off); + wkst = omap2_prm_read_mod_reg(module, wkst_off); + wkst &= omap2_prm_read_mod_reg(module, grpsel_off); if (wkst) { - iclk = cm_read_mod_reg(module, iclk_off); - fclk = cm_read_mod_reg(module, fclk_off); + iclk = omap2_cm_read_mod_reg(module, iclk_off); + fclk = omap2_cm_read_mod_reg(module, fclk_off); while (wkst) { clken = wkst; - cm_set_mod_reg_bits(clken, module, iclk_off); + omap2_cm_set_mod_reg_bits(clken, module, iclk_off); /* * For USBHOST, we don't know whether HOST1 or * HOST2 woke us up, so enable both f-clocks */ if (module == OMAP3430ES2_USBHOST_MOD) clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; - cm_set_mod_reg_bits(clken, module, fclk_off); - prm_write_mod_reg(wkst, module, wkst_off); - wkst = prm_read_mod_reg(module, wkst_off); + omap2_cm_set_mod_reg_bits(clken, module, fclk_off); + omap2_prm_write_mod_reg(wkst, module, wkst_off); + wkst = omap2_prm_read_mod_reg(module, wkst_off); c++; } - cm_write_mod_reg(iclk, module, iclk_off); - cm_write_mod_reg(fclk, module, fclk_off); + omap2_cm_write_mod_reg(iclk, module, iclk_off); + omap2_cm_write_mod_reg(fclk, module, fclk_off); } return c; @@ -281,9 +275,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) u32 irqenable_mpu, irqstatus_mpu; int c = 0; - irqenable_mpu = prm_read_mod_reg(OCP_MOD, + irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); - irqstatus_mpu = prm_read_mod_reg(OCP_MOD, + irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); irqstatus_mpu &= irqenable_mpu; @@ -304,10 +298,10 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) "no code to handle it (%08x)\n", irqstatus_mpu); } - prm_write_mod_reg(irqstatus_mpu, OCP_MOD, + omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - irqstatus_mpu = prm_read_mod_reg(OCP_MOD, + irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); irqstatus_mpu &= irqenable_mpu; @@ -357,6 +351,7 @@ void omap_sram_idle(void) int mpu_next_state = PWRDM_POWER_ON; int per_next_state = PWRDM_POWER_ON; int core_next_state = PWRDM_POWER_ON; + int per_going_off; int core_prev_state, per_prev_state; u32 sdrc_pwr = 0; @@ -395,7 +390,7 @@ void omap_sram_idle(void) if (omap3_has_io_wakeup() && (per_next_state < PWRDM_POWER_ON || core_next_state < PWRDM_POWER_ON)) { - prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); + omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); omap3_enable_io_chain(); } @@ -408,9 +403,10 @@ void omap_sram_idle(void) /* PER */ if (per_next_state < PWRDM_POWER_ON) { + per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; omap_uart_prepare_idle(2); omap_uart_prepare_idle(3); - omap2_gpio_prepare_for_idle(per_next_state); + omap2_gpio_prepare_for_idle(per_going_off); if (per_next_state == PWRDM_POWER_OFF) omap3_per_save_context(); } @@ -421,7 +417,7 @@ void omap_sram_idle(void) omap_uart_prepare_idle(1); if (core_next_state == PWRDM_POWER_OFF) { omap3_core_save_context(); - omap3_prcm_save_context(); + omap3_cm_save_context(); } } @@ -430,7 +426,7 @@ void omap_sram_idle(void) /* * On EMU/HS devices ROM code restores a SRDC value * from scratchpad which has automatic self refresh on timeout - * of AUTO_CNT = 1 enabled. This takes care of errata 1.142. + * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. * Hence store/restore the SDRC_POWER register here. */ if (omap_rev() >= OMAP3430_REV_ES3_0 && @@ -461,14 +457,14 @@ void omap_sram_idle(void) core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); if (core_prev_state == PWRDM_POWER_OFF) { omap3_core_restore_context(); - omap3_prcm_restore_context(); + omap3_cm_restore_context(); omap3_sram_restore_context(); omap2_sms_restore_context(); } omap_uart_resume_idle(0); omap_uart_resume_idle(1); if (core_next_state == PWRDM_POWER_OFF) - prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, + omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, OMAP3430_GR_MOD, OMAP3_PRM_VOLTCTRL_OFFSET); } @@ -492,7 +488,8 @@ console_still_active: if (omap3_has_io_wakeup() && (per_next_state < PWRDM_POWER_ON || core_next_state < PWRDM_POWER_ON)) { - prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); + omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, + PM_WKEN); omap3_disable_io_chain(); } @@ -529,12 +526,6 @@ out: } #ifdef CONFIG_SUSPEND -static int omap3_pm_prepare(void) -{ - disable_hlt(); - return 0; -} - static int omap3_pm_suspend(void) { struct power_state *pwrst; @@ -597,14 +588,10 @@ static int omap3_pm_enter(suspend_state_t unused) return ret; } -static void omap3_pm_finish(void) -{ - enable_hlt(); -} - /* Hooks to enable / disable UART interrupts during suspend */ static int omap3_pm_begin(suspend_state_t state) { + disable_hlt(); suspend_state = state; omap_uart_enable_irqs(0); return 0; @@ -614,15 +601,14 @@ static void omap3_pm_end(void) { suspend_state = PM_SUSPEND_ON; omap_uart_enable_irqs(1); + enable_hlt(); return; } static struct platform_suspend_ops omap_pm_ops = { .begin = omap3_pm_begin, .end = omap3_pm_end, - .prepare = omap3_pm_prepare, .enter = omap3_pm_enter, - .finish = omap3_pm_finish, .valid = suspend_valid_only_mem, }; #endif /* CONFIG_SUSPEND */ @@ -641,21 +627,21 @@ static struct platform_suspend_ops omap_pm_ops = { static void __init omap3_iva_idle(void) { /* ensure IVA2 clock is disabled */ - cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); + omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); /* if no clock activity, nothing else to do */ - if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & + if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & OMAP3430_CLKACTIVITY_IVA2_MASK)) return; /* Reset IVA2 */ - prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | + omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK | OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); /* Enable IVA2 clock */ - cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, + omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, OMAP3430_IVA2_MOD, CM_FCLKEN); /* Set IVA2 boot mode to 'idle' */ @@ -663,13 +649,13 @@ static void __init omap3_iva_idle(void) OMAP343X_CONTROL_IVA2_BOOTMOD); /* Un-reset IVA2 */ - prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); + omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); /* Disable IVA2 clock */ - cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); + omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); /* Reset IVA2 */ - prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | + omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK | OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); @@ -693,10 +679,10 @@ static void __init omap3_d2d_idle(void) omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); /* reset modem */ - prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | + omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, CORE_MOD, OMAP2_RM_RSTCTRL); - prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); + omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); } static void __init prcm_setup_regs(void) @@ -711,23 +697,23 @@ static void __init prcm_setup_regs(void) /* XXX Reset all wkdeps. This should be done when initializing * powerdomains */ - prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); - prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); if (omap_rev() > OMAP3430_REV_ES1_0) { - prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); } else - prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); /* * Enable interface clock autoidle for all modules. * Note that in the long run this should be done by clockfw */ - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_MODEM_MASK | OMAP3430ES2_AUTO_MMC3_MASK | OMAP3430ES2_AUTO_ICR_MASK | @@ -760,7 +746,7 @@ static void __init prcm_setup_regs(void) OMAP3430_AUTO_SSI_MASK, CORE_MOD, CM_AUTOIDLE1); - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_PKA_MASK | OMAP3430_AUTO_AES1_MASK | OMAP3430_AUTO_RNG_MASK | @@ -769,13 +755,13 @@ static void __init prcm_setup_regs(void) CORE_MOD, CM_AUTOIDLE2); if (omap_rev() > OMAP3430_REV_ES1_0) { - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_MAD2D_MASK | OMAP3430ES2_AUTO_USBTLL_MASK, CORE_MOD, CM_AUTOIDLE3); } - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_WDT2_MASK | OMAP3430_AUTO_WDT1_MASK | OMAP3430_AUTO_GPIO1_MASK | @@ -784,17 +770,17 @@ static void __init prcm_setup_regs(void) OMAP3430_AUTO_GPT1_MASK, WKUP_MOD, CM_AUTOIDLE); - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_DSS_MASK, OMAP3430_DSS_MOD, CM_AUTOIDLE); - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_CAM_MASK, OMAP3430_CAM_MOD, CM_AUTOIDLE); - cm_write_mod_reg( + omap2_cm_write_mod_reg( omap3630_auto_uart4_mask | OMAP3430_AUTO_GPIO6_MASK | OMAP3430_AUTO_GPIO5_MASK | @@ -818,7 +804,7 @@ static void __init prcm_setup_regs(void) CM_AUTOIDLE); if (omap_rev() > OMAP3430_REV_ES1_0) { - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430ES2_AUTO_USBHOST_MASK, OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); @@ -830,16 +816,16 @@ static void __init prcm_setup_regs(void) * Set all plls to autoidle. This is needed until autoidle is * enabled by clockfw */ - cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, + omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, OMAP3430_IVA2_MOD, CM_AUTOIDLE2); - cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, + omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, MPU_MOD, CM_AUTOIDLE2); - cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | + omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), PLL_MOD, CM_AUTOIDLE); - cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, + omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, PLL_MOD, CM_AUTOIDLE2); @@ -848,31 +834,31 @@ static void __init prcm_setup_regs(void) * sys_clkreq. In the long run clock framework should * take care of this. */ - prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, + omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 1 << OMAP_AUTOEXTCLKMODE_SHIFT, OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET); /* setup wakup source */ - prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | + omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, WKUP_MOD, PM_WKEN); /* No need to write EN_IO, that is always enabled */ - prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | + omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | OMAP3430_GRPSEL_GPT1_MASK | OMAP3430_GRPSEL_GPT12_MASK, WKUP_MOD, OMAP3430_PM_MPUGRPSEL); /* For some reason IO doesn't generate wakeup event even if * it is selected to mpu wakeup goup */ - prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, + omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); /* Enable PM_WKEN to support DSS LPR */ - prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, + omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, OMAP3430_DSS_MOD, PM_WKEN); /* Enable wakeups in PER */ - prm_write_mod_reg(omap3630_en_uart4_mask | + omap2_prm_write_mod_reg(omap3630_en_uart4_mask | OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | @@ -880,7 +866,7 @@ static void __init prcm_setup_regs(void) OMAP3430_EN_MCBSP4_MASK, OMAP3430_PER_MOD, PM_WKEN); /* and allow them to wake up MPU */ - prm_write_mod_reg(omap3630_grpsel_uart4_mask | + omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | OMAP3430_GRPSEL_GPIO2_MASK | OMAP3430_GRPSEL_GPIO3_MASK | OMAP3430_GRPSEL_GPIO4_MASK | @@ -893,22 +879,22 @@ static void __init prcm_setup_regs(void) OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); /* Don't attach IVA interrupts */ - prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); - prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); - prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); - prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); + omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); + omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); + omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); + omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); /* Clear any pending 'reset' flags */ - prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); /* Clear any pending PRCM interrupts */ - prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); omap3_iva_idle(); omap3_d2d_idle(); @@ -925,12 +911,29 @@ void omap3_pm_off_mode_enable(int enable) state = PWRDM_POWER_RET; #ifdef CONFIG_CPU_IDLE - omap3_cpuidle_update_states(); + /* + * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot + * enable OFF mode in a stable form for previous revisions, restrict + * instead to RET + */ + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) + omap3_cpuidle_update_states(state, PWRDM_POWER_RET); + else + omap3_cpuidle_update_states(state, state); #endif list_for_each_entry(pwrst, &pwrst_list, node) { - pwrst->next_state = state; - omap_set_pwrdm_state(pwrst->pwrdm, state); + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && + pwrst->pwrdm == core_pwrdm && + state == PWRDM_POWER_OFF) { + pwrst->next_state = PWRDM_POWER_RET; + WARN_ONCE(1, + "%s: Core OFF disabled due to errata i583\n", + __func__); + } else { + pwrst->next_state = state; + } + omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); } } @@ -1002,6 +1005,17 @@ void omap_push_sram_idle(void) save_secure_ram_context_sz); } +static void __init pm_errata_configure(void) +{ + if (cpu_is_omap3630()) { + pm34xx_errata |= PM_RTA_ERRATUM_i608; + /* Enable the l2 cache toggling in sleep logic */ + enable_omap3630_toggle_l2_on_restore(); + if (omap_rev() < OMAP3630_REV_ES1_2) + pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; + } +} + static int __init omap3_pm_init(void) { struct power_state *pwrst, *tmp; @@ -1011,6 +1025,8 @@ static int __init omap3_pm_init(void) if (!cpu_is_omap34xx()) return -ENODEV; + pm_errata_configure(); + printk(KERN_ERR "Power Management for TI OMAP3.\n"); /* XXX prcm_setup_regs needs to be before enabling hw @@ -1058,6 +1074,14 @@ static int __init omap3_pm_init(void) pm_idle = omap3_pm_idle; omap3_idle_init(); + /* + * RTA is disabled during initialization as per erratum i608 + * it is safer to disable RTA by the bootloader, but we would like + * to be doubly sure here and prevent any mishaps. + */ + if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) + omap3630_ctrl_disable_rta(); + clkdm_add_wkdep(neon_clkdm, mpu_clkdm); if (omap_type() != OMAP2_DEVICE_TYPE_GP) { omap3_secure_ram_storage = diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index 54544b4fc76b..e9f4862c4de4 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -16,7 +16,7 @@ #include <linux/err.h> #include <linux/slab.h> -#include <plat/powerdomain.h> +#include "powerdomain.h" #include <mach/omap4-common.h> struct power_state { @@ -31,12 +31,6 @@ struct power_state { static LIST_HEAD(pwrst_list); #ifdef CONFIG_SUSPEND -static int omap4_pm_prepare(void) -{ - disable_hlt(); - return 0; -} - static int omap4_pm_suspend(void) { do_wfi(); @@ -59,28 +53,22 @@ static int omap4_pm_enter(suspend_state_t suspend_state) return ret; } -static void omap4_pm_finish(void) -{ - enable_hlt(); - return; -} - static int omap4_pm_begin(suspend_state_t state) { + disable_hlt(); return 0; } static void omap4_pm_end(void) { + enable_hlt(); return; } static struct platform_suspend_ops omap_pm_ops = { .begin = omap4_pm_begin, .end = omap4_pm_end, - .prepare = omap4_pm_prepare, .enter = omap4_pm_enter, - .finish = omap4_pm_finish, .valid = suspend_valid_only_mem, }; #endif /* CONFIG_SUSPEND */ diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c new file mode 100644 index 000000000000..171fccd208c7 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomain-common.c @@ -0,0 +1,110 @@ +/* + * linux/arch/arm/mach-omap2/powerdomain-common.c + * Contains common powerdomain framework functions + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Copyright (C) 2010 Nokia Corporation + * + * Derived from mach-omap2/powerdomain.c written by Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/errno.h> +#include <linux/kernel.h> +#include "pm.h" +#include "cm.h" +#include "cm-regbits-34xx.h" +#include "cm-regbits-44xx.h" +#include "prm-regbits-34xx.h" +#include "prm-regbits-44xx.h" + +/* + * OMAP3 and OMAP4 specific register bit initialisations + * Notice that the names here are not according to each power + * domain but the bit mapping used applies to all of them + */ +/* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */ +#define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK +#define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK +#define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK +#define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK +#define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK + +/* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */ +#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK +#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK +#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK +#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK +#define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK + +/* OMAP3 and OMAP4 Memory Status bits */ +#define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK +#define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK +#define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK +#define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK +#define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK + +/* Common Internal functions used across OMAP rev's*/ +u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank) +{ + switch (bank) { + case 0: + return OMAP_MEM0_ONSTATE_MASK; + case 1: + return OMAP_MEM1_ONSTATE_MASK; + case 2: + return OMAP_MEM2_ONSTATE_MASK; + case 3: + return OMAP_MEM3_ONSTATE_MASK; + case 4: + return OMAP_MEM4_ONSTATE_MASK; + default: + WARN_ON(1); /* should never happen */ + return -EEXIST; + } + return 0; +} + +u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank) +{ + switch (bank) { + case 0: + return OMAP_MEM0_RETSTATE_MASK; + case 1: + return OMAP_MEM1_RETSTATE_MASK; + case 2: + return OMAP_MEM2_RETSTATE_MASK; + case 3: + return OMAP_MEM3_RETSTATE_MASK; + case 4: + return OMAP_MEM4_RETSTATE_MASK; + default: + WARN_ON(1); /* should never happen */ + return -EEXIST; + } + return 0; +} + +u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank) +{ + switch (bank) { + case 0: + return OMAP_MEM0_STATEST_MASK; + case 1: + return OMAP_MEM1_STATEST_MASK; + case 2: + return OMAP_MEM2_STATEST_MASK; + case 3: + return OMAP_MEM3_STATEST_MASK; + case 4: + return OMAP_MEM4_STATEST_MASK; + default: + WARN_ON(1); /* should never happen */ + return -EEXIST; + } + return 0; +} + diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 6527ec30dc17..eaed0df16699 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -15,27 +15,19 @@ #undef DEBUG #include <linux/kernel.h> -#include <linux/module.h> #include <linux/types.h> -#include <linux/delay.h> -#include <linux/spinlock.h> #include <linux/list.h> #include <linux/errno.h> -#include <linux/err.h> -#include <linux/io.h> - -#include <asm/atomic.h> - -#include "cm.h" -#include "cm-regbits-34xx.h" -#include "cm-regbits-44xx.h" -#include "prm.h" -#include "prm-regbits-34xx.h" -#include "prm-regbits-44xx.h" +#include <linux/string.h> +#include "cm2xxx_3xxx.h" +#include "prcm44xx.h" +#include "cm44xx.h" +#include "prm2xxx_3xxx.h" +#include "prm44xx.h" #include <plat/cpu.h> -#include <plat/powerdomain.h> -#include <plat/clockdomain.h> +#include "powerdomain.h" +#include "clockdomain.h" #include <plat/prcm.h> #include "pm.h" @@ -45,41 +37,12 @@ enum { PWRDM_STATE_PREV, }; -/* Variable holding value of the CPU dependent PWRSTCTRL Register Offset */ -static u16 pwrstctrl_reg_offs; - -/* Variable holding value of the CPU dependent PWRSTST Register Offset */ -static u16 pwrstst_reg_offs; - -/* OMAP3 and OMAP4 specific register bit initialisations - * Notice that the names here are not according to each power - * domain but the bit mapping used applies to all of them - */ - -/* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */ -#define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK -#define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK -#define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK -#define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK -#define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK - -/* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */ -#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK -#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK -#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK -#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK -#define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK - -/* OMAP3 and OMAP4 Memory Status bits */ -#define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK -#define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK -#define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK -#define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK -#define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK /* pwrdm_list contains all registered struct powerdomains */ static LIST_HEAD(pwrdm_list); +static struct pwrdm_ops *arch_pwrdm; + /* Private functions */ static struct powerdomain *_pwrdm_lookup(const char *name) @@ -110,12 +73,19 @@ static int _pwrdm_register(struct powerdomain *pwrdm) { int i; - if (!pwrdm) + if (!pwrdm || !pwrdm->name) return -EINVAL; if (!omap_chip_is(pwrdm->omap_chip)) return -EINVAL; + if (cpu_is_omap44xx() && + pwrdm->prcm_partition == OMAP4430_INVALID_PRCM_PARTITION) { + pr_err("powerdomain: %s: missing OMAP4 PRCM partition ID\n", + pwrdm->name); + return -EINVAL; + } + if (_pwrdm_lookup(pwrdm->name)) return -EEXIST; @@ -211,6 +181,7 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused) /** * pwrdm_init - set up the powerdomain layer * @pwrdm_list: array of struct powerdomain pointers to register + * @custom_funcs: func pointers for arch specfic implementations * * Loop through the array of powerdomains @pwrdm_list, registering all * that are available on the current CPU. If pwrdm_list is supplied @@ -218,21 +189,14 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused) * registered. No return value. XXX pwrdm_list is not really a * "list"; it is an array. Rename appropriately. */ -void pwrdm_init(struct powerdomain **pwrdm_list) +void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs) { struct powerdomain **p = NULL; - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { - pwrstctrl_reg_offs = OMAP2_PM_PWSTCTRL; - pwrstst_reg_offs = OMAP2_PM_PWSTST; - } else if (cpu_is_omap44xx()) { - pwrstctrl_reg_offs = OMAP4_PM_PWSTCTRL; - pwrstst_reg_offs = OMAP4_PM_PWSTST; - } else { - printk(KERN_ERR "Power Domain struct not supported for " \ - "this CPU\n"); - return; - } + if (!custom_funcs) + WARN(1, "powerdomain: No custom pwrdm functions registered\n"); + else + arch_pwrdm = custom_funcs; if (pwrdm_list) { for (p = pwrdm_list; *p; p++) @@ -431,6 +395,8 @@ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm) */ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) { + int ret = -EINVAL; + if (!pwrdm) return -EINVAL; @@ -440,11 +406,10 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) pr_debug("powerdomain: setting next powerstate for %s to %0x\n", pwrdm->name, pwrst); - prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, - (pwrst << OMAP_POWERSTATE_SHIFT), - pwrdm->prcm_offs, pwrstctrl_reg_offs); + if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) + ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst); - return 0; + return ret; } /** @@ -457,11 +422,15 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) */ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm) { + int ret = -EINVAL; + if (!pwrdm) return -EINVAL; - return prm_read_mod_bits_shift(pwrdm->prcm_offs, - pwrstctrl_reg_offs, OMAP_POWERSTATE_MASK); + if (arch_pwrdm && arch_pwrdm->pwrdm_read_next_pwrst) + ret = arch_pwrdm->pwrdm_read_next_pwrst(pwrdm); + + return ret; } /** @@ -474,11 +443,15 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm) */ int pwrdm_read_pwrst(struct powerdomain *pwrdm) { + int ret = -EINVAL; + if (!pwrdm) return -EINVAL; - return prm_read_mod_bits_shift(pwrdm->prcm_offs, - pwrstst_reg_offs, OMAP_POWERSTATEST_MASK); + if (arch_pwrdm && arch_pwrdm->pwrdm_read_pwrst) + ret = arch_pwrdm->pwrdm_read_pwrst(pwrdm); + + return ret; } /** @@ -491,11 +464,15 @@ int pwrdm_read_pwrst(struct powerdomain *pwrdm) */ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) { + int ret = -EINVAL; + if (!pwrdm) return -EINVAL; - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, - OMAP3430_LASTPOWERSTATEENTERED_MASK); + if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_pwrst) + ret = arch_pwrdm->pwrdm_read_prev_pwrst(pwrdm); + + return ret; } /** @@ -511,7 +488,7 @@ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) */ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) { - u32 v; + int ret = -EINVAL; if (!pwrdm) return -EINVAL; @@ -522,17 +499,10 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n", pwrdm->name, pwrst); - /* - * The register bit names below may not correspond to the - * actual names of the bits in each powerdomain's register, - * but the type of value returned is the same for each - * powerdomain. - */ - v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK); - prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v, - pwrdm->prcm_offs, pwrstctrl_reg_offs); + if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst) + ret = arch_pwrdm->pwrdm_set_logic_retst(pwrdm, pwrst); - return 0; + return ret; } /** @@ -552,7 +522,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) */ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) { - u32 m; + int ret = -EINVAL; if (!pwrdm) return -EINVAL; @@ -566,37 +536,10 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) pr_debug("powerdomain: setting next memory powerstate for domain %s " "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst); - /* - * The register bit names below may not correspond to the - * actual names of the bits in each powerdomain's register, - * but the type of value returned is the same for each - * powerdomain. - */ - switch (bank) { - case 0: - m = OMAP_MEM0_ONSTATE_MASK; - break; - case 1: - m = OMAP_MEM1_ONSTATE_MASK; - break; - case 2: - m = OMAP_MEM2_ONSTATE_MASK; - break; - case 3: - m = OMAP_MEM3_ONSTATE_MASK; - break; - case 4: - m = OMAP_MEM4_ONSTATE_MASK; - break; - default: - WARN_ON(1); /* should never happen */ - return -EEXIST; - } + if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_onst) + ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst); - prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), - pwrdm->prcm_offs, pwrstctrl_reg_offs); - - return 0; + return ret; } /** @@ -617,7 +560,7 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) */ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) { - u32 m; + int ret = -EINVAL; if (!pwrdm) return -EINVAL; @@ -631,37 +574,10 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) pr_debug("powerdomain: setting next memory powerstate for domain %s " "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst); - /* - * The register bit names below may not correspond to the - * actual names of the bits in each powerdomain's register, - * but the type of value returned is the same for each - * powerdomain. - */ - switch (bank) { - case 0: - m = OMAP_MEM0_RETSTATE_MASK; - break; - case 1: - m = OMAP_MEM1_RETSTATE_MASK; - break; - case 2: - m = OMAP_MEM2_RETSTATE_MASK; - break; - case 3: - m = OMAP_MEM3_RETSTATE_MASK; - break; - case 4: - m = OMAP_MEM4_RETSTATE_MASK; - break; - default: - WARN_ON(1); /* should never happen */ - return -EEXIST; - } - - prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, - pwrstctrl_reg_offs); + if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_retst) + ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst); - return 0; + return ret; } /** @@ -675,11 +591,15 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) */ int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) { + int ret = -EINVAL; + if (!pwrdm) return -EINVAL; - return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstst_reg_offs, - OMAP3430_LOGICSTATEST_MASK); + if (arch_pwrdm && arch_pwrdm->pwrdm_read_logic_pwrst) + ret = arch_pwrdm->pwrdm_read_logic_pwrst(pwrdm); + + return ret; } /** @@ -692,17 +612,15 @@ int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) */ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) { + int ret = -EINVAL; + if (!pwrdm) return -EINVAL; - /* - * The register bit names below may not correspond to the - * actual names of the bits in each powerdomain's register, - * but the type of value returned is the same for each - * powerdomain. - */ - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, - OMAP3430_LASTLOGICSTATEENTERED_MASK); + if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_logic_pwrst) + ret = arch_pwrdm->pwrdm_read_prev_logic_pwrst(pwrdm); + + return ret; } /** @@ -715,17 +633,15 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) */ int pwrdm_read_logic_retst(struct powerdomain *pwrdm) { + int ret = -EINVAL; + if (!pwrdm) return -EINVAL; - /* - * The register bit names below may not correspond to the - * actual names of the bits in each powerdomain's register, - * but the type of value returned is the same for each - * powerdomain. - */ - return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstctrl_reg_offs, - OMAP3430_LOGICSTATEST_MASK); + if (arch_pwrdm && arch_pwrdm->pwrdm_read_logic_retst) + ret = arch_pwrdm->pwrdm_read_logic_retst(pwrdm); + + return ret; } /** @@ -740,46 +656,21 @@ int pwrdm_read_logic_retst(struct powerdomain *pwrdm) */ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) { - u32 m; + int ret = -EINVAL; if (!pwrdm) - return -EINVAL; + return ret; if (pwrdm->banks < (bank + 1)) - return -EEXIST; + return ret; if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK) bank = 1; - /* - * The register bit names below may not correspond to the - * actual names of the bits in each powerdomain's register, - * but the type of value returned is the same for each - * powerdomain. - */ - switch (bank) { - case 0: - m = OMAP_MEM0_STATEST_MASK; - break; - case 1: - m = OMAP_MEM1_STATEST_MASK; - break; - case 2: - m = OMAP_MEM2_STATEST_MASK; - break; - case 3: - m = OMAP_MEM3_STATEST_MASK; - break; - case 4: - m = OMAP_MEM4_STATEST_MASK; - break; - default: - WARN_ON(1); /* should never happen */ - return -EEXIST; - } + if (arch_pwrdm && arch_pwrdm->pwrdm_read_mem_pwrst) + ret = arch_pwrdm->pwrdm_read_mem_pwrst(pwrdm, bank); - return prm_read_mod_bits_shift(pwrdm->prcm_offs, - pwrstst_reg_offs, m); + return ret; } /** @@ -795,43 +686,21 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) */ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) { - u32 m; + int ret = -EINVAL; if (!pwrdm) - return -EINVAL; + return ret; if (pwrdm->banks < (bank + 1)) - return -EEXIST; + return ret; if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK) bank = 1; - /* - * The register bit names below may not correspond to the - * actual names of the bits in each powerdomain's register, - * but the type of value returned is the same for each - * powerdomain. - */ - switch (bank) { - case 0: - m = OMAP3430_LASTMEM1STATEENTERED_MASK; - break; - case 1: - m = OMAP3430_LASTMEM2STATEENTERED_MASK; - break; - case 2: - m = OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK; - break; - case 3: - m = OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK; - break; - default: - WARN_ON(1); /* should never happen */ - return -EEXIST; - } + if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_mem_pwrst) + ret = arch_pwrdm->pwrdm_read_prev_mem_pwrst(pwrdm, bank); - return prm_read_mod_bits_shift(pwrdm->prcm_offs, - OMAP3430_PM_PREPWSTST, m); + return ret; } /** @@ -846,43 +715,18 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) */ int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) { - u32 m; + int ret = -EINVAL; if (!pwrdm) - return -EINVAL; + return ret; if (pwrdm->banks < (bank + 1)) - return -EEXIST; + return ret; - /* - * The register bit names below may not correspond to the - * actual names of the bits in each powerdomain's register, - * but the type of value returned is the same for each - * powerdomain. - */ - switch (bank) { - case 0: - m = OMAP_MEM0_RETSTATE_MASK; - break; - case 1: - m = OMAP_MEM1_RETSTATE_MASK; - break; - case 2: - m = OMAP_MEM2_RETSTATE_MASK; - break; - case 3: - m = OMAP_MEM3_RETSTATE_MASK; - break; - case 4: - m = OMAP_MEM4_RETSTATE_MASK; - break; - default: - WARN_ON(1); /* should never happen */ - return -EEXIST; - } + if (arch_pwrdm && arch_pwrdm->pwrdm_read_mem_retst) + ret = arch_pwrdm->pwrdm_read_mem_retst(pwrdm, bank); - return prm_read_mod_bits_shift(pwrdm->prcm_offs, - pwrstctrl_reg_offs, m); + return ret; } /** @@ -896,8 +740,10 @@ int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) */ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) { + int ret = -EINVAL; + if (!pwrdm) - return -EINVAL; + return ret; /* * XXX should get the powerdomain's current state here; @@ -907,9 +753,10 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) pr_debug("powerdomain: clearing previous power state reg for %s\n", pwrdm->name); - prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); + if (arch_pwrdm && arch_pwrdm->pwrdm_clear_all_prev_pwrst) + ret = arch_pwrdm->pwrdm_clear_all_prev_pwrst(pwrdm); - return 0; + return ret; } /** @@ -925,19 +772,21 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) */ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) { + int ret = -EINVAL; + if (!pwrdm) - return -EINVAL; + return ret; if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) - return -EINVAL; + return ret; pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", pwrdm->name); - prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, - pwrdm->prcm_offs, pwrstctrl_reg_offs); + if (arch_pwrdm && arch_pwrdm->pwrdm_enable_hdwr_sar) + ret = arch_pwrdm->pwrdm_enable_hdwr_sar(pwrdm); - return 0; + return ret; } /** @@ -953,19 +802,21 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) */ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) { + int ret = -EINVAL; + if (!pwrdm) - return -EINVAL; + return ret; if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) - return -EINVAL; + return ret; pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", pwrdm->name); - prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0, - pwrdm->prcm_offs, pwrstctrl_reg_offs); + if (arch_pwrdm && arch_pwrdm->pwrdm_disable_hdwr_sar) + ret = arch_pwrdm->pwrdm_disable_hdwr_sar(pwrdm); - return 0; + return ret; } /** @@ -992,6 +843,8 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm) */ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) { + int ret = -EINVAL; + if (!pwrdm) return -EINVAL; @@ -1001,11 +854,10 @@ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) pr_debug("powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n", pwrdm->name); - prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, - (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT), - pwrdm->prcm_offs, pwrstctrl_reg_offs); + if (arch_pwrdm && arch_pwrdm->pwrdm_set_lowpwrstchange) + ret = arch_pwrdm->pwrdm_set_lowpwrstchange(pwrdm); - return 0; + return ret; } /** @@ -1020,32 +872,15 @@ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) */ int pwrdm_wait_transition(struct powerdomain *pwrdm) { - u32 c = 0; + int ret = -EINVAL; if (!pwrdm) return -EINVAL; - /* - * REVISIT: pwrdm_wait_transition() may be better implemented - * via a callback and a periodic timer check -- how long do we expect - * powerdomain transitions to take? - */ - - /* XXX Is this udelay() value meaningful? */ - while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) & - OMAP_INTRANSITION_MASK) && - (c++ < PWRDM_TRANSITION_BAILOUT)) - udelay(1); - - if (c > PWRDM_TRANSITION_BAILOUT) { - printk(KERN_ERR "powerdomain: waited too long for " - "powerdomain %s to complete transition\n", pwrdm->name); - return -EAGAIN; - } - - pr_debug("powerdomain: completed transition in %d loops\n", c); + if (arch_pwrdm && arch_pwrdm->pwrdm_wait_transition) + ret = arch_pwrdm->pwrdm_wait_transition(pwrdm); - return 0; + return ret; } int pwrdm_state_switch(struct powerdomain *pwrdm) @@ -1075,3 +910,31 @@ int pwrdm_post_transition(void) return 0; } +/** + * pwrdm_get_context_loss_count - get powerdomain's context loss count + * @pwrdm: struct powerdomain * to wait for + * + * Context loss count is the sum of powerdomain off-mode counter, the + * logic off counter and the per-bank memory off counter. Returns 0 + * (and WARNs) upon error, otherwise, returns the context loss count. + */ +u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm) +{ + int i, count; + + if (!pwrdm) { + WARN(1, "powerdomain: %s: pwrdm is null\n", __func__); + return 0; + } + + count = pwrdm->state_counter[PWRDM_POWER_OFF]; + count += pwrdm->ret_logic_off_counter; + + for (i = 0; i < pwrdm->banks; i++) + count += pwrdm->ret_mem_off_counter[i]; + + pr_debug("powerdomain: %s: context loss count = %u\n", + pwrdm->name, count); + + return count; +} diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h new file mode 100644 index 000000000000..c66431edfeb7 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomain.h @@ -0,0 +1,233 @@ +/* + * OMAP2/3/4 powerdomain control + * + * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc. + * Copyright (C) 2007-2010 Nokia Corporation + * + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX This should be moved to the mach-omap2/ directory at the earliest + * opportunity. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H +#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H + +#include <linux/types.h> +#include <linux/list.h> + +#include <linux/atomic.h> + +#include <plat/cpu.h> + +/* Powerdomain basic power states */ +#define PWRDM_POWER_OFF 0x0 +#define PWRDM_POWER_RET 0x1 +#define PWRDM_POWER_INACTIVE 0x2 +#define PWRDM_POWER_ON 0x3 + +#define PWRDM_MAX_PWRSTS 4 + +/* Powerdomain allowable state bitfields */ +#define PWRSTS_ON (1 << PWRDM_POWER_ON) +#define PWRSTS_OFF (1 << PWRDM_POWER_OFF) +#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ + (1 << PWRDM_POWER_ON)) + +#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ + (1 << PWRDM_POWER_RET)) + +#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ + (1 << PWRDM_POWER_ON)) + +#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) + + +/* Powerdomain flags */ +#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ +#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits + * in MEM bank 1 position. This is + * true for OMAP3430 + */ +#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* + * support to transition from a + * sleep state to a lower sleep + * state without waking up the + * powerdomain + */ + +/* + * Number of memory banks that are power-controllable. On OMAP4430, the + * maximum is 5. + */ +#define PWRDM_MAX_MEM_BANKS 5 + +/* + * Maximum number of clockdomains that can be associated with a powerdomain. + * CORE powerdomain on OMAP4 is the worst case + */ +#define PWRDM_MAX_CLKDMS 9 + +/* XXX A completely arbitrary number. What is reasonable here? */ +#define PWRDM_TRANSITION_BAILOUT 100000 + +struct clockdomain; +struct powerdomain; + +/** + * struct powerdomain - OMAP powerdomain + * @name: Powerdomain name + * @omap_chip: represents the OMAP chip types containing this pwrdm + * @prcm_offs: the address offset from CM_BASE/PRM_BASE + * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs + * @pwrsts: Possible powerdomain power states + * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION + * @flags: Powerdomain flags + * @banks: Number of software-controllable memory banks in this powerdomain + * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION + * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON + * @pwrdm_clkdms: Clockdomains in this powerdomain + * @node: list_head linking all powerdomains + * @state: + * @state_counter: + * @timer: + * @state_timer: + * + * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h. + */ +struct powerdomain { + const char *name; + const struct omap_chip_id omap_chip; + const s16 prcm_offs; + const u8 pwrsts; + const u8 pwrsts_logic_ret; + const u8 flags; + const u8 banks; + const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; + const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; + const u8 prcm_partition; + struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; + struct list_head node; + int state; + unsigned state_counter[PWRDM_MAX_PWRSTS]; + unsigned ret_logic_off_counter; + unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; + +#ifdef CONFIG_PM_DEBUG + s64 timer; + s64 state_timer[PWRDM_MAX_PWRSTS]; +#endif +}; + +/** + * struct pwrdm_ops - Arch specfic function implementations + * @pwrdm_set_next_pwrst: Set the target power state for a pd + * @pwrdm_read_next_pwrst: Read the target power state set for a pd + * @pwrdm_read_pwrst: Read the current power state of a pd + * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd + * @pwrdm_set_logic_retst: Set the logic state in RET for a pd + * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd + * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd + * @pwrdm_read_logic_pwrst: Read the current logic state of a pd + * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd + * @pwrdm_read_logic_retst: Read the logic state in RET for a pd + * @pwrdm_read_mem_pwrst: Read the current memory state of a pd + * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd + * @pwrdm_read_mem_retst: Read the memory state in RET for a pd + * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd + * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd + * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd + * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep + * @pwrdm_wait_transition: Wait for a pd state transition to complete + */ +struct pwrdm_ops { + int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst); + int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst); + int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); + int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); + int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm); + int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); + int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); + int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank); + int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm); + int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm); + int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); + int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); +}; + +void pwrdm_fw_init(void); +void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs); + +struct powerdomain *pwrdm_lookup(const char *name); + +int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), + void *user); +int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), + void *user); + +int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); +int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); +int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, + int (*fn)(struct powerdomain *pwrdm, + struct clockdomain *clkdm)); + +int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); + +int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); +int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); +int pwrdm_read_pwrst(struct powerdomain *pwrdm); +int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); +int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); + +int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); +int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); +int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); + +int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); +int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); +int pwrdm_read_logic_retst(struct powerdomain *pwrdm); +int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); +int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); +int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); + +int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); +int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); +bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); + +int pwrdm_wait_transition(struct powerdomain *pwrdm); + +int pwrdm_state_switch(struct powerdomain *pwrdm); +int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); +int pwrdm_pre_transition(void); +int pwrdm_post_transition(void); +int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); +u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm); + +extern void omap2xxx_powerdomains_init(void); +extern void omap3xxx_powerdomains_init(void); +extern void omap44xx_powerdomains_init(void); + +extern struct pwrdm_ops omap2_pwrdm_operations; +extern struct pwrdm_ops omap3_pwrdm_operations; +extern struct pwrdm_ops omap4_pwrdm_operations; + +/* Common Internal functions used across OMAP rev's */ +extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank); +extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank); +extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank); + +extern struct powerdomain wkup_omap2_pwrdm; +extern struct powerdomain gfx_omap2_pwrdm; + + +#endif diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c new file mode 100644 index 000000000000..d5233890370c --- /dev/null +++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c @@ -0,0 +1,242 @@ +/* + * OMAP2 and OMAP3 powerdomain control + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2007-2009 Nokia Corporation + * + * Derived from mach-omap2/powerdomain.c written by Paul Walmsley + * Rajendra Nayak <rnayak@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/io.h> +#include <linux/errno.h> +#include <linux/delay.h> + +#include <plat/prcm.h> + +#include "powerdomain.h" +#include "prm-regbits-34xx.h" +#include "prm.h" +#include "prm-regbits-24xx.h" +#include "prm-regbits-34xx.h" + + +/* Common functions across OMAP2 and OMAP3 */ +static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) +{ + omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, + (pwrst << OMAP_POWERSTATE_SHIFT), + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); + return 0; +} + +static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) +{ + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL, + OMAP_POWERSTATE_MASK); +} + +static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm) +{ + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTST, + OMAP_POWERSTATEST_MASK); +} + +static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst) +{ + u32 m; + + m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); + + omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL); + + return 0; +} + +static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst) +{ + u32 m; + + m = omap2_pwrdm_get_mem_bank_retst_mask(bank); + + omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL); + + return 0; +} + +static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) +{ + u32 m; + + m = omap2_pwrdm_get_mem_bank_stst_mask(bank); + + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, + m); +} + +static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) +{ + u32 m; + + m = omap2_pwrdm_get_mem_bank_retst_mask(bank); + + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL, m); +} + +static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) +{ + u32 v; + + v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK); + omap2_prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v, + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); + + return 0; +} + +static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm) +{ + u32 c = 0; + + /* + * REVISIT: pwrdm_wait_transition() may be better implemented + * via a callback and a periodic timer check -- how long do we expect + * powerdomain transitions to take? + */ + + /* XXX Is this udelay() value meaningful? */ + while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) & + OMAP_INTRANSITION_MASK) && + (c++ < PWRDM_TRANSITION_BAILOUT)) + udelay(1); + + if (c > PWRDM_TRANSITION_BAILOUT) { + printk(KERN_ERR "powerdomain: waited too long for " + "powerdomain %s to complete transition\n", pwrdm->name); + return -EAGAIN; + } + + pr_debug("powerdomain: completed transition in %d loops\n", c); + + return 0; +} + +/* Applicable only for OMAP3. Not supported on OMAP2 */ +static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) +{ + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP3430_PM_PREPWSTST, + OMAP3430_LASTPOWERSTATEENTERED_MASK); +} + +static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) +{ + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTST, + OMAP3430_LOGICSTATEST_MASK); +} + +static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm) +{ + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL, + OMAP3430_LOGICSTATEST_MASK); +} + +static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) +{ + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP3430_PM_PREPWSTST, + OMAP3430_LASTLOGICSTATEENTERED_MASK); +} + +static int omap3_get_mem_bank_lastmemst_mask(u8 bank) +{ + switch (bank) { + case 0: + return OMAP3430_LASTMEM1STATEENTERED_MASK; + case 1: + return OMAP3430_LASTMEM2STATEENTERED_MASK; + case 2: + return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK; + case 3: + return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK; + default: + WARN_ON(1); /* should never happen */ + return -EEXIST; + } + return 0; +} + +static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) +{ + u32 m; + + m = omap3_get_mem_bank_lastmemst_mask(bank); + + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP3430_PM_PREPWSTST, m); +} + +static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) +{ + omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); + return 0; +} + +static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) +{ + return omap2_prm_rmw_mod_reg_bits(0, + 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); +} + +static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) +{ + return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, + 0, pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL); +} + +struct pwrdm_ops omap2_pwrdm_operations = { + .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, + .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, + .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, + .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, + .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst, + .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst, + .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst, + .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst, + .pwrdm_wait_transition = omap2_pwrdm_wait_transition, +}; + +struct pwrdm_ops omap3_pwrdm_operations = { + .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, + .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, + .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, + .pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst, + .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, + .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst, + .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst, + .pwrdm_read_prev_logic_pwrst = omap3_pwrdm_read_prev_logic_pwrst, + .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst, + .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst, + .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst, + .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst, + .pwrdm_read_prev_mem_pwrst = omap3_pwrdm_read_prev_mem_pwrst, + .pwrdm_clear_all_prev_pwrst = omap3_pwrdm_clear_all_prev_pwrst, + .pwrdm_enable_hdwr_sar = omap3_pwrdm_enable_hdwr_sar, + .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar, + .pwrdm_wait_transition = omap2_pwrdm_wait_transition, +}; diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c new file mode 100644 index 000000000000..a7880af4b3d9 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomain44xx.c @@ -0,0 +1,225 @@ +/* + * OMAP4 powerdomain control + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2007-2009 Nokia Corporation + * + * Derived from mach-omap2/powerdomain.c written by Paul Walmsley + * Rajendra Nayak <rnayak@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/io.h> +#include <linux/errno.h> +#include <linux/delay.h> + +#include "powerdomain.h" +#include <plat/prcm.h> +#include "prm2xxx_3xxx.h" +#include "prm44xx.h" +#include "prminst44xx.h" +#include "prm-regbits-44xx.h" + +static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) +{ + omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK, + (pwrst << OMAP_POWERSTATE_SHIFT), + pwrdm->prcm_partition, + pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); + return 0; +} + +static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL); + v &= OMAP_POWERSTATE_MASK; + v >>= OMAP_POWERSTATE_SHIFT; + + return v; +} + +static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTST); + v &= OMAP_POWERSTATEST_MASK; + v >>= OMAP_POWERSTATEST_SHIFT; + + return v; +} + +static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTST); + v &= OMAP4430_LASTPOWERSTATEENTERED_MASK; + v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT; + + return v; +} + +static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) +{ + omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, + (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT), + pwrdm->prcm_partition, + pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); + return 0; +} + +static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) +{ + omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK, + OMAP4430_LASTPOWERSTATEENTERED_MASK, + pwrdm->prcm_partition, + pwrdm->prcm_offs, OMAP4_PM_PWSTST); + return 0; +} + +static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) +{ + u32 v; + + v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK); + omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v, + pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL); + + return 0; +} + +static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst) +{ + u32 m; + + m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); + + omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)), + pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL); + + return 0; +} + +static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst) +{ + u32 m; + + m = omap2_pwrdm_get_mem_bank_retst_mask(bank); + + omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)), + pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL); + + return 0; +} + +static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTST); + v &= OMAP4430_LOGICSTATEST_MASK; + v >>= OMAP4430_LOGICSTATEST_SHIFT; + + return v; +} + +static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm) +{ + u32 v; + + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL); + v &= OMAP4430_LOGICRETSTATE_MASK; + v >>= OMAP4430_LOGICRETSTATE_SHIFT; + + return v; +} + +static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) +{ + u32 m, v; + + m = omap2_pwrdm_get_mem_bank_stst_mask(bank); + + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTST); + v &= m; + v >>= __ffs(m); + + return v; +} + +static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) +{ + u32 m, v; + + m = omap2_pwrdm_get_mem_bank_retst_mask(bank); + + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL); + v &= m; + v >>= __ffs(m); + + return v; +} + +static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) +{ + u32 c = 0; + + /* + * REVISIT: pwrdm_wait_transition() may be better implemented + * via a callback and a periodic timer check -- how long do we expect + * powerdomain transitions to take? + */ + + /* XXX Is this udelay() value meaningful? */ + while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition, + pwrdm->prcm_offs, + OMAP4_PM_PWSTST) & + OMAP_INTRANSITION_MASK) && + (c++ < PWRDM_TRANSITION_BAILOUT)) + udelay(1); + + if (c > PWRDM_TRANSITION_BAILOUT) { + printk(KERN_ERR "powerdomain: waited too long for " + "powerdomain %s to complete transition\n", pwrdm->name); + return -EAGAIN; + } + + pr_debug("powerdomain: completed transition in %d loops\n", c); + + return 0; +} + +struct pwrdm_ops omap4_pwrdm_operations = { + .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst, + .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst, + .pwrdm_read_pwrst = omap4_pwrdm_read_pwrst, + .pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst, + .pwrdm_set_lowpwrstchange = omap4_pwrdm_set_lowpwrstchange, + .pwrdm_clear_all_prev_pwrst = omap4_pwrdm_clear_all_prev_pwrst, + .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst, + .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst, + .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst, + .pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst, + .pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst, + .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst, + .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst, + .pwrdm_wait_transition = omap4_pwrdm_wait_transition, +}; diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c index 105cbcaefd3b..5b4dd971320a 100644 --- a/arch/arm/mach-omap2/powerdomains.h +++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c @@ -2,10 +2,9 @@ * OMAP2/3 common powerdomain definitions * * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2009 Nokia Corporation + * Copyright (C) 2007-2010 Nokia Corporation * - * Written by Paul Walmsley - * Debugging and integration fixes by Jouni Högander + * Paul Walmsley, Jouni Högander * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -18,9 +17,6 @@ * Clock Domain Framework */ -#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS -#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS - /* * This file contains all of the powerdomains that have some element * of software control for the OMAP24xx and OMAP34xx chips. @@ -49,24 +45,18 @@ * address offset is different between the C55 and C64 DSPs. */ -#include <plat/powerdomain.h> +#include "powerdomain.h" #include "prcm-common.h" #include "prm.h" -#include "cm.h" -#include "powerdomains24xx.h" -#include "powerdomains34xx.h" -#include "powerdomains44xx.h" /* OMAP2/3-common powerdomains */ -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - /* * The GFX powerdomain is not present on 3430ES2, but currently we do not * have a macro to filter it out at compile-time. */ -static struct powerdomain gfx_omap2_pwrdm = { +struct powerdomain gfx_omap2_pwrdm = { .name = "gfx_pwrdm", .prcm_offs = GFX_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | @@ -82,72 +72,8 @@ static struct powerdomain gfx_omap2_pwrdm = { }, }; -static struct powerdomain wkup_omap2_pwrdm = { +struct powerdomain wkup_omap2_pwrdm = { .name = "wkup_pwrdm", .prcm_offs = WKUP_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), }; - -#endif - - -/* As powerdomains are added or removed above, this list must also be changed */ -static struct powerdomain *powerdomains_omap[] __initdata = { - -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - &wkup_omap2_pwrdm, - &gfx_omap2_pwrdm, -#endif - -#ifdef CONFIG_ARCH_OMAP2 - &dsp_pwrdm, - &mpu_24xx_pwrdm, - &core_24xx_pwrdm, -#endif - -#ifdef CONFIG_ARCH_OMAP2430 - &mdm_pwrdm, -#endif - -#ifdef CONFIG_ARCH_OMAP3 - &iva2_pwrdm, - &mpu_3xxx_pwrdm, - &neon_pwrdm, - &core_3xxx_pre_es3_1_pwrdm, - &core_3xxx_es3_1_pwrdm, - &cam_pwrdm, - &dss_pwrdm, - &per_pwrdm, - &emu_pwrdm, - &sgx_pwrdm, - &usbhost_pwrdm, - &dpll1_pwrdm, - &dpll2_pwrdm, - &dpll3_pwrdm, - &dpll4_pwrdm, - &dpll5_pwrdm, -#endif - -#ifdef CONFIG_ARCH_OMAP4 - &core_44xx_pwrdm, - &gfx_44xx_pwrdm, - &abe_44xx_pwrdm, - &dss_44xx_pwrdm, - &tesla_44xx_pwrdm, - &wkup_44xx_pwrdm, - &cpu0_44xx_pwrdm, - &cpu1_44xx_pwrdm, - &emu_44xx_pwrdm, - &mpu_44xx_pwrdm, - &ivahd_44xx_pwrdm, - &cam_44xx_pwrdm, - &l3init_44xx_pwrdm, - &l4per_44xx_pwrdm, - &always_on_core_44xx_pwrdm, - &cefuse_44xx_pwrdm, -#endif - NULL -}; - - -#endif diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h new file mode 100644 index 000000000000..fa311669d53d --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h @@ -0,0 +1,22 @@ +/* + * OMAP2/3 common powerdomains - prototypes + * + * Copyright (C) 2008 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation + * + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H +#define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H + +#include "powerdomain.h" + +extern struct powerdomain gfx_omap2_pwrdm; +extern struct powerdomain wkup_omap2_pwrdm; + +#endif diff --git a/arch/arm/mach-omap2/powerdomains24xx.h b/arch/arm/mach-omap2/powerdomains2xxx_data.c index 775093add9b6..9b1a33500577 100644 --- a/arch/arm/mach-omap2/powerdomains24xx.h +++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c @@ -1,37 +1,28 @@ /* - * OMAP24XX powerdomain definitions + * OMAP2XXX powerdomain definitions * * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2009 Nokia Corporation + * Copyright (C) 2007-2010 Nokia Corporation * - * Written by Paul Walmsley - * Debugging and integration fixes by Jouni Högander + * Paul Walmsley, Jouni Högander * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX -#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX +#include <linux/kernel.h> +#include <linux/init.h> -/* - * N.B. If powerdomains are added or removed from this file, update - * the array in mach-omap2/powerdomains.h. - */ - -#include <plat/powerdomain.h> +#include "powerdomain.h" +#include "powerdomains2xxx_3xxx_data.h" #include "prcm-common.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" -#include "cm.h" -#include "cm-regbits-24xx.h" /* 24XX powerdomains and dependencies */ -#ifdef CONFIG_ARCH_OMAP2 - /* Powerdomains */ static struct powerdomain dsp_pwrdm = { @@ -82,9 +73,6 @@ static struct powerdomain core_24xx_pwrdm = { }, }; -#endif /* CONFIG_ARCH_OMAP2 */ - - /* * 2430-specific powerdomains @@ -111,5 +99,25 @@ static struct powerdomain mdm_pwrdm = { #endif /* CONFIG_ARCH_OMAP2430 */ +/* As powerdomains are added or removed above, this list must also be changed */ +static struct powerdomain *powerdomains_omap2xxx[] __initdata = { + &wkup_omap2_pwrdm, + &gfx_omap2_pwrdm, + +#ifdef CONFIG_ARCH_OMAP2 + &dsp_pwrdm, + &mpu_24xx_pwrdm, + &core_24xx_pwrdm, #endif + +#ifdef CONFIG_ARCH_OMAP2430 + &mdm_pwrdm, +#endif + NULL +}; + +void __init omap2xxx_powerdomains_init(void) +{ + pwrdm_init(powerdomains_omap2xxx, &omap2_pwrdm_operations); +} diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains3xxx_data.c index fa904861668b..e1bec562625b 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -4,28 +4,23 @@ * Copyright (C) 2007-2008 Texas Instruments, Inc. * Copyright (C) 2007-2010 Nokia Corporation * - * Written by Paul Walmsley - * Debugging and integration fixes by Jouni Högander + * Paul Walmsley, Jouni Högander * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX -#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX +#include <linux/kernel.h> +#include <linux/init.h> -/* - * N.B. If powerdomains are added or removed from this file, update - * the array in mach-omap2/powerdomains.h. - */ - -#include <plat/powerdomain.h> +#include "powerdomain.h" +#include "powerdomains2xxx_3xxx_data.h" #include "prcm-common.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-34xx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" /* @@ -80,6 +75,10 @@ static struct powerdomain mpu_3xxx_pwrdm = { * 3430s upto ES3.0 and 3630ES1.0. Hence this feature * needs to be disabled on these chips. * Refer: 3430 errata ID i459 and 3630 errata ID i579 + * + * Note: setting the SAR flag could help for errata ID i478 + * which applies to 3430 <= ES3.1, but since the SAR feature + * is broken, do not use it. */ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { .name = "core_pwrdm", @@ -108,6 +107,10 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = { CHIP_GE_OMAP3630ES1_1), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, + /* + * Setting the SAR flag for errata ID i478 which applies + * to 3430 <= ES3.1 + */ .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ .banks = 2, .pwrsts_mem_ret = { @@ -252,8 +255,33 @@ static struct powerdomain dpll5_pwrdm = { .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), }; +/* As powerdomains are added or removed above, this list must also be changed */ +static struct powerdomain *powerdomains_omap3xxx[] __initdata = { -#endif /* CONFIG_ARCH_OMAP3 */ + &wkup_omap2_pwrdm, + &gfx_omap2_pwrdm, + &iva2_pwrdm, + &mpu_3xxx_pwrdm, + &neon_pwrdm, + &core_3xxx_pre_es3_1_pwrdm, + &core_3xxx_es3_1_pwrdm, + &cam_pwrdm, + &dss_pwrdm, + &per_pwrdm, + &emu_pwrdm, + &sgx_pwrdm, + &usbhost_pwrdm, + &dpll1_pwrdm, + &dpll2_pwrdm, + &dpll3_pwrdm, + &dpll4_pwrdm, + &dpll5_pwrdm, +#endif + NULL +}; -#endif +void __init omap3xxx_powerdomains_init(void) +{ + pwrdm_init(powerdomains_omap3xxx, &omap3_pwrdm_operations); +} diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx_data.c index 9c01b55d6102..26d7641076d7 100644 --- a/arch/arm/mach-omap2/powerdomains44xx.h +++ b/arch/arm/mach-omap2/powerdomains44xx_data.c @@ -19,23 +19,22 @@ * published by the Free Software Foundation. */ -#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H -#define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H +#include <linux/kernel.h> +#include <linux/init.h> -#include <plat/powerdomain.h> +#include "powerdomain.h" #include "prcm-common.h" -#include "cm.h" -#include "cm-regbits-44xx.h" -#include "prm.h" +#include "prcm44xx.h" #include "prm-regbits-44xx.h" - -#if defined(CONFIG_ARCH_OMAP4) +#include "prm44xx.h" +#include "prcm_mpu44xx.h" /* core_44xx_pwrdm: CORE power domain */ static struct powerdomain core_44xx_pwrdm = { .name = "core_pwrdm", - .prcm_offs = OMAP4430_PRM_CORE_MOD, + .prcm_offs = OMAP4430_PRM_CORE_INST, + .prcm_partition = OMAP4430_PRM_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, @@ -60,7 +59,8 @@ static struct powerdomain core_44xx_pwrdm = { /* gfx_44xx_pwrdm: 3D accelerator power domain */ static struct powerdomain gfx_44xx_pwrdm = { .name = "gfx_pwrdm", - .prcm_offs = OMAP4430_PRM_GFX_MOD, + .prcm_offs = OMAP4430_PRM_GFX_INST, + .prcm_partition = OMAP4430_PRM_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_ON, .banks = 1, @@ -76,7 +76,8 @@ static struct powerdomain gfx_44xx_pwrdm = { /* abe_44xx_pwrdm: Audio back end power domain */ static struct powerdomain abe_44xx_pwrdm = { .name = "abe_pwrdm", - .prcm_offs = OMAP4430_PRM_ABE_MOD, + .prcm_offs = OMAP4430_PRM_ABE_INST, + .prcm_partition = OMAP4430_PRM_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRDM_POWER_OFF, @@ -95,7 +96,8 @@ static struct powerdomain abe_44xx_pwrdm = { /* dss_44xx_pwrdm: Display subsystem power domain */ static struct powerdomain dss_44xx_pwrdm = { .name = "dss_pwrdm", - .prcm_offs = OMAP4430_PRM_DSS_MOD, + .prcm_offs = OMAP4430_PRM_DSS_INST, + .prcm_partition = OMAP4430_PRM_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF, @@ -112,7 +114,8 @@ static struct powerdomain dss_44xx_pwrdm = { /* tesla_44xx_pwrdm: Tesla processor power domain */ static struct powerdomain tesla_44xx_pwrdm = { .name = "tesla_pwrdm", - .prcm_offs = OMAP4430_PRM_TESLA_MOD, + .prcm_offs = OMAP4430_PRM_TESLA_INST, + .prcm_partition = OMAP4430_PRM_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, @@ -133,7 +136,8 @@ static struct powerdomain tesla_44xx_pwrdm = { /* wkup_44xx_pwrdm: Wake-up power domain */ static struct powerdomain wkup_44xx_pwrdm = { .name = "wkup_pwrdm", - .prcm_offs = OMAP4430_PRM_WKUP_MOD, + .prcm_offs = OMAP4430_PRM_WKUP_INST, + .prcm_partition = OMAP4430_PRM_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_ON, .banks = 1, @@ -148,7 +152,8 @@ static struct powerdomain wkup_44xx_pwrdm = { /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ static struct powerdomain cpu0_44xx_pwrdm = { .name = "cpu0_pwrdm", - .prcm_offs = OMAP4430_PRCM_MPU_CPU0_MOD, + .prcm_offs = OMAP4430_PRCM_MPU_CPU0_INST, + .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, @@ -164,7 +169,8 @@ static struct powerdomain cpu0_44xx_pwrdm = { /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ static struct powerdomain cpu1_44xx_pwrdm = { .name = "cpu1_pwrdm", - .prcm_offs = OMAP4430_PRCM_MPU_CPU1_MOD, + .prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST, + .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, @@ -180,7 +186,8 @@ static struct powerdomain cpu1_44xx_pwrdm = { /* emu_44xx_pwrdm: Emulation power domain */ static struct powerdomain emu_44xx_pwrdm = { .name = "emu_pwrdm", - .prcm_offs = OMAP4430_PRM_EMU_MOD, + .prcm_offs = OMAP4430_PRM_EMU_INST, + .prcm_partition = OMAP4430_PRM_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_ON, .banks = 1, @@ -195,7 +202,8 @@ static struct powerdomain emu_44xx_pwrdm = { /* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */ static struct powerdomain mpu_44xx_pwrdm = { .name = "mpu_pwrdm", - .prcm_offs = OMAP4430_PRM_MPU_MOD, + .prcm_offs = OMAP4430_PRM_MPU_INST, + .prcm_partition = OMAP4430_PRM_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, @@ -215,7 +223,8 @@ static struct powerdomain mpu_44xx_pwrdm = { /* ivahd_44xx_pwrdm: IVA-HD power domain */ static struct powerdomain ivahd_44xx_pwrdm = { .name = "ivahd_pwrdm", - .prcm_offs = OMAP4430_PRM_IVAHD_MOD, + .prcm_offs = OMAP4430_PRM_IVAHD_INST, + .prcm_partition = OMAP4430_PRM_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRDM_POWER_OFF, @@ -238,7 +247,8 @@ static struct powerdomain ivahd_44xx_pwrdm = { /* cam_44xx_pwrdm: Camera subsystem power domain */ static struct powerdomain cam_44xx_pwrdm = { .name = "cam_pwrdm", - .prcm_offs = OMAP4430_PRM_CAM_MOD, + .prcm_offs = OMAP4430_PRM_CAM_INST, + .prcm_partition = OMAP4430_PRM_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_ON, .banks = 1, @@ -254,9 +264,10 @@ static struct powerdomain cam_44xx_pwrdm = { /* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ static struct powerdomain l3init_44xx_pwrdm = { .name = "l3init_pwrdm", - .prcm_offs = OMAP4430_PRM_L3INIT_MOD, + .prcm_offs = OMAP4430_PRM_L3INIT_INST, + .prcm_partition = OMAP4430_PRM_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts = PWRSTS_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 1, .pwrsts_mem_ret = { @@ -271,9 +282,10 @@ static struct powerdomain l3init_44xx_pwrdm = { /* l4per_44xx_pwrdm: Target peripherals power domain */ static struct powerdomain l4per_44xx_pwrdm = { .name = "l4per_pwrdm", - .prcm_offs = OMAP4430_PRM_L4PER_MOD, + .prcm_offs = OMAP4430_PRM_L4PER_INST, + .prcm_partition = OMAP4430_PRM_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts = PWRSTS_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 2, .pwrsts_mem_ret = { @@ -293,7 +305,8 @@ static struct powerdomain l4per_44xx_pwrdm = { */ static struct powerdomain always_on_core_44xx_pwrdm = { .name = "always_on_core_pwrdm", - .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD, + .prcm_offs = OMAP4430_PRM_ALWAYS_ON_INST, + .prcm_partition = OMAP4430_PRM_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_ON, }; @@ -301,7 +314,8 @@ static struct powerdomain always_on_core_44xx_pwrdm = { /* cefuse_44xx_pwrdm: Customer efuse controller power domain */ static struct powerdomain cefuse_44xx_pwrdm = { .name = "cefuse_pwrdm", - .prcm_offs = OMAP4430_PRM_CEFUSE_MOD, + .prcm_offs = OMAP4430_PRM_CEFUSE_INST, + .prcm_partition = OMAP4430_PRM_PARTITION, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_ON, }; @@ -314,6 +328,28 @@ static struct powerdomain cefuse_44xx_pwrdm = { * stdefuse */ -#endif +/* As powerdomains are added or removed above, this list must also be changed */ +static struct powerdomain *powerdomains_omap44xx[] __initdata = { + &core_44xx_pwrdm, + &gfx_44xx_pwrdm, + &abe_44xx_pwrdm, + &dss_44xx_pwrdm, + &tesla_44xx_pwrdm, + &wkup_44xx_pwrdm, + &cpu0_44xx_pwrdm, + &cpu1_44xx_pwrdm, + &emu_44xx_pwrdm, + &mpu_44xx_pwrdm, + &ivahd_44xx_pwrdm, + &cam_44xx_pwrdm, + &l3init_44xx_pwrdm, + &l4per_44xx_pwrdm, + &always_on_core_44xx_pwrdm, + &cefuse_44xx_pwrdm, + NULL +}; -#endif +void __init omap44xx_powerdomains_init(void) +{ + pwrdm_init(powerdomains_omap44xx, &omap4_pwrdm_operations); +} diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index f81acee4738d..87486f559784 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -8,15 +8,12 @@ * Copyright (C) 2007-2009 Nokia Corporation * * Written by Paul Walmsley - * OMAP4 defines in this file are automatically generated from the OMAP hardware - * databases. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ - /* Module offsets from both CM_BASE & PRM_BASE */ /* @@ -51,75 +48,6 @@ #define OMAP3430_NEON_MOD 0xb00 #define OMAP3430ES2_USBHOST_MOD 0xc00 -#define BITS(n_bit) \ - (((1 << n_bit) - 1) | (1 << n_bit)) - -#define BITFIELD(l_bit, u_bit) \ - (BITS(u_bit) & ~((BITS(l_bit)) >> 1)) - -/* OMAP44XX specific module offsets */ - -/* CM1 instances */ - -#define OMAP4430_CM1_OCP_SOCKET_MOD 0x0000 -#define OMAP4430_CM1_CKGEN_MOD 0x0100 -#define OMAP4430_CM1_MPU_MOD 0x0300 -#define OMAP4430_CM1_TESLA_MOD 0x0400 -#define OMAP4430_CM1_ABE_MOD 0x0500 -#define OMAP4430_CM1_RESTORE_MOD 0x0e00 -#define OMAP4430_CM1_INSTR_MOD 0x0f00 - -/* CM2 instances */ - -#define OMAP4430_CM2_OCP_SOCKET_MOD 0x0000 -#define OMAP4430_CM2_CKGEN_MOD 0x0100 -#define OMAP4430_CM2_ALWAYS_ON_MOD 0x0600 -#define OMAP4430_CM2_CORE_MOD 0x0700 -#define OMAP4430_CM2_IVAHD_MOD 0x0f00 -#define OMAP4430_CM2_CAM_MOD 0x1000 -#define OMAP4430_CM2_DSS_MOD 0x1100 -#define OMAP4430_CM2_GFX_MOD 0x1200 -#define OMAP4430_CM2_L3INIT_MOD 0x1300 -#define OMAP4430_CM2_L4PER_MOD 0x1400 -#define OMAP4430_CM2_CEFUSE_MOD 0x1600 -#define OMAP4430_CM2_RESTORE_MOD 0x1e00 -#define OMAP4430_CM2_INSTR_MOD 0x1f00 - -/* PRM instances */ - -#define OMAP4430_PRM_OCP_SOCKET_MOD 0x0000 -#define OMAP4430_PRM_CKGEN_MOD 0x0100 -#define OMAP4430_PRM_MPU_MOD 0x0300 -#define OMAP4430_PRM_TESLA_MOD 0x0400 -#define OMAP4430_PRM_ABE_MOD 0x0500 -#define OMAP4430_PRM_ALWAYS_ON_MOD 0x0600 -#define OMAP4430_PRM_CORE_MOD 0x0700 -#define OMAP4430_PRM_IVAHD_MOD 0x0f00 -#define OMAP4430_PRM_CAM_MOD 0x1000 -#define OMAP4430_PRM_DSS_MOD 0x1100 -#define OMAP4430_PRM_GFX_MOD 0x1200 -#define OMAP4430_PRM_L3INIT_MOD 0x1300 -#define OMAP4430_PRM_L4PER_MOD 0x1400 -#define OMAP4430_PRM_CEFUSE_MOD 0x1600 -#define OMAP4430_PRM_WKUP_MOD 0x1700 -#define OMAP4430_PRM_WKUP_CM_MOD 0x1800 -#define OMAP4430_PRM_EMU_MOD 0x1900 -#define OMAP4430_PRM_EMU_CM_MOD 0x1a00 -#define OMAP4430_PRM_DEVICE_MOD 0x1b00 -#define OMAP4430_PRM_INSTR_MOD 0x1f00 - -/* SCRM instances */ - -#define OMAP4430_SCRM_SCRM_MOD 0x0000 - -/* PRCM_MPU instances */ - -#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD 0x0000 -#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD 0x0200 -#define OMAP4430_PRCM_MPU_CPU0_MOD 0x0400 -#define OMAP4430_PRCM_MPU_CPU1_MOD 0x0800 - - /* 24XX register bits shared between CM & PRM registers */ /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ @@ -461,5 +389,18 @@ #define OMAP3430_EN_CORE_SHIFT 0 #define OMAP3430_EN_CORE_MASK (1 << 0) + +/* + * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP + * submodule to exit hardreset + */ +#define MAX_MODULE_HARDRESET_WAIT 10000 + +# ifndef __ASSEMBLER__ +extern void __iomem *prm_base; +extern void __iomem *cm_base; +extern void __iomem *cm2_base; +# endif + #endif diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index a51846e3a6fa..679bcd28576e 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -17,7 +17,8 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include <linux/module.h> + +#include <linux/kernel.h> #include <linux/init.h> #include <linux/clk.h> #include <linux/io.h> @@ -29,105 +30,27 @@ #include "clock.h" #include "clock2xxx.h" -#include "cm.h" -#include "prm.h" +#include "cm2xxx_3xxx.h" +#include "prm2xxx_3xxx.h" +#include "prm44xx.h" +#include "prminst44xx.h" #include "prm-regbits-24xx.h" #include "prm-regbits-44xx.h" #include "control.h" -static void __iomem *prm_base; -static void __iomem *cm_base; -static void __iomem *cm2_base; +void __iomem *prm_base; +void __iomem *cm_base; +void __iomem *cm2_base; #define MAX_MODULE_ENABLE_WAIT 100000 -struct omap3_prcm_regs { - u32 control_padconf_sys_nirq; - u32 iva2_cm_clksel1; - u32 iva2_cm_clksel2; - u32 cm_sysconfig; - u32 sgx_cm_clksel; - u32 dss_cm_clksel; - u32 cam_cm_clksel; - u32 per_cm_clksel; - u32 emu_cm_clksel; - u32 emu_cm_clkstctrl; - u32 pll_cm_autoidle2; - u32 pll_cm_clksel4; - u32 pll_cm_clksel5; - u32 pll_cm_clken2; - u32 cm_polctrl; - u32 iva2_cm_fclken; - u32 iva2_cm_clken_pll; - u32 core_cm_fclken1; - u32 core_cm_fclken3; - u32 sgx_cm_fclken; - u32 wkup_cm_fclken; - u32 dss_cm_fclken; - u32 cam_cm_fclken; - u32 per_cm_fclken; - u32 usbhost_cm_fclken; - u32 core_cm_iclken1; - u32 core_cm_iclken2; - u32 core_cm_iclken3; - u32 sgx_cm_iclken; - u32 wkup_cm_iclken; - u32 dss_cm_iclken; - u32 cam_cm_iclken; - u32 per_cm_iclken; - u32 usbhost_cm_iclken; - u32 iva2_cm_autiidle2; - u32 mpu_cm_autoidle2; - u32 iva2_cm_clkstctrl; - u32 mpu_cm_clkstctrl; - u32 core_cm_clkstctrl; - u32 sgx_cm_clkstctrl; - u32 dss_cm_clkstctrl; - u32 cam_cm_clkstctrl; - u32 per_cm_clkstctrl; - u32 neon_cm_clkstctrl; - u32 usbhost_cm_clkstctrl; - u32 core_cm_autoidle1; - u32 core_cm_autoidle2; - u32 core_cm_autoidle3; - u32 wkup_cm_autoidle; - u32 dss_cm_autoidle; - u32 cam_cm_autoidle; - u32 per_cm_autoidle; - u32 usbhost_cm_autoidle; - u32 sgx_cm_sleepdep; - u32 dss_cm_sleepdep; - u32 cam_cm_sleepdep; - u32 per_cm_sleepdep; - u32 usbhost_cm_sleepdep; - u32 cm_clkout_ctrl; - u32 prm_clkout_ctrl; - u32 sgx_pm_wkdep; - u32 dss_pm_wkdep; - u32 cam_pm_wkdep; - u32 per_pm_wkdep; - u32 neon_pm_wkdep; - u32 usbhost_pm_wkdep; - u32 core_pm_mpugrpsel1; - u32 iva2_pm_ivagrpsel1; - u32 core_pm_mpugrpsel3; - u32 core_pm_ivagrpsel3; - u32 wkup_pm_mpugrpsel; - u32 wkup_pm_ivagrpsel; - u32 per_pm_mpugrpsel; - u32 per_pm_ivagrpsel; - u32 wkup_pm_wken; -}; - -static struct omap3_prcm_regs prcm_context; - u32 omap_prcm_get_reset_sources(void) { /* XXX This presumably needs modification for 34XX */ if (cpu_is_omap24xx() || cpu_is_omap34xx()) - return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; + return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; if (cpu_is_omap44xx()) - return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; + return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; return 0; } @@ -143,126 +66,46 @@ void omap_prcm_arch_reset(char mode, const char *cmd) prcm_offs = WKUP_MOD; } else if (cpu_is_omap34xx()) { - u32 l; - prcm_offs = OMAP3430_GR_MOD; - l = ('B' << 24) | ('M' << 16) | (cmd ? (u8)*cmd : 0); - /* Reserve the first word in scratchpad for communicating - * with the boot ROM. A pointer to a data structure - * describing the boot process can be stored there, - * cf. OMAP34xx TRM, Initialization / Software Booting - * Configuration. */ - omap_writel(l, OMAP343X_SCRATCHPAD + 4); - } else if (cpu_is_omap44xx()) - prcm_offs = OMAP4430_PRM_DEVICE_MOD; - else + omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0)); + } else if (cpu_is_omap44xx()) { + omap4_prm_global_warm_sw_reset(); /* never returns */ + } else { WARN_ON(1); + } - if (cpu_is_omap24xx() || cpu_is_omap34xx()) - prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, - OMAP2_RM_RSTCTRL); - if (cpu_is_omap44xx()) - prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK, - prcm_offs, OMAP4_RM_RSTCTRL); -} - -static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) -{ - BUG_ON(!base); - return __raw_readl(base + module + reg); -} - -static inline void __omap_prcm_write(u32 value, void __iomem *base, - s16 module, u16 reg) -{ - BUG_ON(!base); - __raw_writel(value, base + module + reg); -} - -/* Read a register in a PRM module */ -u32 prm_read_mod_reg(s16 module, u16 idx) -{ - return __omap_prcm_read(prm_base, module, idx); -} - -/* Write into a register in a PRM module */ -void prm_write_mod_reg(u32 val, s16 module, u16 idx) -{ - __omap_prcm_write(val, prm_base, module, idx); -} - -/* Read-modify-write a register in a PRM module. Caller must lock */ -u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) -{ - u32 v; - - v = prm_read_mod_reg(module, idx); - v &= ~mask; - v |= bits; - prm_write_mod_reg(v, module, idx); - - return v; -} - -/* Read a PRM register, AND it, and shift the result down to bit 0 */ -u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) -{ - u32 v; - - v = prm_read_mod_reg(domain, idx); - v &= mask; - v >>= __ffs(mask); - - return v; -} - -/* Read a PRM register, AND it, and shift the result down to bit 0 */ -u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask) -{ - u32 v; - - v = __raw_readl(reg); - v &= mask; - v >>= __ffs(mask); - - return v; -} - -/* Read-modify-write a register in a PRM module. Caller must lock */ -u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg) -{ - u32 v; - - v = __raw_readl(reg); - v &= ~mask; - v |= bits; - __raw_writel(v, reg); - - return v; -} -/* Read a register in a CM module */ -u32 cm_read_mod_reg(s16 module, u16 idx) -{ - return __omap_prcm_read(cm_base, module, idx); -} - -/* Write into a register in a CM module */ -void cm_write_mod_reg(u32 val, s16 module, u16 idx) -{ - __omap_prcm_write(val, cm_base, module, idx); -} - -/* Read-modify-write a register in a CM module. Caller must lock */ -u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) -{ - u32 v; - - v = cm_read_mod_reg(module, idx); - v &= ~mask; - v |= bits; - cm_write_mod_reg(v, module, idx); - - return v; + /* + * As per Errata i520, in some cases, user will not be able to + * access DDR memory after warm-reset. + * This situation occurs while the warm-reset happens during a read + * access to DDR memory. In that particular condition, DDR memory + * does not respond to a corrupted read command due to the warm + * reset occurrence but SDRC is waiting for read completion. + * SDRC is not sensitive to the warm reset, but the interconnect is + * reset on the fly, thus causing a misalignment between SDRC logic, + * interconnect logic and DDR memory state. + * WORKAROUND: + * Steps to perform before a Warm reset is trigged: + * 1. enable self-refresh on idle request + * 2. put SDRC in idle + * 3. wait until SDRC goes to idle + * 4. generate SW reset (Global SW reset) + * + * Steps to be performed after warm reset occurs (in bootloader): + * if HW warm reset is the source, apply below steps before any + * accesses to SDRAM: + * 1. Reset SMS and SDRC and wait till reset is complete + * 2. Re-initialize SMS, SDRC and memory + * + * NOTE: Above work around is required only if arch reset is implemented + * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need + * the WA since it resets SDRC as well as part of cold reset. + */ + + /* XXX should be moved to some OMAP2/3 specific code */ + omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, + OMAP2_RM_RSTCTRL); + omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ } /** @@ -274,6 +117,9 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) * * Returns 1 if the module indicated readiness in time, or 0 if it * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds. + * + * XXX This function is deprecated. It should be removed once the + * hwmod conversion is complete. */ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, const char *name) @@ -316,303 +162,3 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) WARN_ON(!cm2_base); } } - -#ifdef CONFIG_ARCH_OMAP3 -void omap3_prcm_save_context(void) -{ - prcm_context.control_padconf_sys_nirq = - omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); - prcm_context.iva2_cm_clksel1 = - cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); - prcm_context.iva2_cm_clksel2 = - cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); - prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); - prcm_context.sgx_cm_clksel = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); - prcm_context.dss_cm_clksel = - cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); - prcm_context.cam_cm_clksel = - cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); - prcm_context.per_cm_clksel = - cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); - prcm_context.emu_cm_clksel = - cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); - prcm_context.emu_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); - prcm_context.pll_cm_autoidle2 = - cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); - prcm_context.pll_cm_clksel4 = - cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); - prcm_context.pll_cm_clksel5 = - cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); - prcm_context.pll_cm_clken2 = - cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); - prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); - prcm_context.iva2_cm_fclken = - cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); - prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD, - OMAP3430_CM_CLKEN_PLL); - prcm_context.core_cm_fclken1 = - cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - prcm_context.core_cm_fclken3 = - cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); - prcm_context.sgx_cm_fclken = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); - prcm_context.wkup_cm_fclken = - cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); - prcm_context.dss_cm_fclken = - cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); - prcm_context.cam_cm_fclken = - cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); - prcm_context.per_cm_fclken = - cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); - prcm_context.usbhost_cm_fclken = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); - prcm_context.core_cm_iclken1 = - cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); - prcm_context.core_cm_iclken2 = - cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); - prcm_context.core_cm_iclken3 = - cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); - prcm_context.sgx_cm_iclken = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); - prcm_context.wkup_cm_iclken = - cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); - prcm_context.dss_cm_iclken = - cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); - prcm_context.cam_cm_iclken = - cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); - prcm_context.per_cm_iclken = - cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); - prcm_context.usbhost_cm_iclken = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); - prcm_context.iva2_cm_autiidle2 = - cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); - prcm_context.mpu_cm_autoidle2 = - cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); - prcm_context.iva2_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); - prcm_context.mpu_cm_clkstctrl = - cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); - prcm_context.core_cm_clkstctrl = - cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); - prcm_context.sgx_cm_clkstctrl = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, - OMAP2_CM_CLKSTCTRL); - prcm_context.dss_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); - prcm_context.cam_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); - prcm_context.per_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); - prcm_context.neon_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); - prcm_context.usbhost_cm_clkstctrl = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, - OMAP2_CM_CLKSTCTRL); - prcm_context.core_cm_autoidle1 = - cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); - prcm_context.core_cm_autoidle2 = - cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); - prcm_context.core_cm_autoidle3 = - cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); - prcm_context.wkup_cm_autoidle = - cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); - prcm_context.dss_cm_autoidle = - cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); - prcm_context.cam_cm_autoidle = - cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); - prcm_context.per_cm_autoidle = - cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); - prcm_context.usbhost_cm_autoidle = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); - prcm_context.sgx_cm_sleepdep = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP); - prcm_context.dss_cm_sleepdep = - cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); - prcm_context.cam_cm_sleepdep = - cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); - prcm_context.per_cm_sleepdep = - cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); - prcm_context.usbhost_cm_sleepdep = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); - prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD, - OMAP3_CM_CLKOUT_CTRL_OFFSET); - prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD, - OMAP3_PRM_CLKOUT_CTRL_OFFSET); - prcm_context.sgx_pm_wkdep = - prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP); - prcm_context.dss_pm_wkdep = - prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP); - prcm_context.cam_pm_wkdep = - prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP); - prcm_context.per_pm_wkdep = - prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP); - prcm_context.neon_pm_wkdep = - prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP); - prcm_context.usbhost_pm_wkdep = - prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP); - prcm_context.core_pm_mpugrpsel1 = - prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1); - prcm_context.iva2_pm_ivagrpsel1 = - prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1); - prcm_context.core_pm_mpugrpsel3 = - prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3); - prcm_context.core_pm_ivagrpsel3 = - prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); - prcm_context.wkup_pm_mpugrpsel = - prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL); - prcm_context.wkup_pm_ivagrpsel = - prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL); - prcm_context.per_pm_mpugrpsel = - prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); - prcm_context.per_pm_ivagrpsel = - prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); - prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN); - return; -} - -void omap3_prcm_restore_context(void) -{ - omap_ctrl_writel(prcm_context.control_padconf_sys_nirq, - OMAP343X_CONTROL_PADCONF_SYSNIRQ); - cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, - CM_CLKSEL1); - cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, - CM_CLKSEL2); - __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); - cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, - CM_CLKSEL); - cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD, - CM_CLKSEL); - cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD, - CM_CLKSEL); - cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD, - CM_CLKSEL); - cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD, - CM_CLKSEL1); - cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD, - CM_AUTOIDLE2); - cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD, - OMAP3430ES2_CM_CLKSEL4); - cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD, - OMAP3430ES2_CM_CLKSEL5); - cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD, - OMAP3430ES2_CM_CLKEN2); - __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL); - cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, - CM_FCLKEN); - cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, - OMAP3430_CM_CLKEN_PLL); - cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1); - cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD, - OMAP3430ES2_CM_FCLKEN3); - cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, - CM_FCLKEN); - cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); - cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD, - CM_FCLKEN); - cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD, - CM_FCLKEN); - cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD, - CM_FCLKEN); - cm_write_mod_reg(prcm_context.usbhost_cm_fclken, - OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); - cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1); - cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2); - cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3); - cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, - CM_ICLKEN); - cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); - cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD, - CM_ICLKEN); - cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD, - CM_ICLKEN); - cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD, - CM_ICLKEN); - cm_write_mod_reg(prcm_context.usbhost_cm_iclken, - OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); - cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD, - CM_AUTOIDLE2); - cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); - cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl, - OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD, - CM_AUTOIDLE1); - cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD, - CM_AUTOIDLE2); - cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD, - CM_AUTOIDLE3); - cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE); - cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, - CM_AUTOIDLE); - cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, - CM_AUTOIDLE); - cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD, - CM_AUTOIDLE); - cm_write_mod_reg(prcm_context.usbhost_cm_autoidle, - OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); - cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, - OMAP3430_CM_SLEEPDEP); - cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, - OMAP3430_CM_SLEEPDEP); - cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, - OMAP3430_CM_SLEEPDEP); - cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD, - OMAP3430_CM_SLEEPDEP); - cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep, - OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); - cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, - OMAP3_CM_CLKOUT_CTRL_OFFSET); - prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD, - OMAP3_PRM_CLKOUT_CTRL_OFFSET); - prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD, - PM_WKDEP); - prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD, - PM_WKDEP); - prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD, - PM_WKDEP); - prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD, - PM_WKDEP); - prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD, - PM_WKDEP); - prm_write_mod_reg(prcm_context.usbhost_pm_wkdep, - OMAP3430ES2_USBHOST_MOD, PM_WKDEP); - prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD, - OMAP3430_PM_MPUGRPSEL1); - prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD, - OMAP3430_PM_IVAGRPSEL1); - prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD, - OMAP3430ES2_PM_MPUGRPSEL3); - prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD, - OMAP3430ES2_PM_IVAGRPSEL3); - prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD, - OMAP3430_PM_MPUGRPSEL); - prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD, - OMAP3430_PM_IVAGRPSEL); - prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD, - OMAP3430_PM_MPUGRPSEL); - prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD, - OMAP3430_PM_IVAGRPSEL); - prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN); - return; -} -#endif diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h new file mode 100644 index 000000000000..7334ffb9d2c1 --- /dev/null +++ b/arch/arm/mach-omap2/prcm44xx.h @@ -0,0 +1,42 @@ +/* + * OMAP4 PRCM definitions + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Copyright (C) 2010 Nokia Corporation + * + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This file contains macros and functions that are common to all of + * the PRM/CM/PRCM blocks on the OMAP4 devices: PRM, CM1, CM2, + * PRCM_MPU, SCRM + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRCM44XX_H +#define __ARCH_ARM_MACH_OMAP2_PRCM44XX_H + +/* + * OMAP4 PRCM partition IDs + * + * The numbers and order are arbitrary, but 0 is reserved for the + * 'invalid' partition in case someone forgets to add a + * .prcm_partition field. + */ +#define OMAP4430_INVALID_PRCM_PARTITION 0 +#define OMAP4430_PRM_PARTITION 1 +#define OMAP4430_CM1_PARTITION 2 +#define OMAP4430_CM2_PARTITION 3 +#define OMAP4430_SCRM_PARTITION 4 +#define OMAP4430_PRCM_MPU_PARTITION 5 + +/* + * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition + * IDs, plus one + */ +#define OMAP4_MAX_PRCM_PARTITIONS 6 + + +#endif diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c new file mode 100644 index 000000000000..171fe171a749 --- /dev/null +++ b/arch/arm/mach-omap2/prcm_mpu44xx.c @@ -0,0 +1,45 @@ +/* + * OMAP4 PRCM_MPU module functions + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/io.h> + +#include <plat/common.h> + +#include "prcm_mpu44xx.h" +#include "cm-regbits-44xx.h" + +/* PRCM_MPU low-level functions */ + +u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg) +{ + return __raw_readl(OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); +} + +void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg) +{ + __raw_writel(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); +} + +u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) +{ + u32 v; + + v = omap4_prcm_mpu_read_inst_reg(inst, reg); + v &= ~mask; + v |= bits; + omap4_prcm_mpu_write_inst_reg(v, inst, reg); + + return v; +} diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h new file mode 100644 index 000000000000..729a644ce852 --- /dev/null +++ b/arch/arm/mach-omap2/prcm_mpu44xx.h @@ -0,0 +1,104 @@ +/* + * OMAP44xx PRCM MPU instance offset macros + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Copyright (C) 2010 Nokia Corporation + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", + * or "OMAP4430". + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H +#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H + +#define OMAP4430_PRCM_MPU_BASE 0x48243000 + +#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg)) + +/* PRCM_MPU instances */ + +#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000 +#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200 +#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400 +#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800 + +/* PRCM_MPU clockdomain register offsets (from instance start) */ +#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0000 +#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0000 + + +/* + * PRCM_MPU + * + * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global) + * point of view the PRCM_MPU is a single entity. It shares the same + * programming model as the global PRCM and thus can be assimilate as two new + * MOD inside the PRCM + */ + +/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */ +#define OMAP4_REVISION_PRCM_OFFSET 0x0000 +#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000) + +/* PRCM_MPU.DEVICE_PRM register offsets */ +#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 +#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000) +#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 +#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004) + +/* PRCM_MPU.CPU0 register offsets */ +#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 +#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000) +#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004 +#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004) +#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008 +#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008) +#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c +#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c) +#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010 +#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010) +#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014 +#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014) +#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018 +#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018) + +/* PRCM_MPU.CPU1 register offsets */ +#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 +#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000) +#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004 +#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004) +#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008 +#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008) +#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c +#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c) +#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010 +#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010) +#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014 +#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014) +#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 +#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018) + +/* Function prototypes */ +# ifndef __ASSEMBLER__ +extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx); +extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx); +extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, + s16 idx); +# endif + +#endif diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h index 0b188ffa710e..6ac966103f34 100644 --- a/arch/arm/mach-omap2/prm-regbits-24xx.h +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h @@ -14,7 +14,7 @@ * published by the Free Software Foundation. */ -#include "prm.h" +#include "prm2xxx_3xxx.h" /* Bits shared between registers */ diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 9e63cb743a97..64c087af6a8b 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -1,6 +1,3 @@ -#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H -#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H - /* * OMAP3430 Power/Reset Management register bits * @@ -13,8 +10,11 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H +#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H + -#include "prm.h" +#include "prm2xxx_3xxx.h" /* Shared register bits */ @@ -101,8 +101,11 @@ #define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20) #define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19) #define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18) +#define OMAP3430_GRPSEL_I2C3_SHIFT 17 #define OMAP3430_GRPSEL_I2C3_MASK (1 << 17) +#define OMAP3430_GRPSEL_I2C2_SHIFT 16 #define OMAP3430_GRPSEL_I2C2_MASK (1 << 16) +#define OMAP3430_GRPSEL_I2C1_SHIFT 15 #define OMAP3430_GRPSEL_I2C1_MASK (1 << 15) #define OMAP3430_GRPSEL_UART2_MASK (1 << 14) #define OMAP3430_GRPSEL_UART1_MASK (1 << 13) diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h index 25b19b610177..6d2776f6fc08 100644 --- a/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/arch/arm/mach-omap2/prm-regbits-44xx.h @@ -22,8 +22,6 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H -#include "prm.h" - /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 7be040b2fdab..39d562169d18 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -1,321 +1,20 @@ -#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H -#define __ARCH_ARM_MACH_OMAP2_PRM_H - /* - * OMAP2/3 Power/Reset Management (PRM) register definitions + * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions * * Copyright (C) 2007-2009 Texas Instruments, Inc. * Copyright (C) 2010 Nokia Corporation * - * Written by Paul Walmsley + * Paul Walmsley * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H +#define __ARCH_ARM_MACH_OMAP2_PRM_H #include "prcm-common.h" -#define OMAP2420_PRM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) -#define OMAP2430_PRM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) -#define OMAP34XX_PRM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) -#define OMAP44XX_PRM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg)) -#define OMAP44XX_PRCM_MPU_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg)) - -#include "prm44xx.h" - -/* - * Architecture-specific global PRM registers - * Use __raw_{read,write}l() with these registers. - * - * With a few exceptions, these are the register names beginning with - * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the - * IRQSTATUS and IRQENABLE bits.) - * - */ - -#define OMAP2_PRCM_REVISION_OFFSET 0x0000 -#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000) -#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010 -#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010) - -#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018 -#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018) -#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c -#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c) - -#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050 -#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050) -#define OMAP2_PRCM_VOLTST_OFFSET 0x0054 -#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054) -#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060 -#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060) -#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070 -#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070) -#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078 -#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078) -#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080 -#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080) -#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084 -#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084) -#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090 -#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090) -#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094 -#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094) -#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098 -#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098) - -#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000) -#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010) - -#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018) -#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c) - -#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050) -#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054) -#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060) -#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070) -#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078) -#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080) -#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084) -#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090) -#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094) -#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098) - -#define OMAP3_PRM_REVISION_OFFSET 0x0004 -#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004) -#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014 -#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014) - -#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018 -#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018) -#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c -#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c) - - -#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020 -#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) -#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024 -#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) -#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028 -#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) -#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c -#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) -#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030 -#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) -#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034 -#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) -#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038 -#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) -#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c -#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) -#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050 -#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) -#define OMAP3_PRM_RSTTIME_OFFSET 0x0054 -#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) -#define OMAP3_PRM_RSTST_OFFSET 0x0058 -#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) -#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060 -#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) -#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064 -#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) -#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070 -#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) -#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090 -#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) -#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094 -#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) -#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098 -#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) -#define OMAP3_PRM_POLCTRL_OFFSET 0x009c -#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) -#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0 -#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) -#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0 -#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) -#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4 -#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) -#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8 -#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) -#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc -#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) -#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0 -#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) -#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4 -#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) -#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0 -#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) -#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4 -#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) -#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8 -#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) -#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc -#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) -#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0 -#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) -#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 -#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) - -#define OMAP3_PRM_CLKSEL_OFFSET 0x0040 -#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) -#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070 -#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) - -/* - * Module specific PRM registers from PRM_BASE + domain offset - * - * Use prm_{read,write}_mod_reg() with these registers. - * - * With a few exceptions, these are the register names beginning with - * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS - * and IRQENABLE bits.) - * - */ - -/* Registers appearing on both 24xx and 34xx */ - -#define OMAP2_RM_RSTCTRL 0x0050 -#define OMAP2_RM_RSTTIME 0x0054 -#define OMAP2_RM_RSTST 0x0058 -#define OMAP2_PM_PWSTCTRL 0x00e0 -#define OMAP2_PM_PWSTST 0x00e4 - -#define PM_WKEN 0x00a0 -#define PM_WKEN1 PM_WKEN -#define PM_WKST 0x00b0 -#define PM_WKST1 PM_WKST -#define PM_WKDEP 0x00c8 -#define PM_EVGENCTRL 0x00d4 -#define PM_EVGENONTIM 0x00d8 -#define PM_EVGENOFFTIM 0x00dc - -/* Omap2 specific registers */ -#define OMAP24XX_PM_WKEN2 0x00a4 -#define OMAP24XX_PM_WKST2 0x00b4 - -#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ -#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ -#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 -#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc - -/* Omap3 specific registers */ -#define OMAP3430ES2_PM_WKEN3 0x00f0 -#define OMAP3430ES2_PM_WKST3 0x00b8 - -#define OMAP3430_PM_MPUGRPSEL 0x00a4 -#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL -#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8 - -#define OMAP3430_PM_IVAGRPSEL 0x00a8 -#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL -#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4 - -#define OMAP3430_PM_PREPWSTST 0x00e8 - -#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 -#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc - -/* Omap4 specific registers */ -#define OMAP4_RM_RSTCTRL 0x0000 -#define OMAP4_RM_RSTTIME 0x0004 -#define OMAP4_RM_RSTST 0x0008 -#define OMAP4_PM_PWSTCTRL 0x0000 -#define OMAP4_PM_PWSTST 0x0004 - - -#ifndef __ASSEMBLER__ - -/* Power/reset management domain register get/set */ -extern u32 prm_read_mod_reg(s16 module, u16 idx); -extern void prm_write_mod_reg(u32 val, s16 module, u16 idx); -extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); - -/* Read-modify-write bits in a PRM register (by domain) */ -static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) -{ - return prm_rmw_mod_reg_bits(bits, bits, module, idx); -} - -static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) -{ - return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); -} - -/* These omap2_ PRM functions apply to both OMAP2 and 3 */ -int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); -int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); -int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift); - -int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift); -int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift); -int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); - -#endif - -/* - * Bits common to specific registers - * - * The 3430 register and bit names are generally used, - * since they tend to make more sense - */ - -/* PM_EVGENONTIM_MPU */ -/* Named PM_EVEGENONTIM_MPU on the 24XX */ -#define OMAP_ONTIMEVAL_SHIFT 0 -#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0) - -/* PM_EVGENOFFTIM_MPU */ -/* Named PM_EVEGENOFFTIM_MPU on the 24XX */ -#define OMAP_OFFTIMEVAL_SHIFT 0 -#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0) - -/* PRM_CLKSETUP and PRCM_VOLTSETUP */ -/* Named PRCM_CLKSSETUP on the 24XX */ -#define OMAP_SETUP_TIME_SHIFT 0 -#define OMAP_SETUP_TIME_MASK (0xffff << 0) - -/* PRM_CLKSRC_CTRL */ -/* Named PRCM_CLKSRC_CTRL on the 24XX */ -#define OMAP_SYSCLKDIV_SHIFT 6 -#define OMAP_SYSCLKDIV_MASK (0x3 << 6) -#define OMAP_AUTOEXTCLKMODE_SHIFT 3 -#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3) -#define OMAP_SYSCLKSEL_SHIFT 0 -#define OMAP_SYSCLKSEL_MASK (0x3 << 0) - -/* PM_EVGENCTRL_MPU */ -#define OMAP_OFFLOADMODE_SHIFT 3 -#define OMAP_OFFLOADMODE_MASK (0x3 << 3) -#define OMAP_ONLOADMODE_SHIFT 1 -#define OMAP_ONLOADMODE_MASK (0x3 << 1) -#define OMAP_ENABLE_MASK (1 << 0) - -/* PRM_RSTTIME */ -/* Named RM_RSTTIME_WKUP on the 24xx */ -#define OMAP_RSTTIME2_SHIFT 8 -#define OMAP_RSTTIME2_MASK (0x1f << 8) -#define OMAP_RSTTIME1_SHIFT 0 -#define OMAP_RSTTIME1_MASK (0xff << 0) - -/* PRM_RSTCTRL */ -/* Named RM_RSTCTRL_WKUP on the 24xx */ -/* 2420 calls RST_DPLL3 'RST_DPLL' */ -#define OMAP_RST_DPLL3_MASK (1 << 2) -#define OMAP_RST_GS_MASK (1 << 1) - - -/* - * Bits common to module-shared registers - * - * Not all registers of a particular type support all of these bits - - * check TRM if you are unsure - */ - /* * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP * @@ -341,59 +40,6 @@ int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); #define OMAP_POWERSTATEST_MASK (0x3 << 0) /* - * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is - * called 'COREWKUP_RST' - * - * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, - * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON - */ -#define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3) - -/* - * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP - * - * 2430: RM_RSTST_MDM - * - * 3430: RM_RSTST_CORE, RM_RSTST_EMU - */ -#define OMAP_DOMAINWKUP_RST_MASK (1 << 2) - -/* - * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP - * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'. - * - * 2430: RM_RSTST_MDM - * - * 3430: RM_RSTST_CORE, RM_RSTST_EMU - */ -#define OMAP_GLOBALWARM_RST_MASK (1 << 1) -#define OMAP_GLOBALCOLD_RST_MASK (1 << 0) - -/* - * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP - * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP" - * - * 2430: PM_WKDEP_MDM - * - * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, - * PM_WKDEP_PER - */ -#define OMAP_EN_WKUP_SHIFT 4 -#define OMAP_EN_WKUP_MASK (1 << 4) - -/* - * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, - * PM_PWSTCTRL_DSP - * - * 2430: PM_PWSTCTRL_MDM - * - * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, - * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, - * PM_PWSTCTRL_NEON - */ -#define OMAP_LOGICRETSTATE_MASK (1 << 2) - -/* * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, * PM_PWSTCTRL_DSP, PM_PWSTST_MPU * @@ -407,11 +53,4 @@ int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); #define OMAP_POWERSTATE_MASK (0x3 << 0) -/* - * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP - * submodule to exit hardreset - */ -#define MAX_MODULE_HARDRESET_WAIT 10000 - - #endif diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index 421771eee450..ec0362574b5e 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -12,18 +12,65 @@ */ #include <linux/kernel.h> -#include <linux/delay.h> #include <linux/errno.h> #include <linux/err.h> +#include <linux/io.h> #include <plat/common.h> #include <plat/cpu.h> #include <plat/prcm.h> -#include "prm.h" +#include "prm2xxx_3xxx.h" +#include "cm2xxx_3xxx.h" #include "prm-regbits-24xx.h" #include "prm-regbits-34xx.h" +u32 omap2_prm_read_mod_reg(s16 module, u16 idx) +{ + return __raw_readl(prm_base + module + idx); +} + +void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) +{ + __raw_writel(val, prm_base + module + idx); +} + +/* Read-modify-write a register in a PRM module. Caller must lock */ +u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) +{ + u32 v; + + v = omap2_prm_read_mod_reg(module, idx); + v &= ~mask; + v |= bits; + omap2_prm_write_mod_reg(v, module, idx); + + return v; +} + +/* Read a PRM register, AND it, and shift the result down to bit 0 */ +u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) +{ + u32 v; + + v = omap2_prm_read_mod_reg(domain, idx); + v &= mask; + v >>= __ffs(mask); + + return v; +} + +u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) +{ + return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx); +} + +u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) +{ + return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx); +} + + /** * omap2_prm_is_hardreset_asserted - read the HW reset line state of * submodules contained in the hwmod module @@ -39,7 +86,7 @@ int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) return -EINVAL; - return prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, + return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, (1 << shift)); } @@ -63,7 +110,7 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) return -EINVAL; mask = 1 << shift; - prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); + omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); return 0; } @@ -93,18 +140,17 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift) mask = 1 << shift; /* Check the current status to avoid de-asserting the line twice */ - if (prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0) + if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0) return -EEXIST; /* Clear the reset status by writing 1 to the status bit */ - prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST); + omap2_prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST); /* de-assert the reset control line */ - prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL); + omap2_prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL); /* wait the status to be set */ - omap_test_timeout(prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, + omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, mask), MAX_MODULE_HARDRESET_WAIT, c); return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; } - diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h new file mode 100644 index 000000000000..53d44f6e3736 --- /dev/null +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h @@ -0,0 +1,367 @@ +/* + * OMAP2/3 Power/Reset Management (PRM) register definitions + * + * Copyright (C) 2007-2009 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * The PRM hardware modules on the OMAP2/3 are quite similar to each + * other. The PRM on OMAP4 has a new register layout, and is handled + * in a separate file. + */ +#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H +#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H + +#include "prcm-common.h" +#include "prm.h" + +#define OMAP2420_PRM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) +#define OMAP2430_PRM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) +#define OMAP34XX_PRM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) + + +/* + * OMAP2-specific global PRM registers + * Use __raw_{read,write}l() with these registers. + * + * With a few exceptions, these are the register names beginning with + * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE + * bits.) + * + */ + +#define OMAP2_PRCM_REVISION_OFFSET 0x0000 +#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000) +#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010 +#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010) + +#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018 +#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c +#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c) + +#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050 +#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050) +#define OMAP2_PRCM_VOLTST_OFFSET 0x0054 +#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054) +#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060 +#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060) +#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070 +#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070) +#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078 +#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078) +#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080 +#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080) +#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084 +#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084) +#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090 +#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090) +#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094 +#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094) +#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098 +#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098) + +#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000) +#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010) + +#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c) + +#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050) +#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054) +#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060) +#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070) +#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078) +#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080) +#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084) +#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090) +#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094) +#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098) + +/* + * OMAP3-specific global PRM registers + * Use __raw_{read,write}l() with these registers. + * + * With a few exceptions, these are the register names beginning with + * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE + * bits.) + */ + +#define OMAP3_PRM_REVISION_OFFSET 0x0004 +#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004) +#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014 +#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014) + +#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018 +#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c +#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c) + + +#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020 +#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) +#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024 +#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) +#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028 +#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) +#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c +#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) +#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030 +#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) +#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034 +#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) +#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038 +#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) +#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c +#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) +#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050 +#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) +#define OMAP3_PRM_RSTTIME_OFFSET 0x0054 +#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) +#define OMAP3_PRM_RSTST_OFFSET 0x0058 +#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) +#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060 +#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) +#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064 +#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) +#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070 +#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) +#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090 +#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) +#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094 +#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) +#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098 +#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) +#define OMAP3_PRM_POLCTRL_OFFSET 0x009c +#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) +#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0 +#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) +#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0 +#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) +#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4 +#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) +#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8 +#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) +#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc +#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) +#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0 +#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) +#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4 +#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) +#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0 +#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) +#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4 +#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) +#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8 +#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) +#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc +#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) +#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0 +#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) +#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 +#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) + +#define OMAP3_PRM_CLKSEL_OFFSET 0x0040 +#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) +#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070 +#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) + +/* + * Module specific PRM register offsets from PRM_BASE + domain offset + * + * Use prm_{read,write}_mod_reg() with these registers. + * + * With a few exceptions, these are the register names beginning with + * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the + * IRQSTATUS and IRQENABLE bits.) + */ + +/* Register offsets appearing on both OMAP2 and OMAP3 */ + +#define OMAP2_RM_RSTCTRL 0x0050 +#define OMAP2_RM_RSTTIME 0x0054 +#define OMAP2_RM_RSTST 0x0058 +#define OMAP2_PM_PWSTCTRL 0x00e0 +#define OMAP2_PM_PWSTST 0x00e4 + +#define PM_WKEN 0x00a0 +#define PM_WKEN1 PM_WKEN +#define PM_WKST 0x00b0 +#define PM_WKST1 PM_WKST +#define PM_WKDEP 0x00c8 +#define PM_EVGENCTRL 0x00d4 +#define PM_EVGENONTIM 0x00d8 +#define PM_EVGENOFFTIM 0x00dc + +/* OMAP2xxx specific register offsets */ +#define OMAP24XX_PM_WKEN2 0x00a4 +#define OMAP24XX_PM_WKST2 0x00b4 + +#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ +#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ +#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 +#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc + +/* OMAP3 specific register offsets */ +#define OMAP3430ES2_PM_WKEN3 0x00f0 +#define OMAP3430ES2_PM_WKST3 0x00b8 + +#define OMAP3430_PM_MPUGRPSEL 0x00a4 +#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL +#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8 + +#define OMAP3430_PM_IVAGRPSEL 0x00a8 +#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL +#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4 + +#define OMAP3430_PM_PREPWSTST 0x00e8 + +#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 +#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc + + +#ifndef __ASSEMBLER__ + +/* Power/reset management domain register get/set */ +extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx); +extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx); +extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); +extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); +extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); +extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); + +/* These omap2_ PRM functions apply to both OMAP2 and 3 */ +extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); +extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); +extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift); + +#endif + +/* + * Bits common to specific registers + * + * The 3430 register and bit names are generally used, + * since they tend to make more sense + */ + +/* PM_EVGENONTIM_MPU */ +/* Named PM_EVEGENONTIM_MPU on the 24XX */ +#define OMAP_ONTIMEVAL_SHIFT 0 +#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0) + +/* PM_EVGENOFFTIM_MPU */ +/* Named PM_EVEGENOFFTIM_MPU on the 24XX */ +#define OMAP_OFFTIMEVAL_SHIFT 0 +#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0) + +/* PRM_CLKSETUP and PRCM_VOLTSETUP */ +/* Named PRCM_CLKSSETUP on the 24XX */ +#define OMAP_SETUP_TIME_SHIFT 0 +#define OMAP_SETUP_TIME_MASK (0xffff << 0) + +/* PRM_CLKSRC_CTRL */ +/* Named PRCM_CLKSRC_CTRL on the 24XX */ +#define OMAP_SYSCLKDIV_SHIFT 6 +#define OMAP_SYSCLKDIV_MASK (0x3 << 6) +#define OMAP_AUTOEXTCLKMODE_SHIFT 3 +#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3) +#define OMAP_SYSCLKSEL_SHIFT 0 +#define OMAP_SYSCLKSEL_MASK (0x3 << 0) + +/* PM_EVGENCTRL_MPU */ +#define OMAP_OFFLOADMODE_SHIFT 3 +#define OMAP_OFFLOADMODE_MASK (0x3 << 3) +#define OMAP_ONLOADMODE_SHIFT 1 +#define OMAP_ONLOADMODE_MASK (0x3 << 1) +#define OMAP_ENABLE_MASK (1 << 0) + +/* PRM_RSTTIME */ +/* Named RM_RSTTIME_WKUP on the 24xx */ +#define OMAP_RSTTIME2_SHIFT 8 +#define OMAP_RSTTIME2_MASK (0x1f << 8) +#define OMAP_RSTTIME1_SHIFT 0 +#define OMAP_RSTTIME1_MASK (0xff << 0) + +/* PRM_RSTCTRL */ +/* Named RM_RSTCTRL_WKUP on the 24xx */ +/* 2420 calls RST_DPLL3 'RST_DPLL' */ +#define OMAP_RST_DPLL3_MASK (1 << 2) +#define OMAP_RST_GS_MASK (1 << 1) + + +/* + * Bits common to module-shared registers + * + * Not all registers of a particular type support all of these bits - + * check TRM if you are unsure + */ + +/* + * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is + * called 'COREWKUP_RST' + * + * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, + * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON + */ +#define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3) + +/* + * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP + * + * 2430: RM_RSTST_MDM + * + * 3430: RM_RSTST_CORE, RM_RSTST_EMU + */ +#define OMAP_DOMAINWKUP_RST_MASK (1 << 2) + +/* + * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP + * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'. + * + * 2430: RM_RSTST_MDM + * + * 3430: RM_RSTST_CORE, RM_RSTST_EMU + */ +#define OMAP_GLOBALWARM_RST_MASK (1 << 1) +#define OMAP_GLOBALCOLD_RST_MASK (1 << 0) + +/* + * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP + * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP" + * + * 2430: PM_WKDEP_MDM + * + * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, + * PM_WKDEP_PER + */ +#define OMAP_EN_WKUP_SHIFT 4 +#define OMAP_EN_WKUP_MASK (1 << 4) + +/* + * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, + * PM_PWSTCTRL_DSP + * + * 2430: PM_PWSTCTRL_MDM + * + * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, + * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, + * PM_PWSTCTRL_NEON + */ +#define OMAP_LOGICRETSTATE_MASK (1 << 2) + + +/* + * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP + * submodule to exit hardreset + */ +#define MAX_MODULE_HARDRESET_WAIT 10000 + + +#endif diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index a1ff918d9bed..a2a04bfa9628 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -15,12 +15,13 @@ #include <linux/delay.h> #include <linux/errno.h> #include <linux/err.h> +#include <linux/io.h> #include <plat/common.h> #include <plat/cpu.h> #include <plat/prcm.h> -#include "prm.h" +#include "prm44xx.h" #include "prm-regbits-44xx.h" /* @@ -29,6 +30,70 @@ */ #define OMAP4_RST_CTRL_ST_OFFSET 4 +/* PRM low-level functions */ + +/* Read a register in a CM/PRM instance in the PRM module */ +u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) +{ + return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg)); +} + +/* Write into a register in a CM/PRM instance in the PRM module */ +void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) +{ + __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg)); +} + +/* Read-modify-write a register in a PRM module. Caller must lock */ +u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) +{ + u32 v; + + v = omap4_prm_read_inst_reg(inst, reg); + v &= ~mask; + v |= bits; + omap4_prm_write_inst_reg(v, inst, reg); + + return v; +} + +/* Read a PRM register, AND it, and shift the result down to bit 0 */ +/* XXX deprecated */ +u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask) +{ + u32 v; + + v = __raw_readl(reg); + v &= mask; + v >>= __ffs(mask); + + return v; +} + +/* Read-modify-write a register in a PRM module. Caller must lock */ +/* XXX deprecated */ +u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg) +{ + u32 v; + + v = __raw_readl(reg); + v &= ~mask; + v |= bits; + __raw_writel(v, reg); + + return v; +} + +u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 reg) +{ + return omap4_prm_rmw_inst_reg_bits(bits, bits, inst, reg); +} + +u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 reg) +{ + return omap4_prm_rmw_inst_reg_bits(bits, 0x0, inst, reg); +} + /** * omap4_prm_is_hardreset_asserted - read the HW reset line state of * submodules contained in the hwmod module @@ -114,3 +179,17 @@ int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift) return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; } +void omap4_prm_global_warm_sw_reset(void) +{ + u32 v; + + v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, + OMAP4_RM_RSTCTRL); + v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK; + omap4_prm_write_inst_reg(v, OMAP4430_PRM_DEVICE_INST, + OMAP4_RM_RSTCTRL); + + /* OCP barrier */ + v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, + OMAP4_RM_RSTCTRL); +} diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index 59839dbabd84..67a0d3feb3f6 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -17,736 +17,762 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. + * + * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", + * or "OMAP4430". */ #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H +#include "prcm-common.h" +#include "prm.h" + +#define OMAP4430_PRM_BASE 0x4a306000 + +#define OMAP44XX_PRM_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg)) + + +/* PRM instances */ +#define OMAP4430_PRM_OCP_SOCKET_INST 0x0000 +#define OMAP4430_PRM_CKGEN_INST 0x0100 +#define OMAP4430_PRM_MPU_INST 0x0300 +#define OMAP4430_PRM_TESLA_INST 0x0400 +#define OMAP4430_PRM_ABE_INST 0x0500 +#define OMAP4430_PRM_ALWAYS_ON_INST 0x0600 +#define OMAP4430_PRM_CORE_INST 0x0700 +#define OMAP4430_PRM_IVAHD_INST 0x0f00 +#define OMAP4430_PRM_CAM_INST 0x1000 +#define OMAP4430_PRM_DSS_INST 0x1100 +#define OMAP4430_PRM_GFX_INST 0x1200 +#define OMAP4430_PRM_L3INIT_INST 0x1300 +#define OMAP4430_PRM_L4PER_INST 0x1400 +#define OMAP4430_PRM_CEFUSE_INST 0x1600 +#define OMAP4430_PRM_WKUP_INST 0x1700 +#define OMAP4430_PRM_WKUP_CM_INST 0x1800 +#define OMAP4430_PRM_EMU_INST 0x1900 +#define OMAP4430_PRM_EMU_CM_INST 0x1a00 +#define OMAP4430_PRM_DEVICE_INST 0x1b00 +#define OMAP4430_PRM_INSTR_INST 0x1f00 + +/* PRM clockdomain register offsets (from instance start) */ +#define OMAP4430_PRM_MPU_MPU_CDOFFS 0x0000 +#define OMAP4430_PRM_TESLA_TESLA_CDOFFS 0x0000 +#define OMAP4430_PRM_ABE_ABE_CDOFFS 0x0000 +#define OMAP4430_PRM_CORE_CORE_CDOFFS 0x0000 +#define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS 0x0000 +#define OMAP4430_PRM_CAM_CAM_CDOFFS 0x0000 +#define OMAP4430_PRM_DSS_DSS_CDOFFS 0x0000 +#define OMAP4430_PRM_GFX_GFX_CDOFFS 0x0000 +#define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS 0x0000 +#define OMAP4430_PRM_L4PER_L4PER_CDOFFS 0x0000 +#define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS 0x0000 +#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000 +#define OMAP4430_PRM_EMU_EMU_CDOFFS 0x0000 +#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000 + +/* OMAP4 specific register offsets */ +#define OMAP4_RM_RSTCTRL 0x0000 +#define OMAP4_RM_RSTTIME 0x0004 +#define OMAP4_RM_RSTST 0x0008 +#define OMAP4_PM_PWSTCTRL 0x0000 +#define OMAP4_PM_PWSTST 0x0004 + /* PRM */ /* PRM.OCP_SOCKET_PRM register offsets */ #define OMAP4_REVISION_PRM_OFFSET 0x0000 -#define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000) +#define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0000) #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010 -#define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010) +#define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010) #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 -#define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014) +#define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0014) #define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018 -#define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018) +#define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018) #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET 0x001c -#define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c) +#define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x001c) #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET 0x0020 -#define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020) +#define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0020) #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET 0x0028 -#define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028) +#define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0028) #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET 0x0030 -#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030) +#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0030) #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 -#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038) +#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0038) #define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) +#define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0040) /* PRM.CKGEN_PRM register offsets */ #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 -#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000) +#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0000) #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 -#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008) +#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0008) #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c -#define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c) +#define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x000c) #define OMAP4_CM_SYS_CLKSEL_OFFSET 0x0010 -#define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010) +#define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0010) /* PRM.MPU_PRM register offsets */ #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000) +#define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0000) #define OMAP4_PM_MPU_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004) +#define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0004) #define OMAP4_RM_MPU_RSTST_OFFSET 0x0014 -#define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014) +#define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0014) #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024) +#define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0024) /* PRM.TESLA_PRM register offsets */ #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000) +#define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0000) #define OMAP4_PM_TESLA_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004) +#define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0004) #define OMAP4_RM_TESLA_RSTCTRL_OFFSET 0x0010 -#define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010) +#define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0010) #define OMAP4_RM_TESLA_RSTST_OFFSET 0x0014 -#define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014) +#define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0014) #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024) +#define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0024) /* PRM.ABE_PRM register offsets */ #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000) +#define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0000) #define OMAP4_PM_ABE_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004) +#define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0004) #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c) +#define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x002c) #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET 0x0030 -#define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030) +#define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0030) #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET 0x0034 -#define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034) +#define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0034) #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 -#define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038) +#define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0038) #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c -#define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c) +#define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x003c) #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 -#define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040) +#define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0040) #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 -#define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044) +#define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0044) #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 -#define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048) +#define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0048) #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c -#define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c) +#define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x004c) #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 -#define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050) +#define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0050) #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 -#define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054) +#define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0054) #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 -#define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058) +#define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0058) #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c -#define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c) +#define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x005c) #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET 0x0060 -#define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060) +#define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0060) #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET 0x0064 -#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064) +#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0064) #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 -#define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068) +#define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0068) #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c -#define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c) +#define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x006c) #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 -#define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070) +#define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0070) #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 -#define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074) +#define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0074) #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 -#define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078) +#define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0078) #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c -#define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c) +#define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x007c) #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 -#define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080) +#define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0080) #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 -#define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084) +#define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0084) #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET 0x0088 -#define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088) +#define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0088) #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET 0x008c -#define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c) +#define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x008c) /* PRM.ALWAYS_ON_PRM register offsets */ #define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024) +#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0024) #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET 0x0028 -#define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028) +#define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0028) #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c) +#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x002c) #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET 0x0030 -#define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030) +#define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0030) #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET 0x0034 -#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034) +#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0034) #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET 0x0038 -#define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038) +#define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0038) #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET 0x003c -#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c) +#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x003c) /* PRM.CORE_PRM register offsets */ #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000) +#define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0000) #define OMAP4_PM_CORE_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004) +#define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0004) #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024) +#define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0024) #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET 0x0124 -#define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124) +#define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0124) #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET 0x012c -#define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c) +#define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x012c) #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET 0x0134 -#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134) +#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0134) #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET 0x0210 -#define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210) +#define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0210) #define OMAP4_RM_DUCATI_RSTST_OFFSET 0x0214 -#define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214) +#define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0214) #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET 0x0224 -#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224) +#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0224) #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET 0x0324 -#define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324) +#define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0324) #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET 0x0424 -#define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424) +#define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0424) #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET 0x042c -#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c) +#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x042c) #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET 0x0434 -#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434) +#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0434) #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET 0x043c -#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c) +#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x043c) #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET 0x0444 -#define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444) +#define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0444) #define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET 0x0454 -#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454) +#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0454) #define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET 0x045c -#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c) +#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x045c) #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET 0x0464 -#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464) +#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464) #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524 -#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524) -#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c -#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c) +#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524) +#define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET 0x052c +#define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c) #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534 -#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534) +#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534) #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 -#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624) +#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0624) #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET 0x062c -#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c) +#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x062c) #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 -#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634) +#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0634) #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c -#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c) +#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x063c) #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET 0x0724 -#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724) +#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0724) #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c -#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c) +#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x072c) #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET 0x0744 -#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744) +#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0744) /* PRM.IVAHD_PRM register offsets */ #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000) +#define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0000) #define OMAP4_PM_IVAHD_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004) +#define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0004) #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET 0x0010 -#define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010) +#define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0010) #define OMAP4_RM_IVAHD_RSTST_OFFSET 0x0014 -#define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014) +#define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0014) #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024) +#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0024) #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c) +#define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x002c) /* PRM.CAM_PRM register offsets */ #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000) +#define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0000) #define OMAP4_PM_CAM_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004) +#define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0004) #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024) +#define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0024) #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c) +#define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x002c) /* PRM.DSS_PRM register offsets */ #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000) +#define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0000) #define OMAP4_PM_DSS_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004) +#define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0004) #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET 0x0020 -#define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020) +#define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0020) #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024) +#define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0024) #define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c) +#define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x002c) /* PRM.GFX_PRM register offsets */ #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000) +#define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0000) #define OMAP4_PM_GFX_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004) +#define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0004) #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024) +#define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0024) /* PRM.L3INIT_PRM register offsets */ #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000) +#define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0000) #define OMAP4_PM_L3INIT_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004) +#define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0004) #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 -#define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028) +#define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0028) #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c) +#define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x002c) #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 -#define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030) +#define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0030) #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 -#define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034) +#define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0034) #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 -#define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038) +#define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0038) #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c -#define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c) +#define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x003c) #define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET 0x0040 -#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040) +#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0040) #define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET 0x0044 -#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044) +#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0044) #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET 0x0058 -#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058) +#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0058) #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET 0x005c -#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c) +#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x005c) #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET 0x0060 -#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060) +#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0060) #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET 0x0064 -#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064) +#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0064) #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET 0x0068 -#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068) +#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0068) #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET 0x006c -#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c) +#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x006c) #define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET 0x007c -#define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c) +#define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x007c) #define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET 0x0084 -#define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084) +#define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0084) #define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 -#define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088) +#define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0088) #define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c -#define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c) +#define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x008c) #define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET 0x0094 -#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094) +#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0094) #define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET 0x0098 -#define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098) +#define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0098) #define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET 0x009c -#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c) +#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x009c) #define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET 0x00ac -#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac) +#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00ac) #define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET 0x00c0 -#define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0) +#define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c0) #define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET 0x00c4 -#define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4) +#define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c4) #define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET 0x00c8 -#define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8) +#define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c8) #define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET 0x00cc -#define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc) +#define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00cc) #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET 0x00d0 -#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0) +#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d0) #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET 0x00d4 -#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4) +#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d4) #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET 0x00e4 -#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4) +#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00e4) /* PRM.L4PER_PRM register offsets */ #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000) +#define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0000) #define OMAP4_PM_L4PER_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004) +#define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0004) #define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024) +#define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0024) #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET 0x0028 -#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028) +#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0028) #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c) +#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x002c) #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET 0x0030 -#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030) +#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0030) #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET 0x0034 -#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034) +#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0034) #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET 0x0038 -#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038) +#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0038) #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET 0x003c -#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c) +#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x003c) #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET 0x0040 -#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040) +#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0040) #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET 0x0044 -#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044) +#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0044) #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET 0x0048 -#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048) +#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0048) #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET 0x004c -#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c) +#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x004c) #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET 0x0050 -#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050) +#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0050) #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET 0x0054 -#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054) +#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0054) #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c -#define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c) +#define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x005c) #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 -#define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060) +#define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0060) #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 -#define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064) +#define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0064) #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 -#define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068) +#define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0068) #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c -#define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c) +#define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x006c) #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 -#define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070) +#define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0070) #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 -#define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074) +#define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0074) #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 -#define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078) +#define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0078) #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c -#define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c) +#define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x007c) #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 -#define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080) +#define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0080) #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 -#define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084) +#define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0084) #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c -#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c) +#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x008c) #define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET 0x0090 -#define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090) +#define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0090) #define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET 0x0094 -#define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094) +#define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0094) #define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET 0x0098 -#define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098) +#define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0098) #define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET 0x009c -#define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c) +#define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x009c) #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 -#define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0) +#define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a0) #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 -#define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4) +#define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a4) #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 -#define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8) +#define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a8) #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac -#define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac) +#define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ac) #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 -#define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0) +#define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b0) #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 -#define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4) +#define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b4) #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 -#define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8) +#define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b8) #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc -#define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc) +#define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00bc) #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x00c0 -#define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0) +#define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00c0) #define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET 0x00d0 -#define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0) +#define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d0) #define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET 0x00d4 -#define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4) +#define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d4) #define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET 0x00d8 -#define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8) +#define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d8) #define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET 0x00dc -#define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc) +#define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00dc) #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET 0x00e0 -#define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0) +#define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e0) #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET 0x00e4 -#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4) +#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e4) #define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET 0x00ec -#define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec) +#define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ec) #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 -#define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0) +#define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f0) #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 -#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4) +#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f4) #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 -#define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8) +#define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f8) #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc -#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc) +#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00fc) #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 -#define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100) +#define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0100) #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 -#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104) +#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0104) #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 -#define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108) +#define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0108) #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c -#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c) +#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x010c) #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET 0x0120 -#define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120) +#define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0120) #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET 0x0124 -#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124) +#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0124) #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET 0x0128 -#define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128) +#define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0128) #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET 0x012c -#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c) +#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x012c) #define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET 0x0134 -#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134) +#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0134) #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET 0x0138 -#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138) +#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0138) #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET 0x013c -#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c) +#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x013c) #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 -#define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140) +#define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0140) #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 -#define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144) +#define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0144) #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 -#define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148) +#define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0148) #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c -#define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c) +#define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x014c) #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 -#define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150) +#define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0150) #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 -#define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154) +#define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0154) #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 -#define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158) +#define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0158) #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c -#define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c) +#define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x015c) #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET 0x0160 -#define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160) +#define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0160) #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET 0x0164 -#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164) +#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0164) #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET 0x0168 -#define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168) +#define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0168) #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET 0x016c -#define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c) +#define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x016c) #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 -#define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4) +#define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01a4) #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac -#define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac) +#define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01ac) #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 -#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4) +#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01b4) #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET 0x01bc -#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc) +#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01bc) #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 -#define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4) +#define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01c4) #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc -#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc) +#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01cc) #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET 0x01dc -#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc) +#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01dc) /* PRM.CEFUSE_PRM register offsets */ #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000) +#define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0000) #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004) +#define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0004) #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024) +#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0024) /* PRM.WKUP_PRM register offsets */ #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024) +#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0024) #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c) +#define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x002c) #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET 0x0030 -#define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030) +#define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0030) #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET 0x0034 -#define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034) +#define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0034) #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET 0x0038 -#define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038) +#define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0038) #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET 0x003c -#define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c) +#define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x003c) #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET 0x0040 -#define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040) +#define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0040) #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET 0x0044 -#define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044) +#define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0044) #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET 0x0048 -#define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048) +#define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0048) #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET 0x004c -#define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c) +#define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x004c) #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET 0x0054 -#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054) +#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0054) #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET 0x0058 -#define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058) +#define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0058) #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET 0x005c -#define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c) +#define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x005c) #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET 0x0064 -#define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064) +#define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0064) #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET 0x0078 -#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078) +#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0078) #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET 0x007c -#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c) +#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x007c) #define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET 0x0080 -#define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080) +#define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0080) #define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET 0x0084 -#define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084) +#define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0084) /* PRM.WKUP_CM register offsets */ #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000) +#define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0000) #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020) +#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0020) #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028) +#define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0028) #define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET 0x0030 -#define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030) +#define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0030) #define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET 0x0038 -#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038) +#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0038) #define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040) +#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0040) #define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET 0x0048 -#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048) +#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0048) #define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0050 -#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050) +#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0050) #define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET 0x0058 -#define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058) +#define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0058) #define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET 0x0060 -#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060) +#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0060) #define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET 0x0078 -#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078) +#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0078) #define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET 0x0080 -#define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080) +#define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0080) #define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET 0x0088 -#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088) +#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0088) /* PRM.EMU_PRM register offsets */ #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000) +#define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0000) #define OMAP4_PM_EMU_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004) +#define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0004) #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024) +#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0024) /* PRM.EMU_CM register offsets */ #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000) +#define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0000) #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008) +#define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0008) #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020) +#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0020) /* PRM.DEVICE_PRM register offsets */ #define OMAP4_PRM_RSTCTRL_OFFSET 0x0000 -#define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000) +#define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0000) #define OMAP4_PRM_RSTST_OFFSET 0x0004 -#define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004) +#define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0004) #define OMAP4_PRM_RSTTIME_OFFSET 0x0008 -#define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008) +#define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0008) #define OMAP4_PRM_CLKREQCTRL_OFFSET 0x000c -#define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c) +#define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x000c) #define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010 -#define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010) +#define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0010) #define OMAP4_PRM_PWRREQCTRL_OFFSET 0x0014 -#define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014) +#define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0014) #define OMAP4_PRM_PSCON_COUNT_OFFSET 0x0018 -#define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018) +#define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0018) #define OMAP4_PRM_IO_COUNT_OFFSET 0x001c -#define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c) +#define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x001c) #define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020 -#define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020) +#define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0020) #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 -#define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024) +#define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0024) #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 -#define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028) +#define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0028) #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c -#define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c) +#define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x002c) #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030 -#define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030) +#define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0030) #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 -#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034) +#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0034) #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 -#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038) +#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0038) #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c -#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c) +#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x003c) #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040 -#define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040) +#define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0040) #define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044 -#define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044) +#define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0044) #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 -#define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048) +#define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0048) #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c -#define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c) +#define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x004c) #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 -#define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050) +#define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0050) #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 -#define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054) +#define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0054) #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058 -#define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058) +#define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0058) #define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c -#define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c) +#define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x005c) #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 -#define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060) +#define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0060) #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 -#define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064) +#define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0064) #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 -#define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068) +#define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0068) #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c -#define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c) +#define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x006c) #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070 -#define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070) +#define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0070) #define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074 -#define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074) +#define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0074) #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078 -#define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078) +#define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0078) #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c -#define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c) +#define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x007c) #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080 -#define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080) +#define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0080) #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084 -#define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084) +#define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0084) #define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088 -#define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088) +#define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0088) #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c -#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c) +#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x008c) #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090 -#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090) +#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0090) #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 -#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094) +#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0094) #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098 -#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098) +#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0098) #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c -#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c) +#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x009c) #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 -#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0) +#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0) #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 -#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4) -#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8 -#define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8) +#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4) +#define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET 0x00a8 +#define OMAP4430_PRM_VC_CFG_I2C_INSTE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8) #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac -#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac) +#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac) #define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0 -#define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0) +#define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b0) #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET 0x00b4 -#define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4) +#define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b4) #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x00b8 -#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8) +#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b8) #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x00bc -#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc) +#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00bc) #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x00c0 -#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0) +#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c0) #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x00c4 -#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4) +#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c4) #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET 0x00c8 -#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8) +#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c8) #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET 0x00cc -#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc) +#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00cc) #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET 0x00d0 -#define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0) +#define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d0) #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET 0x00d4 -#define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4) +#define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d4) #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET 0x00d8 -#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8) +#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d8) #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc -#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc) +#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00dc) #define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0 -#define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) +#define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e0) #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 -#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4) +#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e4) #define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 -#define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8) +#define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e8) #define OMAP4_PRM_PHASE2A_CNDP_OFFSET 0x00ec -#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec) +#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec) #define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0 -#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0) -#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 -#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4) +#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0) +#define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET 0x00f4 +#define OMAP4430_PRM_INSTEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4) #define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 -#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8) +#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) -/* - * PRCM_MPU - * - * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global) - * point of view the PRCM_MPU is a single entity. It shares the same - * programming model as the global PRCM and thus can be assimilate as two new - * MOD inside the PRCM - */ +/* Function prototypes */ +# ifndef __ASSEMBLER__ + +extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx); +extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx); +extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); +extern u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg); +extern u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 idx); +extern u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx); +extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask); + +extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift); +extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift); +extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); + +extern void omap4_prm_global_warm_sw_reset(void); + +# endif -/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */ -#define OMAP4_REVISION_PRCM_OFFSET 0x0000 -#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD, 0x0000) - -/* PRCM_MPU.DEVICE_PRM register offsets */ -#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 -#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000) -#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 -#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004) - -/* PRCM_MPU.CPU0 register offsets */ -#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0000) -#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0004) -#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008 -#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0008) -#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c -#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x000c) -#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010 -#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0010) -#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014 -#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0014) -#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018 -#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0018) - -/* PRCM_MPU.CPU1 register offsets */ -#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0000) -#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0004) -#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008 -#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0008) -#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c -#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x000c) -#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010 -#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0010) -#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014 -#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0014) -#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 -#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0018) #endif diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c new file mode 100644 index 000000000000..a30324297278 --- /dev/null +++ b/arch/arm/mach-omap2/prminst44xx.c @@ -0,0 +1,66 @@ +/* + * OMAP4 PRM instance functions + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/io.h> + +#include <plat/common.h> + +#include "prm44xx.h" +#include "prminst44xx.h" +#include "prm-regbits-44xx.h" +#include "prcm44xx.h" +#include "prcm_mpu44xx.h" + +static u32 _prm_bases[OMAP4_MAX_PRCM_PARTITIONS] = { + [OMAP4430_INVALID_PRCM_PARTITION] = 0, + [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE, + [OMAP4430_CM1_PARTITION] = 0, + [OMAP4430_CM2_PARTITION] = 0, + [OMAP4430_SCRM_PARTITION] = 0, + [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE, +}; + +/* Read a register in a PRM instance */ +u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) +{ + BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || + part == OMAP4430_INVALID_PRCM_PARTITION || + !_prm_bases[part]); + return __raw_readl(OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + + idx)); +} + +/* Write into a register in a PRM instance */ +void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) +{ + BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || + part == OMAP4430_INVALID_PRCM_PARTITION || + !_prm_bases[part]); + __raw_writel(val, OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + idx)); +} + +/* Read-modify-write a register in PRM. Caller must lock */ +u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, + s16 idx) +{ + u32 v; + + v = omap4_prminst_read_inst_reg(part, inst, idx); + v &= ~mask; + v |= bits; + omap4_prminst_write_inst_reg(v, part, inst, idx); + + return v; +} diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h new file mode 100644 index 000000000000..02dd66ddda8b --- /dev/null +++ b/arch/arm/mach-omap2/prminst44xx.h @@ -0,0 +1,25 @@ +/* + * OMAP4 Power/Reset Management (PRM) function prototypes + * + * Copyright (C) 2010 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H +#define __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H + +/* + * In an ideal world, we would not export these low-level functions, + * but this will probably take some time to fix properly + */ +extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx); +extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx); +extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, + s16 inst, s16 idx); + +extern void omap4_prm_global_warm_sw_reset(void); + +#endif diff --git a/arch/arm/mach-omap2/scrm44xx.h b/arch/arm/mach-omap2/scrm44xx.h new file mode 100644 index 000000000000..701bf2d32949 --- /dev/null +++ b/arch/arm/mach-omap2/scrm44xx.h @@ -0,0 +1,175 @@ +/* + * OMAP44xx SCRM registers and bitfields + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H +#define __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H + +#define OMAP4_SCRM_BASE 0x4a30a000 + +#define OMAP44XX_SCRM_REGADDR(reg) \ + OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg)) + +/* Registers offset */ +#define OMAP4_SCRM_REVISION_SCRM_OFFSET 0x0000 +#define OMAP4_SCRM_REVISION_SCRM OMAP44XX_SCRM_REGADDR(0x0000) +#define OMAP4_SCRM_CLKSETUPTIME_OFFSET 0x0100 +#define OMAP4_SCRM_CLKSETUPTIME OMAP44XX_SCRM_REGADDR(0x0100) +#define OMAP4_SCRM_PMICSETUPTIME_OFFSET 0x0104 +#define OMAP4_SCRM_PMICSETUPTIME OMAP44XX_SCRM_REGADDR(0x0104) +#define OMAP4_SCRM_ALTCLKSRC_OFFSET 0x0110 +#define OMAP4_SCRM_ALTCLKSRC OMAP44XX_SCRM_REGADDR(0x0110) +#define OMAP4_SCRM_MODEMCLKM_OFFSET 0x0118 +#define OMAP4_SCRM_MODEMCLKM OMAP44XX_SCRM_REGADDR(0x0118) +#define OMAP4_SCRM_D2DCLKM_OFFSET 0x011c +#define OMAP4_SCRM_D2DCLKM OMAP44XX_SCRM_REGADDR(0x011c) +#define OMAP4_SCRM_EXTCLKREQ_OFFSET 0x0200 +#define OMAP4_SCRM_EXTCLKREQ OMAP44XX_SCRM_REGADDR(0x0200) +#define OMAP4_SCRM_ACCCLKREQ_OFFSET 0x0204 +#define OMAP4_SCRM_ACCCLKREQ OMAP44XX_SCRM_REGADDR(0x0204) +#define OMAP4_SCRM_PWRREQ_OFFSET 0x0208 +#define OMAP4_SCRM_PWRREQ OMAP44XX_SCRM_REGADDR(0x0208) +#define OMAP4_SCRM_AUXCLKREQ0_OFFSET 0x0210 +#define OMAP4_SCRM_AUXCLKREQ0 OMAP44XX_SCRM_REGADDR(0x0210) +#define OMAP4_SCRM_AUXCLKREQ1_OFFSET 0x0214 +#define OMAP4_SCRM_AUXCLKREQ1 OMAP44XX_SCRM_REGADDR(0x0214) +#define OMAP4_SCRM_AUXCLKREQ2_OFFSET 0x0218 +#define OMAP4_SCRM_AUXCLKREQ2 OMAP44XX_SCRM_REGADDR(0x0218) +#define OMAP4_SCRM_AUXCLKREQ3_OFFSET 0x021c +#define OMAP4_SCRM_AUXCLKREQ3 OMAP44XX_SCRM_REGADDR(0x021c) +#define OMAP4_SCRM_AUXCLKREQ4_OFFSET 0x0220 +#define OMAP4_SCRM_AUXCLKREQ4 OMAP44XX_SCRM_REGADDR(0x0220) +#define OMAP4_SCRM_AUXCLKREQ5_OFFSET 0x0224 +#define OMAP4_SCRM_AUXCLKREQ5 OMAP44XX_SCRM_REGADDR(0x0224) +#define OMAP4_SCRM_D2DCLKREQ_OFFSET 0x0234 +#define OMAP4_SCRM_D2DCLKREQ OMAP44XX_SCRM_REGADDR(0x0234) +#define OMAP4_SCRM_AUXCLK0_OFFSET 0x0310 +#define OMAP4_SCRM_AUXCLK0 OMAP44XX_SCRM_REGADDR(0x0310) +#define OMAP4_SCRM_AUXCLK1_OFFSET 0x0314 +#define OMAP4_SCRM_AUXCLK1 OMAP44XX_SCRM_REGADDR(0x0314) +#define OMAP4_SCRM_AUXCLK2_OFFSET 0x0318 +#define OMAP4_SCRM_AUXCLK2 OMAP44XX_SCRM_REGADDR(0x0318) +#define OMAP4_SCRM_AUXCLK3_OFFSET 0x031c +#define OMAP4_SCRM_AUXCLK3 OMAP44XX_SCRM_REGADDR(0x031c) +#define OMAP4_SCRM_AUXCLK4_OFFSET 0x0320 +#define OMAP4_SCRM_AUXCLK4 OMAP44XX_SCRM_REGADDR(0x0320) +#define OMAP4_SCRM_AUXCLK5_OFFSET 0x0324 +#define OMAP4_SCRM_AUXCLK5 OMAP44XX_SCRM_REGADDR(0x0324) +#define OMAP4_SCRM_RSTTIME_OFFSET 0x0400 +#define OMAP4_SCRM_RSTTIME OMAP44XX_SCRM_REGADDR(0x0400) +#define OMAP4_SCRM_MODEMRSTCTRL_OFFSET 0x0418 +#define OMAP4_SCRM_MODEMRSTCTRL OMAP44XX_SCRM_REGADDR(0x0418) +#define OMAP4_SCRM_D2DRSTCTRL_OFFSET 0x041c +#define OMAP4_SCRM_D2DRSTCTRL OMAP44XX_SCRM_REGADDR(0x041c) +#define OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420 +#define OMAP4_SCRM_EXTPWRONRSTCTRL OMAP44XX_SCRM_REGADDR(0x0420) +#define OMAP4_SCRM_EXTWARMRSTST_OFFSET 0x0510 +#define OMAP4_SCRM_EXTWARMRSTST OMAP44XX_SCRM_REGADDR(0x0510) +#define OMAP4_SCRM_APEWARMRSTST_OFFSET 0x0514 +#define OMAP4_SCRM_APEWARMRSTST OMAP44XX_SCRM_REGADDR(0x0514) +#define OMAP4_SCRM_MODEMWARMRSTST_OFFSET 0x0518 +#define OMAP4_SCRM_MODEMWARMRSTST OMAP44XX_SCRM_REGADDR(0x0518) +#define OMAP4_SCRM_D2DWARMRSTST_OFFSET 0x051c +#define OMAP4_SCRM_D2DWARMRSTST OMAP44XX_SCRM_REGADDR(0x051c) + +/* Registers shifts and masks */ + +/* REVISION_SCRM */ +#define OMAP4_REV_SHIFT 0 +#define OMAP4_REV_MASK (0xff << 0) + +/* CLKSETUPTIME */ +#define OMAP4_DOWNTIME_SHIFT 16 +#define OMAP4_DOWNTIME_MASK (0x3f << 16) +#define OMAP4_SETUPTIME_SHIFT 0 +#define OMAP4_SETUPTIME_MASK (0xfff << 0) + +/* PMICSETUPTIME */ +#define OMAP4_WAKEUPTIME_SHIFT 16 +#define OMAP4_WAKEUPTIME_MASK (0x3f << 16) +#define OMAP4_SLEEPTIME_SHIFT 0 +#define OMAP4_SLEEPTIME_MASK (0x3f << 0) + +/* ALTCLKSRC */ +#define OMAP4_ENABLE_EXT_SHIFT 3 +#define OMAP4_ENABLE_EXT_MASK (1 << 3) +#define OMAP4_ENABLE_INT_SHIFT 2 +#define OMAP4_ENABLE_INT_MASK (1 << 2) +#define OMAP4_ALTCLKSRC_MODE_SHIFT 0 +#define OMAP4_ALTCLKSRC_MODE_MASK (0x3 << 0) + +/* MODEMCLKM */ +#define OMAP4_CLK_32KHZ_SHIFT 0 +#define OMAP4_CLK_32KHZ_MASK (1 << 0) + +/* D2DCLKM */ +#define OMAP4_SYSCLK_SHIFT 1 +#define OMAP4_SYSCLK_MASK (1 << 1) + +/* EXTCLKREQ */ +#define OMAP4_POLARITY_SHIFT 0 +#define OMAP4_POLARITY_MASK (1 << 0) + +/* AUXCLKREQ0 */ +#define OMAP4_MAPPING_SHIFT 2 +#define OMAP4_MAPPING_MASK (0x7 << 2) +#define OMAP4_ACCURACY_SHIFT 1 +#define OMAP4_ACCURACY_MASK (1 << 1) + +/* AUXCLK0 */ +#define OMAP4_CLKDIV_SHIFT 16 +#define OMAP4_CLKDIV_MASK (0xf << 16) +#define OMAP4_DISABLECLK_SHIFT 9 +#define OMAP4_DISABLECLK_MASK (1 << 9) +#define OMAP4_ENABLE_SHIFT 8 +#define OMAP4_ENABLE_MASK (1 << 8) +#define OMAP4_SRCSELECT_SHIFT 1 +#define OMAP4_SRCSELECT_MASK (0x3 << 1) + +/* RSTTIME */ +#define OMAP4_RSTTIME_SHIFT 0 +#define OMAP4_RSTTIME_MASK (0xf << 0) + +/* MODEMRSTCTRL */ +#define OMAP4_WARMRST_SHIFT 1 +#define OMAP4_WARMRST_MASK (1 << 1) +#define OMAP4_COLDRST_SHIFT 0 +#define OMAP4_COLDRST_MASK (1 << 0) + +/* EXTPWRONRSTCTRL */ +#define OMAP4_PWRONRST_SHIFT 1 +#define OMAP4_PWRONRST_MASK (1 << 1) +#define OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT 0 +#define OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK (1 << 0) + +/* EXTWARMRSTST */ +#define OMAP4_EXTWARMRSTST_SHIFT 0 +#define OMAP4_EXTWARMRSTST_MASK (1 << 0) + +/* APEWARMRSTST */ +#define OMAP4_APEWARMRSTST_SHIFT 1 +#define OMAP4_APEWARMRSTST_MASK (1 << 1) + +/* MODEMWARMRSTST */ +#define OMAP4_MODEMWARMRSTST_SHIFT 2 +#define OMAP4_MODEMWARMRSTST_MASK (1 << 2) + +/* D2DWARMRSTST */ +#define OMAP4_D2DWARMRSTST_SHIFT 3 +#define OMAP4_D2DWARMRSTST_MASK (1 << 3) + +#endif diff --git a/arch/arm/mach-omap2/board-rx51-sdram.c b/arch/arm/mach-omap2/sdram-nokia.c index a43b2c5c838b..14caa228bc0d 100644 --- a/arch/arm/mach-omap2/board-rx51-sdram.c +++ b/arch/arm/mach-omap2/sdram-nokia.c @@ -1,7 +1,7 @@ /* - * SDRC register values for RX51 + * SDRC register values for Nokia boards * - * Copyright (C) 2008 Nokia Corporation + * Copyright (C) 2008, 2010 Nokia Corporation * * Lauri Leukkunen <lauri.leukkunen@nokia.com> * @@ -22,6 +22,7 @@ #include <plat/clock.h> #include <plat/sdrc.h> +#include "sdram-nokia.h" /* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */ struct sdram_timings { @@ -43,9 +44,28 @@ struct sdram_timings { u32 tWTR; }; -static struct omap_sdrc_params rx51_sdrc_params[4]; +static const struct sdram_timings nokia_97dot6mhz_timings[] = { + { + .casl = 3, + .tDAL = 30725, + .tDPL = 15362, + .tRRD = 10241, + .tRCD = 20483, + .tRP = 15362, + .tRAS = 40967, + .tRC = 56330, + .tRFC = 138266, + .tXSR = 204839, + + .tREF = 7798, + + .tXP = 2, + .tCKE = 4, + .tWTR = 2, + }, +}; -static const struct sdram_timings rx51_timings[] = { +static const struct sdram_timings nokia_166mhz_timings[] = { { .casl = 3, .tDAL = 33000, @@ -66,6 +86,38 @@ static const struct sdram_timings rx51_timings[] = { }, }; +static const struct sdram_timings nokia_195dot2mhz_timings[] = { + { + .casl = 3, + .tDAL = 30725, + .tDPL = 15362, + .tRRD = 10241, + .tRCD = 20483, + .tRP = 15362, + .tRAS = 40967, + .tRC = 56330, + .tRFC = 138266, + .tXSR = 204839, + + .tREF = 7752, + + .tXP = 2, + .tCKE = 4, + .tWTR = 2, + }, +}; + +static const struct { + long rate; + struct sdram_timings const *data; +} nokia_timings[] = { + { 83000000, nokia_166mhz_timings }, + { 97600000, nokia_97dot6mhz_timings }, + { 166000000, nokia_166mhz_timings }, + { 195200000, nokia_195dot2mhz_timings }, +}; +static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1]; + static unsigned long sdrc_get_fclk_period(long rate) { /* In picoseconds */ @@ -110,12 +162,12 @@ static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, #ifdef DEBUG #define SDRC_SET_ONE(reg, st, end, field, rate) \ if (set_sdrc_timing_regval((reg), (st), (end), \ - rx51_timings->field, (rate), #field) < 0) \ + memory_timings->field, (rate), #field) < 0) \ err = -1; #else #define SDRC_SET_ONE(reg, st, end, field, rate) \ if (set_sdrc_timing_regval((reg), (st), (end), \ - rx51_timings->field) < 0) \ + memory_timings->field) < 0) \ err = -1; #endif @@ -148,18 +200,19 @@ static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit, #ifdef DEBUG #define SDRC_SET_ONE_PS(reg, st, end, field, rate) \ if (set_sdrc_timing_regval_ps((reg), (st), (end), \ - rx51_timings->field, \ + memory_timings->field, \ (rate), #field) < 0) \ err = -1; #else #define SDRC_SET_ONE_PS(reg, st, end, field, rate) \ if (set_sdrc_timing_regval_ps((reg), (st), (end), \ - rx51_timings->field, (rate)) < 0) \ + memory_timings->field, (rate)) < 0) \ err = -1; #endif -static int sdrc_timings(int id, long rate) +static int sdrc_timings(int id, long rate, + const struct sdram_timings *memory_timings) { u32 ticks_per_ms; u32 rfr, l; @@ -184,7 +237,7 @@ static int sdrc_timings(int id, long rate) SDRC_SET_ONE(&actim_ctrlb, 16, 17, tWTR, l3_rate); ticks_per_ms = l3_rate; - rfr = rx51_timings[0].tREF * ticks_per_ms / 1000000; + rfr = memory_timings[0].tREF * ticks_per_ms / 1000000; if (rfr > 65535 + 50) rfr = 65535; else @@ -197,25 +250,30 @@ static int sdrc_timings(int id, long rate) l = rfr << 8; rfr_ctrl = l | 0x1; /* autorefresh, reload counter with 1xARCV */ - rx51_sdrc_params[id].rate = rate; - rx51_sdrc_params[id].actim_ctrla = actim_ctrla; - rx51_sdrc_params[id].actim_ctrlb = actim_ctrlb; - rx51_sdrc_params[id].rfr_ctrl = rfr_ctrl; - rx51_sdrc_params[id].mr = 0x32; + nokia_sdrc_params[id].rate = rate; + nokia_sdrc_params[id].actim_ctrla = actim_ctrla; + nokia_sdrc_params[id].actim_ctrlb = actim_ctrlb; + nokia_sdrc_params[id].rfr_ctrl = rfr_ctrl; + nokia_sdrc_params[id].mr = 0x32; - rx51_sdrc_params[id + 1].rate = 0; + nokia_sdrc_params[id + 1].rate = 0; return err; } -struct omap_sdrc_params *rx51_get_sdram_timings(void) +struct omap_sdrc_params *nokia_get_sdram_timings(void) { - int err; + int err = 0; + int i; - err = sdrc_timings(0, 41500000); - err |= sdrc_timings(1, 83000000); - err |= sdrc_timings(2, 166000000); + for (i = 0; i < ARRAY_SIZE(nokia_timings); i++) { + err |= sdrc_timings(i, nokia_timings[i].rate, + nokia_timings[i].data); + if (err) + pr_err("%s: error with rate %ld: %d\n", __func__, + nokia_timings[i].rate, err); + } - return &rx51_sdrc_params[0]; + return err ? NULL : nokia_sdrc_params; } diff --git a/arch/arm/mach-omap2/sdram-nokia.h b/arch/arm/mach-omap2/sdram-nokia.h new file mode 100644 index 000000000000..ee63da5f8df0 --- /dev/null +++ b/arch/arm/mach-omap2/sdram-nokia.h @@ -0,0 +1,12 @@ +/* + * SDRC register values for Nokia boards + * + * Copyright (C) 2010 Nokia + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +struct omap_sdrc_params *nokia_get_sdram_timings(void); + diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c index 4c65f5628b39..da6f3a63b5d5 100644 --- a/arch/arm/mach-omap2/sdrc.c +++ b/arch/arm/mach-omap2/sdrc.c @@ -27,8 +27,6 @@ #include <plat/clock.h> #include <plat/sram.h> -#include "prm.h" - #include <plat/sdrc.h> #include "sdrc.h" diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h index 68f57bb67fc5..b3f83799e6cf 100644 --- a/arch/arm/mach-omap2/sdrc.h +++ b/arch/arm/mach-omap2/sdrc.h @@ -74,5 +74,4 @@ static inline u32 sms_read_reg(u16 reg) */ #define SDRC_MPURATE_LOOPS 96 - #endif diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c index 0f4d27aef44d..ccdb010f169d 100644 --- a/arch/arm/mach-omap2/sdrc2xxx.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c @@ -28,7 +28,7 @@ #include <plat/clock.h> #include <plat/sram.h> -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "clock.h" #include <plat/sdrc.h> #include "sdrc.h" @@ -99,6 +99,10 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) m_type = omap2xxx_sdrc_get_type(); local_irq_save(flags); + /* + * XXX These calls should be abstracted out through a + * prm2xxx.c function + */ if (cpu_is_omap2420()) __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP); else diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index d17960a1be25..c64578853a8d 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -40,11 +40,12 @@ #include <plat/omap_hwmod.h> #include <plat/omap_device.h> -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "pm.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "prm-regbits-34xx.h" #include "control.h" +#include "mux.h" #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 #define UART_OMAP_WER 0x17 /* Wake-up enable register */ @@ -106,21 +107,16 @@ struct omap_uart_state { static LIST_HEAD(uart_list); static u8 num_uarts; -/* - * Since these idle/enable hooks are used in the idle path itself - * which has interrupts disabled, use the non-locking versions of - * the hwmod enable/disable functions. - */ static int uart_idle_hwmod(struct omap_device *od) { - _omap_hwmod_idle(od->hwmods[0]); + omap_hwmod_idle(od->hwmods[0]); return 0; } static int uart_enable_hwmod(struct omap_device *od) { - _omap_hwmod_enable(od->hwmods[0]); + omap_hwmod_enable(od->hwmods[0]); return 0; } @@ -169,9 +165,9 @@ static inline void serial_write_reg(struct omap_uart_state *uart, int offset, static inline void __init omap_uart_reset(struct omap_uart_state *uart) { - serial_write_reg(uart, UART_OMAP_MDR1, 0x07); + serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); serial_write_reg(uart, UART_OMAP_SCR, 0x08); - serial_write_reg(uart, UART_OMAP_MDR1, 0x00); + serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE); } #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) @@ -219,7 +215,7 @@ static void omap_uart_save_context(struct omap_uart_state *uart) return; lcr = serial_read_reg(uart, UART_LCR); - serial_write_reg(uart, UART_LCR, 0xBF); + serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); uart->dll = serial_read_reg(uart, UART_DLL); uart->dlh = serial_read_reg(uart, UART_DLM); serial_write_reg(uart, UART_LCR, lcr); @@ -227,7 +223,7 @@ static void omap_uart_save_context(struct omap_uart_state *uart) uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC); uart->scr = serial_read_reg(uart, UART_OMAP_SCR); uart->wer = serial_read_reg(uart, UART_OMAP_WER); - serial_write_reg(uart, UART_LCR, 0x80); + serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); uart->mcr = serial_read_reg(uart, UART_MCR); serial_write_reg(uart, UART_LCR, lcr); @@ -247,32 +243,35 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) uart->context_valid = 0; if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) - omap_uart_mdr1_errataset(uart, 0x07, 0xA0); + omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0); else - serial_write_reg(uart, UART_OMAP_MDR1, 0x7); - serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ + serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); + + serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); efr = serial_read_reg(uart, UART_EFR); serial_write_reg(uart, UART_EFR, UART_EFR_ECB); serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ serial_write_reg(uart, UART_IER, 0x0); - serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ + serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); serial_write_reg(uart, UART_DLL, uart->dll); serial_write_reg(uart, UART_DLM, uart->dlh); serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ serial_write_reg(uart, UART_IER, uart->ier); - serial_write_reg(uart, UART_LCR, 0x80); + serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); serial_write_reg(uart, UART_MCR, uart->mcr); - serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ + serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); serial_write_reg(uart, UART_EFR, efr); serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8); serial_write_reg(uart, UART_OMAP_SCR, uart->scr); serial_write_reg(uart, UART_OMAP_WER, uart->wer); serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc); + if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) - omap_uart_mdr1_errataset(uart, 0x00, 0xA1); + omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1); else /* UART 16x mode */ - serial_write_reg(uart, UART_OMAP_MDR1, 0x00); + serial_write_reg(uart, UART_OMAP_MDR1, + UART_OMAP_MDR1_16X_MODE); } #else static inline void omap_uart_save_context(struct omap_uart_state *uart) {} @@ -492,6 +491,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) u32 wk_mask = 0; u32 padconf = 0; + /* XXX These PRM accesses do not belong here */ uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); switch (uart->num) { @@ -695,16 +695,16 @@ void __init omap_serial_early_init(void) /** * omap_serial_init_port() - initialize single serial port - * @port: serial port number (0-3) + * @bdata: port specific board data pointer * - * This function initialies serial driver for given @port only. + * This function initialies serial driver for given port only. * Platforms can call this function instead of omap_serial_init() * if they don't plan to use all available UARTs as serial ports. * * Don't mix calls to omap_serial_init_port() and omap_serial_init(), * use only one of the two. */ -void __init omap_serial_init_port(int port) +void __init omap_serial_init_port(struct omap_board_data *bdata) { struct omap_uart_state *uart; struct omap_hwmod *oh; @@ -722,13 +722,15 @@ void __init omap_serial_init_port(int port) struct omap_uart_port_info omap_up; #endif - if (WARN_ON(port < 0)) + if (WARN_ON(!bdata)) + return; + if (WARN_ON(bdata->id < 0)) return; - if (WARN_ON(port >= num_uarts)) + if (WARN_ON(bdata->id >= num_uarts)) return; list_for_each_entry(uart, &uart_list, node) - if (port == uart->num) + if (bdata->id == uart->num) break; oh = uart->oh; @@ -800,6 +802,8 @@ void __init omap_serial_init_port(int port) WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n", name, oh->name); + oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); + uart->irq = oh->mpu_irqs[0].irq; uart->regshift = 2; uart->mapbase = oh->slaves[0]->addr->pa_start; @@ -857,7 +861,14 @@ void __init omap_serial_init_port(int port) void __init omap_serial_init(void) { struct omap_uart_state *uart; + struct omap_board_data bdata; - list_for_each_entry(uart, &uart_list, node) - omap_serial_init_port(uart->num); + list_for_each_entry(uart, &uart_list, node) { + bdata.id = uart->num; + bdata.flags = 0; + bdata.pads = NULL; + bdata.pads_cnt = 0; + omap_serial_init_port(&bdata); + + } } diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 2fb205a7f285..98d8232808b8 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -1,6 +1,4 @@ /* - * linux/arch/arm/mach-omap2/sleep.S - * * (C) Copyright 2007 * Texas Instruments * Karthik Dasu <karthik-dp@ti.com> @@ -26,28 +24,35 @@ */ #include <linux/linkage.h> #include <asm/assembler.h> +#include <plat/sram.h> #include <mach/io.h> -#include "cm.h" -#include "prm.h" +#include "cm2xxx_3xxx.h" +#include "prm2xxx_3xxx.h" #include "sdrc.h" #include "control.h" -#define SDRC_SCRATCHPAD_SEM_V 0xfa00291c - -#define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \ - OMAP3430_PM_PREPWSTST) -#define PM_PREPWSTST_CORE_P 0x48306AE8 -#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ - OMAP3430_PM_PREPWSTST) +/* + * Registers access definitions + */ +#define SDRC_SCRATCHPAD_SEM_OFFS 0xc +#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\ + (SDRC_SCRATCHPAD_SEM_OFFS) +#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\ + OMAP3430_PM_PREPWSTST #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) -#define SRAM_BASE_P 0x40200000 -#define CONTROL_STAT 0x480022F0 -#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is - * available */ -#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\ - + SCRATCHPAD_MEM_OFFS) +#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) +#define SRAM_BASE_P OMAP3_SRAM_PA +#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS +#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\ + OMAP36XX_CONTROL_MEM_RTA_CTRL) + +/* Move this as correct place is available */ +#define SCRATCHPAD_MEM_OFFS 0x310 +#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\ + OMAP343X_CONTROL_MEM_WKUP +\ + SCRATCHPAD_MEM_OFFS) #define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) #define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) #define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) @@ -59,48 +64,38 @@ #define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) #define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) - .text -/* Function to acquire the semaphore in scratchpad */ -ENTRY(lock_scratchpad_sem) - stmfd sp!, {lr} @ save registers on stack -wait_sem: - mov r0,#1 - ldr r1, sdrc_scratchpad_sem -wait_loop: - ldr r2, [r1] @ load the lock value - cmp r2, r0 @ is the lock free ? - beq wait_loop @ not free... - swp r2, r0, [r1] @ semaphore free so lock it and proceed - cmp r2, r0 @ did we succeed ? - beq wait_sem @ no - try again - ldmfd sp!, {pc} @ restore regs and return -sdrc_scratchpad_sem: - .word SDRC_SCRATCHPAD_SEM_V -ENTRY(lock_scratchpad_sem_sz) - .word . - lock_scratchpad_sem - - .text -/* Function to release the scratchpad semaphore */ -ENTRY(unlock_scratchpad_sem) - stmfd sp!, {lr} @ save registers on stack - ldr r3, sdrc_scratchpad_sem - mov r2,#0 - str r2,[r3] - ldmfd sp!, {pc} @ restore regs and return -ENTRY(unlock_scratchpad_sem_sz) - .word . - unlock_scratchpad_sem + +/* + * API functions + */ + +/* + * The "get_*restore_pointer" functions are used to provide a + * physical restore address where the ROM code jumps while waking + * up from MPU OFF/OSWR state. + * The restore pointer is stored into the scratchpad. + */ .text /* Function call to get the restore pointer for resume from OFF */ ENTRY(get_restore_pointer) - stmfd sp!, {lr} @ save registers on stack + stmfd sp!, {lr} @ save registers on stack adr r0, restore - ldmfd sp!, {pc} @ restore regs and return + ldmfd sp!, {pc} @ restore regs and return ENTRY(get_restore_pointer_sz) - .word . - get_restore_pointer + .word . - get_restore_pointer .text -/* Function call to get the restore pointer for for ES3 to resume from OFF */ +/* Function call to get the restore pointer for 3630 resume from OFF */ +ENTRY(get_omap3630_restore_pointer) + stmfd sp!, {lr} @ save registers on stack + adr r0, restore_3630 + ldmfd sp!, {pc} @ restore regs and return +ENTRY(get_omap3630_restore_pointer_sz) + .word . - get_omap3630_restore_pointer + + .text +/* Function call to get the restore pointer for ES3 to resume from OFF */ ENTRY(get_es3_restore_pointer) stmfd sp!, {lr} @ save registers on stack adr r0, restore_es3 @@ -108,54 +103,23 @@ ENTRY(get_es3_restore_pointer) ENTRY(get_es3_restore_pointer_sz) .word . - get_es3_restore_pointer -ENTRY(es3_sdrc_fix) - ldr r4, sdrc_syscfg @ get config addr - ldr r5, [r4] @ get value - tst r5, #0x100 @ is part access blocked - it eq - biceq r5, r5, #0x100 @ clear bit if set - str r5, [r4] @ write back change - ldr r4, sdrc_mr_0 @ get config addr - ldr r5, [r4] @ get value - str r5, [r4] @ write back change - ldr r4, sdrc_emr2_0 @ get config addr - ldr r5, [r4] @ get value - str r5, [r4] @ write back change - ldr r4, sdrc_manual_0 @ get config addr - mov r5, #0x2 @ autorefresh command - str r5, [r4] @ kick off refreshes - ldr r4, sdrc_mr_1 @ get config addr - ldr r5, [r4] @ get value - str r5, [r4] @ write back change - ldr r4, sdrc_emr2_1 @ get config addr - ldr r5, [r4] @ get value - str r5, [r4] @ write back change - ldr r4, sdrc_manual_1 @ get config addr - mov r5, #0x2 @ autorefresh command - str r5, [r4] @ kick off refreshes - bx lr -sdrc_syscfg: - .word SDRC_SYSCONFIG_P -sdrc_mr_0: - .word SDRC_MR_0_P -sdrc_emr2_0: - .word SDRC_EMR2_0_P -sdrc_manual_0: - .word SDRC_MANUAL_0_P -sdrc_mr_1: - .word SDRC_MR_1_P -sdrc_emr2_1: - .word SDRC_EMR2_1_P -sdrc_manual_1: - .word SDRC_MANUAL_1_P -ENTRY(es3_sdrc_fix_sz) - .word . - es3_sdrc_fix + .text +/* + * L2 cache needs to be toggled for stable OFF mode functionality on 3630. + * This function sets up a flag that will allow for this toggling to take + * place on 3630. Hopefully some version in the future may not need this. + */ +ENTRY(enable_omap3630_toggle_l2_on_restore) + stmfd sp!, {lr} @ save registers on stack + /* Setup so that we will disable and enable l2 */ + mov r1, #0x1 + str r1, l2dis_3630 + ldmfd sp!, {pc} @ restore regs and return + .text /* Function to call rom code to save secure ram context */ ENTRY(save_secure_ram_context) stmfd sp!, {r1-r12, lr} @ save registers on stack -save_secure_ram_debug: - /* b save_secure_ram_debug */ @ enable to debug save code adr r3, api_params @ r3 points to parameters str r0, [r3,#0x4] @ r0 has sdram address ldr r12, high_mask @@ -185,35 +149,162 @@ ENTRY(save_secure_ram_context_sz) .word . - save_secure_ram_context /* + * ====================== + * == Idle entry point == + * ====================== + */ + +/* * Forces OMAP into idle state * - * omap34xx_suspend() - This bit of code just executes the WFI - * for normal idles. + * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed + * and executes the WFI instruction. Calling WFI effectively changes the + * power domains states to the desired target power states. + * * - * Note: This code get's copied to internal SRAM at boot. When the OMAP - * wakes up it continues execution at the point it went to sleep. + * Notes: + * - this code gets copied to internal SRAM at boot and after wake-up + * from OFF mode. The execution pointer in SRAM is _omap_sram_idle. + * - when the OMAP wakes up it continues at different execution points + * depending on the low power mode (non-OFF vs OFF modes), + * cf. 'Resume path for xxx mode' comments. */ ENTRY(omap34xx_cpu_suspend) - stmfd sp!, {r0-r12, lr} @ save registers on stack -loop: - /*b loop*/ @Enable to debug by stepping through code - /* r0 contains restore pointer in sdram */ - /* r1 contains information about saving context */ - ldr r4, sdrc_power @ read the SDRC_POWER register - ldr r5, [r4] @ read the contents of SDRC_POWER - orr r5, r5, #0x40 @ enable self refresh on idle req - str r5, [r4] @ write back to SDRC_POWER register + stmfd sp!, {r0-r12, lr} @ save registers on stack + /* + * r0 contains restore pointer in sdram + * r1 contains information about saving context: + * 0 - No context lost + * 1 - Only L1 and logic lost + * 2 - Only L2 lost + * 3 - Both L1 and L2 lost + */ + + /* Directly jump to WFI is the context save is not required */ cmp r1, #0x0 - /* If context save is required, do that and execute wfi */ - bne save_context_wfi + beq omap3_do_wfi + + /* Otherwise fall through to the save context code */ +save_context_wfi: + mov r8, r0 @ Store SDRAM address in r8 + mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register + mov r4, #0x1 @ Number of parameters for restore call + stmia r8!, {r4-r5} @ Push parameters for restore call + mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register + stmia r8!, {r4-r5} @ Push parameters for restore call + + /* Check what that target sleep state is from r1 */ + cmp r1, #0x2 @ Only L2 lost, no need to save context + beq clean_caches + +l1_logic_lost: + /* Store sp and spsr to SDRAM */ + mov r4, sp + mrs r5, spsr + mov r6, lr + stmia r8!, {r4-r6} + /* Save all ARM registers */ + /* Coprocessor access control register */ + mrc p15, 0, r6, c1, c0, 2 + stmia r8!, {r6} + /* TTBR0, TTBR1 and Translation table base control */ + mrc p15, 0, r4, c2, c0, 0 + mrc p15, 0, r5, c2, c0, 1 + mrc p15, 0, r6, c2, c0, 2 + stmia r8!, {r4-r6} + /* + * Domain access control register, data fault status register, + * and instruction fault status register + */ + mrc p15, 0, r4, c3, c0, 0 + mrc p15, 0, r5, c5, c0, 0 + mrc p15, 0, r6, c5, c0, 1 + stmia r8!, {r4-r6} + /* + * Data aux fault status register, instruction aux fault status, + * data fault address register and instruction fault address register + */ + mrc p15, 0, r4, c5, c1, 0 + mrc p15, 0, r5, c5, c1, 1 + mrc p15, 0, r6, c6, c0, 0 + mrc p15, 0, r7, c6, c0, 2 + stmia r8!, {r4-r7} + /* + * user r/w thread and process ID, user r/o thread and process ID, + * priv only thread and process ID, cache size selection + */ + mrc p15, 0, r4, c13, c0, 2 + mrc p15, 0, r5, c13, c0, 3 + mrc p15, 0, r6, c13, c0, 4 + mrc p15, 2, r7, c0, c0, 0 + stmia r8!, {r4-r7} + /* Data TLB lockdown, instruction TLB lockdown registers */ + mrc p15, 0, r5, c10, c0, 0 + mrc p15, 0, r6, c10, c0, 1 + stmia r8!, {r5-r6} + /* Secure or non secure vector base address, FCSE PID, Context PID*/ + mrc p15, 0, r4, c12, c0, 0 + mrc p15, 0, r5, c13, c0, 0 + mrc p15, 0, r6, c13, c0, 1 + stmia r8!, {r4-r6} + /* Primary remap, normal remap registers */ + mrc p15, 0, r4, c10, c2, 0 + mrc p15, 0, r5, c10, c2, 1 + stmia r8!,{r4-r5} + + /* Store current cpsr*/ + mrs r2, cpsr + stmia r8!, {r2} + + mrc p15, 0, r4, c1, c0, 0 + /* save control register */ + stmia r8!, {r4} + +clean_caches: + /* + * Clean Data or unified cache to POU + * How to invalidate only L1 cache???? - #FIX_ME# + * mcr p15, 0, r11, c7, c11, 1 + */ + cmp r1, #0x1 @ Check whether L2 inval is required + beq omap3_do_wfi + +clean_l2: + /* + * jump out to kernel flush routine + * - reuse that code is better + * - it executes in a cached space so is faster than refetch per-block + * - should be faster and will change with kernel + * - 'might' have to copy address, load and jump to it + */ + ldr r1, kernel_flush + mov lr, pc + bx r1 + +omap3_do_wfi: + ldr r4, sdrc_power @ read the SDRC_POWER register + ldr r5, [r4] @ read the contents of SDRC_POWER + orr r5, r5, #0x40 @ enable self refresh on idle req + str r5, [r4] @ write back to SDRC_POWER register + /* Data memory barrier and Data sync barrier */ mov r1, #0 mcr p15, 0, r1, c7, c10, 4 mcr p15, 0, r1, c7, c10, 5 +/* + * =================================== + * == WFI instruction => Enter idle == + * =================================== + */ wfi @ wait for interrupt +/* + * =================================== + * == Resume path for non-OFF modes == + * =================================== + */ nop nop nop @@ -226,9 +317,30 @@ loop: nop bl wait_sdrc_ok - ldmfd sp!, {r0-r12, pc} @ restore regs and return +/* + * =================================== + * == Exit point from non-OFF modes == + * =================================== + */ + ldmfd sp!, {r0-r12, pc} @ restore regs and return + + +/* + * ============================== + * == Resume path for OFF mode == + * ============================== + */ + +/* + * The restore_* functions are called by the ROM code + * when back from WFI in OFF mode. + * Cf. the get_*restore_pointer functions. + * + * restore_es3: applies to 34xx >= ES3.0 + * restore_3630: applies to 36xx + * restore: common code for 3xxx + */ restore_es3: - /*b restore_es3*/ @ Enable to debug restore code ldr r5, pm_prepwstst_core_p ldr r4, [r5] and r4, r4, #0x3 @@ -245,82 +357,117 @@ copy_to_sram: bne copy_to_sram ldr r1, sram_base blx r1 + b restore + +restore_3630: + ldr r1, pm_prepwstst_core_p + ldr r2, [r1] + and r2, r2, #0x3 + cmp r2, #0x0 @ Check if previous power state of CORE is OFF + bne restore + /* Disable RTA before giving control */ + ldr r1, control_mem_rta + mov r2, #OMAP36XX_RTA_DISABLE + str r2, [r1] + + /* Fall through to common code for the remaining logic */ + restore: - /* b restore*/ @ Enable to debug restore code - /* Check what was the reason for mpu reset and store the reason in r9*/ - /* 1 - Only L1 and logic lost */ - /* 2 - Only L2 lost - In this case, we wont be here */ - /* 3 - Both L1 and L2 lost */ - ldr r1, pm_pwstctrl_mpu + /* + * Check what was the reason for mpu reset and store the reason in r9: + * 0 - No context lost + * 1 - Only L1 and logic lost + * 2 - Only L2 lost - In this case, we wont be here + * 3 - Both L1 and L2 lost + */ + ldr r1, pm_pwstctrl_mpu ldr r2, [r1] - and r2, r2, #0x3 - cmp r2, #0x0 @ Check if target power state was OFF or RET - moveq r9, #0x3 @ MPU OFF => L1 and L2 lost + and r2, r2, #0x3 + cmp r2, #0x0 @ Check if target power state was OFF or RET + moveq r9, #0x3 @ MPU OFF => L1 and L2 lost movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation bne logic_l1_restore + + ldr r0, l2dis_3630 + cmp r0, #0x1 @ should we disable L2 on 3630? + bne skipl2dis + mrc p15, 0, r0, c1, c0, 1 + bic r0, r0, #2 @ disable L2 cache + mcr p15, 0, r0, c1, c0, 1 +skipl2dis: ldr r0, control_stat ldr r1, [r0] and r1, #0x700 cmp r1, #0x300 beq l2_inv_gp - mov r0, #40 @ set service ID for PPA - mov r12, r0 @ copy secure Service ID in r12 - mov r1, #0 @ set task id for ROM code in r1 - mov r2, #4 @ set some flags in r2, r6 + mov r0, #40 @ set service ID for PPA + mov r12, r0 @ copy secure Service ID in r12 + mov r1, #0 @ set task id for ROM code in r1 + mov r2, #4 @ set some flags in r2, r6 mov r6, #0xff adr r3, l2_inv_api_params @ r3 points to dummy parameters mcr p15, 0, r0, c7, c10, 4 @ data write barrier mcr p15, 0, r0, c7, c10, 5 @ data memory barrier .word 0xE1600071 @ call SMI monitor (smi #1) /* Write to Aux control register to set some bits */ - mov r0, #42 @ set service ID for PPA - mov r12, r0 @ copy secure Service ID in r12 - mov r1, #0 @ set task id for ROM code in r1 - mov r2, #4 @ set some flags in r2, r6 + mov r0, #42 @ set service ID for PPA + mov r12, r0 @ copy secure Service ID in r12 + mov r1, #0 @ set task id for ROM code in r1 + mov r2, #4 @ set some flags in r2, r6 mov r6, #0xff ldr r4, scratchpad_base - ldr r3, [r4, #0xBC] @ r3 points to parameters + ldr r3, [r4, #0xBC] @ r3 points to parameters mcr p15, 0, r0, c7, c10, 4 @ data write barrier mcr p15, 0, r0, c7, c10, 5 @ data memory barrier .word 0xE1600071 @ call SMI monitor (smi #1) #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE /* Restore L2 aux control register */ - @ set service ID for PPA + @ set service ID for PPA mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID - mov r12, r0 @ copy service ID in r12 - mov r1, #0 @ set task ID for ROM code in r1 - mov r2, #4 @ set some flags in r2, r6 + mov r12, r0 @ copy service ID in r12 + mov r1, #0 @ set task ID for ROM code in r1 + mov r2, #4 @ set some flags in r2, r6 mov r6, #0xff ldr r4, scratchpad_base ldr r3, [r4, #0xBC] - adds r3, r3, #8 @ r3 points to parameters + adds r3, r3, #8 @ r3 points to parameters mcr p15, 0, r0, c7, c10, 4 @ data write barrier mcr p15, 0, r0, c7, c10, 5 @ data memory barrier .word 0xE1600071 @ call SMI monitor (smi #1) #endif b logic_l1_restore + l2_inv_api_params: - .word 0x1, 0x00 + .word 0x1, 0x00 l2_inv_gp: /* Execute smi to invalidate L2 cache */ - mov r12, #0x1 @ set up to invalide L2 -smi: .word 0xE1600070 @ Call SMI monitor (smieq) + mov r12, #0x1 @ set up to invalidate L2 + .word 0xE1600070 @ Call SMI monitor (smieq) /* Write to Aux control register to set some bits */ ldr r4, scratchpad_base ldr r3, [r4,#0xBC] ldr r0, [r3,#4] mov r12, #0x3 - .word 0xE1600070 @ Call SMI monitor (smieq) + .word 0xE1600070 @ Call SMI monitor (smieq) ldr r4, scratchpad_base ldr r3, [r4,#0xBC] ldr r0, [r3,#12] mov r12, #0x2 - .word 0xE1600070 @ Call SMI monitor (smieq) + .word 0xE1600070 @ Call SMI monitor (smieq) logic_l1_restore: + ldr r1, l2dis_3630 + cmp r1, #0x1 @ Test if L2 re-enable needed on 3630 + bne skipl2reen + mrc p15, 0, r1, c1, c0, 1 + orr r1, r1, #2 @ re-enable L2 cache + mcr p15, 0, r1, c1, c0, 1 +skipl2reen: mov r1, #0 - /* Invalidate all instruction caches to PoU - * and flush branch target cache */ + /* + * Invalidate all instruction caches to PoU + * and flush branch target cache + */ mcr p15, 0, r1, c7, c5, 0 ldr r4, scratchpad_base @@ -341,33 +488,33 @@ logic_l1_restore: MCR p15, 0, r6, c2, c0, 1 /* Translation table base control register */ MCR p15, 0, r7, c2, c0, 2 - /*domain access Control Register */ + /* Domain access Control Register */ MCR p15, 0, r8, c3, c0, 0 - /* data fault status Register */ + /* Data fault status Register */ MCR p15, 0, r9, c5, c0, 0 - ldmia r3!,{r4-r8} - /* instruction fault status Register */ + ldmia r3!,{r4-r8} + /* Instruction fault status Register */ MCR p15, 0, r4, c5, c0, 1 - /*Data Auxiliary Fault Status Register */ + /* Data Auxiliary Fault Status Register */ MCR p15, 0, r5, c5, c1, 0 - /*Instruction Auxiliary Fault Status Register*/ + /* Instruction Auxiliary Fault Status Register*/ MCR p15, 0, r6, c5, c1, 1 - /*Data Fault Address Register */ + /* Data Fault Address Register */ MCR p15, 0, r7, c6, c0, 0 - /*Instruction Fault Address Register*/ + /* Instruction Fault Address Register*/ MCR p15, 0, r8, c6, c0, 2 - ldmia r3!,{r4-r7} + ldmia r3!,{r4-r7} - /* user r/w thread and process ID */ + /* User r/w thread and process ID */ MCR p15, 0, r4, c13, c0, 2 - /* user ro thread and process ID */ + /* User ro thread and process ID */ MCR p15, 0, r5, c13, c0, 3 - /*Privileged only thread and process ID */ + /* Privileged only thread and process ID */ MCR p15, 0, r6, c13, c0, 4 - /* cache size selection */ + /* Cache size selection */ MCR p15, 2, r7, c0, c0, 0 - ldmia r3!,{r4-r8} + ldmia r3!,{r4-r8} /* Data TLB lockdown registers */ MCR p15, 0, r4, c10, c0, 0 /* Instruction TLB lockdown registers */ @@ -379,26 +526,27 @@ logic_l1_restore: /* Context PID */ MCR p15, 0, r8, c13, c0, 1 - ldmia r3!,{r4-r5} - /* primary memory remap register */ + ldmia r3!,{r4-r5} + /* Primary memory remap register */ MCR p15, 0, r4, c10, c2, 0 - /*normal memory remap register */ + /* Normal memory remap register */ MCR p15, 0, r5, c10, c2, 1 /* Restore cpsr */ - ldmia r3!,{r4} /*load CPSR from SDRAM*/ - msr cpsr, r4 /*store cpsr */ + ldmia r3!,{r4} @ load CPSR from SDRAM + msr cpsr, r4 @ store cpsr /* Enabling MMU here */ - mrc p15, 0, r7, c2, c0, 2 /* Read TTBRControl */ - /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/ + mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl + /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */ and r7, #0x7 cmp r7, #0x0 beq usettbr0 ttbr_error: - /* More work needs to be done to support N[0:2] value other than 0 - * So looping here so that the error can be detected - */ + /* + * More work needs to be done to support N[0:2] value other than 0 + * So looping here so that the error can be detected + */ b ttbr_error usettbr0: mrc p15, 0, r2, c2, c0, 0 @@ -406,21 +554,25 @@ usettbr0: and r2, r5 mov r4, pc ldr r5, table_index_mask - and r4, r5 /* r4 = 31 to 20 bits of pc */ + and r4, r5 @ r4 = 31 to 20 bits of pc /* Extract the value to be written to table entry */ ldr r1, table_entry - add r1, r1, r4 /* r1 has value to be written to table entry*/ + /* r1 has the value to be written to table entry*/ + add r1, r1, r4 /* Getting the address of table entry to modify */ lsr r4, #18 - add r2, r4 /* r2 has the location which needs to be modified */ + /* r2 has the location which needs to be modified */ + add r2, r4 /* Storing previous entry of location being modified */ ldr r5, scratchpad_base ldr r4, [r2] str r4, [r5, #0xC0] /* Modify the table entry */ str r1, [r2] - /* Storing address of entry being modified - * - will be restored after enabling MMU */ + /* + * Storing address of entry being modified + * - will be restored after enabling MMU + */ ldr r5, scratchpad_base str r2, [r5, #0xC4] @@ -429,8 +581,11 @@ usettbr0: mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB - /* Restore control register but dont enable caches here*/ - /* Caches will be enabled after restoring MMU table entry */ + /* + * Restore control register. This enables the MMU. + * The caches and prediction are not enabled here, they + * will be enabled after restoring the MMU table entry. + */ ldmia r3!, {r4} /* Store previous value of control register in scratchpad */ str r4, [r5, #0xC8] @@ -438,212 +593,144 @@ usettbr0: and r4, r2 mcr p15, 0, r4, c1, c0, 0 - ldmfd sp!, {r0-r12, pc} @ restore regs and return -save_context_wfi: - /*b save_context_wfi*/ @ enable to debug save code - mov r8, r0 /* Store SDRAM address in r8 */ - mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register - mov r4, #0x1 @ Number of parameters for restore call - stmia r8!, {r4-r5} @ Push parameters for restore call - mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register - stmia r8!, {r4-r5} @ Push parameters for restore call - /* Check what that target sleep state is:stored in r1*/ - /* 1 - Only L1 and logic lost */ - /* 2 - Only L2 lost */ - /* 3 - Both L1 and L2 lost */ - cmp r1, #0x2 /* Only L2 lost */ - beq clean_l2 - cmp r1, #0x1 /* L2 retained */ - /* r9 stores whether to clean L2 or not*/ - moveq r9, #0x0 /* Dont Clean L2 */ - movne r9, #0x1 /* Clean L2 */ -l1_logic_lost: - /* Store sp and spsr to SDRAM */ - mov r4, sp - mrs r5, spsr - mov r6, lr - stmia r8!, {r4-r6} - /* Save all ARM registers */ - /* Coprocessor access control register */ - mrc p15, 0, r6, c1, c0, 2 - stmia r8!, {r6} - /* TTBR0, TTBR1 and Translation table base control */ - mrc p15, 0, r4, c2, c0, 0 - mrc p15, 0, r5, c2, c0, 1 - mrc p15, 0, r6, c2, c0, 2 - stmia r8!, {r4-r6} - /* Domain access control register, data fault status register, - and instruction fault status register */ - mrc p15, 0, r4, c3, c0, 0 - mrc p15, 0, r5, c5, c0, 0 - mrc p15, 0, r6, c5, c0, 1 - stmia r8!, {r4-r6} - /* Data aux fault status register, instruction aux fault status, - datat fault address register and instruction fault address register*/ - mrc p15, 0, r4, c5, c1, 0 - mrc p15, 0, r5, c5, c1, 1 - mrc p15, 0, r6, c6, c0, 0 - mrc p15, 0, r7, c6, c0, 2 - stmia r8!, {r4-r7} - /* user r/w thread and process ID, user r/o thread and process ID, - priv only thread and process ID, cache size selection */ - mrc p15, 0, r4, c13, c0, 2 - mrc p15, 0, r5, c13, c0, 3 - mrc p15, 0, r6, c13, c0, 4 - mrc p15, 2, r7, c0, c0, 0 - stmia r8!, {r4-r7} - /* Data TLB lockdown, instruction TLB lockdown registers */ - mrc p15, 0, r5, c10, c0, 0 - mrc p15, 0, r6, c10, c0, 1 - stmia r8!, {r5-r6} - /* Secure or non secure vector base address, FCSE PID, Context PID*/ - mrc p15, 0, r4, c12, c0, 0 - mrc p15, 0, r5, c13, c0, 0 - mrc p15, 0, r6, c13, c0, 1 - stmia r8!, {r4-r6} - /* Primary remap, normal remap registers */ - mrc p15, 0, r4, c10, c2, 0 - mrc p15, 0, r5, c10, c2, 1 - stmia r8!,{r4-r5} +/* + * ============================== + * == Exit point from OFF mode == + * ============================== + */ + ldmfd sp!, {r0-r12, pc} @ restore regs and return - /* Store current cpsr*/ - mrs r2, cpsr - stmia r8!, {r2} - mrc p15, 0, r4, c1, c0, 0 - /* save control register */ - stmia r8!, {r4} -clean_caches: - /* Clean Data or unified cache to POU*/ - /* How to invalidate only L1 cache???? - #FIX_ME# */ - /* mcr p15, 0, r11, c7, c11, 1 */ - cmp r9, #1 /* Check whether L2 inval is required or not*/ - bne skip_l2_inval -clean_l2: - /* read clidr */ - mrc p15, 1, r0, c0, c0, 1 - /* extract loc from clidr */ - ands r3, r0, #0x7000000 - /* left align loc bit field */ - mov r3, r3, lsr #23 - /* if loc is 0, then no need to clean */ - beq finished - /* start clean at cache level 0 */ - mov r10, #0 -loop1: - /* work out 3x current cache level */ - add r2, r10, r10, lsr #1 - /* extract cache type bits from clidr*/ - mov r1, r0, lsr r2 - /* mask of the bits for current cache only */ - and r1, r1, #7 - /* see what cache we have at this level */ - cmp r1, #2 - /* skip if no cache, or just i-cache */ - blt skip - /* select current cache level in cssr */ - mcr p15, 2, r10, c0, c0, 0 - /* isb to sych the new cssr&csidr */ - isb - /* read the new csidr */ - mrc p15, 1, r1, c0, c0, 0 - /* extract the length of the cache lines */ - and r2, r1, #7 - /* add 4 (line length offset) */ - add r2, r2, #4 - ldr r4, assoc_mask - /* find maximum number on the way size */ - ands r4, r4, r1, lsr #3 - /* find bit position of way size increment */ - clz r5, r4 - ldr r7, numset_mask - /* extract max number of the index size*/ - ands r7, r7, r1, lsr #13 -loop2: - mov r9, r4 - /* create working copy of max way size*/ -loop3: - /* factor way and cache number into r11 */ - orr r11, r10, r9, lsl r5 - /* factor index number into r11 */ - orr r11, r11, r7, lsl r2 - /*clean & invalidate by set/way */ - mcr p15, 0, r11, c7, c10, 2 - /* decrement the way*/ - subs r9, r9, #1 - bge loop3 - /*decrement the index */ - subs r7, r7, #1 - bge loop2 -skip: - add r10, r10, #2 - /* increment cache number */ - cmp r3, r10 - bgt loop1 -finished: - /*swith back to cache level 0 */ - mov r10, #0 - /* select current cache level in cssr */ - mcr p15, 2, r10, c0, c0, 0 - isb -skip_l2_inval: - /* Data memory barrier and Data sync barrier */ - mov r1, #0 - mcr p15, 0, r1, c7, c10, 4 - mcr p15, 0, r1, c7, c10, 5 +/* + * Internal functions + */ - wfi @ wait for interrupt - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - bl wait_sdrc_ok - /* restore regs and return */ - ldmfd sp!, {r0-r12, pc} +/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */ + .text +ENTRY(es3_sdrc_fix) + ldr r4, sdrc_syscfg @ get config addr + ldr r5, [r4] @ get value + tst r5, #0x100 @ is part access blocked + it eq + biceq r5, r5, #0x100 @ clear bit if set + str r5, [r4] @ write back change + ldr r4, sdrc_mr_0 @ get config addr + ldr r5, [r4] @ get value + str r5, [r4] @ write back change + ldr r4, sdrc_emr2_0 @ get config addr + ldr r5, [r4] @ get value + str r5, [r4] @ write back change + ldr r4, sdrc_manual_0 @ get config addr + mov r5, #0x2 @ autorefresh command + str r5, [r4] @ kick off refreshes + ldr r4, sdrc_mr_1 @ get config addr + ldr r5, [r4] @ get value + str r5, [r4] @ write back change + ldr r4, sdrc_emr2_1 @ get config addr + ldr r5, [r4] @ get value + str r5, [r4] @ write back change + ldr r4, sdrc_manual_1 @ get config addr + mov r5, #0x2 @ autorefresh command + str r5, [r4] @ kick off refreshes + bx lr + +sdrc_syscfg: + .word SDRC_SYSCONFIG_P +sdrc_mr_0: + .word SDRC_MR_0_P +sdrc_emr2_0: + .word SDRC_EMR2_0_P +sdrc_manual_0: + .word SDRC_MANUAL_0_P +sdrc_mr_1: + .word SDRC_MR_1_P +sdrc_emr2_1: + .word SDRC_EMR2_1_P +sdrc_manual_1: + .word SDRC_MANUAL_1_P +ENTRY(es3_sdrc_fix_sz) + .word . - es3_sdrc_fix + +/* + * This function implements the erratum ID i581 WA: + * SDRC state restore before accessing the SDRAM + * + * Only used at return from non-OFF mode. For OFF + * mode the ROM code configures the SDRC and + * the DPLL before calling the restore code directly + * from DDR. + */ /* Make sure SDRC accesses are ok */ wait_sdrc_ok: - ldr r4, cm_idlest1_core - ldr r5, [r4] - and r5, r5, #0x2 - cmp r5, #0 - bne wait_sdrc_ok - ldr r4, sdrc_power - ldr r5, [r4] - bic r5, r5, #0x40 - str r5, [r4] + +/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */ + ldr r4, cm_idlest_ckgen +wait_dpll3_lock: + ldr r5, [r4] + tst r5, #1 + beq wait_dpll3_lock + + ldr r4, cm_idlest1_core +wait_sdrc_ready: + ldr r5, [r4] + tst r5, #0x2 + bne wait_sdrc_ready + /* allow DLL powerdown upon hw idle req */ + ldr r4, sdrc_power + ldr r5, [r4] + bic r5, r5, #0x40 + str r5, [r4] + +is_dll_in_lock_mode: + /* Is dll in lock mode? */ + ldr r4, sdrc_dlla_ctrl + ldr r5, [r4] + tst r5, #0x4 + bxne lr @ Return if locked + /* wait till dll locks */ +wait_dll_lock_timed: + ldr r4, wait_dll_lock_counter + add r4, r4, #1 + str r4, wait_dll_lock_counter + ldr r4, sdrc_dlla_status + /* Wait 20uS for lock */ + mov r6, #8 wait_dll_lock: - /* Is dll in lock mode? */ - ldr r4, sdrc_dlla_ctrl - ldr r5, [r4] - tst r5, #0x4 - bxne lr - /* wait till dll locks */ - ldr r4, sdrc_dlla_status - ldr r5, [r4] - and r5, r5, #0x4 - cmp r5, #0x4 - bne wait_dll_lock - bx lr + subs r6, r6, #0x1 + beq kick_dll + ldr r5, [r4] + and r5, r5, #0x4 + cmp r5, #0x4 + bne wait_dll_lock + bx lr @ Return when locked + + /* disable/reenable DLL if not locked */ +kick_dll: + ldr r4, sdrc_dlla_ctrl + ldr r5, [r4] + mov r6, r5 + bic r6, #(1<<3) @ disable dll + str r6, [r4] + dsb + orr r6, r6, #(1<<3) @ enable dll + str r6, [r4] + dsb + ldr r4, kick_counter + add r4, r4, #1 + str r4, kick_counter + b wait_dll_lock_timed cm_idlest1_core: .word CM_IDLEST1_CORE_V +cm_idlest_ckgen: + .word CM_IDLEST_CKGEN_V sdrc_dlla_status: .word SDRC_DLLA_STATUS_V sdrc_dlla_ctrl: .word SDRC_DLLA_CTRL_V -pm_prepwstst_core: - .word PM_PREPWSTST_CORE_V pm_prepwstst_core_p: .word PM_PREPWSTST_CORE_P -pm_prepwstst_mpu: - .word PM_PREPWSTST_MPU_V pm_pwstctrl_mpu: .word PM_PWSTCTRL_MPU_P scratchpad_base: @@ -651,13 +738,7 @@ scratchpad_base: sram_base: .word SRAM_BASE_P + 0x8000 sdrc_power: - .word SDRC_POWER_V -clk_stabilize_delay: - .word 0x000001FF -assoc_mask: - .word 0x3ff -numset_mask: - .word 0x7fff + .word SDRC_POWER_V ttbrbit_mask: .word 0xFFFFC000 table_index_mask: @@ -668,5 +749,20 @@ cache_pred_disable_mask: .word 0xFFFFE7FB control_stat: .word CONTROL_STAT +control_mem_rta: + .word CONTROL_MEM_RTA_CTRL +kernel_flush: + .word v7_flush_dcache_all +l2dis_3630: + .word 0 + /* + * When exporting to userspace while the counters are in SRAM, + * these 2 words need to be at the end to facilitate retrival! + */ +kick_counter: + .word 0 +wait_dll_lock_counter: + .word 0 + ENTRY(omap34xx_cpu_suspend_sz) .word . - omap34xx_cpu_suspend diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c new file mode 100644 index 000000000000..60e70552b4c5 --- /dev/null +++ b/arch/arm/mach-omap2/smartreflex-class3.c @@ -0,0 +1,59 @@ +/* + * Smart reflex Class 3 specific implementations + * + * Author: Thara Gopinath <thara@ti.com> + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Thara Gopinath <thara@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <plat/smartreflex.h> + +static int sr_class3_enable(struct voltagedomain *voltdm) +{ + unsigned long volt = omap_voltage_get_nom_volt(voltdm); + + if (!volt) { + pr_warning("%s: Curr voltage unknown. Cannot enable sr_%s\n", + __func__, voltdm->name); + return -ENODATA; + } + + omap_vp_enable(voltdm); + return sr_enable(voltdm, volt); +} + +static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset) +{ + omap_vp_disable(voltdm); + sr_disable(voltdm); + if (is_volt_reset) + omap_voltage_reset(voltdm); + + return 0; +} + +static int sr_class3_configure(struct voltagedomain *voltdm) +{ + return sr_configure_errgen(voltdm); +} + +/* SR class3 structure */ +static struct omap_sr_class_data class3_data = { + .enable = sr_class3_enable, + .disable = sr_class3_disable, + .configure = sr_class3_configure, + .class_type = SR_CLASS3, +}; + +/* Smartreflex Class3 init API to be called from board file */ +static int __init sr_class3_init(void) +{ + pr_info("SmartReflex Class3 initialized\n"); + return sr_register_class(&class3_data); +} +late_initcall(sr_class3_init); diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c new file mode 100644 index 000000000000..77ecebf3fae2 --- /dev/null +++ b/arch/arm/mach-omap2/smartreflex.c @@ -0,0 +1,1029 @@ +/* + * OMAP SmartReflex Voltage Control + * + * Author: Thara Gopinath <thara@ti.com> + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Thara Gopinath <thara@ti.com> + * + * Copyright (C) 2008 Nokia Corporation + * Kalle Jokiniemi + * + * Copyright (C) 2007 Texas Instruments, Inc. + * Lesly A M <x0080970@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/interrupt.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/debugfs.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/pm_runtime.h> + +#include <plat/common.h> +#include <plat/smartreflex.h> + +#include "pm.h" + +#define SMARTREFLEX_NAME_LEN 16 +#define NVALUE_NAME_LEN 40 +#define SR_DISABLE_TIMEOUT 200 + +struct omap_sr { + int srid; + int ip_type; + int nvalue_count; + bool autocomp_active; + u32 clk_length; + u32 err_weight; + u32 err_minlimit; + u32 err_maxlimit; + u32 accum_data; + u32 senn_avgweight; + u32 senp_avgweight; + u32 senp_mod; + u32 senn_mod; + unsigned int irq; + void __iomem *base; + struct platform_device *pdev; + struct list_head node; + struct omap_sr_nvalue_table *nvalue_table; + struct voltagedomain *voltdm; +}; + +/* sr_list contains all the instances of smartreflex module */ +static LIST_HEAD(sr_list); + +static struct omap_sr_class_data *sr_class; +static struct omap_sr_pmic_data *sr_pmic_data; + +static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value) +{ + __raw_writel(value, (sr->base + offset)); +} + +static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask, + u32 value) +{ + u32 reg_val; + u32 errconfig_offs = 0, errconfig_mask = 0; + + reg_val = __raw_readl(sr->base + offset); + reg_val &= ~mask; + + /* + * Smartreflex error config register is special as it contains + * certain status bits which if written a 1 into means a clear + * of those bits. So in order to make sure no accidental write of + * 1 happens to those status bits, do a clear of them in the read + * value. This mean this API doesn't rewrite values in these bits + * if they are currently set, but does allow the caller to write + * those bits. + */ + if (sr->ip_type == SR_TYPE_V1) { + errconfig_offs = ERRCONFIG_V1; + errconfig_mask = ERRCONFIG_STATUS_V1_MASK; + } else if (sr->ip_type == SR_TYPE_V2) { + errconfig_offs = ERRCONFIG_V2; + errconfig_mask = ERRCONFIG_VPBOUNDINTST_V2; + } + + if (offset == errconfig_offs) + reg_val &= ~errconfig_mask; + + reg_val |= value; + + __raw_writel(reg_val, (sr->base + offset)); +} + +static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset) +{ + return __raw_readl(sr->base + offset); +} + +static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm) +{ + struct omap_sr *sr_info; + + if (!voltdm) { + pr_err("%s: Null voltage domain passed!\n", __func__); + return ERR_PTR(-EINVAL); + } + + list_for_each_entry(sr_info, &sr_list, node) { + if (voltdm == sr_info->voltdm) + return sr_info; + } + + return ERR_PTR(-ENODATA); +} + +static irqreturn_t sr_interrupt(int irq, void *data) +{ + struct omap_sr *sr_info = (struct omap_sr *)data; + u32 status = 0; + + if (sr_info->ip_type == SR_TYPE_V1) { + /* Read the status bits */ + status = sr_read_reg(sr_info, ERRCONFIG_V1); + + /* Clear them by writing back */ + sr_write_reg(sr_info, ERRCONFIG_V1, status); + } else if (sr_info->ip_type == SR_TYPE_V2) { + /* Read the status bits */ + sr_read_reg(sr_info, IRQSTATUS); + + /* Clear them by writing back */ + sr_write_reg(sr_info, IRQSTATUS, status); + } + + if (sr_class->class_type == SR_CLASS2 && sr_class->notify) + sr_class->notify(sr_info->voltdm, status); + + return IRQ_HANDLED; +} + +static void sr_set_clk_length(struct omap_sr *sr) +{ + struct clk *sys_ck; + u32 sys_clk_speed; + + if (cpu_is_omap34xx()) + sys_ck = clk_get(NULL, "sys_ck"); + else + sys_ck = clk_get(NULL, "sys_clkin_ck"); + + if (IS_ERR(sys_ck)) { + dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n", + __func__); + return; + } + sys_clk_speed = clk_get_rate(sys_ck); + clk_put(sys_ck); + + switch (sys_clk_speed) { + case 12000000: + sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK; + break; + case 13000000: + sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK; + break; + case 19200000: + sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK; + break; + case 26000000: + sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK; + break; + case 38400000: + sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK; + break; + default: + dev_err(&sr->pdev->dev, "%s: Invalid sysclk value: %d\n", + __func__, sys_clk_speed); + break; + } +} + +static void sr_set_regfields(struct omap_sr *sr) +{ + /* + * For time being these values are defined in smartreflex.h + * and populated during init. May be they can be moved to board + * file or pmic specific data structure. In that case these structure + * fields will have to be populated using the pdata or pmic structure. + */ + if (cpu_is_omap34xx() || cpu_is_omap44xx()) { + sr->err_weight = OMAP3430_SR_ERRWEIGHT; + sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT; + sr->accum_data = OMAP3430_SR_ACCUMDATA; + if (!(strcmp(sr->voltdm->name, "mpu"))) { + sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT; + sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT; + } else { + sr->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT; + sr->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT; + } + } +} + +static void sr_start_vddautocomp(struct omap_sr *sr) +{ + if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) { + dev_warn(&sr->pdev->dev, + "%s: smartreflex class driver not registered\n", + __func__); + return; + } + + if (!sr_class->enable(sr->voltdm)) + sr->autocomp_active = true; +} + +static void sr_stop_vddautocomp(struct omap_sr *sr) +{ + if (!sr_class || !(sr_class->disable)) { + dev_warn(&sr->pdev->dev, + "%s: smartreflex class driver not registered\n", + __func__); + return; + } + + if (sr->autocomp_active) { + sr_class->disable(sr->voltdm, 1); + sr->autocomp_active = false; + } +} + +/* + * This function handles the intializations which have to be done + * only when both sr device and class driver regiter has + * completed. This will be attempted to be called from both sr class + * driver register and sr device intializtion API's. Only one call + * will ultimately succeed. + * + * Currenly this function registers interrrupt handler for a particular SR + * if smartreflex class driver is already registered and has + * requested for interrupts and the SR interrupt line in present. + */ +static int sr_late_init(struct omap_sr *sr_info) +{ + char *name; + struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data; + struct resource *mem; + int ret = 0; + + if (sr_class->class_type == SR_CLASS2 && + sr_class->notify_flags && sr_info->irq) { + + name = kzalloc(SMARTREFLEX_NAME_LEN + 1, GFP_KERNEL); + strcpy(name, "sr_"); + strcat(name, sr_info->voltdm->name); + ret = request_irq(sr_info->irq, sr_interrupt, + 0, name, (void *)sr_info); + if (ret) + goto error; + } + + if (pdata && pdata->enable_on_init) + sr_start_vddautocomp(sr_info); + + return ret; + +error: + iounmap(sr_info->base); + mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0); + release_mem_region(mem->start, resource_size(mem)); + list_del(&sr_info->node); + dev_err(&sr_info->pdev->dev, "%s: ERROR in registering" + "interrupt handler. Smartreflex will" + "not function as desired\n", __func__); + kfree(sr_info); + return ret; +} + +static void sr_v1_disable(struct omap_sr *sr) +{ + int timeout = 0; + + /* Enable MCUDisableAcknowledge interrupt */ + sr_modify_reg(sr, ERRCONFIG_V1, + ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN); + + /* SRCONFIG - disable SR */ + sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0); + + /* Disable all other SR interrupts and clear the status */ + sr_modify_reg(sr, ERRCONFIG_V1, + (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN | + ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1), + (ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST | + ERRCONFIG_MCUBOUNDINTST | + ERRCONFIG_VPBOUNDINTST_V1)); + + /* + * Wait for SR to be disabled. + * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us. + */ + omap_test_timeout((sr_read_reg(sr, ERRCONFIG_V1) & + ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT, + timeout); + + if (timeout >= SR_DISABLE_TIMEOUT) + dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n", + __func__); + + /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */ + sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN, + ERRCONFIG_MCUDISACKINTST); +} + +static void sr_v2_disable(struct omap_sr *sr) +{ + int timeout = 0; + + /* Enable MCUDisableAcknowledge interrupt */ + sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT); + + /* SRCONFIG - disable SR */ + sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0); + + /* Disable all other SR interrupts and clear the status */ + sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2, + ERRCONFIG_VPBOUNDINTST_V2); + sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT | + IRQENABLE_MCUVALIDINT | + IRQENABLE_MCUBOUNDSINT)); + sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT | + IRQSTATUS_MCVALIDINT | + IRQSTATUS_MCBOUNDSINT)); + + /* + * Wait for SR to be disabled. + * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us. + */ + omap_test_timeout((sr_read_reg(sr, IRQSTATUS) & + IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT, + timeout); + + if (timeout >= SR_DISABLE_TIMEOUT) + dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n", + __func__); + + /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */ + sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT); + sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT); +} + +static u32 sr_retrieve_nvalue(struct omap_sr *sr, u32 efuse_offs) +{ + int i; + + if (!sr->nvalue_table) { + dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n", + __func__); + return 0; + } + + for (i = 0; i < sr->nvalue_count; i++) { + if (sr->nvalue_table[i].efuse_offs == efuse_offs) + return sr->nvalue_table[i].nvalue; + } + + return 0; +} + +/* Public Functions */ + +/** + * sr_configure_errgen() - Configures the smrtreflex to perform AVS using the + * error generator module. + * @voltdm: VDD pointer to which the SR module to be configured belongs to. + * + * This API is to be called from the smartreflex class driver to + * configure the error generator module inside the smartreflex module. + * SR settings if using the ERROR module inside Smartreflex. + * SR CLASS 3 by default uses only the ERROR module where as + * SR CLASS 2 can choose between ERROR module and MINMAXAVG + * module. Returns 0 on success and error value in case of failure. + */ +int sr_configure_errgen(struct voltagedomain *voltdm) +{ + u32 sr_config, sr_errconfig, errconfig_offs, vpboundint_en; + u32 vpboundint_st, senp_en = 0, senn_en = 0; + u8 senp_shift, senn_shift; + struct omap_sr *sr = _sr_lookup(voltdm); + + if (IS_ERR(sr)) { + pr_warning("%s: omap_sr struct for sr_%s not found\n", + __func__, voltdm->name); + return -EINVAL; + } + + if (!sr->clk_length) + sr_set_clk_length(sr); + + senp_en = sr->senp_mod; + senn_en = sr->senn_mod; + + sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | + SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN; + + if (sr->ip_type == SR_TYPE_V1) { + sr_config |= SRCONFIG_DELAYCTRL; + senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT; + senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT; + errconfig_offs = ERRCONFIG_V1; + vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1; + vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1; + } else if (sr->ip_type == SR_TYPE_V2) { + senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT; + senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT; + errconfig_offs = ERRCONFIG_V2; + vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2; + vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2; + } else { + dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex" + "module without specifying the ip\n", __func__); + return -EINVAL; + } + + sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift)); + sr_write_reg(sr, SRCONFIG, sr_config); + sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) | + (sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) | + (sr->err_minlimit << ERRCONFIG_ERRMINLIMIT_SHIFT); + sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK | + SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK), + sr_errconfig); + + /* Enabling the interrupts if the ERROR module is used */ + sr_modify_reg(sr, errconfig_offs, + vpboundint_en, (vpboundint_en | vpboundint_st)); + + return 0; +} + +/** + * sr_configure_minmax() - Configures the smrtreflex to perform AVS using the + * minmaxavg module. + * @voltdm: VDD pointer to which the SR module to be configured belongs to. + * + * This API is to be called from the smartreflex class driver to + * configure the minmaxavg module inside the smartreflex module. + * SR settings if using the ERROR module inside Smartreflex. + * SR CLASS 3 by default uses only the ERROR module where as + * SR CLASS 2 can choose between ERROR module and MINMAXAVG + * module. Returns 0 on success and error value in case of failure. + */ +int sr_configure_minmax(struct voltagedomain *voltdm) +{ + u32 sr_config, sr_avgwt; + u32 senp_en = 0, senn_en = 0; + u8 senp_shift, senn_shift; + struct omap_sr *sr = _sr_lookup(voltdm); + + if (IS_ERR(sr)) { + pr_warning("%s: omap_sr struct for sr_%s not found\n", + __func__, voltdm->name); + return -EINVAL; + } + + if (!sr->clk_length) + sr_set_clk_length(sr); + + senp_en = sr->senp_mod; + senn_en = sr->senn_mod; + + sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | + SRCONFIG_SENENABLE | + (sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT); + + if (sr->ip_type == SR_TYPE_V1) { + sr_config |= SRCONFIG_DELAYCTRL; + senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT; + senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT; + } else if (sr->ip_type == SR_TYPE_V2) { + senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT; + senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT; + } else { + dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex" + "module without specifying the ip\n", __func__); + return -EINVAL; + } + + sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift)); + sr_write_reg(sr, SRCONFIG, sr_config); + sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) | + (sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT); + sr_write_reg(sr, AVGWEIGHT, sr_avgwt); + + /* + * Enabling the interrupts if MINMAXAVG module is used. + * TODO: check if all the interrupts are mandatory + */ + if (sr->ip_type == SR_TYPE_V1) { + sr_modify_reg(sr, ERRCONFIG_V1, + (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN | + ERRCONFIG_MCUBOUNDINTEN), + (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST | + ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST | + ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST)); + } else if (sr->ip_type == SR_TYPE_V2) { + sr_write_reg(sr, IRQSTATUS, + IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT | + IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT); + sr_write_reg(sr, IRQENABLE_SET, + IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT | + IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT); + } + + return 0; +} + +/** + * sr_enable() - Enables the smartreflex module. + * @voltdm: VDD pointer to which the SR module to be configured belongs to. + * @volt: The voltage at which the Voltage domain associated with + * the smartreflex module is operating at. + * This is required only to program the correct Ntarget value. + * + * This API is to be called from the smartreflex class driver to + * enable a smartreflex module. Returns 0 on success. Returns error + * value if the voltage passed is wrong or if ntarget value is wrong. + */ +int sr_enable(struct voltagedomain *voltdm, unsigned long volt) +{ + u32 nvalue_reciprocal; + struct omap_volt_data *volt_data; + struct omap_sr *sr = _sr_lookup(voltdm); + int ret; + + if (IS_ERR(sr)) { + pr_warning("%s: omap_sr struct for sr_%s not found\n", + __func__, voltdm->name); + return -EINVAL; + } + + volt_data = omap_voltage_get_voltdata(sr->voltdm, volt); + + if (IS_ERR(volt_data)) { + dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table" + "for nominal voltage %ld\n", __func__, volt); + return -ENODATA; + } + + nvalue_reciprocal = sr_retrieve_nvalue(sr, volt_data->sr_efuse_offs); + + if (!nvalue_reciprocal) { + dev_warn(&sr->pdev->dev, "%s: NVALUE = 0 at voltage %ld\n", + __func__, volt); + return -ENODATA; + } + + /* errminlimit is opp dependent and hence linked to voltage */ + sr->err_minlimit = volt_data->sr_errminlimit; + + pm_runtime_get_sync(&sr->pdev->dev); + + /* Check if SR is already enabled. If yes do nothing */ + if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) + return 0; + + /* Configure SR */ + ret = sr_class->configure(voltdm); + if (ret) + return ret; + + sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal); + + /* SRCONFIG - enable SR */ + sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE); + return 0; +} + +/** + * sr_disable() - Disables the smartreflex module. + * @voltdm: VDD pointer to which the SR module to be configured belongs to. + * + * This API is to be called from the smartreflex class driver to + * disable a smartreflex module. + */ +void sr_disable(struct voltagedomain *voltdm) +{ + struct omap_sr *sr = _sr_lookup(voltdm); + + if (IS_ERR(sr)) { + pr_warning("%s: omap_sr struct for sr_%s not found\n", + __func__, voltdm->name); + return; + } + + /* Check if SR clocks are already disabled. If yes do nothing */ + if (pm_runtime_suspended(&sr->pdev->dev)) + return; + + /* + * Disable SR if only it is indeed enabled. Else just + * disable the clocks. + */ + if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) { + if (sr->ip_type == SR_TYPE_V1) + sr_v1_disable(sr); + else if (sr->ip_type == SR_TYPE_V2) + sr_v2_disable(sr); + } + + pm_runtime_put_sync(&sr->pdev->dev); +} + +/** + * sr_register_class() - API to register a smartreflex class parameters. + * @class_data: The structure containing various sr class specific data. + * + * This API is to be called by the smartreflex class driver to register itself + * with the smartreflex driver during init. Returns 0 on success else the + * error value. + */ +int sr_register_class(struct omap_sr_class_data *class_data) +{ + struct omap_sr *sr_info; + + if (!class_data) { + pr_warning("%s:, Smartreflex class data passed is NULL\n", + __func__); + return -EINVAL; + } + + if (sr_class) { + pr_warning("%s: Smartreflex class driver already registered\n", + __func__); + return -EBUSY; + } + + sr_class = class_data; + + /* + * Call into late init to do intializations that require + * both sr driver and sr class driver to be initiallized. + */ + list_for_each_entry(sr_info, &sr_list, node) + sr_late_init(sr_info); + + return 0; +} + +/** + * omap_sr_enable() - API to enable SR clocks and to call into the + * registered smartreflex class enable API. + * @voltdm: VDD pointer to which the SR module to be configured belongs to. + * + * This API is to be called from the kernel in order to enable + * a particular smartreflex module. This API will do the initial + * configurations to turn on the smartreflex module and in turn call + * into the registered smartreflex class enable API. + */ +void omap_sr_enable(struct voltagedomain *voltdm) +{ + struct omap_sr *sr = _sr_lookup(voltdm); + + if (IS_ERR(sr)) { + pr_warning("%s: omap_sr struct for sr_%s not found\n", + __func__, voltdm->name); + return; + } + + if (!sr->autocomp_active) + return; + + if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) { + dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not" + "registered\n", __func__); + return; + } + + sr_class->enable(voltdm); +} + +/** + * omap_sr_disable() - API to disable SR without resetting the voltage + * processor voltage + * @voltdm: VDD pointer to which the SR module to be configured belongs to. + * + * This API is to be called from the kernel in order to disable + * a particular smartreflex module. This API will in turn call + * into the registered smartreflex class disable API. This API will tell + * the smartreflex class disable not to reset the VP voltage after + * disabling smartreflex. + */ +void omap_sr_disable(struct voltagedomain *voltdm) +{ + struct omap_sr *sr = _sr_lookup(voltdm); + + if (IS_ERR(sr)) { + pr_warning("%s: omap_sr struct for sr_%s not found\n", + __func__, voltdm->name); + return; + } + + if (!sr->autocomp_active) + return; + + if (!sr_class || !(sr_class->disable)) { + dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not" + "registered\n", __func__); + return; + } + + sr_class->disable(voltdm, 0); +} + +/** + * omap_sr_disable_reset_volt() - API to disable SR and reset the + * voltage processor voltage + * @voltdm: VDD pointer to which the SR module to be configured belongs to. + * + * This API is to be called from the kernel in order to disable + * a particular smartreflex module. This API will in turn call + * into the registered smartreflex class disable API. This API will tell + * the smartreflex class disable to reset the VP voltage after + * disabling smartreflex. + */ +void omap_sr_disable_reset_volt(struct voltagedomain *voltdm) +{ + struct omap_sr *sr = _sr_lookup(voltdm); + + if (IS_ERR(sr)) { + pr_warning("%s: omap_sr struct for sr_%s not found\n", + __func__, voltdm->name); + return; + } + + if (!sr->autocomp_active) + return; + + if (!sr_class || !(sr_class->disable)) { + dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not" + "registered\n", __func__); + return; + } + + sr_class->disable(voltdm, 1); +} + +/** + * omap_sr_register_pmic() - API to register pmic specific info. + * @pmic_data: The structure containing pmic specific data. + * + * This API is to be called from the PMIC specific code to register with + * smartreflex driver pmic specific info. Currently the only info required + * is the smartreflex init on the PMIC side. + */ +void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data) +{ + if (!pmic_data) { + pr_warning("%s: Trying to register NULL PMIC data structure" + "with smartreflex\n", __func__); + return; + } + + sr_pmic_data = pmic_data; +} + +/* PM Debug Fs enteries to enable disable smartreflex. */ +static int omap_sr_autocomp_show(void *data, u64 *val) +{ + struct omap_sr *sr_info = (struct omap_sr *) data; + + if (!sr_info) { + pr_warning("%s: omap_sr struct for sr_%s not found\n", + __func__, sr_info->voltdm->name); + return -EINVAL; + } + + *val = sr_info->autocomp_active; + + return 0; +} + +static int omap_sr_autocomp_store(void *data, u64 val) +{ + struct omap_sr *sr_info = (struct omap_sr *) data; + + if (!sr_info) { + pr_warning("%s: omap_sr struct for sr_%s not found\n", + __func__, sr_info->voltdm->name); + return -EINVAL; + } + + /* Sanity check */ + if (val && (val != 1)) { + pr_warning("%s: Invalid argument %lld\n", __func__, val); + return -EINVAL; + } + + if (!val) + sr_stop_vddautocomp(sr_info); + else + sr_start_vddautocomp(sr_info); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show, + omap_sr_autocomp_store, "%llu\n"); + +static int __init omap_sr_probe(struct platform_device *pdev) +{ + struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL); + struct omap_sr_data *pdata = pdev->dev.platform_data; + struct resource *mem, *irq; + struct dentry *vdd_dbg_dir, *dbg_dir, *nvalue_dir; + struct omap_volt_data *volt_data; + int i, ret = 0; + + if (!sr_info) { + dev_err(&pdev->dev, "%s: unable to allocate sr_info\n", + __func__); + return -ENOMEM; + } + + if (!pdata) { + dev_err(&pdev->dev, "%s: platform data missing\n", __func__); + return -EINVAL; + } + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(&pdev->dev, "%s: no mem resource\n", __func__); + ret = -ENODEV; + goto err_free_devinfo; + } + + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + + pm_runtime_enable(&pdev->dev); + + sr_info->pdev = pdev; + sr_info->srid = pdev->id; + sr_info->voltdm = pdata->voltdm; + sr_info->nvalue_table = pdata->nvalue_table; + sr_info->nvalue_count = pdata->nvalue_count; + sr_info->senn_mod = pdata->senn_mod; + sr_info->senp_mod = pdata->senp_mod; + sr_info->autocomp_active = false; + sr_info->ip_type = pdata->ip_type; + sr_info->base = ioremap(mem->start, resource_size(mem)); + if (!sr_info->base) { + dev_err(&pdev->dev, "%s: ioremap fail\n", __func__); + ret = -ENOMEM; + goto err_release_region; + } + + if (irq) + sr_info->irq = irq->start; + + sr_set_clk_length(sr_info); + sr_set_regfields(sr_info); + + list_add(&sr_info->node, &sr_list); + + /* + * Call into late init to do intializations that require + * both sr driver and sr class driver to be initiallized. + */ + if (sr_class) { + ret = sr_late_init(sr_info); + if (ret) { + pr_warning("%s: Error in SR late init\n", __func__); + return ret; + } + } + + dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__); + + /* + * If the voltage domain debugfs directory is not created, do + * not try to create rest of the debugfs entries. + */ + vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm); + if (!vdd_dbg_dir) + return -EINVAL; + + dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir); + if (IS_ERR(dbg_dir)) { + dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n", + __func__); + return PTR_ERR(dbg_dir); + } + + (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUGO, dbg_dir, + (void *)sr_info, &pm_sr_fops); + (void) debugfs_create_x32("errweight", S_IRUGO, dbg_dir, + &sr_info->err_weight); + (void) debugfs_create_x32("errmaxlimit", S_IRUGO, dbg_dir, + &sr_info->err_maxlimit); + (void) debugfs_create_x32("errminlimit", S_IRUGO, dbg_dir, + &sr_info->err_minlimit); + + nvalue_dir = debugfs_create_dir("nvalue", dbg_dir); + if (IS_ERR(nvalue_dir)) { + dev_err(&pdev->dev, "%s: Unable to create debugfs directory" + "for n-values\n", __func__); + return PTR_ERR(nvalue_dir); + } + + omap_voltage_get_volttable(sr_info->voltdm, &volt_data); + if (!volt_data) { + dev_warn(&pdev->dev, "%s: No Voltage table for the" + " corresponding vdd vdd_%s. Cannot create debugfs" + "entries for n-values\n", + __func__, sr_info->voltdm->name); + return -ENODATA; + } + + for (i = 0; i < sr_info->nvalue_count; i++) { + char *name; + char volt_name[32]; + + name = kzalloc(NVALUE_NAME_LEN + 1, GFP_KERNEL); + if (!name) { + dev_err(&pdev->dev, "%s: Unable to allocate memory" + " for n-value directory name\n", __func__); + return -ENOMEM; + } + + strcpy(name, "volt_"); + sprintf(volt_name, "%d", volt_data[i].volt_nominal); + strcat(name, volt_name); + (void) debugfs_create_x32(name, S_IRUGO | S_IWUGO, nvalue_dir, + &(sr_info->nvalue_table[i].nvalue)); + } + + return ret; + +err_release_region: + release_mem_region(mem->start, resource_size(mem)); +err_free_devinfo: + kfree(sr_info); + + return ret; +} + +static int __devexit omap_sr_remove(struct platform_device *pdev) +{ + struct omap_sr_data *pdata = pdev->dev.platform_data; + struct omap_sr *sr_info; + struct resource *mem; + + if (!pdata) { + dev_err(&pdev->dev, "%s: platform data missing\n", __func__); + return -EINVAL; + } + + sr_info = _sr_lookup(pdata->voltdm); + if (!sr_info) { + dev_warn(&pdev->dev, "%s: omap_sr struct not found\n", + __func__); + return -EINVAL; + } + + if (sr_info->autocomp_active) + sr_stop_vddautocomp(sr_info); + + list_del(&sr_info->node); + iounmap(sr_info->base); + kfree(sr_info); + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(mem->start, resource_size(mem)); + + return 0; +} + +static struct platform_driver smartreflex_driver = { + .remove = omap_sr_remove, + .driver = { + .name = "smartreflex", + }, +}; + +static int __init sr_init(void) +{ + int ret = 0; + + /* + * sr_init is a late init. If by then a pmic specific API is not + * registered either there is no need for anything to be done on + * the PMIC side or somebody has forgotten to register a PMIC + * handler. Warn for the second condition. + */ + if (sr_pmic_data && sr_pmic_data->sr_pmic_init) + sr_pmic_data->sr_pmic_init(); + else + pr_warning("%s: No PMIC hook to init smartreflex\n", __func__); + + ret = platform_driver_probe(&smartreflex_driver, omap_sr_probe); + if (ret) { + pr_err("%s: platform driver register failed for SR\n", + __func__); + return ret; + } + + return 0; +} + +static void __exit sr_exit(void) +{ + platform_driver_unregister(&smartreflex_driver); +} +late_initcall(sr_init); +module_exit(sr_exit); + +MODULE_DESCRIPTION("OMAP Smartreflex Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRIVER_NAME); +MODULE_AUTHOR("Texas Instruments Inc"); diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c new file mode 100644 index 000000000000..786d685c09a9 --- /dev/null +++ b/arch/arm/mach-omap2/sr_device.c @@ -0,0 +1,146 @@ +/* + * OMAP3/OMAP4 smartreflex device file + * + * Author: Thara Gopinath <thara@ti.com> + * + * Based originally on code from smartreflex.c + * Copyright (C) 2010 Texas Instruments, Inc. + * Thara Gopinath <thara@ti.com> + * + * Copyright (C) 2008 Nokia Corporation + * Kalle Jokiniemi + * + * Copyright (C) 2007 Texas Instruments, Inc. + * Lesly A M <x0080970@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/slab.h> +#include <linux/io.h> + +#include <plat/omap_device.h> +#include <plat/smartreflex.h> +#include <plat/voltage.h> + +#include "control.h" + +static bool sr_enable_on_init; + +static struct omap_device_pm_latency omap_sr_latency[] = { + { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST + }, +}; + +/* Read EFUSE values from control registers for OMAP3430 */ +static void __init sr_set_nvalues(struct omap_volt_data *volt_data, + struct omap_sr_data *sr_data) +{ + struct omap_sr_nvalue_table *nvalue_table; + int i, count = 0; + + while (volt_data[count].volt_nominal) + count++; + + nvalue_table = kzalloc(sizeof(struct omap_sr_nvalue_table)*count, + GFP_KERNEL); + + for (i = 0; i < count; i++) { + u32 v; + /* + * In OMAP4 the efuse registers are 24 bit aligned. + * A __raw_readl will fail for non-32 bit aligned address + * and hence the 8-bit read and shift. + */ + if (cpu_is_omap44xx()) { + u16 offset = volt_data[i].sr_efuse_offs; + + v = omap_ctrl_readb(offset) | + omap_ctrl_readb(offset + 1) << 8 | + omap_ctrl_readb(offset + 2) << 16; + } else { + v = omap_ctrl_readl(volt_data[i].sr_efuse_offs); + } + + nvalue_table[i].efuse_offs = volt_data[i].sr_efuse_offs; + nvalue_table[i].nvalue = v; + } + + sr_data->nvalue_table = nvalue_table; + sr_data->nvalue_count = count; +} + +static int sr_dev_init(struct omap_hwmod *oh, void *user) +{ + struct omap_sr_data *sr_data; + struct omap_device *od; + struct omap_volt_data *volt_data; + char *name = "smartreflex"; + static int i; + + sr_data = kzalloc(sizeof(struct omap_sr_data), GFP_KERNEL); + if (!sr_data) { + pr_err("%s: Unable to allocate memory for %s sr_data.Error!\n", + __func__, oh->name); + return -ENOMEM; + } + + if (!oh->vdd_name) { + pr_err("%s: No voltage domain specified for %s." + "Cannot initialize\n", __func__, oh->name); + goto exit; + } + + sr_data->ip_type = oh->class->rev; + sr_data->senn_mod = 0x1; + sr_data->senp_mod = 0x1; + + sr_data->voltdm = omap_voltage_domain_lookup(oh->vdd_name); + if (IS_ERR(sr_data->voltdm)) { + pr_err("%s: Unable to get voltage domain pointer for VDD %s\n", + __func__, oh->vdd_name); + goto exit; + } + + omap_voltage_get_volttable(sr_data->voltdm, &volt_data); + if (!volt_data) { + pr_warning("%s: No Voltage table registerd fo VDD%d." + "Something really wrong\n\n", __func__, i + 1); + goto exit; + } + + sr_set_nvalues(volt_data, sr_data); + + sr_data->enable_on_init = sr_enable_on_init; + + od = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data), + omap_sr_latency, + ARRAY_SIZE(omap_sr_latency), 0); + if (IS_ERR(od)) + pr_warning("%s: Could not build omap_device for %s: %s.\n\n", + __func__, name, oh->name); +exit: + i++; + kfree(sr_data); + return 0; +} + +/* + * API to be called from board files to enable smartreflex + * autocompensation at init. + */ +void __init omap_enable_smartreflex_on_init(void) +{ + sr_enable_on_init = true; +} + +int __init omap_devinit_smartreflex(void) +{ + return omap_hwmod_for_each_by_class("smartreflex", sr_dev_init, NULL); +} diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S index 92e6e1a12af8..055310cc77de 100644 --- a/arch/arm/mach-omap2/sram242x.S +++ b/arch/arm/mach-omap2/sram242x.S @@ -21,14 +21,20 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * + * Richard Woodruff notes that any changes to this code must be carefully + * audited and tested to ensure that they don't cause a TLB miss while + * the SDRAM is inaccessible. Such a situation will crash the system + * since it will cause the ARM MMU to attempt to walk the page tables. + * These crashes may be intermittent. */ #include <linux/linkage.h> #include <asm/assembler.h> #include <mach/io.h> #include <mach/hardware.h> -#include "prm.h" -#include "cm.h" +#include "prm2xxx_3xxx.h" +#include "cm2xxx_3xxx.h" #include "sdrc.h" .text diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S index ab4973695c71..f9007580aea3 100644 --- a/arch/arm/mach-omap2/sram243x.S +++ b/arch/arm/mach-omap2/sram243x.S @@ -21,14 +21,20 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * + * Richard Woodruff notes that any changes to this code must be carefully + * audited and tested to ensure that they don't cause a TLB miss while + * the SDRAM is inaccessible. Such a situation will crash the system + * since it will cause the ARM MMU to attempt to walk the page tables. + * These crashes may be intermittent. */ #include <linux/linkage.h> #include <asm/assembler.h> #include <mach/io.h> #include <mach/hardware.h> -#include "prm.h" -#include "cm.h" +#include "prm2xxx_3xxx.h" +#include "cm2xxx_3xxx.h" #include "sdrc.h" .text diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 3637274af5be..7f893a29d500 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -32,7 +32,7 @@ #include <mach/io.h> #include "sdrc.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" .text @@ -104,6 +104,12 @@ * touching the SDRAM. Until that time, users who know that their use case * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING * option. + * + * Richard Woodruff notes that any changes to this code must be carefully + * audited and tested to ensure that they don't cause a TLB miss while + * the SDRAM is inaccessible. Such a situation will crash the system + * since it will cause the ARM MMU to attempt to walk the page tables. + * These crashes may be intermittent. */ ENTRY(omap3_sram_configure_core_dpll) stmfd sp!, {r1-r12, lr} @ store regs to stack diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index a7816dbdc6b1..4e48e786bec7 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@ -202,7 +202,7 @@ static struct clocksource clocksource_gpt = { static void __init omap2_gp_clocksource_init(void) { static struct omap_dm_timer *gpt; - u32 tick_rate, tick_period; + u32 tick_rate; static char err1[] __initdata = KERN_ERR "%s: failed to request dm-timer\n"; static char err2[] __initdata = KERN_ERR @@ -215,7 +215,6 @@ static void __init omap2_gp_clocksource_init(void) omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt)); - tick_period = (tick_rate / HZ) - 1; omap_dm_timer_set_load_start(gpt, 1, 0); diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c index b11bf385d360..25eeadabc39b 100644 --- a/arch/arm/mach-omap2/usb-ehci.c +++ b/arch/arm/mach-omap2/usb-ehci.c @@ -34,22 +34,15 @@ static struct resource ehci_resources[] = { { - .start = OMAP34XX_EHCI_BASE, - .end = OMAP34XX_EHCI_BASE + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .start = OMAP34XX_UHH_CONFIG_BASE, - .end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .start = OMAP34XX_USBTLL_BASE, - .end = OMAP34XX_USBTLL_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, { /* general IRQ */ - .start = INT_34XX_EHCI_IRQ, .flags = IORESOURCE_IRQ, } }; @@ -214,13 +207,148 @@ static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) return; } +static void setup_4430ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) +{ + switch (port_mode[0]) { + case EHCI_HCD_OMAP_MODE_PHY: + omap_mux_init_signal("usbb1_ulpiphy_stp", + OMAP_PIN_OUTPUT); + omap_mux_init_signal("usbb1_ulpiphy_clk", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpiphy_dir", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpiphy_nxt", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpiphy_dat0", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpiphy_dat1", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpiphy_dat2", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpiphy_dat3", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpiphy_dat4", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpiphy_dat5", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpiphy_dat6", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpiphy_dat7", + OMAP_PIN_INPUT_PULLDOWN); + break; + case EHCI_HCD_OMAP_MODE_TLL: + omap_mux_init_signal("usbb1_ulpitll_stp", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("usbb1_ulpitll_clk", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpitll_dir", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpitll_nxt", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpitll_dat0", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpitll_dat1", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpitll_dat2", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpitll_dat3", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpitll_dat4", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpitll_dat5", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpitll_dat6", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_ulpitll_dat7", + OMAP_PIN_INPUT_PULLDOWN); + break; + case EHCI_HCD_OMAP_MODE_UNKNOWN: + default: + break; + } + switch (port_mode[1]) { + case EHCI_HCD_OMAP_MODE_PHY: + omap_mux_init_signal("usbb2_ulpiphy_stp", + OMAP_PIN_OUTPUT); + omap_mux_init_signal("usbb2_ulpiphy_clk", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpiphy_dir", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpiphy_nxt", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpiphy_dat0", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpiphy_dat1", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpiphy_dat2", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpiphy_dat3", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpiphy_dat4", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpiphy_dat5", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpiphy_dat6", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpiphy_dat7", + OMAP_PIN_INPUT_PULLDOWN); + break; + case EHCI_HCD_OMAP_MODE_TLL: + omap_mux_init_signal("usbb2_ulpitll_stp", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("usbb2_ulpitll_clk", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpitll_dir", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpitll_nxt", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpitll_dat0", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpitll_dat1", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpitll_dat2", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpitll_dat3", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpitll_dat4", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpitll_dat5", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpitll_dat6", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_ulpitll_dat7", + OMAP_PIN_INPUT_PULLDOWN); + break; + case EHCI_HCD_OMAP_MODE_UNKNOWN: + default: + break; + } +} + void __init usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata) { platform_device_add_data(&ehci_device, pdata, sizeof(*pdata)); /* Setup Pin IO MUX for EHCI */ - if (cpu_is_omap34xx()) + if (cpu_is_omap34xx()) { + ehci_resources[0].start = OMAP34XX_EHCI_BASE; + ehci_resources[0].end = OMAP34XX_EHCI_BASE + SZ_1K - 1; + ehci_resources[1].start = OMAP34XX_UHH_CONFIG_BASE; + ehci_resources[1].end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1; + ehci_resources[2].start = OMAP34XX_USBTLL_BASE; + ehci_resources[2].end = OMAP34XX_USBTLL_BASE + SZ_4K - 1; + ehci_resources[3].start = INT_34XX_EHCI_IRQ; setup_ehci_io_mux(pdata->port_mode); + } else if (cpu_is_omap44xx()) { + ehci_resources[0].start = OMAP44XX_HSUSB_EHCI_BASE; + ehci_resources[0].end = OMAP44XX_HSUSB_EHCI_BASE + SZ_1K - 1; + ehci_resources[1].start = OMAP44XX_UHH_CONFIG_BASE; + ehci_resources[1].end = OMAP44XX_UHH_CONFIG_BASE + SZ_2K - 1; + ehci_resources[2].start = OMAP44XX_USBTLL_BASE; + ehci_resources[2].end = OMAP44XX_USBTLL_BASE + SZ_4K - 1; + ehci_resources[3].start = OMAP44XX_IRQ_EHCI; + setup_4430ehci_io_mux(pdata->port_mode); + } if (platform_device_register(&ehci_device) < 0) { printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n"); diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 72605584bfff..5298949d4b11 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -30,8 +30,101 @@ #include <mach/irqs.h> #include <mach/am35xx.h> #include <plat/usb.h> +#include "control.h" -#ifdef CONFIG_USB_MUSB_SOC +#if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X) + +static void am35x_musb_reset(void) +{ + u32 regval; + + /* Reset the musb interface */ + regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); + + regval |= AM35XX_USBOTGSS_SW_RST; + omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); + + regval &= ~AM35XX_USBOTGSS_SW_RST; + omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); + + regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); +} + +static void am35x_musb_phy_power(u8 on) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(100); + u32 devconf2; + + if (on) { + /* + * Start the on-chip PHY and its PLL. + */ + devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + + devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN); + devconf2 |= CONF2_PHY_PLLON; + + omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); + + pr_info(KERN_INFO "Waiting for PHY clock good...\n"); + while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) + & CONF2_PHYCLKGD)) { + cpu_relax(); + + if (time_after(jiffies, timeout)) { + pr_err(KERN_ERR "musb PHY clock good timed out\n"); + break; + } + } + } else { + /* + * Power down the on-chip PHY. + */ + devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + + devconf2 &= ~CONF2_PHY_PLLON; + devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN; + omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); + } +} + +static void am35x_musb_clear_irq(void) +{ + u32 regval; + + regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + regval |= AM35XX_USBOTGSS_INT_CLR; + omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); + regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); +} + +static void am35x_musb_set_mode(u8 musb_mode) +{ + u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + + devconf2 &= ~CONF2_OTGMODE; + switch (musb_mode) { +#ifdef CONFIG_USB_MUSB_HDRC_HCD + case MUSB_HOST: /* Force VBUS valid, ID = 0 */ + devconf2 |= CONF2_FORCE_HOST; + break; +#endif +#ifdef CONFIG_USB_GADGET_MUSB_HDRC + case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ + devconf2 |= CONF2_FORCE_DEVICE; + break; +#endif +#ifdef CONFIG_USB_MUSB_OTG + case MUSB_OTG: /* Don't override the VBUS/ID comparators */ + devconf2 |= CONF2_NO_OVERRIDE; + break; +#endif + default: + pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode); + } + + omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); +} static struct resource musb_resources[] = { [0] = { /* start and end set dynamically */ @@ -40,10 +133,12 @@ static struct resource musb_resources[] = { [1] = { /* general IRQ */ .start = INT_243X_HS_USB_MC, .flags = IORESOURCE_IRQ, + .name = "mc", }, [2] = { /* DMA IRQ */ .start = INT_243X_HS_USB_DMA, .flags = IORESOURCE_IRQ, + .name = "dma", }, }; @@ -75,7 +170,7 @@ static struct musb_hdrc_platform_data musb_plat = { static u64 musb_dmamask = DMA_BIT_MASK(32); static struct platform_device musb_device = { - .name = "musb_hdrc", + .name = "musb-omap2430", .id = -1, .dev = { .dma_mask = &musb_dmamask, @@ -91,8 +186,13 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data) if (cpu_is_omap243x()) { musb_resources[0].start = OMAP243X_HS_BASE; } else if (cpu_is_omap3517() || cpu_is_omap3505()) { + musb_device.name = "musb-am35x"; musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE; musb_resources[1].start = INT_35XX_USBOTG_IRQ; + board_data->set_phy_power = am35x_musb_phy_power; + board_data->clear_irq = am35x_musb_clear_irq; + board_data->set_mode = am35x_musb_set_mode; + board_data->reset = am35x_musb_reset; } else if (cpu_is_omap34xx()) { musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; } else if (cpu_is_omap44xx()) { diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index 64a0112b70a5..8a3c05f3c1d6 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c @@ -120,8 +120,8 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps) t.adv_on = next_clk(t.cs_on, t_scsnh_advnh - 7000, fclk_ps); /* GPMC_CLK rate = fclk rate / div */ - t.sync_clk = 12 /* 11.1 nsec */; - tmp = (t.sync_clk * 1000 + fclk_ps - 1) / fclk_ps; + t.sync_clk = 11100 /* 11.1 nsec */; + tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps; if (tmp > 4) return -ERANGE; if (tmp <= 0) @@ -216,6 +216,7 @@ static struct resource tusb_resources[] = { .flags = IORESOURCE_MEM, }, { /* IRQ */ + .name = "mc", .flags = IORESOURCE_IRQ, }, }; @@ -223,7 +224,7 @@ static struct resource tusb_resources[] = { static u64 tusb_dmamask = ~(u32)0; static struct platform_device tusb_device = { - .name = "musb_hdrc", + .name = "musb-tusb", .id = -1, .dev = { .dma_mask = &tusb_dmamask, diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c new file mode 100644 index 000000000000..ed6079c94c57 --- /dev/null +++ b/arch/arm/mach-omap2/voltage.c @@ -0,0 +1,1571 @@ +/* + * OMAP3/OMAP4 Voltage Management Routines + * + * Author: Thara Gopinath <thara@ti.com> + * + * Copyright (C) 2007 Texas Instruments, Inc. + * Rajendra Nayak <rnayak@ti.com> + * Lesly A M <x0080970@ti.com> + * + * Copyright (C) 2008 Nokia Corporation + * Kalle Jokiniemi + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Thara Gopinath <thara@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/debugfs.h> +#include <linux/slab.h> + +#include <plat/common.h> +#include <plat/voltage.h> + +#include "prm-regbits-34xx.h" +#include "prm-regbits-44xx.h" +#include "prm44xx.h" +#include "prcm44xx.h" +#include "prminst44xx.h" +#include "control.h" + +#define VP_IDLE_TIMEOUT 200 +#define VP_TRANXDONE_TIMEOUT 300 +#define VOLTAGE_DIR_SIZE 16 + +/* Voltage processor register offsets */ +struct vp_reg_offs { + u8 vpconfig; + u8 vstepmin; + u8 vstepmax; + u8 vlimitto; + u8 vstatus; + u8 voltage; +}; + +/* Voltage Processor bit field values, shifts and masks */ +struct vp_reg_val { + /* PRM module */ + u16 prm_mod; + /* VPx_VPCONFIG */ + u32 vpconfig_erroroffset; + u16 vpconfig_errorgain; + u32 vpconfig_errorgain_mask; + u8 vpconfig_errorgain_shift; + u32 vpconfig_initvoltage_mask; + u8 vpconfig_initvoltage_shift; + u32 vpconfig_timeouten; + u32 vpconfig_initvdd; + u32 vpconfig_forceupdate; + u32 vpconfig_vpenable; + /* VPx_VSTEPMIN */ + u8 vstepmin_stepmin; + u16 vstepmin_smpswaittimemin; + u8 vstepmin_stepmin_shift; + u8 vstepmin_smpswaittimemin_shift; + /* VPx_VSTEPMAX */ + u8 vstepmax_stepmax; + u16 vstepmax_smpswaittimemax; + u8 vstepmax_stepmax_shift; + u8 vstepmax_smpswaittimemax_shift; + /* VPx_VLIMITTO */ + u8 vlimitto_vddmin; + u8 vlimitto_vddmax; + u16 vlimitto_timeout; + u8 vlimitto_vddmin_shift; + u8 vlimitto_vddmax_shift; + u8 vlimitto_timeout_shift; + /* PRM_IRQSTATUS*/ + u32 tranxdone_status; +}; + +/* Voltage controller registers and offsets */ +struct vc_reg_info { + /* PRM module */ + u16 prm_mod; + /* VC register offsets */ + u8 smps_sa_reg; + u8 smps_volra_reg; + u8 bypass_val_reg; + u8 cmdval_reg; + u8 voltsetup_reg; + /*VC_SMPS_SA*/ + u8 smps_sa_shift; + u32 smps_sa_mask; + /* VC_SMPS_VOL_RA */ + u8 smps_volra_shift; + u32 smps_volra_mask; + /* VC_BYPASS_VAL */ + u8 data_shift; + u8 slaveaddr_shift; + u8 regaddr_shift; + u32 valid; + /* VC_CMD_VAL */ + u8 cmd_on_shift; + u8 cmd_onlp_shift; + u8 cmd_ret_shift; + u8 cmd_off_shift; + u32 cmd_on_mask; + /* PRM_VOLTSETUP */ + u8 voltsetup_shift; + u32 voltsetup_mask; +}; + +/** + * omap_vdd_info - Per Voltage Domain info + * + * @volt_data : voltage table having the distinct voltages supported + * by the domain and other associated per voltage data. + * @pmic_info : pmic specific parameters which should be populted by + * the pmic drivers. + * @vp_offs : structure containing the offsets for various + * vp registers + * @vp_reg : the register values, shifts, masks for various + * vp registers + * @vc_reg : structure containing various various vc registers, + * shifts, masks etc. + * @voltdm : pointer to the voltage domain structure + * @debug_dir : debug directory for this voltage domain. + * @curr_volt : current voltage for this vdd. + * @ocp_mod : The prm module for accessing the prm irqstatus reg. + * @prm_irqst_reg : prm irqstatus register. + * @vp_enabled : flag to keep track of whether vp is enabled or not + * @volt_scale : API to scale the voltage of the vdd. + */ +struct omap_vdd_info { + struct omap_volt_data *volt_data; + struct omap_volt_pmic_info *pmic_info; + struct vp_reg_offs vp_offs; + struct vp_reg_val vp_reg; + struct vc_reg_info vc_reg; + struct voltagedomain voltdm; + struct dentry *debug_dir; + u32 curr_volt; + u16 ocp_mod; + u8 prm_irqst_reg; + bool vp_enabled; + u32 (*read_reg) (u16 mod, u8 offset); + void (*write_reg) (u32 val, u16 mod, u8 offset); + int (*volt_scale) (struct omap_vdd_info *vdd, + unsigned long target_volt); +}; + +static struct omap_vdd_info *vdd_info; +/* + * Number of scalable voltage domains. + */ +static int nr_scalable_vdd; + +/* OMAP3 VDD sturctures */ +static struct omap_vdd_info omap3_vdd_info[] = { + { + .vp_offs = { + .vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET, + .vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET, + .vstepmax = OMAP3_PRM_VP1_VSTEPMAX_OFFSET, + .vlimitto = OMAP3_PRM_VP1_VLIMITTO_OFFSET, + .vstatus = OMAP3_PRM_VP1_STATUS_OFFSET, + .voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET, + }, + .voltdm = { + .name = "mpu", + }, + }, + { + .vp_offs = { + .vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET, + .vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET, + .vstepmax = OMAP3_PRM_VP2_VSTEPMAX_OFFSET, + .vlimitto = OMAP3_PRM_VP2_VLIMITTO_OFFSET, + .vstatus = OMAP3_PRM_VP2_STATUS_OFFSET, + .voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET, + }, + .voltdm = { + .name = "core", + }, + }, +}; + +#define OMAP3_NR_SCALABLE_VDD ARRAY_SIZE(omap3_vdd_info) + +/* OMAP4 VDD sturctures */ +static struct omap_vdd_info omap4_vdd_info[] = { + { + .vp_offs = { + .vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET, + .vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET, + .vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET, + .vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET, + .vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET, + .voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET, + }, + .voltdm = { + .name = "mpu", + }, + }, + { + .vp_offs = { + .vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET, + .vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET, + .vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET, + .vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET, + .vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET, + .voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET, + }, + .voltdm = { + .name = "iva", + }, + }, + { + .vp_offs = { + .vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET, + .vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET, + .vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET, + .vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET, + .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET, + .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET, + }, + .voltdm = { + .name = "core", + }, + }, +}; + +#define OMAP4_NR_SCALABLE_VDD ARRAY_SIZE(omap4_vdd_info) + +/* + * Structures containing OMAP3430/OMAP3630 voltage supported and various + * voltage dependent data for each VDD. + */ +#define VOLT_DATA_DEFINE(_v_nom, _efuse_offs, _errminlimit, _errgain) \ +{ \ + .volt_nominal = _v_nom, \ + .sr_efuse_offs = _efuse_offs, \ + .sr_errminlimit = _errminlimit, \ + .vp_errgain = _errgain \ +} + +/* VDD1 */ +static struct omap_volt_data omap34xx_vddmpu_volt_data[] = { + VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c), + VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c), + VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18), + VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18), + VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18), + VOLT_DATA_DEFINE(0, 0, 0, 0), +}; + +static struct omap_volt_data omap36xx_vddmpu_volt_data[] = { + VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c), + VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16), + VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23), + VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27), + VOLT_DATA_DEFINE(0, 0, 0, 0), +}; + +/* VDD2 */ +static struct omap_volt_data omap34xx_vddcore_volt_data[] = { + VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c), + VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c), + VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18), + VOLT_DATA_DEFINE(0, 0, 0, 0), +}; + +static struct omap_volt_data omap36xx_vddcore_volt_data[] = { + VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c), + VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16), + VOLT_DATA_DEFINE(0, 0, 0, 0), +}; + +/* + * Structures containing OMAP4430 voltage supported and various + * voltage dependent data for each VDD. + */ +static struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = { + VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c), + VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16), + VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23), + VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27), + VOLT_DATA_DEFINE(0, 0, 0, 0), +}; + +static struct omap_volt_data omap44xx_vdd_iva_volt_data[] = { + VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c), + VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16), + VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23), + VOLT_DATA_DEFINE(0, 0, 0, 0), +}; + +static struct omap_volt_data omap44xx_vdd_core_volt_data[] = { + VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c), + VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16), + VOLT_DATA_DEFINE(0, 0, 0, 0), +}; + +static struct dentry *voltage_dir; + +/* Init function pointers */ +static void (*vc_init) (struct omap_vdd_info *vdd); +static int (*vdd_data_configure) (struct omap_vdd_info *vdd); + +static u32 omap3_voltage_read_reg(u16 mod, u8 offset) +{ + return omap2_prm_read_mod_reg(mod, offset); +} + +static void omap3_voltage_write_reg(u32 val, u16 mod, u8 offset) +{ + omap2_prm_write_mod_reg(val, mod, offset); +} + +static u32 omap4_voltage_read_reg(u16 mod, u8 offset) +{ + return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, + mod, offset); +} + +static void omap4_voltage_write_reg(u32 val, u16 mod, u8 offset) +{ + omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset); +} + +/* Voltage debugfs support */ +static int vp_volt_debug_get(void *data, u64 *val) +{ + struct omap_vdd_info *vdd = (struct omap_vdd_info *) data; + u8 vsel; + + if (!vdd) { + pr_warning("Wrong paramater passed\n"); + return -EINVAL; + } + + vsel = vdd->read_reg(vdd->vp_reg.prm_mod, vdd->vp_offs.voltage); + pr_notice("curr_vsel = %x\n", vsel); + + if (!vdd->pmic_info->vsel_to_uv) { + pr_warning("PMIC function to convert vsel to voltage" + "in uV not registerd\n"); + return -EINVAL; + } + + *val = vdd->pmic_info->vsel_to_uv(vsel); + return 0; +} + +static int nom_volt_debug_get(void *data, u64 *val) +{ + struct omap_vdd_info *vdd = (struct omap_vdd_info *) data; + + if (!vdd) { + pr_warning("Wrong paramater passed\n"); + return -EINVAL; + } + + *val = omap_voltage_get_nom_volt(&vdd->voltdm); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(vp_volt_debug_fops, vp_volt_debug_get, NULL, "%llu\n"); +DEFINE_SIMPLE_ATTRIBUTE(nom_volt_debug_fops, nom_volt_debug_get, NULL, + "%llu\n"); +static void vp_latch_vsel(struct omap_vdd_info *vdd) +{ + u32 vpconfig; + u16 mod; + unsigned long uvdc; + char vsel; + + uvdc = omap_voltage_get_nom_volt(&vdd->voltdm); + if (!uvdc) { + pr_warning("%s: unable to find current voltage for vdd_%s\n", + __func__, vdd->voltdm.name); + return; + } + + if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) { + pr_warning("%s: PMIC function to convert voltage in uV to" + " vsel not registered\n", __func__); + return; + } + + mod = vdd->vp_reg.prm_mod; + + vsel = vdd->pmic_info->uv_to_vsel(uvdc); + + vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); + vpconfig &= ~(vdd->vp_reg.vpconfig_initvoltage_mask | + vdd->vp_reg.vpconfig_initvdd); + vpconfig |= vsel << vdd->vp_reg.vpconfig_initvoltage_shift; + + vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); + + /* Trigger initVDD value copy to voltage processor */ + vdd->write_reg((vpconfig | vdd->vp_reg.vpconfig_initvdd), mod, + vdd->vp_offs.vpconfig); + + /* Clear initVDD copy trigger bit */ + vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); +} + +/* Generic voltage init functions */ +static void __init vp_init(struct omap_vdd_info *vdd) +{ + u32 vp_val; + u16 mod; + + if (!vdd->read_reg || !vdd->write_reg) { + pr_err("%s: No read/write API for accessing vdd_%s regs\n", + __func__, vdd->voltdm.name); + return; + } + + mod = vdd->vp_reg.prm_mod; + + vp_val = vdd->vp_reg.vpconfig_erroroffset | + (vdd->vp_reg.vpconfig_errorgain << + vdd->vp_reg.vpconfig_errorgain_shift) | + vdd->vp_reg.vpconfig_timeouten; + vdd->write_reg(vp_val, mod, vdd->vp_offs.vpconfig); + + vp_val = ((vdd->vp_reg.vstepmin_smpswaittimemin << + vdd->vp_reg.vstepmin_smpswaittimemin_shift) | + (vdd->vp_reg.vstepmin_stepmin << + vdd->vp_reg.vstepmin_stepmin_shift)); + vdd->write_reg(vp_val, mod, vdd->vp_offs.vstepmin); + + vp_val = ((vdd->vp_reg.vstepmax_smpswaittimemax << + vdd->vp_reg.vstepmax_smpswaittimemax_shift) | + (vdd->vp_reg.vstepmax_stepmax << + vdd->vp_reg.vstepmax_stepmax_shift)); + vdd->write_reg(vp_val, mod, vdd->vp_offs.vstepmax); + + vp_val = ((vdd->vp_reg.vlimitto_vddmax << + vdd->vp_reg.vlimitto_vddmax_shift) | + (vdd->vp_reg.vlimitto_vddmin << + vdd->vp_reg.vlimitto_vddmin_shift) | + (vdd->vp_reg.vlimitto_timeout << + vdd->vp_reg.vlimitto_timeout_shift)); + vdd->write_reg(vp_val, mod, vdd->vp_offs.vlimitto); +} + +static void __init vdd_debugfs_init(struct omap_vdd_info *vdd) +{ + char *name; + + name = kzalloc(VOLTAGE_DIR_SIZE, GFP_KERNEL); + if (!name) { + pr_warning("%s: Unable to allocate memory for debugfs" + " directory name for vdd_%s", + __func__, vdd->voltdm.name); + return; + } + strcpy(name, "vdd_"); + strcat(name, vdd->voltdm.name); + + vdd->debug_dir = debugfs_create_dir(name, voltage_dir); + if (IS_ERR(vdd->debug_dir)) { + pr_warning("%s: Unable to create debugfs directory for" + " vdd_%s\n", __func__, vdd->voltdm.name); + vdd->debug_dir = NULL; + return; + } + + (void) debugfs_create_x16("vp_errorgain", S_IRUGO, vdd->debug_dir, + &(vdd->vp_reg.vpconfig_errorgain)); + (void) debugfs_create_x16("vp_smpswaittimemin", S_IRUGO, + vdd->debug_dir, + &(vdd->vp_reg.vstepmin_smpswaittimemin)); + (void) debugfs_create_x8("vp_stepmin", S_IRUGO, vdd->debug_dir, + &(vdd->vp_reg.vstepmin_stepmin)); + (void) debugfs_create_x16("vp_smpswaittimemax", S_IRUGO, + vdd->debug_dir, + &(vdd->vp_reg.vstepmax_smpswaittimemax)); + (void) debugfs_create_x8("vp_stepmax", S_IRUGO, vdd->debug_dir, + &(vdd->vp_reg.vstepmax_stepmax)); + (void) debugfs_create_x8("vp_vddmax", S_IRUGO, vdd->debug_dir, + &(vdd->vp_reg.vlimitto_vddmax)); + (void) debugfs_create_x8("vp_vddmin", S_IRUGO, vdd->debug_dir, + &(vdd->vp_reg.vlimitto_vddmin)); + (void) debugfs_create_x16("vp_timeout", S_IRUGO, vdd->debug_dir, + &(vdd->vp_reg.vlimitto_timeout)); + (void) debugfs_create_file("curr_vp_volt", S_IRUGO, vdd->debug_dir, + (void *) vdd, &vp_volt_debug_fops); + (void) debugfs_create_file("curr_nominal_volt", S_IRUGO, + vdd->debug_dir, (void *) vdd, + &nom_volt_debug_fops); +} + +/* Voltage scale and accessory APIs */ +static int _pre_volt_scale(struct omap_vdd_info *vdd, + unsigned long target_volt, u8 *target_vsel, u8 *current_vsel) +{ + struct omap_volt_data *volt_data; + u32 vc_cmdval, vp_errgain_val; + u16 vp_mod, vc_mod; + + /* Check if suffiecient pmic info is available for this vdd */ + if (!vdd->pmic_info) { + pr_err("%s: Insufficient pmic info to scale the vdd_%s\n", + __func__, vdd->voltdm.name); + return -EINVAL; + } + + if (!vdd->pmic_info->uv_to_vsel) { + pr_err("%s: PMIC function to convert voltage in uV to" + "vsel not registered. Hence unable to scale voltage" + "for vdd_%s\n", __func__, vdd->voltdm.name); + return -ENODATA; + } + + if (!vdd->read_reg || !vdd->write_reg) { + pr_err("%s: No read/write API for accessing vdd_%s regs\n", + __func__, vdd->voltdm.name); + return -EINVAL; + } + + vp_mod = vdd->vp_reg.prm_mod; + vc_mod = vdd->vc_reg.prm_mod; + + /* Get volt_data corresponding to target_volt */ + volt_data = omap_voltage_get_voltdata(&vdd->voltdm, target_volt); + if (IS_ERR(volt_data)) + volt_data = NULL; + + *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt); + *current_vsel = vdd->read_reg(vp_mod, vdd->vp_offs.voltage); + + /* Setting the ON voltage to the new target voltage */ + vc_cmdval = vdd->read_reg(vc_mod, vdd->vc_reg.cmdval_reg); + vc_cmdval &= ~vdd->vc_reg.cmd_on_mask; + vc_cmdval |= (*target_vsel << vdd->vc_reg.cmd_on_shift); + vdd->write_reg(vc_cmdval, vc_mod, vdd->vc_reg.cmdval_reg); + + /* Setting vp errorgain based on the voltage */ + if (volt_data) { + vp_errgain_val = vdd->read_reg(vp_mod, + vdd->vp_offs.vpconfig); + vdd->vp_reg.vpconfig_errorgain = volt_data->vp_errgain; + vp_errgain_val &= ~vdd->vp_reg.vpconfig_errorgain_mask; + vp_errgain_val |= vdd->vp_reg.vpconfig_errorgain << + vdd->vp_reg.vpconfig_errorgain_shift; + vdd->write_reg(vp_errgain_val, vp_mod, + vdd->vp_offs.vpconfig); + } + + return 0; +} + +static void _post_volt_scale(struct omap_vdd_info *vdd, + unsigned long target_volt, u8 target_vsel, u8 current_vsel) +{ + u32 smps_steps = 0, smps_delay = 0; + + smps_steps = abs(target_vsel - current_vsel); + /* SMPS slew rate / step size. 2us added as buffer. */ + smps_delay = ((smps_steps * vdd->pmic_info->step_size) / + vdd->pmic_info->slew_rate) + 2; + udelay(smps_delay); + + vdd->curr_volt = target_volt; +} + +/* vc_bypass_scale_voltage - VC bypass method of voltage scaling */ +static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd, + unsigned long target_volt) +{ + u32 loop_cnt = 0, retries_cnt = 0; + u32 vc_valid, vc_bypass_val_reg, vc_bypass_value; + u16 mod; + u8 target_vsel, current_vsel; + int ret; + + ret = _pre_volt_scale(vdd, target_volt, &target_vsel, ¤t_vsel); + if (ret) + return ret; + + mod = vdd->vc_reg.prm_mod; + + vc_valid = vdd->vc_reg.valid; + vc_bypass_val_reg = vdd->vc_reg.bypass_val_reg; + vc_bypass_value = (target_vsel << vdd->vc_reg.data_shift) | + (vdd->pmic_info->pmic_reg << + vdd->vc_reg.regaddr_shift) | + (vdd->pmic_info->i2c_slave_addr << + vdd->vc_reg.slaveaddr_shift); + + vdd->write_reg(vc_bypass_value, mod, vc_bypass_val_reg); + vdd->write_reg(vc_bypass_value | vc_valid, mod, vc_bypass_val_reg); + + vc_bypass_value = vdd->read_reg(mod, vc_bypass_val_reg); + /* + * Loop till the bypass command is acknowledged from the SMPS. + * NOTE: This is legacy code. The loop count and retry count needs + * to be revisited. + */ + while (!(vc_bypass_value & vc_valid)) { + loop_cnt++; + + if (retries_cnt > 10) { + pr_warning("%s: Retry count exceeded\n", __func__); + return -ETIMEDOUT; + } + + if (loop_cnt > 50) { + retries_cnt++; + loop_cnt = 0; + udelay(10); + } + vc_bypass_value = vdd->read_reg(mod, vc_bypass_val_reg); + } + + _post_volt_scale(vdd, target_volt, target_vsel, current_vsel); + return 0; +} + +/* VP force update method of voltage scaling */ +static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd, + unsigned long target_volt) +{ + u32 vpconfig; + u16 mod, ocp_mod; + u8 target_vsel, current_vsel, prm_irqst_reg; + int ret, timeout = 0; + + ret = _pre_volt_scale(vdd, target_volt, &target_vsel, ¤t_vsel); + if (ret) + return ret; + + mod = vdd->vp_reg.prm_mod; + ocp_mod = vdd->ocp_mod; + prm_irqst_reg = vdd->prm_irqst_reg; + + /* + * Clear all pending TransactionDone interrupt/status. Typical latency + * is <3us + */ + while (timeout++ < VP_TRANXDONE_TIMEOUT) { + vdd->write_reg(vdd->vp_reg.tranxdone_status, + ocp_mod, prm_irqst_reg); + if (!(vdd->read_reg(ocp_mod, prm_irqst_reg) & + vdd->vp_reg.tranxdone_status)) + break; + udelay(1); + } + if (timeout >= VP_TRANXDONE_TIMEOUT) { + pr_warning("%s: vdd_%s TRANXDONE timeout exceeded." + "Voltage change aborted", __func__, vdd->voltdm.name); + return -ETIMEDOUT; + } + + /* Configure for VP-Force Update */ + vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); + vpconfig &= ~(vdd->vp_reg.vpconfig_initvdd | + vdd->vp_reg.vpconfig_forceupdate | + vdd->vp_reg.vpconfig_initvoltage_mask); + vpconfig |= ((target_vsel << + vdd->vp_reg.vpconfig_initvoltage_shift)); + vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); + + /* Trigger initVDD value copy to voltage processor */ + vpconfig |= vdd->vp_reg.vpconfig_initvdd; + vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); + + /* Force update of voltage */ + vpconfig |= vdd->vp_reg.vpconfig_forceupdate; + vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); + + /* + * Wait for TransactionDone. Typical latency is <200us. + * Depends on SMPSWAITTIMEMIN/MAX and voltage change + */ + timeout = 0; + omap_test_timeout((vdd->read_reg(ocp_mod, prm_irqst_reg) & + vdd->vp_reg.tranxdone_status), + VP_TRANXDONE_TIMEOUT, timeout); + if (timeout >= VP_TRANXDONE_TIMEOUT) + pr_err("%s: vdd_%s TRANXDONE timeout exceeded." + "TRANXDONE never got set after the voltage update\n", + __func__, vdd->voltdm.name); + + _post_volt_scale(vdd, target_volt, target_vsel, current_vsel); + + /* + * Disable TransactionDone interrupt , clear all status, clear + * control registers + */ + timeout = 0; + while (timeout++ < VP_TRANXDONE_TIMEOUT) { + vdd->write_reg(vdd->vp_reg.tranxdone_status, + ocp_mod, prm_irqst_reg); + if (!(vdd->read_reg(ocp_mod, prm_irqst_reg) & + vdd->vp_reg.tranxdone_status)) + break; + udelay(1); + } + + if (timeout >= VP_TRANXDONE_TIMEOUT) + pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying" + "to clear the TRANXDONE status\n", + __func__, vdd->voltdm.name); + + vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); + /* Clear initVDD copy trigger bit */ + vpconfig &= ~vdd->vp_reg.vpconfig_initvdd;; + vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); + /* Clear force bit */ + vpconfig &= ~vdd->vp_reg.vpconfig_forceupdate; + vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); + + return 0; +} + +/* OMAP3 specific voltage init functions */ + +/* + * Intializes the voltage controller registers with the PMIC and board + * specific parameters and voltage setup times for OMAP3. + */ +static void __init omap3_vc_init(struct omap_vdd_info *vdd) +{ + u32 vc_val; + u16 mod; + u8 on_vsel, onlp_vsel, ret_vsel, off_vsel; + static bool is_initialized; + + if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) { + pr_err("%s: PMIC info requried to configure vc for" + "vdd_%s not populated.Hence cannot initialize vc\n", + __func__, vdd->voltdm.name); + return; + } + + if (!vdd->read_reg || !vdd->write_reg) { + pr_err("%s: No read/write API for accessing vdd_%s regs\n", + __func__, vdd->voltdm.name); + return; + } + + mod = vdd->vc_reg.prm_mod; + + /* Set up the SMPS_SA(i2c slave address in VC */ + vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg); + vc_val &= ~vdd->vc_reg.smps_sa_mask; + vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_reg.smps_sa_shift; + vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg); + + /* Setup the VOLRA(pmic reg addr) in VC */ + vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_volra_reg); + vc_val &= ~vdd->vc_reg.smps_volra_mask; + vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_reg.smps_volra_shift; + vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg); + + /*Configure the setup times */ + vc_val = vdd->read_reg(mod, vdd->vc_reg.voltsetup_reg); + vc_val &= ~vdd->vc_reg.voltsetup_mask; + vc_val |= vdd->pmic_info->volt_setup_time << + vdd->vc_reg.voltsetup_shift; + vdd->write_reg(vc_val, mod, vdd->vc_reg.voltsetup_reg); + + /* Set up the on, inactive, retention and off voltage */ + on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt); + onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt); + ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt); + off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt); + vc_val = ((on_vsel << vdd->vc_reg.cmd_on_shift) | + (onlp_vsel << vdd->vc_reg.cmd_onlp_shift) | + (ret_vsel << vdd->vc_reg.cmd_ret_shift) | + (off_vsel << vdd->vc_reg.cmd_off_shift)); + vdd->write_reg(vc_val, mod, vdd->vc_reg.cmdval_reg); + + if (is_initialized) + return; + + /* Generic VC parameters init */ + vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, mod, + OMAP3_PRM_VC_CH_CONF_OFFSET); + vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, mod, + OMAP3_PRM_VC_I2C_CFG_OFFSET); + vdd->write_reg(OMAP3_CLKSETUP, mod, OMAP3_PRM_CLKSETUP_OFFSET); + vdd->write_reg(OMAP3_VOLTOFFSET, mod, OMAP3_PRM_VOLTOFFSET_OFFSET); + vdd->write_reg(OMAP3_VOLTSETUP2, mod, OMAP3_PRM_VOLTSETUP2_OFFSET); + is_initialized = true; +} + +/* Sets up all the VDD related info for OMAP3 */ +static int __init omap3_vdd_data_configure(struct omap_vdd_info *vdd) +{ + struct clk *sys_ck; + u32 sys_clk_speed, timeout_val, waittime; + + if (!vdd->pmic_info) { + pr_err("%s: PMIC info requried to configure vdd_%s not" + "populated.Hence cannot initialize vdd_%s\n", + __func__, vdd->voltdm.name, vdd->voltdm.name); + return -EINVAL; + } + + if (!strcmp(vdd->voltdm.name, "mpu")) { + if (cpu_is_omap3630()) + vdd->volt_data = omap36xx_vddmpu_volt_data; + else + vdd->volt_data = omap34xx_vddmpu_volt_data; + + vdd->vp_reg.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK; + vdd->vc_reg.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET; + vdd->vc_reg.smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT; + vdd->vc_reg.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK; + vdd->vc_reg.smps_volra_shift = OMAP3430_VOLRA0_SHIFT; + vdd->vc_reg.smps_volra_mask = OMAP3430_VOLRA0_MASK; + vdd->vc_reg.voltsetup_shift = OMAP3430_SETUP_TIME1_SHIFT; + vdd->vc_reg.voltsetup_mask = OMAP3430_SETUP_TIME1_MASK; + } else if (!strcmp(vdd->voltdm.name, "core")) { + if (cpu_is_omap3630()) + vdd->volt_data = omap36xx_vddcore_volt_data; + else + vdd->volt_data = omap34xx_vddcore_volt_data; + + vdd->vp_reg.tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK; + vdd->vc_reg.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET; + vdd->vc_reg.smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT; + vdd->vc_reg.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK; + vdd->vc_reg.smps_volra_shift = OMAP3430_VOLRA1_SHIFT; + vdd->vc_reg.smps_volra_mask = OMAP3430_VOLRA1_MASK; + vdd->vc_reg.voltsetup_shift = OMAP3430_SETUP_TIME2_SHIFT; + vdd->vc_reg.voltsetup_mask = OMAP3430_SETUP_TIME2_MASK; + } else { + pr_warning("%s: vdd_%s does not exisit in OMAP3\n", + __func__, vdd->voltdm.name); + return -EINVAL; + } + + /* + * Sys clk rate is require to calculate vp timeout value and + * smpswaittimemin and smpswaittimemax. + */ + sys_ck = clk_get(NULL, "sys_ck"); + if (IS_ERR(sys_ck)) { + pr_warning("%s: Could not get the sys clk to calculate" + "various vdd_%s params\n", __func__, vdd->voltdm.name); + return -EINVAL; + } + sys_clk_speed = clk_get_rate(sys_ck); + clk_put(sys_ck); + /* Divide to avoid overflow */ + sys_clk_speed /= 1000; + + /* Generic voltage parameters */ + vdd->curr_volt = 1200000; + vdd->ocp_mod = OCP_MOD; + vdd->prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET; + vdd->read_reg = omap3_voltage_read_reg; + vdd->write_reg = omap3_voltage_write_reg; + vdd->volt_scale = vp_forceupdate_scale_voltage; + vdd->vp_enabled = false; + + /* VC parameters */ + vdd->vc_reg.prm_mod = OMAP3430_GR_MOD; + vdd->vc_reg.smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET; + vdd->vc_reg.smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET; + vdd->vc_reg.bypass_val_reg = OMAP3_PRM_VC_BYPASS_VAL_OFFSET; + vdd->vc_reg.voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET; + vdd->vc_reg.data_shift = OMAP3430_DATA_SHIFT; + vdd->vc_reg.slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT; + vdd->vc_reg.regaddr_shift = OMAP3430_REGADDR_SHIFT; + vdd->vc_reg.valid = OMAP3430_VALID_MASK; + vdd->vc_reg.cmd_on_shift = OMAP3430_VC_CMD_ON_SHIFT; + vdd->vc_reg.cmd_on_mask = OMAP3430_VC_CMD_ON_MASK; + vdd->vc_reg.cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT; + vdd->vc_reg.cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT; + vdd->vc_reg.cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT; + + vdd->vp_reg.prm_mod = OMAP3430_GR_MOD; + + /* VPCONFIG bit fields */ + vdd->vp_reg.vpconfig_erroroffset = (vdd->pmic_info->vp_erroroffset << + OMAP3430_ERROROFFSET_SHIFT); + vdd->vp_reg.vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK; + vdd->vp_reg.vpconfig_errorgain_shift = OMAP3430_ERRORGAIN_SHIFT; + vdd->vp_reg.vpconfig_initvoltage_shift = OMAP3430_INITVOLTAGE_SHIFT; + vdd->vp_reg.vpconfig_initvoltage_mask = OMAP3430_INITVOLTAGE_MASK; + vdd->vp_reg.vpconfig_timeouten = OMAP3430_TIMEOUTEN_MASK; + vdd->vp_reg.vpconfig_initvdd = OMAP3430_INITVDD_MASK; + vdd->vp_reg.vpconfig_forceupdate = OMAP3430_FORCEUPDATE_MASK; + vdd->vp_reg.vpconfig_vpenable = OMAP3430_VPENABLE_MASK; + + /* VSTEPMIN VSTEPMAX bit fields */ + waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) * + sys_clk_speed) / 1000; + vdd->vp_reg.vstepmin_smpswaittimemin = waittime; + vdd->vp_reg.vstepmax_smpswaittimemax = waittime; + vdd->vp_reg.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin; + vdd->vp_reg.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax; + vdd->vp_reg.vstepmin_smpswaittimemin_shift = + OMAP3430_SMPSWAITTIMEMIN_SHIFT; + vdd->vp_reg.vstepmax_smpswaittimemax_shift = + OMAP3430_SMPSWAITTIMEMAX_SHIFT; + vdd->vp_reg.vstepmin_stepmin_shift = OMAP3430_VSTEPMIN_SHIFT; + vdd->vp_reg.vstepmax_stepmax_shift = OMAP3430_VSTEPMAX_SHIFT; + + /* VLIMITTO bit fields */ + timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000; + vdd->vp_reg.vlimitto_timeout = timeout_val; + vdd->vp_reg.vlimitto_vddmin = vdd->pmic_info->vp_vddmin; + vdd->vp_reg.vlimitto_vddmax = vdd->pmic_info->vp_vddmax; + vdd->vp_reg.vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT; + vdd->vp_reg.vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT; + vdd->vp_reg.vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT; + + return 0; +} + +/* OMAP4 specific voltage init functions */ +static void __init omap4_vc_init(struct omap_vdd_info *vdd) +{ + u32 vc_val; + u16 mod; + static bool is_initialized; + + if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) { + pr_err("%s: PMIC info requried to configure vc for" + "vdd_%s not populated.Hence cannot initialize vc\n", + __func__, vdd->voltdm.name); + return; + } + + if (!vdd->read_reg || !vdd->write_reg) { + pr_err("%s: No read/write API for accessing vdd_%s regs\n", + __func__, vdd->voltdm.name); + return; + } + + mod = vdd->vc_reg.prm_mod; + + /* Set up the SMPS_SA(i2c slave address in VC */ + vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg); + vc_val &= ~vdd->vc_reg.smps_sa_mask; + vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_reg.smps_sa_shift; + vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg); + + /* Setup the VOLRA(pmic reg addr) in VC */ + vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_volra_reg); + vc_val &= ~vdd->vc_reg.smps_volra_mask; + vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_reg.smps_volra_shift; + vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg); + + /* TODO: Configure setup times and CMD_VAL values*/ + + if (is_initialized) + return; + + /* Generic VC parameters init */ + vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK | + OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK | + OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK); + vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET); + + vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT); + vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET); + + is_initialized = true; +} + +/* Sets up all the VDD related info for OMAP4 */ +static int __init omap4_vdd_data_configure(struct omap_vdd_info *vdd) +{ + struct clk *sys_ck; + u32 sys_clk_speed, timeout_val, waittime; + + if (!vdd->pmic_info) { + pr_err("%s: PMIC info requried to configure vdd_%s not" + "populated.Hence cannot initialize vdd_%s\n", + __func__, vdd->voltdm.name, vdd->voltdm.name); + return -EINVAL; + } + + if (!strcmp(vdd->voltdm.name, "mpu")) { + vdd->volt_data = omap44xx_vdd_mpu_volt_data; + vdd->vp_reg.tranxdone_status = + OMAP4430_VP_MPU_TRANXDONE_ST_MASK; + vdd->vc_reg.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET; + vdd->vc_reg.smps_sa_shift = + OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT; + vdd->vc_reg.smps_sa_mask = + OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK; + vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_MPU_L_SHIFT; + vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK; + vdd->vc_reg.voltsetup_reg = + OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET; + vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET; + } else if (!strcmp(vdd->voltdm.name, "core")) { + vdd->volt_data = omap44xx_vdd_core_volt_data; + vdd->vp_reg.tranxdone_status = + OMAP4430_VP_CORE_TRANXDONE_ST_MASK; + vdd->vc_reg.cmdval_reg = + OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET; + vdd->vc_reg.smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT; + vdd->vc_reg.smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK; + vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT; + vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK; + vdd->vc_reg.voltsetup_reg = + OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET; + vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET; + } else if (!strcmp(vdd->voltdm.name, "iva")) { + vdd->volt_data = omap44xx_vdd_iva_volt_data; + vdd->vp_reg.tranxdone_status = + OMAP4430_VP_IVA_TRANXDONE_ST_MASK; + vdd->vc_reg.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET; + vdd->vc_reg.smps_sa_shift = + OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT; + vdd->vc_reg.smps_sa_mask = + OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK; + vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_IVA_L_SHIFT; + vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK; + vdd->vc_reg.voltsetup_reg = + OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET; + vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET; + } else { + pr_warning("%s: vdd_%s does not exisit in OMAP4\n", + __func__, vdd->voltdm.name); + return -EINVAL; + } + + /* + * Sys clk rate is require to calculate vp timeout value and + * smpswaittimemin and smpswaittimemax. + */ + sys_ck = clk_get(NULL, "sys_clkin_ck"); + if (IS_ERR(sys_ck)) { + pr_warning("%s: Could not get the sys clk to calculate" + "various vdd_%s params\n", __func__, vdd->voltdm.name); + return -EINVAL; + } + sys_clk_speed = clk_get_rate(sys_ck); + clk_put(sys_ck); + /* Divide to avoid overflow */ + sys_clk_speed /= 1000; + + /* Generic voltage parameters */ + vdd->curr_volt = 1200000; + vdd->ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST; + vdd->read_reg = omap4_voltage_read_reg; + vdd->write_reg = omap4_voltage_write_reg; + vdd->volt_scale = vp_forceupdate_scale_voltage; + vdd->vp_enabled = false; + + /* VC parameters */ + vdd->vc_reg.prm_mod = OMAP4430_PRM_DEVICE_INST; + vdd->vc_reg.smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET; + vdd->vc_reg.smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET; + vdd->vc_reg.bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET; + vdd->vc_reg.data_shift = OMAP4430_DATA_SHIFT; + vdd->vc_reg.slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT; + vdd->vc_reg.regaddr_shift = OMAP4430_REGADDR_SHIFT; + vdd->vc_reg.valid = OMAP4430_VALID_MASK; + vdd->vc_reg.cmd_on_shift = OMAP4430_ON_SHIFT; + vdd->vc_reg.cmd_on_mask = OMAP4430_ON_MASK; + vdd->vc_reg.cmd_onlp_shift = OMAP4430_ONLP_SHIFT; + vdd->vc_reg.cmd_ret_shift = OMAP4430_RET_SHIFT; + vdd->vc_reg.cmd_off_shift = OMAP4430_OFF_SHIFT; + + vdd->vp_reg.prm_mod = OMAP4430_PRM_DEVICE_INST; + + /* VPCONFIG bit fields */ + vdd->vp_reg.vpconfig_erroroffset = (vdd->pmic_info->vp_erroroffset << + OMAP4430_ERROROFFSET_SHIFT); + vdd->vp_reg.vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK; + vdd->vp_reg.vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT; + vdd->vp_reg.vpconfig_initvoltage_shift = OMAP4430_INITVOLTAGE_SHIFT; + vdd->vp_reg.vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK; + vdd->vp_reg.vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK; + vdd->vp_reg.vpconfig_initvdd = OMAP4430_INITVDD_MASK; + vdd->vp_reg.vpconfig_forceupdate = OMAP4430_FORCEUPDATE_MASK; + vdd->vp_reg.vpconfig_vpenable = OMAP4430_VPENABLE_MASK; + + /* VSTEPMIN VSTEPMAX bit fields */ + waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) * + sys_clk_speed) / 1000; + vdd->vp_reg.vstepmin_smpswaittimemin = waittime; + vdd->vp_reg.vstepmax_smpswaittimemax = waittime; + vdd->vp_reg.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin; + vdd->vp_reg.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax; + vdd->vp_reg.vstepmin_smpswaittimemin_shift = + OMAP4430_SMPSWAITTIMEMIN_SHIFT; + vdd->vp_reg.vstepmax_smpswaittimemax_shift = + OMAP4430_SMPSWAITTIMEMAX_SHIFT; + vdd->vp_reg.vstepmin_stepmin_shift = OMAP4430_VSTEPMIN_SHIFT; + vdd->vp_reg.vstepmax_stepmax_shift = OMAP4430_VSTEPMAX_SHIFT; + + /* VLIMITTO bit fields */ + timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000; + vdd->vp_reg.vlimitto_timeout = timeout_val; + vdd->vp_reg.vlimitto_vddmin = vdd->pmic_info->vp_vddmin; + vdd->vp_reg.vlimitto_vddmax = vdd->pmic_info->vp_vddmax; + vdd->vp_reg.vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT; + vdd->vp_reg.vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT; + vdd->vp_reg.vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT; + + return 0; +} + +/* Public functions */ +/** + * omap_voltage_get_nom_volt() - Gets the current non-auto-compensated voltage + * @voltdm: pointer to the VDD for which current voltage info is needed + * + * API to get the current non-auto-compensated voltage for a VDD. + * Returns 0 in case of error else returns the current voltage for the VDD. + */ +unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm) +{ + struct omap_vdd_info *vdd; + + if (!voltdm || IS_ERR(voltdm)) { + pr_warning("%s: VDD specified does not exist!\n", __func__); + return 0; + } + + vdd = container_of(voltdm, struct omap_vdd_info, voltdm); + + return vdd->curr_volt; +} + +/** + * omap_vp_get_curr_volt() - API to get the current vp voltage. + * @voltdm: pointer to the VDD. + * + * This API returns the current voltage for the specified voltage processor + */ +unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm) +{ + struct omap_vdd_info *vdd; + u8 curr_vsel; + + if (!voltdm || IS_ERR(voltdm)) { + pr_warning("%s: VDD specified does not exist!\n", __func__); + return 0; + } + + vdd = container_of(voltdm, struct omap_vdd_info, voltdm); + if (!vdd->read_reg) { + pr_err("%s: No read API for reading vdd_%s regs\n", + __func__, voltdm->name); + return 0; + } + + curr_vsel = vdd->read_reg(vdd->vp_reg.prm_mod, + vdd->vp_offs.voltage); + + if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) { + pr_warning("%s: PMIC function to convert vsel to voltage" + "in uV not registerd\n", __func__); + return 0; + } + + return vdd->pmic_info->vsel_to_uv(curr_vsel); +} + +/** + * omap_vp_enable() - API to enable a particular VP + * @voltdm: pointer to the VDD whose VP is to be enabled. + * + * This API enables a particular voltage processor. Needed by the smartreflex + * class drivers. + */ +void omap_vp_enable(struct voltagedomain *voltdm) +{ + struct omap_vdd_info *vdd; + u32 vpconfig; + u16 mod; + + if (!voltdm || IS_ERR(voltdm)) { + pr_warning("%s: VDD specified does not exist!\n", __func__); + return; + } + + vdd = container_of(voltdm, struct omap_vdd_info, voltdm); + if (!vdd->read_reg || !vdd->write_reg) { + pr_err("%s: No read/write API for accessing vdd_%s regs\n", + __func__, voltdm->name); + return; + } + + mod = vdd->vp_reg.prm_mod; + + /* If VP is already enabled, do nothing. Return */ + if (vdd->vp_enabled) + return; + + vp_latch_vsel(vdd); + + /* Enable VP */ + vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); + vpconfig |= vdd->vp_reg.vpconfig_vpenable; + vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); + vdd->vp_enabled = true; +} + +/** + * omap_vp_disable() - API to disable a particular VP + * @voltdm: pointer to the VDD whose VP is to be disabled. + * + * This API disables a particular voltage processor. Needed by the smartreflex + * class drivers. + */ +void omap_vp_disable(struct voltagedomain *voltdm) +{ + struct omap_vdd_info *vdd; + u32 vpconfig; + u16 mod; + int timeout; + + if (!voltdm || IS_ERR(voltdm)) { + pr_warning("%s: VDD specified does not exist!\n", __func__); + return; + } + + vdd = container_of(voltdm, struct omap_vdd_info, voltdm); + if (!vdd->read_reg || !vdd->write_reg) { + pr_err("%s: No read/write API for accessing vdd_%s regs\n", + __func__, voltdm->name); + return; + } + + mod = vdd->vp_reg.prm_mod; + + /* If VP is already disabled, do nothing. Return */ + if (!vdd->vp_enabled) { + pr_warning("%s: Trying to disable VP for vdd_%s when" + "it is already disabled\n", __func__, voltdm->name); + return; + } + + /* Disable VP */ + vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); + vpconfig &= ~vdd->vp_reg.vpconfig_vpenable; + vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); + + /* + * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us + */ + omap_test_timeout((vdd->read_reg(mod, vdd->vp_offs.vstatus)), + VP_IDLE_TIMEOUT, timeout); + + if (timeout >= VP_IDLE_TIMEOUT) + pr_warning("%s: vdd_%s idle timedout\n", + __func__, voltdm->name); + + vdd->vp_enabled = false; + + return; +} + +/** + * omap_voltage_scale_vdd() - API to scale voltage of a particular + * voltage domain. + * @voltdm: pointer to the VDD which is to be scaled. + * @target_volt: The target voltage of the voltage domain + * + * This API should be called by the kernel to do the voltage scaling + * for a particular voltage domain during dvfs or any other situation. + */ +int omap_voltage_scale_vdd(struct voltagedomain *voltdm, + unsigned long target_volt) +{ + struct omap_vdd_info *vdd; + + if (!voltdm || IS_ERR(voltdm)) { + pr_warning("%s: VDD specified does not exist!\n", __func__); + return -EINVAL; + } + + vdd = container_of(voltdm, struct omap_vdd_info, voltdm); + + if (!vdd->volt_scale) { + pr_err("%s: No voltage scale API registered for vdd_%s\n", + __func__, voltdm->name); + return -ENODATA; + } + + return vdd->volt_scale(vdd, target_volt); +} + +/** + * omap_voltage_reset() - Resets the voltage of a particular voltage domain + * to that of the current OPP. + * @voltdm: pointer to the VDD whose voltage is to be reset. + * + * This API finds out the correct voltage the voltage domain is supposed + * to be at and resets the voltage to that level. Should be used expecially + * while disabling any voltage compensation modules. + */ +void omap_voltage_reset(struct voltagedomain *voltdm) +{ + unsigned long target_uvdc; + + if (!voltdm || IS_ERR(voltdm)) { + pr_warning("%s: VDD specified does not exist!\n", __func__); + return; + } + + target_uvdc = omap_voltage_get_nom_volt(voltdm); + if (!target_uvdc) { + pr_err("%s: unable to find current voltage for vdd_%s\n", + __func__, voltdm->name); + return; + } + + omap_voltage_scale_vdd(voltdm, target_uvdc); +} + +/** + * omap_voltage_get_volttable() - API to get the voltage table associated with a + * particular voltage domain. + * @voltdm: pointer to the VDD for which the voltage table is required + * @volt_data: the voltage table for the particular vdd which is to be + * populated by this API + * + * This API populates the voltage table associated with a VDD into the + * passed parameter pointer. Returns the count of distinct voltages + * supported by this vdd. + * + */ +void omap_voltage_get_volttable(struct voltagedomain *voltdm, + struct omap_volt_data **volt_data) +{ + struct omap_vdd_info *vdd; + + if (!voltdm || IS_ERR(voltdm)) { + pr_warning("%s: VDD specified does not exist!\n", __func__); + return; + } + + vdd = container_of(voltdm, struct omap_vdd_info, voltdm); + + *volt_data = vdd->volt_data; +} + +/** + * omap_voltage_get_voltdata() - API to get the voltage table entry for a + * particular voltage + * @voltdm: pointer to the VDD whose voltage table has to be searched + * @volt: the voltage to be searched in the voltage table + * + * This API searches through the voltage table for the required voltage + * domain and tries to find a matching entry for the passed voltage volt. + * If a matching entry is found volt_data is populated with that entry. + * This API searches only through the non-compensated voltages int the + * voltage table. + * Returns pointer to the voltage table entry corresponding to volt on + * sucess. Returns -ENODATA if no voltage table exisits for the passed voltage + * domain or if there is no matching entry. + */ +struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, + unsigned long volt) +{ + struct omap_vdd_info *vdd; + int i; + + if (!voltdm || IS_ERR(voltdm)) { + pr_warning("%s: VDD specified does not exist!\n", __func__); + return ERR_PTR(-EINVAL); + } + + vdd = container_of(voltdm, struct omap_vdd_info, voltdm); + + if (!vdd->volt_data) { + pr_warning("%s: voltage table does not exist for vdd_%s\n", + __func__, voltdm->name); + return ERR_PTR(-ENODATA); + } + + for (i = 0; vdd->volt_data[i].volt_nominal != 0; i++) { + if (vdd->volt_data[i].volt_nominal == volt) + return &vdd->volt_data[i]; + } + + pr_notice("%s: Unable to match the current voltage with the voltage" + "table for vdd_%s\n", __func__, voltdm->name); + + return ERR_PTR(-ENODATA); +} + +/** + * omap_voltage_register_pmic() - API to register PMIC specific data + * @voltdm: pointer to the VDD for which the PMIC specific data is + * to be registered + * @pmic_info: the structure containing pmic info + * + * This API is to be called by the SOC/PMIC file to specify the + * pmic specific info as present in omap_volt_pmic_info structure. + */ +int omap_voltage_register_pmic(struct voltagedomain *voltdm, + struct omap_volt_pmic_info *pmic_info) +{ + struct omap_vdd_info *vdd; + + if (!voltdm || IS_ERR(voltdm)) { + pr_warning("%s: VDD specified does not exist!\n", __func__); + return -EINVAL; + } + + vdd = container_of(voltdm, struct omap_vdd_info, voltdm); + + vdd->pmic_info = pmic_info; + + return 0; +} + +/** + * omap_voltage_get_dbgdir() - API to get pointer to the debugfs directory + * corresponding to a voltage domain. + * + * @voltdm: pointer to the VDD whose debug directory is required. + * + * This API returns pointer to the debugfs directory corresponding + * to the voltage domain. Should be used by drivers requiring to + * add any debug entry for a particular voltage domain. Returns NULL + * in case of error. + */ +struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm) +{ + struct omap_vdd_info *vdd; + + if (!voltdm || IS_ERR(voltdm)) { + pr_warning("%s: VDD specified does not exist!\n", __func__); + return NULL; + } + + vdd = container_of(voltdm, struct omap_vdd_info, voltdm); + + return vdd->debug_dir; +} + +/** + * omap_change_voltscale_method() - API to change the voltage scaling method. + * @voltdm: pointer to the VDD whose voltage scaling method + * has to be changed. + * @voltscale_method: the method to be used for voltage scaling. + * + * This API can be used by the board files to change the method of voltage + * scaling between vpforceupdate and vcbypass. The parameter values are + * defined in voltage.h + */ +void omap_change_voltscale_method(struct voltagedomain *voltdm, + int voltscale_method) +{ + struct omap_vdd_info *vdd; + + if (!voltdm || IS_ERR(voltdm)) { + pr_warning("%s: VDD specified does not exist!\n", __func__); + return; + } + + vdd = container_of(voltdm, struct omap_vdd_info, voltdm); + + switch (voltscale_method) { + case VOLTSCALE_VPFORCEUPDATE: + vdd->volt_scale = vp_forceupdate_scale_voltage; + return; + case VOLTSCALE_VCBYPASS: + vdd->volt_scale = vc_bypass_scale_voltage; + return; + default: + pr_warning("%s: Trying to change the method of voltage scaling" + "to an unsupported one!\n", __func__); + } +} + +/** + * omap_voltage_domain_lookup() - API to get the voltage domain pointer + * @name: Name of the voltage domain + * + * This API looks up in the global vdd_info struct for the + * existence of voltage domain <name>. If it exists, the API returns + * a pointer to the voltage domain structure corresponding to the + * VDD<name>. Else retuns error pointer. + */ +struct voltagedomain *omap_voltage_domain_lookup(char *name) +{ + int i; + + if (!vdd_info) { + pr_err("%s: Voltage driver init not yet happened.Faulting!\n", + __func__); + return ERR_PTR(-EINVAL); + } + + if (!name) { + pr_err("%s: No name to get the votage domain!\n", __func__); + return ERR_PTR(-EINVAL); + } + + for (i = 0; i < nr_scalable_vdd; i++) { + if (!(strcmp(name, vdd_info[i].voltdm.name))) + return &vdd_info[i].voltdm; + } + + return ERR_PTR(-EINVAL); +} + +/** + * omap_voltage_late_init() - Init the various voltage parameters + * + * This API is to be called in the later stages of the + * system boot to init the voltage controller and + * voltage processors. + */ +int __init omap_voltage_late_init(void) +{ + int i; + + if (!vdd_info) { + pr_err("%s: Voltage driver support not added\n", + __func__); + return -EINVAL; + } + + voltage_dir = debugfs_create_dir("voltage", NULL); + if (IS_ERR(voltage_dir)) + pr_err("%s: Unable to create voltage debugfs main dir\n", + __func__); + for (i = 0; i < nr_scalable_vdd; i++) { + if (vdd_data_configure(&vdd_info[i])) + continue; + vc_init(&vdd_info[i]); + vp_init(&vdd_info[i]); + vdd_debugfs_init(&vdd_info[i]); + } + + return 0; +} + +/** + * omap_voltage_early_init()- Volatage driver early init + */ +static int __init omap_voltage_early_init(void) +{ + if (cpu_is_omap34xx()) { + vdd_info = omap3_vdd_info; + nr_scalable_vdd = OMAP3_NR_SCALABLE_VDD; + vc_init = omap3_vc_init; + vdd_data_configure = omap3_vdd_data_configure; + } else if (cpu_is_omap44xx()) { + vdd_info = omap4_vdd_info; + nr_scalable_vdd = OMAP4_NR_SCALABLE_VDD; + vc_init = omap4_vc_init; + vdd_data_configure = omap4_vdd_data_configure; + } else { + pr_warning("%s: voltage driver support not added\n", __func__); + } + + return 0; +} +core_initcall(omap_voltage_early_init); diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c new file mode 100644 index 000000000000..b0c4907ab3ca --- /dev/null +++ b/arch/arm/mach-omap2/wd_timer.c @@ -0,0 +1,54 @@ +/* + * OMAP2+ MPU WD_TIMER-specific code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/err.h> + +#include <plat/omap_hwmod.h> + +/* + * In order to avoid any assumptions from bootloader regarding WDT + * settings, WDT module is reset during init. This enables the watchdog + * timer. Hence it is required to disable the watchdog after the WDT reset + * during init. Otherwise the system would reboot as per the default + * watchdog timer registers settings. + */ +#define OMAP_WDT_WPS 0x34 +#define OMAP_WDT_SPR 0x48 + + +int omap2_wd_timer_disable(struct omap_hwmod *oh) +{ + void __iomem *base; + + if (!oh) { + pr_err("%s: Could not look up wdtimer_hwmod\n", __func__); + return -EINVAL; + } + + base = omap_hwmod_get_mpu_rt_va(oh); + if (!base) { + pr_err("%s: Could not get the base address for %s\n", + oh->name, __func__); + return -EINVAL; + } + + /* sequence required to disable watchdog */ + __raw_writel(0xAAAA, base + OMAP_WDT_SPR); + while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) + cpu_relax(); + + __raw_writel(0x5555, base + OMAP_WDT_SPR); + while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) + cpu_relax(); + + return 0; +} + diff --git a/arch/arm/mach-omap2/wd_timer.h b/arch/arm/mach-omap2/wd_timer.h new file mode 100644 index 000000000000..e0054a2d5505 --- /dev/null +++ b/arch/arm/mach-omap2/wd_timer.h @@ -0,0 +1,17 @@ +/* + * OMAP2+ MPU WD_TIMER-specific function prototypes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_WD_TIMER_H +#define __ARCH_ARM_MACH_OMAP2_WD_TIMER_H + +#include <plat/omap_hwmod.h> + +extern int omap2_wd_timer_disable(struct omap_hwmod *oh); + +#endif |
