diff options
Diffstat (limited to 'arch/arm/mach-omap2')
42 files changed, 469 insertions, 6783 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index dc21df166161..653b489479e0 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -76,6 +76,16 @@ config SOC_AM43XX select ARM_GIC select MACH_OMAP_GENERIC +config SOC_DRA7XX + bool "TI DRA7XX" + depends on ARCH_MULTI_V7 + select ARCH_OMAP2PLUS + select ARM_CPU_SUSPEND if PM + select ARM_GIC + select CPU_V7 + select HAVE_SMP + select HAVE_ARM_ARCH_TIMER + config ARCH_OMAP2PLUS bool select ARCH_HAS_BANDGAP @@ -128,14 +138,6 @@ config SOC_HAS_REALTIME_COUNTER depends on SOC_OMAP5 || SOC_DRA7XX default y -config SOC_DRA7XX - bool "TI DRA7XX" - select ARM_ARCH_TIMER - select CPU_V7 - select ARM_GIC - select HAVE_SMP - select COMMON_CLK - comment "OMAP Core Type" depends on ARCH_OMAP2 @@ -192,19 +194,6 @@ config MACH_OMAP2_TUSB6010 depends on ARCH_OMAP2 && SOC_OMAP2420 default y if MACH_NOKIA_N8X0 -config MACH_OMAP_H4 - bool "OMAP 2420 H4 board" - depends on SOC_OMAP2420 - default y - select OMAP_DEBUG_DEVICES - select OMAP_PACKAGE_ZAF - -config MACH_OMAP_2430SDP - bool "OMAP 2430 SDP board" - depends on SOC_OMAP2430 - default y - select OMAP_PACKAGE_ZAC - config MACH_OMAP3_BEAGLE bool "OMAP3 BEAGLE board" depends on ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index adcef406ff0a..e6eec6f72fd3 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -66,8 +66,6 @@ obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o # Pin multiplexing -obj-$(CONFIG_SOC_OMAP2420) += mux2420.o -obj-$(CONFIG_SOC_OMAP2430) += mux2430.o obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o # SMS/SDRC @@ -132,6 +130,7 @@ obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) obj-$(CONFIG_SOC_AM43XX) += $(voltagedomain-common) obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o +obj-$(CONFIG_SOC_DRA7XX) += $(voltagedomain-common) # OMAP powerdomain framework powerdomain-common += powerdomain.o powerdomain-common.o @@ -186,12 +185,14 @@ obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o -obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) cclock44xx_data.o +obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o -obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o obj-$(CONFIG_SOC_OMAP5) += $(clock-common) obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o +obj-$(CONFIG_SOC_DRA7XX) += $(clock-common) +obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o +obj-$(CONFIG_SOC_AM43XX) += $(clock-common) dpll3xxx.o # OMAP2 clock rate set data (old "OPP" data) obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o @@ -237,8 +238,6 @@ obj-$(CONFIG_SOC_OMAP2420) += msdi.o # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o -obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o -obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c deleted file mode 100644 index c711ad6ac067..000000000000 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/board-2430sdp.c - * - * Copyright (C) 2006 Texas Instruments - * - * Modified from mach-omap2/board-generic.c - * - * Initial Code : Based on a patch from Komal Shah and Richard Woodruff - * Updated the Code for 2430 SDP : Syed Mohammed Khasim - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/mmc/host.h> -#include <linux/delay.h> -#include <linux/i2c/twl.h> -#include <linux/regulator/machine.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/usb/phy.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "gpmc.h" -#include "gpmc-smc91x.h" - -#include <video/omapdss.h> -#include <video/omap-panel-data.h> - -#include "mux.h" -#include "hsmmc.h" -#include "common-board-devices.h" - -#define SDP2430_CS0_BASE 0x04000000 -#define SECONDARY_LCD_GPIO 147 - -static struct mtd_partition sdp2430_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - { - .name = "bootloader", - .offset = 0, - .size = SZ_256K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0, - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0 - }, - /* file system */ - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - } -}; - -static struct physmap_flash_data sdp2430_flash_data = { - .width = 2, - .parts = sdp2430_partitions, - .nr_parts = ARRAY_SIZE(sdp2430_partitions), -}; - -static struct resource sdp2430_flash_resource = { - .start = SDP2430_CS0_BASE, - .end = SDP2430_CS0_BASE + SZ_64M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device sdp2430_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &sdp2430_flash_data, - }, - .num_resources = 1, - .resource = &sdp2430_flash_resource, -}; - -/* LCD */ -#define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91 -#define SDP2430_LCD_PANEL_ENABLE_GPIO 154 - -static const struct display_timing sdp2430_lcd_videomode = { - .pixelclock = { 0, 5400000, 0 }, - - .hactive = { 0, 240, 0 }, - .hfront_porch = { 0, 3, 0 }, - .hback_porch = { 0, 39, 0 }, - .hsync_len = { 0, 3, 0 }, - - .vactive = { 0, 320, 0 }, - .vfront_porch = { 0, 2, 0 }, - .vback_porch = { 0, 7, 0 }, - .vsync_len = { 0, 1, 0 }, - - .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | - DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, -}; - -static struct panel_dpi_platform_data sdp2430_lcd_pdata = { - .name = "lcd", - .source = "dpi.0", - - .data_lines = 16, - - .display_timing = &sdp2430_lcd_videomode, - - .enable_gpio = SDP2430_LCD_PANEL_ENABLE_GPIO, - .backlight_gpio = SDP2430_LCD_PANEL_BACKLIGHT_GPIO, -}; - -static struct platform_device sdp2430_lcd_device = { - .name = "panel-dpi", - .id = 0, - .dev.platform_data = &sdp2430_lcd_pdata, -}; - -static struct omap_dss_board_info sdp2430_dss_data = { - .default_display_name = "lcd", -}; - -static struct platform_device *sdp2430_devices[] __initdata = { - &sdp2430_flash_device, - &sdp2430_lcd_device, -}; - -#if IS_ENABLED(CONFIG_SMC91X) - -static struct omap_smc91x_platform_data board_smc91x_data = { - .cs = 5, - .gpio_irq = 149, - .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 | - IORESOURCE_IRQ_LOWLEVEL, - -}; - -static void __init board_smc91x_init(void) -{ - omap_mux_init_gpio(149, OMAP_PIN_INPUT); - gpmc_smc91x_init(&board_smc91x_data); -} - -#else - -static inline void board_smc91x_init(void) -{ -} - -#endif - -static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = { - REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), -}; - -/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ -static struct regulator_init_data sdp2430_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(sdp2430_vmmc1_supplies), - .consumer_supplies = &sdp2430_vmmc1_supplies[0], -}; - -static struct twl4030_gpio_platform_data sdp2430_gpio_data = { -}; - -static struct twl4030_platform_data sdp2430_twldata = { - /* platform_data for children goes here */ - .gpio = &sdp2430_gpio_data, - .vmmc1 = &sdp2430_vmmc1, -}; - -static struct i2c_board_info __initdata sdp2430_i2c1_boardinfo[] = { - { - I2C_BOARD_INFO("isp1301_omap", 0x2D), - .flags = I2C_CLIENT_WAKE, - }, -}; - -static int __init omap2430_i2c_init(void) -{ - sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78); - omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo, - ARRAY_SIZE(sdp2430_i2c1_boardinfo)); - omap_pmic_init(2, 100, "twl4030", 7 + OMAP_INTC_START, - &sdp2430_twldata); - return 0; -} - -static struct omap2_hsmmc_info mmc[] __initdata = { - { - .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - .ext_clock = 1, - }, - {} /* Terminator */ -}; - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#endif - -static void __init omap_2430sdp_init(void) -{ - omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC); - - omap2430_i2c_init(); - - platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); - omap_serial_init(); - omap_sdrc_init(NULL, NULL); - omap_hsmmc_init(mmc); - - omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP); - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); - usb_musb_init(NULL); - - board_smc91x_init(); - - /* Turn off secondary LCD backlight */ - gpio_request_one(SECONDARY_LCD_GPIO, GPIOF_OUT_INIT_LOW, - "Secondary LCD backlight"); - - omap_display_init(&sdp2430_dss_data); -} - -MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") - /* Maintainer: Syed Khasim - Texas Instruments Inc */ - .atag_offset = 0x100, - .reserve = omap_reserve, - .map_io = omap243x_map_io, - .init_early = omap2430_init_early, - .init_irq = omap2_init_irq, - .handle_irq = omap2_intc_handle_irq, - .init_machine = omap_2430sdp_init, - .init_late = omap2430_init_late, - .init_time = omap2_sync32k_timer_init, - .restart = omap2xxx_restart, -MACHINE_END diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 8d972ff18c56..8e3daa11602b 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -78,6 +78,7 @@ MACHINE_END #ifdef CONFIG_ARCH_OMAP3 static const char *omap3_boards_compat[] __initdata = { + "ti,omap3430", "ti,omap3", NULL, }; @@ -173,6 +174,8 @@ MACHINE_END #ifdef CONFIG_ARCH_OMAP4 static const char *omap4_boards_compat[] __initdata = { + "ti,omap4460", + "ti,omap4430", "ti,omap4", NULL, }; @@ -193,6 +196,8 @@ MACHINE_END #ifdef CONFIG_SOC_OMAP5 static const char *omap5_boards_compat[] __initdata = { + "ti,omap5432", + "ti,omap5430", "ti,omap5", NULL, }; @@ -213,6 +218,7 @@ MACHINE_END #ifdef CONFIG_SOC_AM43XX static const char *am43_boards_compat[] __initdata = { + "ti,am4372", "ti,am43", NULL, }; @@ -230,6 +236,7 @@ MACHINE_END #ifdef CONFIG_SOC_DRA7XX static const char *dra7xx_boards_compat[] __initdata = { + "ti,dra7xx", "ti,dra7", NULL, }; diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c deleted file mode 100644 index f7808349a734..000000000000 --- a/arch/arm/mach-omap2/board-h4.c +++ /dev/null @@ -1,365 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/board-h4.c - * - * Copyright (C) 2005 Nokia Corporation - * Author: Paul Mundt <paul.mundt@nokia.com> - * - * Modified from mach-omap/omap1/board-generic.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/delay.h> -#include <linux/workqueue.h> -#include <linux/i2c.h> -#include <linux/platform_data/at24.h> -#include <linux/input.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/input/matrix_keypad.h> -#include <linux/mfd/menelaus.h> -#include <linux/omap-dma.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include <video/omapdss.h> -#include <video/omap-panel-data.h> - -#include "common.h" -#include "mux.h" -#include "control.h" -#include "gpmc.h" -#include "gpmc-smc91x.h" - -#define H4_FLASH_CS 0 - -#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE) -static const uint32_t board_matrix_keys[] = { - KEY(0, 0, KEY_LEFT), - KEY(1, 0, KEY_RIGHT), - KEY(2, 0, KEY_A), - KEY(3, 0, KEY_B), - KEY(4, 0, KEY_C), - KEY(0, 1, KEY_DOWN), - KEY(1, 1, KEY_UP), - KEY(2, 1, KEY_E), - KEY(3, 1, KEY_F), - KEY(4, 1, KEY_G), - KEY(0, 2, KEY_ENTER), - KEY(1, 2, KEY_I), - KEY(2, 2, KEY_J), - KEY(3, 2, KEY_K), - KEY(4, 2, KEY_3), - KEY(0, 3, KEY_M), - KEY(1, 3, KEY_N), - KEY(2, 3, KEY_O), - KEY(3, 3, KEY_P), - KEY(4, 3, KEY_Q), - KEY(0, 4, KEY_R), - KEY(1, 4, KEY_4), - KEY(2, 4, KEY_T), - KEY(3, 4, KEY_U), - KEY(4, 4, KEY_ENTER), - KEY(0, 5, KEY_V), - KEY(1, 5, KEY_W), - KEY(2, 5, KEY_L), - KEY(3, 5, KEY_S), - KEY(4, 5, KEY_ENTER), -}; - -static const struct matrix_keymap_data board_keymap_data = { - .keymap = board_matrix_keys, - .keymap_size = ARRAY_SIZE(board_matrix_keys), -}; - -static unsigned int board_keypad_row_gpios[] = { - 88, 89, 124, 11, 6, 96 -}; - -static unsigned int board_keypad_col_gpios[] = { - 90, 91, 100, 36, 12, 97, 98 -}; - -static struct matrix_keypad_platform_data board_keypad_platform_data = { - .keymap_data = &board_keymap_data, - .row_gpios = board_keypad_row_gpios, - .num_row_gpios = ARRAY_SIZE(board_keypad_row_gpios), - .col_gpios = board_keypad_col_gpios, - .num_col_gpios = ARRAY_SIZE(board_keypad_col_gpios), - .active_low = 1, - - .debounce_ms = 20, - .col_scan_delay_us = 5, -}; - -static struct platform_device board_keyboard = { - .name = "matrix-keypad", - .id = -1, - .dev = { - .platform_data = &board_keypad_platform_data, - }, -}; -static void __init board_mkp_init(void) -{ - omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP); - omap_mux_init_gpio(89, OMAP_PULL_ENA | OMAP_PULL_UP); - omap_mux_init_gpio(124, OMAP_PULL_ENA | OMAP_PULL_UP); - omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP); - if (omap_has_menelaus()) { - omap_mux_init_signal("sdrc_a14.gpio0", - OMAP_PULL_ENA | OMAP_PULL_UP); - omap_mux_init_signal("vlynq_rx0.gpio_15", 0); - omap_mux_init_signal("gpio_98", 0); - board_keypad_row_gpios[5] = 0; - board_keypad_col_gpios[2] = 15; - board_keypad_col_gpios[6] = 18; - } else { - omap_mux_init_signal("gpio_96", OMAP_PULL_ENA | OMAP_PULL_UP); - omap_mux_init_signal("gpio_100", 0); - omap_mux_init_signal("gpio_98", 0); - } - omap_mux_init_signal("gpio_90", 0); - omap_mux_init_signal("gpio_91", 0); - omap_mux_init_signal("gpio_36", 0); - omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0); - omap_mux_init_signal("gpio_97", 0); - - platform_device_register(&board_keyboard); -} -#else -static inline void board_mkp_init(void) -{ -} -#endif - -static struct mtd_partition h4_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - { - .name = "bootloader", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0, - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0 - }, - /* file system */ - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - } -}; - -static struct physmap_flash_data h4_flash_data = { - .width = 2, - .parts = h4_partitions, - .nr_parts = ARRAY_SIZE(h4_partitions), -}; - -static struct resource h4_flash_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device h4_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &h4_flash_data, - }, - .num_resources = 1, - .resource = &h4_flash_resource, -}; - -static const struct display_timing cm_t35_lcd_videomode = { - .pixelclock = { 0, 6250000, 0 }, - - .hactive = { 0, 240, 0 }, - .hfront_porch = { 0, 15, 0 }, - .hback_porch = { 0, 60, 0 }, - .hsync_len = { 0, 15, 0 }, - - .vactive = { 0, 320, 0 }, - .vfront_porch = { 0, 1, 0 }, - .vback_porch = { 0, 1, 0 }, - .vsync_len = { 0, 1, 0 }, - - .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | - DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, -}; - -static struct panel_dpi_platform_data cm_t35_lcd_pdata = { - .name = "lcd", - .source = "dpi.0", - - .data_lines = 16, - - .display_timing = &cm_t35_lcd_videomode, - - .enable_gpio = -1, - .backlight_gpio = -1, -}; - -static struct platform_device cm_t35_lcd_device = { - .name = "panel-dpi", - .id = 0, - .dev.platform_data = &cm_t35_lcd_pdata, -}; - -static struct platform_device *h4_devices[] __initdata = { - &h4_flash_device, - &cm_t35_lcd_device, -}; - -static struct omap_dss_board_info h4_dss_data = { - .default_display_name = "lcd", -}; - -/* 2420 Sysboot setup (2430 is different) */ -static u32 get_sysboot_value(void) -{ - return (omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) & - (OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK | - OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK | - OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK)); -} - -/* H4-2420's always used muxed mode, H4-2422's always use non-muxed - * - * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423 - * correctly. The macro needs to look at production_id not just hawkeye. - */ -static u32 is_gpmc_muxed(void) -{ - u32 mux; - mux = get_sysboot_value(); - if ((mux & 0xF) == 0xd) - return 1; /* NAND config (could be either) */ - if (mux & 0x2) /* if mux'ed */ - return 1; - else - return 0; -} - -#if IS_ENABLED(CONFIG_SMC91X) - -static struct omap_smc91x_platform_data board_smc91x_data = { - .cs = 1, - .gpio_irq = 92, - .flags = GPMC_TIMINGS_SMC91C96 | IORESOURCE_IRQ_LOWLEVEL, -}; - -static void __init board_smc91x_init(void) -{ - if (is_gpmc_muxed()) - board_smc91x_data.flags |= GPMC_MUX_ADD_DATA; - - omap_mux_init_gpio(board_smc91x_data.gpio_irq, OMAP_PIN_INPUT); - gpmc_smc91x_init(&board_smc91x_data); -} - -#else - -static inline void board_smc91x_init(void) -{ -} - -#endif - -static void __init h4_init_flash(void) -{ - unsigned long base; - - if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) { - printk("Can't request GPMC CS for flash\n"); - return; - } - h4_flash_resource.start = base; - h4_flash_resource.end = base + SZ_64M - 1; -} - -static struct at24_platform_data m24c01 = { - .byte_len = SZ_1K / 8, - .page_size = 16, -}; - -static struct i2c_board_info __initdata h4_i2c_board_info[] = { - { - I2C_BOARD_INFO("isp1301_omap", 0x2d), - }, - { /* EEPROM on mainboard */ - I2C_BOARD_INFO("24c01", 0x52), - .platform_data = &m24c01, - }, - { /* EEPROM on cpu card */ - I2C_BOARD_INFO("24c01", 0x57), - .platform_data = &m24c01, - }, -}; - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#endif - -static void __init omap_h4_init(void) -{ - omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF); - - /* - * Make sure the serial ports are muxed on at this point. - * You have to mux them off in device drivers later on - * if not needed. - */ - - board_mkp_init(); - h4_i2c_board_info[0].irq = gpio_to_irq(125); - i2c_register_board_info(1, h4_i2c_board_info, - ARRAY_SIZE(h4_i2c_board_info)); - - platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); - omap_serial_init(); - omap_sdrc_init(NULL, NULL); - h4_init_flash(); - board_smc91x_init(); - - omap_display_init(&h4_dss_data); -} - -MACHINE_START(OMAP_H4, "OMAP2420 H4 board") - /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ - .atag_offset = 0x100, - .reserve = omap_reserve, - .map_io = omap242x_map_io, - .init_early = omap2420_init_early, - .init_irq = omap2_init_irq, - .handle_irq = omap2_intc_handle_irq, - .init_machine = omap_h4_init, - .init_late = omap2420_init_late, - .init_time = omap2_sync32k_timer_init, - .restart = omap2xxx_restart, -MACHINE_END diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 4ec8d82b0492..44a59c3abfb0 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -242,12 +242,18 @@ static void __init ldp_display_init(void) static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { + int res; + /* LCD enable GPIO */ ldp_lcd_pdata.enable_gpio = gpio + 7; /* Backlight enable GPIO */ ldp_lcd_pdata.backlight_gpio = gpio + 15; + res = platform_device_register(&ldp_lcd_device); + if (res) + pr_err("Unable to register LCD: %d\n", res); + return 0; } @@ -346,7 +352,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = { static struct platform_device *ldp_devices[] __initdata = { &ldp_gpio_keys_device, - &ldp_lcd_device, }; #ifdef CONFIG_OMAP_MUX diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 827d15009a86..aead77a4bc6d 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -21,7 +21,6 @@ #include <linux/i2c.h> #include <linux/spi/spi.h> #include <linux/usb/musb.h> -#include <linux/platform_data/i2c-cbus-gpio.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/platform_data/mtd-onenand-omap2.h> #include <linux/mfd/menelaus.h> @@ -32,8 +31,7 @@ #include "common.h" #include "mmc.h" - -#include "mux.h" +#include "soc.h" #include "gpmc-onenand.h" #define TUSB6010_ASYNC_CS 1 @@ -42,44 +40,30 @@ #define TUSB6010_GPIO_ENABLE 0 #define TUSB6010_DMACHAN 0x3f -#if defined(CONFIG_I2C_CBUS_GPIO) || defined(CONFIG_I2C_CBUS_GPIO_MODULE) -static struct i2c_cbus_platform_data n8x0_cbus_data = { - .clk_gpio = 66, - .dat_gpio = 65, - .sel_gpio = 64, -}; +#define NOKIA_N810_WIMAX (1 << 2) +#define NOKIA_N810 (1 << 1) +#define NOKIA_N800 (1 << 0) -static struct platform_device n8x0_cbus_device = { - .name = "i2c-cbus-gpio", - .id = 3, - .dev = { - .platform_data = &n8x0_cbus_data, - }, -}; +static u32 board_caps; -static struct i2c_board_info n8x0_i2c_board_info_3[] __initdata = { - { - I2C_BOARD_INFO("retu-mfd", 0x01), - }, -}; +#define board_is_n800() (board_caps & NOKIA_N800) +#define board_is_n810() (board_caps & NOKIA_N810) +#define board_is_n810_wimax() (board_caps & NOKIA_N810_WIMAX) -static void __init n8x0_cbus_init(void) +static void board_check_revision(void) { - const int retu_irq_gpio = 108; + if (of_have_populated_dt()) { + if (of_machine_is_compatible("nokia,n800")) + board_caps = NOKIA_N800; + else if (of_machine_is_compatible("nokia,n810")) + board_caps = NOKIA_N810; + else if (of_machine_is_compatible("nokia,n810-wimax")) + board_caps = NOKIA_N810_WIMAX; + } - if (gpio_request_one(retu_irq_gpio, GPIOF_IN, "Retu IRQ")) - return; - irq_set_irq_type(gpio_to_irq(retu_irq_gpio), IRQ_TYPE_EDGE_RISING); - n8x0_i2c_board_info_3[0].irq = gpio_to_irq(retu_irq_gpio); - i2c_register_board_info(3, n8x0_i2c_board_info_3, - ARRAY_SIZE(n8x0_i2c_board_info_3)); - platform_device_register(&n8x0_cbus_device); -} -#else /* CONFIG_I2C_CBUS_GPIO */ -static void __init n8x0_cbus_init(void) -{ + if (!board_caps) + pr_err("Unknown board\n"); } -#endif /* CONFIG_I2C_CBUS_GPIO */ #if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) /* @@ -178,49 +162,6 @@ static struct spi_board_info n800_spi_board_info[] __initdata = { }, }; -#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ - defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) - -static struct mtd_partition onenand_partitions[] = { - { - .name = "bootloader", - .offset = 0, - .size = 0x20000, - .mask_flags = MTD_WRITEABLE, /* Force read-only */ - }, - { - .name = "config", - .offset = MTDPART_OFS_APPEND, - .size = 0x60000, - }, - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = 0x200000, - }, - { - .name = "initfs", - .offset = MTDPART_OFS_APPEND, - .size = 0x400000, - }, - { - .name = "rootfs", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct omap_onenand_platform_data board_onenand_data[] = { - { - .cs = 0, - .gpio_irq = 26, - .parts = onenand_partitions, - .nr_parts = ARRAY_SIZE(onenand_partitions), - .flags = ONENAND_SYNC_READ, - } -}; -#endif - #if defined(CONFIG_MENELAUS) && \ (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)) @@ -342,7 +283,7 @@ static void n810_set_power_emmc(struct device *dev, static int n8x0_mmc_set_power(struct device *dev, int slot, int power_on, int vdd) { - if (machine_is_nokia_n800() || slot == 0) + if (board_is_n800() || slot == 0) return n8x0_mmc_set_power_menelaus(dev, slot, power_on, vdd); n810_set_power_emmc(dev, power_on); @@ -388,7 +329,7 @@ static void n8x0_mmc_callback(void *data, u8 card_mask) { int bit, *openp, index; - if (machine_is_nokia_n800()) { + if (board_is_n800()) { bit = 1 << 1; openp = &slot2_cover_open; index = 1; @@ -421,7 +362,7 @@ static int n8x0_mmc_late_init(struct device *dev) if (r < 0) return r; - if (machine_is_nokia_n800()) + if (board_is_n800()) vs2sel = 0; else vs2sel = 2; @@ -444,7 +385,7 @@ static int n8x0_mmc_late_init(struct device *dev) if (r < 0) return r; - if (machine_is_nokia_n800()) { + if (board_is_n800()) { bit = 1 << 1; openp = &slot2_cover_open; } else { @@ -471,7 +412,7 @@ static void n8x0_mmc_shutdown(struct device *dev) { int vs2sel; - if (machine_is_nokia_n800()) + if (board_is_n800()) vs2sel = 0; else vs2sel = 2; @@ -486,7 +427,7 @@ static void n8x0_mmc_cleanup(struct device *dev) gpio_free(N8X0_SLOT_SWITCH_GPIO); - if (machine_is_nokia_n810()) { + if (board_is_n810()) { gpio_free(N810_EMMC_VSD_GPIO); gpio_free(N810_EMMC_VIO_GPIO); } @@ -497,7 +438,7 @@ static void n8x0_mmc_cleanup(struct device *dev) * MMC controller2 is not in use. */ static struct omap_mmc_platform_data mmc1_data = { - .nr_slots = 2, + .nr_slots = 0, .switch_slot = n8x0_mmc_switch_slot, .init = n8x0_mmc_late_init, .cleanup = n8x0_mmc_cleanup, @@ -537,7 +478,7 @@ static void __init n8x0_mmc_init(void) { int err; - if (machine_is_nokia_n810()) { + if (board_is_n810()) { mmc1_data.slots[0].name = "external"; /* @@ -555,7 +496,7 @@ static void __init n8x0_mmc_init(void) if (err) return; - if (machine_is_nokia_n810()) { + if (board_is_n810()) { err = gpio_request_array(n810_emmc_gpios, ARRAY_SIZE(n810_emmc_gpios)); if (err) { @@ -564,11 +505,11 @@ static void __init n8x0_mmc_init(void) } } + mmc1_data.nr_slots = 2; mmc_data[0] = &mmc1_data; - omap242x_init_mmc(mmc_data); } #else - +static struct omap_mmc_platform_data mmc1_data; void __init n8x0_mmc_init(void) { } @@ -650,109 +591,32 @@ static struct i2c_board_info n810_i2c_board_info_2[] __initdata = { }, }; -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - /* I2S codec port pins for McBSP block */ - OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - -static struct omap_device_pad serial2_pads[] __initdata = { - { - .name = "uart3_rx_irrx.uart3_rx_irrx", - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, - .enable = OMAP_MUX_MODE0, - .idle = OMAP_MUX_MODE3 /* Mux as GPIO for idle */ - }, -}; - -static inline void board_serial_init(void) +static int __init n8x0_late_initcall(void) { - struct omap_board_data bdata; - - bdata.flags = 0; - bdata.pads = NULL; - bdata.pads_cnt = 0; - - bdata.id = 0; - omap_serial_init_port(&bdata, NULL); - - bdata.id = 1; - omap_serial_init_port(&bdata, NULL); - - bdata.id = 2; - bdata.pads = serial2_pads; - bdata.pads_cnt = ARRAY_SIZE(serial2_pads); - omap_serial_init_port(&bdata, NULL); -} + if (!board_caps) + return -ENODEV; -#else + n8x0_mmc_init(); + n8x0_usb_init(); -static inline void board_serial_init(void) -{ - omap_serial_init(); + return 0; } +omap_late_initcall(n8x0_late_initcall); -#endif - -static void __init n8x0_init_machine(void) +/* + * Legacy init pdata init for n8x0. Note that we want to follow the + * I2C bus numbering starting at 0 for device tree like other omaps. + */ +void * __init n8x0_legacy_init(void) { - omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); - /* FIXME: add n810 spi devices */ + board_check_revision(); spi_register_board_info(n800_spi_board_info, ARRAY_SIZE(n800_spi_board_info)); - omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, - ARRAY_SIZE(n8x0_i2c_board_info_1)); - omap_register_i2c_bus(2, 400, NULL, 0); - if (machine_is_nokia_n810()) - i2c_register_board_info(2, n810_i2c_board_info_2, + i2c_register_board_info(0, n8x0_i2c_board_info_1, + ARRAY_SIZE(n8x0_i2c_board_info_1)); + if (board_is_n810()) + i2c_register_board_info(1, n810_i2c_board_info_2, ARRAY_SIZE(n810_i2c_board_info_2)); - board_serial_init(); - omap_sdrc_init(NULL, NULL); - gpmc_onenand_init(board_onenand_data); - n8x0_mmc_init(); - n8x0_usb_init(); - n8x0_cbus_init(); -} -MACHINE_START(NOKIA_N800, "Nokia N800") - .atag_offset = 0x100, - .reserve = omap_reserve, - .map_io = omap242x_map_io, - .init_early = omap2420_init_early, - .init_irq = omap2_init_irq, - .handle_irq = omap2_intc_handle_irq, - .init_machine = n8x0_init_machine, - .init_late = omap2420_init_late, - .init_time = omap2_sync32k_timer_init, - .restart = omap2xxx_restart, -MACHINE_END - -MACHINE_START(NOKIA_N810, "Nokia N810") - .atag_offset = 0x100, - .reserve = omap_reserve, - .map_io = omap242x_map_io, - .init_early = omap2420_init_early, - .init_irq = omap2_init_irq, - .handle_irq = omap2_intc_handle_irq, - .init_machine = n8x0_init_machine, - .init_late = omap2420_init_late, - .init_time = omap2_sync32k_timer_init, - .restart = omap2xxx_restart, -MACHINE_END - -MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") - .atag_offset = 0x100, - .reserve = omap_reserve, - .map_io = omap242x_map_io, - .init_early = omap2420_init_early, - .init_irq = omap2_init_irq, - .handle_irq = omap2_intc_handle_irq, - .init_machine = n8x0_init_machine, - .init_late = omap2420_init_late, - .init_time = omap2_sync32k_timer_init, - .restart = omap2xxx_restart, -MACHINE_END + return &mmc1_data; +} diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c deleted file mode 100644 index 865d30ee812f..000000000000 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ /dev/null @@ -1,1064 +0,0 @@ -/* - * AM33XX Clock data - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Vaibhav Hiremath <hvaibhav@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/clk-private.h> -#include <linux/clkdev.h> -#include <linux/io.h> - -#include "am33xx.h" -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "control.h" -#include "cm.h" -#include "cm33xx.h" -#include "cm-regbits-33xx.h" -#include "prm.h" - -/* Modulemode control */ -#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0 -#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1 - -/*LIST_HEAD(clocks);*/ - -/* Root clocks */ - -/* RTC 32k */ -DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0); - -/* On-Chip 32KHz RC OSC */ -DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0); - -/* Crystal input clks */ -DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0); - -/* Oscillator clock */ -/* 19.2, 24, 25 or 26 MHz */ -static const char *sys_clkin_ck_parents[] = { - "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck", - "virt_26000000_ck", -}; - -/* - * sys_clk in: input to the dpll and also used as funtional clock for, - * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse - * - */ -DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0, - AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS), - AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT, - AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH, - 0, NULL); - -/* External clock - 12 MHz */ -DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0); - -/* Module clocks and DPLL outputs */ - -/* DPLL_CORE */ -static struct dpll_data dpll_core_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - -/* CLKDCOLDO output */ -static const char *dpll_core_ck_parents[] = { - "sys_clkin_ck", -}; - -static struct clk dpll_core_ck; - -static const struct clk_ops dpll_core_ck_ops = { - .recalc_rate = &omap3_dpll_recalc, - .get_parent = &omap2_init_dpll_parent, -}; - -static struct clk_hw_omap dpll_core_ck_hw = { - .hw = { - .clk = &dpll_core_ck, - }, - .dpll_data = &dpll_core_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); - -static const char *dpll_core_x2_ck_parents[] = { - "dpll_core_ck", -}; - -static struct clk dpll_core_x2_ck; - -static const struct clk_ops dpll_x2_ck_ops = { - .recalc_rate = &omap3_clkoutx2_recalc, -}; - -static struct clk_hw_omap dpll_core_x2_ck_hw = { - .hw = { - .clk = &dpll_core_x2_ck, - }, - .flags = CLOCK_CLKOUTX2, -}; - -DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops); - -DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, - 0x0, AM33XX_CM_DIV_M4_DPLL_CORE, - AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT, - AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, - NULL); - -DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, - 0x0, AM33XX_CM_DIV_M5_DPLL_CORE, - AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT, - AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, - 0x0, AM33XX_CM_DIV_M6_DPLL_CORE, - AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT, - AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - - -/* DPLL_MPU */ -static struct dpll_data dpll_mpu_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - -/* CLKOUT: fdpll/M2 */ -static struct clk dpll_mpu_ck; - -static const struct clk_ops dpll_mpu_ck_ops = { - .enable = &omap3_noncore_dpll_enable, - .disable = &omap3_noncore_dpll_disable, - .recalc_rate = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .get_parent = &omap2_init_dpll_parent, -}; - -static struct clk_hw_omap dpll_mpu_ck_hw = { - .hw = { - .clk = &dpll_mpu_ck, - }, - .dpll_data = &dpll_mpu_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops); - -/* - * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 - * and ALT_CLK1/2) - */ -DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, - 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT, - AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); - -/* DPLL_DDR */ -static struct dpll_data dpll_ddr_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - -/* CLKOUT: fdpll/M2 */ -static struct clk dpll_ddr_ck; - -static const struct clk_ops dpll_ddr_ck_ops = { - .recalc_rate = &omap3_dpll_recalc, - .get_parent = &omap2_init_dpll_parent, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -static struct clk_hw_omap dpll_ddr_ck_hw = { - .hw = { - .clk = &dpll_ddr_ck, - }, - .dpll_data = &dpll_ddr_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); - -/* - * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 - * and ALT_CLK1/2) - */ -DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck, - 0x0, AM33XX_CM_DIV_M2_DPLL_DDR, - AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -/* emif_fck functional clock */ -DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, - 0x0, 1, 2); - -/* DPLL_DISP */ -static struct dpll_data dpll_disp_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - -/* CLKOUT: fdpll/M2 */ -static struct clk dpll_disp_ck; - -static struct clk_hw_omap dpll_disp_ck_hw = { - .hw = { - .clk = &dpll_disp_ck, - }, - .dpll_data = &dpll_disp_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); - -/* - * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 - * and ALT_CLK1/2) - */ -DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, - CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP, - AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -/* DPLL_PER */ -static struct dpll_data dpll_per_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_PER, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER, - .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK, - .div1_mask = AM33XX_DPLL_PER_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, - .flags = DPLL_J_TYPE, -}; - -/* CLKDCOLDO */ -static struct clk dpll_per_ck; - -static struct clk_hw_omap dpll_per_ck_hw = { - .hw = { - .clk = &dpll_per_ck, - }, - .dpll_data = &dpll_per_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); - -/* CLKOUT: fdpll/M2 */ -DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0, - AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT, - AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, - NULL); - -DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck", - &dpll_per_m2_ck, 0x0, 1, 4); - -DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck", - &dpll_per_m2_ck, 0x0, 1, 4); - -DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck", - &dpll_core_m4_ck, 0x0, 1, 2); - -DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, - 1, 2); - -DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, - 8); - -/* - * Below clock nodes describes clockdomains derived out - * of core clock. - */ -static const struct clk_ops clk_ops_null = { -}; - -static const char *l3_gclk_parents[] = { - "dpll_core_m4_ck" -}; - -static struct clk l3_gclk; -DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL); -DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null); - -static struct clk l4hs_gclk; -DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL); -DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null); - -static const char *l3s_gclk_parents[] = { - "dpll_core_m4_div2_ck" -}; - -static struct clk l3s_gclk; -DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL); -DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null); - -static struct clk l4fw_gclk; -DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL); -DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null); - -static struct clk l4ls_gclk; -DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL); -DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null); - -static struct clk sysclk_div_ck; -DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL); -DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null); - -/* - * In order to match the clock domain with hwmod clockdomain entry, - * separate clock nodes is required for the modules which are - * directly getting their funtioncal clock from sys_clkin. - */ -static struct clk adc_tsc_fck; -DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL); -DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk dcan0_fck; -DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL); -DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk dcan1_fck; -DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL); -DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk mcasp0_fck; -DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL); -DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk mcasp1_fck; -DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL); -DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk smartreflex0_fck; -DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL); -DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk smartreflex1_fck; -DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL); -DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk sha0_fck; -DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL); -DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk aes0_fck; -DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL); -DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk rng_fck; -DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL); -DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null); - -/* - * Modules clock nodes - * - * The following clock leaf nodes are added for the moment because: - * - * - hwmod data is not present for these modules, either hwmod - * control is not required or its not populated. - * - Driver code is not yet migrated to use hwmod/runtime pm - * - Modules outside kernel access (to disable them by default) - * - * - mmu (gfx domain) - * - cefuse - * - usbotg_fck (its additional clock and not really a modulemode) - * - ieee5000 - */ - -DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, - AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0, - AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); - -/* - * clkdiv32 is generated from fixed division of 732.4219 - */ -DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732); - -static struct clk clkdiv32k_ick; - -static const char *clkdiv32k_ick_parent_names[] = { - "clkdiv32k_ck", -}; - -static const struct clk_ops clkdiv32k_ick_ops = { - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .init = &omap2_init_clk_clkdm, -}; - -static struct clk_hw_omap clkdiv32k_ick_hw = { - .hw = { - .clk = &clkdiv32k_ick, - }, - .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL, - .enable_bit = AM33XX_MODULEMODE_SWCTRL_SHIFT, - .clkdm_name = "clk_24mhz_clkdm", -}; - -DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops); - -/* "usbotg_fck" is an additional clock and not really a modulemode */ -DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0, - AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, - 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL, - AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -/* Timers */ -static const struct clksel timer1_clkmux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, - { .parent = &tclkin_ck, .rates = div_1_2_rates }, - { .parent = &clk_rc32k_ck, .rates = div_1_3_rates }, - { .parent = &clk_32768_ck, .rates = div_1_4_rates }, - { .parent = NULL }, -}; - -static const char *timer1_ck_parents[] = { - "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck", - "clk_32768_ck", -}; - -static struct clk timer1_fck; - -static const struct clk_ops timer1_fck_ops = { - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, - .init = &omap2_init_clk_clkdm, -}; - -static struct clk_hw_omap timer1_fck_hw = { - .hw = { - .clk = &timer1_fck, - }, - .clkdm_name = "l4ls_clkdm", - .clksel = timer1_clkmux_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK, - .clksel_mask = AM33XX_CLKSEL_0_2_MASK, -}; - -DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops); - -static const struct clksel timer2_to_7_clk_sel[] = { - { .parent = &tclkin_ck, .rates = div_1_0_rates }, - { .parent = &sys_clkin_ck, .rates = div_1_1_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const char *timer2_to_7_ck_parents[] = { - "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick", -}; - -static struct clk timer2_fck; - -static struct clk_hw_omap timer2_fck_hw = { - .hw = { - .clk = &timer2_fck, - }, - .clkdm_name = "l4ls_clkdm", - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops); - -static struct clk timer3_fck; - -static struct clk_hw_omap timer3_fck_hw = { - .hw = { - .clk = &timer3_fck, - }, - .clkdm_name = "l4ls_clkdm", - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops); - -static struct clk timer4_fck; - -static struct clk_hw_omap timer4_fck_hw = { - .hw = { - .clk = &timer4_fck, - }, - .clkdm_name = "l4ls_clkdm", - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops); - -static struct clk timer5_fck; - -static struct clk_hw_omap timer5_fck_hw = { - .hw = { - .clk = &timer5_fck, - }, - .clkdm_name = "l4ls_clkdm", - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops); - -static struct clk timer6_fck; - -static struct clk_hw_omap timer6_fck_hw = { - .hw = { - .clk = &timer6_fck, - }, - .clkdm_name = "l4ls_clkdm", - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops); - -static struct clk timer7_fck; - -static struct clk_hw_omap timer7_fck_hw = { - .hw = { - .clk = &timer7_fck, - }, - .clkdm_name = "l4ls_clkdm", - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops); - -DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk, - "dpll_core_m5_ck", - &dpll_core_m5_ck, - 0x0, - 1, 2); - -static const struct clk_ops cpsw_fck_ops = { - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -static const struct clksel cpsw_cpts_rft_clkmux_sel[] = { - { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static const char *cpsw_cpts_rft_ck_parents[] = { - "dpll_core_m5_ck", "dpll_core_m4_ck", -}; - -static struct clk cpsw_cpts_rft_clk; - -static struct clk_hw_omap cpsw_cpts_rft_clk_hw = { - .hw = { - .clk = &cpsw_cpts_rft_clk, - }, - .clkdm_name = "cpsw_125mhz_clkdm", - .clksel = cpsw_cpts_rft_clkmux_sel, - .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL, - .clksel_mask = AM33XX_CLKSEL_0_0_MASK, -}; - -DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops); - - -/* gpio */ -static const char *gpio0_ck_parents[] = { - "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick", -}; - -static const struct clksel gpio0_dbclk_mux_sel[] = { - { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, - { .parent = &clk_32768_ck, .rates = div_1_1_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const struct clk_ops gpio_fck_ops = { - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, - .init = &omap2_init_clk_clkdm, -}; - -static struct clk gpio0_dbclk_mux_ck; - -static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = { - .hw = { - .clk = &gpio0_dbclk_mux_ck, - }, - .clkdm_name = "l4_wkup_clkdm", - .clksel = gpio0_dbclk_mux_sel, - .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops); - -DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0, - AM33XX_CM_WKUP_GPIO0_CLKCTRL, - AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0, - AM33XX_CM_PER_GPIO1_CLKCTRL, - AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0, - AM33XX_CM_PER_GPIO2_CLKCTRL, - AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0, - AM33XX_CM_PER_GPIO3_CLKCTRL, - AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL); - - -static const char *pruss_ck_parents[] = { - "l3_gclk", "dpll_disp_m2_ck", -}; - -static const struct clksel pruss_ocp_clk_mux_sel[] = { - { .parent = &l3_gclk, .rates = div_1_0_rates }, - { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk pruss_ocp_gclk; - -static struct clk_hw_omap pruss_ocp_gclk_hw = { - .hw = { - .clk = &pruss_ocp_gclk, - }, - .clkdm_name = "pruss_ocp_clkdm", - .clksel = pruss_ocp_clk_mux_sel, - .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK, - .clksel_mask = AM33XX_CLKSEL_0_0_MASK, -}; - -DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops); - -static const char *lcd_ck_parents[] = { - "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck", -}; - -static const struct clksel lcd_clk_mux_sel[] = { - { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates }, - { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static struct clk lcd_gclk; - -static struct clk_hw_omap lcd_gclk_hw = { - .hw = { - .clk = &lcd_gclk, - }, - .clkdm_name = "lcdc_clkdm", - .clksel = lcd_clk_mux_sel, - .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents, - gpio_fck_ops, CLK_SET_RATE_PARENT); - -DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2); - -static const char *gfx_ck_parents[] = { - "dpll_core_m4_ck", "dpll_per_m2_ck", -}; - -static const struct clksel gfx_clksel_sel[] = { - { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk gfx_fclk_clksel_ck; - -static struct clk_hw_omap gfx_fclk_clksel_ck_hw = { - .hw = { - .clk = &gfx_fclk_clksel_ck, - }, - .clksel = gfx_clksel_sel, - .clksel_reg = AM33XX_CLKSEL_GFX_FCLK, - .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK, -}; - -DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops); - -static const struct clk_div_table div_1_0_2_1_rates[] = { - { .div = 1, .val = 0, }, - { .div = 2, .val = 1, }, - { .div = 0 }, -}; - -DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck", - &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK, - AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH, - 0x0, div_1_0_2_1_rates, NULL); - -static const char *sysclkout_ck_parents[] = { - "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck", - "lcd_gclk", -}; - -static const struct clksel sysclkout_pre_sel[] = { - { .parent = &clk_32768_ck, .rates = div_1_0_rates }, - { .parent = &l3_gclk, .rates = div_1_1_rates }, - { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates }, - { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates }, - { .parent = &lcd_gclk, .rates = div_1_4_rates }, - { .parent = NULL }, -}; - -static struct clk sysclkout_pre_ck; - -static struct clk_hw_omap sysclkout_pre_ck_hw = { - .hw = { - .clk = &sysclkout_pre_ck, - }, - .clksel = sysclkout_pre_sel, - .clksel_reg = AM33XX_CM_CLKOUT_CTRL, - .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK, -}; - -DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops); - -/* Divide by 8 clock rates with default clock is 1/1*/ -static const struct clk_div_table div8_rates[] = { - { .div = 1, .val = 0, }, - { .div = 2, .val = 1, }, - { .div = 3, .val = 2, }, - { .div = 4, .val = 3, }, - { .div = 5, .val = 4, }, - { .div = 6, .val = 5, }, - { .div = 7, .val = 6, }, - { .div = 8, .val = 7, }, - { .div = 0 }, -}; - -DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck, - 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT, - AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL); - -DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0, - AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL); - -static const char *wdt_ck_parents[] = { - "clk_rc32k_ck", "clkdiv32k_ick", -}; - -static const struct clksel wdt_clkmux_sel[] = { - { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk wdt1_fck; - -static struct clk_hw_omap wdt1_fck_hw = { - .hw = { - .clk = &wdt1_fck, - }, - .clkdm_name = "l4_wkup_clkdm", - .clksel = wdt_clkmux_sel, - .clksel_reg = AM33XX_CLKSEL_WDT1_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops); - -static const char *pwmss_clk_parents[] = { - "dpll_per_m2_ck", -}; - -static const struct clk_ops ehrpwm_tbclk_ops = { - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, -}; - -DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm", - NULL, NULL, 0, - AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), - AM33XX_PWMSS0_TBCLKEN_SHIFT, - NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); - -DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm", - NULL, NULL, 0, - AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), - AM33XX_PWMSS1_TBCLKEN_SHIFT, - NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); - -DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm", - NULL, NULL, 0, - AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), - AM33XX_PWMSS2_TBCLKEN_SHIFT, - NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); - -/* - * debugss optional clocks - */ -DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck, - 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, - AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck, - 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, - AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL); - -static const char *stm_pmd_clock_mux_ck_parents[] = { - "dbg_sysclk_ck", "dbg_clka_ck", -}; - -DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0, - AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT, - AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL); - -DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0, - AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, - AM33XX_TRC_PMD_CLKSEL_SHIFT, - AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL); - -DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck", - &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, - AM33XX_STM_PMD_CLKDIVSEL_SHIFT, - AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, - NULL); - -DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck", - &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, - AM33XX_TRC_PMD_CLKDIVSEL_SHIFT, - AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, - NULL); - -/* - * clkdev - */ -static struct omap_clk am33xx_clks[] = { - CLK(NULL, "clk_32768_ck", &clk_32768_ck), - CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), - CLK(NULL, "virt_24000000_ck", &virt_24000000_ck), - CLK(NULL, "virt_25000000_ck", &virt_25000000_ck), - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck), - CLK(NULL, "sys_clkin_ck", &sys_clkin_ck), - CLK(NULL, "tclkin_ck", &tclkin_ck), - CLK(NULL, "dpll_core_ck", &dpll_core_ck), - CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck), - CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck), - CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck), - CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck), - CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck), - CLK("cpu0", NULL, &dpll_mpu_ck), - CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck), - CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck), - CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck), - CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck), - CLK(NULL, "dpll_disp_ck", &dpll_disp_ck), - CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck), - CLK(NULL, "dpll_per_ck", &dpll_per_ck), - CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck), - CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck), - CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck), - CLK(NULL, "adc_tsc_fck", &adc_tsc_fck), - CLK(NULL, "cefuse_fck", &cefuse_fck), - CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck), - CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick), - CLK(NULL, "dcan0_fck", &dcan0_fck), - CLK("481cc000.d_can", NULL, &dcan0_fck), - CLK(NULL, "dcan1_fck", &dcan1_fck), - CLK("481d0000.d_can", NULL, &dcan1_fck), - CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk), - CLK(NULL, "mcasp0_fck", &mcasp0_fck), - CLK(NULL, "mcasp1_fck", &mcasp1_fck), - CLK(NULL, "mmu_fck", &mmu_fck), - CLK(NULL, "smartreflex0_fck", &smartreflex0_fck), - CLK(NULL, "smartreflex1_fck", &smartreflex1_fck), - CLK(NULL, "sha0_fck", &sha0_fck), - CLK(NULL, "aes0_fck", &aes0_fck), - CLK(NULL, "rng_fck", &rng_fck), - CLK(NULL, "timer1_fck", &timer1_fck), - CLK(NULL, "timer2_fck", &timer2_fck), - CLK(NULL, "timer3_fck", &timer3_fck), - CLK(NULL, "timer4_fck", &timer4_fck), - CLK(NULL, "timer5_fck", &timer5_fck), - CLK(NULL, "timer6_fck", &timer6_fck), - CLK(NULL, "timer7_fck", &timer7_fck), - CLK(NULL, "usbotg_fck", &usbotg_fck), - CLK(NULL, "ieee5000_fck", &ieee5000_fck), - CLK(NULL, "wdt1_fck", &wdt1_fck), - CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk), - CLK(NULL, "l3_gclk", &l3_gclk), - CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck), - CLK(NULL, "l4hs_gclk", &l4hs_gclk), - CLK(NULL, "l3s_gclk", &l3s_gclk), - CLK(NULL, "l4fw_gclk", &l4fw_gclk), - CLK(NULL, "l4ls_gclk", &l4ls_gclk), - CLK(NULL, "clk_24mhz", &clk_24mhz), - CLK(NULL, "sysclk_div_ck", &sysclk_div_ck), - CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk), - CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk), - CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck), - CLK(NULL, "gpio0_dbclk", &gpio0_dbclk), - CLK(NULL, "gpio1_dbclk", &gpio1_dbclk), - CLK(NULL, "gpio2_dbclk", &gpio2_dbclk), - CLK(NULL, "gpio3_dbclk", &gpio3_dbclk), - CLK(NULL, "lcd_gclk", &lcd_gclk), - CLK(NULL, "mmc_clk", &mmc_clk), - CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck), - CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck), - CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck), - CLK(NULL, "clkout2_div_ck", &clkout2_div_ck), - CLK(NULL, "timer_32k_ck", &clkdiv32k_ick), - CLK(NULL, "timer_sys_ck", &sys_clkin_ck), - CLK(NULL, "dbg_sysclk_ck", &dbg_sysclk_ck), - CLK(NULL, "dbg_clka_ck", &dbg_clka_ck), - CLK(NULL, "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck), - CLK(NULL, "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck), - CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck), - CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck), - CLK(NULL, "clkout2_ck", &clkout2_ck), - CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk), - CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk), - CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk), -}; - - -static const char *enable_init_clks[] = { - "dpll_ddr_m2_ck", - "dpll_mpu_m2_ck", - "l3_gclk", - "l4hs_gclk", - "l4fw_gclk", - "l4ls_gclk", - "clkout2_ck", /* Required for external peripherals like, Audio codecs */ -}; - -int __init am33xx_clk_init(void) -{ - if (soc_is_am33xx()) - cpu_mask = RATE_IN_AM33XX; - - omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks)); - - omap2_clk_disable_autoidle_all(); - - omap2_clk_enable_init_clocks(enable_init_clks, - ARRAY_SIZE(enable_init_clks)); - - /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always - * physically present, in such a case HWMOD enabling of - * clock would be failure with default parent. And timer - * probe thinks clock is already enabled, this leads to - * crash upon accessing timer 3 & 6 registers in probe. - * Fix by setting parent of both these timers to master - * oscillator clock. - */ - - clk_set_parent(&timer3_fck, &sys_clkin_ck); - clk_set_parent(&timer6_fck, &sys_clkin_ck); - /* - * The On-Chip 32K RC Osc clock is not an accurate clock-source as per - * the design/spec, so as a result, for example, timer which supposed - * to get expired @60Sec, but will expire somewhere ~@40Sec, which is - * not expected by any use-case, so change WDT1 clock source to PRCM - * 32KHz clock. - */ - clk_set_parent(&wdt1_fck, &clkdiv32k_ick); - - return 0; -} diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c deleted file mode 100644 index ec0dc0b1755e..000000000000 --- a/arch/arm/mach-omap2/cclock44xx_data.c +++ /dev/null @@ -1,1735 +0,0 @@ -/* - * OMAP4 Clock data - * - * Copyright (C) 2009-2012 Texas Instruments, Inc. - * Copyright (C) 2009-2010 Nokia Corporation - * - * Paul Walmsley (paul@pwsan.com) - * Rajendra Nayak (rnayak@ti.com) - * Benoit Cousson (b-cousson@ti.com) - * Mike Turquette (mturquette@ti.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * XXX Some of the ES1 clocks have been removed/changed; once support - * is added for discriminating clocks by ES level, these should be added back - * in. - * - * XXX All of the remaining MODULEMODE clock nodes should be removed - * once the drivers are updated to use pm_runtime or to use the appropriate - * upstream clock node for rate/parent selection. - */ - -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/clk-private.h> -#include <linux/clkdev.h> -#include <linux/io.h> - -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "clock44xx.h" -#include "cm1_44xx.h" -#include "cm2_44xx.h" -#include "cm-regbits-44xx.h" -#include "prm44xx.h" -#include "prm-regbits-44xx.h" -#include "control.h" -#include "scrm44xx.h" - -/* OMAP4 modulemode control */ -#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0 -#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1 - -/* - * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section - * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK - * must be set to 196.608 MHz" and hence, the DPLL locked frequency is - * half of this value. - */ -#define OMAP4_DPLL_ABE_DEFFREQ 98304000 - -/* - * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section - * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred - * locked frequency for the USB DPLL is 960MHz. - */ -#define OMAP4_DPLL_USB_DEFFREQ 960000000 - -/* Root clocks */ - -DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0); - -DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0); - -DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0, - OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT, - 0x0, NULL); - -DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0); - -DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0); - -DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0); - -DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0, - OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT, - 0x0, NULL); - -DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0); - -static const char *sys_clkin_ck_parents[] = { - "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck", - "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck", - "virt_38400000_ck", -}; - -DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0, - OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT, - OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL); - -DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0); - -DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0); - -DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0); - -DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0); - -DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0); - -/* Module clocks and DPLL outputs */ - -static const char *abe_dpll_bypass_clk_mux_ck_parents[] = { - "sys_clkin_ck", "sys_32k_ck", -}; - -DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, - NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT, - OMAP4430_CLKSEL_WIDTH, 0x0, NULL); - -DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL, - 0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, - OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); - -/* DPLL_ABE */ -static struct dpll_data dpll_abe_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, - .clk_bypass = &abe_dpll_bypass_clk_mux_ck, - .clk_ref = &abe_dpll_refclk_mux_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .m4xen_mask = OMAP4430_DPLL_REGM4XEN_MASK, - .lpmode_mask = OMAP4430_DPLL_LPMODE_EN_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - - -static const char *dpll_abe_ck_parents[] = { - "abe_dpll_refclk_mux_ck", -}; - -static struct clk dpll_abe_ck; - -static const struct clk_ops dpll_abe_ck_ops = { - .enable = &omap3_noncore_dpll_enable, - .disable = &omap3_noncore_dpll_disable, - .recalc_rate = &omap4_dpll_regm4xen_recalc, - .round_rate = &omap4_dpll_regm4xen_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .get_parent = &omap2_init_dpll_parent, -}; - -static struct clk_hw_omap dpll_abe_ck_hw = { - .hw = { - .clk = &dpll_abe_ck, - }, - .dpll_data = &dpll_abe_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops); - -static const char *dpll_abe_x2_ck_parents[] = { - "dpll_abe_ck", -}; - -static struct clk dpll_abe_x2_ck; - -static const struct clk_ops dpll_abe_x2_ck_ops = { - .recalc_rate = &omap3_clkoutx2_recalc, -}; - -static struct clk_hw_omap dpll_abe_x2_ck_hw = { - .hw = { - .clk = &dpll_abe_x2_ck, - }, - .flags = CLOCK_CLKOUTX2, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, - .ops = &clkhwops_omap4_dpllmx, -}; - -DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops); - -static const struct clk_ops omap_hsdivider_ops = { - .set_rate = &omap2_clksel_set_rate, - .recalc_rate = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, -}; - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, - 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE, - OMAP4430_DPLL_CLKOUT_DIV_MASK); - -DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, - 0x0, 1, 8); - -DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0, - OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT, - OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0, - OMAP4430_CM1_ABE_AESS_CLKCTRL, - OMAP4430_CLKSEL_AESS_FCLK_SHIFT, - OMAP4430_CLKSEL_AESS_FCLK_WIDTH, - 0x0, NULL); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, - 0x0, OMAP4430_CM_DIV_M3_DPLL_ABE, - OMAP4430_DPLL_CLKOUTHIF_DIV_MASK); - -static const char *core_hsd_byp_clk_mux_ck_parents[] = { - "sys_clkin_ck", "dpll_abe_m3x2_ck", -}; - -DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL, - 0x0, OMAP4430_CM_CLKSEL_DPLL_CORE, - OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH, - 0x0, NULL); - -/* DPLL_CORE */ -static struct dpll_data dpll_core_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, - .clk_bypass = &core_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - - -static const char *dpll_core_ck_parents[] = { - "sys_clkin_ck", "core_hsd_byp_clk_mux_ck" -}; - -static struct clk dpll_core_ck; - -static const struct clk_ops dpll_core_ck_ops = { - .recalc_rate = &omap3_dpll_recalc, - .get_parent = &omap2_init_dpll_parent, -}; - -static struct clk_hw_omap dpll_core_ck_hw = { - .hw = { - .clk = &dpll_core_ck, - }, - .dpll_data = &dpll_core_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); - -static const char *dpll_core_x2_ck_parents[] = { - "dpll_core_ck", -}; - -static struct clk dpll_core_x2_ck; - -static struct clk_hw_omap dpll_core_x2_ck_hw = { - .hw = { - .clk = &dpll_core_x2_ck, - }, -}; - -DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck", - &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE, - OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0, - OMAP4430_CM_DIV_M2_DPLL_CORE, - OMAP4430_DPLL_CLKOUT_DIV_MASK); - -DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1, - 2); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck", - &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE, - OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); - -DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0, - OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT, - OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL); - -DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, - 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT, - OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, - 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT, - OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck", - &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE, - OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); - -DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, - 0x0, 1, 2); - -DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0, - OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, - OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); - -static const struct clk_ops dpll_hsd_ops = { - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, - .init = &omap2_init_clk_clkdm, -}; - -static const struct clk_ops func_dmic_abe_gfclk_ops = { - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -static const char *dpll_core_m3x2_ck_parents[] = { - "dpll_core_x2_ck", -}; - -static const struct clksel dpll_core_m3x2_div[] = { - { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -/* XXX Missing round_rate, set_rate in ops */ -DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div, - OMAP4430_CM_DIV_M3_DPLL_CORE, - OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - OMAP4430_CM_DIV_M3_DPLL_CORE, - OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, - dpll_core_m3x2_ck_parents, dpll_hsd_ops); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck", - &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE, - OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); - -static const char *iva_hsd_byp_clk_mux_ck_parents[] = { - "sys_clkin_ck", "div_iva_hs_clk", -}; - -DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL, - 0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, - OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); - -/* DPLL_IVA */ -static struct dpll_data dpll_iva_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, - .clk_bypass = &iva_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - -static const char *dpll_iva_ck_parents[] = { - "sys_clkin_ck", "iva_hsd_byp_clk_mux_ck" -}; - -static struct clk dpll_iva_ck; - -static const struct clk_ops dpll_ck_ops = { - .enable = &omap3_noncore_dpll_enable, - .disable = &omap3_noncore_dpll_disable, - .recalc_rate = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .get_parent = &omap2_init_dpll_parent, -}; - -static struct clk_hw_omap dpll_iva_ck_hw = { - .hw = { - .clk = &dpll_iva_ck, - }, - .dpll_data = &dpll_iva_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops); - -static const char *dpll_iva_x2_ck_parents[] = { - "dpll_iva_ck", -}; - -static struct clk dpll_iva_x2_ck; - -static struct clk_hw_omap dpll_iva_x2_ck_hw = { - .hw = { - .clk = &dpll_iva_x2_ck, - }, -}; - -DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, - 0x0, OMAP4430_CM_DIV_M4_DPLL_IVA, - OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, - 0x0, OMAP4430_CM_DIV_M5_DPLL_IVA, - OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); - -/* DPLL_MPU */ -static struct dpll_data dpll_mpu_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, - .clk_bypass = &div_mpu_hs_clk, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - -static const char *dpll_mpu_ck_parents[] = { - "sys_clkin_ck", "div_mpu_hs_clk" -}; - -static struct clk dpll_mpu_ck; - -static struct clk_hw_omap dpll_mpu_ck_hw = { - .hw = { - .clk = &dpll_mpu_ck, - }, - .dpll_data = &dpll_mpu_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops); - -DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, - OMAP4430_CM_DIV_M2_DPLL_MPU, - OMAP4430_DPLL_CLKOUT_DIV_MASK); - -DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck", - &dpll_abe_m3x2_ck, 0x0, 1, 2); - -static const char *per_hsd_byp_clk_mux_ck_parents[] = { - "sys_clkin_ck", "per_hs_clk_div_ck", -}; - -DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL, - 0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, - OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); - -/* DPLL_PER */ -static struct dpll_data dpll_per_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, - .clk_bypass = &per_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - -static const char *dpll_per_ck_parents[] = { - "sys_clkin_ck", "per_hsd_byp_clk_mux_ck" -}; - -static struct clk dpll_per_ck; - -static struct clk_hw_omap dpll_per_ck_hw = { - .hw = { - .clk = &dpll_per_ck, - }, - .dpll_data = &dpll_per_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops); - -DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0, - OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, - OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); - -static const char *dpll_per_x2_ck_parents[] = { - "dpll_per_ck", -}; - -static struct clk dpll_per_x2_ck; - -static struct clk_hw_omap dpll_per_x2_ck_hw = { - .hw = { - .clk = &dpll_per_x2_ck, - }, - .flags = CLOCK_CLKOUTX2, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, - .ops = &clkhwops_omap4_dpllmx, -}; - -DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, - 0x0, OMAP4430_CM_DIV_M2_DPLL_PER, - OMAP4430_DPLL_CLKOUT_DIV_MASK); - -static const char *dpll_per_m3x2_ck_parents[] = { - "dpll_per_x2_ck", -}; - -static const struct clksel dpll_per_m3x2_div[] = { - { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -/* XXX Missing round_rate, set_rate in ops */ -DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div, - OMAP4430_CM_DIV_M3_DPLL_PER, - OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - OMAP4430_CM_DIV_M3_DPLL_PER, - OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, - dpll_per_m3x2_ck_parents, dpll_hsd_ops); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, - 0x0, OMAP4430_CM_DIV_M4_DPLL_PER, - OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, - 0x0, OMAP4430_CM_DIV_M5_DPLL_PER, - OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, - 0x0, OMAP4430_CM_DIV_M6_DPLL_PER, - OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, - 0x0, OMAP4430_CM_DIV_M7_DPLL_PER, - OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); - -DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck", - &dpll_abe_m3x2_ck, 0x0, 1, 3); - -/* DPLL_USB */ -static struct dpll_data dpll_usb_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, - .clk_bypass = &usb_hs_clk_div_ck, - .flags = DPLL_J_TYPE, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, - .mult_mask = OMAP4430_DPLL_MULT_USB_MASK, - .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, - .max_multiplier = 4095, - .max_divider = 256, - .min_divider = 1, -}; - -static const char *dpll_usb_ck_parents[] = { - "sys_clkin_ck", "usb_hs_clk_div_ck" -}; - -static struct clk dpll_usb_ck; - -static const struct clk_ops dpll_usb_ck_ops = { - .enable = &omap3_noncore_dpll_enable, - .disable = &omap3_noncore_dpll_disable, - .recalc_rate = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .get_parent = &omap2_init_dpll_parent, - .init = &omap2_init_clk_clkdm, -}; - -static struct clk_hw_omap dpll_usb_ck_hw = { - .hw = { - .clk = &dpll_usb_ck, - }, - .dpll_data = &dpll_usb_dd, - .clkdm_name = "l3_init_clkdm", - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops); - -static const char *dpll_usb_clkdcoldo_ck_parents[] = { - "dpll_usb_ck", -}; - -static struct clk dpll_usb_clkdcoldo_ck; - -static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = { -}; - -static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = { - .hw = { - .clk = &dpll_usb_clkdcoldo_ck, - }, - .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, - .ops = &clkhwops_omap4_dpllmx, -}; - -DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents, - dpll_usb_clkdcoldo_ck_ops); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0, - OMAP4430_CM_DIV_M2_DPLL_USB, - OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK); - -static const char *ducati_clk_mux_ck_parents[] = { - "div_core_ck", "dpll_per_m6x2_ck", -}; - -DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0, - OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT, - OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); - -DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, - 0x0, 1, 16); - -DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, - 1, 4); - -DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, - 0x0, 1, 8); - -static const struct clk_div_table func_48m_fclk_rates[] = { - { .div = 4, .val = 0 }, - { .div = 8, .val = 1 }, - { .div = 0 }, -}; -DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, - 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, - OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates, - NULL); - -DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, - 0x0, 1, 4); - -static const struct clk_div_table func_64m_fclk_rates[] = { - { .div = 2, .val = 0 }, - { .div = 4, .val = 1 }, - { .div = 0 }, -}; -DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, - 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, - OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates, - NULL); - -static const struct clk_div_table func_96m_fclk_rates[] = { - { .div = 2, .val = 0 }, - { .div = 4, .val = 1 }, - { .div = 0 }, -}; -DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, - 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, - OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates, - NULL); - -static const struct clk_div_table init_60m_fclk_rates[] = { - { .div = 1, .val = 0 }, - { .div = 8, .val = 1 }, - { .div = 0 }, -}; -DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck, - 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ, - OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH, - 0x0, init_60m_fclk_rates, NULL); - -DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0, - OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT, - OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL); - -DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0, - OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT, - OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL); - -DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, - 0x0, 1, 16); - -static const char *l4_wkup_clk_mux_ck_parents[] = { - "sys_clkin_ck", "lp_clk_div_ck", -}; - -DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0, - OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, - OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); - -static const struct clk_div_table ocp_abe_iclk_rates[] = { - { .div = 2, .val = 0 }, - { .div = 1, .val = 1 }, - { .div = 0 }, -}; -DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0, - OMAP4430_CM1_ABE_AESS_CLKCTRL, - OMAP4430_CLKSEL_AESS_FCLK_SHIFT, - OMAP4430_CLKSEL_AESS_FCLK_WIDTH, - 0x0, ocp_abe_iclk_rates, NULL); - -DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, - 0x0, 1, 4); - -DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0, - OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, - OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL); - -DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0, - OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, - OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); - -static const char *dbgclk_mux_ck_parents[] = { - "sys_clkin_ck" -}; - -static struct clk dbgclk_mux_ck; -DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL); -DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents, - dpll_usb_clkdcoldo_ck_ops); - -/* Leaf clocks controlled by modules */ - -DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0, - OMAP4430_CM_L4SEC_AES1_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0, - OMAP4430_CM_L4SEC_AES2_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, - OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL); - -static const struct clk_div_table div_ts_ck_rates[] = { - { .div = 8, .val = 0 }, - { .div = 16, .val = 1 }, - { .div = 32, .val = 2 }, - { .div = 0 }, -}; -DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, - 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, - OMAP4430_CLKSEL_24_25_SHIFT, - OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates, - NULL); - -DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0, - OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, - OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, - 0x0, NULL); - -static const char *dmic_sync_mux_ck_parents[] = { - "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk", -}; - -DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, - 0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL, - OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, - OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); - -static const struct clksel func_dmic_abe_gfclk_sel[] = { - { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const char *func_dmic_abe_gfclk_parents[] = { - "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk", -}; - -DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel, - OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK, - func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0, - OMAP4430_CM_DSS_DSS_CLKCTRL, - OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, - OMAP4430_CM_DSS_DSS_CLKCTRL, - OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, - CLK_SET_RATE_PARENT, - OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0, - OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0, - OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); - -DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, - OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT, - OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_WKUP_GPIO1_CLKCTRL, - OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_L4PER_GPIO3_CLKCTRL, - OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - 0x0, NULL); - -static const struct clksel sgx_clk_mux_sel[] = { - { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static const char *sgx_clk_mux_parents[] = { - "dpll_core_m7x2_ck", "dpll_per_m7x2_ck", -}; - -DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel, - OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK, - sgx_clk_mux_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0, - OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT, - OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO, - NULL); - -DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0, - OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, - 0x0, NULL); - -DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, - OMAP4430_CM1_ABE_MCASP_CLKCTRL, - OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, - OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); - -static const struct clksel func_mcasp_abe_gfclk_sel[] = { - { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const char *func_mcasp_abe_gfclk_parents[] = { - "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk", -}; - -DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel, - OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK, - func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, - OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, - OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, - OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); - -static const struct clksel func_mcbsp1_gfclk_sel[] = { - { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const char *func_mcbsp1_gfclk_parents[] = { - "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk", -}; - -DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel, - OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, - OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents, - func_dmic_abe_gfclk_ops); - -DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, - OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, - OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, - OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); - -static const struct clksel func_mcbsp2_gfclk_sel[] = { - { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const char *func_mcbsp2_gfclk_parents[] = { - "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk", -}; - -DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel, - OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, - OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents, - func_dmic_abe_gfclk_ops); - -DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, - OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, - OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, - OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); - -static const struct clksel func_mcbsp3_gfclk_sel[] = { - { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const char *func_mcbsp3_gfclk_parents[] = { - "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk", -}; - -DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel, - OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, - OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents, - func_dmic_abe_gfclk_ops); - -static const char *mcbsp4_sync_mux_ck_parents[] = { - "func_96m_fclk", "per_abe_nc_fclk", -}; - -DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0, - OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, - OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, - OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); - -static const struct clksel per_mcbsp4_gfclk_sel[] = { - { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static const char *per_mcbsp4_gfclk_parents[] = { - "mcbsp4_sync_mux_ck", "pad_clks_ck", -}; - -DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel, - OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, - OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents, - func_dmic_abe_gfclk_ops); - -static const struct clksel hsmmc1_fclk_sel[] = { - { .parent = &func_64m_fclk, .rates = div_1_0_rates }, - { .parent = &func_96m_fclk, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static const char *hsmmc1_fclk_parents[] = { - "func_64m_fclk", "func_96m_fclk", -}; - -DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel, - OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK, - hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel, - OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, - hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0, - OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, - OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0, - OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0, - OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0, - OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0, - OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0, - OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0, - OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck", - &pad_slimbus_core_clks_ck, 0x0, - OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, - 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, - 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, - 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -static const struct clksel dmt1_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK, - abe_dpll_bypass_clk_mux_ck_parents, - func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK, - abe_dpll_bypass_clk_mux_ck_parents, - func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK, - abe_dpll_bypass_clk_mux_ck_parents, - func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK, - abe_dpll_bypass_clk_mux_ck_parents, - func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK, - abe_dpll_bypass_clk_mux_ck_parents, - func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK, - abe_dpll_bypass_clk_mux_ck_parents, - func_dmic_abe_gfclk_ops); - -static const struct clksel timer5_sync_mux_sel[] = { - { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static const char *timer5_sync_mux_parents[] = { - "syc_clk_div_ck", "sys_32k_ck", -}; - -DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel, - OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK, - timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel, - OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK, - timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel, - OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK, - timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel, - OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK, - timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK, - abe_dpll_bypass_clk_mux_ck_parents, - func_dmic_abe_gfclk_ops); - -static struct clk usb_host_fs_fck; - -static const char *usb_host_fs_fck_parent_names[] = { - "func_48mc_fclk", -}; - -static const struct clk_ops usb_host_fs_fck_ops = { - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, -}; - -static struct clk_hw_omap usb_host_fs_fck_hw = { - .hw = { - .clk = &usb_host_fs_fck, - }, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, - .clkdm_name = "l3_init_clkdm", -}; - -DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names, - usb_host_fs_fck_ops); - -static const char *utmi_p1_gfclk_parents[] = { - "init_60m_fclk", "xclk60mhsp1_ck", -}; - -DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH, - 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL); - -static const char *utmi_p2_gfclk_parents[] = { - "init_60m_fclk", "xclk60mhsp2_ck", -}; - -DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH, - 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck", - &dpll_usb_m2_ck, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk", - &init_60m_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk", - &init_60m_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck", - &dpll_usb_m2_ck, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -static const char *otg_60m_gfclk_parents[] = { - "utmi_phy_clkout_ck", "xclk60motg_ck", -}; - -DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0, - OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT, - OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL); - -DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0, - OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0, - OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_ALWON_USBPHY_CLKCTRL, - OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0, - OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); - -static const struct clk_div_table usim_ck_rates[] = { - { .div = 14, .val = 0 }, - { .div = 18, .val = 1 }, - { .div = 0 }, -}; -DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, - OMAP4430_CM_WKUP_USIM_CLKCTRL, - OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH, - 0x0, usim_ck_rates, NULL); - -DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0, - OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT, - 0x0, NULL); - -/* Remaining optional clocks */ -static const char *pmd_stm_clock_mux_ck_parents[] = { - "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck", -}; - -DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, - OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT, - OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL); - -DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, - OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT, - OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL); - -DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck", - &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT, - OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, - NULL); - -static const char *trace_clk_div_ck_parents[] = { - "pmd_trace_clk_mux_ck", -}; - -static const struct clksel trace_clk_div_div[] = { - { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; - -static struct clk trace_clk_div_ck; - -static const struct clk_ops trace_clk_div_ck_ops = { - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .init = &omap2_init_clk_clkdm, - .enable = &omap2_clkops_enable_clkdm, - .disable = &omap2_clkops_disable_clkdm, -}; - -static struct clk_hw_omap trace_clk_div_ck_hw = { - .hw = { - .clk = &trace_clk_div_ck, - }, - .clkdm_name = "emu_sys_clkdm", - .clksel = trace_clk_div_div, - .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, -}; - -DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents, - trace_clk_div_ck_ops); - -/* SCRM aux clk nodes */ - -static const struct clksel auxclk_src_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, - { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const char *auxclk_src_ck_parents[] = { - "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck", -}; - -static const struct clk_ops auxclk_src_ck_ops = { - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, -}; - -DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel, - OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK, - OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL, - auxclk_src_ck_parents, auxclk_src_ck_ops); - -DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0, - OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, - 0x0, NULL); - -DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel, - OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK, - OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL, - auxclk_src_ck_parents, auxclk_src_ck_ops); - -DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0, - OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, - 0x0, NULL); - -DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel, - OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK, - OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL, - auxclk_src_ck_parents, auxclk_src_ck_ops); - -DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0, - OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, - 0x0, NULL); - -DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel, - OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK, - OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL, - auxclk_src_ck_parents, auxclk_src_ck_ops); - -DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0, - OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, - 0x0, NULL); - -DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel, - OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK, - OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL, - auxclk_src_ck_parents, auxclk_src_ck_ops); - -DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0, - OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, - 0x0, NULL); - -DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel, - OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK, - OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL, - auxclk_src_ck_parents, auxclk_src_ck_ops); - -DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0, - OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, - 0x0, NULL); - -static const char *auxclkreq_ck_parents[] = { - "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck", - "auxclk5_ck", -}; - -DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0, - OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, - 0x0, NULL); - -DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0, - OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, - 0x0, NULL); - -DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0, - OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, - 0x0, NULL); - -DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0, - OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, - 0x0, NULL); - -DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0, - OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, - 0x0, NULL); - -DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0, - OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, - 0x0, NULL); - -/* - * clocks specific to omap4460 - */ -static struct omap_clk omap446x_clks[] = { - CLK(NULL, "div_ts_ck", &div_ts_ck), - CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk), -}; - -/* - * clocks specific to omap4430 - */ -static struct omap_clk omap443x_clks[] = { - CLK(NULL, "bandgap_fclk", &bandgap_fclk), -}; - -/* - * clocks common to omap44xx - */ -static struct omap_clk omap44xx_clks[] = { - CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck), - CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck), - CLK(NULL, "pad_clks_ck", &pad_clks_ck), - CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck), - CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck), - CLK(NULL, "slimbus_src_clk", &slimbus_src_clk), - CLK(NULL, "slimbus_clk", &slimbus_clk), - CLK(NULL, "sys_32k_ck", &sys_32k_ck), - CLK(NULL, "virt_12000000_ck", &virt_12000000_ck), - CLK(NULL, "virt_13000000_ck", &virt_13000000_ck), - CLK(NULL, "virt_16800000_ck", &virt_16800000_ck), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck), - CLK(NULL, "virt_27000000_ck", &virt_27000000_ck), - CLK(NULL, "virt_38400000_ck", &virt_38400000_ck), - CLK(NULL, "sys_clkin_ck", &sys_clkin_ck), - CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck), - CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck), - CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck), - CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck), - CLK(NULL, "xclk60motg_ck", &xclk60motg_ck), - CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck), - CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck), - CLK(NULL, "dpll_abe_ck", &dpll_abe_ck), - CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck), - CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck), - CLK(NULL, "abe_24m_fclk", &abe_24m_fclk), - CLK(NULL, "abe_clk", &abe_clk), - CLK(NULL, "aess_fclk", &aess_fclk), - CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck), - CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck), - CLK(NULL, "dpll_core_ck", &dpll_core_ck), - CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck), - CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck), - CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck), - CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck), - CLK(NULL, "ddrphy_ck", &ddrphy_ck), - CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck), - CLK(NULL, "div_core_ck", &div_core_ck), - CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk), - CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk), - CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck), - CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck), - CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck), - CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck), - CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck), - CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck), - CLK(NULL, "dpll_iva_ck", &dpll_iva_ck), - CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck), - CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck), - CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck), - CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck), - CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck), - CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck), - CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck), - CLK(NULL, "dpll_per_ck", &dpll_per_ck), - CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck), - CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck), - CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck), - CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck), - CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck), - CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck), - CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck), - CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck), - CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck), - CLK(NULL, "dpll_usb_ck", &dpll_usb_ck), - CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck), - CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck), - CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck), - CLK(NULL, "func_12m_fclk", &func_12m_fclk), - CLK(NULL, "func_24m_clk", &func_24m_clk), - CLK(NULL, "func_24mc_fclk", &func_24mc_fclk), - CLK(NULL, "func_48m_fclk", &func_48m_fclk), - CLK(NULL, "func_48mc_fclk", &func_48mc_fclk), - CLK(NULL, "func_64m_fclk", &func_64m_fclk), - CLK(NULL, "func_96m_fclk", &func_96m_fclk), - CLK(NULL, "init_60m_fclk", &init_60m_fclk), - CLK(NULL, "l3_div_ck", &l3_div_ck), - CLK(NULL, "l4_div_ck", &l4_div_ck), - CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck), - CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck), - CLK("smp_twd", NULL, &mpu_periphclk), - CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk), - CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk), - CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk), - CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck), - CLK(NULL, "aes1_fck", &aes1_fck), - CLK(NULL, "aes2_fck", &aes2_fck), - CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck), - CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk), - CLK(NULL, "dss_sys_clk", &dss_sys_clk), - CLK(NULL, "dss_tv_clk", &dss_tv_clk), - CLK(NULL, "dss_dss_clk", &dss_dss_clk), - CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk), - CLK(NULL, "dss_fck", &dss_fck), - CLK("omapdss_dss", "ick", &dss_fck), - CLK(NULL, "fdif_fck", &fdif_fck), - CLK(NULL, "gpio1_dbclk", &gpio1_dbclk), - CLK(NULL, "gpio2_dbclk", &gpio2_dbclk), - CLK(NULL, "gpio3_dbclk", &gpio3_dbclk), - CLK(NULL, "gpio4_dbclk", &gpio4_dbclk), - CLK(NULL, "gpio5_dbclk", &gpio5_dbclk), - CLK(NULL, "gpio6_dbclk", &gpio6_dbclk), - CLK(NULL, "sgx_clk_mux", &sgx_clk_mux), - CLK(NULL, "hsi_fck", &hsi_fck), - CLK(NULL, "iss_ctrlclk", &iss_ctrlclk), - CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck), - CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk), - CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck), - CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk), - CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck), - CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk), - CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck), - CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk), - CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck), - CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk), - CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk), - CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk), - CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m), - CLK(NULL, "sha2md5_fck", &sha2md5_fck), - CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1), - CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0), - CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2), - CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk), - CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1), - CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0), - CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk), - CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck), - CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck), - CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck), - CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux), - CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux), - CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux), - CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux), - CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux), - CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux), - CLK(NULL, "timer5_sync_mux", &timer5_sync_mux), - CLK(NULL, "timer6_sync_mux", &timer6_sync_mux), - CLK(NULL, "timer7_sync_mux", &timer7_sync_mux), - CLK(NULL, "timer8_sync_mux", &timer8_sync_mux), - CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux), - CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck), - CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck), - CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk), - CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk), - CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk), - CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk), - CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk), - CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk), - CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk), - CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk), - CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk), - CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk), - CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck), - CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck), - CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk), - CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk), - CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick), - CLK("musb-omap2430", "ick", &usb_otg_hs_ick), - CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k), - CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk), - CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk), - CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk), - CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick), - CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick), - CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick), - CLK(NULL, "usim_ck", &usim_ck), - CLK(NULL, "usim_fclk", &usim_fclk), - CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck), - CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck), - CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck), - CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck), - CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck), - CLK(NULL, "auxclk0_ck", &auxclk0_ck), - CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck), - CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck), - CLK(NULL, "auxclk1_ck", &auxclk1_ck), - CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck), - CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck), - CLK(NULL, "auxclk2_ck", &auxclk2_ck), - CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck), - CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck), - CLK(NULL, "auxclk3_ck", &auxclk3_ck), - CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck), - CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck), - CLK(NULL, "auxclk4_ck", &auxclk4_ck), - CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck), - CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck), - CLK(NULL, "auxclk5_ck", &auxclk5_ck), - CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck), - CLK("50000000.gpmc", "fck", &dummy_ck), - CLK("omap_i2c.1", "ick", &dummy_ck), - CLK("omap_i2c.2", "ick", &dummy_ck), - CLK("omap_i2c.3", "ick", &dummy_ck), - CLK("omap_i2c.4", "ick", &dummy_ck), - CLK(NULL, "mailboxes_ick", &dummy_ck), - CLK("omap_hsmmc.0", "ick", &dummy_ck), - CLK("omap_hsmmc.1", "ick", &dummy_ck), - CLK("omap_hsmmc.2", "ick", &dummy_ck), - CLK("omap_hsmmc.3", "ick", &dummy_ck), - CLK("omap_hsmmc.4", "ick", &dummy_ck), - CLK("omap-mcbsp.1", "ick", &dummy_ck), - CLK("omap-mcbsp.2", "ick", &dummy_ck), - CLK("omap-mcbsp.3", "ick", &dummy_ck), - CLK("omap-mcbsp.4", "ick", &dummy_ck), - CLK("omap2_mcspi.1", "ick", &dummy_ck), - CLK("omap2_mcspi.2", "ick", &dummy_ck), - CLK("omap2_mcspi.3", "ick", &dummy_ck), - CLK("omap2_mcspi.4", "ick", &dummy_ck), - CLK(NULL, "uart1_ick", &dummy_ck), - CLK(NULL, "uart2_ick", &dummy_ck), - CLK(NULL, "uart3_ick", &dummy_ck), - CLK(NULL, "uart4_ick", &dummy_ck), - CLK("usbhs_omap", "usbhost_ick", &dummy_ck), - CLK("usbhs_omap", "usbtll_fck", &dummy_ck), - CLK("usbhs_tll", "usbtll_fck", &dummy_ck), - CLK("omap_wdt", "ick", &dummy_ck), - CLK(NULL, "timer_32k_ck", &sys_32k_ck), - /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ - CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck), - CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck), - CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck), - CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck), - CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck), - CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck), - CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck), - CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck), - CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck), - CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck), - CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck), - CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck), - CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck), - CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck), - CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck), - CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck), - CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck), - CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck), - CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck), - CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck), - CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck), - CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck), - CLK(NULL, "cpufreq_ck", &dpll_mpu_ck), -}; - -int __init omap4xxx_clk_init(void) -{ - int rc; - - if (cpu_is_omap443x()) { - cpu_mask = RATE_IN_4430; - omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks)); - } else if (cpu_is_omap446x() || cpu_is_omap447x()) { - cpu_mask = RATE_IN_4460 | RATE_IN_4430; - omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks)); - if (cpu_is_omap447x()) - pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); - } else { - return 0; - } - - omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks)); - - omap2_clk_disable_autoidle_all(); - - /* - * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL - * when its in bypass. So always lock USB before ABE DPLL. - */ - /* - * Lock USB DPLL on OMAP4 devices so that the L3INIT power - * domain can transition to retention state when not in use. - */ - rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ); - if (rc) - pr_err("%s: failed to configure USB DPLL!\n", __func__); - - /* - * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power - * state when turning the ABE clock domain. Workaround this by - * locking the ABE DPLL on boot. - * Lock the ABE DPLL in any case to avoid issues with audio. - */ - rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck); - if (!rc) - rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ); - if (rc) - pr_err("%s: failed to configure ABE DPLL!\n", __func__); - - return 0; -} diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 0ec9f6fdf046..7ee26108ac0d 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -97,12 +97,12 @@ static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) { u32 v; - v = __raw_readl(clk->clksel_reg); + v = omap2_clk_readl(clk, clk->clksel_reg); v &= ~clk->clksel_mask; v |= field_val << __ffs(clk->clksel_mask); - __raw_writel(v, clk->clksel_reg); + omap2_clk_writel(v, clk, clk->clksel_reg); - v = __raw_readl(clk->clksel_reg); /* OCP barrier */ + v = omap2_clk_readl(clk, clk->clksel_reg); /* OCP barrier */ } /** @@ -204,7 +204,7 @@ static u32 _read_divisor(struct clk_hw_omap *clk) if (!clk->clksel || !clk->clksel_mask) return 0; - v = __raw_readl(clk->clksel_reg); + v = omap2_clk_readl(clk, clk->clksel_reg); v &= clk->clksel_mask; v >>= __ffs(clk->clksel_mask); @@ -320,7 +320,7 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw) WARN((!clk->clksel || !clk->clksel_mask), "clock: %s: attempt to call on a non-clksel clock", clk_name); - r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; + r = omap2_clk_readl(clk, clk->clksel_reg) & clk->clksel_mask; r >>= __ffs(clk->clksel_mask); for (clks = clk->clksel; clks->parent && !found; clks++) { diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 924c230f8948..47f9562ca7aa 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -196,7 +196,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) if (!dd) return -EINVAL; - v = __raw_readl(dd->control_reg); + v = omap2_clk_readl(clk, dd->control_reg); v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); @@ -243,7 +243,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) return 0; /* Return bypass rate if DPLL is bypassed */ - v = __raw_readl(dd->control_reg); + v = omap2_clk_readl(clk, dd->control_reg); v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); @@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) return __clk_get_rate(dd->clk_bypass); } - v = __raw_readl(dd->mult_div1_reg); + v = omap2_clk_readl(clk, dd->mult_div1_reg); dpll_mult = v & dd->mult_mask; dpll_mult >>= __ffs(dd->mult_mask); dpll_div = v & dd->div1_mask; diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c index f10eb03ce3e2..333f0a666171 100644 --- a/arch/arm/mach-omap2/clkt_iclk.c +++ b/arch/arm/mach-omap2/clkt_iclk.c @@ -25,25 +25,29 @@ /* XXX */ void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) { - u32 v, r; + u32 v; + void __iomem *r; - r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); + r = (__force void __iomem *) + ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); - v = __raw_readl((__force void __iomem *)r); + v = omap2_clk_readl(clk, r); v |= (1 << clk->enable_bit); - __raw_writel(v, (__force void __iomem *)r); + omap2_clk_writel(v, clk, r); } /* XXX */ void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) { - u32 v, r; + u32 v; + void __iomem *r; - r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); + r = (__force void __iomem *) + ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); - v = __raw_readl((__force void __iomem *)r); + v = omap2_clk_readl(clk, r); v &= ~(1 << clk->enable_bit); - __raw_writel(v, (__force void __iomem *)r); + omap2_clk_writel(v, clk, r); } /* Public data */ diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index c7c5d31e9082..591581a66532 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -26,7 +26,6 @@ #include <linux/clk-private.h> #include <asm/cpu.h> - #include <trace/events/power.h> #include "soc.h" @@ -56,6 +55,31 @@ u16 cpu_mask; static bool clkdm_control = true; static LIST_HEAD(clk_hw_omap_clocks); +void __iomem *clk_memmaps[CLK_MAX_MEMMAPS]; + +void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) +{ + if (clk->flags & MEMMAP_ADDRESSING) { + struct clk_omap_reg *r = (struct clk_omap_reg *)® + writel_relaxed(val, clk_memmaps[r->index] + r->offset); + } else { + writel_relaxed(val, reg); + } +} + +u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) +{ + u32 val; + + if (clk->flags & MEMMAP_ADDRESSING) { + struct clk_omap_reg *r = (struct clk_omap_reg *)® + val = readl_relaxed(clk_memmaps[r->index] + r->offset); + } else { + val = readl_relaxed(reg); + } + + return val; +} /* * Used for clocks that have the same value as the parent clock, @@ -87,6 +111,7 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, /** * _wait_idlest_generic - wait for a module to leave the idle state + * @clk: module clock to wait for (needed for register offsets) * @reg: virtual address of module IDLEST register * @mask: value to mask against to determine if the module is active * @idlest: idle state indicator (0 or 1) for the clock @@ -98,14 +123,14 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, * elapsed. XXX Deprecated - should be moved into drivers for the * individual IP block that the IDLEST register exists in. */ -static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest, - const char *name) +static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, + u32 mask, u8 idlest, const char *name) { int i = 0, ena = 0; ena = (idlest) ? 0 : mask; - omap_test_timeout(((__raw_readl(reg) & mask) == ena), + omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), MAX_MODULE_ENABLE_WAIT, i); if (i < MAX_MODULE_ENABLE_WAIT) @@ -138,7 +163,7 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk) /* Not all modules have multiple clocks that their IDLEST depends on */ if (clk->ops->find_companion) { clk->ops->find_companion(clk, &companion_reg, &other_bit); - if (!(__raw_readl(companion_reg) & (1 << other_bit))) + if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) return; } @@ -146,8 +171,8 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk) r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); if (r) { /* IDLEST register not in the CM module */ - _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val, - __clk_get_name(clk->hw.clk)); + _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), + idlest_val, __clk_get_name(clk->hw.clk)); } else { cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); }; @@ -309,13 +334,13 @@ int omap2_dflt_clk_enable(struct clk_hw *hw) } /* FIXME should not have INVERT_ENABLE bit here */ - v = __raw_readl(clk->enable_reg); + v = omap2_clk_readl(clk, clk->enable_reg); if (clk->flags & INVERT_ENABLE) v &= ~(1 << clk->enable_bit); else v |= (1 << clk->enable_bit); - __raw_writel(v, clk->enable_reg); - v = __raw_readl(clk->enable_reg); /* OCP barrier */ + omap2_clk_writel(v, clk, clk->enable_reg); + v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ if (clk->ops && clk->ops->find_idlest) _omap2_module_wait_ready(clk); @@ -353,12 +378,12 @@ void omap2_dflt_clk_disable(struct clk_hw *hw) return; } - v = __raw_readl(clk->enable_reg); + v = omap2_clk_readl(clk, clk->enable_reg); if (clk->flags & INVERT_ENABLE) v |= (1 << clk->enable_bit); else v &= ~(1 << clk->enable_bit); - __raw_writel(v, clk->enable_reg); + omap2_clk_writel(v, clk, clk->enable_reg); /* No OCP barrier needed here since it is a disable operation */ if (clkdm_control && clk->clkdm) @@ -454,7 +479,7 @@ int omap2_dflt_clk_is_enabled(struct clk_hw *hw) struct clk_hw_omap *clk = to_clk_hw_omap(hw); u32 v; - v = __raw_readl(clk->enable_reg); + v = omap2_clk_readl(clk, clk->enable_reg); if (clk->flags & INVERT_ENABLE) v ^= BIT(clk->enable_bit); @@ -520,6 +545,9 @@ int omap2_clk_enable_autoidle_all(void) list_for_each_entry(c, &clk_hw_omap_clocks, node) if (c->ops && c->ops->allow_idle) c->ops->allow_idle(c); + + of_ti_clk_allow_autoidle_all(); + return 0; } @@ -539,6 +567,9 @@ int omap2_clk_disable_autoidle_all(void) list_for_each_entry(c, &clk_hw_omap_clocks, node) if (c->ops && c->ops->deny_idle) c->ops->deny_idle(c); + + of_ti_clk_deny_autoidle_all(); + return 0; } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 82916cc82c92..bda767a9dea8 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -21,6 +21,7 @@ #include <linux/clkdev.h> #include <linux/clk-provider.h> +#include <linux/clk/ti.h> struct omap_clk { u16 cpu; @@ -37,7 +38,6 @@ struct omap_clk { } struct clockdomain; -#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ static struct clk _name = { \ @@ -178,141 +178,6 @@ struct clksel { const struct clksel_rate *rates; }; -/** - * struct dpll_data - DPLL registers and integration data - * @mult_div1_reg: register containing the DPLL M and N bitfields - * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg - * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg - * @clk_bypass: struct clk pointer to the clock's bypass clock input - * @clk_ref: struct clk pointer to the clock's reference clock input - * @control_reg: register containing the DPLL mode bitfield - * @enable_mask: mask of the DPLL mode bitfield in @control_reg - * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() - * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() - * @last_rounded_m4xen: cache of the last M4X result of - * omap4_dpll_regm4xen_round_rate() - * @last_rounded_lpmode: cache of the last lpmode result of - * omap4_dpll_lpmode_recalc() - * @max_multiplier: maximum valid non-bypass multiplier value (actual) - * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() - * @min_divider: minimum valid non-bypass divider value (actual) - * @max_divider: maximum valid non-bypass divider value (actual) - * @modes: possible values of @enable_mask - * @autoidle_reg: register containing the DPLL autoidle mode bitfield - * @idlest_reg: register containing the DPLL idle status bitfield - * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg - * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg - * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg - * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg - * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg - * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg - * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs - * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs - * @flags: DPLL type/features (see below) - * - * Possible values for @flags: - * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) - * - * @freqsel_mask is only used on the OMAP34xx family and AM35xx. - * - * XXX Some DPLLs have multiple bypass inputs, so it's not technically - * correct to only have one @clk_bypass pointer. - * - * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, - * @last_rounded_n) should be separated from the runtime-fixed fields - * and placed into a different structure, so that the runtime-fixed data - * can be placed into read-only space. - */ -struct dpll_data { - void __iomem *mult_div1_reg; - u32 mult_mask; - u32 div1_mask; - struct clk *clk_bypass; - struct clk *clk_ref; - void __iomem *control_reg; - u32 enable_mask; - unsigned long last_rounded_rate; - u16 last_rounded_m; - u8 last_rounded_m4xen; - u8 last_rounded_lpmode; - u16 max_multiplier; - u8 last_rounded_n; - u8 min_divider; - u16 max_divider; - u8 modes; - void __iomem *autoidle_reg; - void __iomem *idlest_reg; - u32 autoidle_mask; - u32 freqsel_mask; - u32 idlest_mask; - u32 dco_mask; - u32 sddiv_mask; - u32 lpmode_mask; - u32 m4xen_mask; - u8 auto_recal_bit; - u8 recal_en_bit; - u8 recal_st_bit; - u8 flags; -}; - -/* - * struct clk.flags possibilities - * - * XXX document the rest of the clock flags here - * - * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL - * bits share the same register. This flag allows the - * omap4_dpllmx*() code to determine which GATE_CTRL bit field - * should be used. This is a temporary solution - a better approach - * would be to associate clock type-specific data with the clock, - * similar to the struct dpll_data approach. - */ -#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ -#define CLOCK_IDLE_CONTROL (1 << 1) -#define CLOCK_NO_IDLE_PARENT (1 << 2) -#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ -#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ -#define CLOCK_CLKOUTX2 (1 << 5) - -/** - * struct clk_hw_omap - OMAP struct clk - * @node: list_head connecting this clock into the full clock list - * @enable_reg: register to write to enable the clock (see @enable_bit) - * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) - * @flags: see "struct clk.flags possibilities" above - * @clksel_reg: for clksel clks, register va containing src/divisor select - * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector - * @clksel: for clksel clks, pointer to struct clksel for this clock - * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock - * @clkdm_name: clockdomain name that this clock is contained in - * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime - * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) - * @src_offset: bitshift for source selection bitfield (OMAP1 only) - * - * XXX @rate_offset, @src_offset should probably be removed and OMAP1 - * clock code converted to use clksel. - * - */ - -struct clk_hw_omap_ops; - -struct clk_hw_omap { - struct clk_hw hw; - struct list_head node; - unsigned long fixed_rate; - u8 fixed_div; - void __iomem *enable_reg; - u8 enable_bit; - u8 flags; - void __iomem *clksel_reg; - u32 clksel_mask; - const struct clksel *clksel; - struct dpll_data *dpll_data; - const char *clkdm_name; - struct clockdomain *clkdm; - const struct clk_hw_omap_ops *ops; -}; - struct clk_hw_omap_ops { void (*find_idlest)(struct clk_hw_omap *oclk, void __iomem **idlest_reg, @@ -348,36 +213,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 #define OMAP4XXX_EN_DPLL_LOCKED 0x7 -/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ -#define DPLL_LOW_POWER_STOP 0x1 -#define DPLL_LOW_POWER_BYPASS 0x5 -#define DPLL_LOCKED 0x7 - -/* DPLL Type and DCO Selection Flags */ -#define DPLL_J_TYPE 0x1 - -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, - unsigned long *parent_rate); -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); -int omap3_noncore_dpll_enable(struct clk_hw *hw); -void omap3_noncore_dpll_disable(struct clk_hw *hw); -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate); u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); void omap3_dpll_allow_idle(struct clk_hw_omap *clk); void omap3_dpll_deny_idle(struct clk_hw_omap *clk); -unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, - unsigned long parent_rate); int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk); void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); -unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, - unsigned long parent_rate); -long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, - unsigned long target_rate, - unsigned long *parent_rate); -void omap2_init_clk_clkdm(struct clk_hw *clk); void __init omap2_clk_disable_clkdm_control(void); /* clkt_clksel.c public functions */ @@ -396,29 +238,25 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); -u8 omap2_init_dpll_parent(struct clk_hw *hw); unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); -int omap2_dflt_clk_enable(struct clk_hw *hw); -void omap2_dflt_clk_disable(struct clk_hw *hw); -int omap2_dflt_clk_is_enabled(struct clk_hw *hw); void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, void __iomem **other_reg, u8 *other_bit); void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val); -void omap2_init_clk_hw_omap_clocks(struct clk *clk); int omap2_clk_enable_autoidle_all(void); -int omap2_clk_disable_autoidle_all(void); int omap2_clk_allow_idle(struct clk *clk); int omap2_clk_deny_idle(struct clk *clk); -void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, const char *mpu_ck_name); +u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg); +void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg); + extern u16 cpu_mask; extern const struct clkops clkops_omap2_dflt_wait; @@ -433,19 +271,12 @@ extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; extern struct clk dummy_ck; -extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; extern const struct clk_hw_omap_ops clkhwops_wait; -extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; -extern const struct clk_hw_omap_ops clkhwops_iclk; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait; extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; -extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; extern const struct clk_hw_omap_ops clkhwops_apll54; extern const struct clk_hw_omap_ops clkhwops_apll96; extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; @@ -460,6 +291,8 @@ extern const struct clksel_rate div_1_3_rates[]; extern const struct clksel_rate div_1_4_rates[]; extern const struct clksel_rate div31_1to31_rates[]; +extern void __iomem *clk_memmaps[]; + extern int am33xx_clk_init(void); extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c index bbd6a3f717e6..91ccb962e09e 100644 --- a/arch/arm/mach-omap2/clock36xx.c +++ b/arch/arm/mach-omap2/clock36xx.c @@ -43,6 +43,7 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) struct clk_divider *parent; struct clk_hw *parent_hw; u32 dummy_v, orig_v; + struct clk_hw_omap *omap_clk = to_clk_hw_omap(clk); int ret; /* Clear PWRDN bit of HSDIVIDER */ @@ -53,15 +54,15 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) /* Restore the dividers */ if (!ret) { - orig_v = __raw_readl(parent->reg); + orig_v = omap2_clk_readl(omap_clk, parent->reg); dummy_v = orig_v; /* Write any other value different from the Read value */ dummy_v ^= (1 << parent->shift); - __raw_writel(dummy_v, parent->reg); + omap2_clk_writel(dummy_v, omap_clk, parent->reg); /* Write the original divider */ - __raw_writel(orig_v, parent->reg); + omap2_clk_writel(orig_v, omap_clk, parent->reg); } return ret; diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h index 8cd4b0a882ae..78d9f562e3ce 100644 --- a/arch/arm/mach-omap2/clock3xxx.h +++ b/arch/arm/mach-omap2/clock3xxx.h @@ -9,11 +9,8 @@ #define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H int omap3xxx_clk_init(void); -int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, - unsigned long parent_rate); int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); -void omap3_clk_lock_dpll5(void); extern struct clk *sdrc_ick_p; extern struct clk *arm_fck_p; diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h index 72bb41b3fd25..f338177e6900 100644 --- a/arch/arm/mach-omap2/common-board-devices.h +++ b/arch/arm/mach-omap2/common-board-devices.h @@ -10,5 +10,6 @@ struct ads7846_platform_data; void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce, struct ads7846_platform_data *board_pdata); +void *n8x0_legacy_init(void); #endif /* __OMAP_COMMON_BOARD_DEVICES__ */ diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index e30ef6797c63..e51527835160 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -293,6 +293,7 @@ static inline void omap4_cpu_resume(void) #endif void pdata_quirks_init(struct of_device_id *); +void omap_auxdata_legacy_init(struct device *dev); void omap_pcs_legacy_init(int irq, void (*rearm)(void)); struct omap_sdrc_params; @@ -305,7 +306,7 @@ struct omap_hwmod; extern int omap_dss_reset(struct omap_hwmod *); /* SoC specific clock initializer */ -extern int (*omap_clk_init)(void); +int omap_clk_init(void); #endif /* __ASSEMBLER__ */ #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 3a0296cfcace..3185ced807c9 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -50,10 +50,10 @@ static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) dd = clk->dpll_data; - v = __raw_readl(dd->control_reg); + v = omap2_clk_readl(clk, dd->control_reg); v &= ~dd->enable_mask; v |= clken_bits << __ffs(dd->enable_mask); - __raw_writel(v, dd->control_reg); + omap2_clk_writel(v, clk, dd->control_reg); } /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ @@ -69,8 +69,8 @@ static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) state <<= __ffs(dd->idlest_mask); - while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && - i < MAX_DPLL_WAIT_TRIES) { + while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) + != state) && i < MAX_DPLL_WAIT_TRIES) { i++; udelay(1); } @@ -147,7 +147,7 @@ static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) state <<= __ffs(dd->idlest_mask); /* Check if already locked */ - if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state) + if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state) goto done; ai = omap3_dpll_autoidle_read(clk); @@ -311,14 +311,14 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) * only since freqsel field is no longer present on other devices. */ if (cpu_is_omap343x()) { - v = __raw_readl(dd->control_reg); + v = omap2_clk_readl(clk, dd->control_reg); v &= ~dd->freqsel_mask; v |= freqsel << __ffs(dd->freqsel_mask); - __raw_writel(v, dd->control_reg); + omap2_clk_writel(v, clk, dd->control_reg); } /* Set DPLL multiplier, divider */ - v = __raw_readl(dd->mult_div1_reg); + v = omap2_clk_readl(clk, dd->mult_div1_reg); v &= ~(dd->mult_mask | dd->div1_mask); v |= dd->last_rounded_m << __ffs(dd->mult_mask); v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask); @@ -336,11 +336,11 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) v |= sd_div << __ffs(dd->sddiv_mask); } - __raw_writel(v, dd->mult_div1_reg); + omap2_clk_writel(v, clk, dd->mult_div1_reg); /* Set 4X multiplier and low-power mode */ if (dd->m4xen_mask || dd->lpmode_mask) { - v = __raw_readl(dd->control_reg); + v = omap2_clk_readl(clk, dd->control_reg); if (dd->m4xen_mask) { if (dd->last_rounded_m4xen) @@ -356,7 +356,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) v &= ~dd->lpmode_mask; } - __raw_writel(v, dd->control_reg); + omap2_clk_writel(v, clk, dd->control_reg); } /* We let the clock framework set the other output dividers later */ @@ -554,7 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) if (!dd->autoidle_reg) return -EINVAL; - v = __raw_readl(dd->autoidle_reg); + v = omap2_clk_readl(clk, dd->autoidle_reg); v &= dd->autoidle_mask; v >>= __ffs(dd->autoidle_mask); @@ -588,10 +588,10 @@ void omap3_dpll_allow_idle(struct clk_hw_omap *clk) * by writing 0x5 instead of 0x1. Add some mechanism to * optionally enter this mode. */ - v = __raw_readl(dd->autoidle_reg); + v = omap2_clk_readl(clk, dd->autoidle_reg); v &= ~dd->autoidle_mask; v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); - __raw_writel(v, dd->autoidle_reg); + omap2_clk_writel(v, clk, dd->autoidle_reg); } @@ -614,10 +614,10 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk) if (!dd->autoidle_reg) return; - v = __raw_readl(dd->autoidle_reg); + v = omap2_clk_readl(clk, dd->autoidle_reg); v &= ~dd->autoidle_mask; v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); - __raw_writel(v, dd->autoidle_reg); + omap2_clk_writel(v, clk, dd->autoidle_reg); } @@ -639,6 +639,9 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, struct clk_hw_omap *pclk = NULL; struct clk *parent; + if (!parent_rate) + return 0; + /* Walk up the parents of clk, looking for a DPLL */ do { do { @@ -660,7 +663,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, WARN_ON(!dd->enable_mask); - v = __raw_readl(dd->control_reg) & dd->enable_mask; + v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask; v >>= __ffs(dd->enable_mask); if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) rate = parent_rate; diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index d28b0f726715..52f9438b92f2 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -42,7 +42,7 @@ int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; - v = __raw_readl(clk->clksel_reg); + v = omap2_clk_readl(clk, clk->clksel_reg); v &= mask; v >>= __ffs(mask); @@ -61,10 +61,10 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; - v = __raw_readl(clk->clksel_reg); + v = omap2_clk_readl(clk, clk->clksel_reg); /* Clear the bit to allow gatectrl */ v &= ~mask; - __raw_writel(v, clk->clksel_reg); + omap2_clk_writel(v, clk, clk->clksel_reg); } void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) @@ -79,10 +79,10 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; - v = __raw_readl(clk->clksel_reg); + v = omap2_clk_readl(clk, clk->clksel_reg); /* Set the bit to deny gatectrl */ v |= mask; - __raw_writel(v, clk->clksel_reg); + omap2_clk_writel(v, clk, clk->clksel_reg); } const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { @@ -140,7 +140,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, rate = omap2_get_dpll_rate(clk); /* regm4xen adds a multiplier of 4 to DPLL calculations */ - v = __raw_readl(dd->control_reg); + v = omap2_clk_readl(clk, dd->control_reg); if (v & OMAP4430_DPLL_REGM4XEN_MASK) rate *= OMAP4430_REGM4XEN_MULT; diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 662c7fd633cc..174caecc3186 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -65,6 +65,22 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) return 1; } +/* This function will go away once the device-tree convertion is complete */ +static void gpmc_set_legacy(struct omap_nand_platform_data *gpmc_nand_data, + struct gpmc_settings *s) +{ + /* Enable RD PIN Monitoring Reg */ + if (gpmc_nand_data->dev_ready) { + s->wait_on_read = true; + s->wait_on_write = true; + } + + if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) + s->device_width = GPMC_DEVWIDTH_16BIT; + else + s->device_width = GPMC_DEVWIDTH_8BIT; +} + int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, struct gpmc_timings *gpmc_t) { @@ -98,32 +114,22 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, dev_err(dev, "Unable to set gpmc timings: %d\n", err); return err; } + } - if (gpmc_nand_data->of_node) { - gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); - } else { - /* Enable RD PIN Monitoring Reg */ - if (gpmc_nand_data->dev_ready) { - s.wait_on_read = true; - s.wait_on_write = true; - } - } - - s.device_nand = true; + if (gpmc_nand_data->of_node) + gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); + else + gpmc_set_legacy(gpmc_nand_data, &s); - if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) - s.device_width = GPMC_DEVWIDTH_16BIT; - else - s.device_width = GPMC_DEVWIDTH_8BIT; + s.device_nand = true; - err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); - if (err < 0) - goto out_free_cs; + err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); + if (err < 0) + goto out_free_cs; - err = gpmc_configure(GPMC_CONFIG_WP, 0); - if (err < 0) - goto out_free_cs; - } + err = gpmc_configure(GPMC_CONFIG_WP, 0); + if (err < 0) + goto out_free_cs; gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index cd22262a2cc0..47381fd8746f 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -55,10 +55,10 @@ #include "prm44xx.h" /* - * omap_clk_init: points to a function that does the SoC-specific + * omap_clk_soc_init: points to a function that does the SoC-specific * clock initializations */ -int (*omap_clk_init)(void); +static int (*omap_clk_soc_init)(void); /* * The machine specific code may provide the extra mapping besides the @@ -244,7 +244,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = { .virtual = OMAP4_SRAM_VA, .pfn = __phys_to_pfn(OMAP4_SRAM_PA), .length = PAGE_SIZE, - .type = MT_MEMORY_SO, + .type = MT_MEMORY_RW_SO, }, #endif @@ -282,7 +282,7 @@ static struct map_desc omap54xx_io_desc[] __initdata = { .virtual = OMAP4_SRAM_VA, .pfn = __phys_to_pfn(OMAP4_SRAM_PA), .length = PAGE_SIZE, - .type = MT_MEMORY_SO, + .type = MT_MEMORY_RW_SO, }, #endif }; @@ -419,7 +419,7 @@ void __init omap2420_init_early(void) omap242x_clockdomains_init(); omap2420_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_init = omap2420_clk_init; + omap_clk_soc_init = omap2420_clk_init; } void __init omap2420_init_late(void) @@ -448,7 +448,7 @@ void __init omap2430_init_early(void) omap243x_clockdomains_init(); omap2430_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_init = omap2430_clk_init; + omap_clk_soc_init = omap2430_clk_init; } void __init omap2430_init_late(void) @@ -482,27 +482,35 @@ void __init omap3_init_early(void) omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_init = omap3xxx_clk_init; + omap_clk_soc_init = omap3xxx_clk_init; } void __init omap3430_init_early(void) { omap3_init_early(); + if (of_have_populated_dt()) + omap_clk_soc_init = omap3430_dt_clk_init; } void __init omap35xx_init_early(void) { omap3_init_early(); + if (of_have_populated_dt()) + omap_clk_soc_init = omap3430_dt_clk_init; } void __init omap3630_init_early(void) { omap3_init_early(); + if (of_have_populated_dt()) + omap_clk_soc_init = omap3630_dt_clk_init; } void __init am35xx_init_early(void) { omap3_init_early(); + if (of_have_populated_dt()) + omap_clk_soc_init = am35xx_dt_clk_init; } void __init ti81xx_init_early(void) @@ -520,7 +528,10 @@ void __init ti81xx_init_early(void) omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_init = omap3xxx_clk_init; + if (of_have_populated_dt()) + omap_clk_soc_init = ti81xx_dt_clk_init; + else + omap_clk_soc_init = omap3xxx_clk_init; } void __init omap3_init_late(void) @@ -581,7 +592,7 @@ void __init am33xx_init_early(void) am33xx_clockdomains_init(); am33xx_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_init = am33xx_clk_init; + omap_clk_soc_init = am33xx_dt_clk_init; } void __init am33xx_init_late(void) @@ -606,6 +617,7 @@ void __init am43xx_init_early(void) am43xx_clockdomains_init(); am43xx_hwmod_init(); omap_hwmod_init_postsetup(); + omap_clk_soc_init = am43xx_dt_clk_init; } void __init am43xx_init_late(void) @@ -635,7 +647,7 @@ void __init omap4430_init_early(void) omap44xx_clockdomains_init(); omap44xx_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_init = omap4xxx_clk_init; + omap_clk_soc_init = omap4xxx_dt_clk_init; } void __init omap4430_init_late(void) @@ -666,6 +678,7 @@ void __init omap5_init_early(void) omap54xx_clockdomains_init(); omap54xx_hwmod_init(); omap_hwmod_init_postsetup(); + omap_clk_soc_init = omap5xxx_dt_clk_init; } void __init omap5_init_late(void) @@ -691,6 +704,7 @@ void __init dra7xx_init_early(void) dra7xx_clockdomains_init(); dra7xx_hwmod_init(); omap_hwmod_init_postsetup(); + omap_clk_soc_init = dra7xx_dt_clk_init; } void __init dra7xx_init_late(void) @@ -710,3 +724,17 @@ void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, _omap2_init_reprogram_sdrc(); } } + +int __init omap_clk_init(void) +{ + int ret = 0; + + if (!omap_clk_soc_init) + return 0; + + ret = of_prcm_init(); + if (!ret) + ret = omap_clk_soc_init(); + + return ret; +} diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c index c52d8b4a3e91..828e0db3d943 100644 --- a/arch/arm/mach-omap2/msdi.c +++ b/arch/arm/mach-omap2/msdi.c @@ -88,72 +88,3 @@ int omap_msdi_reset(struct omap_hwmod *oh) return 0; } - -#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) - -static inline void omap242x_mmc_mux(struct omap_mmc_platform_data - *mmc_controller) -{ - if ((mmc_controller->slots[0].switch_pin > 0) && \ - (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) - omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, - OMAP_PIN_INPUT_PULLUP); - if ((mmc_controller->slots[0].gpio_wp > 0) && \ - (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) - omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, - OMAP_PIN_INPUT_PULLUP); - - omap_mux_init_signal("sdmmc_cmd", 0); - omap_mux_init_signal("sdmmc_clki", 0); - omap_mux_init_signal("sdmmc_clko", 0); - omap_mux_init_signal("sdmmc_dat0", 0); - omap_mux_init_signal("sdmmc_dat_dir0", 0); - omap_mux_init_signal("sdmmc_cmd_dir", 0); - if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { - omap_mux_init_signal("sdmmc_dat1", 0); - omap_mux_init_signal("sdmmc_dat2", 0); - omap_mux_init_signal("sdmmc_dat3", 0); - omap_mux_init_signal("sdmmc_dat_dir1", 0); - omap_mux_init_signal("sdmmc_dat_dir2", 0); - omap_mux_init_signal("sdmmc_dat_dir3", 0); - } - - /* - * Use internal loop-back in MMC/SDIO Module Input Clock - * selection - */ - if (mmc_controller->slots[0].internal_clock) { - u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); - v |= (1 << 24); - omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); - } -} - -void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) -{ - struct platform_device *pdev; - struct omap_hwmod *oh; - int id = 0; - char *oh_name = "msdi1"; - char *dev_name = "mmci-omap"; - - if (!mmc_data[0]) { - pr_err("%s fails: Incomplete platform data\n", __func__); - return; - } - - omap242x_mmc_mux(mmc_data[0]); - - oh = omap_hwmod_lookup(oh_name); - if (!oh) { - pr_err("Could not look up %s\n", oh_name); - return; - } - pdev = omap_device_build(dev_name, id, oh, mmc_data[0], - sizeof(struct omap_mmc_platform_data)); - if (IS_ERR(pdev)) - WARN(1, "Can'd build omap_device for %s:%s.\n", - dev_name, oh->name); -} - -#endif diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index 16f78a990d04..a722330d4d53 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h @@ -7,8 +7,6 @@ * published by the Free Software Foundation. */ -#include "mux2420.h" -#include "mux2430.h" #include "mux34xx.h" #define OMAP_MUX_TERMINATOR 0xffff diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c deleted file mode 100644 index cf6de0971c6c..000000000000 --- a/arch/arm/mach-omap2/mux2420.c +++ /dev/null @@ -1,690 +0,0 @@ -/* - * Copyright (C) 2010 Nokia - * Copyright (C) 2010 Texas Instruments - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/module.h> -#include <linux/init.h> - -#include "mux.h" - -#ifdef CONFIG_OMAP_MUX - -#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ -{ \ - .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \ - .gpio = (g), \ - .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ -} - -#else - -#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ -{ \ - .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \ - .gpio = (g), \ -} - -#endif - -#define _OMAP2420_BALLENTRY(M0, bb, bt) \ -{ \ - .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \ - .balls = { bb, bt }, \ -} - -/* - * Superset of all mux modes for omap2420 - */ -static struct omap_mux __initdata omap2420_muxmodes[] = { - _OMAP2420_MUXENTRY(CAM_D0, 54, - "cam_d0", "hw_dbg2", "sti_dout", "gpio_54", - NULL, NULL, "etk_d2", NULL), - _OMAP2420_MUXENTRY(CAM_D1, 53, - "cam_d1", "hw_dbg3", "sti_din", "gpio_53", - NULL, NULL, "etk_d3", NULL), - _OMAP2420_MUXENTRY(CAM_D2, 52, - "cam_d2", "hw_dbg4", "mcbsp1_clkx", "gpio_52", - NULL, NULL, "etk_d4", NULL), - _OMAP2420_MUXENTRY(CAM_D3, 51, - "cam_d3", "hw_dbg5", "mcbsp1_dr", "gpio_51", - NULL, NULL, "etk_d5", NULL), - _OMAP2420_MUXENTRY(CAM_D4, 50, - "cam_d4", "hw_dbg6", "mcbsp1_fsr", "gpio_50", - NULL, NULL, "etk_d6", NULL), - _OMAP2420_MUXENTRY(CAM_D5, 49, - "cam_d5", "hw_dbg7", "mcbsp1_clkr", "gpio_49", - NULL, NULL, "etk_d7", NULL), - _OMAP2420_MUXENTRY(CAM_D6, 0, - "cam_d6", "hw_dbg8", NULL, NULL, - NULL, NULL, "etk_d8", NULL), - _OMAP2420_MUXENTRY(CAM_D7, 0, - "cam_d7", "hw_dbg9", NULL, NULL, - NULL, NULL, "etk_d9", NULL), - _OMAP2420_MUXENTRY(CAM_D8, 54, - "cam_d8", "hw_dbg10", NULL, "gpio_54", - NULL, NULL, "etk_d10", NULL), - _OMAP2420_MUXENTRY(CAM_D9, 53, - "cam_d9", "hw_dbg11", NULL, "gpio_53", - NULL, NULL, "etk_d11", NULL), - _OMAP2420_MUXENTRY(CAM_HS, 55, - "cam_hs", "hw_dbg1", "mcbsp1_dx", "gpio_55", - NULL, NULL, "etk_d1", NULL), - _OMAP2420_MUXENTRY(CAM_LCLK, 57, - "cam_lclk", NULL, "mcbsp_clks", "gpio_57", - NULL, NULL, "etk_c1", NULL), - _OMAP2420_MUXENTRY(CAM_VS, 56, - "cam_vs", "hw_dbg0", "mcbsp1_fsx", "gpio_56", - NULL, NULL, "etk_d0", NULL), - _OMAP2420_MUXENTRY(CAM_XCLK, 0, - "cam_xclk", NULL, "sti_clk", NULL, - NULL, NULL, "etk_c2", NULL), - _OMAP2420_MUXENTRY(DSS_ACBIAS, 48, - "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA10, 40, - "dss_data10", NULL, NULL, "gpio_40", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA11, 41, - "dss_data11", NULL, NULL, "gpio_41", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA12, 42, - "dss_data12", NULL, NULL, "gpio_42", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA13, 43, - "dss_data13", NULL, NULL, "gpio_43", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA14, 44, - "dss_data14", NULL, NULL, "gpio_44", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA15, 45, - "dss_data15", NULL, NULL, "gpio_45", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA16, 46, - "dss_data16", NULL, NULL, "gpio_46", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA17, 47, - "dss_data17", NULL, NULL, "gpio_47", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA8, 38, - "dss_data8", NULL, NULL, "gpio_38", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA9, 39, - "dss_data9", NULL, NULL, "gpio_39", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(EAC_AC_DIN, 115, - "eac_ac_din", "mcbsp2_dr", NULL, "gpio_115", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(EAC_AC_DOUT, 116, - "eac_ac_dout", "mcbsp2_dx", NULL, "gpio_116", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(EAC_AC_FS, 114, - "eac_ac_fs", "mcbsp2_fsx", NULL, "gpio_114", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(EAC_AC_MCLK, 117, - "eac_ac_mclk", NULL, NULL, "gpio_117", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(EAC_AC_RST, 118, - "eac_ac_rst", "eac_bt_din", NULL, "gpio_118", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(EAC_AC_SCLK, 113, - "eac_ac_sclk", "mcbsp2_clkx", NULL, "gpio_113", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(EAC_BT_DIN, 73, - "eac_bt_din", NULL, NULL, "gpio_73", - NULL, NULL, "etk_d9", NULL), - _OMAP2420_MUXENTRY(EAC_BT_DOUT, 74, - "eac_bt_dout", NULL, "sti_clk", "gpio_74", - NULL, NULL, "etk_d8", NULL), - _OMAP2420_MUXENTRY(EAC_BT_FS, 72, - "eac_bt_fs", NULL, NULL, "gpio_72", - NULL, NULL, "etk_d10", NULL), - _OMAP2420_MUXENTRY(EAC_BT_SCLK, 71, - "eac_bt_sclk", NULL, NULL, "gpio_71", - NULL, NULL, "etk_d11", NULL), - _OMAP2420_MUXENTRY(GPIO_119, 119, - "gpio_119", NULL, "sti_din", "gpio_119", - NULL, "sys_boot0", "etk_d12", NULL), - _OMAP2420_MUXENTRY(GPIO_120, 120, - "gpio_120", NULL, "sti_dout", "gpio_120", - "cam_d9", "sys_boot1", "etk_d13", NULL), - _OMAP2420_MUXENTRY(GPIO_121, 121, - "gpio_121", NULL, NULL, "gpio_121", - "jtag_emu2", "sys_boot2", "etk_d14", NULL), - _OMAP2420_MUXENTRY(GPIO_122, 122, - "gpio_122", NULL, NULL, "gpio_122", - "jtag_emu3", "sys_boot3", "etk_d15", NULL), - _OMAP2420_MUXENTRY(GPIO_124, 124, - "gpio_124", NULL, NULL, "gpio_124", - NULL, "sys_boot5", NULL, NULL), - _OMAP2420_MUXENTRY(GPIO_125, 125, - "gpio_125", "sys_jtagsel1", "sys_jtagsel2", "gpio_125", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPIO_36, 36, - "gpio_36", NULL, NULL, "gpio_36", - NULL, "sys_boot4", NULL, NULL), - _OMAP2420_MUXENTRY(GPIO_62, 62, - "gpio_62", "uart1_rx", "usb1_dat", "gpio_62", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPIO_6, 6, - "gpio_6", "tv_detpulse", NULL, "gpio_6", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A10, 3, - "gpmc_a10", NULL, "sys_ndmareq5", "gpio_3", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A1, 12, - "gpmc_a1", "dss_data18", NULL, "gpio_12", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A2, 11, - "gpmc_a2", "dss_data19", NULL, "gpio_11", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A3, 10, - "gpmc_a3", "dss_data20", NULL, "gpio_10", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A4, 9, - "gpmc_a4", "dss_data21", NULL, "gpio_9", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A5, 8, - "gpmc_a5", "dss_data22", NULL, "gpio_8", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A6, 7, - "gpmc_a6", "dss_data23", NULL, "gpio_7", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A7, 6, - "gpmc_a7", NULL, "sys_ndmareq2", "gpio_6", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A8, 5, - "gpmc_a8", NULL, "sys_ndmareq3", "gpio_5", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A9, 4, - "gpmc_a9", NULL, "sys_ndmareq4", "gpio_4", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_CLK, 21, - "gpmc_clk", NULL, NULL, "gpio_21", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D10, 18, - "gpmc_d10", "ssi2_rdy_rx", NULL, "gpio_18", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D11, 17, - "gpmc_d11", "ssi2_flag_rx", NULL, "gpio_17", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D12, 16, - "gpmc_d12", "ssi2_dat_rx", NULL, "gpio_16", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D13, 15, - "gpmc_d13", "ssi2_rdy_tx", NULL, "gpio_15", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D14, 14, - "gpmc_d14", "ssi2_flag_tx", NULL, "gpio_14", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D15, 13, - "gpmc_d15", "ssi2_dat_tx", NULL, "gpio_13", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D8, 20, - "gpmc_d8", NULL, NULL, "gpio_20", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D9, 19, - "gpmc_d9", "ssi2_wake", NULL, "gpio_19", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NBE0, 29, - "gpmc_nbe0", NULL, NULL, "gpio_29", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NBE1, 30, - "gpmc_nbe1", NULL, NULL, "gpio_30", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NCS1, 22, - "gpmc_ncs1", NULL, NULL, "gpio_22", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NCS2, 23, - "gpmc_ncs2", NULL, NULL, "gpio_23", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NCS3, 24, - "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NCS4, 25, - "gpmc_ncs4", NULL, NULL, "gpio_25", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NCS5, 26, - "gpmc_ncs5", NULL, NULL, "gpio_26", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NCS6, 27, - "gpmc_ncs6", NULL, NULL, "gpio_27", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NCS7, 28, - "gpmc_ncs7", "gpmc_io_dir", "gpio_28", NULL, - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NWP, 31, - "gpmc_nwp", NULL, NULL, "gpio_31", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_WAIT1, 33, - "gpmc_wait1", NULL, NULL, "gpio_33", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_WAIT2, 34, - "gpmc_wait2", NULL, NULL, "gpio_34", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_WAIT3, 35, - "gpmc_wait3", NULL, NULL, "gpio_35", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(HDQ_SIO, 101, - "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(I2C2_SCL, 99, - "i2c2_scl", NULL, "gpt9_pwm_evt", "gpio_99", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(I2C2_SDA, 100, - "i2c2_sda", NULL, "spi2_ncs1", "gpio_100", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(JTAG_EMU0, 127, - "jtag_emu0", NULL, NULL, "gpio_127", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(JTAG_EMU1, 126, - "jtag_emu1", NULL, NULL, "gpio_126", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP1_CLKR, 92, - "mcbsp1_clkr", "ssi2_dat_tx", "vlynq_tx1", "gpio_92", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP1_CLKX, 98, - "mcbsp1_clkx", "ssi2_wake", "vlynq_nla", "gpio_98", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP1_DR, 95, - "mcbsp1_dr", "ssi2_dat_rx", "vlynq_rx1", "gpio_95", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP1_DX, 94, - "mcbsp1_dx", "ssi2_rdy_tx", "vlynq_clk", "gpio_94", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP1_FSR, 93, - "mcbsp1_fsr", "ssi2_flag_tx", "vlynq_tx0", "gpio_93", - "spi2_ncs1", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP1_FSX, 97, - "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP2_CLKX, 12, - "mcbsp2_clkx", NULL, "dss_data23", "gpio_12", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP2_DR, 11, - "mcbsp2_dr", NULL, "dss_data22", "gpio_11", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP_CLKS, 96, - "mcbsp_clks", "ssi2_flag_rx", "vlynq_rx0", "gpio_96", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_CLKI, 59, - "sdmmc_clki", "ms_clki", NULL, "gpio_59", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_CLKO, 0, - "sdmmc_clko", "ms_clko", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_CMD_DIR, 8, - "sdmmc_cmd_dir", NULL, NULL, "gpio_8", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_CMD, 0, - "sdmmc_cmd", "ms_bs", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT_DIR0, 7, - "sdmmc_dat_dir0", "ms_dat0_dir", NULL, "gpio_7", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT0, 0, - "sdmmc_dat0", "ms_dat0", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT_DIR1, 78, - "sdmmc_dat_dir1", "ms_datu_dir", "uart2_rts", "gpio_78", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT1, 75, - "sdmmc_dat1", "ms_dat1", NULL, "gpio_75", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT_DIR2, 79, - "sdmmc_dat_dir2", "ms_datu_dir", "uart2_tx", "gpio_79", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT2, 76, - "sdmmc_dat2", "ms_dat2", "uart2_cts", "gpio_76", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT_DIR3, 80, - "sdmmc_dat_dir3", "ms_datu_dir", "uart2_rx", "gpio_80", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT3, 77, - "sdmmc_dat3", "ms_dat3", NULL, "gpio_77", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SDRC_A12, 2, - "sdrc_a12", NULL, NULL, "gpio_2", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SDRC_A13, 1, - "sdrc_a13", NULL, NULL, "gpio_1", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SDRC_A14, 0, - "sdrc_a14", NULL, NULL, "gpio_0", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SDRC_CKE1, 38, - "sdrc_cke1", NULL, NULL, "gpio_38", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SDRC_NCS1, 37, - "sdrc_ncs1", NULL, NULL, "gpio_37", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI1_CLK, 81, - "spi1_clk", NULL, NULL, "gpio_81", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI1_NCS0, 84, - "spi1_ncs0", NULL, NULL, "gpio_84", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI1_NCS1, 85, - "spi1_ncs1", NULL, NULL, "gpio_85", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI1_NCS2, 86, - "spi1_ncs2", NULL, NULL, "gpio_86", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI1_NCS3, 87, - "spi1_ncs3", NULL, NULL, "gpio_87", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI1_SIMO, 82, - "spi1_simo", NULL, NULL, "gpio_82", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI1_SOMI, 83, - "spi1_somi", NULL, NULL, "gpio_83", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI2_CLK, 88, - "spi2_clk", NULL, NULL, "gpio_88", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI2_NCS0, 91, - "spi2_ncs0", "gpt12_pwm_evt", NULL, "gpio_91", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI2_SIMO, 89, - "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI2_SOMI, 90, - "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SSI1_DAT_RX, 63, - "ssi1_dat_rx", "eac_md_sclk", NULL, "gpio_63", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SSI1_DAT_TX, 59, - "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SSI1_FLAG_RX, 64, - "ssi1_flag_rx", "eac_md_din", NULL, "gpio_64", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SSI1_FLAG_TX, 25, - "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_25", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SSI1_RDY_RX, 65, - "ssi1_rdy_rx", "eac_md_dout", NULL, "gpio_65", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SSI1_RDY_TX, 61, - "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SSI1_WAKE, 66, - "ssi1_wake", "eac_md_fs", NULL, "gpio_66", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SYS_CLKOUT, 123, - "sys_clkout", NULL, NULL, "gpio_123", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SYS_CLKREQ, 52, - "sys_clkreq", NULL, NULL, "gpio_52", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SYS_NIRQ, 60, - "sys_nirq", NULL, NULL, "gpio_60", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART1_CTS, 32, - "uart1_cts", NULL, "dss_data18", "gpio_32", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART1_RTS, 8, - "uart1_rts", NULL, "dss_data19", "gpio_8", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART1_RX, 10, - "uart1_rx", NULL, "dss_data21", "gpio_10", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART1_TX, 9, - "uart1_tx", NULL, "dss_data20", "gpio_9", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART2_CTS, 67, - "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART2_RTS, 68, - "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART2_RX, 70, - "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART2_TX, 69, - "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART3_CTS_RCTX, 102, - "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART3_RTS_SD, 103, - "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART3_RX_IRRX, 105, - "uart3_rx_irrx", NULL, NULL, "gpio_105", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART3_TX_IRTX, 104, - "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(USB0_DAT, 112, - "usb0_dat", "uart3_rx_irrx", "uart2_rx", "gpio_112", - "uart2_tx", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(USB0_PUEN, 106, - "usb0_puen", "mcbsp2_dx", NULL, "gpio_106", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(USB0_RCV, 109, - "usb0_rcv", "mcbsp2_fsx", NULL, "gpio_109", - "uart2_cts", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(USB0_SE0, 111, - "usb0_se0", "uart3_tx_irtx", "uart2_tx", "gpio_111", - "uart2_rx", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(USB0_TXEN, 110, - "usb0_txen", "uart3_cts_rctx", "uart2_cts", "gpio_110", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(USB0_VM, 108, - "usb0_vm", "mcbsp2_clkx", NULL, "gpio_108", - "uart2_rx", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(USB0_VP, 107, - "usb0_vp", "mcbsp2_dr", NULL, "gpio_107", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(VLYNQ_CLK, 13, - "vlynq_clk", "usb2_se0", "sys_ndmareq0", "gpio_13", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(VLYNQ_NLA, 58, - "vlynq_nla", NULL, NULL, "gpio_58", - "cam_d6", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(VLYNQ_RX0, 15, - "vlynq_rx0", "usb2_tllse0", NULL, "gpio_15", - "cam_d7", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(VLYNQ_RX1, 14, - "vlynq_rx1", "usb2_rcv", "sys_ndmareq1", "gpio_14", - "cam_d8", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(VLYNQ_TX0, 17, - "vlynq_tx0", "usb2_txen", NULL, "gpio_17", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(VLYNQ_TX1, 16, - "vlynq_tx1", "usb2_dat", "sys_clkout2", "gpio_16", - NULL, NULL, NULL, NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - -/* - * Balls for 447-pin POP package - */ -#ifdef CONFIG_DEBUG_FS -static struct omap_ball __initdata omap2420_pop_ball[] = { - _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL), - _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL), - _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL), - _OMAP2420_BALLENTRY(CAM_D3, "ab3", NULL), - _OMAP2420_BALLENTRY(CAM_D4, "v2", NULL), - _OMAP2420_BALLENTRY(CAM_D5, "ad3", NULL), - _OMAP2420_BALLENTRY(CAM_D6, "aa4", NULL), - _OMAP2420_BALLENTRY(CAM_D7, "ab4", NULL), - _OMAP2420_BALLENTRY(CAM_D8, "ac6", NULL), - _OMAP2420_BALLENTRY(CAM_D9, "ac7", NULL), - _OMAP2420_BALLENTRY(CAM_HS, "v4", NULL), - _OMAP2420_BALLENTRY(CAM_LCLK, "ad6", NULL), - _OMAP2420_BALLENTRY(CAM_VS, "p7", NULL), - _OMAP2420_BALLENTRY(CAM_XCLK, "w4", NULL), - _OMAP2420_BALLENTRY(DSS_ACBIAS, "ae8", NULL), - _OMAP2420_BALLENTRY(DSS_DATA10, "ac12", NULL), - _OMAP2420_BALLENTRY(DSS_DATA11, "ae11", NULL), - _OMAP2420_BALLENTRY(DSS_DATA12, "ae13", NULL), - _OMAP2420_BALLENTRY(DSS_DATA13, "ad13", NULL), - _OMAP2420_BALLENTRY(DSS_DATA14, "ac13", NULL), - _OMAP2420_BALLENTRY(DSS_DATA15, "y12", NULL), - _OMAP2420_BALLENTRY(DSS_DATA16, "ad14", NULL), - _OMAP2420_BALLENTRY(DSS_DATA17, "y13", NULL), - _OMAP2420_BALLENTRY(DSS_DATA8, "ad11", NULL), - _OMAP2420_BALLENTRY(DSS_DATA9, "ad12", NULL), - _OMAP2420_BALLENTRY(EAC_AC_DIN, "ad19", NULL), - _OMAP2420_BALLENTRY(EAC_AC_DOUT, "af22", NULL), - _OMAP2420_BALLENTRY(EAC_AC_FS, "ad16", NULL), - _OMAP2420_BALLENTRY(EAC_AC_MCLK, "y17", NULL), - _OMAP2420_BALLENTRY(EAC_AC_RST, "ae22", NULL), - _OMAP2420_BALLENTRY(EAC_AC_SCLK, "ac18", NULL), - _OMAP2420_BALLENTRY(EAC_BT_DIN, "u8", NULL), - _OMAP2420_BALLENTRY(EAC_BT_DOUT, "ad5", NULL), - _OMAP2420_BALLENTRY(EAC_BT_FS, "w7", NULL), - _OMAP2420_BALLENTRY(EAC_BT_SCLK, "ad4", NULL), - _OMAP2420_BALLENTRY(GPIO_119, "af6", NULL), - _OMAP2420_BALLENTRY(GPIO_120, "af4", NULL), - _OMAP2420_BALLENTRY(GPIO_121, "ae6", NULL), - _OMAP2420_BALLENTRY(GPIO_122, "w3", NULL), - _OMAP2420_BALLENTRY(GPIO_124, "y19", NULL), - _OMAP2420_BALLENTRY(GPIO_125, "ae24", NULL), - _OMAP2420_BALLENTRY(GPIO_36, "y18", NULL), - _OMAP2420_BALLENTRY(GPIO_6, "d6", NULL), - _OMAP2420_BALLENTRY(GPIO_62, "ad18", NULL), - _OMAP2420_BALLENTRY(GPMC_A1, "m8", NULL), - _OMAP2420_BALLENTRY(GPMC_A10, "d5", NULL), - _OMAP2420_BALLENTRY(GPMC_A2, "w9", NULL), - _OMAP2420_BALLENTRY(GPMC_A3, "af10", NULL), - _OMAP2420_BALLENTRY(GPMC_A4, "w8", NULL), - _OMAP2420_BALLENTRY(GPMC_A5, "ae16", NULL), - _OMAP2420_BALLENTRY(GPMC_A6, "af9", NULL), - _OMAP2420_BALLENTRY(GPMC_A7, "e4", NULL), - _OMAP2420_BALLENTRY(GPMC_A8, "j7", NULL), - _OMAP2420_BALLENTRY(GPMC_A9, "ae18", NULL), - _OMAP2420_BALLENTRY(GPMC_CLK, "p1", "l1"), - _OMAP2420_BALLENTRY(GPMC_D10, "t1", "n1"), - _OMAP2420_BALLENTRY(GPMC_D11, "u2", "p2"), - _OMAP2420_BALLENTRY(GPMC_D12, "u1", "p1"), - _OMAP2420_BALLENTRY(GPMC_D13, "p2", "m1"), - _OMAP2420_BALLENTRY(GPMC_D14, "h2", "j2"), - _OMAP2420_BALLENTRY(GPMC_D15, "h1", "k2"), - _OMAP2420_BALLENTRY(GPMC_D8, "v1", "r1"), - _OMAP2420_BALLENTRY(GPMC_D9, "y1", "t1"), - _OMAP2420_BALLENTRY(GPMC_NBE0, "af12", "aa10"), - _OMAP2420_BALLENTRY(GPMC_NBE1, "u3", NULL), - _OMAP2420_BALLENTRY(GPMC_NCS1, "af14", "w1"), - _OMAP2420_BALLENTRY(GPMC_NCS2, "g4", NULL), - _OMAP2420_BALLENTRY(GPMC_NCS3, "t8", NULL), - _OMAP2420_BALLENTRY(GPMC_NCS4, "h8", NULL), - _OMAP2420_BALLENTRY(GPMC_NCS5, "k3", NULL), - _OMAP2420_BALLENTRY(GPMC_NCS6, "m7", NULL), - _OMAP2420_BALLENTRY(GPMC_NCS7, "p3", NULL), - _OMAP2420_BALLENTRY(GPMC_NWP, "ae15", "y5"), - _OMAP2420_BALLENTRY(GPMC_WAIT1, "ae20", "y8"), - _OMAP2420_BALLENTRY(GPMC_WAIT2, "n2", NULL), - _OMAP2420_BALLENTRY(GPMC_WAIT3, "t4", NULL), - _OMAP2420_BALLENTRY(HDQ_SIO, "t23", NULL), - _OMAP2420_BALLENTRY(I2C2_SCL, "l2", NULL), - _OMAP2420_BALLENTRY(I2C2_SDA, "k19", NULL), - _OMAP2420_BALLENTRY(JTAG_EMU0, "n24", NULL), - _OMAP2420_BALLENTRY(JTAG_EMU1, "ac22", NULL), - _OMAP2420_BALLENTRY(MCBSP1_CLKR, "y24", NULL), - _OMAP2420_BALLENTRY(MCBSP1_CLKX, "t19", NULL), - _OMAP2420_BALLENTRY(MCBSP1_DR, "u23", NULL), - _OMAP2420_BALLENTRY(MCBSP1_DX, "r24", NULL), - _OMAP2420_BALLENTRY(MCBSP1_FSR, "r20", NULL), - _OMAP2420_BALLENTRY(MCBSP1_FSX, "r23", NULL), - _OMAP2420_BALLENTRY(MCBSP2_CLKX, "t24", NULL), - _OMAP2420_BALLENTRY(MCBSP2_DR, "p20", NULL), - _OMAP2420_BALLENTRY(MCBSP_CLKS, "p23", NULL), - _OMAP2420_BALLENTRY(MMC_CLKI, "c23", NULL), - _OMAP2420_BALLENTRY(MMC_CLKO, "h23", NULL), - _OMAP2420_BALLENTRY(MMC_CMD, "j23", NULL), - _OMAP2420_BALLENTRY(MMC_CMD_DIR, "j24", NULL), - _OMAP2420_BALLENTRY(MMC_DAT0, "h17", NULL), - _OMAP2420_BALLENTRY(MMC_DAT_DIR0, "f23", NULL), - _OMAP2420_BALLENTRY(MMC_DAT1, "g19", NULL), - _OMAP2420_BALLENTRY(MMC_DAT_DIR1, "d23", NULL), - _OMAP2420_BALLENTRY(MMC_DAT2, "h20", NULL), - _OMAP2420_BALLENTRY(MMC_DAT_DIR2, "g23", NULL), - _OMAP2420_BALLENTRY(MMC_DAT3, "d24", NULL), - _OMAP2420_BALLENTRY(MMC_DAT_DIR3, "e23", NULL), - _OMAP2420_BALLENTRY(SDRC_A12, "w26", "r21"), - _OMAP2420_BALLENTRY(SDRC_A13, "w25", "aa15"), - _OMAP2420_BALLENTRY(SDRC_A14, "aa26", "y12"), - _OMAP2420_BALLENTRY(SDRC_CKE1, "ae25", "y13"), - _OMAP2420_BALLENTRY(SDRC_NCS1, "y25", "t20"), - _OMAP2420_BALLENTRY(SPI1_CLK, "y23", NULL), - _OMAP2420_BALLENTRY(SPI1_NCS0, "w24", NULL), - _OMAP2420_BALLENTRY(SPI1_NCS1, "w23", NULL), - _OMAP2420_BALLENTRY(SPI1_NCS2, "v23", NULL), - _OMAP2420_BALLENTRY(SPI1_NCS3, "u20", NULL), - _OMAP2420_BALLENTRY(SPI1_SIMO, "h10", NULL), - _OMAP2420_BALLENTRY(SPI1_SOMI, "v19", NULL), - _OMAP2420_BALLENTRY(SPI2_CLK, "v24", NULL), - _OMAP2420_BALLENTRY(SPI2_NCS0, "aa24", NULL), - _OMAP2420_BALLENTRY(SPI2_SIMO, "u24", NULL), - _OMAP2420_BALLENTRY(SPI2_SOMI, "v25", NULL), - _OMAP2420_BALLENTRY(SSI1_DAT_RX, "w15", NULL), - _OMAP2420_BALLENTRY(SSI1_DAT_TX, "w13", NULL), - _OMAP2420_BALLENTRY(SSI1_FLAG_RX, "af11", NULL), - _OMAP2420_BALLENTRY(SSI1_FLAG_TX, "ac15", NULL), - _OMAP2420_BALLENTRY(SSI1_RDY_RX, "ac16", NULL), - _OMAP2420_BALLENTRY(SSI1_RDY_TX, "af15", NULL), - _OMAP2420_BALLENTRY(SSI1_WAKE, "ad15", NULL), - _OMAP2420_BALLENTRY(SYS_CLKOUT, "ae19", NULL), - _OMAP2420_BALLENTRY(SYS_CLKREQ, "ad20", NULL), - _OMAP2420_BALLENTRY(SYS_NIRQ, "y20", NULL), - _OMAP2420_BALLENTRY(UART1_CTS, "g20", NULL), - _OMAP2420_BALLENTRY(UART1_RTS, "k20", NULL), - _OMAP2420_BALLENTRY(UART1_RX, "t20", NULL), - _OMAP2420_BALLENTRY(UART1_TX, "h12", NULL), - _OMAP2420_BALLENTRY(UART2_CTS, "ac24", NULL), - _OMAP2420_BALLENTRY(UART2_RTS, "w20", NULL), - _OMAP2420_BALLENTRY(UART2_RX, "ad24", NULL), - _OMAP2420_BALLENTRY(UART2_TX, "ab24", NULL), - _OMAP2420_BALLENTRY(UART3_CTS_RCTX, "k24", NULL), - _OMAP2420_BALLENTRY(UART3_RTS_SD, "m20", NULL), - _OMAP2420_BALLENTRY(UART3_RX_IRRX, "h24", NULL), - _OMAP2420_BALLENTRY(UART3_TX_IRTX, "g24", NULL), - _OMAP2420_BALLENTRY(USB0_DAT, "j25", NULL), - _OMAP2420_BALLENTRY(USB0_PUEN, "l23", NULL), - _OMAP2420_BALLENTRY(USB0_RCV, "k23", NULL), - _OMAP2420_BALLENTRY(USB0_SE0, "l24", NULL), - _OMAP2420_BALLENTRY(USB0_TXEN, "m24", NULL), - _OMAP2420_BALLENTRY(USB0_VM, "n23", NULL), - _OMAP2420_BALLENTRY(USB0_VP, "m23", NULL), - _OMAP2420_BALLENTRY(VLYNQ_CLK, "w12", NULL), - _OMAP2420_BALLENTRY(VLYNQ_NLA, "ae10", NULL), - _OMAP2420_BALLENTRY(VLYNQ_RX0, "ad7", NULL), - _OMAP2420_BALLENTRY(VLYNQ_RX1, "w10", NULL), - _OMAP2420_BALLENTRY(VLYNQ_TX0, "y15", NULL), - _OMAP2420_BALLENTRY(VLYNQ_TX1, "w14", NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define omap2420_pop_ball NULL -#endif - -int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags) -{ - struct omap_ball *package_balls = NULL; - - switch (flags & OMAP_PACKAGE_MASK) { - case OMAP_PACKAGE_ZAC: - package_balls = omap2420_pop_ball; - break; - case OMAP_PACKAGE_ZAF: - /* REVISIT: Please add data */ - default: - pr_warning("%s: No ball data available for omap2420 package\n", - __func__); - } - - return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3, - OMAP2420_CONTROL_PADCONF_MUX_PBASE, - OMAP2420_CONTROL_PADCONF_MUX_SIZE, - omap2420_muxmodes, NULL, board_subset, - package_balls); -} diff --git a/arch/arm/mach-omap2/mux2420.h b/arch/arm/mach-omap2/mux2420.h deleted file mode 100644 index 0f555aa847b5..000000000000 --- a/arch/arm/mach-omap2/mux2420.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright (C) 2009 Nokia - * Copyright (C) 2009 Texas Instruments - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define OMAP2420_CONTROL_PADCONF_MUX_PBASE 0x48000030LU - -#define OMAP2420_MUX(mode0, mux_value) \ -{ \ - .reg_offset = (OMAP2420_CONTROL_PADCONF_##mode0##_OFFSET), \ - .value = (mux_value), \ -} - -/* - * OMAP2420 CONTROL_PADCONF* register offsets for pin-muxing - * - * Extracted from the TRM. Add 0x48000030 to these values to get the - * absolute addresses. The name in the macro is the mode-0 name of - * the pin. NOTE: These registers are 8-bits wide. - */ -#define OMAP2420_CONTROL_PADCONF_SDRC_A14_OFFSET 0x000 -#define OMAP2420_CONTROL_PADCONF_SDRC_A13_OFFSET 0x001 -#define OMAP2420_CONTROL_PADCONF_SDRC_A12_OFFSET 0x002 -#define OMAP2420_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x003 -#define OMAP2420_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x004 -#define OMAP2420_CONTROL_PADCONF_SDRC_A11_OFFSET 0x005 -#define OMAP2420_CONTROL_PADCONF_SDRC_A10_OFFSET 0x006 -#define OMAP2420_CONTROL_PADCONF_SDRC_A9_OFFSET 0x007 -#define OMAP2420_CONTROL_PADCONF_SDRC_A8_OFFSET 0x008 -#define OMAP2420_CONTROL_PADCONF_SDRC_A7_OFFSET 0x009 -#define OMAP2420_CONTROL_PADCONF_SDRC_A6_OFFSET 0x00a -#define OMAP2420_CONTROL_PADCONF_SDRC_A5_OFFSET 0x00b -#define OMAP2420_CONTROL_PADCONF_SDRC_A4_OFFSET 0x00c -#define OMAP2420_CONTROL_PADCONF_SDRC_A3_OFFSET 0x00d -#define OMAP2420_CONTROL_PADCONF_SDRC_A2_OFFSET 0x00e -#define OMAP2420_CONTROL_PADCONF_SDRC_A1_OFFSET 0x00f -#define OMAP2420_CONTROL_PADCONF_SDRC_A0_OFFSET 0x010 -#define OMAP2420_CONTROL_PADCONF_SDRC_D31_OFFSET 0x021 -#define OMAP2420_CONTROL_PADCONF_SDRC_D30_OFFSET 0x022 -#define OMAP2420_CONTROL_PADCONF_SDRC_D29_OFFSET 0x023 -#define OMAP2420_CONTROL_PADCONF_SDRC_D28_OFFSET 0x024 -#define OMAP2420_CONTROL_PADCONF_SDRC_D27_OFFSET 0x025 -#define OMAP2420_CONTROL_PADCONF_SDRC_D26_OFFSET 0x026 -#define OMAP2420_CONTROL_PADCONF_SDRC_D25_OFFSET 0x027 -#define OMAP2420_CONTROL_PADCONF_SDRC_D24_OFFSET 0x028 -#define OMAP2420_CONTROL_PADCONF_SDRC_D23_OFFSET 0x029 -#define OMAP2420_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02a -#define OMAP2420_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02b -#define OMAP2420_CONTROL_PADCONF_SDRC_D20_OFFSET 0x02c -#define OMAP2420_CONTROL_PADCONF_SDRC_D19_OFFSET 0x02d -#define OMAP2420_CONTROL_PADCONF_SDRC_D18_OFFSET 0x02e -#define OMAP2420_CONTROL_PADCONF_SDRC_D17_OFFSET 0x02f -#define OMAP2420_CONTROL_PADCONF_SDRC_D16_OFFSET 0x030 -#define OMAP2420_CONTROL_PADCONF_SDRC_D15_OFFSET 0x031 -#define OMAP2420_CONTROL_PADCONF_SDRC_D14_OFFSET 0x032 -#define OMAP2420_CONTROL_PADCONF_SDRC_D13_OFFSET 0x033 -#define OMAP2420_CONTROL_PADCONF_SDRC_D12_OFFSET 0x034 -#define OMAP2420_CONTROL_PADCONF_SDRC_D11_OFFSET 0x035 -#define OMAP2420_CONTROL_PADCONF_SDRC_D10_OFFSET 0x036 -#define OMAP2420_CONTROL_PADCONF_SDRC_D9_OFFSET 0x037 -#define OMAP2420_CONTROL_PADCONF_SDRC_D8_OFFSET 0x038 -#define OMAP2420_CONTROL_PADCONF_SDRC_D7_OFFSET 0x039 -#define OMAP2420_CONTROL_PADCONF_SDRC_D6_OFFSET 0x03a -#define OMAP2420_CONTROL_PADCONF_SDRC_D5_OFFSET 0x03b -#define OMAP2420_CONTROL_PADCONF_SDRC_D4_OFFSET 0x03c -#define OMAP2420_CONTROL_PADCONF_SDRC_D3_OFFSET 0x03d -#define OMAP2420_CONTROL_PADCONF_SDRC_D2_OFFSET 0x03e -#define OMAP2420_CONTROL_PADCONF_SDRC_D1_OFFSET 0x03f -#define OMAP2420_CONTROL_PADCONF_SDRC_D0_OFFSET 0x040 -#define OMAP2420_CONTROL_PADCONF_GPMC_A10_OFFSET 0x041 -#define OMAP2420_CONTROL_PADCONF_GPMC_A9_OFFSET 0x042 -#define OMAP2420_CONTROL_PADCONF_GPMC_A8_OFFSET 0x043 -#define OMAP2420_CONTROL_PADCONF_GPMC_A7_OFFSET 0x044 -#define OMAP2420_CONTROL_PADCONF_GPMC_A6_OFFSET 0x045 -#define OMAP2420_CONTROL_PADCONF_GPMC_A5_OFFSET 0x046 -#define OMAP2420_CONTROL_PADCONF_GPMC_A4_OFFSET 0x047 -#define OMAP2420_CONTROL_PADCONF_GPMC_A3_OFFSET 0x048 -#define OMAP2420_CONTROL_PADCONF_GPMC_A2_OFFSET 0x049 -#define OMAP2420_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a -#define OMAP2420_CONTROL_PADCONF_GPMC_D15_OFFSET 0x04b -#define OMAP2420_CONTROL_PADCONF_GPMC_D14_OFFSET 0x04c -#define OMAP2420_CONTROL_PADCONF_GPMC_D13_OFFSET 0x04d -#define OMAP2420_CONTROL_PADCONF_GPMC_D12_OFFSET 0x04e -#define OMAP2420_CONTROL_PADCONF_GPMC_D11_OFFSET 0x04f -#define OMAP2420_CONTROL_PADCONF_GPMC_D10_OFFSET 0x050 -#define OMAP2420_CONTROL_PADCONF_GPMC_D9_OFFSET 0x051 -#define OMAP2420_CONTROL_PADCONF_GPMC_D8_OFFSET 0x052 -#define OMAP2420_CONTROL_PADCONF_GPMC_D7_OFFSET 0x053 -#define OMAP2420_CONTROL_PADCONF_GPMC_D6_OFFSET 0x054 -#define OMAP2420_CONTROL_PADCONF_GPMC_D5_OFFSET 0x055 -#define OMAP2420_CONTROL_PADCONF_GPMC_D4_OFFSET 0x056 -#define OMAP2420_CONTROL_PADCONF_GPMC_D3_OFFSET 0x057 -#define OMAP2420_CONTROL_PADCONF_GPMC_D2_OFFSET 0x058 -#define OMAP2420_CONTROL_PADCONF_GPMC_D1_OFFSET 0x059 -#define OMAP2420_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05a -#define OMAP2420_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x05b -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x05c -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x05d -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x05e -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x05f -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x060 -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x061 -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x062 -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x063 -#define OMAP2420_CONTROL_PADCONF_GPMC_NALE_ALE_OFFSET 0x064 -#define OMAP2420_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x065 -#define OMAP2420_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x066 -#define OMAP2420_CONTROL_PADCONF_GPMC_NBE0_OFFSET 0x067 -#define OMAP2420_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x068 -#define OMAP2420_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x069 -#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x06a -#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x06b -#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x06c -#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x06d -#define OMAP2420_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x06e -#define OMAP2420_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x06f -#define OMAP2420_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x070 -#define OMAP2420_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x071 -#define OMAP2420_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x072 -#define OMAP2420_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x073 -#define OMAP2420_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x074 -#define OMAP2420_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x075 -#define OMAP2420_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x076 -#define OMAP2420_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x077 -#define OMAP2420_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x078 -#define OMAP2420_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x079 -#define OMAP2420_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x07a -#define OMAP2420_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x07f -#define OMAP2420_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x080 -#define OMAP2420_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x081 -#define OMAP2420_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x082 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x083 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x084 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x085 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x086 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x087 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x088 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x089 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x08a -#define OMAP2420_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x08b -#define OMAP2420_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x08c -#define OMAP2420_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x08d -#define OMAP2420_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x08e -#define OMAP2420_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x08f -#define OMAP2420_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x090 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x091 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x092 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x093 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x094 -#define OMAP2420_CONTROL_PADCONF_UART1_CTS_OFFSET 0x095 -#define OMAP2420_CONTROL_PADCONF_UART1_RTS_OFFSET 0x096 -#define OMAP2420_CONTROL_PADCONF_UART1_TX_OFFSET 0x097 -#define OMAP2420_CONTROL_PADCONF_UART1_RX_OFFSET 0x098 -#define OMAP2420_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x099 -#define OMAP2420_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x09a -#define OMAP2420_CONTROL_PADCONF_DSS_PCL_OFFSET 0x09b -#define OMAP2420_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x09c -#define OMAP2420_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x09d -#define OMAP2420_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x09e -#define OMAP2420_CONTROL_PADCONF_CAM_D9_OFFSET 0x09f -#define OMAP2420_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a0 -#define OMAP2420_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a1 -#define OMAP2420_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a2 -#define OMAP2420_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a3 -#define OMAP2420_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a4 -#define OMAP2420_CONTROL_PADCONF_CAM_D3_OFFSET 0x0a5 -#define OMAP2420_CONTROL_PADCONF_CAM_D2_OFFSET 0x0a6 -#define OMAP2420_CONTROL_PADCONF_CAM_D1_OFFSET 0x0a7 -#define OMAP2420_CONTROL_PADCONF_CAM_D0_OFFSET 0x0a8 -#define OMAP2420_CONTROL_PADCONF_CAM_HS_OFFSET 0x0a9 -#define OMAP2420_CONTROL_PADCONF_CAM_VS_OFFSET 0x0aa -#define OMAP2420_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0ab -#define OMAP2420_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0ac -#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0ad -#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0ae -#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0af -#define OMAP2420_CONTROL_PADCONF_GPIO_62_OFFSET 0x0b0 -#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0b1 -#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0b2 -#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0b3 -#define OMAP2420_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0b4 -#define OMAP2420_CONTROL_PADCONF_VLYNQ_CLK_OFFSET 0x0b5 -#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX1_OFFSET 0x0b6 -#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX0_OFFSET 0x0b7 -#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX1_OFFSET 0x0b8 -#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX0_OFFSET 0x0b9 -#define OMAP2420_CONTROL_PADCONF_VLYNQ_NLA_OFFSET 0x0ba -#define OMAP2420_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0bb -#define OMAP2420_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0bc -#define OMAP2420_CONTROL_PADCONF_UART2_TX_OFFSET 0x0bd -#define OMAP2420_CONTROL_PADCONF_UART2_RX_OFFSET 0x0be -#define OMAP2420_CONTROL_PADCONF_EAC_BT_SCLK_OFFSET 0x0bf -#define OMAP2420_CONTROL_PADCONF_EAC_BT_FS_OFFSET 0x0c0 -#define OMAP2420_CONTROL_PADCONF_EAC_BT_DIN_OFFSET 0x0c1 -#define OMAP2420_CONTROL_PADCONF_EAC_BT_DOUT_OFFSET 0x0c2 -#define OMAP2420_CONTROL_PADCONF_MMC_CLKO_OFFSET 0x0c3 -#define OMAP2420_CONTROL_PADCONF_MMC_CMD_OFFSET 0x0c4 -#define OMAP2420_CONTROL_PADCONF_MMC_DAT0_OFFSET 0x0c5 -#define OMAP2420_CONTROL_PADCONF_MMC_DAT1_OFFSET 0x0c6 -#define OMAP2420_CONTROL_PADCONF_MMC_DAT2_OFFSET 0x0c7 -#define OMAP2420_CONTROL_PADCONF_MMC_DAT3_OFFSET 0x0c8 -#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR0_OFFSET 0x0c9 -#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR1_OFFSET 0x0ca -#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR2_OFFSET 0x0cb -#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR3_OFFSET 0x0cc -#define OMAP2420_CONTROL_PADCONF_MMC_CMD_DIR_OFFSET 0x0cd -#define OMAP2420_CONTROL_PADCONF_MMC_CLKI_OFFSET 0x0ce -#define OMAP2420_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0cf -#define OMAP2420_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0d0 -#define OMAP2420_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0d1 -#define OMAP2420_CONTROL_PADCONF_SPI1_NCS0_OFFSET 0x0d2 -#define OMAP2420_CONTROL_PADCONF_SPI1_NCS1_OFFSET 0x0d3 -#define OMAP2420_CONTROL_PADCONF_SPI1_NCS2_OFFSET 0x0d4 -#define OMAP2420_CONTROL_PADCONF_SPI1_NCS3_OFFSET 0x0d5 -#define OMAP2420_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0d6 -#define OMAP2420_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0d7 -#define OMAP2420_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0d8 -#define OMAP2420_CONTROL_PADCONF_SPI2_NCS0_OFFSET 0x0d9 -#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0da -#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0db -#define OMAP2420_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0dc -#define OMAP2420_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0dd -#define OMAP2420_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0de -#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0df -#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0e0 -#define OMAP2420_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0e1 -#define OMAP2420_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0e2 -#define OMAP2420_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0e3 -#define OMAP2420_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0e4 -#define OMAP2420_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0e5 -#define OMAP2420_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0e6 -#define OMAP2420_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0e7 -#define OMAP2420_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0e8 -#define OMAP2420_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0e9 -#define OMAP2420_CONTROL_PADCONF_TV_CVBS_OFFSET 0x0ea -#define OMAP2420_CONTROL_PADCONF_TV_VREF_OFFSET 0x0eb -#define OMAP2420_CONTROL_PADCONF_TV_RREF_OFFSET 0x0ec -#define OMAP2420_CONTROL_PADCONF_USB0_PUEN_OFFSET 0x0ed -#define OMAP2420_CONTROL_PADCONF_USB0_VP_OFFSET 0x0ee -#define OMAP2420_CONTROL_PADCONF_USB0_VM_OFFSET 0x0ef -#define OMAP2420_CONTROL_PADCONF_USB0_RCV_OFFSET 0x0f0 -#define OMAP2420_CONTROL_PADCONF_USB0_TXEN_OFFSET 0x0f1 -#define OMAP2420_CONTROL_PADCONF_USB0_SE0_OFFSET 0x0f2 -#define OMAP2420_CONTROL_PADCONF_USB0_DAT_OFFSET 0x0f3 -#define OMAP2420_CONTROL_PADCONF_EAC_AC_SCLK_OFFSET 0x0f4 -#define OMAP2420_CONTROL_PADCONF_EAC_AC_FS_OFFSET 0x0f5 -#define OMAP2420_CONTROL_PADCONF_EAC_AC_DIN_OFFSET 0x0f6 -#define OMAP2420_CONTROL_PADCONF_EAC_AC_DOUT_OFFSET 0x0f7 -#define OMAP2420_CONTROL_PADCONF_EAC_AC_MCLK_OFFSET 0x0f8 -#define OMAP2420_CONTROL_PADCONF_EAC_AC_RST_OFFSET 0x0f9 -#define OMAP2420_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x0fa -#define OMAP2420_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x0fb -#define OMAP2420_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x0fc -#define OMAP2420_CONTROL_PADCONF_SYS_NV_OFFSET 0x0fd -#define OMAP2420_CONTROL_PADCONF_GPIO_119_OFFSET 0x0fe -#define OMAP2420_CONTROL_PADCONF_GPIO_120_OFFSET 0x0ff -#define OMAP2420_CONTROL_PADCONF_GPIO_121_OFFSET 0x100 -#define OMAP2420_CONTROL_PADCONF_GPIO_122_OFFSET 0x101 -#define OMAP2420_CONTROL_PADCONF_SYS_32K_OFFSET 0x102 -#define OMAP2420_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x103 -#define OMAP2420_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x104 -#define OMAP2420_CONTROL_PADCONF_GPIO_36_OFFSET 0x105 -#define OMAP2420_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x106 -#define OMAP2420_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x107 -#define OMAP2420_CONTROL_PADCONF_GPIO_6_OFFSET 0x108 -#define OMAP2420_CONTROL_PADCONF_GPIO_124_OFFSET 0x109 -#define OMAP2420_CONTROL_PADCONF_GPIO_125_OFFSET 0x10a -#define OMAP2420_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x10b -#define OMAP2420_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x10c -#define OMAP2420_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x10d -#define OMAP2420_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x10e -#define OMAP2420_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x10f -#define OMAP2420_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x110 -#define OMAP2420_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x111 -#define OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x112 - -#define OMAP2420_CONTROL_PADCONF_MUX_SIZE \ - (OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x1) diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c deleted file mode 100644 index 4185f92553db..000000000000 --- a/arch/arm/mach-omap2/mux2430.c +++ /dev/null @@ -1,793 +0,0 @@ -/* - * Copyright (C) 2010 Nokia - * Copyright (C) 2010 Texas Instruments - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/module.h> -#include <linux/init.h> - -#include "mux.h" - -#ifdef CONFIG_OMAP_MUX - -#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ -{ \ - .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \ - .gpio = (g), \ - .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ -} - -#else - -#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ -{ \ - .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \ - .gpio = (g), \ -} - -#endif - -#define _OMAP2430_BALLENTRY(M0, bb, bt) \ -{ \ - .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \ - .balls = { bb, bt }, \ -} - -/* - * Superset of all mux modes for omap2430 - */ -static struct omap_mux __initdata omap2430_muxmodes[] = { - _OMAP2430_MUXENTRY(CAM_D0, 133, - "cam_d0", "hw_dbg0", "sti_dout", "gpio_133", - NULL, NULL, "etk_d2", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D10, 146, - "cam_d10", NULL, NULL, "gpio_146", - NULL, NULL, "etk_d12", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D11, 145, - "cam_d11", NULL, NULL, "gpio_145", - NULL, NULL, "etk_d13", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D1, 132, - "cam_d1", "hw_dbg1", "sti_din", "gpio_132", - NULL, NULL, "etk_d3", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D2, 129, - "cam_d2", "hw_dbg2", "mcbsp1_clkx", "gpio_129", - NULL, NULL, "etk_d4", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D3, 128, - "cam_d3", "hw_dbg3", "mcbsp1_dr", "gpio_128", - NULL, NULL, "etk_d5", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D4, 143, - "cam_d4", "hw_dbg4", "mcbsp1_fsr", "gpio_143", - NULL, NULL, "etk_d6", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D5, 112, - "cam_d5", "hw_dbg5", "mcbsp1_clkr", "gpio_112", - NULL, NULL, "etk_d7", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D6, 137, - "cam_d6", "hw_dbg6", NULL, "gpio_137", - NULL, NULL, "etk_d8", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D7, 136, - "cam_d7", "hw_dbg7", NULL, "gpio_136", - NULL, NULL, "etk_d9", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D8, 135, - "cam_d8", "hw_dbg8", NULL, "gpio_135", - NULL, NULL, "etk_d10", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D9, 134, - "cam_d9", "hw_dbg9", NULL, "gpio_134", - NULL, NULL, "etk_d11", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_HS, 11, - "cam_hs", "hw_dbg10", "mcbsp1_dx", "gpio_11", - NULL, NULL, "etk_d1", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_LCLK, 0, - "cam_lclk", NULL, "mcbsp_clks", NULL, - NULL, NULL, "etk_c1", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_VS, 12, - "cam_vs", "hw_dbg11", "mcbsp1_fsx", "gpio_12", - NULL, NULL, "etk_d0", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_XCLK, 0, - "cam_xclk", NULL, "sti_clk", NULL, - NULL, NULL, "etk_c2", NULL), - _OMAP2430_MUXENTRY(DSS_ACBIAS, 48, - "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA0, 40, - "dss_data0", "uart1_cts", NULL, "gpio_40", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA10, 128, - "dss_data10", "sdi_data1n", NULL, "gpio_128", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA11, 129, - "dss_data11", "sdi_data1p", NULL, "gpio_129", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA12, 130, - "dss_data12", "sdi_data2n", NULL, "gpio_130", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA13, 131, - "dss_data13", "sdi_data2p", NULL, "gpio_131", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA14, 132, - "dss_data14", "sdi_data3n", NULL, "gpio_132", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA15, 133, - "dss_data15", "sdi_data3p", NULL, "gpio_133", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA16, 46, - "dss_data16", NULL, NULL, "gpio_46", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA17, 47, - "dss_data17", NULL, NULL, "gpio_47", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA1, 41, - "dss_data1", "uart1_rts", NULL, "gpio_41", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA2, 42, - "dss_data2", "uart1_tx", NULL, "gpio_42", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA3, 43, - "dss_data3", "uart1_rx", NULL, "gpio_43", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA4, 44, - "dss_data4", "uart3_rx_irrx", NULL, "gpio_44", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA5, 45, - "dss_data5", "uart3_tx_irtx", NULL, "gpio_45", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA6, 144, - "dss_data6", NULL, NULL, "gpio_144", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA7, 147, - "dss_data7", NULL, NULL, "gpio_147", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA8, 38, - "dss_data8", NULL, NULL, "gpio_38", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA9, 39, - "dss_data9", NULL, NULL, "gpio_39", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_HSYNC, 110, - "dss_hsync", NULL, NULL, "gpio_110", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_113, 113, - "gpio_113", "mcbsp2_clkx", NULL, "gpio_113", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_114, 114, - "gpio_114", "mcbsp2_fsx", NULL, "gpio_114", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_115, 115, - "gpio_115", "mcbsp2_dr", NULL, "gpio_115", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_116, 116, - "gpio_116", "mcbsp2_dx", NULL, "gpio_116", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_128, 128, - "gpio_128", NULL, "sti_din", "gpio_128", - NULL, "sys_boot0", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_129, 129, - "gpio_129", NULL, "sti_dout", "gpio_129", - NULL, "sys_boot1", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_130, 130, - "gpio_130", NULL, NULL, "gpio_130", - "jtag_emu2", "sys_boot2", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_131, 131, - "gpio_131", NULL, NULL, "gpio_131", - "jtag_emu3", "sys_boot3", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_132, 132, - "gpio_132", NULL, NULL, "gpio_132", - NULL, "sys_boot4", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_133, 133, - "gpio_133", NULL, NULL, "gpio_133", - NULL, "sys_boot5", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_134, 134, - "gpio_134", "ccp_datn", NULL, "gpio_134", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_135, 135, - "gpio_135", "ccp_datp", NULL, "gpio_135", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_136, 136, - "gpio_136", "ccp_clkn", NULL, "gpio_136", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_137, 137, - "gpio_137", "ccp_clkp", NULL, "gpio_137", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_138, 138, - "gpio_138", "spi3_clk", NULL, "gpio_138", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_139, 139, - "gpio_139", "spi3_cs0", "sys_ndmareq3", "gpio_139", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_140, 140, - "gpio_140", "spi3_simo", "sys_ndmareq4", "gpio_140", - NULL, NULL, "etk_d14", "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_141, 141, - "gpio_141", "spi3_somi", NULL, "gpio_141", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_142, 142, - "gpio_142", "spi3_cs1", "sys_ndmareq2", "gpio_142", - NULL, NULL, "etk_d15", "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_148, 148, - "gpio_148", "mcbsp5_fsx", NULL, "gpio_148", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_149, 149, - "gpio_149", "mcbsp5_dx", NULL, "gpio_149", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_150, 150, - "gpio_150", "mcbsp5_dr", NULL, "gpio_150", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_151, 151, - "gpio_151", "sys_pwrok", NULL, "gpio_151", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_152, 152, - "gpio_152", "uart1_cts", "sys_ndmareq1", "gpio_152", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_153, 153, - "gpio_153", "uart1_rx", "sys_ndmareq0", "gpio_153", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_154, 154, - "gpio_154", "mcbsp5_clkx", NULL, "gpio_154", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_63, 63, - "gpio_63", "mcbsp4_clkx", NULL, "gpio_63", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_78, 78, - "gpio_78", NULL, "uart2_rts", "gpio_78", - "uart3_rts_sd", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_79, 79, - "gpio_79", "secure_indicator", "uart2_tx", "gpio_79", - "uart3_tx_irtx", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_7, 7, - "gpio_7", NULL, "uart2_cts", "gpio_7", - "uart3_cts_rctx", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_80, 80, - "gpio_80", NULL, "uart2_rx", "gpio_80", - "uart3_rx_irrx", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A10, 3, - "gpmc_a10", NULL, "sys_ndmareq0", "gpio_3", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A1, 31, - "gpmc_a1", NULL, NULL, "gpio_31", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A2, 30, - "gpmc_a2", NULL, NULL, "gpio_30", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A3, 29, - "gpmc_a3", NULL, NULL, "gpio_29", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A4, 49, - "gpmc_a4", NULL, NULL, "gpio_49", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A5, 53, - "gpmc_a5", NULL, NULL, "gpio_53", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A6, 52, - "gpmc_a6", NULL, NULL, "gpio_52", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A7, 6, - "gpmc_a7", NULL, NULL, "gpio_6", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A8, 5, - "gpmc_a8", NULL, NULL, "gpio_5", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A9, 4, - "gpmc_a9", NULL, "sys_ndmareq1", "gpio_4", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_CLK, 21, - "gpmc_clk", NULL, NULL, "gpio_21", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D10, 18, - "gpmc_d10", NULL, NULL, "gpio_18", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D11, 57, - "gpmc_d11", NULL, NULL, "gpio_57", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D12, 77, - "gpmc_d12", NULL, NULL, "gpio_77", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D13, 76, - "gpmc_d13", NULL, NULL, "gpio_76", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D14, 55, - "gpmc_d14", NULL, NULL, "gpio_55", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D15, 54, - "gpmc_d15", NULL, NULL, "gpio_54", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D8, 20, - "gpmc_d8", NULL, NULL, "gpio_20", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D9, 19, - "gpmc_d9", NULL, NULL, "gpio_19", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_NCS1, 22, - "gpmc_ncs1", NULL, NULL, "gpio_22", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_NCS2, 23, - "gpmc_ncs2", NULL, NULL, "gpio_23", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_NCS3, 24, - "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_NCS4, 25, - "gpmc_ncs4", NULL, NULL, "gpio_25", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_NCS5, 26, - "gpmc_ncs5", NULL, NULL, "gpio_26", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_NCS6, 27, - "gpmc_ncs6", NULL, NULL, "gpio_27", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_NCS7, 28, - "gpmc_ncs7", "gpmc_io_dir", NULL, "gpio_28", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_WAIT1, 33, - "gpmc_wait1", NULL, NULL, "gpio_33", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_WAIT2, 34, - "gpmc_wait2", NULL, NULL, "gpio_34", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_WAIT3, 35, - "gpmc_wait3", NULL, NULL, "gpio_35", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(HDQ_SIO, 101, - "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101", - "uart3_rx_irrx", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(I2C1_SCL, 50, - "i2c1_scl", NULL, NULL, "gpio_50", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(I2C1_SDA, 51, - "i2c1_sda", NULL, NULL, "gpio_51", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(I2C2_SCL, 99, - "i2c2_scl", NULL, NULL, "gpio_99", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(I2C2_SDA, 100, - "i2c2_sda", NULL, NULL, "gpio_100", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(JTAG_EMU0, 127, - "jtag_emu0", "secure_indicator", NULL, "gpio_127", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(JTAG_EMU1, 126, - "jtag_emu1", NULL, NULL, "gpio_126", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP1_CLKR, 92, - "mcbsp1_clkr", "ssi2_dat_tx", NULL, "gpio_92", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP1_CLKX, 98, - "mcbsp1_clkx", "ssi2_wake", NULL, "gpio_98", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP1_DR, 95, - "mcbsp1_dr", "ssi2_dat_rx", NULL, "gpio_95", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP1_DX, 94, - "mcbsp1_dx", "ssi2_rdy_tx", NULL, "gpio_94", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP1_FSR, 93, - "mcbsp1_fsr", "ssi2_flag_tx", NULL, "gpio_93", - "spi2_cs1", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP1_FSX, 97, - "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP2_CLKX, 147, - "mcbsp2_clkx", "sdi_clkp", "dss_data23", "gpio_147", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP2_DR, 144, - "mcbsp2_dr", "sdi_clkn", "dss_data22", "gpio_144", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP3_CLKX, 71, - "mcbsp3_clkx", NULL, NULL, "gpio_71", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP3_DR, 73, - "mcbsp3_dr", NULL, NULL, "gpio_73", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP3_DX, 74, - "mcbsp3_dx", NULL, "sti_clk", "gpio_74", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP3_FSX, 72, - "mcbsp3_fsx", NULL, NULL, "gpio_72", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP_CLKS, 96, - "mcbsp_clks", "ssi2_flag_rx", NULL, "gpio_96", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC1_CLKO, 0, - "sdmmc1_clko", "ms_clko", NULL, NULL, - NULL, "hw_dbg9", "hw_dbg3", "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC1_CMD, 0, - "sdmmc1_cmd", "ms_bs", NULL, NULL, - NULL, "hw_dbg8", "hw_dbg2", "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC1_DAT0, 0, - "sdmmc1_dat0", "ms_dat0", NULL, NULL, - NULL, "hw_dbg7", "hw_dbg1", "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC1_DAT1, 75, - "sdmmc1_dat1", "ms_dat1", NULL, "gpio_75", - NULL, "hw_dbg6", "hw_dbg0", "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC1_DAT2, 0, - "sdmmc1_dat2", "ms_dat2", NULL, NULL, - NULL, "hw_dbg5", "hw_dbg10", "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC1_DAT3, 0, - "sdmmc1_dat3", "ms_dat3", NULL, NULL, - NULL, "hw_dbg4", "hw_dbg11", "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC2_CLKO, 13, - "sdmmc2_clko", NULL, NULL, "gpio_13", - NULL, "spi3_clk", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC2_CMD, 15, - "sdmmc2_cmd", "usb2_rcv", NULL, "gpio_15", - NULL, "spi3_simo", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC2_DAT0, 16, - "sdmmc2_dat0", "usb2_tllse0", NULL, "gpio_16", - NULL, "spi3_somi", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC2_DAT1, 58, - "sdmmc2_dat1", "usb2_txen", NULL, "gpio_58", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC2_DAT2, 17, - "sdmmc2_dat2", "usb2_dat", NULL, "gpio_17", - NULL, "spi3_cs1", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC2_DAT3, 14, - "sdmmc2_dat3", "usb2_se0", NULL, "gpio_14", - NULL, "spi3_cs0", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDRC_A12, 2, - "sdrc_a12", NULL, NULL, "gpio_2", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDRC_A13, 1, - "sdrc_a13", NULL, NULL, "gpio_1", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDRC_A14, 0, - "sdrc_a14", NULL, NULL, "gpio_0", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDRC_CKE1, 36, - "sdrc_cke1", NULL, NULL, "gpio_36", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDRC_NCS1, 37, - "sdrc_ncs1", NULL, NULL, "gpio_37", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI1_CLK, 81, - "spi1_clk", NULL, NULL, "gpio_81", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI1_CS0, 84, - "spi1_cs0", NULL, NULL, "gpio_84", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI1_CS1, 85, - "spi1_cs1", NULL, NULL, "gpio_85", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI1_CS2, 86, - "spi1_cs2", NULL, NULL, "gpio_86", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI1_CS3, 87, - "spi1_cs3", "spi2_cs1", NULL, "gpio_87", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI1_SIMO, 82, - "spi1_simo", NULL, NULL, "gpio_82", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI1_SOMI, 83, - "spi1_somi", NULL, NULL, "gpio_83", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI2_CLK, 88, - "spi2_clk", "gpt9_pwm_evt", NULL, "gpio_88", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI2_CS0, 91, - "spi2_cs0", "gpt12_pwm_evt", NULL, "gpio_91", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI2_SIMO, 89, - "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI2_SOMI, 90, - "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SSI1_DAT_RX, 62, - "ssi1_dat_rx", "uart1_rx", "usb1_dat", "gpio_62", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SSI1_DAT_TX, 59, - "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SSI1_FLAG_RX, 64, - "ssi1_flag_rx", "mcbsp4_dr", NULL, "gpio_64", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SSI1_FLAG_TX, 60, - "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_60", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SSI1_RDY_RX, 65, - "ssi1_rdy_rx", "mcbsp4_dx", NULL, "gpio_65", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SSI1_RDY_TX, 61, - "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SSI1_WAKE, 66, - "ssi1_wake", "mcbsp4_fsx", NULL, "gpio_66", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SYS_CLKOUT, 111, - "sys_clkout", NULL, NULL, "gpio_111", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SYS_DRM_MSECURE, 118, - "sys_drm_msecure", NULL, "sys_ndmareq6", "gpio_118", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SYS_NIRQ0, 56, - "sys_nirq0", NULL, NULL, "gpio_56", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SYS_NIRQ1, 125, - "sys_nirq1", NULL, "sys_ndmareq5", "gpio_125", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART1_CTS, 32, - "uart1_cts", "sdi_vsync", "dss_data18", "gpio_32", - "mcbsp5_clkx", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART1_RTS, 8, - "uart1_rts", "sdi_hsync", "dss_data19", "gpio_8", - "mcbsp5_fsx", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART1_RX, 10, - "uart1_rx", "sdi_stp", "dss_data21", "gpio_10", - "mcbsp5_dr", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART1_TX, 9, - "uart1_tx", "sdi_den", "dss_data20", "gpio_9", - "mcbsp5_dx", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART2_CTS, 67, - "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART2_RTS, 68, - "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART2_RX, 70, - "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART2_TX, 69, - "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART3_CTS_RCTX, 102, - "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART3_RTS_SD, 103, - "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART3_RX_IRRX, 105, - "uart3_rx_irrx", NULL, NULL, "gpio_105", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART3_TX_IRTX, 104, - "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_CLK, 120, - "usb0hs_clk", NULL, NULL, "gpio_120", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA0, 0, - "usb0hs_data0", "uart3_tx_irtx", NULL, NULL, - "usb0_txen", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA1, 0, - "usb0hs_data1", "uart3_rx_irrx", NULL, NULL, - "usb0_dat", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA2, 0, - "usb0hs_data2", "uart3_rts_sd", NULL, NULL, - "usb0_se0", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA3, 106, - "usb0hs_data3", NULL, "uart3_cts_rctx", "gpio_106", - "usb0_puen", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA4, 107, - "usb0hs_data4", "mcbsp2_dr", NULL, "gpio_107", - "usb0_vp", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA5, 108, - "usb0hs_data5", "mcbsp2_dx", NULL, "gpio_108", - "usb0_vm", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA6, 109, - "usb0hs_data6", "mcbsp2_fsx", NULL, "gpio_109", - "usb0_rcv", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA7, 124, - "usb0hs_data7", "mcbsp2_clkx", NULL, "gpio_124", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DIR, 121, - "usb0hs_dir", NULL, NULL, "gpio_121", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_NXT, 123, - "usb0hs_nxt", NULL, NULL, "gpio_123", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_STP, 122, - "usb0hs_stp", NULL, NULL, "gpio_122", - NULL, NULL, NULL, "safe_mode"), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - -/* - * Balls for POP package - * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom) - */ -#ifdef CONFIG_DEBUG_FS -static struct omap_ball __initdata omap2430_pop_ball[] = { - _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL), - _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL), - _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL), - _OMAP2430_BALLENTRY(CAM_D11, "w3", NULL), - _OMAP2430_BALLENTRY(CAM_D2, "r2", NULL), - _OMAP2430_BALLENTRY(CAM_D3, "u3", NULL), - _OMAP2430_BALLENTRY(CAM_D4, "u2", NULL), - _OMAP2430_BALLENTRY(CAM_D5, "v1", NULL), - _OMAP2430_BALLENTRY(CAM_D6, "t3", NULL), - _OMAP2430_BALLENTRY(CAM_D7, "r3", NULL), - _OMAP2430_BALLENTRY(CAM_D8, "u7", NULL), - _OMAP2430_BALLENTRY(CAM_D9, "t7", NULL), - _OMAP2430_BALLENTRY(CAM_HS, "p2", NULL), - _OMAP2430_BALLENTRY(CAM_LCLK, "r7", NULL), - _OMAP2430_BALLENTRY(CAM_VS, "n2", NULL), - _OMAP2430_BALLENTRY(CAM_XCLK, "p3", NULL), - _OMAP2430_BALLENTRY(DSS_ACBIAS, "y3", NULL), - _OMAP2430_BALLENTRY(DSS_DATA0, "v8", NULL), - _OMAP2430_BALLENTRY(DSS_DATA1, "w1", NULL), - _OMAP2430_BALLENTRY(DSS_DATA10, "k25", NULL), - _OMAP2430_BALLENTRY(DSS_DATA11, "j25", NULL), - _OMAP2430_BALLENTRY(DSS_DATA12, "k24", NULL), - _OMAP2430_BALLENTRY(DSS_DATA13, "j24", NULL), - _OMAP2430_BALLENTRY(DSS_DATA14, "h25", NULL), - _OMAP2430_BALLENTRY(DSS_DATA15, "g25", NULL), - _OMAP2430_BALLENTRY(DSS_DATA16, "ac3", NULL), - _OMAP2430_BALLENTRY(DSS_DATA17, "y7", NULL), - _OMAP2430_BALLENTRY(DSS_DATA2, "u8", NULL), - _OMAP2430_BALLENTRY(DSS_DATA3, "u4", NULL), - _OMAP2430_BALLENTRY(DSS_DATA4, "v3", NULL), - _OMAP2430_BALLENTRY(DSS_DATA5, "aa4", NULL), - _OMAP2430_BALLENTRY(DSS_DATA6, "w8", NULL), - _OMAP2430_BALLENTRY(DSS_DATA7, "y1", NULL), - _OMAP2430_BALLENTRY(DSS_DATA8, "aa2", NULL), - _OMAP2430_BALLENTRY(DSS_DATA9, "ab4", NULL), - _OMAP2430_BALLENTRY(DSS_HSYNC, "v2", NULL), - _OMAP2430_BALLENTRY(GPIO_113, "ad16", NULL), - _OMAP2430_BALLENTRY(GPIO_114, "ac10", NULL), - _OMAP2430_BALLENTRY(GPIO_115, "ad13", NULL), - _OMAP2430_BALLENTRY(GPIO_116, "ae15", NULL), - _OMAP2430_BALLENTRY(GPIO_128, "p1", NULL), - _OMAP2430_BALLENTRY(GPIO_129, "r1", NULL), - _OMAP2430_BALLENTRY(GPIO_130, "p7", NULL), - _OMAP2430_BALLENTRY(GPIO_131, "l8", NULL), - _OMAP2430_BALLENTRY(GPIO_132, "w24", NULL), - _OMAP2430_BALLENTRY(GPIO_133, "aa24", NULL), - _OMAP2430_BALLENTRY(GPIO_134, "ae12", NULL), - _OMAP2430_BALLENTRY(GPIO_135, "ae11", NULL), - _OMAP2430_BALLENTRY(GPIO_136, "ad12", NULL), - _OMAP2430_BALLENTRY(GPIO_137, "ad11", NULL), - _OMAP2430_BALLENTRY(GPIO_138, "y12", NULL), - _OMAP2430_BALLENTRY(GPIO_139, "ad17", NULL), - _OMAP2430_BALLENTRY(GPIO_140, "l7", NULL), - _OMAP2430_BALLENTRY(GPIO_141, "ac24", NULL), - _OMAP2430_BALLENTRY(GPIO_142, "m3", NULL), - _OMAP2430_BALLENTRY(GPIO_148, "af12", NULL), - _OMAP2430_BALLENTRY(GPIO_149, "k7", NULL), - _OMAP2430_BALLENTRY(GPIO_150, "m1", NULL), - _OMAP2430_BALLENTRY(GPIO_151, "ad14", NULL), - _OMAP2430_BALLENTRY(GPIO_152, "ad18", NULL), - _OMAP2430_BALLENTRY(GPIO_153, "u24", NULL), - _OMAP2430_BALLENTRY(GPIO_154, "ae16", NULL), - _OMAP2430_BALLENTRY(GPIO_63, "n3", NULL), - _OMAP2430_BALLENTRY(GPIO_7, "ac23", NULL), - _OMAP2430_BALLENTRY(GPIO_78, "ad10", NULL), - _OMAP2430_BALLENTRY(GPIO_79, "ae10", NULL), - _OMAP2430_BALLENTRY(GPIO_80, "ae13", NULL), - _OMAP2430_BALLENTRY(GPMC_A1, "a9", NULL), - _OMAP2430_BALLENTRY(GPMC_A10, "g12", NULL), - _OMAP2430_BALLENTRY(GPMC_A2, "b8", NULL), - _OMAP2430_BALLENTRY(GPMC_A3, "g10", NULL), - _OMAP2430_BALLENTRY(GPMC_A4, "g11", NULL), - _OMAP2430_BALLENTRY(GPMC_A5, "a10", NULL), - _OMAP2430_BALLENTRY(GPMC_A6, "g13", NULL), - _OMAP2430_BALLENTRY(GPMC_A7, "a6", NULL), - _OMAP2430_BALLENTRY(GPMC_A8, "h1", NULL), - _OMAP2430_BALLENTRY(GPMC_A9, "c8", NULL), - _OMAP2430_BALLENTRY(GPMC_CLK, "n1", "l1"), - _OMAP2430_BALLENTRY(GPMC_D10, "d1", "n1"), - _OMAP2430_BALLENTRY(GPMC_D11, "d2", "p2"), - _OMAP2430_BALLENTRY(GPMC_D12, "e1", "p1"), - _OMAP2430_BALLENTRY(GPMC_D13, "e3", "m1"), - _OMAP2430_BALLENTRY(GPMC_D14, "c7", "j2"), - _OMAP2430_BALLENTRY(GPMC_D15, "f3", "k2"), - _OMAP2430_BALLENTRY(GPMC_D8, "e2", "r1"), - _OMAP2430_BALLENTRY(GPMC_D9, "ab1", "t1"), - _OMAP2430_BALLENTRY(GPMC_NCS1, "ac1", "w1"), - _OMAP2430_BALLENTRY(GPMC_NCS2, "c6", NULL), - _OMAP2430_BALLENTRY(GPMC_NCS3, "b9", NULL), - _OMAP2430_BALLENTRY(GPMC_NCS4, "b4", NULL), - _OMAP2430_BALLENTRY(GPMC_NCS5, "a4", NULL), - _OMAP2430_BALLENTRY(GPMC_NCS6, "f1", NULL), - _OMAP2430_BALLENTRY(GPMC_NCS7, "a7", NULL), - _OMAP2430_BALLENTRY(GPMC_WAIT1, "j1", "y8"), - _OMAP2430_BALLENTRY(GPMC_WAIT2, "b7", NULL), - _OMAP2430_BALLENTRY(GPMC_WAIT3, "g14", NULL), - _OMAP2430_BALLENTRY(HDQ_SIO, "h20", NULL), - _OMAP2430_BALLENTRY(I2C1_SCL, "y17", NULL), - _OMAP2430_BALLENTRY(I2C1_SDA, "ac19", NULL), - _OMAP2430_BALLENTRY(I2C2_SCL, "n7", NULL), - _OMAP2430_BALLENTRY(I2C2_SDA, "m4", NULL), - _OMAP2430_BALLENTRY(JTAG_EMU0, "e25", NULL), - _OMAP2430_BALLENTRY(JTAG_EMU1, "e24", NULL), - _OMAP2430_BALLENTRY(MCBSP1_CLKR, "ab2", NULL), - _OMAP2430_BALLENTRY(MCBSP1_CLKX, "y9", NULL), - _OMAP2430_BALLENTRY(MCBSP1_DR, "af3", NULL), - _OMAP2430_BALLENTRY(MCBSP1_DX, "aa1", NULL), - _OMAP2430_BALLENTRY(MCBSP1_FSR, "ad5", NULL), - _OMAP2430_BALLENTRY(MCBSP1_FSX, "ab3", NULL), - _OMAP2430_BALLENTRY(MCBSP2_CLKX, "j26", NULL), - _OMAP2430_BALLENTRY(MCBSP2_DR, "k26", NULL), - _OMAP2430_BALLENTRY(MCBSP3_CLKX, "ac9", NULL), - _OMAP2430_BALLENTRY(MCBSP3_DR, "ae2", NULL), - _OMAP2430_BALLENTRY(MCBSP3_DX, "af4", NULL), - _OMAP2430_BALLENTRY(MCBSP3_FSX, "ae4", NULL), - _OMAP2430_BALLENTRY(MCBSP_CLKS, "ad6", NULL), - _OMAP2430_BALLENTRY(SDMMC1_CLKO, "n23", NULL), - _OMAP2430_BALLENTRY(SDMMC1_CMD, "l23", NULL), - _OMAP2430_BALLENTRY(SDMMC1_DAT0, "m24", NULL), - _OMAP2430_BALLENTRY(SDMMC1_DAT1, "p23", NULL), - _OMAP2430_BALLENTRY(SDMMC1_DAT2, "t20", NULL), - _OMAP2430_BALLENTRY(SDMMC1_DAT3, "r20", NULL), - _OMAP2430_BALLENTRY(SDMMC2_CLKO, "v26", NULL), - _OMAP2430_BALLENTRY(SDMMC2_CMD, "w20", NULL), - _OMAP2430_BALLENTRY(SDMMC2_DAT0, "v23", NULL), - _OMAP2430_BALLENTRY(SDMMC2_DAT1, "y24", NULL), - _OMAP2430_BALLENTRY(SDMMC2_DAT2, "v25", NULL), - _OMAP2430_BALLENTRY(SDMMC2_DAT3, "v24", NULL), - _OMAP2430_BALLENTRY(SDRC_A12, "w26", "r21"), - _OMAP2430_BALLENTRY(SDRC_A13, "af20", "aa15"), - _OMAP2430_BALLENTRY(SDRC_A14, "af16", "y12"), - _OMAP2430_BALLENTRY(SDRC_CKE1, "af15", "y13"), - _OMAP2430_BALLENTRY(SDRC_NCS1, "aa25", "t20"), - _OMAP2430_BALLENTRY(SPI1_CLK, "y18", NULL), - _OMAP2430_BALLENTRY(SPI1_CS0, "u1", NULL), - _OMAP2430_BALLENTRY(SPI1_CS1, "af19", NULL), - _OMAP2430_BALLENTRY(SPI1_CS2, "ae19", NULL), - _OMAP2430_BALLENTRY(SPI1_CS3, "h24", NULL), - _OMAP2430_BALLENTRY(SPI1_SIMO, "ad15", NULL), - _OMAP2430_BALLENTRY(SPI1_SOMI, "ae17", NULL), - _OMAP2430_BALLENTRY(SPI2_CLK, "y20", NULL), - _OMAP2430_BALLENTRY(SPI2_CS0, "y19", NULL), - _OMAP2430_BALLENTRY(SPI2_SIMO, "ac20", NULL), - _OMAP2430_BALLENTRY(SPI2_SOMI, "ad19", NULL), - _OMAP2430_BALLENTRY(SSI1_DAT_RX, "aa26", NULL), - _OMAP2430_BALLENTRY(SSI1_DAT_TX, "ad24", NULL), - _OMAP2430_BALLENTRY(SSI1_FLAG_RX, "ad23", NULL), - _OMAP2430_BALLENTRY(SSI1_FLAG_TX, "ab24", NULL), - _OMAP2430_BALLENTRY(SSI1_RDY_RX, "ab25", NULL), - _OMAP2430_BALLENTRY(SSI1_RDY_TX, "y25", NULL), - _OMAP2430_BALLENTRY(SSI1_WAKE, "ac25", NULL), - _OMAP2430_BALLENTRY(SYS_CLKOUT, "r25", NULL), - _OMAP2430_BALLENTRY(SYS_DRM_MSECURE, "ae3", NULL), - _OMAP2430_BALLENTRY(SYS_NIRQ0, "w25", NULL), - _OMAP2430_BALLENTRY(SYS_NIRQ1, "ad21", NULL), - _OMAP2430_BALLENTRY(UART1_CTS, "p24", NULL), - _OMAP2430_BALLENTRY(UART1_RTS, "p25", NULL), - _OMAP2430_BALLENTRY(UART1_RX, "n24", NULL), - _OMAP2430_BALLENTRY(UART1_TX, "r24", NULL), - _OMAP2430_BALLENTRY(UART2_CTS, "u25", NULL), - _OMAP2430_BALLENTRY(UART2_RTS, "t23", NULL), - _OMAP2430_BALLENTRY(UART2_RX, "t24", NULL), - _OMAP2430_BALLENTRY(UART2_TX, "u20", NULL), - _OMAP2430_BALLENTRY(UART3_CTS_RCTX, "m2", NULL), - _OMAP2430_BALLENTRY(UART3_RTS_SD, "k2", NULL), - _OMAP2430_BALLENTRY(UART3_RX_IRRX, "l3", NULL), - _OMAP2430_BALLENTRY(UART3_TX_IRTX, "l2", NULL), - _OMAP2430_BALLENTRY(USB0HS_CLK, "ae8", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA0, "ad4", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA1, "ae6", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA2, "af9", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA3, "ad9", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA4, "y11", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA5, "ad7", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA6, "ae7", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA7, "ac7", NULL), - _OMAP2430_BALLENTRY(USB0HS_DIR, "ad8", NULL), - _OMAP2430_BALLENTRY(USB0HS_NXT, "ae9", NULL), - _OMAP2430_BALLENTRY(USB0HS_STP, "ae5", NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define omap2430_pop_ball NULL -#endif - -int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags) -{ - struct omap_ball *package_balls = NULL; - - switch (flags & OMAP_PACKAGE_MASK) { - case OMAP_PACKAGE_ZAC: - package_balls = omap2430_pop_ball; - break; - default: - pr_warning("%s: No ball data available for omap2420 package\n", - __func__); - } - - return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3, - OMAP2430_CONTROL_PADCONF_MUX_PBASE, - OMAP2430_CONTROL_PADCONF_MUX_SIZE, - omap2430_muxmodes, NULL, board_subset, - package_balls); -} diff --git a/arch/arm/mach-omap2/mux2430.h b/arch/arm/mach-omap2/mux2430.h deleted file mode 100644 index 9fd93149ebd9..000000000000 --- a/arch/arm/mach-omap2/mux2430.h +++ /dev/null @@ -1,370 +0,0 @@ -/* - * Copyright (C) 2009 Nokia - * Copyright (C) 2009 Texas Instruments - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define OMAP2430_CONTROL_PADCONF_MUX_PBASE 0x49002030LU - -#define OMAP2430_MUX(mode0, mux_value) \ -{ \ - .reg_offset = (OMAP2430_CONTROL_PADCONF_##mode0##_OFFSET), \ - .value = (mux_value), \ -} - -/* - * OMAP2430 CONTROL_PADCONF* register offsets for pin-muxing - * - * Extracted from the TRM. Add 0x49002030 to these values to get the - * absolute addresses. The name in the macro is the mode-0 name of - * the pin. NOTE: These registers are 8-bits wide. - * - * Note that these defines use SDMMC instead of MMC for compatibility - * with signal names used in 3630. - */ -#define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x000 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x001 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x002 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x003 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x004 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x005 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x006 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x007 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x008 -#define OMAP2430_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x009 -#define OMAP2430_CONTROL_PADCONF_GPMC_NOE_NRE_OFFSET 0x00a -#define OMAP2430_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x00b -#define OMAP2430_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x00c -#define OMAP2430_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x00d -#define OMAP2430_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x00e -#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x00f -#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x010 -#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x011 -#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x012 -#define OMAP2430_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x013 -#define OMAP2430_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x014 -#define OMAP2430_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x015 -#define OMAP2430_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x016 -#define OMAP2430_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x017 -#define OMAP2430_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x018 -#define OMAP2430_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x019 -#define OMAP2430_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x01a -#define OMAP2430_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x01b -#define OMAP2430_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x01c -#define OMAP2430_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x01d -#define OMAP2430_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x01e -#define OMAP2430_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x01f -#define OMAP2430_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x020 -#define OMAP2430_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x021 -#define OMAP2430_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x022 -#define OMAP2430_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x023 -#define OMAP2430_CONTROL_PADCONF_SDRC_A14_OFFSET 0x024 -#define OMAP2430_CONTROL_PADCONF_SDRC_A13_OFFSET 0x025 -#define OMAP2430_CONTROL_PADCONF_SDRC_A12_OFFSET 0x026 -#define OMAP2430_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x027 -#define OMAP2430_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x028 -#define OMAP2430_CONTROL_PADCONF_SDRC_A11_OFFSET 0x029 -#define OMAP2430_CONTROL_PADCONF_SDRC_A10_OFFSET 0x02a -#define OMAP2430_CONTROL_PADCONF_SDRC_A9_OFFSET 0x02b -#define OMAP2430_CONTROL_PADCONF_SDRC_A8_OFFSET 0x02c -#define OMAP2430_CONTROL_PADCONF_SDRC_A7_OFFSET 0x02d -#define OMAP2430_CONTROL_PADCONF_SDRC_A6_OFFSET 0x02e -#define OMAP2430_CONTROL_PADCONF_SDRC_A5_OFFSET 0x02f -#define OMAP2430_CONTROL_PADCONF_SDRC_A4_OFFSET 0x030 -#define OMAP2430_CONTROL_PADCONF_SDRC_A3_OFFSET 0x031 -#define OMAP2430_CONTROL_PADCONF_SDRC_A2_OFFSET 0x032 -#define OMAP2430_CONTROL_PADCONF_SDRC_A1_OFFSET 0x033 -#define OMAP2430_CONTROL_PADCONF_SDRC_A0_OFFSET 0x034 -#define OMAP2430_CONTROL_PADCONF_SDRC_D31_OFFSET 0x035 -#define OMAP2430_CONTROL_PADCONF_SDRC_D30_OFFSET 0x036 -#define OMAP2430_CONTROL_PADCONF_SDRC_D29_OFFSET 0x037 -#define OMAP2430_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038 -#define OMAP2430_CONTROL_PADCONF_SDRC_D27_OFFSET 0x039 -#define OMAP2430_CONTROL_PADCONF_SDRC_D26_OFFSET 0x03a -#define OMAP2430_CONTROL_PADCONF_SDRC_D25_OFFSET 0x03b -#define OMAP2430_CONTROL_PADCONF_SDRC_D24_OFFSET 0x03c -#define OMAP2430_CONTROL_PADCONF_SDRC_D23_OFFSET 0x03d -#define OMAP2430_CONTROL_PADCONF_SDRC_D22_OFFSET 0x03e -#define OMAP2430_CONTROL_PADCONF_SDRC_D21_OFFSET 0x03f -#define OMAP2430_CONTROL_PADCONF_SDRC_D20_OFFSET 0x040 -#define OMAP2430_CONTROL_PADCONF_SDRC_D19_OFFSET 0x041 -#define OMAP2430_CONTROL_PADCONF_SDRC_D18_OFFSET 0x042 -#define OMAP2430_CONTROL_PADCONF_SDRC_D17_OFFSET 0x043 -#define OMAP2430_CONTROL_PADCONF_SDRC_D16_OFFSET 0x044 -#define OMAP2430_CONTROL_PADCONF_SDRC_D15_OFFSET 0x045 -#define OMAP2430_CONTROL_PADCONF_SDRC_D14_OFFSET 0x046 -#define OMAP2430_CONTROL_PADCONF_SDRC_D13_OFFSET 0x047 -#define OMAP2430_CONTROL_PADCONF_SDRC_D12_OFFSET 0x048 -#define OMAP2430_CONTROL_PADCONF_SDRC_D11_OFFSET 0x049 -#define OMAP2430_CONTROL_PADCONF_SDRC_D10_OFFSET 0x04a -#define OMAP2430_CONTROL_PADCONF_SDRC_D9_OFFSET 0x04b -#define OMAP2430_CONTROL_PADCONF_SDRC_D8_OFFSET 0x04c -#define OMAP2430_CONTROL_PADCONF_SDRC_D7_OFFSET 0x04d -#define OMAP2430_CONTROL_PADCONF_SDRC_D6_OFFSET 0x04e -#define OMAP2430_CONTROL_PADCONF_SDRC_D5_OFFSET 0x04f -#define OMAP2430_CONTROL_PADCONF_SDRC_D4_OFFSET 0x050 -#define OMAP2430_CONTROL_PADCONF_SDRC_D3_OFFSET 0x051 -#define OMAP2430_CONTROL_PADCONF_SDRC_D2_OFFSET 0x052 -#define OMAP2430_CONTROL_PADCONF_SDRC_D1_OFFSET 0x053 -#define OMAP2430_CONTROL_PADCONF_SDRC_D0_OFFSET 0x054 -#define OMAP2430_CONTROL_PADCONF_GPMC_A10_OFFSET 0x055 -#define OMAP2430_CONTROL_PADCONF_GPMC_A9_OFFSET 0x056 -#define OMAP2430_CONTROL_PADCONF_GPMC_A8_OFFSET 0x057 -#define OMAP2430_CONTROL_PADCONF_GPMC_A7_OFFSET 0x058 -#define OMAP2430_CONTROL_PADCONF_GPMC_A6_OFFSET 0x059 -#define OMAP2430_CONTROL_PADCONF_GPMC_A5_OFFSET 0x05a -#define OMAP2430_CONTROL_PADCONF_GPMC_A4_OFFSET 0x05b -#define OMAP2430_CONTROL_PADCONF_GPMC_A3_OFFSET 0x05c -#define OMAP2430_CONTROL_PADCONF_GPMC_A2_OFFSET 0x05d -#define OMAP2430_CONTROL_PADCONF_GPMC_A1_OFFSET 0x05e -#define OMAP2430_CONTROL_PADCONF_GPMC_D15_OFFSET 0x05f -#define OMAP2430_CONTROL_PADCONF_GPMC_D14_OFFSET 0x060 -#define OMAP2430_CONTROL_PADCONF_GPMC_D13_OFFSET 0x061 -#define OMAP2430_CONTROL_PADCONF_GPMC_D12_OFFSET 0x062 -#define OMAP2430_CONTROL_PADCONF_GPMC_D11_OFFSET 0x063 -#define OMAP2430_CONTROL_PADCONF_GPMC_D10_OFFSET 0x064 -#define OMAP2430_CONTROL_PADCONF_GPMC_D9_OFFSET 0x065 -#define OMAP2430_CONTROL_PADCONF_GPMC_D8_OFFSET 0x066 -#define OMAP2430_CONTROL_PADCONF_GPMC_D7_OFFSET 0x067 -#define OMAP2430_CONTROL_PADCONF_GPMC_D6_OFFSET 0x068 -#define OMAP2430_CONTROL_PADCONF_GPMC_D5_OFFSET 0x069 -#define OMAP2430_CONTROL_PADCONF_GPMC_D4_OFFSET 0x06a -#define OMAP2430_CONTROL_PADCONF_GPMC_D3_OFFSET 0x06b -#define OMAP2430_CONTROL_PADCONF_GPMC_D2_OFFSET 0x06c -#define OMAP2430_CONTROL_PADCONF_GPMC_D1_OFFSET 0x06d -#define OMAP2430_CONTROL_PADCONF_GPMC_D0_OFFSET 0x06e -#define OMAP2430_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x06f -#define OMAP2430_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x070 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x071 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x072 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x073 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x074 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x075 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x076 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x077 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x078 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x079 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x07a -#define OMAP2430_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x07b -#define OMAP2430_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x07c -#define OMAP2430_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x07d -#define OMAP2430_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x07e -#define OMAP2430_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x07f -#define OMAP2430_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x080 -#define OMAP2430_CONTROL_PADCONF_UART1_CTS_OFFSET 0x081 -#define OMAP2430_CONTROL_PADCONF_UART1_RTS_OFFSET 0x082 -#define OMAP2430_CONTROL_PADCONF_UART1_TX_OFFSET 0x083 -#define OMAP2430_CONTROL_PADCONF_UART1_RX_OFFSET 0x084 -#define OMAP2430_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x085 -#define OMAP2430_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x086 -#define OMAP2430_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x087 -#define OMAP2430_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x088 -#define OMAP2430_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x089 -#define OMAP2430_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x08a -#define OMAP2430_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x08b -#define OMAP2430_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x08c -#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ0_OFFSET 0x08d -#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ1_OFFSET 0x08e -#define OMAP2430_CONTROL_PADCONF_SYS_VMODE_OFFSET 0x08f -#define OMAP2430_CONTROL_PADCONF_GPIO_128_OFFSET 0x090 -#define OMAP2430_CONTROL_PADCONF_GPIO_129_OFFSET 0x091 -#define OMAP2430_CONTROL_PADCONF_GPIO_130_OFFSET 0x092 -#define OMAP2430_CONTROL_PADCONF_GPIO_131_OFFSET 0x093 -#define OMAP2430_CONTROL_PADCONF_SYS_32K_OFFSET 0x094 -#define OMAP2430_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x095 -#define OMAP2430_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x096 -#define OMAP2430_CONTROL_PADCONF_GPIO_132_OFFSET 0x097 -#define OMAP2430_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x098 -#define OMAP2430_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x099 -#define OMAP2430_CONTROL_PADCONF_GPIO_151_OFFSET 0x09a -#define OMAP2430_CONTROL_PADCONF_GPIO_133_OFFSET 0x09b -#define OMAP2430_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x09c -#define OMAP2430_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x09d -#define OMAP2430_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x09e -#define OMAP2430_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x09f -#define OMAP2430_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x0a0 -#define OMAP2430_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x0a1 -#define OMAP2430_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x0a2 -#define OMAP2430_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x0a3 -#define OMAP2430_CONTROL_PADCONF_CAM_D9_OFFSET 0x0a4 -#define OMAP2430_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a5 -#define OMAP2430_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a6 -#define OMAP2430_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a7 -#define OMAP2430_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a8 -#define OMAP2430_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a9 -#define OMAP2430_CONTROL_PADCONF_CAM_D3_OFFSET 0x0aa -#define OMAP2430_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ab -#define OMAP2430_CONTROL_PADCONF_CAM_D1_OFFSET 0x0ac -#define OMAP2430_CONTROL_PADCONF_CAM_D0_OFFSET 0x0ad -#define OMAP2430_CONTROL_PADCONF_CAM_HS_OFFSET 0x0ae -#define OMAP2430_CONTROL_PADCONF_CAM_VS_OFFSET 0x0af -#define OMAP2430_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0b0 -#define OMAP2430_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0b1 -#define OMAP2430_CONTROL_PADCONF_CAM_D11_OFFSET 0x0b2 -#define OMAP2430_CONTROL_PADCONF_CAM_D10_OFFSET 0x0b3 -#define OMAP2430_CONTROL_PADCONF_GPIO_134_OFFSET 0x0b4 -#define OMAP2430_CONTROL_PADCONF_GPIO_135_OFFSET 0x0b5 -#define OMAP2430_CONTROL_PADCONF_GPIO_136_OFFSET 0x0b6 -#define OMAP2430_CONTROL_PADCONF_GPIO_137_OFFSET 0x0b7 -#define OMAP2430_CONTROL_PADCONF_GPIO_138_OFFSET 0x0b8 -#define OMAP2430_CONTROL_PADCONF_GPIO_139_OFFSET 0x0b9 -#define OMAP2430_CONTROL_PADCONF_GPIO_140_OFFSET 0x0ba -#define OMAP2430_CONTROL_PADCONF_GPIO_141_OFFSET 0x0bb -#define OMAP2430_CONTROL_PADCONF_GPIO_142_OFFSET 0x0bc -#define OMAP2430_CONTROL_PADCONF_GPIO_154_OFFSET 0x0bd -#define OMAP2430_CONTROL_PADCONF_GPIO_148_OFFSET 0x0be -#define OMAP2430_CONTROL_PADCONF_GPIO_149_OFFSET 0x0bf -#define OMAP2430_CONTROL_PADCONF_GPIO_150_OFFSET 0x0c0 -#define OMAP2430_CONTROL_PADCONF_GPIO_152_OFFSET 0x0c1 -#define OMAP2430_CONTROL_PADCONF_GPIO_153_OFFSET 0x0c2 -#define OMAP2430_CONTROL_PADCONF_SDMMC1_CLKO_OFFSET 0x0c3 -#define OMAP2430_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x0c4 -#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x0c5 -#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x0c6 -#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x0c7 -#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x0c8 -#define OMAP2430_CONTROL_PADCONF_SDMMC2_CLKO_OFFSET 0x0c9 -#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x0ca -#define OMAP2430_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x0cb -#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x0cc -#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x0cd -#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x0ce -#define OMAP2430_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0cf -#define OMAP2430_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0d0 -#define OMAP2430_CONTROL_PADCONF_UART2_TX_OFFSET 0x0d1 -#define OMAP2430_CONTROL_PADCONF_UART2_RX_OFFSET 0x0d2 -#define OMAP2430_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x0d3 -#define OMAP2430_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x0d4 -#define OMAP2430_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x0d5 -#define OMAP2430_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x0d6 -#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0d7 -#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0d8 -#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0d9 -#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0da -#define OMAP2430_CONTROL_PADCONF_GPIO_63_OFFSET 0x0db -#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0dc -#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0dd -#define OMAP2430_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0de -#define OMAP2430_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0df -#define OMAP2430_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0e0 -#define OMAP2430_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0e1 -#define OMAP2430_CONTROL_PADCONF_SPI1_CS0_OFFSET 0x0e2 -#define OMAP2430_CONTROL_PADCONF_SPI1_CS1_OFFSET 0x0e3 -#define OMAP2430_CONTROL_PADCONF_SPI1_CS2_OFFSET 0x0e4 -#define OMAP2430_CONTROL_PADCONF_SPI1_CS3_OFFSET 0x0e5 -#define OMAP2430_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0e6 -#define OMAP2430_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0e7 -#define OMAP2430_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0e8 -#define OMAP2430_CONTROL_PADCONF_SPI2_CS0_OFFSET 0x0e9 -#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0ea -#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0eb -#define OMAP2430_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0ec -#define OMAP2430_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0ed -#define OMAP2430_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0ee -#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0ef -#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0f0 -#define OMAP2430_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0f1 -#define OMAP2430_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0f2 -#define OMAP2430_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0f3 -#define OMAP2430_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0f4 -#define OMAP2430_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0f5 -#define OMAP2430_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0f6 -#define OMAP2430_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0f7 -#define OMAP2430_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0f8 -#define OMAP2430_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0f9 -#define OMAP2430_CONTROL_PADCONF_GPIO_7_OFFSET 0x0fa -#define OMAP2430_CONTROL_PADCONF_GPIO_78_OFFSET 0x0fb -#define OMAP2430_CONTROL_PADCONF_GPIO_79_OFFSET 0x0fc -#define OMAP2430_CONTROL_PADCONF_GPIO_80_OFFSET 0x0fd -#define OMAP2430_CONTROL_PADCONF_GPIO_113_OFFSET 0x0fe -#define OMAP2430_CONTROL_PADCONF_GPIO_114_OFFSET 0x0ff -#define OMAP2430_CONTROL_PADCONF_GPIO_115_OFFSET 0x100 -#define OMAP2430_CONTROL_PADCONF_GPIO_116_OFFSET 0x101 -#define OMAP2430_CONTROL_PADCONF_SYS_DRM_MSECURE_OFFSET 0x102 -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA3_OFFSET 0x103 -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA4_OFFSET 0x104 -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA5_OFFSET 0x105 -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA6_OFFSET 0x106 -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA2_OFFSET 0x107 -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA0_OFFSET 0x108 -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA1_OFFSET 0x109 -#define OMAP2430_CONTROL_PADCONF_USB0HS_CLK_OFFSET 0x10a -#define OMAP2430_CONTROL_PADCONF_USB0HS_DIR_OFFSET 0x10b -#define OMAP2430_CONTROL_PADCONF_USB0HS_STP_OFFSET 0x10c -#define OMAP2430_CONTROL_PADCONF_USB0HS_NXT_OFFSET 0x10d -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA7_OFFSET 0x10e -#define OMAP2430_CONTROL_PADCONF_TV_OUT_OFFSET 0x10f -#define OMAP2430_CONTROL_PADCONF_TV_VREF_OFFSET 0x110 -#define OMAP2430_CONTROL_PADCONF_TV_RSET_OFFSET 0x111 -#define OMAP2430_CONTROL_PADCONF_TV_VFB_OFFSET 0x112 -#define OMAP2430_CONTROL_PADCONF_TV_DACOUT_OFFSET 0x113 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD0_OFFSET 0x114 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD1_OFFSET 0x115 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD2_OFFSET 0x116 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD3_OFFSET 0x117 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD4_OFFSET 0x118 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD5_OFFSET 0x119 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD6_OFFSET 0x11a -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD7_OFFSET 0x11b -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD8_OFFSET 0x11c -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD9_OFFSET 0x11d -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD10_OFFSET 0x11e -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD11_OFFSET 0x11f -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD12_OFFSET 0x120 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD13_OFFSET 0x121 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD14_OFFSET 0x122 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD15_OFFSET 0x123 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD16_OFFSET 0x124 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD17_OFFSET 0x125 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD18_OFFSET 0x126 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD19_OFFSET 0x127 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD20_OFFSET 0x128 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD21_OFFSET 0x129 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD22_OFFSET 0x12a -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD23_OFFSET 0x12b -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD24_OFFSET 0x12c -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD25_OFFSET 0x12d -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD26_OFFSET 0x12e -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD27_OFFSET 0x12f -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD28_OFFSET 0x130 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD29_OFFSET 0x131 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD30_OFFSET 0x132 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD31_OFFSET 0x133 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD32_OFFSET 0x134 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD33_OFFSET 0x135 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD34_OFFSET 0x136 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD35_OFFSET 0x137 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD36_OFFSET 0x138 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD37_OFFSET 0x139 -#define OMAP2430_CONTROL_PADCONF_AD2DMWRITE_OFFSET 0x13a -#define OMAP2430_CONTROL_PADCONF_D2DCLK26MI_OFFSET 0x13b -#define OMAP2430_CONTROL_PADCONF_D2DNRESPWRON1_OFFSET 0x13c -#define OMAP2430_CONTROL_PADCONF_D2DNRESWARM_OFFSET 0x13d -#define OMAP2430_CONTROL_PADCONF_D2DARM9NIRQ_OFFSET 0x13e -#define OMAP2430_CONTROL_PADCONF_D2DUMA2P6FIQ_OFFSET 0x13f -#define OMAP2430_CONTROL_PADCONF_D2DSPINT_OFFSET 0x140 -#define OMAP2430_CONTROL_PADCONF_D2DFRINT_OFFSET 0x141 -#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ0_OFFSET 0x142 -#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ1_OFFSET 0x143 -#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ2_OFFSET 0x144 -#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ3_OFFSET 0x145 -#define OMAP2430_CONTROL_PADCONF_D2DN3GTRST_OFFSET 0x146 -#define OMAP2430_CONTROL_PADCONF_D2DN3GTDI_OFFSET 0x147 -#define OMAP2430_CONTROL_PADCONF_D2DN3GTDO_OFFSET 0x148 -#define OMAP2430_CONTROL_PADCONF_D2DN3GTMS_OFFSET 0x149 -#define OMAP2430_CONTROL_PADCONF_D2DN3GTCK_OFFSET 0x14a -#define OMAP2430_CONTROL_PADCONF_D2DN3GRTCK_OFFSET 0x14b -#define OMAP2430_CONTROL_PADCONF_D2DMSTDBY_OFFSET 0x14c -#define OMAP2430_CONTROL_PADCONF_AD2DSREAD_OFFSET 0x14d -#define OMAP2430_CONTROL_PADCONF_D2DSWAKEUP_OFFSET 0x14e -#define OMAP2430_CONTROL_PADCONF_D2DIDLEREQ_OFFSET 0x14f -#define OMAP2430_CONTROL_PADCONF_D2DIDLEACK_OFFSET 0x150 -#define OMAP2430_CONTROL_PADCONF_D2DSPARE0_OFFSET 0x151 -#define OMAP2430_CONTROL_PADCONF_AD2DSWRITE_OFFSET 0x152 -#define OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET 0x153 - -#define OMAP2430_CONTROL_PADCONF_MUX_SIZE \ - (OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET + 0x1) diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index b39efd46abf9..dd893ec4c8f2 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -87,7 +87,7 @@ void __init omap_barriers_init(void) dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA; dram_io_desc[0].pfn = __phys_to_pfn(paddr); dram_io_desc[0].length = size; - dram_io_desc[0].type = MT_MEMORY_SO; + dram_io_desc[0].type = MT_MEMORY_RW_SO; iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc)); dram_sync = (void __iomem *) dram_io_desc[0].virtual; sram_sync = (void __iomem *) OMAP4_SRAM_VA; @@ -162,6 +162,7 @@ void __iomem *omap4_get_l2cache_base(void) static void omap4_l2x0_disable(void) { + outer_flush_all(); /* Disable PL310 L2 Cache controller */ omap_smc1(0x102, 0x0); } diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index e0a398cf28d8..01ef59def44b 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -36,6 +36,7 @@ #include <linux/of.h> #include <linux/notifier.h> +#include "common.h" #include "soc.h" #include "omap_device.h" #include "omap_hwmod.h" @@ -204,6 +205,7 @@ static int _omap_device_notifier_call(struct notifier_block *nb, case BUS_NOTIFY_ADD_DEVICE: if (pdev->dev.of_node) omap_device_build_from_dt(pdev); + omap_auxdata_legacy_init(dev); /* fall through */ default: od = to_omap_device(pdev); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 8a1b5e0bad40..42d81885c700 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -686,6 +686,8 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh) if (oh->clkdm) { return oh->clkdm; } else if (oh->_clk) { + if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC) + return NULL; clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); return clk->clkdm; } @@ -1576,7 +1578,7 @@ static int _init_clkdm(struct omap_hwmod *oh) if (!oh->clkdm) { pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", oh->name, oh->clkdm_name); - return -EINVAL; + return 0; } pr_debug("omap_hwmod: %s: associated to clkdm %s\n", @@ -2791,9 +2793,7 @@ static int __init _alloc_links(struct omap_hwmod_link **ml, sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF; *sl = NULL; - *ml = alloc_bootmem(sz); - - memset(*ml, 0, sz); + *ml = memblock_virt_alloc(sz, 0); *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link); @@ -2912,9 +2912,7 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n", __func__, sz, max_ls); - linkspace = alloc_bootmem(sz); - - memset(linkspace, 0, sz); + linkspace = memblock_virt_alloc(sz, 0); return 0; } @@ -4235,6 +4233,7 @@ void __init omap_hwmod_init(void) soc_ops.assert_hardreset = _omap2_assert_hardreset; soc_ops.deassert_hardreset = _omap2_deassert_hardreset; soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; + soc_ops.init_clkdm = _init_clkdm; } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { soc_ops.enable_module = _omap4_enable_module; soc_ops.disable_module = _omap4_disable_module; diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index d8b9d60f854f..2f15979c2e9c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -108,8 +108,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { /* I2C1 */ static struct omap_hwmod omap2420_i2c1_hwmod = { .name = "i2c1", - .mpu_irqs = omap2_i2c1_mpu_irqs, - .sdma_reqs = omap2_i2c1_sdma_reqs, .main_clk = "i2c1_fck", .prcm = { .omap2 = { @@ -133,8 +131,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = { /* I2C2 */ static struct omap_hwmod omap2420_i2c2_hwmod = { .name = "i2c2", - .mpu_irqs = omap2_i2c2_mpu_irqs, - .sdma_reqs = omap2_i2c2_sdma_reqs, .main_clk = "i2c2_fck", .prcm = { .omap2 = { @@ -179,16 +175,9 @@ static struct omap_mbox_pdata omap2420_mailbox_attrs = { .info = omap2420_mailbox_info, }; -static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { - { .name = "dsp", .irq = 26 + OMAP_INTC_START, }, - { .name = "iva", .irq = 34 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2420_mailbox_hwmod = { .name = "mailbox", .class = &omap2xxx_mailbox_hwmod_class, - .mpu_irqs = omap2420_mailbox_irqs, .main_clk = "mailboxes_ick", .prcm = { .omap2 = { @@ -217,17 +206,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { }; /* mcbsp1 */ -static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { - { .name = "tx", .irq = 59 + OMAP_INTC_START, }, - { .name = "rx", .irq = 60 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2420_mcbsp1_hwmod = { .name = "mcbsp1", .class = &omap2420_mcbsp_hwmod_class, - .mpu_irqs = omap2420_mcbsp1_irqs, - .sdma_reqs = omap2_mcbsp1_sdma_reqs, .main_clk = "mcbsp1_fck", .prcm = { .omap2 = { @@ -243,17 +224,9 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = { }; /* mcbsp2 */ -static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { - { .name = "tx", .irq = 62 + OMAP_INTC_START, }, - { .name = "rx", .irq = 63 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2420_mcbsp2_hwmod = { .name = "mcbsp2", .class = &omap2420_mcbsp_hwmod_class, - .mpu_irqs = omap2420_mcbsp2_irqs, - .sdma_reqs = omap2_mcbsp2_sdma_reqs, .main_clk = "mcbsp2_fck", .prcm = { .omap2 = { @@ -283,22 +256,9 @@ static struct omap_hwmod_class omap2420_msdi_hwmod_class = { }; /* msdi1 */ -static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = { - { .irq = 83 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = { - { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */ - { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */ - { .dma_req = -1 } -}; - static struct omap_hwmod omap2420_msdi1_hwmod = { .name = "msdi1", .class = &omap2420_msdi_hwmod_class, - .mpu_irqs = omap2420_msdi1_irqs, - .sdma_reqs = omap2420_msdi1_sdma_reqs, .main_clk = "mmc_fck", .prcm = { .omap2 = { @@ -315,7 +275,6 @@ static struct omap_hwmod omap2420_msdi1_hwmod = { /* HDQ1W/1-wire */ static struct omap_hwmod omap2420_hdq1w_hwmod = { .name = "hdq1w", - .mpu_irqs = omap2_hdq1w_mpu_irqs, .main_clk = "hdq_fck", .prcm = { .omap2 = { @@ -338,7 +297,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_i2c1_hwmod, .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -347,7 +305,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_i2c2_hwmod, .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -367,111 +324,51 @@ static struct omap_hwmod_ocp_if omap2420_l3__dsp = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { - { - .pa_start = 0x48028000, - .pa_end = 0x48028000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_wkup -> timer1 */ static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_timer1_hwmod, .clk = "gpt1_ick", - .addr = omap2420_timer1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { - { - .pa_start = 0x48022000, - .pa_end = 0x4802207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_wd_timer2_hwmod, .clk = "mpu_wdt_ick", - .addr = omap2420_wd_timer2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio1 */ -static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { - { - .pa_start = 0x48018000, - .pa_end = 0x480181ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio1_hwmod, .clk = "gpios_ick", - .addr = omap2420_gpio1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio2 */ -static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { - { - .pa_start = 0x4801a000, - .pa_end = 0x4801a1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio2_hwmod, .clk = "gpios_ick", - .addr = omap2420_gpio2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio3 */ -static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { - { - .pa_start = 0x4801c000, - .pa_end = 0x4801c1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio3_hwmod, .clk = "gpios_ick", - .addr = omap2420_gpio3_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio4 */ -static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { - { - .pa_start = 0x4801e000, - .pa_end = 0x4801e1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio4_hwmod, .clk = "gpios_ick", - .addr = omap2420_gpio4_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -496,7 +393,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_mailbox_hwmod, - .addr = omap2_mailbox_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -505,7 +401,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_mcbsp1_hwmod, .clk = "mcbsp1_ick", - .addr = omap2_mcbsp1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -514,25 +409,14 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_mcbsp2_hwmod, .clk = "mcbsp2_ick", - .addr = omap2xxx_mcbsp2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = { - { - .pa_start = 0x4809c000, - .pa_end = 0x4809c000 + SZ_128 - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - /* l4_core -> msdi1 */ static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_msdi1_hwmod, .clk = "mmc_ick", - .addr = omap2420_msdi1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -541,36 +425,16 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_hdq1w_hwmod, .clk = "hdq_ick", - .addr = omap2_hdq1w_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, }; /* l4_wkup -> 32ksync_counter */ -static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = { - { - .pa_start = 0x48004000, - .pa_end = 0x4800401f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = { - { - .pa_start = 0x6800a000, - .pa_end = 0x6800afff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_counter_32k_hwmod, .clk = "sync_32k_ick", - .addr = omap2420_counter_32k_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -578,7 +442,6 @@ static struct omap_hwmod_ocp_if omap2420_l3__gpmc = { .master = &omap2xxx_l3_main_hwmod, .slave = &omap2xxx_gpmc_hwmod, .clk = "core_l3_ck", - .addr = omap2420_gpmc_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 5b9083461dc5..6d1b60902179 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -86,8 +86,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { static struct omap_hwmod omap2430_i2c1_hwmod = { .name = "i2c1", .flags = HWMOD_16BIT_REG, - .mpu_irqs = omap2_i2c1_mpu_irqs, - .sdma_reqs = omap2_i2c1_sdma_reqs, .main_clk = "i2chs1_fck", .prcm = { .omap2 = { @@ -114,8 +112,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = { static struct omap_hwmod omap2430_i2c2_hwmod = { .name = "i2c2", .flags = HWMOD_16BIT_REG, - .mpu_irqs = omap2_i2c2_mpu_irqs, - .sdma_reqs = omap2_i2c2_sdma_reqs, .main_clk = "i2chs2_fck", .prcm = { .omap2 = { @@ -131,15 +127,9 @@ static struct omap_hwmod omap2430_i2c2_hwmod = { }; /* gpio5 */ -static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { - { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */ - { .irq = -1 }, -}; - static struct omap_hwmod omap2430_gpio5_hwmod = { .name = "gpio5", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap243x_gpio5_irqs, .main_clk = "gpio5_fck", .prcm = { .omap2 = { @@ -182,15 +172,9 @@ static struct omap_mbox_pdata omap2430_mailbox_attrs = { .info = omap2430_mailbox_info, }; -static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { - { .irq = 26 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2430_mailbox_hwmod = { .name = "mailbox", .class = &omap2xxx_mailbox_hwmod_class, - .mpu_irqs = omap2430_mailbox_irqs, .main_clk = "mailboxes_ick", .prcm = { .omap2 = { @@ -205,27 +189,12 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { }; /* mcspi3 */ -static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { - { .irq = 91 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { - { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ - { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ - { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ - { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ - { .dma_req = -1 } -}; - static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { .num_chipselect = 2, }; static struct omap_hwmod omap2430_mcspi3_hwmod = { .name = "mcspi3", - .mpu_irqs = omap2430_mcspi3_mpu_irqs, - .sdma_reqs = omap2430_mcspi3_sdma_reqs, .main_clk = "mcspi3_fck", .prcm = { .omap2 = { @@ -259,16 +228,8 @@ static struct omap_hwmod_class usbotg_class = { }; /* usb_otg_hs */ -static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { - - { .name = "mc", .irq = 92 + OMAP_INTC_START, }, - { .name = "dma", .irq = 93 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2430_usbhsotg_hwmod = { .name = "usb_otg_hs", - .mpu_irqs = omap2430_usbhsotg_mpu_irqs, .main_clk = "usbhs_ick", .prcm = { .omap2 = { @@ -313,19 +274,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { }; /* mcbsp1 */ -static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { - { .name = "tx", .irq = 59 + OMAP_INTC_START, }, - { .name = "rx", .irq = 60 + OMAP_INTC_START, }, - { .name = "ovr", .irq = 61 + OMAP_INTC_START, }, - { .name = "common", .irq = 64 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2430_mcbsp1_hwmod = { .name = "mcbsp1", .class = &omap2430_mcbsp_hwmod_class, - .mpu_irqs = omap2430_mcbsp1_irqs, - .sdma_reqs = omap2_mcbsp1_sdma_reqs, .main_clk = "mcbsp1_fck", .prcm = { .omap2 = { @@ -341,18 +292,9 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = { }; /* mcbsp2 */ -static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { - { .name = "tx", .irq = 62 + OMAP_INTC_START, }, - { .name = "rx", .irq = 63 + OMAP_INTC_START, }, - { .name = "common", .irq = 16 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2430_mcbsp2_hwmod = { .name = "mcbsp2", .class = &omap2430_mcbsp_hwmod_class, - .mpu_irqs = omap2430_mcbsp2_irqs, - .sdma_reqs = omap2_mcbsp2_sdma_reqs, .main_clk = "mcbsp2_fck", .prcm = { .omap2 = { @@ -368,18 +310,9 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = { }; /* mcbsp3 */ -static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { - { .name = "tx", .irq = 89 + OMAP_INTC_START, }, - { .name = "rx", .irq = 90 + OMAP_INTC_START, }, - { .name = "common", .irq = 17 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2430_mcbsp3_hwmod = { .name = "mcbsp3", .class = &omap2430_mcbsp_hwmod_class, - .mpu_irqs = omap2430_mcbsp3_irqs, - .sdma_reqs = omap2_mcbsp3_sdma_reqs, .main_clk = "mcbsp3_fck", .prcm = { .omap2 = { @@ -395,24 +328,9 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = { }; /* mcbsp4 */ -static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { - { .name = "tx", .irq = 54 + OMAP_INTC_START, }, - { .name = "rx", .irq = 55 + OMAP_INTC_START, }, - { .name = "common", .irq = 18 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { - { .name = "rx", .dma_req = 20 }, - { .name = "tx", .dma_req = 19 }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap2430_mcbsp4_hwmod = { .name = "mcbsp4", .class = &omap2430_mcbsp_hwmod_class, - .mpu_irqs = omap2430_mcbsp4_irqs, - .sdma_reqs = omap2430_mcbsp4_sdma_chs, .main_clk = "mcbsp4_fck", .prcm = { .omap2 = { @@ -428,24 +346,9 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = { }; /* mcbsp5 */ -static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { - { .name = "tx", .irq = 81 + OMAP_INTC_START, }, - { .name = "rx", .irq = 82 + OMAP_INTC_START, }, - { .name = "common", .irq = 19 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { - { .name = "rx", .dma_req = 22 }, - { .name = "tx", .dma_req = 21 }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap2430_mcbsp5_hwmod = { .name = "mcbsp5", .class = &omap2430_mcbsp_hwmod_class, - .mpu_irqs = omap2430_mcbsp5_irqs, - .sdma_reqs = omap2430_mcbsp5_sdma_chs, .main_clk = "mcbsp5_fck", .prcm = { .omap2 = { @@ -478,17 +381,6 @@ static struct omap_hwmod_class omap2430_mmc_class = { }; /* MMC/SD/SDIO1 */ -static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { - { .irq = 83 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { - { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ - { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { { .role = "dbck", .clk = "mmchsdb1_fck" }, }; @@ -500,8 +392,6 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = { static struct omap_hwmod omap2430_mmc1_hwmod = { .name = "mmc1", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2430_mmc1_mpu_irqs, - .sdma_reqs = omap2430_mmc1_sdma_reqs, .opt_clks = omap2430_mmc1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), .main_clk = "mmchs1_fck", @@ -519,17 +409,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = { }; /* MMC/SD/SDIO2 */ -static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { - { .irq = 86 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { - { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ - { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { { .role = "dbck", .clk = "mmchsdb2_fck" }, }; @@ -537,8 +416,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { static struct omap_hwmod omap2430_mmc2_hwmod = { .name = "mmc2", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2430_mmc2_mpu_irqs, - .sdma_reqs = omap2430_mmc2_sdma_reqs, .opt_clks = omap2430_mmc2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), .main_clk = "mmchs2_fck", @@ -557,7 +434,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = { /* HDQ1W/1-wire */ static struct omap_hwmod omap2430_hdq1w_hwmod = { .name = "hdq1w", - .mpu_irqs = omap2_hdq1w_mpu_irqs, .main_clk = "hdq_fck", .prcm = { .omap2 = { @@ -589,7 +465,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_i2c1_hwmod, .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -598,25 +473,14 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_i2c2_hwmod, .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { - { - .pa_start = OMAP243X_HS_BASE, - .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_core ->usbhsotg interface */ static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_usbhsotg_hwmod, .clk = "usb_l4_ick", - .addr = omap2430_usbhsotg_addrs, .user = OCP_USER_MPU, }; @@ -625,7 +489,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mmc1_hwmod, .clk = "mmchs1_ick", - .addr = omap2430_mmc1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -634,7 +497,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mmc2_hwmod, .clk = "mmchs2_ick", - .addr = omap2430_mmc2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -643,7 +505,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mcspi3_hwmod, .clk = "mcspi3_ick", - .addr = omap2430_mcspi3_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -655,129 +516,59 @@ static struct omap_hwmod_ocp_if omap2430_l3__iva = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { - { - .pa_start = 0x49018000, - .pa_end = 0x49018000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_wkup -> timer1 */ static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_timer1_hwmod, .clk = "gpt1_ick", - .addr = omap2430_timer1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { - { - .pa_start = 0x49016000, - .pa_end = 0x4901607f, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_wd_timer2_hwmod, .clk = "mpu_wdt_ick", - .addr = omap2430_wd_timer2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio1 */ -static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { - { - .pa_start = 0x4900C000, - .pa_end = 0x4900C1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio1_hwmod, .clk = "gpios_ick", - .addr = omap2430_gpio1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio2 */ -static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { - { - .pa_start = 0x4900E000, - .pa_end = 0x4900E1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio2_hwmod, .clk = "gpios_ick", - .addr = omap2430_gpio2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio3 */ -static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { - { - .pa_start = 0x49010000, - .pa_end = 0x490101ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio3_hwmod, .clk = "gpios_ick", - .addr = omap2430_gpio3_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio4 */ -static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { - { - .pa_start = 0x49012000, - .pa_end = 0x490121ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio4_hwmod, .clk = "gpios_ick", - .addr = omap2430_gpio4_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_core -> gpio5 */ -static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { - { - .pa_start = 0x480B6000, - .pa_end = 0x480B61ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_gpio5_hwmod, .clk = "gpio5_ick", - .addr = omap2430_gpio5_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -802,7 +593,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mailbox_hwmod, - .addr = omap2_mailbox_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -811,7 +601,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mcbsp1_hwmod, .clk = "mcbsp1_ick", - .addr = omap2_mcbsp1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -820,64 +609,30 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mcbsp2_hwmod, .clk = "mcbsp2_ick", - .addr = omap2xxx_mcbsp2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { - { - .name = "mpu", - .pa_start = 0x4808C000, - .pa_end = 0x4808C0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_core -> mcbsp3 */ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mcbsp3_hwmod, .clk = "mcbsp3_ick", - .addr = omap2430_mcbsp3_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { - { - .name = "mpu", - .pa_start = 0x4808E000, - .pa_end = 0x4808E0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_core -> mcbsp4 */ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mcbsp4_hwmod, .clk = "mcbsp4_ick", - .addr = omap2430_mcbsp4_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { - { - .name = "mpu", - .pa_start = 0x48096000, - .pa_end = 0x480960ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_core -> mcbsp5 */ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mcbsp5_hwmod, .clk = "mcbsp5_ick", - .addr = omap2430_mcbsp5_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -886,35 +641,15 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_hdq1w_hwmod, .clk = "hdq_ick", - .addr = omap2_hdq1w_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, }; /* l4_wkup -> 32ksync_counter */ -static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = { - { - .pa_start = 0x49020000, - .pa_end = 0x4902001f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = { - { - .pa_start = 0x6e000000, - .pa_end = 0x6e000fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_counter_32k_hwmod, .clk = "sync_32k_ick", - .addr = omap2430_counter_32k_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -922,7 +657,6 @@ static struct omap_hwmod_ocp_if omap2430_l3__gpmc = { .master = &omap2xxx_l3_main_hwmod, .slave = &omap2xxx_gpmc_hwmod, .clk = "core_l3_ck", - .addr = omap2430_gpmc_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c index 5fd40d4a989e..656861c29d5c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c @@ -20,142 +20,6 @@ #include "omap_hwmod_common_data.h" -static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = { - { - .pa_start = OMAP2_UART1_BASE, - .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = { - { - .pa_start = OMAP2_UART2_BASE, - .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = { - { - .pa_start = OMAP2_UART3_BASE, - .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = { - { - .pa_start = 0x4802a000, - .pa_end = 0x4802a000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = { - { - .pa_start = 0x48078000, - .pa_end = 0x48078000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = { - { - .pa_start = 0x4807a000, - .pa_end = 0x4807a000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = { - { - .pa_start = 0x4807c000, - .pa_end = 0x4807c000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = { - { - .pa_start = 0x4807e000, - .pa_end = 0x4807e000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = { - { - .pa_start = 0x48080000, - .pa_end = 0x48080000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = { - { - .pa_start = 0x48082000, - .pa_end = 0x48082000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = { - { - .pa_start = 0x48084000, - .pa_end = 0x48084000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = { - { - .name = "mpu", - .pa_start = 0x48076000, - .pa_end = 0x480760ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2_rng_addr_space[] = { - { - .pa_start = 0x480a0000, - .pa_end = 0x480a004f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = { - { - .pa_start = 0x480a4000, - .pa_end = 0x480a4000 + 0x64 - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = { - { - .pa_start = 0x480a6000, - .pa_end = 0x480a6000 + 0x50 - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* * Common interconnect data */ @@ -182,7 +46,7 @@ struct omap_hwmod_ocp_if omap2xxx_dss__l3 = { .omap2 = { .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, .flags = OMAP_FIREWALL_L3, - } + }, }, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -199,7 +63,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_uart1_hwmod, .clk = "uart1_ick", - .addr = omap2xxx_uart1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -208,7 +71,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_uart2_hwmod, .clk = "uart2_ick", - .addr = omap2xxx_uart2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -217,7 +79,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_uart3_hwmod, .clk = "uart3_ick", - .addr = omap2xxx_uart3_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -226,7 +87,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_mcspi1_hwmod, .clk = "mcspi1_ick", - .addr = omap2_mcspi1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -235,7 +95,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_mcspi2_hwmod, .clk = "mcspi2_ick", - .addr = omap2_mcspi2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -244,7 +103,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer2_hwmod, .clk = "gpt2_ick", - .addr = omap2xxx_timer2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -253,7 +111,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer3_hwmod, .clk = "gpt3_ick", - .addr = omap2xxx_timer3_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -262,7 +119,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer4_hwmod, .clk = "gpt4_ick", - .addr = omap2xxx_timer4_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -271,7 +127,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer5_hwmod, .clk = "gpt5_ick", - .addr = omap2xxx_timer5_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -280,7 +135,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer6_hwmod, .clk = "gpt6_ick", - .addr = omap2xxx_timer6_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -289,7 +143,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer7_hwmod, .clk = "gpt7_ick", - .addr = omap2xxx_timer7_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -298,7 +151,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer8_hwmod, .clk = "gpt8_ick", - .addr = omap2xxx_timer8_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -307,7 +159,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer9_hwmod, .clk = "gpt9_ick", - .addr = omap2xxx_timer9_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -316,7 +167,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer10_hwmod, .clk = "gpt10_ick", - .addr = omap2_timer10_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -325,7 +175,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer11_hwmod, .clk = "gpt11_ick", - .addr = omap2_timer11_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -334,7 +183,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer12_hwmod, .clk = "gpt12_ick", - .addr = omap2xxx_timer12_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -348,7 +196,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = { .omap2 = { .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, .flags = OMAP_FIREWALL_L4, - } + }, }, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -363,7 +211,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = { .omap2 = { .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, .flags = OMAP_FIREWALL_L4, - } + }, }, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -378,7 +226,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = { .omap2 = { .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, .flags = OMAP_FIREWALL_L4, - } + }, }, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -393,7 +241,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = { .omap2 = { .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, .flags = OMAP_FIREWALL_L4, - } + }, }, .flags = OCPIF_SWSUP_IDLE, .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -404,7 +252,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_rng_hwmod, .clk = "rng_ick", - .addr = omap2_rng_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -413,7 +260,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_sham_hwmod, .clk = "sha_ick", - .addr = omap2xxx_sham_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -422,6 +268,5 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_aes_hwmod, .clk = "aes_ick", - .addr = omap2xxx_aes_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index 56cebb05509e..8821b9d6bae4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -20,14 +20,9 @@ #include "prm-regbits-24xx.h" #include "wd_timer.h" -struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = { - { .irq = 48 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { { .name = "dispc", .dma_req = 5 }, - { .dma_req = -1 } + { .dma_req = -1, }, }; /* @@ -219,14 +214,8 @@ struct omap_hwmod omap2xxx_l4_wkup_hwmod = { }; /* MPU */ -static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = { - { .name = "pmu", .irq = 3 + OMAP_INTC_START }, - { .irq = -1 } -}; - struct omap_hwmod omap2xxx_mpu_hwmod = { .name = "mpu", - .mpu_irqs = omap2xxx_mpu_irqs, .class = &mpu_hwmod_class, .main_clk = "mpu_ck", }; @@ -256,7 +245,6 @@ static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { struct omap_hwmod omap2xxx_timer1_hwmod = { .name = "timer1", - .mpu_irqs = omap2_timer1_mpu_irqs, .main_clk = "gpt1_fck", .prcm = { .omap2 = { @@ -276,7 +264,6 @@ struct omap_hwmod omap2xxx_timer1_hwmod = { struct omap_hwmod omap2xxx_timer2_hwmod = { .name = "timer2", - .mpu_irqs = omap2_timer2_mpu_irqs, .main_clk = "gpt2_fck", .prcm = { .omap2 = { @@ -295,7 +282,6 @@ struct omap_hwmod omap2xxx_timer2_hwmod = { struct omap_hwmod omap2xxx_timer3_hwmod = { .name = "timer3", - .mpu_irqs = omap2_timer3_mpu_irqs, .main_clk = "gpt3_fck", .prcm = { .omap2 = { @@ -314,7 +300,6 @@ struct omap_hwmod omap2xxx_timer3_hwmod = { struct omap_hwmod omap2xxx_timer4_hwmod = { .name = "timer4", - .mpu_irqs = omap2_timer4_mpu_irqs, .main_clk = "gpt4_fck", .prcm = { .omap2 = { @@ -333,7 +318,6 @@ struct omap_hwmod omap2xxx_timer4_hwmod = { struct omap_hwmod omap2xxx_timer5_hwmod = { .name = "timer5", - .mpu_irqs = omap2_timer5_mpu_irqs, .main_clk = "gpt5_fck", .prcm = { .omap2 = { @@ -353,7 +337,6 @@ struct omap_hwmod omap2xxx_timer5_hwmod = { struct omap_hwmod omap2xxx_timer6_hwmod = { .name = "timer6", - .mpu_irqs = omap2_timer6_mpu_irqs, .main_clk = "gpt6_fck", .prcm = { .omap2 = { @@ -373,7 +356,6 @@ struct omap_hwmod omap2xxx_timer6_hwmod = { struct omap_hwmod omap2xxx_timer7_hwmod = { .name = "timer7", - .mpu_irqs = omap2_timer7_mpu_irqs, .main_clk = "gpt7_fck", .prcm = { .omap2 = { @@ -393,7 +375,6 @@ struct omap_hwmod omap2xxx_timer7_hwmod = { struct omap_hwmod omap2xxx_timer8_hwmod = { .name = "timer8", - .mpu_irqs = omap2_timer8_mpu_irqs, .main_clk = "gpt8_fck", .prcm = { .omap2 = { @@ -413,7 +394,6 @@ struct omap_hwmod omap2xxx_timer8_hwmod = { struct omap_hwmod omap2xxx_timer9_hwmod = { .name = "timer9", - .mpu_irqs = omap2_timer9_mpu_irqs, .main_clk = "gpt9_fck", .prcm = { .omap2 = { @@ -433,7 +413,6 @@ struct omap_hwmod omap2xxx_timer9_hwmod = { struct omap_hwmod omap2xxx_timer10_hwmod = { .name = "timer10", - .mpu_irqs = omap2_timer10_mpu_irqs, .main_clk = "gpt10_fck", .prcm = { .omap2 = { @@ -453,7 +432,6 @@ struct omap_hwmod omap2xxx_timer10_hwmod = { struct omap_hwmod omap2xxx_timer11_hwmod = { .name = "timer11", - .mpu_irqs = omap2_timer11_mpu_irqs, .main_clk = "gpt11_fck", .prcm = { .omap2 = { @@ -473,7 +451,6 @@ struct omap_hwmod omap2xxx_timer11_hwmod = { struct omap_hwmod omap2xxx_timer12_hwmod = { .name = "timer12", - .mpu_irqs = omap2xxx_timer12_mpu_irqs, .main_clk = "gpt12_fck", .prcm = { .omap2 = { @@ -509,8 +486,6 @@ struct omap_hwmod omap2xxx_wd_timer2_hwmod = { struct omap_hwmod omap2xxx_uart1_hwmod = { .name = "uart1", - .mpu_irqs = omap2_uart1_mpu_irqs, - .sdma_reqs = omap2_uart1_sdma_reqs, .main_clk = "uart1_fck", .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, .prcm = { @@ -529,8 +504,6 @@ struct omap_hwmod omap2xxx_uart1_hwmod = { struct omap_hwmod omap2xxx_uart2_hwmod = { .name = "uart2", - .mpu_irqs = omap2_uart2_mpu_irqs, - .sdma_reqs = omap2_uart2_sdma_reqs, .main_clk = "uart2_fck", .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT, .prcm = { @@ -549,8 +522,6 @@ struct omap_hwmod omap2xxx_uart2_hwmod = { struct omap_hwmod omap2xxx_uart3_hwmod = { .name = "uart3", - .mpu_irqs = omap2_uart3_mpu_irqs, - .sdma_reqs = omap2_uart3_sdma_reqs, .main_clk = "uart3_fck", .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT, .prcm = { @@ -610,7 +581,7 @@ struct omap_hwmod omap2xxx_dss_dispc_hwmod = { }, }, .flags = HWMOD_NO_IDLEST, - .dev_attr = &omap2_3_dss_dispc_dev_attr + .dev_attr = &omap2_3_dss_dispc_dev_attr, }; static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { @@ -657,7 +628,6 @@ struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = { struct omap_hwmod omap2xxx_gpio1_hwmod = { .name = "gpio1", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio1_irqs, .main_clk = "gpios_fck", .prcm = { .omap2 = { @@ -676,7 +646,6 @@ struct omap_hwmod omap2xxx_gpio1_hwmod = { struct omap_hwmod omap2xxx_gpio2_hwmod = { .name = "gpio2", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio2_irqs, .main_clk = "gpios_fck", .prcm = { .omap2 = { @@ -695,7 +664,6 @@ struct omap_hwmod omap2xxx_gpio2_hwmod = { struct omap_hwmod omap2xxx_gpio3_hwmod = { .name = "gpio3", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio3_irqs, .main_clk = "gpios_fck", .prcm = { .omap2 = { @@ -714,7 +682,6 @@ struct omap_hwmod omap2xxx_gpio3_hwmod = { struct omap_hwmod omap2xxx_gpio4_hwmod = { .name = "gpio4", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio4_irqs, .main_clk = "gpios_fck", .prcm = { .omap2 = { @@ -736,8 +703,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { struct omap_hwmod omap2xxx_mcspi1_hwmod = { .name = "mcspi1", - .mpu_irqs = omap2_mcspi1_mpu_irqs, - .sdma_reqs = omap2_mcspi1_sdma_reqs, .main_clk = "mcspi1_fck", .prcm = { .omap2 = { @@ -759,8 +724,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { struct omap_hwmod omap2xxx_mcspi2_hwmod = { .name = "mcspi2", - .mpu_irqs = omap2_mcspi2_mpu_irqs, - .sdma_reqs = omap2_mcspi2_sdma_reqs, .main_clk = "mcspi2_fck", .prcm = { .omap2 = { @@ -795,15 +758,9 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = { }; /* gpmc */ -static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = { - { .irq = 20 }, - { .irq = -1 } -}; - struct omap_hwmod omap2xxx_gpmc_hwmod = { .name = "gpmc", .class = &omap2xxx_gpmc_hwmod_class, - .mpu_irqs = omap2xxx_gpmc_irqs, .main_clk = "gpmc_fck", /* * XXX HWMOD_INIT_NO_RESET should not be needed for this IP @@ -840,14 +797,8 @@ static struct omap_hwmod_class omap2_rng_hwmod_class = { .sysc = &omap2_rng_sysc, }; -static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = { - { .irq = 52 }, - { .irq = -1 } -}; - struct omap_hwmod omap2xxx_rng_hwmod = { .name = "rng", - .mpu_irqs = omap2_rng_mpu_irqs, .main_clk = "l4_ck", .prcm = { .omap2 = { @@ -884,20 +835,8 @@ static struct omap_hwmod_class omap2xxx_sham_class = { .sysc = &omap2_sham_sysc, }; -static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = { - { .irq = 51 + OMAP_INTC_START, }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = { - { .name = "rx", .dma_req = 13 }, - { .dma_req = -1 } -}; - struct omap_hwmod omap2xxx_sham_hwmod = { .name = "sham", - .mpu_irqs = omap2_sham_mpu_irqs, - .sdma_reqs = omap2_sham_sdma_chs, .main_clk = "l4_ck", .prcm = { .omap2 = { @@ -927,15 +866,8 @@ static struct omap_hwmod_class omap2xxx_aes_class = { .sysc = &omap2_aes_sysc, }; -static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = { - { .name = "tx", .dma_req = 9 }, - { .name = "rx", .dma_req = 10 }, - { .dma_req = -1 } -}; - struct omap_hwmod omap2xxx_aes_hwmod = { .name = "aes", - .sdma_reqs = omap2_aes_sdma_chs, .main_clk = "l4_ck", .prcm = { .omap2 = { diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index d33742908f97..4c3b1e6df508 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -2165,7 +2165,7 @@ static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = { }; static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = { - { .irq = 20 }, + { .irq = 20 + OMAP_INTC_START, }, { .irq = -1 } }; @@ -2999,7 +2999,7 @@ static struct omap_mmu_dev_attr mmu_isp_dev_attr = { static struct omap_hwmod omap3xxx_mmu_isp_hwmod; static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = { - { .irq = 24 }, + { .irq = 24 + OMAP_INTC_START, }, { .irq = -1 } }; @@ -3041,7 +3041,7 @@ static struct omap_mmu_dev_attr mmu_iva_dev_attr = { static struct omap_hwmod omap3xxx_mmu_iva_hwmod; static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = { - { .irq = 28 }, + { .irq = 28 + OMAP_INTC_START, }, { .irq = -1 } }; diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index db32d5380b11..18f333c440db 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1637,7 +1637,7 @@ static struct omap_hwmod dra7xx_uart1_hwmod = { .class = &dra7xx_uart_hwmod_class, .clkdm_name = "l4per_clkdm", .main_clk = "uart1_gfclk_mux", - .flags = HWMOD_SWSUP_SIDLE_ACT, + .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS, .prcm = { .omap4 = { .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET, diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index 6e04ff7065e1..2c38c6b0ee03 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -18,9 +18,6 @@ #include "common.h" #include "display.h" -/* Common address space across OMAP2xxx */ -extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[]; - /* Common address space across OMAP2xxx/3xxx */ extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[]; extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[]; @@ -41,8 +38,6 @@ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[]; extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[]; /* Common IP block data across OMAP2xxx */ -extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[]; -extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[]; extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr; extern struct omap_hwmod omap2xxx_l3_main_hwmod; extern struct omap_hwmod omap2xxx_l4_core_hwmod; diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 39f020c982e8..3d5b24dcd9a4 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -8,6 +8,7 @@ * published by the Free Software Foundation. */ #include <linux/clk.h> +#include <linux/davinci_emac.h> #include <linux/gpio.h> #include <linux/init.h> #include <linux/kernel.h> @@ -16,6 +17,7 @@ #include <linux/platform_data/pinctrl-single.h> +#include "am35xx.h" #include "common.h" #include "common-board-devices.h" #include "dss-common.h" @@ -26,6 +28,9 @@ struct pdata_init { void (*fn)(void); }; +struct of_dev_auxdata omap_auxdata_lookup[]; +static struct twl4030_gpio_platform_data twl_gpio_auxdata; + /* * Create alias for USB host PHY clock. * Remove this when clock phandle can be provided via DT @@ -68,6 +73,15 @@ static inline void legacy_init_wl12xx(unsigned ref_clock, } #endif +#ifdef CONFIG_MACH_NOKIA_N8X0 +static void __init omap2420_n8x0_legacy_init(void) +{ + omap_auxdata_lookup[0].platform_data = n8x0_legacy_init(); +} +#else +#define omap2420_n8x0_legacy_init NULL +#endif + #ifdef CONFIG_ARCH_OMAP3 static void __init hsmmc2_internal_input_clk(void) { @@ -78,6 +92,33 @@ static void __init hsmmc2_internal_input_clk(void) omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1); } +static int omap3_sbc_t3730_twl_callback(struct device *dev, + unsigned gpio, + unsigned ngpio) +{ + int res; + + res = gpio_request_one(gpio + 2, GPIOF_OUT_INIT_HIGH, + "wlan rst"); + if (res) + return res; + + gpio_export(gpio, 0); + + return 0; +} + +static void __init omap3_sbc_t3730_twl_init(void) +{ + twl_gpio_auxdata.setup = omap3_sbc_t3730_twl_callback; +} + +static void __init omap3_sbc_t3730_legacy_init(void) +{ + legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 136); + omap_ads7846_init(1, 57, 0, NULL); +} + static void __init omap3_igep0020_legacy_init(void) { omap3_igep2_display_init_of(); @@ -92,6 +133,42 @@ static void __init omap3_zoom_legacy_init(void) { legacy_init_wl12xx(WL12XX_REFCLOCK_26, 0, 162); } + +static void am35xx_enable_emac_int(void) +{ + u32 v; + + v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR | + AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR); + omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR); + omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */ +} + +static void am35xx_disable_emac_int(void) +{ + u32 v; + + v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR); + omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR); + omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */ +} + +static struct emac_platform_data am35xx_emac_pdata = { + .interrupt_enable = am35xx_enable_emac_int, + .interrupt_disable = am35xx_disable_emac_int, +}; + +static void __init am3517_evm_legacy_init(void) +{ + u32 v; + + v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); + v &= ~AM35XX_CPGMACSS_SW_RST; + omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET); + omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */ +} #endif /* CONFIG_ARCH_OMAP3 */ #ifdef CONFIG_ARCH_OMAP4 @@ -125,10 +202,48 @@ void omap_pcs_legacy_init(int irq, void (*rearm)(void)) pcs_pdata.rearm = rearm; } +/* + * GPIOs for TWL are initialized by the I2C bus and need custom + * handing until DSS has device tree bindings. + */ +void omap_auxdata_legacy_init(struct device *dev) +{ + if (dev->platform_data) + return; + + if (strcmp("twl4030-gpio", dev_name(dev))) + return; + + dev->platform_data = &twl_gpio_auxdata; +} + +/* + * Few boards still need auxdata populated before we populate + * the dev entries in of_platform_populate(). + */ +static struct pdata_init auxdata_quirks[] __initdata = { +#ifdef CONFIG_SOC_OMAP2420 + { "nokia,n800", omap2420_n8x0_legacy_init, }, + { "nokia,n810", omap2420_n8x0_legacy_init, }, + { "nokia,n810-wimax", omap2420_n8x0_legacy_init, }, +#endif +#ifdef CONFIG_ARCH_OMAP3 + { "compulab,omap3-sbc-t3730", omap3_sbc_t3730_twl_init, }, +#endif + { /* sentinel */ }, +}; + struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { +#ifdef CONFIG_MACH_NOKIA_N8X0 + OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL), +#endif #ifdef CONFIG_ARCH_OMAP3 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata), OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata), + /* Only on am3517 */ + OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL), + OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0", + &am35xx_emac_pdata), #endif #ifdef CONFIG_ARCH_OMAP4 OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata), @@ -137,14 +252,20 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { { /* sentinel */ }, }; +/* + * Few boards still need to initialize some legacy devices with + * platform data until the drivers support device tree. + */ static struct pdata_init pdata_quirks[] __initdata = { #ifdef CONFIG_ARCH_OMAP3 + { "compulab,omap3-sbc-t3730", omap3_sbc_t3730_legacy_init, }, { "nokia,omap3-n900", hsmmc2_internal_input_clk, }, { "nokia,omap3-n9", hsmmc2_internal_input_clk, }, { "nokia,omap3-n950", hsmmc2_internal_input_clk, }, { "isee,omap3-igep0020", omap3_igep0020_legacy_init, }, { "ti,omap3-evm-37xx", omap3_evm_legacy_init, }, { "ti,omap3-zoom3", omap3_zoom_legacy_init, }, + { "ti,am3517-evm", am3517_evm_legacy_init, }, #endif #ifdef CONFIG_ARCH_OMAP4 { "ti,omap4-sdp", omap4_sdp_legacy_init, }, @@ -156,14 +277,8 @@ static struct pdata_init pdata_quirks[] __initdata = { { /* sentinel */ }, }; -void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table) +static void pdata_quirks_check(struct pdata_init *quirks) { - struct pdata_init *quirks = pdata_quirks; - - omap_sdrc_init(NULL, NULL); - of_platform_populate(NULL, omap_dt_match_table, - omap_auxdata_lookup, NULL); - while (quirks->compatible) { if (of_machine_is_compatible(quirks->compatible)) { if (quirks->fn) @@ -173,3 +288,12 @@ void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table) quirks++; } } + +void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table) +{ + omap_sdrc_init(NULL, NULL); + pdata_quirks_check(auxdata_quirks); + of_platform_populate(NULL, omap_dt_match_table, + omap_auxdata_lookup, NULL); + pdata_quirks_check(pdata_quirks); +} diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index ac25ae6667cf..623db40fdbbd 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -18,6 +18,7 @@ # ifndef __ASSEMBLER__ extern void __iomem *prm_base; extern void omap2_set_globals_prm(void __iomem *prm); +int of_prcm_init(void); # endif diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index a2e1174ad1b6..b4c4ab9c8044 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -23,6 +23,10 @@ #include <linux/irq.h> #include <linux/interrupt.h> #include <linux/slab.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/clk-provider.h> +#include <linux/clk/ti.h> #include "soc.h" #include "prm2xxx_3xxx.h" @@ -30,6 +34,7 @@ #include "prm3xxx.h" #include "prm44xx.h" #include "common.h" +#include "clock.h" /* * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs @@ -464,3 +469,64 @@ int prm_unregister(struct prm_ll_data *pld) return 0; } + +static struct of_device_id omap_prcm_dt_match_table[] = { + { .compatible = "ti,am3-prcm" }, + { .compatible = "ti,am3-scrm" }, + { .compatible = "ti,am4-prcm" }, + { .compatible = "ti,am4-scrm" }, + { .compatible = "ti,omap3-prm" }, + { .compatible = "ti,omap3-cm" }, + { .compatible = "ti,omap3-scrm" }, + { .compatible = "ti,omap4-cm1" }, + { .compatible = "ti,omap4-prm" }, + { .compatible = "ti,omap4-cm2" }, + { .compatible = "ti,omap4-scrm" }, + { .compatible = "ti,omap5-prm" }, + { .compatible = "ti,omap5-cm-core-aon" }, + { .compatible = "ti,omap5-scrm" }, + { .compatible = "ti,omap5-cm-core" }, + { .compatible = "ti,dra7-prm" }, + { .compatible = "ti,dra7-cm-core-aon" }, + { .compatible = "ti,dra7-cm-core" }, + { } +}; + +static struct clk_hw_omap memmap_dummy_ck = { + .flags = MEMMAP_ADDRESSING, +}; + +static u32 prm_clk_readl(void __iomem *reg) +{ + return omap2_clk_readl(&memmap_dummy_ck, reg); +} + +static void prm_clk_writel(u32 val, void __iomem *reg) +{ + omap2_clk_writel(val, &memmap_dummy_ck, reg); +} + +static struct ti_clk_ll_ops omap_clk_ll_ops = { + .clk_readl = prm_clk_readl, + .clk_writel = prm_clk_writel, +}; + +int __init of_prcm_init(void) +{ + struct device_node *np; + void __iomem *mem; + int memmap_index = 0; + + ti_clk_ll_ops = &omap_clk_ll_ops; + + for_each_matching_node(np, omap_prcm_dt_match_table) { + mem = of_iomap(np, 0); + clk_memmaps[memmap_index] = mem; + ti_dt_clk_init_provider(np, memmap_index); + memmap_index++; + } + + ti_dt_clockdomains_setup(); + + return 0; +} diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 3ca81e0ada5e..74044aaf438b 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -379,7 +379,7 @@ static struct clocksource clocksource_gpt = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; -static u32 notrace dmtimer_read_sched_clock(void) +static u64 notrace dmtimer_read_sched_clock(void) { if (clksrc.reserved) return __omap_dm_timer_read_counter(&clksrc, @@ -471,7 +471,7 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id, __omap_dm_timer_load_start(&clksrc, OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, OMAP_TIMER_NONPOSTED); - setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); + sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate); if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) pr_err("Could not register clocksource %s\n", @@ -570,8 +570,7 @@ static inline void __init realtime_counter_init(void) clksrc_nr, clksrc_src, clksrc_prop) \ void __init omap##name##_gptimer_timer_init(void) \ { \ - if (omap_clk_init) \ - omap_clk_init(); \ + omap_clk_init(); \ omap_dmtimer_init(); \ omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ @@ -582,8 +581,7 @@ void __init omap##name##_gptimer_timer_init(void) \ clksrc_nr, clksrc_src, clksrc_prop) \ void __init omap##name##_sync32k_timer_init(void) \ { \ - if (omap_clk_init) \ - omap_clk_init(); \ + omap_clk_init(); \ omap_dmtimer_init(); \ omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ /* Enable the use of clocksource="gp_timer" kernel parameter */ \ |
