diff options
Diffstat (limited to 'arch/arm/mach-exynos4/include/mach')
18 files changed, 853 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos4/include/mach/debug-macro.S b/arch/arm/mach-exynos4/include/mach/debug-macro.S new file mode 100644 index 000000000000..58bbd049a6c4 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/debug-macro.S @@ -0,0 +1,35 @@ +/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* pull in the relevant register and map files. */ + +#include <mach/map.h> + + /* note, for the boot process to work we have to keep the UART + * virtual address aligned to an 1MiB boundary for the L1 + * mapping the head code makes. We keep the UART virtual address + * aligned and add in the offset when we load the value here. + */ + + .macro addruart, rp, rv + ldreq \rp, = S3C_PA_UART + ldrne \rv, = S3C_VA_UART +#if CONFIG_DEBUG_S3C_UART != 0 + add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART) + add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART) +#endif + .endm + +#define fifo_full fifo_full_s5pv210 +#define fifo_level fifo_level_s5pv210 + +#include <plat/debug-macro.S> diff --git a/arch/arm/mach-exynos4/include/mach/dma.h b/arch/arm/mach-exynos4/include/mach/dma.h new file mode 100644 index 000000000000..81209eb1409b --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/dma.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __MACH_DMA_H +#define __MACH_DMA_H + +/* This platform uses the common S3C DMA API driver for PL330 */ +#include <plat/s3c-dma-pl330.h> + +#endif /* __MACH_DMA_H */ diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S new file mode 100644 index 000000000000..d8f38c2e5654 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S @@ -0,0 +1,84 @@ +/* arch/arm/mach-exynos4/include/mach/entry-macro.S + * + * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for EXYNOS4 platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +#include <mach/hardware.h> +#include <asm/hardware/gic.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =gic_cpu_base_addr + ldr \base, [\base] + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + /* + * The interrupt numbering scheme is defined in the + * interrupt controller spec. To wit: + * + * Interrupts 0-15 are IPI + * 16-28 are reserved + * 29-31 are local. We allow 30 to be used for the watchdog. + * 32-1020 are global + * 1021-1022 are reserved + * 1023 is "spurious" (no interrupt) + * + * For now, we ignore all local interrupts so only return an interrupt if it's + * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. + * + * A simple read from the controller will tell us the number of the highest + * priority enabled interrupt. We then just need to check whether it is in the + * valid range for an IRQ (30-1020 inclusive). + */ + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ + + ldr \tmp, =1021 + + bic \irqnr, \irqstat, #0x1c00 + + cmp \irqnr, #29 + cmpcc \irqnr, \irqnr + cmpne \irqnr, \tmp + cmpcs \irqnr, \irqnr + addne \irqnr, \irqnr, #32 + + .endm + + /* We assume that irqstat (the raw value of the IRQ acknowledge + * register) is preserved from the macro above. + * If there is an IPI, we immediately signal end of interrupt on the + * controller, since this requires the original irqstat value which + * we won't easily be able to recreate later. + */ + + .macro test_for_ipi, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #16 + strcc \irqstat, [\base, #GIC_CPU_EOI] + cmpcs \irqnr, \irqnr + .endm + + /* As above, this assumes that irqstat and base are preserved.. */ + + .macro test_for_ltirq, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + mov \tmp, #0 + cmp \irqnr, #29 + moveq \tmp, #1 + streq \irqstat, [\base, #GIC_CPU_EOI] + cmp \tmp, #0 + .endm diff --git a/arch/arm/mach-exynos4/include/mach/gpio.h b/arch/arm/mach-exynos4/include/mach/gpio.h new file mode 100644 index 000000000000..16082998bcd8 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/gpio.h @@ -0,0 +1,135 @@ +/* linux/arch/arm/mach-exynos4/include/mach/gpio.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - GPIO lib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H __FILE__ + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq + +/* Practically, GPIO banks upto GPZ are the configurable gpio banks */ + +/* GPIO bank sizes */ +#define EXYNOS4_GPIO_A0_NR (8) +#define EXYNOS4_GPIO_A1_NR (6) +#define EXYNOS4_GPIO_B_NR (8) +#define EXYNOS4_GPIO_C0_NR (5) +#define EXYNOS4_GPIO_C1_NR (5) +#define EXYNOS4_GPIO_D0_NR (4) +#define EXYNOS4_GPIO_D1_NR (4) +#define EXYNOS4_GPIO_E0_NR (5) +#define EXYNOS4_GPIO_E1_NR (8) +#define EXYNOS4_GPIO_E2_NR (6) +#define EXYNOS4_GPIO_E3_NR (8) +#define EXYNOS4_GPIO_E4_NR (8) +#define EXYNOS4_GPIO_F0_NR (8) +#define EXYNOS4_GPIO_F1_NR (8) +#define EXYNOS4_GPIO_F2_NR (8) +#define EXYNOS4_GPIO_F3_NR (6) +#define EXYNOS4_GPIO_J0_NR (8) +#define EXYNOS4_GPIO_J1_NR (5) +#define EXYNOS4_GPIO_K0_NR (7) +#define EXYNOS4_GPIO_K1_NR (7) +#define EXYNOS4_GPIO_K2_NR (7) +#define EXYNOS4_GPIO_K3_NR (7) +#define EXYNOS4_GPIO_L0_NR (8) +#define EXYNOS4_GPIO_L1_NR (3) +#define EXYNOS4_GPIO_L2_NR (8) +#define EXYNOS4_GPIO_X0_NR (8) +#define EXYNOS4_GPIO_X1_NR (8) +#define EXYNOS4_GPIO_X2_NR (8) +#define EXYNOS4_GPIO_X3_NR (8) +#define EXYNOS4_GPIO_Z_NR (7) + +/* GPIO bank numbers */ + +#define EXYNOS4_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) + +enum s5p_gpio_number { + EXYNOS4_GPIO_A0_START = 0, + EXYNOS4_GPIO_A1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0), + EXYNOS4_GPIO_B_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1), + EXYNOS4_GPIO_C0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B), + EXYNOS4_GPIO_C1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0), + EXYNOS4_GPIO_D0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1), + EXYNOS4_GPIO_D1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0), + EXYNOS4_GPIO_E0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1), + EXYNOS4_GPIO_E1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0), + EXYNOS4_GPIO_E2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1), + EXYNOS4_GPIO_E3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2), + EXYNOS4_GPIO_E4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3), + EXYNOS4_GPIO_F0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4), + EXYNOS4_GPIO_F1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0), + EXYNOS4_GPIO_F2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1), + EXYNOS4_GPIO_F3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2), + EXYNOS4_GPIO_J0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3), + EXYNOS4_GPIO_J1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0), + EXYNOS4_GPIO_K0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1), + EXYNOS4_GPIO_K1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0), + EXYNOS4_GPIO_K2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1), + EXYNOS4_GPIO_K3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2), + EXYNOS4_GPIO_L0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3), + EXYNOS4_GPIO_L1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0), + EXYNOS4_GPIO_L2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1), + EXYNOS4_GPIO_X0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2), + EXYNOS4_GPIO_X1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0), + EXYNOS4_GPIO_X2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1), + EXYNOS4_GPIO_X3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2), + EXYNOS4_GPIO_Z_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3), +}; + +/* EXYNOS4 GPIO number definitions */ +#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr)) +#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr)) +#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr)) +#define EXYNOS4_GPC0(_nr) (EXYNOS4_GPIO_C0_START + (_nr)) +#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr)) +#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr)) +#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr)) +#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr)) +#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr)) +#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr)) +#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr)) +#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr)) +#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr)) +#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr)) +#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr)) +#define EXYNOS4_GPF3(_nr) (EXYNOS4_GPIO_F3_START + (_nr)) +#define EXYNOS4_GPJ0(_nr) (EXYNOS4_GPIO_J0_START + (_nr)) +#define EXYNOS4_GPJ1(_nr) (EXYNOS4_GPIO_J1_START + (_nr)) +#define EXYNOS4_GPK0(_nr) (EXYNOS4_GPIO_K0_START + (_nr)) +#define EXYNOS4_GPK1(_nr) (EXYNOS4_GPIO_K1_START + (_nr)) +#define EXYNOS4_GPK2(_nr) (EXYNOS4_GPIO_K2_START + (_nr)) +#define EXYNOS4_GPK3(_nr) (EXYNOS4_GPIO_K3_START + (_nr)) +#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr)) +#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr)) +#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr)) +#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr)) +#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr)) +#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr)) +#define EXYNOS4_GPX3(_nr) (EXYNOS4_GPIO_X3_START + (_nr)) +#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr)) + +/* the end of the EXYNOS4 specific gpios */ +#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1) +#define S3C_GPIO_END EXYNOS4_GPIO_END + +/* define the number of gpios we need to the one after the GPZ() range */ +#define ARCH_NR_GPIOS (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + \ + CONFIG_SAMSUNG_GPIO_EXTRA + 1) + +#include <asm-generic/gpio.h> + +#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-exynos4/include/mach/hardware.h b/arch/arm/mach-exynos4/include/mach/hardware.h new file mode 100644 index 000000000000..5109eb232f23 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/hardware.h @@ -0,0 +1,18 @@ +/* linux/arch/arm/mach-exynos4/include/mach/hardware.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - Hardware support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H __FILE__ + +/* currently nothing here, placeholder */ + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-exynos4/include/mach/io.h b/arch/arm/mach-exynos4/include/mach/io.h new file mode 100644 index 000000000000..d5478d247535 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/io.h @@ -0,0 +1,26 @@ +/* linux/arch/arm/mach-exynos4/include/mach/io.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org> + * + * Based on arch/arm/mach-s5p6442/include/mach/io.h + * + * Default IO routines for EXYNOS4 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H __FILE__ + +/* No current ISA/PCI bus support. */ +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#define IO_SPACE_LIMIT (0xFFFFFFFF) + +#endif /* __ASM_ARM_ARCH_IO_H */ diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h new file mode 100644 index 000000000000..80a41e03cc17 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/map.h @@ -0,0 +1,144 @@ +/* linux/arch/arm/mach-exynos4/include/mach/map.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS4 - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MAP_H +#define __ASM_ARCH_MAP_H __FILE__ + +#include <plat/map-base.h> + +/* + * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400. + * So need to define it, and here is to avoid redefinition warning. + */ +#define S3C_UART_OFFSET (0x10000) + +#include <plat/map-s5p.h> + +#define EXYNOS4_PA_SYSRAM 0x02020000 + +#define EXYNOS4_PA_I2S0 0x03830000 +#define EXYNOS4_PA_I2S1 0xE3100000 +#define EXYNOS4_PA_I2S2 0xE2A00000 + +#define EXYNOS4_PA_PCM0 0x03840000 +#define EXYNOS4_PA_PCM1 0x13980000 +#define EXYNOS4_PA_PCM2 0x13990000 + +#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000)) + +#define EXYNOS4_PA_ONENAND 0x0C000000 +#define EXYNOS4_PA_ONENAND_DMA 0x0C600000 + +#define EXYNOS4_PA_CHIPID 0x10000000 + +#define EXYNOS4_PA_SYSCON 0x10010000 +#define EXYNOS4_PA_PMU 0x10020000 +#define EXYNOS4_PA_CMU 0x10030000 + +#define EXYNOS4_PA_WATCHDOG 0x10060000 +#define EXYNOS4_PA_RTC 0x10070000 + +#define EXYNOS4_PA_DMC0 0x10400000 + +#define EXYNOS4_PA_COMBINER 0x10448000 + +#define EXYNOS4_PA_COREPERI 0x10500000 +#define EXYNOS4_PA_GIC_CPU 0x10500100 +#define EXYNOS4_PA_TWD 0x10500600 +#define EXYNOS4_PA_GIC_DIST 0x10501000 +#define EXYNOS4_PA_L2CC 0x10502000 + +#define EXYNOS4_PA_MDMA 0x10810000 +#define EXYNOS4_PA_PDMA0 0x12680000 +#define EXYNOS4_PA_PDMA1 0x12690000 + +#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000 +#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000 +#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000 +#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000 +#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000 +#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000 +#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000 +#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000 +#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000 +#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000 +#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000 +#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000 +#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000 +#define EXYNOS4_PA_SYSMMU_TV 0x12E20000 +#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000 +#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000 + +#define EXYNOS4_PA_GPIO1 0x11400000 +#define EXYNOS4_PA_GPIO2 0x11000000 +#define EXYNOS4_PA_GPIO3 0x03860000 + +#define EXYNOS4_PA_MIPI_CSIS0 0x11880000 +#define EXYNOS4_PA_MIPI_CSIS1 0x11890000 + +#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) + +#define EXYNOS4_PA_SROMC 0x12570000 + +#define EXYNOS4_PA_UART 0x13800000 + +#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) + +#define EXYNOS4_PA_AC97 0x139A0000 + +#define EXYNOS4_PA_TIMER 0x139D0000 + +#define EXYNOS4_PA_SDRAM 0x40000000 + +#define EXYNOS4_PA_SPDIF 0xE1100000 + +/* Compatibiltiy Defines */ + +#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0) +#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1) +#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2) +#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3) +#define S3C_PA_IIC EXYNOS4_PA_IIC(0) +#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1) +#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2) +#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3) +#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4) +#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5) +#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6) +#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) +#define S3C_PA_RTC EXYNOS4_PA_RTC +#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG + +#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID +#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0 +#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1 +#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND +#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA +#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM +#define S5P_PA_SROMC EXYNOS4_PA_SROMC +#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON +#define S5P_PA_TIMER EXYNOS4_PA_TIMER + +/* UART */ + +#define S3C_PA_UART EXYNOS4_PA_UART + +#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) +#define S5P_PA_UART0 S5P_PA_UART(0) +#define S5P_PA_UART1 S5P_PA_UART(1) +#define S5P_PA_UART2 S5P_PA_UART(2) +#define S5P_PA_UART3 S5P_PA_UART(3) +#define S5P_PA_UART4 S5P_PA_UART(4) + +#define S5P_SZ_UART SZ_256 + +#endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-exynos4/include/mach/memory.h b/arch/arm/mach-exynos4/include/mach/memory.h new file mode 100644 index 000000000000..39b47d06f9bb --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/memory.h @@ -0,0 +1,22 @@ +/* linux/arch/arm/mach-exynos4/include/mach/memory.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - Memory definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H __FILE__ + +#define PHYS_OFFSET UL(0x40000000) + +/* Maximum of 256MiB in one bank */ +#define MAX_PHYSMEM_BITS 32 +#define SECTION_SIZE_BITS 28 + +#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-exynos4/include/mach/regs-gpio.h b/arch/arm/mach-exynos4/include/mach/regs-gpio.h new file mode 100644 index 000000000000..1401b21663a5 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/regs-gpio.h @@ -0,0 +1,42 @@ +/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - GPIO (including EINT) register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_GPIO_H +#define __ASM_ARCH_REGS_GPIO_H __FILE__ + +#include <mach/map.h> +#include <mach/irqs.h> + +#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00) +#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4)) + +#define EXYNOS4_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80) +#define S5P_EINT_FLTCON(x) (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4)) + +#define EXYNOS4_EINT40MASK (S5P_VA_GPIO2 + 0xF00) +#define S5P_EINT_MASK(x) (EXYNOS4_EINT40MASK + ((x) * 0x4)) + +#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40) +#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4)) + +#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3) + +#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7)) + +#define EINT_MODE S3C_GPIO_SFN(0xf) + +#define EINT_GPIO_0(x) EXYNOS4_GPX0(x) +#define EINT_GPIO_1(x) EXYNOS4_GPX1(x) +#define EINT_GPIO_2(x) EXYNOS4_GPX2(x) +#define EINT_GPIO_3(x) EXYNOS4_GPX3(x) + +#endif /* __ASM_ARCH_REGS_GPIO_H */ diff --git a/arch/arm/mach-exynos4/include/mach/regs-mem.h b/arch/arm/mach-exynos4/include/mach/regs-mem.h new file mode 100644 index 000000000000..0368b5a27252 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/regs-mem.h @@ -0,0 +1,23 @@ +/* linux/arch/arm/mach-exynos4/include/mach/regs-mem.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - SROMC and DMC register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_MEM_H +#define __ASM_ARCH_REGS_MEM_H __FILE__ + +#include <mach/map.h> + +#define S5P_DMC0_MEMCON_OFFSET 0x04 + +#define S5P_DMC0_MEMTYPE_SHIFT 8 +#define S5P_DMC0_MEMTYPE_MASK 0xF + +#endif /* __ASM_ARCH_REGS_MEM_H */ diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h new file mode 100644 index 000000000000..2ddd6175dfa0 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h @@ -0,0 +1,30 @@ +/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - Power management unit definition + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_PMU_H +#define __ASM_ARCH_REGS_PMU_H __FILE__ + +#include <mach/map.h> + +#define S5P_PMUREG(x) (S5P_VA_PMU + (x)) + +#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) +#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) +#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) +#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) +#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) +#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) +#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) + +#define S5P_INT_LOCAL_PWR_EN 0x7 + +#endif /* __ASM_ARCH_REGS_PMU_H */ diff --git a/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h b/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h new file mode 100644 index 000000000000..b6aef863b9d6 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h @@ -0,0 +1,24 @@ +/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - System MMU register + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_SYSMMU_H +#define __ASM_ARCH_REGS_SYSMMU_H __FILE__ + +#define S5P_MMU_CTRL 0x000 +#define S5P_MMU_CFG 0x004 +#define S5P_MMU_STATUS 0x008 +#define S5P_MMU_FLUSH 0x00C +#define S5P_PT_BASE_ADDR 0x014 +#define S5P_INT_STATUS 0x018 +#define S5P_PAGE_FAULT_ADDR 0x024 + +#endif /* __ASM_ARCH_REGS_SYSMMU_H */ diff --git a/arch/arm/mach-exynos4/include/mach/smp.h b/arch/arm/mach-exynos4/include/mach/smp.h new file mode 100644 index 000000000000..a463dcebcfd3 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/smp.h @@ -0,0 +1,19 @@ +/* linux/arch/arm/mach-exynos4/include/mach/smp.h + * + * Cloned from arch/arm/mach-realview/include/mach/smp.h +*/ + +#ifndef ASM_ARCH_SMP_H +#define ASM_ARCH_SMP_H __FILE__ + +#include <asm/hardware/gic.h> + +/* + * We use IRQ1 as the IPI + */ +static inline void smp_cross_call(const struct cpumask *mask, int ipi) +{ + gic_raise_softirq(mask, ipi); +} + +#endif diff --git a/arch/arm/mach-exynos4/include/mach/sysmmu.h b/arch/arm/mach-exynos4/include/mach/sysmmu.h new file mode 100644 index 000000000000..1428adad8379 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/sysmmu.h @@ -0,0 +1,122 @@ +/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung sysmmu driver for EXYNOS4 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARM_ARCH_SYSMMU_H +#define __ASM_ARM_ARCH_SYSMMU_H __FILE__ + +#define EXYNOS4_SYSMMU_TOTAL_IPNUM 16 +#define S5P_SYSMMU_TOTAL_IPNUM EXYNOS4_SYSMMU_TOTAL_IPNUM + +enum exynos4_sysmmu_ips { + SYSMMU_MDMA, + SYSMMU_SSS, + SYSMMU_FIMC0, + SYSMMU_FIMC1, + SYSMMU_FIMC2, + SYSMMU_FIMC3, + SYSMMU_JPEG, + SYSMMU_FIMD0, + SYSMMU_FIMD1, + SYSMMU_PCIe, + SYSMMU_G2D, + SYSMMU_ROTATOR, + SYSMMU_MDMA2, + SYSMMU_TV, + SYSMMU_MFC_L, + SYSMMU_MFC_R, +}; + +static char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = { + "SYSMMU_MDMA" , + "SYSMMU_SSS" , + "SYSMMU_FIMC0" , + "SYSMMU_FIMC1" , + "SYSMMU_FIMC2" , + "SYSMMU_FIMC3" , + "SYSMMU_JPEG" , + "SYSMMU_FIMD0" , + "SYSMMU_FIMD1" , + "SYSMMU_PCIe" , + "SYSMMU_G2D" , + "SYSMMU_ROTATOR", + "SYSMMU_MDMA2" , + "SYSMMU_TV" , + "SYSMMU_MFC_L" , + "SYSMMU_MFC_R" , +}; + +typedef enum exynos4_sysmmu_ips sysmmu_ips; + +struct sysmmu_tt_info { + unsigned long *pgd; + unsigned long pgd_paddr; + unsigned long *pte; +}; + +struct sysmmu_controller { + const char *name; + + /* channels registers */ + void __iomem *regs; + + /* channel irq */ + unsigned int irq; + + sysmmu_ips ips; + + /* Translation Table Info. */ + struct sysmmu_tt_info *tt_info; + + struct resource *mem; + struct device *dev; + + /* SysMMU controller enable - true : enable */ + bool enable; +}; + +/** + * s5p_sysmmu_enable() - enable system mmu of ip + * @ips: The ip connected system mmu. + * + * This function enable system mmu to transfer address + * from virtual address to physical address + */ +int s5p_sysmmu_enable(sysmmu_ips ips); + +/** + * s5p_sysmmu_disable() - disable sysmmu mmu of ip + * @ips: The ip connected system mmu. + * + * This function disable system mmu to transfer address + * from virtual address to physical address + */ +int s5p_sysmmu_disable(sysmmu_ips ips); + +/** + * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table + * @ips: The ip connected system mmu. + * @pgd: The page table base address. + * + * This function set page table base address + * When system mmu transfer address from virtaul address to physical address, + * system mmu refer address information from page table + */ +int s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd); + +/** + * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu + * @ips: The ip connected system mmu. + * + * This function flush all TLB entry in system mmu + */ +int s5p_sysmmu_tlb_invalidate(sysmmu_ips ips); +#endif /* __ASM_ARM_ARCH_SYSMMU_H */ diff --git a/arch/arm/mach-exynos4/include/mach/system.h b/arch/arm/mach-exynos4/include/mach/system.h new file mode 100644 index 000000000000..5e3220c18fc7 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/system.h @@ -0,0 +1,22 @@ +/* linux/arch/arm/mach-exynos4/include/mach/system.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - system support header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H __FILE__ + +#include <plat/system-reset.h> + +static void arch_idle(void) +{ + /* nothing here yet */ +} +#endif /* __ASM_ARCH_SYSTEM_H */ diff --git a/arch/arm/mach-exynos4/include/mach/timex.h b/arch/arm/mach-exynos4/include/mach/timex.h new file mode 100644 index 000000000000..6d138750a708 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/timex.h @@ -0,0 +1,29 @@ +/* linux/arch/arm/mach-exynos4/include/mach/timex.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Copyright (c) 2003-2010 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * Based on arch/arm/mach-s5p6442/include/mach/timex.h + * + * EXYNOS4 - time parameters + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H __FILE__ + +/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it + * a variable is useless. It seems as long as we make our timers an + * exact multiple of HZ, any value that makes a 1->1 correspondence + * for the time conversion functions to/from jiffies is acceptable. +*/ + +#define CLOCK_TICK_RATE 12000000 + +#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-exynos4/include/mach/uncompress.h b/arch/arm/mach-exynos4/include/mach/uncompress.h new file mode 100644 index 000000000000..21d97bcd9acb --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/uncompress.h @@ -0,0 +1,30 @@ +/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - uncompress code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H __FILE__ + +#include <mach/map.h> +#include <plat/uncompress.h> + +static void arch_detect_cpu(void) +{ + /* we do not need to do any cpu detection here at the moment. */ + + /* + * For preventing FIFO overrun or infinite loop of UART console, + * fifo_max should be the minimum fifo size of all of the UART channels + */ + fifo_mask = S5PV210_UFSTAT_TXMASK; + fifo_max = 15 << S5PV210_UFSTAT_TXSHIFT; +} +#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-exynos4/include/mach/vmalloc.h b/arch/arm/mach-exynos4/include/mach/vmalloc.h new file mode 100644 index 000000000000..284330e571d2 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/vmalloc.h @@ -0,0 +1,22 @@ +/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Copyright 2010 Ben Dooks <ben-linux@fluff.org> + * + * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * EXYNOS4 vmalloc definition +*/ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H __FILE__ + +#define VMALLOC_END 0xF6000000UL + +#endif /* __ASM_ARCH_VMALLOC_H */ |
