diff options
Diffstat (limited to 'arch/arm/mach-aaec2000/include/mach')
| -rw-r--r-- | arch/arm/mach-aaec2000/include/mach/aaec2000.h | 207 | ||||
| -rw-r--r-- | arch/arm/mach-aaec2000/include/mach/aaed2000.h | 40 | ||||
| -rw-r--r-- | arch/arm/mach-aaec2000/include/mach/debug-macro.S | 37 | ||||
| -rw-r--r-- | arch/arm/mach-aaec2000/include/mach/dma.h | 9 | ||||
| -rw-r--r-- | arch/arm/mach-aaec2000/include/mach/entry-macro.S | 40 | ||||
| -rw-r--r-- | arch/arm/mach-aaec2000/include/mach/hardware.h | 50 | ||||
| -rw-r--r-- | arch/arm/mach-aaec2000/include/mach/io.h | 20 | ||||
| -rw-r--r-- | arch/arm/mach-aaec2000/include/mach/irqs.h | 46 | ||||
| -rw-r--r-- | arch/arm/mach-aaec2000/include/mach/memory.h | 30 | ||||
| -rw-r--r-- | arch/arm/mach-aaec2000/include/mach/system.h | 24 | ||||
| -rw-r--r-- | arch/arm/mach-aaec2000/include/mach/timex.h | 18 | ||||
| -rw-r--r-- | arch/arm/mach-aaec2000/include/mach/uncompress.h | 46 | ||||
| -rw-r--r-- | arch/arm/mach-aaec2000/include/mach/vmalloc.h | 16 |
13 files changed, 583 insertions, 0 deletions
diff --git a/arch/arm/mach-aaec2000/include/mach/aaec2000.h b/arch/arm/mach-aaec2000/include/mach/aaec2000.h new file mode 100644 index 000000000000..bc729c42f843 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/aaec2000.h @@ -0,0 +1,207 @@ +/* + * arch/arm/mach-aaec2000/include/mach/aaec2000.h + * + * AAEC-2000 registers definition + * + * Copyright (c) 2005 Nicolas Bellido Y Ortega + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_AAEC2000_H +#define __ASM_ARCH_AAEC2000_H + +#ifndef __ASM_ARCH_HARDWARE_H +#error You must include hardware.h not this file +#endif /* __ASM_ARCH_HARDWARE_H */ + +/* Chip selects */ +#define AAEC_CS0 0x00000000 +#define AAEC_CS1 0x10000000 +#define AAEC_CS2 0x20000000 +#define AAEC_CS3 0x30000000 + +/* Flash */ +#define AAEC_FLASH_BASE AAEC_CS0 +#define AAEC_FLASH_SIZE SZ_64M + +/* Interrupt controller */ +#define IRQ_BASE __REG(0x80000500) +#define IRQ_INTSR __REG(0x80000500) /* Int Status Register */ +#define IRQ_INTRSR __REG(0x80000504) /* Int Raw (unmasked) Status */ +#define IRQ_INTENS __REG(0x80000508) /* Int Enable Set */ +#define IRQ_INTENC __REG(0x8000050c) /* Int Enable Clear */ + +/* UART 1 */ +#define UART1_BASE __REG(0x80000600) +#define UART1_DR __REG(0x80000600) /* Data/FIFO Register */ +#define UART1_LCR __REG(0x80000604) /* Link Control Register */ +#define UART1_BRCR __REG(0x80000608) /* Baud Rate Control Register */ +#define UART1_CR __REG(0x8000060c) /* Control Register */ +#define UART1_SR __REG(0x80000610) /* Status Register */ +#define UART1_INT __REG(0x80000614) /* Interrupt Status Register */ +#define UART1_INTM __REG(0x80000618) /* Interrupt Mask Register */ +#define UART1_INTRES __REG(0x8000061c) /* Int Result (masked status) Register */ + +/* UART 2 */ +#define UART2_BASE __REG(0x80000700) +#define UART2_DR __REG(0x80000700) /* Data/FIFO Register */ +#define UART2_LCR __REG(0x80000704) /* Link Control Register */ +#define UART2_BRCR __REG(0x80000708) /* Baud Rate Control Register */ +#define UART2_CR __REG(0x8000070c) /* Control Register */ +#define UART2_SR __REG(0x80000710) /* Status Register */ +#define UART2_INT __REG(0x80000714) /* Interrupt Status Register */ +#define UART2_INTM __REG(0x80000718) /* Interrupt Mask Register */ +#define UART2_INTRES __REG(0x8000071c) /* Int Result (masked status) Register */ + +/* UART 3 */ +#define UART3_BASE __REG(0x80000800) +#define UART3_DR __REG(0x80000800) /* Data/FIFO Register */ +#define UART3_LCR __REG(0x80000804) /* Link Control Register */ +#define UART3_BRCR __REG(0x80000808) /* Baud Rate Control Register */ +#define UART3_CR __REG(0x8000080c) /* Control Register */ +#define UART3_SR __REG(0x80000810) /* Status Register */ +#define UART3_INT __REG(0x80000814) /* Interrupt Status Register */ +#define UART3_INTM __REG(0x80000818) /* Interrupt Mask Register */ +#define UART3_INTRES __REG(0x8000081c) /* Int Result (masked status) Register */ + +/* These are used in some places */ +#define _UART1_BASE __PREG(UART1_BASE) +#define _UART2_BASE __PREG(UART2_BASE) +#define _UART3_BASE __PREG(UART3_BASE) + +/* UART Registers Offsets */ +#define UART_DR 0x00 +#define UART_LCR 0x04 +#define UART_BRCR 0x08 +#define UART_CR 0x0c +#define UART_SR 0x10 +#define UART_INT 0x14 +#define UART_INTM 0x18 +#define UART_INTRES 0x1c + +/* UART_LCR Bitmask */ +#define UART_LCR_BRK (1 << 0) /* Send Break */ +#define UART_LCR_PEN (1 << 1) /* Parity Enable */ +#define UART_LCR_EP (1 << 2) /* Even/Odd Parity */ +#define UART_LCR_S2 (1 << 3) /* One/Two Stop bits */ +#define UART_LCR_FIFO (1 << 4) /* FIFO Enable */ +#define UART_LCR_WL5 (0 << 5) /* Word Length - 5 bits */ +#define UART_LCR_WL6 (1 << 5) /* Word Length - 6 bits */ +#define UART_LCR_WL7 (1 << 6) /* Word Length - 7 bits */ +#define UART_LCR_WL8 (1 << 7) /* Word Length - 8 bits */ + +/* UART_CR Bitmask */ +#define UART_CR_EN (1 << 0) /* UART Enable */ +#define UART_CR_SIR (1 << 1) /* IrDA SIR Enable */ +#define UART_CR_SIRLP (1 << 2) /* Low Power IrDA Enable */ +#define UART_CR_RXP (1 << 3) /* Receive Pin Polarity */ +#define UART_CR_TXP (1 << 4) /* Transmit Pin Polarity */ +#define UART_CR_MXP (1 << 5) /* Modem Pin Polarity */ +#define UART_CR_LOOP (1 << 6) /* Loopback Mode */ + +/* UART_SR Bitmask */ +#define UART_SR_CTS (1 << 0) /* Clear To Send Status */ +#define UART_SR_DSR (1 << 1) /* Data Set Ready Status */ +#define UART_SR_DCD (1 << 2) /* Data Carrier Detect Status */ +#define UART_SR_TxBSY (1 << 3) /* Transmitter Busy Status */ +#define UART_SR_RxFE (1 << 4) /* Receive FIFO Empty Status */ +#define UART_SR_TxFF (1 << 5) /* Transmit FIFO Full Status */ +#define UART_SR_RxFF (1 << 6) /* Receive FIFO Full Status */ +#define UART_SR_TxFE (1 << 7) /* Transmit FIFO Empty Status */ + +/* UART_INT Bitmask */ +#define UART_INT_RIS (1 << 0) /* Rx Interrupt */ +#define UART_INT_TIS (1 << 1) /* Tx Interrupt */ +#define UART_INT_MIS (1 << 2) /* Modem Interrupt */ +#define UART_INT_RTIS (1 << 3) /* Receive Timeout Interrupt */ + +/* Timer 1 */ +#define TIMER1_BASE __REG(0x80000c00) +#define TIMER1_LOAD __REG(0x80000c00) /* Timer 1 Load Register */ +#define TIMER1_VAL __REG(0x80000c04) /* Timer 1 Value Register */ +#define TIMER1_CTRL __REG(0x80000c08) /* Timer 1 Control Register */ +#define TIMER1_CLEAR __REG(0x80000c0c) /* Timer 1 Clear Register */ + +/* Timer 2 */ +#define TIMER2_BASE __REG(0x80000d00) +#define TIMER2_LOAD __REG(0x80000d00) /* Timer 2 Load Register */ +#define TIMER2_VAL __REG(0x80000d04) /* Timer 2 Value Register */ +#define TIMER2_CTRL __REG(0x80000d08) /* Timer 2 Control Register */ +#define TIMER2_CLEAR __REG(0x80000d0c) /* Timer 2 Clear Register */ + +/* Timer 3 */ +#define TIMER3_BASE __REG(0x80000e00) +#define TIMER3_LOAD __REG(0x80000e00) /* Timer 3 Load Register */ +#define TIMER3_VAL __REG(0x80000e04) /* Timer 3 Value Register */ +#define TIMER3_CTRL __REG(0x80000e08) /* Timer 3 Control Register */ +#define TIMER3_CLEAR __REG(0x80000e0c) /* Timer 3 Clear Register */ + +/* Timer Control register bits */ +#define TIMER_CTRL_ENABLE (1 << 7) /* Enable (Start Timer) */ +#define TIMER_CTRL_PERIODIC (1 << 6) /* Periodic Running Mode */ +#define TIMER_CTRL_FREE_RUNNING (0 << 6) /* Normal Running Mode */ +#define TIMER_CTRL_CLKSEL_508K (1 << 3) /* 508KHz Clock select (Timer 1, 2) */ +#define TIMER_CTRL_CLKSEL_2K (0 << 3) /* 2KHz Clock Select (Timer 1, 2) */ + +/* Power and State Control */ +#define POWER_BASE __REG(0x80000400) +#define POWER_PWRSR __REG(0x80000400) /* Power Status Register */ +#define POWER_PWRCNT __REG(0x80000404) /* Power/Clock control */ +#define POWER_HALT __REG(0x80000408) /* Power Idle Mode */ +#define POWER_STDBY __REG(0x8000040c) /* Power Standby Mode */ +#define POWER_BLEOI __REG(0x80000410) /* Battery Low End of Interrupt */ +#define POWER_MCEOI __REG(0x80000414) /* Media Changed EoI */ +#define POWER_TEOI __REG(0x80000418) /* Tick EoI */ +#define POWER_STFCLR __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */ +#define POWER_CLKSET __REG(0x80000420) /* Clock Speed Control */ + +/* GPIO Registers */ +#define AAEC_GPIO_PHYS 0x80000e00 + +#define AAEC_GPIO_PADR __REG(AAEC_GPIO_PHYS + 0x00) +#define AAEC_GPIO_PBDR __REG(AAEC_GPIO_PHYS + 0x04) +#define AAEC_GPIO_PCDR __REG(AAEC_GPIO_PHYS + 0x08) +#define AAEC_GPIO_PDDR __REG(AAEC_GPIO_PHYS + 0x0c) +#define AAEC_GPIO_PADDR __REG(AAEC_GPIO_PHYS + 0x10) +#define AAEC_GPIO_PBDDR __REG(AAEC_GPIO_PHYS + 0x14) +#define AAEC_GPIO_PCDDR __REG(AAEC_GPIO_PHYS + 0x18) +#define AAEC_GPIO_PDDDR __REG(AAEC_GPIO_PHYS + 0x1c) +#define AAEC_GPIO_PEDR __REG(AAEC_GPIO_PHYS + 0x20) +#define AAEC_GPIO_PEDDR __REG(AAEC_GPIO_PHYS + 0x24) +#define AAEC_GPIO_KSCAN __REG(AAEC_GPIO_PHYS + 0x28) +#define AAEC_GPIO_PINMUX __REG(AAEC_GPIO_PHYS + 0x2c) +#define AAEC_GPIO_PFDR __REG(AAEC_GPIO_PHYS + 0x30) +#define AAEC_GPIO_PFDDR __REG(AAEC_GPIO_PHYS + 0x34) +#define AAEC_GPIO_PGDR __REG(AAEC_GPIO_PHYS + 0x38) +#define AAEC_GPIO_PGDDR __REG(AAEC_GPIO_PHYS + 0x3c) +#define AAEC_GPIO_PHDR __REG(AAEC_GPIO_PHYS + 0x40) +#define AAEC_GPIO_PHDDR __REG(AAEC_GPIO_PHYS + 0x44) +#define AAEC_GPIO_RAZ __REG(AAEC_GPIO_PHYS + 0x48) +#define AAEC_GPIO_INTTYPE1 __REG(AAEC_GPIO_PHYS + 0x4c) +#define AAEC_GPIO_INTTYPE2 __REG(AAEC_GPIO_PHYS + 0x50) +#define AAEC_GPIO_FEOI __REG(AAEC_GPIO_PHYS + 0x54) +#define AAEC_GPIO_INTEN __REG(AAEC_GPIO_PHYS + 0x58) +#define AAEC_GPIO_INTSTATUS __REG(AAEC_GPIO_PHYS + 0x5c) +#define AAEC_GPIO_RAWINTSTATUS __REG(AAEC_GPIO_PHYS + 0x60) +#define AAEC_GPIO_DB __REG(AAEC_GPIO_PHYS + 0x64) +#define AAEC_GPIO_PAPINDR __REG(AAEC_GPIO_PHYS + 0x68) +#define AAEC_GPIO_PBPINDR __REG(AAEC_GPIO_PHYS + 0x6c) +#define AAEC_GPIO_PCPINDR __REG(AAEC_GPIO_PHYS + 0x70) +#define AAEC_GPIO_PDPINDR __REG(AAEC_GPIO_PHYS + 0x74) +#define AAEC_GPIO_PEPINDR __REG(AAEC_GPIO_PHYS + 0x78) +#define AAEC_GPIO_PFPINDR __REG(AAEC_GPIO_PHYS + 0x7c) +#define AAEC_GPIO_PGPINDR __REG(AAEC_GPIO_PHYS + 0x80) +#define AAEC_GPIO_PHPINDR __REG(AAEC_GPIO_PHYS + 0x84) + +#define AAEC_GPIO_PINMUX_PE0CON (1 << 0) +#define AAEC_GPIO_PINMUX_PD0CON (1 << 1) +#define AAEC_GPIO_PINMUX_CODECON (1 << 2) +#define AAEC_GPIO_PINMUX_UART3CON (1 << 3) + +/* LCD Controller */ +#define AAEC_CLCD_PHYS 0x80003000 + +#endif /* __ARM_ARCH_AAEC2000_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/aaed2000.h b/arch/arm/mach-aaec2000/include/mach/aaed2000.h new file mode 100644 index 000000000000..f821295ca71b --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/aaed2000.h @@ -0,0 +1,40 @@ +/* + * arch/arm/mach-aaec2000/include/mach/aaed2000.h + * + * AAED-2000 specific bits definition + * + * Copyright (c) 2005 Nicolas Bellido Y Ortega + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_AAED2000_H +#define __ASM_ARCH_AAED2000_H + +/* External GPIOs. */ + +#define EXT_GPIO_PBASE AAEC_CS3 +#define EXT_GPIO_VBASE 0xf8100000 +#define EXT_GPIO_LENGTH 0x00001000 + +#define __ext_gpio_p2v(x) ((x) - EXT_GPIO_PBASE + EXT_GPIO_VBASE) +#define __ext_gpio_v2p(x) ((x) + EXT_GPIO_PBASE - EXT_GPIO_VBASE) + +#define __EXT_GPIO_REG(x) (*((volatile u32 *)__ext_gpio_p2v(x))) +#define __EXT_GPIO_PREG(x) (__ext_gpio_v2p((u32)&(x))) + +#define AAED_EXT_GPIO __EXT_GPIO_REG(EXT_GPIO_PBASE) + +#define AAED_EGPIO_KBD_SCAN 0x00003fff /* Keyboard scan data */ +#define AAED_EGPIO_PWR_INT 0x00008fff /* Smart battery charger interrupt */ +#define AAED_EGPIO_SWITCHED 0x000f0000 /* DIP Switches */ +#define AAED_EGPIO_USB_VBUS 0x00400000 /* USB Vbus sense */ +#define AAED_EGPIO_LCD_PWR_EN 0x02000000 /* LCD and backlight PWR enable */ +#define AAED_EGPIO_nLED0 0x20000000 /* LED 0 */ +#define AAED_EGPIO_nLED1 0x20000000 /* LED 1 */ +#define AAED_EGPIO_nLED2 0x20000000 /* LED 2 */ + + +#endif /* __ARM_ARCH_AAED2000_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/debug-macro.S b/arch/arm/mach-aaec2000/include/mach/debug-macro.S new file mode 100644 index 000000000000..0b6351d7c389 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/debug-macro.S @@ -0,0 +1,37 @@ +/* arch/arm/mach-aaec2000/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (c) 2005 Nicolas Bellido Y Ortega + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "hardware.h" + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x80000000 @ physical + movne \rx, #io_p2v(0x80000000) @ virtual + orr \rx, \rx, #0x00000800 + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #0] + .endm + + .macro busyuart,rd,rx +1002: ldr \rd, [\rx, #0x10] + tst \rd, #(1 << 7) + beq 1002b + .endm + + .macro waituart,rd,rx +#if 0 +1001: ldr \rd, [\rx, #0x10] + tst \rd, #(1 << 5) + beq 1001b +#endif + .endm diff --git a/arch/arm/mach-aaec2000/include/mach/dma.h b/arch/arm/mach-aaec2000/include/mach/dma.h new file mode 100644 index 000000000000..2da846c72fe7 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/dma.h @@ -0,0 +1,9 @@ +/* + * arch/arm/mach-aaec2000/include/mach/dma.h + * + * Copyright (c) 2005 Nicolas Bellido Y Ortega + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ diff --git a/arch/arm/mach-aaec2000/include/mach/entry-macro.S b/arch/arm/mach-aaec2000/include/mach/entry-macro.S new file mode 100644 index 000000000000..c8fb34469007 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/entry-macro.S @@ -0,0 +1,40 @@ +/* + * arch/arm/mach-aaec2000/include/mach/entry-macro.S + * + * Low-level IRQ helper for aaec-2000 based platforms + * + * Copyright (c) 2005 Nicolas Bellido Y Ortega + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include <mach/irqs.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mov r4, #0xf8000000 + add r4, r4, #0x00000500 + mov \base, r4 + ldr \irqstat, [\base, #0] + cmp \irqstat, #0 + bne 1001f + ldr \irqnr, =NR_IRQS+1 + b 1003f +1001: mov \irqnr, #0 +1002: ands \tmp, \irqstat, #1 + mov \irqstat, \irqstat, LSR #1 + add \irqnr, \irqnr, #1 + beq 1002b + sub \irqnr, \irqnr, #1 +1003: + .endm diff --git a/arch/arm/mach-aaec2000/include/mach/hardware.h b/arch/arm/mach-aaec2000/include/mach/hardware.h new file mode 100644 index 000000000000..965a6f6672d6 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/hardware.h @@ -0,0 +1,50 @@ +/* + * arch/arm/mach-aaec2000/include/mach/hardware.h + * + * Copyright (c) 2005 Nicolas Bellido Y Ortega + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/sizes.h> +#include <mach/aaec2000.h> + +/* The kernel is loaded at physical address 0xf8000000. + * We map the IO space a bit after + */ +#define PIO_APB_BASE 0x80000000 +#define VIO_APB_BASE 0xf8000000 +#define IO_APB_LENGTH 0x2000 +#define PIO_AHB_BASE 0x80002000 +#define VIO_AHB_BASE 0xf8002000 +#define IO_AHB_LENGTH 0x2000 + +#define VIO_BASE VIO_APB_BASE +#define PIO_BASE PIO_APB_BASE + +#define io_p2v(x) ( (x) - PIO_BASE + VIO_BASE ) +#define io_v2p(x) ( (x) + PIO_BASE - VIO_BASE ) + +#ifndef __ASSEMBLY__ + +#include <asm/types.h> + +/* FIXME: Is it needed to optimize this a la pxa ?? */ +#define __REG(x) (*((volatile u32 *)io_p2v(x))) +#define __PREG(x) (io_v2p((u32)&(x))) + +#else /* __ASSEMBLY__ */ + +#define __REG(x) io_p2v(x) +#define __PREG(x) io_v2p(x) + +#endif + +#include "aaec2000.h" + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/io.h b/arch/arm/mach-aaec2000/include/mach/io.h new file mode 100644 index 000000000000..c87c24de1110 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/io.h @@ -0,0 +1,20 @@ +/* + * arch/arm/mach-aaec2000/include/mach/io.h + * + * Copied from asm/arch/sa1100/io.h + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#include <mach/hardware.h> + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * We don't actually have real ISA nor PCI buses, but there is so many + * drivers out there that might just work if we fake them... + */ +#define __io(a) ((void __iomem *)(a)) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-aaec2000/include/mach/irqs.h b/arch/arm/mach-aaec2000/include/mach/irqs.h new file mode 100644 index 000000000000..bf45c6d2f294 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/irqs.h @@ -0,0 +1,46 @@ +/* + * arch/arm/mach-aaec2000/include/mach/irqs.h + * + * Copyright (c) 2005 Nicolas Bellido Y Ortega + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + + +#define INT_GPIOF0_FIQ 0 /* External GPIO Port F O Fast Interrupt Input */ +#define INT_BL_FIQ 1 /* Battery Low Fast Interrupt */ +#define INT_WE_FIQ 2 /* Watchdog Expired Fast Interrupt */ +#define INT_MV_FIQ 3 /* Media Changed Interrupt */ +#define INT_SC 4 /* Sound Codec Interrupt */ +#define INT_GPIO1 5 /* GPIO Port F Configurable Int 1 */ +#define INT_GPIO2 6 /* GPIO Port F Configurable Int 2 */ +#define INT_GPIO3 7 /* GPIO Port F Configurable Int 3 */ +#define INT_TMR1_OFL 8 /* Timer 1 Overflow Interrupt */ +#define INT_TMR2_OFL 9 /* Timer 2 Overflow Interrupt */ +#define INT_RTC_CM 10 /* RTC Compare Match Interrupt */ +#define INT_TICK 11 /* 64Hz Tick Interrupt */ +#define INT_UART1 12 /* UART1 Interrupt */ +#define INT_UART2 13 /* UART2 & Modem State Changed Interrupt */ +#define INT_LCD 14 /* LCD Interrupt */ +#define INT_SSI 15 /* SSI End of Transfer Interrupt */ +#define INT_UART3 16 /* UART3 Interrupt */ +#define INT_SCI 17 /* SCI Interrupt */ +#define INT_AAC 18 /* Advanced Audio Codec Interrupt */ +#define INT_MMC 19 /* MMC Interrupt */ +#define INT_USB 20 /* USB Interrupt */ +#define INT_DMA 21 /* DMA Interrupt */ +#define INT_TMR3_UOFL 22 /* Timer 3 Underflow Interrupt */ +#define INT_GPIO4 23 /* GPIO Port F Configurable Int 4 */ +#define INT_GPIO5 24 /* GPIO Port F Configurable Int 4 */ +#define INT_GPIO6 25 /* GPIO Port F Configurable Int 4 */ +#define INT_GPIO7 26 /* GPIO Port F Configurable Int 4 */ +#define INT_BMI 27 /* BMI Interrupt */ + +#define NR_IRQS (INT_BMI + 1) + +#endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/memory.h b/arch/arm/mach-aaec2000/include/mach/memory.h new file mode 100644 index 000000000000..56ae900a482e --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/memory.h @@ -0,0 +1,30 @@ +/* + * arch/arm/mach-aaec2000/include/mach/memory.h + * + * Copyright (c) 2005 Nicolas Bellido Y Ortega + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + + +#define PHYS_OFFSET UL(0xf0000000) + +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +/* + * The nodes are the followings: + * + * node 0: 0xf000.0000 - 0xf3ff.ffff + * node 1: 0xf400.0000 - 0xf7ff.ffff + * node 2: 0xf800.0000 - 0xfbff.ffff + * node 3: 0xfc00.0000 - 0xffff.ffff + */ +#define NODE_MEM_SIZE_BITS 26 + +#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/system.h b/arch/arm/mach-aaec2000/include/mach/system.h new file mode 100644 index 000000000000..8f4115d734ce --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/system.h @@ -0,0 +1,24 @@ +/* + * arch/arm/mach-aaed2000/include/mach/system.h + * + * Copyright (c) 2005 Nicolas Bellido Y Ortega + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + cpu_reset(0); +} + +#endif /* __ASM_ARCH_SYSTEM_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/timex.h b/arch/arm/mach-aaec2000/include/mach/timex.h new file mode 100644 index 000000000000..6c8edf4a8828 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/timex.h @@ -0,0 +1,18 @@ +/* + * arch/arm/mach-aaec2000/include/mach/timex.h + * + * AAEC-2000 Architecture timex specification + * + * Copyright (c) 2005 Nicolas Bellido Y Ortega + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +#define CLOCK_TICK_RATE 508000 + +#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/uncompress.h b/arch/arm/mach-aaec2000/include/mach/uncompress.h new file mode 100644 index 000000000000..381ecad1a1bb --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/uncompress.h @@ -0,0 +1,46 @@ +/* + * arch/arm/mach-aaec2000/include/mach/uncompress.h + * + * Copyright (c) 2005 Nicolas Bellido Y Ortega + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include "hardware.h" + +#define UART(x) (*(volatile unsigned long *)(serial_port + (x))) + +static void putc(int c) +{ + unsigned long serial_port; + do { + serial_port = _UART3_BASE; + if (UART(UART_CR) & UART_CR_EN) break; + serial_port = _UART1_BASE; + if (UART(UART_CR) & UART_CR_EN) break; + serial_port = _UART2_BASE; + if (UART(UART_CR) & UART_CR_EN) break; + return; + } while (0); + + /* wait for space in the UART's transmitter */ + while ((UART(UART_SR) & UART_SR_TxFF)) + barrier(); + + /* send the character out. */ + UART(UART_DR) = c; +} + +static inline void flush(void) +{ +} + +#define arch_decomp_setup() +#define arch_decomp_wdog() + +#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/vmalloc.h b/arch/arm/mach-aaec2000/include/mach/vmalloc.h new file mode 100644 index 000000000000..551f68f666bf --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/vmalloc.h @@ -0,0 +1,16 @@ +/* + * arch/arm/mach-aaec2000/include/mach/vmalloc.h + * + * Copyright (c) 2005 Nicolas Bellido Y Ortega + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H + +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) + +#endif /* __ASM_ARCH_VMALLOC_H */ |
