diff options
Diffstat (limited to 'arch/arm/boot')
321 files changed, 18596 insertions, 3390 deletions
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 3580d57ea218..48d0a44270bd 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -27,7 +27,7 @@ OBJS += misc.o decompress.o ifeq ($(CONFIG_DEBUG_UNCOMPRESS),y) OBJS += debug.o endif -FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c +FONTC = $(srctree)/lib/fonts/font_acorn_8x8.c # string library code (-Os is enforced to keep it much smaller) OBJS += string.o @@ -116,7 +116,8 @@ targets := vmlinux vmlinux.lds \ # Make sure files are removed during clean extra-y += piggy.gzip piggy.lzo piggy.lzma piggy.xzkern \ - lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs) + lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs) \ + hyp-stub.S ifeq ($(CONFIG_FUNCTION_TRACER),y) ORIG_CFLAGS := $(KBUILD_CFLAGS) @@ -124,7 +125,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) endif ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj) -asflags-y := -Wa,-march=all -DZIMAGE +asflags-y := -DZIMAGE # Supply kernel BSS size to the decompressor via a linker symbol. KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \ diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c index aabc02a68482..d1153c8a765a 100644 --- a/arch/arm/boot/compressed/atags_to_fdt.c +++ b/arch/arm/boot/compressed/atags_to_fdt.c @@ -53,6 +53,17 @@ static const void *getprop(const void *fdt, const char *node_path, return fdt_getprop(fdt, offset, property, len); } +static uint32_t get_cell_size(const void *fdt) +{ + int len; + uint32_t cell_size = 1; + const uint32_t *size_len = getprop(fdt, "/", "#size-cells", &len); + + if (size_len) + cell_size = fdt32_to_cpu(*size_len); + return cell_size; +} + static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) { char cmdline[COMMAND_LINE_SIZE]; @@ -95,9 +106,11 @@ static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) int atags_to_fdt(void *atag_list, void *fdt, int total_space) { struct tag *atag = atag_list; - uint32_t mem_reg_property[2 * NR_BANKS]; + /* In the case of 64 bits memory size, need to reserve 2 cells for + * address and size for each bank */ + uint32_t mem_reg_property[2 * 2 * NR_BANKS]; int memcount = 0; - int ret; + int ret, memsize; /* make sure we've got an aligned pointer */ if ((u32)atag_list & 0x3) @@ -137,8 +150,25 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space) continue; if (!atag->u.mem.size) continue; - mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.start); - mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.size); + memsize = get_cell_size(fdt); + + if (memsize == 2) { + /* if memsize is 2, that means that + * each data needs 2 cells of 32 bits, + * so the data are 64 bits */ + uint64_t *mem_reg_prop64 = + (uint64_t *)mem_reg_property; + mem_reg_prop64[memcount++] = + cpu_to_fdt64(atag->u.mem.start); + mem_reg_prop64[memcount++] = + cpu_to_fdt64(atag->u.mem.size); + } else { + mem_reg_property[memcount++] = + cpu_to_fdt32(atag->u.mem.start); + mem_reg_property[memcount++] = + cpu_to_fdt32(atag->u.mem.size); + } + } else if (atag->hdr.tag == ATAG_INITRD2) { uint32_t initrd_start, initrd_size; initrd_start = atag->u.initrd.start; @@ -150,8 +180,10 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space) } } - if (memcount) - setprop(fdt, "/memory", "reg", mem_reg_property, 4*memcount); + if (memcount) { + setprop(fdt, "/memory", "reg", mem_reg_property, + 4 * memcount * memsize); + } return fdt_pack(fdt); } diff --git a/arch/arm/boot/compressed/debug.S b/arch/arm/boot/compressed/debug.S index 6e8382d5b7a4..5392ee63338f 100644 --- a/arch/arm/boot/compressed/debug.S +++ b/arch/arm/boot/compressed/debug.S @@ -1,6 +1,8 @@ #include <linux/linkage.h> #include <asm/assembler.h> +#ifndef CONFIG_DEBUG_SEMIHOSTING + #include CONFIG_DEBUG_LL_INCLUDE ENTRY(putc) @@ -10,3 +12,29 @@ ENTRY(putc) busyuart r3, r1 mov pc, lr ENDPROC(putc) + +#else + +ENTRY(putc) + adr r1, 1f + ldmia r1, {r2, r3} + add r2, r2, r1 + ldr r1, [r2, r3] + strb r0, [r1] + mov r0, #0x03 @ SYS_WRITEC + ARM( svc #0x123456 ) + THUMB( svc #0xab ) + mov pc, lr + .align 2 +1: .word _GLOBAL_OFFSET_TABLE_ - . + .word semi_writec_buf(GOT) +ENDPROC(putc) + + .bss + .global semi_writec_buf + .type semi_writec_buf, %object +semi_writec_buf: + .space 4 + .size semi_writec_buf, 4 + +#endif diff --git a/arch/arm/boot/compressed/head-sa1100.S b/arch/arm/boot/compressed/head-sa1100.S index 6179d94dd5c6..3115e313d9f6 100644 --- a/arch/arm/boot/compressed/head-sa1100.S +++ b/arch/arm/boot/compressed/head-sa1100.S @@ -11,6 +11,7 @@ #include <asm/mach-types.h> .section ".start", "ax" + .arch armv4 __SA1100_start: diff --git a/arch/arm/boot/compressed/head-shark.S b/arch/arm/boot/compressed/head-shark.S index 089c560e07f1..92b56897ed64 100644 --- a/arch/arm/boot/compressed/head-shark.S +++ b/arch/arm/boot/compressed/head-shark.S @@ -18,6 +18,7 @@ .section ".start", "ax" + .arch armv4 b __beginning __ofw_data: .long 0 @ the number of memory blocks diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S index fe3719b516fd..e2d636336b7c 100644 --- a/arch/arm/boot/compressed/head-shmobile.S +++ b/arch/arm/boot/compressed/head-shmobile.S @@ -46,7 +46,7 @@ __image_start: __image_end: .long _got_end __load_base: - .long CONFIG_MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM + .long MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM __loaded: .long __continue .align @@ -55,26 +55,9 @@ __tmp_stack: __continue: #endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */ - b 1f -__atags:@ tag #1 - .long 12 @ tag->hdr.size = tag_size(tag_core); - .long 0x54410001 @ tag->hdr.tag = ATAG_CORE; - .long 0 @ tag->u.core.flags = 0; - .long 0 @ tag->u.core.pagesize = 0; - .long 0 @ tag->u.core.rootdev = 0; - @ tag #2 - .long 8 @ tag->hdr.size = tag_size(tag_mem32); - .long 0x54410002 @ tag->hdr.tag = ATAG_MEM; - .long CONFIG_MEMORY_SIZE @ tag->u.mem.size = CONFIG_MEMORY_SIZE; - .long CONFIG_MEMORY_START @ @ tag->u.mem.start = CONFIG_MEMORY_START; - @ tag #3 - .long 0 @ tag->hdr.size = 0 - .long 0 @ tag->hdr.tag = ATAG_NONE; -1: - /* Set board ID necessary for boot */ ldr r7, 1f @ Set machine type register - adr r8, __atags @ Set atag register + mov r8, #0 @ pass null pointer as atag b 2f 1 : .long MACH_TYPE diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index fe4d9c3ad761..75189f13cf54 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -11,6 +11,7 @@ #include <linux/linkage.h> #include <asm/assembler.h> + .arch armv7-a /* * Debugging stuff * @@ -141,7 +142,6 @@ start: mov r7, r1 @ save architecture ID mov r8, r2 @ save atags pointer -#ifndef __ARM_ARCH_2__ /* * Booting from Angel - need to enter SVC mode and disable * FIQs/IRQs (numeric definitions from angel arm.h source). @@ -157,10 +157,6 @@ not_angel: safe_svcmode_maskall r0 msr spsr_cxsf, r9 @ Save the CPU boot mode in @ SPSR -#else - teqp pc, #0x0c000003 @ turn off interrupts -#endif - /* * Note that some cache flushing and other stuff may * be needed here - is there an Angel SWI call for this? @@ -182,7 +178,19 @@ not_angel: ldr r4, =zreladdr #endif - bl cache_on + /* + * Set up a page table only if it won't overwrite ourself. + * That means r4 < pc && r4 - 16k page directory > &_end. + * Given that r4 > &_end is most unfrequent, we add a rough + * additional 1MB of room for a possible appended DTB. + */ + mov r0, pc + cmp r0, r4 + ldrcc r0, LC0+32 + addcc r0, r0, pc + cmpcc r4, r0 + orrcc r4, r4, #1 @ remember we skipped cache_on + blcs cache_on restart: adr r0, LC0 ldmia r0, {r1, r2, r3, r6, r10, r11, r12} @@ -228,7 +236,7 @@ restart: adr r0, LC0 * r0 = delta * r2 = BSS start * r3 = BSS end - * r4 = final kernel address + * r4 = final kernel address (possibly with LSB set) * r5 = appended dtb size (still unknown) * r6 = _edata * r7 = architecture ID @@ -276,6 +284,7 @@ restart: adr r0, LC0 */ cmp r0, #1 sub r0, r4, #TEXT_OFFSET + bic r0, r0, #1 add r0, r0, #0x100 mov r1, r6 sub r2, sp, r6 @@ -322,12 +331,13 @@ dtb_check_done: /* * Check to see if we will overwrite ourselves. - * r4 = final kernel address + * r4 = final kernel address (possibly with LSB set) * r9 = size of decompressed image * r10 = end of this image, including bss/stack/malloc space if non XIP * We basically want: * r4 - 16k page directory >= r10 -> OK * r4 + image length <= address of wont_overwrite -> OK + * Note: the possible LSB in r4 is harmless here. */ add r10, r10, #16384 cmp r4, r10 @@ -389,7 +399,8 @@ dtb_check_done: add sp, sp, r6 #endif - bl cache_clean_flush + tst r4, #1 + bleq cache_clean_flush adr r0, BSYM(restart) add r0, r0, r6 @@ -401,7 +412,7 @@ wont_overwrite: * r0 = delta * r2 = BSS start * r3 = BSS end - * r4 = kernel execution address + * r4 = kernel execution address (possibly with LSB set) * r5 = appended dtb size (0 if not present) * r7 = architecture ID * r8 = atags pointer @@ -464,6 +475,15 @@ not_relocated: mov r0, #0 cmp r2, r3 blo 1b + /* + * Did we skip the cache setup earlier? + * That is indicated by the LSB in r4. + * Do it now if so. + */ + tst r4, #1 + bic r4, r4, #1 + blne cache_on + /* * The C runtime environment should now be setup sufficiently. * Set up some pointers, and start decompressing. @@ -512,6 +532,7 @@ LC0: .word LC0 @ r1 .word _got_start @ r11 .word _got_end @ ip .word .L_user_stack_end @ sp + .word _end - restart + 16384 + 1024*1024 .size LC0, . - LC0 #ifdef CONFIG_ARCH_RPC @@ -805,8 +826,8 @@ call_cache_fn: adr r12, proc_types .align 2 .type proc_types,#object proc_types: - .word 0x00000000 @ old ARM ID - .word 0x0000f000 + .word 0x41000000 @ old ARM ID + .word 0xff00f000 mov pc, lr THUMB( nop ) mov pc, lr diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b9f7121e6ecf..641b3c9a7028 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -16,11 +16,13 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb # sam9g20 +dtb-$(CONFIG_ARCH_AT91) += at91-foxg20.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb +dtb-$(CONFIG_ARCH_AT91) += usb_a9g20_lpw.dtb # sam9g45 dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb @@ -57,6 +59,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos5440-sd5v1.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ + exynos5420-smdk5420.dtb \ exynos5440-ssdk5440.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ ecx-2000.dtb @@ -64,6 +67,8 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ integratorcp.dtb dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ + kirkwood-db-88f6281.dtb \ + kirkwood-db-88f6282.dtb \ kirkwood-dns320.dtb \ kirkwood-dns325.dtb \ kirkwood-dockstar.dtb \ @@ -84,6 +89,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ kirkwood-ns2max.dtb \ kirkwood-ns2mini.dtb \ kirkwood-nsa310.dtb \ + kirkwood-sheevaplug.dtb \ + kirkwood-sheevaplug-esata.dtb \ kirkwood-topkick.dtb \ kirkwood-ts219-6281.dtb \ kirkwood-ts219-6282.dtb \ @@ -103,13 +110,15 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx27-apf27.dtb \ imx27-apf27dev.dtb \ imx27-pdk.dtb \ - imx27-phytec-phycore.dtb \ + imx27-phytec-phycore-som.dtb \ + imx27-phytec-phycore-rdk.dtb \ imx31-bug.dtb \ imx51-apf51.dtb \ imx51-apf51dev.dtb \ imx51-babbage.dtb \ imx53-ard.dtb \ imx53-evk.dtb \ + imx53-m53evk.dtb \ imx53-mba53.dtb \ imx53-qsb.dtb \ imx53-smd.dtb \ @@ -117,10 +126,13 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6dl-sabresd.dtb \ imx6dl-wandboard.dtb \ imx6q-arm2.dtb \ + imx6q-phytec-pbab01.dtb \ imx6q-sabreauto.dtb \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ - imx6q-sbc6x.dtb + imx6q-sbc6x.dtb \ + imx6sl-evk.dtb \ + vf610-twr.dtb dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx23-olinuxino.dtb \ imx23-stmp378x_devb.dtb \ @@ -130,11 +142,16 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx28-cfa10036.dtb \ imx28-cfa10037.dtb \ imx28-cfa10049.dtb \ + imx28-cfa10055.dtb \ + imx28-cfa10057.dtb \ imx28-evk.dtb \ imx28-m28evk.dtb \ imx28-sps1.dtb \ imx28-tx28.dtb dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb +dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \ + nspire-tp.dtb \ + nspire-clp.dtb dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap3430-sdp.dtb \ omap3-beagle.dtb \ @@ -149,19 +166,26 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap4-panda-es.dtb \ omap4-var-som.dtb \ omap4-sdp.dtb \ - omap5-evm.dtb \ + omap4-sdp-es23plus.dtb \ + omap5-uevm.dtb \ am335x-evm.dtb \ am335x-evmsk.dtb \ - am335x-bone.dtb + am335x-bone.dtb \ + am3517-evm.dtb \ + am3517_mt_ventoux.dtb \ + am43x-epos-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \ hrefprev60.dtb \ hrefv60plus.dtb \ + ccu8540.dtb \ ccu9540.dtb +dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a7740-armadillo800eva.dtb \ r8a7778-bockw.dtb \ + r8a7740-armadillo800eva-reference.dtb \ r8a7779-marzen-reference.dtb \ r8a7790-lager.dtb \ sh73a0-kzm9g.dtb \ @@ -177,8 +201,15 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ spear320-evb.dtb \ spear320-hmi.dtb dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \ +dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \ + stih416-b2000.dtb \ + stih415-b2020.dtb \ + stih416-b2020.dtb +dtb-$(CONFIG_ARCH_SUNXI) += \ + sun4i-a10-cubieboard.dtb \ + sun4i-a10-mini-xplus.dtb \ sun4i-a10-hackberry.dtb \ + sun5i-a10s-olinuxino-micro.dtb \ sun5i-a13-olinuxino.dtb dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-iris-512.dtb \ @@ -197,6 +228,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra114-pluto.dtb dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ versatile-pb.dtb +dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ vexpress-v2p-ca9.dtb \ vexpress-v2p-ca15-tc1.dtb \ @@ -205,8 +237,11 @@ dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ wm8505-ref.dtb \ wm8650-mid.dtb \ + wm8750-apc8750.dtb \ wm8850-w70v2.dtb -dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb +dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ + zynq-zc706.dtb \ + zynq-zed.dtb targets += dtbs targets += $(dtb-y) diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts index 29b9f15e7599..54cb5cf8604a 100644 --- a/arch/arm/boot/dts/aks-cdu.dts +++ b/arch/arm/boot/dts/aks-cdu.dts @@ -9,7 +9,7 @@ /dts-v1/; -/include/ "ge863-pro3.dtsi" +#include "ge863-pro3.dtsi" / { chosen { @@ -46,7 +46,7 @@ }; usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 15 0>; + atmel,vbus-gpio = <&pioC 15 GPIO_ACTIVE_HIGH>; status = "okay"; }; }; @@ -90,23 +90,23 @@ compatible = "gpio-leds"; red { - gpios = <&pioC 10 0>; + gpios = <&pioC 10 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; }; green { - gpios = <&pioA 5 1>; + gpios = <&pioA 5 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; default-state = "on"; }; yellow { - gpios = <&pioB 20 1>; + gpios = <&pioB 20 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; blue { - gpios = <&pioB 21 1>; + gpios = <&pioB 21 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; }; diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index 5302f79c05b7..04feaf8f1420 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "am33xx.dtsi" +#include "am33xx.dtsi" / { model = "TI AM335x BeagleBone"; @@ -26,24 +26,104 @@ am33xx_pinmux: pinmux@44e10800 { pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; + pinctrl-0 = <&clkout2_pin>; user_leds_s0: user_leds_s0 { pinctrl-single,pins = < - 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */ - 0x58 0x17 /* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */ - 0x5c 0x7 /* gpmc_a7.gpio1_23, OUTPUT | MODE7 */ - 0x60 0x17 /* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */ + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ + 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ + 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ + 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ + 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ + 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ + 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ + 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; }; ocp { - uart1: serial@44e09000 { + uart0: serial@44e09000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; }; i2c0: i2c@44e0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; clock-frequency = <400000>; @@ -55,31 +135,34 @@ }; leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + compatible = "gpio-leds"; led@2 { label = "beaglebone:green:heartbeat"; - gpios = <&gpio1 21 0>; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; led@3 { label = "beaglebone:green:mmc0"; - gpios = <&gpio1 22 0>; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; led@4 { label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 0>; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led@5 { label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 0>; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; @@ -136,3 +219,16 @@ &cpsw_emac1 { phy_id = <&davinci_mdio>, <1>; }; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; +}; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 0423298a26fe..a16bb9691cc6 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "am33xx.dtsi" +#include "am33xx.dtsi" / { model = "TI AM335x EVM"; @@ -26,32 +26,143 @@ am33xx_pinmux: pinmux@44e10800 { pinctrl-names = "default"; - pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>; + pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; matrix_keypad_s0: matrix_keypad_s0 { pinctrl-single,pins = < - 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */ - 0x58 0x7 /* gpmc_a6.gpio1_22, OUTPUT | MODE7 */ - 0x64 0x27 /* gpmc_a9.gpio1_25, INPUT | MODE7 */ - 0x68 0x27 /* gpmc_a10.gpio1_26, INPUT | MODE7 */ - 0x6c 0x27 /* gpmc_a11.gpio1_27, INPUT | MODE7 */ + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ >; }; volume_keys_s0: volume_keys_s0 { pinctrl-single,pins = < - 0x150 0x27 /* spi0_sclk.gpio0_2, INPUT | MODE7 */ - 0x154 0x27 /* spi0_d0.gpio0_3, INPUT | MODE7 */ + 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ + 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ + 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + nandflash_pins_s0: nandflash_pins_s0 { + pinctrl-single,pins = < + 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; + + ecap0_pins: backlight_pins { + pinctrl-single,pins = < + 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; }; ocp { - uart1: serial@44e09000 { + uart0: serial@44e09000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; }; i2c0: i2c@44e0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; clock-frequency = <400000>; @@ -61,6 +172,9 @@ }; i2c1: i2c@4802a000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; clock-frequency = <100000>; @@ -102,6 +216,101 @@ reg = <0x48>; }; }; + + elm: elm@48080000 { + status = "okay"; + }; + + epwmss0: epwmss@48300000 { + status = "okay"; + + ecap0: ecap@48300100 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; + }; + }; + + gpmc: gpmc@50000000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins_s0>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + gpmc,device-nand = "true"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + elm_id = <&elm>; + + /* MTD partition table */ + partition@0 { + label = "SPL1"; + reg = <0x00000000 0x000020000>; + }; + + partition@1 { + label = "SPL2"; + reg = <0x00020000 0x00020000>; + }; + + partition@2 { + label = "SPL3"; + reg = <0x00040000 0x00020000>; + }; + + partition@3 { + label = "SPL4"; + reg = <0x00060000 0x00020000>; + }; + + partition@4 { + label = "U-boot"; + reg = <0x00080000 0x001e0000>; + }; + + partition@5 { + label = "environment"; + reg = <0x00260000 0x00020000>; + }; + + partition@6 { + label = "Kernel"; + reg = <0x00280000 0x00500000>; + }; + + partition@7 { + label = "File-System"; + reg = <0x00780000 0x0F880000>; + }; + }; + }; }; vbat: fixedregulator@0 { @@ -123,12 +332,12 @@ debounce-delay-ms = <5>; col-scan-delay-us = <2>; - row-gpios = <&gpio1 25 0 /* Bank1, pin25 */ - &gpio1 26 0 /* Bank1, pin26 */ - &gpio1 27 0>; /* Bank1, pin27 */ + row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ + &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ + &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ - col-gpios = <&gpio1 21 0 /* Bank1, pin21 */ - &gpio1 22 0>; /* Bank1, pin22 */ + col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ + &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ linux,keymap = <0x0000008b /* MENU */ 0x0100009e /* BACK */ @@ -147,20 +356,27 @@ switch@9 { label = "volume-up"; linux,code = <115>; - gpios = <&gpio0 2 1>; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; gpio-key,wakeup; }; switch@10 { label = "volume-down"; linux,code = <114>; - gpios = <&gpio0 3 1>; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; gpio-key,wakeup; }; }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 0>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; }; -/include/ "tps65910.dtsi" +#include "tps65910.dtsi" &tps { vcc1-supply = <&vbat>; @@ -237,6 +453,18 @@ }; }; +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; +}; + &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; }; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index f67c360844f4..9e00eef9b74b 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -13,7 +13,7 @@ /dts-v1/; -/include/ "am33xx.dtsi" +#include "am33xx.dtsi" / { model = "TI AM335x EVM-SK"; @@ -32,33 +32,145 @@ am33xx_pinmux: pinmux@44e10800 { pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0 &gpio_keys_s0>; + pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; user_leds_s0: user_leds_s0 { pinctrl-single,pins = < - 0x10 0x7 /* gpmc_ad4.gpio1_4, OUTPUT | MODE7 */ - 0x14 0x7 /* gpmc_ad5.gpio1_5, OUTPUT | MODE7 */ - 0x18 0x7 /* gpmc_ad6.gpio1_6, OUTPUT | MODE7 */ - 0x1c 0x7 /* gpmc_ad7.gpio1_7, OUTPUT | MODE7 */ + 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ + 0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ + 0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ + 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ >; }; gpio_keys_s0: gpio_keys_s0 { pinctrl-single,pins = < - 0x94 0x27 /* gpmc_oen_ren.gpio2_3, INPUT | MODE7 */ - 0x90 0x27 /* gpmc_advn_ale.gpio2_2, INPUT | MODE7 */ - 0x70 0x27 /* gpmc_wait0.gpio0_30, INPUT | MODE7 */ - 0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT | MODE7 */ + 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ + 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ + 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ + 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + ecap2_pins: backlight_pins { + pinctrl-single,pins = < + 0x19c 0x4 /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + + /* Slave 2 */ + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + + /* Slave 2 reset value*/ + 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; }; ocp { - uart1: serial@44e09000 { + uart0: serial@44e09000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; }; i2c0: i2c@44e0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; clock-frequency = <400000>; @@ -94,6 +206,16 @@ st,max-limit-z = <750>; }; }; + + epwmss2: epwmss@48304000 { + status = "okay"; + + ecap2: ecap@48304100 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap2_pins>; + }; + }; }; vbat: fixedregulator@0 { @@ -111,30 +233,33 @@ }; leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + compatible = "gpio-leds"; led@1 { label = "evmsk:green:usr0"; - gpios = <&gpio1 4 0>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led@2 { label = "evmsk:green:usr1"; - gpios = <&gpio1 5 0>; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led@3 { label = "evmsk:green:mmc0"; - gpios = <&gpio1 6 0>; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; led@4 { label = "evmsk:green:heartbeat"; - gpios = <&gpio1 7 0>; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; @@ -148,31 +273,38 @@ switch@1 { label = "button0"; linux,code = <0x100>; - gpios = <&gpio2 3 0>; + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; }; switch@2 { label = "button1"; linux,code = <0x101>; - gpios = <&gpio2 2 0>; + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; }; switch@3 { label = "button2"; linux,code = <0x102>; - gpios = <&gpio0 30 0>; + gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; gpio-key,wakeup; }; switch@4 { label = "button3"; linux,code = <0x103>; - gpios = <&gpio2 5 0>; + gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; }; }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap2 0 50000 1>; + brightness-levels = <0 58 61 66 75 90 125 170 255>; + default-brightness-level = <8>; + }; }; -/include/ "tps65910.dtsi" +#include "tps65910.dtsi" &tps { vcc1-supply = <&vbat>; @@ -248,3 +380,15 @@ }; }; }; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; +}; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 1460d9b88adf..0d4df90477f7 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -8,26 +8,33 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/am33xx.h> + +#include "skeleton.dtsi" / { compatible = "ti,am33xx"; interrupt-parent = <&intc>; aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; d_can0 = &dcan0; d_can1 = &dcan1; }; cpus { + #address-cells = <1>; + #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a8"; + device_type = "cpu"; + reg = <0>; /* * To consider voltage drop between PMIC and SoC, @@ -133,7 +140,7 @@ interrupts = <62>; }; - uart1: serial@44e09000 { + uart0: serial@44e09000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart1"; clock-frequency = <48000000>; @@ -142,7 +149,7 @@ status = "disabled"; }; - uart2: serial@48022000 { + uart1: serial@48022000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart2"; clock-frequency = <48000000>; @@ -151,7 +158,7 @@ status = "disabled"; }; - uart3: serial@48024000 { + uart2: serial@48024000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart3"; clock-frequency = <48000000>; @@ -160,7 +167,7 @@ status = "disabled"; }; - uart4: serial@481a6000 { + uart3: serial@481a6000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart4"; clock-frequency = <48000000>; @@ -169,7 +176,7 @@ status = "disabled"; }; - uart5: serial@481a8000 { + uart4: serial@481a8000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart5"; clock-frequency = <48000000>; @@ -178,7 +185,7 @@ status = "disabled"; }; - uart6: serial@481aa000 { + uart5: serial@481aa000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart6"; clock-frequency = <48000000>; @@ -343,6 +350,90 @@ ti,hwmods = "usb_otg_hs"; }; + epwmss0: epwmss@48300000 { + compatible = "ti,am33xx-pwmss"; + reg = <0x48300000 0x10>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0x48300100 0x48300100 0x80 /* ECAP */ + 0x48300180 0x48300180 0x80 /* EQEP */ + 0x48300200 0x48300200 0x80>; /* EHRPWM */ + + ecap0: ecap@48300100 { + compatible = "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48300100 0x80>; + ti,hwmods = "ecap0"; + status = "disabled"; + }; + + ehrpwm0: ehrpwm@48300200 { + compatible = "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48300200 0x80>; + ti,hwmods = "ehrpwm0"; + status = "disabled"; + }; + }; + + epwmss1: epwmss@48302000 { + compatible = "ti,am33xx-pwmss"; + reg = <0x48302000 0x10>; + ti,hwmods = "epwmss1"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0x48302100 0x48302100 0x80 /* ECAP */ + 0x48302180 0x48302180 0x80 /* EQEP */ + 0x48302200 0x48302200 0x80>; /* EHRPWM */ + + ecap1: ecap@48302100 { + compatible = "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48302100 0x80>; + ti,hwmods = "ecap1"; + status = "disabled"; + }; + + ehrpwm1: ehrpwm@48302200 { + compatible = "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48302200 0x80>; + ti,hwmods = "ehrpwm1"; + status = "disabled"; + }; + }; + + epwmss2: epwmss@48304000 { + compatible = "ti,am33xx-pwmss"; + reg = <0x48304000 0x10>; + ti,hwmods = "epwmss2"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0x48304100 0x48304100 0x80 /* ECAP */ + 0x48304180 0x48304180 0x80 /* EQEP */ + 0x48304200 0x48304200 0x80>; /* EHRPWM */ + + ecap2: ecap@48304100 { + compatible = "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48304100 0x80>; + ti,hwmods = "ecap2"; + status = "disabled"; + }; + + ehrpwm2: ehrpwm@48304200 { + compatible = "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48304200 0x80>; + ti,hwmods = "ehrpwm2"; + status = "disabled"; + }; + }; + mac: ethernet@4a100000 { compatible = "ti,cpsw"; ti,hwmods = "cpgmac0"; @@ -394,7 +485,6 @@ compatible = "ti,am3352-ocmcram"; reg = <0x40300000 0x10000>; ti,hwmods = "ocmcram"; - ti,no_idle_on_suspend; }; wkup_m3: wkup_m3@44d00000 { @@ -404,13 +494,21 @@ ti,hwmods = "wkup_m3"; }; + elm: elm@48080000 { + compatible = "ti,am3352-elm"; + reg = <0x48080000 0x2000>; + interrupts = <4>; + ti,hwmods = "elm"; + status = "disabled"; + }; + gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; reg = <0x50000000 0x2000>; interrupts = <100>; - num-cs = <7>; - num-waitpins = <2>; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; status = "disabled"; diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index e9b5bdae4908..e99dfaf70052 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap34xx.dtsi" +#include "omap34xx.dtsi" / { model = "TI AM3517 EVM (AM3517/05)"; diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts index 556868388a23..fdf5ce63c8e6 100644 --- a/arch/arm/boot/dts/am3517_mt_ventoux.dts +++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap34xx.dtsi" +#include "omap34xx.dtsi" / { model = "TeeJet Mt.Ventoux"; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi new file mode 100644 index 000000000000..ddc1df77ac52 --- /dev/null +++ b/arch/arm/boot/dts/am4372.dtsi @@ -0,0 +1,68 @@ +/* + * Device Tree Source for AM4372 SoC + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include "skeleton.dtsi" + +/ { + compatible = "ti,am4372", "ti,am43"; + interrupt-parent = <&gic>; + + + aliases { + serial0 = &uart0; + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a9"; + }; + }; + + gic: interrupt-controller@48241000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48241000 0x1000>, + <0x48240100 0x0100>; + }; + + ocp { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart0: serial@44e09000 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x44e09000 0x2000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer1: timer@44e31000 { + compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; + reg = <0x44e31000 0x400>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-alwon; + }; + + timer2: timer@48040000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x48040000 0x400>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + }; + + counter32k: counter@44e86000 { + compatible = "ti,am4372-counter32k","ti,omap-counter32k"; + reg = <0x44e86000 0x40>; + }; + }; +}; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts new file mode 100644 index 000000000000..74174d48f476 --- /dev/null +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* AM43x EPOS EVM */ + +/dts-v1/; + +#include "am4372.dtsi" + +/ { + model = "TI AM43x EPOS EVM"; + compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43"; +}; diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index 5160210f74da..3a1de9eb5111 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "at91sam9260.dtsi" +#include "at91sam9260.dtsi" / { model = "Somfy Animeo IP"; @@ -123,7 +123,7 @@ usb0: ohci@00500000 { num-ports = <2>; - atmel,vbus-gpio = <&pioB 15 1>; + atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>; status = "okay"; }; }; @@ -133,23 +133,23 @@ power_green { label = "power_green"; - gpios = <&pioC 17 0>; + gpios = <&pioC 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; power_red { label = "power_red"; - gpios = <&pioA 2 0>; + gpios = <&pioA 2 GPIO_ACTIVE_HIGH>; }; tx_green { label = "tx_green"; - gpios = <&pioC 19 0>; + gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; }; tx_red { label = "tx_red"; - gpios = <&pioC 18 0>; + gpios = <&pioC 18 GPIO_ACTIVE_HIGH>; }; }; @@ -160,21 +160,21 @@ keyswitch_in { label = "keyswitch_in"; - gpios = <&pioB 1 0>; + gpios = <&pioB 1 GPIO_ACTIVE_HIGH>; linux,code = <28>; gpio-key,wakeup; }; error_in { label = "error_in"; - gpios = <&pioB 2 0>; + gpios = <&pioB 2 GPIO_ACTIVE_HIGH>; linux,code = <29>; gpio-key,wakeup; }; btn { label = "btn"; - gpios = <&pioC 23 0>; + gpios = <&pioC 23 GPIO_ACTIVE_HIGH>; linux,code = <31>; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 2353b1f13704..beee1699d49e 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -74,6 +74,7 @@ */ status = "disabled"; /* No CD or WP GPIOs */ + broken-cd; }; usb@50000 { diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 14e36e19d515..45b107763e3b 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -99,6 +99,7 @@ * No CD or WP GPIOs: SDIO interface used for * Wifi/Bluetooth chip */ + broken-cd; }; usb@50000 { diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 130f8390a7e4..a3a2fedb8726 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -64,6 +64,7 @@ pinctrl-names = "default"; status = "okay"; /* No CD or WP GPIOs */ + broken-cd; }; usb@50000 { @@ -84,6 +85,22 @@ gpios = <&gpio0 6 1>; }; }; + + pcie-controller { + status = "okay"; + + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Internal mini-PCIe connector */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 272bbc65fab0..90b117624abb 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -22,9 +22,18 @@ model = "Marvell Armada 370 and XP SoC"; compatible = "marvell,armada-370-xp"; + aliases { + eth0 = ð0; + eth1 = ð1; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; cpu@0 { compatible = "marvell,sheeva-v7"; + device_type = "cpu"; + reg = <0>; }; }; @@ -33,7 +42,8 @@ #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&mpic>; - ranges = <0 0 0xd0000000 0x100000>; + ranges = <0 0 0xd0000000 0x0100000 /* internal registers */ + 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>; internal-regs { compatible = "simple-bus"; @@ -79,7 +89,7 @@ sata@a0000 { compatible = "marvell,orion-sata"; - reg = <0xa0000 0x2400>; + reg = <0xa0000 0x5000>; interrupts = <55>; clocks = <&gateclk 15>, <&gateclk 30>; clock-names = "0", "1"; @@ -93,17 +103,17 @@ reg = <0x72004 0x4>; }; - ethernet@70000 { + eth0: ethernet@70000 { compatible = "marvell,armada-370-neta"; - reg = <0x70000 0x2500>; + reg = <0x70000 0x4000>; interrupts = <8>; clocks = <&gateclk 4>; status = "disabled"; }; - ethernet@74000 { + eth1: ethernet@74000 { compatible = "marvell,armada-370-neta"; - reg = <0x74000 0x2500>; + reg = <0x74000 0x4000>; interrupts = <10>; clocks = <&gateclk 3>; status = "disabled"; @@ -142,6 +152,10 @@ reg = <0xd4000 0x200>; interrupts = <54>; clocks = <&gateclk 17>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; status = "disabled"; }; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index b2c1b5af9749..fa3dfc6b4c6a 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -29,7 +29,8 @@ }; soc { - ranges = <0 0xd0000000 0x100000>; + ranges = <0 0xd0000000 0x0100000 /* internal registers */ + 0xe0000000 0xe0000000 0x8100000 /* PCIe */>; internal-regs { system-controller@18200 { compatible = "marvell,armada-370-xp-system-controller"; @@ -38,12 +39,12 @@ L2: l2-cache { compatible = "marvell,aurora-outer-cache"; - reg = <0xd0008000 0x1000>; + reg = <0x08000 0x1000>; cache-id-part = <0x100>; wt-override; }; - mpic: interrupt-controller@20000 { + interrupt-controller@20000 { reg = <0x20a00 0x1d0>, <0x21870 0x58>; }; @@ -179,10 +180,6 @@ bus-range = <0x00 0xff>; - reg = <0x40000 0x2000>, <0x80000 0x2000>; - - reg-names = "pcie0.0", "pcie1.0"; - ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index d6cc8bf8272e..e28e68ff864d 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -30,6 +30,10 @@ }; soc { + ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ + 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ + 0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */ + internal-regs { serial@12000 { clock-frequency = <250000000>; @@ -97,6 +101,7 @@ pinctrl-names = "default"; status = "okay"; /* No CD or WP GPIOs */ + broken-cd; }; usb@50000 { @@ -155,6 +160,35 @@ status = "okay"; }; }; + + devbus-bootcs@10400 { + status = "okay"; + ranges = <0 0xf0000000 0x1000000>; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 16 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <2>; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 26ad06fc147e..c87b2de29c30 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -39,6 +39,10 @@ }; soc { + ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ + 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ + 0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB */>; + internal-regs { serial@12000 { clock-frequency = <250000000>; @@ -101,6 +105,16 @@ phy-mode = "rgmii-id"; }; + /* Front-side USB slot */ + usb@50000 { + status = "okay"; + }; + + /* Back-side USB slot */ + usb@51000 { + status = "okay"; + }; + spi0: spi@10600 { status = "okay"; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index f4029f015aff..2d9335da210c 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -92,7 +92,7 @@ ethernet@34000 { compatible = "marvell,armada-370-neta"; - reg = <0x34000 0x2500>; + reg = <0x34000 0x4000>; interrupts = <14>; clocks = <&gateclk 1>; status = "disabled"; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 6ab56bd35de9..c7b1f4d5c1c7 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -23,6 +23,7 @@ gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; + eth3 = ð3; }; @@ -105,9 +106,9 @@ interrupts = <91>; }; - ethernet@34000 { + eth3: ethernet@34000 { compatible = "marvell,armada-370-neta"; - reg = <0x34000 0x2500>; + reg = <0x34000 0x4000>; interrupts = <14>; clocks = <&gateclk 1>; status = "disabled"; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index f14d36c46159..8f510458ea86 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -27,6 +27,10 @@ }; soc { + ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ + 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ + 0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>; + internal-regs { serial@12000 { clock-frequency = <250000000>; @@ -134,13 +138,22 @@ nr-ports = <2>; status = "okay"; }; + + /* Front side USB 0 */ usb@50000 { status = "okay"; }; + + /* Front side USB 1 */ usb@51000 { status = "okay"; }; + /* USB interface in the mini-PCIe connector */ + usb@52000 { + status = "okay"; + }; + devbus-bootcs@10400 { status = "okay"; ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index bacab11c10dc..416eb9481844 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -22,6 +22,10 @@ model = "Marvell Armada XP family SoC"; compatible = "marvell,armadaxp", "marvell,armada-370-xp"; + aliases { + eth2 = ð2; + }; + soc { internal-regs { L2: l2-cache { @@ -31,7 +35,7 @@ wt-override; }; - mpic: interrupt-controller@20000 { + interrupt-controller@20000 { reg = <0x20a00 0x2d0>, <0x21070 0x58>; }; @@ -86,9 +90,9 @@ reg = <0x18200 0x500>; }; - ethernet@30000 { + eth2: ethernet@30000 { compatible = "marvell,armada-370-neta"; - reg = <0x30000 0x2500>; + reg = <0x30000 0x4000>; interrupts = <12>; clocks = <&gateclk 2>; status = "disabled"; diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts index c7aebba4e8e7..cce45f5177f9 100644 --- a/arch/arm/boot/dts/at91-ariag25.dts +++ b/arch/arm/boot/dts/at91-ariag25.dts @@ -7,7 +7,7 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9g25.dtsi" +#include "at91sam9g25.dtsi" / { model = "Acme Systems Aria G25"; @@ -21,6 +21,7 @@ serial3 = &usart2; serial4 = &usart3; serial5 = &uart0; + serial6 = &uart1; }; chosen { @@ -112,13 +113,17 @@ status = "okay"; }; + /* + * UART0/1 pins are marked as GPIO on + * Aria documentation. + * Change to "okay" if you need additional serial ports + */ uart0: serial@f8040000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8040000 0x200>; - interrupts = <15 4 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; + status = "disabled"; + }; + + uart1: serial@f8044000 { + status = "disabled"; }; adc0: adc@f804c000 { @@ -138,6 +143,10 @@ }; }; }; + + rtc@fffffeb0 { + status = "okay"; + }; }; usb0: ohci@00600000 { @@ -156,7 +165,7 @@ /* little green LED in middle of Aria G25 module */ aria_led { label = "aria_led"; - gpios = <&pioB 8 0>; /* PB8 */ + gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */ linux,default-trigger = "heartbeat"; }; @@ -164,7 +173,7 @@ onewire@0 { compatible = "w1-gpio"; - gpios = <&pioA 21 1>; + gpios = <&pioA 21 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_w1_0>; }; diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts new file mode 100644 index 000000000000..cbe967343997 --- /dev/null +++ b/arch/arm/boot/dts/at91-foxg20.dts @@ -0,0 +1,157 @@ +/* + * at91-foxg20.dts - Device Tree file for Acme Systems FoxG20 board + * + * Based on DT files for at91sam9g20ek evaluation board (AT91SAM9G20 SoC) + * + * Copyright (C) 2013 Douglas Gilbert <dgilbert@interlog.com> + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9g20.dtsi" + +/ { + model = "Acme Systems FoxG20"; + compatible = "acme,foxg20", "atmel,at91sam9g20", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mmc0: mmc@fffa8000 { + pinctrl-0 = < + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot1_cmd_dat0 + &pinctrl_mmc0_slot1_dat1_3>; + status = "okay"; + + slot@1 { + reg = <1>; + bus-width = <4>; + }; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + >; + status = "okay"; + }; + + usart1: serial@fffb4000 { + status = "okay"; + }; + + usart2: serial@fffb8000 { + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usart3: serial@fffd0000 { + status = "okay"; + }; + + uart0: serial@fffd4000 { + status = "okay"; + }; + + uart1: serial@fffd8000 { + status = "okay"; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + pinctrl@fffff400 { + board { + pinctrl_pck0_as_mck: pck0_as_mck { + atmel,pins = + <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; + + mmc0_slot1 { + pinctrl_board_mmc0_slot1: mmc0_slot1-board { + atmel,pins = + <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* CD pin */ + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* TWD (SDA), open drain */ + AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* TWCK (SCL), open drain */ + }; + }; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + }; + + i2c@0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + i2c-gpio,delay-us = <5>; /* ~85 kHz */ + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + + /* red LED marked "PC7" near mini USB (device) receptacle */ + user_led { + label = "user_led"; + gpios = <&pioC 7 GPIO_ACTIVE_HIGH>; /* PC7 */ + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + btn { + label = "Button"; + gpios = <&pioC 4 GPIO_ACTIVE_LOW>; + linux,code = <0x103>; + gpio-key,wakeup; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 5d3ed5aafc69..92b9e21389db 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -10,7 +10,10 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Atmel AT91RM9200 family SoC"; @@ -35,8 +38,12 @@ ssc2 = &ssc2; }; cpus { - cpu@0 { + #address-cells = <0>; + #size-cells = <0>; + + cpu { compatible = "arm,arm920t"; + device_type = "cpu"; }; }; @@ -77,25 +84,29 @@ st: timer@fffffd00 { compatible = "atmel,at91rm9200-st"; reg = <0xfffffd00 0x100>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; tcb0: timer@fffa0000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfffa0000 0x100>; - interrupts = <17 4 0 18 4 0 19 4 0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 + 18 IRQ_TYPE_LEVEL_HIGH 0 + 19 IRQ_TYPE_LEVEL_HIGH 0>; }; tcb1: timer@fffa4000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfffa4000 0x100>; - interrupts = <20 4 0 21 4 0 22 4 0>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 + 21 IRQ_TYPE_LEVEL_HIGH 0 + 22 IRQ_TYPE_LEVEL_HIGH 0>; }; i2c0: i2c@fffb8000 { compatible = "atmel,at91rm9200-i2c"; reg = <0xfffb8000 0x4000>; - interrupts = <12 4 6>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_twi>; #address-cells = <1>; @@ -106,7 +117,7 @@ mmc0: mmc@fffb4000 { compatible = "atmel,hsmci"; reg = <0xfffb4000 0x4000>; - interrupts = <10 4 0>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -115,7 +126,7 @@ ssc0: ssc@fffd0000 { compatible = "atmel,at91rm9200-ssc"; reg = <0xfffd0000 0x4000>; - interrupts = <14 4 5>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disable"; @@ -124,7 +135,7 @@ ssc1: ssc@fffd4000 { compatible = "atmel,at91rm9200-ssc"; reg = <0xfffd4000 0x4000>; - interrupts = <15 4 5>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; status = "disable"; @@ -133,7 +144,7 @@ ssc2: ssc@fffd8000 { compatible = "atmel,at91rm9200-ssc"; reg = <0xfffd8000 0x4000>; - interrupts = <16 4 5>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; status = "disable"; @@ -142,7 +153,7 @@ macb0: ethernet@fffbc000 { compatible = "cdns,at91rm9200-emac", "cdns,emac"; reg = <0xfffbc000 0x4000>; - interrupts = <24 4 3>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; @@ -167,234 +178,319 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <0 30 0x1 0x0 /* PA30 periph A */ - 0 31 0x1 0x1>; /* PA31 periph with pullup */ + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A */ + AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA31 periph with pullup */ }; }; uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - <0 17 0x1 0x0 /* PA17 periph A */ - 0 18 0x1 0x0>; /* PA18 periph A */ + <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ + AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */ }; pinctrl_uart0_rts: uart0_rts-0 { atmel,pins = - <0 20 0x1 0x0>; /* PA20 periph A */ + <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */ }; pinctrl_uart0_cts: uart0_cts-0 { atmel,pins = - <0 21 0x1 0x0>; /* PA21 periph A */ + <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ }; }; uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - <1 20 0x1 0x1 /* PB20 periph A with pullup */ - 1 21 0x1 0x0>; /* PB21 periph A */ + <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB20 periph A with pullup */ + AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */ }; pinctrl_uart1_rts: uart1_rts-0 { atmel,pins = - <1 24 0x1 0x0>; /* PB24 periph A */ + <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */ }; pinctrl_uart1_cts: uart1_cts-0 { atmel,pins = - <1 26 0x1 0x0>; /* PB26 periph A */ + <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */ }; pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 { atmel,pins = - <1 19 0x1 0x0 /* PB19 periph A */ - 1 25 0x1 0x0>; /* PB25 periph A */ + <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */ + AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */ }; pinctrl_uart1_dcd: uart1_dcd-0 { atmel,pins = - <1 23 0x1 0x0>; /* PB23 periph A */ + <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */ }; pinctrl_uart1_ri: uart1_ri-0 { atmel,pins = - <1 18 0x1 0x0>; /* PB18 periph A */ + <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ }; }; uart2 { pinctrl_uart2: uart2-0 { atmel,pins = - <0 22 0x1 0x0 /* PA22 periph A */ - 0 23 0x1 0x1>; /* PA23 periph A with pullup */ + <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA22 periph A */ + AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */ }; pinctrl_uart2_rts: uart2_rts-0 { atmel,pins = - <0 30 0x2 0x0>; /* PA30 periph B */ + <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ }; pinctrl_uart2_cts: uart2_cts-0 { atmel,pins = - <0 31 0x2 0x0>; /* PA31 periph B */ + <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */ }; }; uart3 { pinctrl_uart3: uart3-0 { atmel,pins = - <0 5 0x2 0x1 /* PA5 periph B with pullup */ - 0 6 0x2 0x0>; /* PA6 periph B */ + <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */ + AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA6 periph B */ }; pinctrl_uart3_rts: uart3_rts-0 { atmel,pins = - <1 0 0x2 0x0>; /* PB0 periph B */ + <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ }; pinctrl_uart3_cts: uart3_cts-0 { atmel,pins = - <1 1 0x2 0x0>; /* PB1 periph B */ + <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ }; }; nand { pinctrl_nand: nand-0 { atmel,pins = - <2 2 0x0 0x1 /* PC2 gpio RDY pin pull_up */ - 1 1 0x0 0x1>; /* PB1 gpio CD pin pull_up */ + <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC2 gpio RDY pin pull_up */ + AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PB1 gpio CD pin pull_up */ }; }; macb { pinctrl_macb_rmii: macb_rmii-0 { atmel,pins = - <0 7 0x1 0x0 /* PA7 periph A */ - 0 8 0x1 0x0 /* PA8 periph A */ - 0 9 0x1 0x0 /* PA9 periph A */ - 0 10 0x1 0x0 /* PA10 periph A */ - 0 11 0x1 0x0 /* PA11 periph A */ - 0 12 0x1 0x0 /* PA12 periph A */ - 0 13 0x1 0x0 /* PA13 periph A */ - 0 14 0x1 0x0 /* PA14 periph A */ - 0 15 0x1 0x0 /* PA15 periph A */ - 0 16 0x1 0x0>; /* PA16 periph A */ + <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */ }; pinctrl_macb_rmii_mii: macb_rmii_mii-0 { atmel,pins = - <1 12 0x2 0x0 /* PB12 periph B */ - 1 13 0x2 0x0 /* PB13 periph B */ - 1 14 0x2 0x0 /* PB14 periph B */ - 1 15 0x2 0x0 /* PB15 periph B */ - 1 16 0x2 0x0 /* PB16 periph B */ - 1 17 0x2 0x0 /* PB17 periph B */ - 1 18 0x2 0x0 /* PB18 periph B */ - 1 19 0x2 0x0>; /* PB19 periph B */ + <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB12 periph B */ + AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB13 periph B */ + AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B */ + AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB15 periph B */ + AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB16 periph B */ + AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB17 periph B */ + AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB18 periph B */ + AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */ }; }; mmc0 { pinctrl_mmc0_clk: mmc0_clk-0 { atmel,pins = - <0 27 0x1 0x0>; /* PA27 periph A */ + <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */ }; pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { atmel,pins = - <0 28 0x1 0x1 /* PA28 periph A with pullup */ - 0 29 0x1 0x1>; /* PA29 periph A with pullup */ + <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */ + AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA29 periph A with pullup */ }; pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { atmel,pins = - <1 3 0x2 0x1 /* PB3 periph B with pullup */ - 1 4 0x2 0x1 /* PB4 periph B with pullup */ - 1 5 0x2 0x1>; /* PB5 periph B with pullup */ + <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */ + AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */ + AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PB5 periph B with pullup */ }; pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { atmel,pins = - <0 8 0x2 0x1 /* PA8 periph B with pullup */ - 0 9 0x2 0x1>; /* PA9 periph B with pullup */ + <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */ + AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA9 periph B with pullup */ }; pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { atmel,pins = - <0 10 0x2 0x1 /* PA10 periph B with pullup */ - 0 11 0x2 0x1 /* PA11 periph B with pullup */ - 0 12 0x2 0x1>; /* PA12 periph B with pullup */ + <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA10 periph B with pullup */ + AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ + AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA12 periph B with pullup */ }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx-0 { atmel,pins = - <1 0 0x1 0x0 /* PB0 periph A */ - 1 1 0x1 0x0 /* PB1 periph A */ - 1 2 0x1 0x0>; /* PB2 periph A */ + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A */ }; pinctrl_ssc0_rx: ssc0_rx-0 { atmel,pins = - <1 3 0x1 0x0 /* PB3 periph A */ - 1 4 0x1 0x0 /* PB4 periph A */ - 1 5 0x1 0x0>; /* PB5 periph A */ + <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ }; }; ssc1 { pinctrl_ssc1_tx: ssc1_tx-0 { atmel,pins = - <1 6 0x1 0x0 /* PB6 periph A */ - 1 7 0x1 0x0 /* PB7 periph A */ - 1 8 0x1 0x0>; /* PB8 periph A */ + <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ + AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ }; pinctrl_ssc1_rx: ssc1_rx-0 { atmel,pins = - <1 9 0x1 0x0 /* PB9 periph A */ - 1 10 0x1 0x0 /* PB10 periph A */ - 1 11 0x1 0x0>; /* PB11 periph A */ + <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ }; }; ssc2 { pinctrl_ssc2_tx: ssc2_tx-0 { atmel,pins = - <1 12 0x1 0x0 /* PB12 periph A */ - 1 13 0x1 0x0 /* PB13 periph A */ - 1 14 0x1 0x0>; /* PB14 periph A */ + <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */ }; pinctrl_ssc2_rx: ssc2_rx-0 { atmel,pins = - <1 15 0x1 0x0 /* PB15 periph A */ - 1 16 0x1 0x0 /* PB16 periph A */ - 1 17 0x1 0x0>; /* PB17 periph A */ + <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ }; }; twi { pinctrl_twi: twi-0 { atmel,pins = - <0 25 0x1 0x2 /* PA25 periph A with multi drive */ - 0 26 0x1 0x2>; /* PA26 periph A with multi drive */ + <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* PA25 periph A with multi drive */ + AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* PA26 periph A with multi drive */ }; pinctrl_twi_gpio: twi_gpio-0 { atmel,pins = - <0 25 0x0 0x2 /* PA25 GPIO with multi drive */ - 0 26 0x0 0x2>; /* PA26 GPIO with multi drive */ + <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */ + AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA26 GPIO with multi drive */ + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; + + tcb1 { + pinctrl_tcb1_tclk0: tcb1_tclk0-0 { + atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tclk1: tcb1_tclk1-0 { + atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tclk2: tcb1_tclk2-0 { + atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa0: tcb1_tioa0-0 { + atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa1: tcb1_tioa1-0 { + atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa2: tcb1_tioa2-0 { + atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob0: tcb1_tiob0-0 { + atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob1: tcb1_tiob1-0 { + atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob2: tcb1_tiob2-0 { + atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */ }; }; pioA: gpio@fffff400 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -404,7 +500,7 @@ pioB: gpio@fffff600 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff600 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -414,7 +510,7 @@ pioC: gpio@fffff800 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff800 0x200>; - interrupts = <4 4 1>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -424,7 +520,7 @@ pioD: gpio@fffffa00 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffffa00 0x200>; - interrupts = <5 4 1>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -435,7 +531,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffff200 0x200>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; status = "disabled"; @@ -444,7 +540,7 @@ usart0: serial@fffc0000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffc0000 0x200>; - interrupts = <6 4 5>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -455,7 +551,7 @@ usart1: serial@fffc4000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffc4000 0x200>; - interrupts = <7 4 5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -466,7 +562,7 @@ usart2: serial@fffc8000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffc8000 0x200>; - interrupts = <8 4 5>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -477,7 +573,7 @@ usart3: serial@fffcc000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffcc000 0x200>; - interrupts = <23 4 5>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -488,7 +584,18 @@ usb1: gadget@fffb0000 { compatible = "atmel,at91rm9200-udc"; reg = <0xfffb0000 0x4000>; - interrupts = <11 4 2>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; + status = "disabled"; + }; + + spi0: spi@fffe0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffe0000 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; status = "disabled"; }; }; @@ -503,9 +610,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; nand-ecc-mode = "soft"; - gpios = <&pioC 2 0 + gpios = <&pioC 2 GPIO_ACTIVE_HIGH 0 - &pioB 1 0 + &pioB 1 GPIO_ACTIVE_HIGH >; status = "disabled"; }; @@ -513,15 +620,15 @@ usb0: ohci@00300000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00300000 0x100000>; - interrupts = <23 4 2>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; }; i2c@0 { compatible = "i2c-gpio"; - gpios = <&pioA 25 0 /* sda */ - &pioA 26 0 /* scl */ + gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */ + &pioA 26 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index e586d85f8e23..d2d72c3b44c4 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2 only */ /dts-v1/; -/include/ "at91rm9200.dtsi" +#include "at91rm9200.dtsi" / { model = "Atmel AT91RM9200 evaluation kit"; @@ -50,9 +50,19 @@ }; usb1: gadget@fffb0000 { - atmel,vbus-gpio = <&pioD 4 0>; + atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; status = "okay"; }; + + spi0: spi@fffe0000 { + status = "okay"; + cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <15000000>; + reg = <0>; + }; + }; }; usb0: ohci@00300000 { @@ -66,19 +76,19 @@ ds2 { label = "green"; - gpios = <&pioB 0 0x1>; + gpios = <&pioB 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "mmc0"; }; ds4 { label = "yellow"; - gpios = <&pioB 1 0x1>; + gpios = <&pioB 1 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; ds6 { label = "red"; - gpios = <&pioB 2 0x1>; + gpios = <&pioB 2 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 70b5ccbac234..c7ccbcbffb3e 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -8,7 +8,10 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Atmel AT91SAM9260 family SoC"; @@ -32,8 +35,12 @@ ssc0 = &ssc0; }; cpus { - cpu@0 { - compatible = "arm,arm926ejs"; + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; }; }; @@ -84,19 +91,23 @@ pit: timer@fffffd30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; tcb0: timer@fffa0000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfffa0000 0x100>; - interrupts = <17 4 0 18 4 0 19 4 0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 + 18 IRQ_TYPE_LEVEL_HIGH 0 + 19 IRQ_TYPE_LEVEL_HIGH 0>; }; tcb1: timer@fffdc000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfffdc000 0x100>; - interrupts = <26 4 0 27 4 0 28 4 0>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 + 27 IRQ_TYPE_LEVEL_HIGH 0 + 28 IRQ_TYPE_LEVEL_HIGH 0>; }; pinctrl@fffff400 { @@ -116,234 +127,318 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <1 14 0x1 0x0 /* PB14 periph A */ - 1 15 0x1 0x1>; /* PB15 periph with pullup */ + <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */ }; }; usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - <1 4 0x1 0x0 /* PB4 periph A */ - 1 5 0x1 0x0>; /* PB5 periph A */ + <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ }; pinctrl_usart0_rts: usart0_rts-0 { atmel,pins = - <1 26 0x1 0x0>; /* PB26 periph A */ + <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */ }; pinctrl_usart0_cts: usart0_cts-0 { atmel,pins = - <1 27 0x1 0x0>; /* PB27 periph A */ + <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */ }; pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { atmel,pins = - <1 24 0x1 0x0 /* PB24 periph A */ - 1 22 0x1 0x0>; /* PB22 periph A */ + <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A */ + AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */ }; pinctrl_usart0_dcd: usart0_dcd-0 { atmel,pins = - <1 23 0x1 0x0>; /* PB23 periph A */ + <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */ }; pinctrl_usart0_ri: usart0_ri-0 { atmel,pins = - <1 25 0x1 0x0>; /* PB25 periph A */ + <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */ }; }; usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - <1 6 0x1 0x1 /* PB6 periph A with pullup */ - 1 7 0x1 0x0>; /* PB7 periph A */ + <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */ }; pinctrl_usart1_rts: usart1_rts-0 { atmel,pins = - <1 28 0x1 0x0>; /* PB28 periph A */ + <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */ }; pinctrl_usart1_cts: usart1_cts-0 { atmel,pins = - <1 29 0x1 0x0>; /* PB29 periph A */ + <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */ }; }; usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - <1 8 0x1 0x1 /* PB8 periph A with pullup */ - 1 9 0x1 0x0>; /* PB9 periph A */ + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB9 periph A */ }; pinctrl_usart2_rts: usart2_rts-0 { atmel,pins = - <0 4 0x1 0x0>; /* PA4 periph A */ + <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */ }; pinctrl_usart2_cts: usart2_cts-0 { atmel,pins = - <0 5 0x1 0x0>; /* PA5 periph A */ + <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ }; }; usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - <1 10 0x1 0x1 /* PB10 periph A with pullup */ - 1 11 0x1 0x0>; /* PB11 periph A */ + <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB10 periph A with pullup */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ }; pinctrl_usart3_rts: usart3_rts-0 { atmel,pins = - <2 8 0x2 0x0>; /* PC8 periph B */ + <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */ }; pinctrl_usart3_cts: usart3_cts-0 { atmel,pins = - <2 10 0x2 0x0>; /* PC10 periph B */ + <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */ }; }; uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - <0 31 0x2 0x1 /* PA31 periph B with pullup */ - 0 30 0x2 0x0>; /* PA30 periph B */ + <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA31 periph B with pullup */ + AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ }; }; uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - <1 12 0x1 0x1 /* PB12 periph A with pullup */ - 1 13 0x1 0x0>; /* PB13 periph A */ + <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB12 periph A with pullup */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */ }; }; nand { pinctrl_nand: nand-0 { atmel,pins = - <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */ - 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */ + <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC13 gpio RDY pin pull_up */ + AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ }; }; macb { pinctrl_macb_rmii: macb_rmii-0 { atmel,pins = - <0 12 0x1 0x0 /* PA12 periph A */ - 0 13 0x1 0x0 /* PA13 periph A */ - 0 14 0x1 0x0 /* PA14 periph A */ - 0 15 0x1 0x0 /* PA15 periph A */ - 0 16 0x1 0x0 /* PA16 periph A */ - 0 17 0x1 0x0 /* PA17 periph A */ - 0 18 0x1 0x0 /* PA18 periph A */ - 0 19 0x1 0x0 /* PA19 periph A */ - 0 20 0x1 0x0 /* PA20 periph A */ - 0 21 0x1 0x0>; /* PA21 periph A */ + <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ + AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ + AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA19 periph A */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA20 periph A */ + AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ }; pinctrl_macb_rmii_mii: macb_rmii_mii-0 { atmel,pins = - <0 22 0x2 0x0 /* PA22 periph B */ - 0 23 0x2 0x0 /* PA23 periph B */ - 0 24 0x2 0x0 /* PA24 periph B */ - 0 25 0x2 0x0 /* PA25 periph B */ - 0 26 0x2 0x0 /* PA26 periph B */ - 0 27 0x2 0x0 /* PA27 periph B */ - 0 28 0x2 0x0 /* PA28 periph B */ - 0 29 0x2 0x0>; /* PA29 periph B */ + <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */ + AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA23 periph B */ + AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ + AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ + AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ + AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ + AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ + AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ }; pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 { atmel,pins = - <0 10 0x2 0x0 /* PA10 periph B */ - 0 11 0x2 0x0 /* PA11 periph B */ - 0 24 0x2 0x0 /* PA24 periph B */ - 0 25 0x2 0x0 /* PA25 periph B */ - 0 26 0x2 0x0 /* PA26 periph B */ - 0 27 0x2 0x0 /* PA27 periph B */ - 0 28 0x2 0x0 /* PA28 periph B */ - 0 29 0x2 0x0>; /* PA29 periph B */ + <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */ + AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */ + AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */ + AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ + AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ + AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ + AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ + AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ }; }; mmc0 { pinctrl_mmc0_clk: mmc0_clk-0 { atmel,pins = - <0 8 0x1 0x0>; /* PA8 periph A */ + <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ }; pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { atmel,pins = - <0 7 0x1 0x1 /* PA7 periph A with pullup */ - 0 6 0x1 0x1>; /* PA6 periph A with pullup */ + <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA6 periph A with pullup */ }; pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { atmel,pins = - <0 9 0x1 0x1 /* PA9 periph A with pullup */ - 0 10 0x1 0x1 /* PA10 periph A with pullup */ - 0 11 0x1 0x1>; /* PA11 periph A with pullup */ + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */ }; pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { atmel,pins = - <0 1 0x2 0x1 /* PA1 periph B with pullup */ - 0 0 0x2 0x1>; /* PA0 periph B with pullup */ + <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA1 periph B with pullup */ + AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */ }; pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { atmel,pins = - <0 5 0x2 0x1 /* PA5 periph B with pullup */ - 0 4 0x2 0x1 /* PA4 periph B with pullup */ - 0 3 0x2 0x1>; /* PA3 periph B with pullup */ + <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */ + AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA4 periph B with pullup */ + AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA3 periph B with pullup */ }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx-0 { atmel,pins = - <1 16 0x1 0x0 /* PB16 periph A */ - 1 17 0x1 0x0 /* PB17 periph A */ - 1 18 0x1 0x0>; /* PB18 periph A */ + <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A */ + AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ }; pinctrl_ssc0_rx: ssc0_rx-0 { atmel,pins = - <1 19 0x1 0x0 /* PB19 periph A */ - 1 20 0x1 0x0 /* PB20 periph A */ - 1 21 0x1 0x0>; /* PB21 periph A */ + <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */ + AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB20 periph A */ + AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */ }; }; spi0 { pinctrl_spi0: spi0-0 { atmel,pins = - <0 0 0x1 0x0 /* PA0 periph A SPI0_MISO pin */ - 0 1 0x1 0x0 /* PA1 periph A SPI0_MOSI pin */ - 0 2 0x1 0x0>; /* PA2 periph A SPI0_SPCK pin */ + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */ }; }; spi1 { pinctrl_spi1: spi1-0 { atmel,pins = - <1 0 0x1 0x0 /* PB0 periph A SPI1_MISO pin */ - 1 1 0x1 0x0 /* PB1 periph A SPI1_MOSI pin */ - 1 2 0x1 0x0>; /* PB2 periph A SPI1_SPCK pin */ + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI1_MOSI pin */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI1_SPCK pin */ + }; + }; + + i2c_gpio0 { + pinctrl_i2c_gpio0: i2c_gpio0-0 { + atmel,pins = + <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE + AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + tcb1 { + pinctrl_tcb1_tclk0: tcb1_tclk0-0 { + atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tclk1: tcb1_tclk1-0 { + atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tclk2: tcb1_tclk2-0 { + atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa0: tcb1_tioa0-0 { + atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa1: tcb1_tioa1-0 { + atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa2: tcb1_tioa2-0 { + atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob0: tcb1_tiob0-0 { + atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob1: tcb1_tiob1-0 { + atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob2: tcb1_tiob2-0 { + atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; }; pioA: gpio@fffff400 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -353,7 +448,7 @@ pioB: gpio@fffff600 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff600 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -363,7 +458,7 @@ pioC: gpio@fffff800 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff800 0x200>; - interrupts = <4 4 1>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -374,7 +469,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; status = "disabled"; @@ -383,7 +478,7 @@ usart0: serial@fffb0000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb0000 0x200>; - interrupts = <6 4 5>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -394,7 +489,7 @@ usart1: serial@fffb4000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb4000 0x200>; - interrupts = <7 4 5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -405,7 +500,7 @@ usart2: serial@fffb8000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb8000 0x200>; - interrupts = <8 4 5>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -416,7 +511,7 @@ usart3: serial@fffd0000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffd0000 0x200>; - interrupts = <23 4 5>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -427,7 +522,7 @@ uart0: serial@fffd4000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffd4000 0x200>; - interrupts = <24 4 5>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -438,7 +533,7 @@ uart1: serial@fffd8000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffd8000 0x200>; - interrupts = <25 4 5>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -449,7 +544,7 @@ macb0: ethernet@fffc4000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xfffc4000 0x100>; - interrupts = <21 4 3>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; status = "disabled"; @@ -458,14 +553,14 @@ usb1: gadget@fffa4000 { compatible = "atmel,at91rm9200-udc"; reg = <0xfffa4000 0x4000>; - interrupts = <10 4 2>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; i2c0: i2c@fffac000 { compatible = "atmel,at91sam9260-i2c"; reg = <0xfffac000 0x100>; - interrupts = <11 4 6>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -474,7 +569,7 @@ mmc0: mmc@fffa8000 { compatible = "atmel,hsmci"; reg = <0xfffa8000 0x600>; - interrupts = <9 4 0>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -483,7 +578,7 @@ ssc0: ssc@fffbc000 { compatible = "atmel,at91rm9200-ssc"; reg = <0xfffbc000 0x4000>; - interrupts = <14 4 5>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; @@ -494,7 +589,7 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xfffc8000 0x200>; - interrupts = <12 4 3>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; status = "disabled"; @@ -505,7 +600,7 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xfffcc000 0x200>; - interrupts = <13 4 3>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; status = "disabled"; @@ -514,7 +609,7 @@ adc0: adc@fffe0000 { compatible = "atmel,at91sam9260-adc"; reg = <0xfffe0000 0x100>; - interrupts = <5 4 0>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; atmel,adc-use-external-triggers; atmel,adc-channels-used = <0xf>; atmel,adc-vref = <3300>; @@ -567,8 +662,8 @@ atmel,nand-cmd-offset = <22>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioC 13 0 - &pioC 14 0 + gpios = <&pioC 13 GPIO_ACTIVE_HIGH + &pioC 14 GPIO_ACTIVE_HIGH 0 >; status = "disabled"; @@ -577,21 +672,23 @@ usb0: ohci@00500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; - interrupts = <20 4 2>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; }; i2c@0 { compatible = "i2c-gpio"; - gpios = <&pioA 23 0 /* sda */ - &pioA 24 0 /* scl */ + gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */ + &pioA 24 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; i2c-gpio,delay-us = <2>; /* ~100 kHz */ #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio0>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 94b58ab2cc08..d5bd65f74602 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -6,7 +6,10 @@ * Licensed under GPLv2 only. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Atmel AT91SAM9263 family SoC"; @@ -29,8 +32,12 @@ ssc1 = &ssc1; }; cpus { - cpu@0 { - compatible = "arm,arm926ejs"; + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; }; }; @@ -72,13 +79,13 @@ pit: timer@fffffd30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; tcb0: timer@fff7c000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfff7c000 0x100>; - interrupts = <19 4 0>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; }; rstc@fffffd00 { @@ -110,221 +117,259 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <2 30 0x1 0x0 /* PC30 periph A */ - 2 31 0x1 0x1>; /* PC31 periph with pullup */ + <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC30 periph A */ + AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC31 periph with pullup */ }; }; usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - <0 26 0x1 0x1 /* PA26 periph A with pullup */ - 0 27 0x1 0x0>; /* PA27 periph A */ + <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA26 periph A with pullup */ + AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */ }; pinctrl_usart0_rts: usart0_rts-0 { atmel,pins = - <0 28 0x1 0x0>; /* PA28 periph A */ + <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */ }; pinctrl_usart0_cts: usart0_cts-0 { atmel,pins = - <0 29 0x1 0x0>; /* PA29 periph A */ + <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */ }; }; usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - <3 0 0x1 0x1 /* PD0 periph A with pullup */ - 3 1 0x1 0x0>; /* PD1 periph A */ + <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */ + AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD1 periph A */ }; pinctrl_usart1_rts: usart1_rts-0 { atmel,pins = - <3 7 0x2 0x0>; /* PD7 periph B */ + <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD7 periph B */ }; pinctrl_usart1_cts: usart1_cts-0 { atmel,pins = - <3 8 0x2 0x0>; /* PD8 periph B */ + <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD8 periph B */ }; }; usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - <3 2 0x1 0x1 /* PD2 periph A with pullup */ - 3 3 0x1 0x0>; /* PD3 periph A */ + <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */ + AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD3 periph A */ }; pinctrl_usart2_rts: usart2_rts-0 { atmel,pins = - <3 5 0x2 0x0>; /* PD5 periph B */ + <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD5 periph B */ }; pinctrl_usart2_cts: usart2_cts-0 { atmel,pins = - <4 6 0x2 0x0>; /* PD6 periph B */ + <AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD6 periph B */ }; }; nand { pinctrl_nand: nand-0 { atmel,pins = - <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/ - 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */ + <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PA22 gpio RDY pin pull_up*/ + AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD15 gpio enable pin pull_up */ }; }; macb { pinctrl_macb_rmii: macb_rmii-0 { atmel,pins = - <2 25 0x2 0x0 /* PC25 periph B */ - 4 21 0x1 0x0 /* PE21 periph A */ - 4 23 0x1 0x0 /* PE23 periph A */ - 4 24 0x1 0x0 /* PE24 periph A */ - 4 25 0x1 0x0 /* PE25 periph A */ - 4 26 0x1 0x0 /* PE26 periph A */ - 4 27 0x1 0x0 /* PE27 periph A */ - 4 28 0x1 0x0 /* PE28 periph A */ - 4 29 0x1 0x0 /* PE29 periph A */ - 4 30 0x1 0x0>; /* PE30 periph A */ + <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */ + AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */ + AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */ + AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */ + AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */ + AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */ + AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */ + AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */ + AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */ + AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ }; pinctrl_macb_rmii_mii: macb_rmii_mii-0 { atmel,pins = - <2 20 0x2 0x0 /* PC20 periph B */ - 2 21 0x2 0x0 /* PC21 periph B */ - 2 22 0x2 0x0 /* PC22 periph B */ - 2 23 0x2 0x0 /* PC23 periph B */ - 2 24 0x2 0x0 /* PC24 periph B */ - 2 25 0x2 0x0 /* PC25 periph B */ - 2 27 0x2 0x0 /* PC27 periph B */ - 4 22 0x2 0x0>; /* PE22 periph B */ + <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */ + AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */ + AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC22 periph B */ + AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC23 periph B */ + AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC24 periph B */ + AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */ + AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */ + AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */ }; }; mmc0 { pinctrl_mmc0_clk: mmc0_clk-0 { atmel,pins = - <0 12 0x1 0x0>; /* PA12 periph A */ + <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */ }; pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { atmel,pins = - <0 1 0x1 0x1 /* PA1 periph A with pullup */ - 0 0 0x1 0x1>; /* PA0 periph A with pullup */ + <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ + AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */ }; pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { atmel,pins = - <0 3 0x1 0x1 /* PA3 periph A with pullup */ - 0 4 0x1 0x1 /* PA4 periph A with pullup */ - 0 5 0x1 0x1>; /* PA5 periph A with pullup */ + <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */ }; pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { atmel,pins = - <0 16 0x1 0x1 /* PA16 periph A with pullup */ - 0 17 0x1 0x1>; /* PA17 periph A with pullup */ + <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ + AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA17 periph A with pullup */ }; pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { atmel,pins = - <0 18 0x1 0x1 /* PA18 periph A with pullup */ - 0 19 0x1 0x1 /* PA19 periph A with pullup */ - 0 20 0x1 0x1>; /* PA20 periph A with pullup */ + <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ }; }; mmc1 { pinctrl_mmc1_clk: mmc1_clk-0 { atmel,pins = - <0 6 0x1 0x0>; /* PA6 periph A */ + <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */ }; pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 { atmel,pins = - <0 7 0x1 0x1 /* PA7 periph A with pullup */ - 0 8 0x1 0x1>; /* PA8 periph A with pullup */ + <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA8 periph A with pullup */ }; pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { atmel,pins = - <0 9 0x1 0x1 /* PA9 periph A with pullup */ - 0 10 0x1 0x1 /* PA10 periph A with pullup */ - 0 11 0x1 0x1>; /* PA11 periph A with pullup */ + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */ }; pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 { atmel,pins = - <0 21 0x1 0x1 /* PA21 periph A with pullup */ - 0 22 0x1 0x1>; /* PA22 periph A with pullup */ + <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA21 periph A with pullup */ + AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA22 periph A with pullup */ }; pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 { atmel,pins = - <0 23 0x1 0x1 /* PA23 periph A with pullup */ - 0 24 0x1 0x1 /* PA24 periph A with pullup */ - 0 25 0x1 0x1>; /* PA25 periph A with pullup */ + <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA23 periph A with pullup */ + AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */ + AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA25 periph A with pullup */ }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx-0 { atmel,pins = - <1 0 0x2 0x0 /* PB0 periph B */ - 1 1 0x2 0x0 /* PB1 periph B */ - 1 2 0x2 0x0>; /* PB2 periph B */ + <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */ + AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB1 periph B */ + AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */ }; pinctrl_ssc0_rx: ssc0_rx-0 { atmel,pins = - <1 3 0x2 0x0 /* PB3 periph B */ - 1 4 0x2 0x0 /* PB4 periph B */ - 1 5 0x2 0x0>; /* PB5 periph B */ + <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B */ + AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B */ + AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B */ }; }; ssc1 { pinctrl_ssc1_tx: ssc1_tx-0 { atmel,pins = - <1 6 0x1 0x0 /* PB6 periph A */ - 1 7 0x1 0x0 /* PB7 periph A */ - 1 8 0x1 0x0>; /* PB8 periph A */ + <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ + AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ }; pinctrl_ssc1_rx: ssc1_rx-0 { atmel,pins = - <1 9 0x1 0x0 /* PB9 periph A */ - 1 10 0x1 0x0 /* PB10 periph A */ - 1 11 0x1 0x0>; /* PB11 periph A */ + <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ }; }; spi0 { pinctrl_spi0: spi0-0 { atmel,pins = - <0 0 0x2 0x0 /* PA0 periph B SPI0_MISO pin */ - 0 1 0x2 0x0 /* PA1 periph B SPI0_MOSI pin */ - 0 2 0x2 0x0>; /* PA2 periph B SPI0_SPCK pin */ + <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */ + AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA1 periph B SPI0_MOSI pin */ + AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA2 periph B SPI0_SPCK pin */ }; }; spi1 { pinctrl_spi1: spi1-0 { atmel,pins = - <1 12 0x1 0x0 /* PB12 periph A SPI1_MISO pin */ - 1 13 0x1 0x0 /* PB13 periph A SPI1_MOSI pin */ - 1 14 0x1 0x0>; /* PB14 periph A SPI1_SPCK pin */ + <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A SPI1_MISO pin */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A SPI1_MOSI pin */ + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */ + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; }; pioA: gpio@fffff200 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff200 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -334,7 +379,7 @@ pioB: gpio@fffff400 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -344,7 +389,7 @@ pioC: gpio@fffff600 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff600 0x200>; - interrupts = <4 4 1>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -354,7 +399,7 @@ pioD: gpio@fffff800 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff800 0x200>; - interrupts = <4 4 1>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -364,7 +409,7 @@ pioE: gpio@fffffa00 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffffa00 0x200>; - interrupts = <4 4 1>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -375,7 +420,7 @@ dbgu: serial@ffffee00 { compatible = "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; status = "disabled"; @@ -384,7 +429,7 @@ usart0: serial@fff8c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff8c000 0x200>; - interrupts = <7 4 5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -395,7 +440,7 @@ usart1: serial@fff90000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff90000 0x200>; - interrupts = <8 4 5>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -406,7 +451,7 @@ usart2: serial@fff94000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff94000 0x200>; - interrupts = <9 4 5>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -417,7 +462,7 @@ ssc0: ssc@fff98000 { compatible = "atmel,at91rm9200-ssc"; reg = <0xfff98000 0x4000>; - interrupts = <16 4 5>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; @@ -426,7 +471,7 @@ ssc1: ssc@fff9c000 { compatible = "atmel,at91rm9200-ssc"; reg = <0xfff9c000 0x4000>; - interrupts = <17 4 5>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; status = "disabled"; @@ -435,7 +480,7 @@ macb0: ethernet@fffbc000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xfffbc000 0x100>; - interrupts = <21 4 3>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; status = "disabled"; @@ -444,14 +489,14 @@ usb1: gadget@fff78000 { compatible = "atmel,at91rm9200-udc"; reg = <0xfff78000 0x4000>; - interrupts = <24 4 2>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; i2c0: i2c@fff88000 { compatible = "atmel,at91sam9263-i2c"; reg = <0xfff88000 0x100>; - interrupts = <13 4 6>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -460,7 +505,7 @@ mmc0: mmc@fff80000 { compatible = "atmel,hsmci"; reg = <0xfff80000 0x600>; - interrupts = <10 4 0>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -469,7 +514,7 @@ mmc1: mmc@fff84000 { compatible = "atmel,hsmci"; reg = <0xfff84000 0x600>; - interrupts = <11 4 0>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -486,7 +531,7 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xfffa4000 0x200>; - interrupts = <14 4 3>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; status = "disabled"; @@ -497,7 +542,7 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xfffa8000 0x200>; - interrupts = <15 4 3>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; status = "disabled"; @@ -515,8 +560,8 @@ atmel,nand-cmd-offset = <22>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioA 22 0 - &pioD 15 0 + gpios = <&pioA 22 GPIO_ACTIVE_HIGH + &pioD 15 GPIO_ACTIVE_HIGH 0 >; status = "disabled"; @@ -525,15 +570,15 @@ usb0: ohci@00a00000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00a00000 0x100000>; - interrupts = <29 4 2>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; }; i2c@0 { compatible = "i2c-gpio"; - gpios = <&pioB 4 0 /* sda */ - &pioB 5 0 /* scl */ + gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ + &pioB 5 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 3b82d91e7fcc..70f835b55c0b 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2 only */ /dts-v1/; -/include/ "at91sam9263.dtsi" +#include "at91sam9263.dtsi" / { model = "Atmel at91sam9263ek"; @@ -51,7 +51,7 @@ }; usb1: gadget@fff78000 { - atmel,vbus-gpio = <&pioA 25 0>; + atmel,vbus-gpio = <&pioA 25 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -65,8 +65,8 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioE 18 0>; - wp-gpios = <&pioE 19 0>; + cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>; + wp-gpios = <&pioE 19 GPIO_ACTIVE_HIGH>; }; }; @@ -74,8 +74,8 @@ mmc0 { pinctrl_board_mmc0: mmc0-board { atmel,pins = - <5 18 0x0 0x5 /* PE18 gpio CD pin pull up and deglitch */ - 5 19 0x0 0x1>; /* PE19 gpio WP pin pull up */ + <AT91_PIOE 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* PE18 gpio CD pin pull up and deglitch */ + AT91_PIOE 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PE19 gpio WP pin pull up */ }; }; }; @@ -89,6 +89,10 @@ reg = <0>; }; }; + + watchdog@fffffd40 { + status = "okay"; + }; }; nand0: nand@40000000 { @@ -141,8 +145,8 @@ usb0: ohci@00a00000 { num-ports = <2>; status = "okay"; - atmel,vbus-gpio = <&pioA 24 0 - &pioA 21 0 + atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH + &pioA 21 GPIO_ACTIVE_HIGH >; }; }; @@ -152,13 +156,13 @@ d3 { label = "d3"; - gpios = <&pioB 7 0>; + gpios = <&pioB 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; d2 { label = "d2"; - gpios = <&pioC 29 1>; + gpios = <&pioC 29 GPIO_ACTIVE_LOW>; linux,default-trigger = "nand-disk"; }; }; @@ -168,14 +172,14 @@ left_click { label = "left_click"; - gpios = <&pioC 5 1>; + gpios = <&pioC 5 GPIO_ACTIVE_LOW>; linux,code = <272>; gpio-key,wakeup; }; right_click { label = "right_click"; - gpios = <&pioC 4 1>; + gpios = <&pioC 4 GPIO_ACTIVE_LOW>; linux,code = <273>; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi index 28467fd6bf96..cfd7044616d7 100644 --- a/arch/arm/boot/dts/at91sam9g15.dtsi +++ b/arch/arm/boot/dts/at91sam9g15.dtsi @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ -/include/ "at91sam9x5.dtsi" +#include "at91sam9x5.dtsi" / { model = "Atmel AT91SAM9G15 SoC"; diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts index 5427b2dba87e..26b0444b0f96 100644 --- a/arch/arm/boot/dts/at91sam9g15ek.dts +++ b/arch/arm/boot/dts/at91sam9g15ek.dts @@ -7,8 +7,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9g15.dtsi" -/include/ "at91sam9x5ek.dtsi" +#include "at91sam9g15.dtsi" +#include "at91sam9x5ek.dtsi" / { model = "Atmel AT91SAM9G15-EK"; diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index 75ce6e760016..b8e79466014f 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ -/include/ "at91sam9260.dtsi" +#include "at91sam9260.dtsi" / { model = "Atmel AT91SAM9G20 family SoC"; diff --git a/arch/arm/boot/dts/at91sam9g20ek.dts b/arch/arm/boot/dts/at91sam9g20ek.dts index e5324bf9d529..bbfd753112c9 100644 --- a/arch/arm/boot/dts/at91sam9g20ek.dts +++ b/arch/arm/boot/dts/at91sam9g20ek.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ /dts-v1/; -/include/ "at91sam9g20ek_common.dtsi" +#include "at91sam9g20ek_common.dtsi" / { model = "Atmel at91sam9g20ek"; @@ -17,13 +17,13 @@ ds1 { label = "ds1"; - gpios = <&pioA 9 0>; + gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds5 { label = "ds5"; - gpios = <&pioA 6 1>; + gpios = <&pioA 6 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts index 66467b113126..bdb799bad179 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts +++ b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ /dts-v1/; -/include/ "at91sam9g20ek_common.dtsi" +#include "at91sam9g20ek_common.dtsi" / { model = "Atmel at91sam9g20ek 2 mmc"; @@ -23,7 +23,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioC 2 0>; + cd-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>; }; }; @@ -31,7 +31,7 @@ mmc0_slot0 { pinctrl_board_mmc0_slot0: mmc0_slot0-board { atmel,pins = - <2 2 0x0 0x5>; /* PC2 gpio CD pin pull up and deglitch */ + <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PC2 gpio CD pin pull up and deglitch */ }; }; }; @@ -43,13 +43,13 @@ ds1 { label = "ds1"; - gpios = <&pioB 9 0>; + gpios = <&pioB 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds5 { label = "ds5"; - gpios = <&pioB 8 1>; + gpios = <&pioB 8 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index 6a92c5baef8c..137354689ad0 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -5,7 +5,7 @@ * * Licensed under GPLv2. */ -/include/ "at91sam9g20.dtsi" +#include "at91sam9g20.dtsi" / { @@ -34,10 +34,17 @@ board { pinctrl_pck0_as_mck: pck0_as_mck { atmel,pins = - <2 1 0x2 0x0>; /* PC1 periph B */ + <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC1 periph B */ }; }; + + mmc0_slot1 { + pinctrl_board_mmc0_slot1: mmc0_slot1-board { + atmel,pins = + <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PC9 gpio CD pin pull up and deglitch */ + }; + }; }; dbgu: serial@fffff200 { @@ -65,7 +72,7 @@ }; usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 0>; + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -79,16 +86,7 @@ slot@1 { reg = <1>; bus-width = <4>; - cd-gpios = <&pioC 9 0>; - }; - }; - - pinctrl@fffff400 { - mmc0_slot1 { - pinctrl_board_mmc0_slot1: mmc0_slot1-board { - atmel,pins = - <2 9 0x0 0x5>; /* PC9 gpio CD pin pull up and deglitch */ - }; + cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; }; }; @@ -106,6 +104,10 @@ reg = <1>; }; }; + + watchdog@fffffd40 { + status = "okay"; + }; }; nand0: nand@40000000 { @@ -180,14 +182,14 @@ btn3 { label = "Button 3"; - gpios = <&pioA 30 1>; + gpios = <&pioA 30 GPIO_ACTIVE_LOW>; linux,code = <0x103>; gpio-key,wakeup; }; btn4 { label = "Button 4"; - gpios = <&pioA 31 1>; + gpios = <&pioA 31 GPIO_ACTIVE_LOW>; linux,code = <0x104>; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi index 5fd32df03f25..b4ec6fe53fc7 100644 --- a/arch/arm/boot/dts/at91sam9g25.dtsi +++ b/arch/arm/boot/dts/at91sam9g25.dtsi @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ -/include/ "at91sam9x5.dtsi" +#include "at91sam9x5.dtsi" / { model = "Atmel AT91SAM9G25 SoC"; diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts index a1c511fecdc1..1e4c49c584d3 100644 --- a/arch/arm/boot/dts/at91sam9g25ek.dts +++ b/arch/arm/boot/dts/at91sam9g25ek.dts @@ -7,8 +7,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9g25.dtsi" -/include/ "at91sam9x5ek.dtsi" +#include "at91sam9g25.dtsi" +#include "at91sam9x5ek.dtsi" / { model = "Atmel AT91SAM9G25-EK"; diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi index d6fa8af50724..bebf9f55614b 100644 --- a/arch/arm/boot/dts/at91sam9g35.dtsi +++ b/arch/arm/boot/dts/at91sam9g35.dtsi @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ -/include/ "at91sam9x5.dtsi" +#include "at91sam9x5.dtsi" / { model = "Atmel AT91SAM9G35 SoC"; diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts index 6f58ab8d21f5..641a9bf89ed1 100644 --- a/arch/arm/boot/dts/at91sam9g35ek.dts +++ b/arch/arm/boot/dts/at91sam9g35ek.dts @@ -7,8 +7,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9g35.dtsi" -/include/ "at91sam9x5ek.dtsi" +#include "at91sam9g35.dtsi" +#include "at91sam9x5ek.dtsi" / { model = "Atmel AT91SAM9G35-EK"; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index bf18a735c37d..c3e514837074 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -9,7 +9,11 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/dma/at91.h> +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Atmel AT91SAM9G45 family SoC"; @@ -35,8 +39,12 @@ ssc1 = &ssc1; }; cpus { - cpu@0 { - compatible = "arm,arm926ejs"; + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; }; }; @@ -83,7 +91,7 @@ pit: timer@fffffd30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; @@ -95,19 +103,19 @@ tcb0: timer@fff7c000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfff7c000 0x100>; - interrupts = <18 4 0>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; }; tcb1: timer@fffd4000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfffd4000 0x100>; - interrupts = <18 4 0>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; }; dma: dma-controller@ffffec00 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffec00 0x200>; - interrupts = <21 4 0>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; }; @@ -130,221 +138,297 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <1 12 0x1 0x0 /* PB12 periph A */ - 1 13 0x1 0x0>; /* PB13 periph A */ + <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */ }; }; usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - <1 19 0x1 0x1 /* PB19 periph A with pullup */ - 1 18 0x1 0x0>; /* PB18 periph A */ + <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */ + AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ }; pinctrl_usart0_rts: usart0_rts-0 { atmel,pins = - <1 17 0x2 0x0>; /* PB17 periph B */ + <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */ }; pinctrl_usart0_cts: usart0_cts-0 { atmel,pins = - <1 15 0x2 0x0>; /* PB15 periph B */ + <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */ }; }; uart1 { pinctrl_usart1: usart1-0 { atmel,pins = - <1 4 0x1 0x1 /* PB4 periph A with pullup */ - 1 5 0x1 0x0>; /* PB5 periph A */ + <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ }; pinctrl_usart1_rts: usart1_rts-0 { atmel,pins = - <3 16 0x1 0x0>; /* PD16 periph A */ + <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */ }; pinctrl_usart1_cts: usart1_cts-0 { atmel,pins = - <3 17 0x1 0x0>; /* PD17 periph A */ + <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */ }; }; usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - <1 6 0x1 0x1 /* PB6 periph A with pullup */ - 1 7 0x1 0x0>; /* PB7 periph A */ + <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */ }; pinctrl_usart2_rts: usart2_rts-0 { atmel,pins = - <2 9 0x2 0x0>; /* PC9 periph B */ + <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */ }; pinctrl_usart2_cts: usart2_cts-0 { atmel,pins = - <2 11 0x2 0x0>; /* PC11 periph B */ + <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */ }; }; usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - <1 8 0x1 0x1 /* PB9 periph A with pullup */ - 1 9 0x1 0x0>; /* PB8 periph A */ + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ }; pinctrl_usart3_rts: usart3_rts-0 { atmel,pins = - <0 23 0x2 0x0>; /* PA23 periph B */ + <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */ }; pinctrl_usart3_cts: usart3_cts-0 { atmel,pins = - <0 24 0x2 0x0>; /* PA24 periph B */ + <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */ }; }; nand { pinctrl_nand: nand-0 { atmel,pins = - <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/ - 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */ + <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/ + AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ }; }; macb { pinctrl_macb_rmii: macb_rmii-0 { atmel,pins = - <0 10 0x1 0x0 /* PA10 periph A */ - 0 11 0x1 0x0 /* PA11 periph A */ - 0 12 0x1 0x0 /* PA12 periph A */ - 0 13 0x1 0x0 /* PA13 periph A */ - 0 14 0x1 0x0 /* PA14 periph A */ - 0 15 0x1 0x0 /* PA15 periph A */ - 0 16 0x1 0x0 /* PA16 periph A */ - 0 17 0x1 0x0 /* PA17 periph A */ - 0 18 0x1 0x0 /* PA18 periph A */ - 0 19 0x1 0x0>; /* PA19 periph A */ + <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ + AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ + AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */ }; pinctrl_macb_rmii_mii: macb_rmii_mii-0 { atmel,pins = - <0 6 0x2 0x0 /* PA6 periph B */ - 0 7 0x2 0x0 /* PA7 periph B */ - 0 8 0x2 0x0 /* PA8 periph B */ - 0 9 0x2 0x0 /* PA9 periph B */ - 0 27 0x2 0x0 /* PA27 periph B */ - 0 28 0x2 0x0 /* PA28 periph B */ - 0 29 0x2 0x0 /* PA29 periph B */ - 0 30 0x2 0x0>; /* PA30 periph B */ + <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */ + AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */ + AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */ + AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */ + AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ + AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ + AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */ + AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ }; }; mmc0 { pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { atmel,pins = - <0 0 0x1 0x0 /* PA0 periph A */ - 0 1 0x1 0x1 /* PA1 periph A with pullup */ - 0 2 0x1 0x1>; /* PA2 periph A with pullup */ + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */ }; pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { atmel,pins = - <0 3 0x1 0x1 /* PA3 periph A with pullup */ - 0 4 0x1 0x1 /* PA4 periph A with pullup */ - 0 5 0x1 0x1>; /* PA5 periph A with pullup */ + <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */ }; pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { atmel,pins = - <0 6 0x1 0x1 /* PA6 periph A with pullup */ - 0 7 0x1 0x1 /* PA7 periph A with pullup */ - 0 8 0x1 0x1 /* PA8 periph A with pullup */ - 0 9 0x1 0x1>; /* PA9 periph A with pullup */ + <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */ }; }; mmc1 { pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { atmel,pins = - <0 31 0x1 0x0 /* PA31 periph A */ - 0 22 0x1 0x1 /* PA22 periph A with pullup */ - 0 23 0x1 0x1>; /* PA23 periph A with pullup */ + <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */ + AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */ + AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */ }; pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { atmel,pins = - <0 24 0x1 0x1 /* PA24 periph A with pullup */ - 0 25 0x1 0x1 /* PA25 periph A with pullup */ - 0 26 0x1 0x1>; /* PA26 periph A with pullup */ + <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */ + AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */ + AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */ }; pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { atmel,pins = - <0 27 0x1 0x1 /* PA27 periph A with pullup */ - 0 28 0x1 0x1 /* PA28 periph A with pullup */ - 0 29 0x1 0x1 /* PA29 periph A with pullup */ - 0 20 0x1 0x1>; /* PA30 periph A with pullup */ + <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */ + AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */ + AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */ }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx-0 { atmel,pins = - <3 0 0x1 0x0 /* PD0 periph A */ - 3 1 0x1 0x0 /* PD1 periph A */ - 3 2 0x1 0x0>; /* PD2 periph A */ + <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */ + AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */ + AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */ }; pinctrl_ssc0_rx: ssc0_rx-0 { atmel,pins = - <3 3 0x1 0x0 /* PD3 periph A */ - 3 4 0x1 0x0 /* PD4 periph A */ - 3 5 0x1 0x0>; /* PD5 periph A */ + <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */ + AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */ + AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */ }; }; ssc1 { pinctrl_ssc1_tx: ssc1_tx-0 { atmel,pins = - <3 10 0x1 0x0 /* PD10 periph A */ - 3 11 0x1 0x0 /* PD11 periph A */ - 3 12 0x1 0x0>; /* PD12 periph A */ + <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */ + AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */ + AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */ }; pinctrl_ssc1_rx: ssc1_rx-0 { atmel,pins = - <3 13 0x1 0x0 /* PD13 periph A */ - 3 14 0x1 0x0 /* PD14 periph A */ - 3 15 0x1 0x0>; /* PD15 periph A */ + <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */ + AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */ + AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */ }; }; spi0 { pinctrl_spi0: spi0-0 { atmel,pins = - <1 0 0x1 0x0 /* PB0 periph A SPI0_MISO pin */ - 1 1 0x1 0x0 /* PB1 periph A SPI0_MOSI pin */ - 1 2 0x1 0x0>; /* PB2 periph A SPI0_SPCK pin */ + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */ }; }; spi1 { pinctrl_spi1: spi1-0 { atmel,pins = - <1 14 0x1 0x0 /* PB14 periph A SPI1_MISO pin */ - 1 15 0x1 0x0 /* PB15 periph A SPI1_MOSI pin */ - 1 16 0x1 0x0>; /* PB16 periph A SPI1_SPCK pin */ + <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */ + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */ + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; + + tcb1 { + pinctrl_tcb1_tclk0: tcb1_tclk0-0 { + atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tclk1: tcb1_tclk1-0 { + atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tclk2: tcb1_tclk2-0 { + atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa0: tcb1_tioa0-0 { + atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa1: tcb1_tioa1-0 { + atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa2: tcb1_tioa2-0 { + atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob0: tcb1_tiob0-0 { + atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob1: tcb1_tiob1-0 { + atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob2: tcb1_tiob2-0 { + atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; }; pioA: gpio@fffff200 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff200 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -354,7 +438,7 @@ pioB: gpio@fffff400 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -364,7 +448,7 @@ pioC: gpio@fffff600 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff600 0x200>; - interrupts = <4 4 1>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -374,7 +458,7 @@ pioD: gpio@fffff800 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff800 0x200>; - interrupts = <5 4 1>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -384,7 +468,7 @@ pioE: gpio@fffffa00 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffffa00 0x200>; - interrupts = <5 4 1>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -395,7 +479,7 @@ dbgu: serial@ffffee00 { compatible = "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; status = "disabled"; @@ -404,7 +488,7 @@ usart0: serial@fff8c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff8c000 0x200>; - interrupts = <7 4 5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -415,7 +499,7 @@ usart1: serial@fff90000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff90000 0x200>; - interrupts = <8 4 5>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -426,7 +510,7 @@ usart2: serial@fff94000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff94000 0x200>; - interrupts = <9 4 5>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -437,7 +521,7 @@ usart3: serial@fff98000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff98000 0x200>; - interrupts = <10 4 5>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -448,7 +532,7 @@ macb0: ethernet@fffbc000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xfffbc000 0x100>; - interrupts = <25 4 3>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; status = "disabled"; @@ -457,7 +541,7 @@ i2c0: i2c@fff84000 { compatible = "atmel,at91sam9g10-i2c"; reg = <0xfff84000 0x100>; - interrupts = <12 4 6>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -466,7 +550,7 @@ i2c1: i2c@fff88000 { compatible = "atmel,at91sam9g10-i2c"; reg = <0xfff88000 0x100>; - interrupts = <13 4 6>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -475,7 +559,7 @@ ssc0: ssc@fff9c000 { compatible = "atmel,at91sam9g45-ssc"; reg = <0xfff9c000 0x4000>; - interrupts = <16 4 5>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; @@ -484,7 +568,7 @@ ssc1: ssc@fffa0000 { compatible = "atmel,at91sam9g45-ssc"; reg = <0xfffa0000 0x4000>; - interrupts = <17 4 5>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; status = "disabled"; @@ -493,7 +577,7 @@ adc0: adc@fffb0000 { compatible = "atmel,at91sam9260-adc"; reg = <0xfffb0000 0x100>; - interrupts = <20 4 0>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; atmel,adc-use-external-triggers; atmel,adc-channels-used = <0xff>; atmel,adc-vref = <3300>; @@ -533,8 +617,8 @@ mmc0: mmc@fff80000 { compatible = "atmel,hsmci"; reg = <0xfff80000 0x600>; - interrupts = <11 4 0>; - dmas = <&dma 1 0>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; @@ -544,8 +628,8 @@ mmc1: mmc@fffd0000 { compatible = "atmel,hsmci"; reg = <0xfffd0000 0x600>; - interrupts = <29 4 0>; - dmas = <&dma 1 13>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; @@ -579,6 +663,68 @@ pinctrl-0 = <&pinctrl_spi1>; status = "disabled"; }; + + usb2: gadget@fff78000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9rl-udc"; + reg = <0x00600000 0x80000 + 0xfff78000 0x400>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + + ep0 { + reg = <0>; + atmel,fifo-size = <64>; + atmel,nb-banks = <1>; + }; + + ep1 { + reg = <1>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep2 { + reg = <2>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep3 { + reg = <3>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep4 { + reg = <4>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep5 { + reg = <5>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep6 { + reg = <6>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + }; }; nand0: nand@40000000 { @@ -592,8 +738,8 @@ atmel,nand-cmd-offset = <22>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioC 8 0 - &pioC 14 0 + gpios = <&pioC 8 GPIO_ACTIVE_HIGH + &pioC 14 GPIO_ACTIVE_HIGH 0 >; status = "disabled"; @@ -602,22 +748,22 @@ usb0: ohci@00700000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00700000 0x100000>; - interrupts = <22 4 2>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; usb1: ehci@00800000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; - interrupts = <22 4 2>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; }; i2c@0 { compatible = "i2c-gpio"; - gpios = <&pioA 20 0 /* sda */ - &pioA 21 0 /* scl */ + gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */ + &pioA 21 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 51d9251b5bbe..a4b00e5c61c0 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -7,7 +7,7 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9g45.dtsi" +#include "at91sam9g45.dtsi" / { model = "Atmel AT91SAM9M10G45-EK"; @@ -59,6 +59,10 @@ status = "okay"; }; + watchdog@fffffd40 { + status = "okay"; + }; + mmc0: mmc@fff80000 { pinctrl-0 = < &pinctrl_board_mmc0 @@ -68,7 +72,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioD 10 0>; + cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>; }; }; @@ -81,8 +85,8 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioD 11 0>; - wp-gpios = <&pioD 29 0>; + cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>; + wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; }; }; @@ -90,15 +94,15 @@ mmc0 { pinctrl_board_mmc0: mmc0-board { atmel,pins = - <3 10 0x0 0x5>; /* PD10 gpio CD pin pull up and deglitch */ + <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD10 gpio CD pin pull up and deglitch */ }; }; mmc1 { pinctrl_board_mmc1: mmc1-board { atmel,pins = - <3 11 0x0 0x5 /* PD11 gpio CD pin pull up and deglitch */ - 3 29 0x0 0x1>; /* PD29 gpio WP pin pull up */ + <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* PD11 gpio CD pin pull up and deglitch */ + AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD29 gpio WP pin pull up */ }; }; }; @@ -112,6 +116,11 @@ reg = <0>; }; }; + + usb2: gadget@fff78000 { + atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; }; nand0: nand@40000000 { @@ -139,8 +148,8 @@ usb0: ohci@00700000 { status = "okay"; num-ports = <2>; - atmel,vbus-gpio = <&pioD 1 1 - &pioD 3 1>; + atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW + &pioD 3 GPIO_ACTIVE_LOW>; }; usb1: ehci@00800000 { @@ -153,19 +162,19 @@ d8 { label = "d8"; - gpios = <&pioD 30 0>; + gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; d6 { label = "d6"; - gpios = <&pioD 0 1>; + gpios = <&pioD 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "nand-disk"; }; d7 { label = "d7"; - gpios = <&pioD 31 1>; + gpios = <&pioD 31 GPIO_ACTIVE_LOW>; linux,default-trigger = "mmc0"; }; }; @@ -175,45 +184,45 @@ left_click { label = "left_click"; - gpios = <&pioB 6 1>; + gpios = <&pioB 6 GPIO_ACTIVE_LOW>; linux,code = <272>; gpio-key,wakeup; }; right_click { label = "right_click"; - gpios = <&pioB 7 1>; + gpios = <&pioB 7 GPIO_ACTIVE_LOW>; linux,code = <273>; gpio-key,wakeup; }; left { label = "Joystick Left"; - gpios = <&pioB 14 1>; + gpios = <&pioB 14 GPIO_ACTIVE_LOW>; linux,code = <105>; }; right { label = "Joystick Right"; - gpios = <&pioB 15 1>; + gpios = <&pioB 15 GPIO_ACTIVE_LOW>; linux,code = <106>; }; up { label = "Joystick Up"; - gpios = <&pioB 16 1>; + gpios = <&pioB 16 GPIO_ACTIVE_LOW>; linux,code = <103>; }; down { label = "Joystick Down"; - gpios = <&pioB 17 1>; + gpios = <&pioB 17 GPIO_ACTIVE_LOW>; linux,code = <108>; }; enter { label = "Joystick Press"; - gpios = <&pioB 18 1>; + gpios = <&pioB 18 GPIO_ACTIVE_LOW>; linux,code = <28>; }; }; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 3de8e6dfbcb1..bb7f564b3a55 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -7,7 +7,11 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/dma/at91.h> +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Atmel AT91SAM9N12 SoC"; @@ -31,8 +35,12 @@ ssc0 = &ssc0; }; cpus { - cpu@0 { - compatible = "arm,arm926ejs"; + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; }; }; @@ -57,6 +65,7 @@ compatible = "atmel,at91rm9200-aic"; interrupt-controller; reg = <0xfffff000 0x200>; + atmel,external-irqs = <31>; }; ramc0: ramc@ffffe800 { @@ -77,7 +86,7 @@ pit: timer@fffffe30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; shdwc@fffffe10 { @@ -88,8 +97,8 @@ mmc0: mmc@f0008000 { compatible = "atmel,hsmci"; reg = <0xf0008000 0x600>; - interrupts = <12 4 0>; - dmas = <&dma 1 0>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; @@ -99,19 +108,19 @@ tcb0: timer@f8008000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8008000 0x100>; - interrupts = <17 4 0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; }; tcb1: timer@f800c000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf800c000 0x100>; - interrupts = <17 4 0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; }; dma: dma-controller@ffffec00 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffec00 0x200>; - interrupts = <20 4 0>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; }; @@ -133,159 +142,235 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <0 9 0x1 0x0 /* PA9 periph A */ - 0 10 0x1 0x1>; /* PA10 periph with pullup */ + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */ }; }; usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - <0 1 0x1 0x1 /* PA1 periph A with pullup */ - 0 0 0x1 0x0>; /* PA0 periph A */ + <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ + AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */ }; pinctrl_usart0_rts: usart0_rts-0 { atmel,pins = - <0 2 0x1 0x0>; /* PA2 periph A */ + <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ }; pinctrl_usart0_cts: usart0_cts-0 { atmel,pins = - <0 3 0x1 0x0>; /* PA3 periph A */ + <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ }; }; usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - <0 6 0x1 0x1 /* PA6 periph A with pullup */ - 0 5 0x1 0x0>; /* PA5 periph A */ + <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ }; }; usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - <0 8 0x1 0x1 /* PA8 periph A with pullup */ - 0 7 0x1 0x0>; /* PA7 periph A */ + <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */ }; pinctrl_usart2_rts: usart2_rts-0 { atmel,pins = - <1 0 0x2 0x0>; /* PB0 periph B */ + <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ }; pinctrl_usart2_cts: usart2_cts-0 { atmel,pins = - <1 1 0x2 0x0>; /* PB1 periph B */ + <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ }; }; usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - <2 23 0x2 0x1 /* PC23 periph B with pullup */ - 2 22 0x2 0x0>; /* PC22 periph B */ + <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */ + AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */ }; pinctrl_usart3_rts: usart3_rts-0 { atmel,pins = - <2 24 0x2 0x0>; /* PC24 periph B */ + <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ }; pinctrl_usart3_cts: usart3_cts-0 { atmel,pins = - <2 25 0x2 0x0>; /* PC25 periph B */ + <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ }; }; uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - <2 9 0x3 0x1 /* PC9 periph C with pullup */ - 2 8 0x3 0x0>; /* PC8 periph C */ + <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */ + AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */ }; }; uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - <2 16 0x3 0x1 /* PC17 periph C with pullup */ - 2 17 0x3 0x0>; /* PC16 periph C */ + <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */ + AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */ }; }; nand { pinctrl_nand: nand-0 { atmel,pins = - <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/ - 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */ + <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/ + AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */ }; }; mmc0 { pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { atmel,pins = - <0 17 0x1 0x0 /* PA17 periph A */ - 0 16 0x1 0x1 /* PA16 periph A with pullup */ - 0 15 0x1 0x1>; /* PA15 periph A with pullup */ + <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ }; pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { atmel,pins = - <0 18 0x1 0x1 /* PA18 periph A with pullup */ - 0 19 0x1 0x1 /* PA19 periph A with pullup */ - 0 20 0x1 0x1>; /* PA20 periph A with pullup */ + <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ }; pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { atmel,pins = - <0 11 0x2 0x1 /* PA11 periph B with pullup */ - 0 12 0x2 0x1 /* PA12 periph B with pullup */ - 0 13 0x2 0x1 /* PA13 periph B with pullup */ - 0 14 0x2 0x1>; /* PA14 periph B with pullup */ + <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ + AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ + AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */ + AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */ }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx-0 { atmel,pins = - <0 24 0x2 0x0 /* PA24 periph B */ - 0 25 0x2 0x0 /* PA25 periph B */ - 0 26 0x2 0x0>; /* PA26 periph B */ + <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ + AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ + AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ }; pinctrl_ssc0_rx: ssc0_rx-0 { atmel,pins = - <0 27 0x2 0x0 /* PA27 periph B */ - 0 28 0x2 0x0 /* PA28 periph B */ - 0 29 0x2 0x0>; /* PA29 periph B */ + <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ + AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ + AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ }; }; spi0 { pinctrl_spi0: spi0-0 { atmel,pins = - <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */ - 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */ - 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */ + <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ }; }; spi1 { pinctrl_spi1: spi1-0 { atmel,pins = - <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */ - 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */ - 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */ + <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ + AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ + AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + tcb1 { + pinctrl_tcb1_tclk0: tcb1_tclk0-0 { + atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tclk1: tcb1_tclk1-0 { + atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tclk2: tcb1_tclk2-0 { + atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa0: tcb1_tioa0-0 { + atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa1: tcb1_tioa1-0 { + atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa2: tcb1_tioa2-0 { + atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob0: tcb1_tiob0-0 { + atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob1: tcb1_tiob1-0 { + atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob2: tcb1_tiob2-0 { + atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; }; }; pioA: gpio@fffff400 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -295,7 +380,7 @@ pioB: gpio@fffff600 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff600 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -305,7 +390,7 @@ pioC: gpio@fffff800 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff800 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -315,7 +400,7 @@ pioD: gpio@fffffa00 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffffa00 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -326,7 +411,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; status = "disabled"; @@ -335,7 +420,7 @@ ssc0: ssc@f0010000 { compatible = "atmel,at91sam9g45-ssc"; reg = <0xf0010000 0x4000>; - interrupts = <28 4 5>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; @@ -344,7 +429,7 @@ usart0: serial@f801c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf801c000 0x4000>; - interrupts = <5 4 5>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; status = "disabled"; @@ -353,7 +438,7 @@ usart1: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x4000>; - interrupts = <6 4 5>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; status = "disabled"; @@ -362,7 +447,7 @@ usart2: serial@f8024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x4000>; - interrupts = <7 4 5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; status = "disabled"; @@ -371,7 +456,7 @@ usart3: serial@f8028000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8028000 0x4000>; - interrupts = <8 4 5>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; status = "disabled"; @@ -380,9 +465,9 @@ i2c0: i2c@f8010000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8010000 0x100>; - interrupts = <9 4 6>; - dmas = <&dma 1 13>, - <&dma 1 14>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>, + <&dma 1 AT91_DMA_CFG_PER_ID(14)>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; @@ -392,9 +477,9 @@ i2c1: i2c@f8014000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8014000 0x100>; - interrupts = <10 4 6>; - dmas = <&dma 1 15>, - <&dma 1 16>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>, + <&dma 1 AT91_DMA_CFG_PER_ID(16)>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; @@ -406,7 +491,10 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xf0000000 0x100>; - interrupts = <13 4 3>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>, + <&dma 1 AT91_DMA_CFG_PER_ID(2)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; status = "disabled"; @@ -417,11 +505,20 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xf0004000 0x100>; - interrupts = <14 4 3>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>, + <&dma 1 AT91_DMA_CFG_PER_ID(4)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; status = "disabled"; }; + + watchdog@fffffe40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffe40 0x10>; + status = "disabled"; + }; }; nand0: nand@40000000 { @@ -438,8 +535,8 @@ atmel,nand-cmd-offset = <22>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioD 5 0 - &pioD 4 0 + gpios = <&pioD 5 GPIO_ACTIVE_HIGH + &pioD 4 GPIO_ACTIVE_HIGH 0 >; status = "disabled"; @@ -448,15 +545,15 @@ usb0: ohci@00500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x00100000>; - interrupts = <22 4 2>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; }; i2c@0 { compatible = "i2c-gpio"; - gpios = <&pioA 30 0 /* sda */ - &pioA 31 0 /* scl */ + gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ + &pioA 31 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index d30e48bd1e9d..d59b70c6a6a0 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -7,7 +7,7 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9n12.dtsi" +#include "at91sam9n12.dtsi" / { model = "Atmel AT91SAM9N12-EK"; @@ -55,7 +55,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioA 7 0>; + cd-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>; }; }; @@ -63,7 +63,7 @@ mmc0 { pinctrl_board_mmc0: mmc0-board { atmel,pins = - <0 7 0x0 0x5>; /* PA7 gpio CD pin pull up and deglitch */ + <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PA7 gpio CD pin pull up and deglitch */ }; }; }; @@ -77,6 +77,10 @@ reg = <0>; }; }; + + watchdog@fffffe40 { + status = "okay"; + }; }; nand0: nand@40000000 { @@ -95,19 +99,19 @@ d8 { label = "d8"; - gpios = <&pioB 4 1>; + gpios = <&pioB 4 GPIO_ACTIVE_LOW>; linux,default-trigger = "mmc0"; }; d9 { label = "d6"; - gpios = <&pioB 5 1>; + gpios = <&pioB 5 GPIO_ACTIVE_LOW>; linux,default-trigger = "nand-disk"; }; d10 { label = "d7"; - gpios = <&pioB 6 0>; + gpios = <&pioB 6 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; @@ -117,7 +121,7 @@ enter { label = "Enter"; - gpios = <&pioB 4 1>; + gpios = <&pioB 4 GPIO_ACTIVE_LOW>; linux,code = <28>; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi index 9ac2bc2b4f07..49e94aba938f 100644 --- a/arch/arm/boot/dts/at91sam9x25.dtsi +++ b/arch/arm/boot/dts/at91sam9x25.dtsi @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ -/include/ "at91sam9x5.dtsi" +#include "at91sam9x5.dtsi" / { model = "Atmel AT91SAM9X25 SoC"; @@ -26,16 +26,16 @@ macb1 { pinctrl_macb1_rmii: macb1_rmii-0 { atmel,pins = - <2 16 0x2 0x0 /* PC16 periph B */ - 2 18 0x2 0x0 /* PC18 periph B */ - 2 19 0x2 0x0 /* PC19 periph B */ - 2 20 0x2 0x0 /* PC20 periph B */ - 2 21 0x2 0x0 /* PC21 periph B */ - 2 27 0x2 0x0 /* PC27 periph B */ - 2 28 0x2 0x0 /* PC28 periph B */ - 2 29 0x2 0x0 /* PC29 periph B */ - 2 30 0x2 0x0 /* PC30 periph B */ - 2 31 0x2 0x0>; /* PC31 periph B */ + <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */ + AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */ + AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */ + AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */ + AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */ + AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */ + AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */ + AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */ + AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */ + AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */ }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts index 3b40d11d65e7..494864836e83 100644 --- a/arch/arm/boot/dts/at91sam9x25ek.dts +++ b/arch/arm/boot/dts/at91sam9x25ek.dts @@ -7,11 +7,11 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9x25.dtsi" -/include/ "at91sam9x5ek.dtsi" +#include "at91sam9x25.dtsi" +#include "at91sam9x5ek.dtsi" / { - model = "Atmel AT91SAM9G25-EK"; + model = "Atmel AT91SAM9X25-EK"; compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; ahb { diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi index ba67d83d17ac..1a3d525a1f5d 100644 --- a/arch/arm/boot/dts/at91sam9x35.dtsi +++ b/arch/arm/boot/dts/at91sam9x35.dtsi @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ -/include/ "at91sam9x5.dtsi" +#include "at91sam9x5.dtsi" / { model = "Atmel AT91SAM9X35 SoC"; diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts index 6ad19a0d5424..343d32818ca3 100644 --- a/arch/arm/boot/dts/at91sam9x35ek.dts +++ b/arch/arm/boot/dts/at91sam9x35ek.dts @@ -7,8 +7,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9x35.dtsi" -/include/ "at91sam9x5ek.dtsi" +#include "at91sam9x35.dtsi" +#include "at91sam9x5ek.dtsi" / { model = "Atmel AT91SAM9X35-EK"; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 1145ac330fb7..57d45f5bea09 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -9,7 +9,11 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/dma/at91.h> +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Atmel AT91SAM9x5 family SoC"; @@ -33,8 +37,12 @@ ssc0 = &ssc0; }; cpus { - cpu@0 { - compatible = "arm,arm926ejs"; + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; }; }; @@ -85,32 +93,32 @@ pit: timer@fffffe30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; tcb0: timer@f8008000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8008000 0x100>; - interrupts = <17 4 0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; }; tcb1: timer@f800c000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf800c000 0x100>; - interrupts = <17 4 0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; }; dma0: dma-controller@ffffec00 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffec00 0x200>; - interrupts = <20 4 0>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; }; dma1: dma-controller@ffffee00 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffee00 0x200>; - interrupts = <21 4 0>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; }; @@ -124,297 +132,373 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <0 9 0x1 0x0 /* PA9 periph A */ - 0 10 0x1 0x1>; /* PA10 periph A with pullup */ + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph A with pullup */ }; }; usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - <0 0 0x1 0x1 /* PA0 periph A with pullup */ - 0 1 0x1 0x0>; /* PA1 periph A */ + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA1 periph A */ }; pinctrl_usart0_rts: usart0_rts-0 { atmel,pins = - <0 2 0x1 0x0>; /* PA2 periph A */ + <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ }; pinctrl_usart0_cts: usart0_cts-0 { atmel,pins = - <0 3 0x1 0x0>; /* PA3 periph A */ + <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ }; pinctrl_usart0_sck: usart0_sck-0 { atmel,pins = - <0 4 0x1 0x0>; /* PA4 periph A */ + <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */ }; }; usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - <0 5 0x1 0x1 /* PA5 periph A with pullup */ - 0 6 0x1 0x0>; /* PA6 periph A */ + <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */ }; pinctrl_usart1_rts: usart1_rts-0 { atmel,pins = - <2 27 0x3 0x0>; /* PC27 periph C */ + <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC27 periph C */ }; pinctrl_usart1_cts: usart1_cts-0 { atmel,pins = - <2 28 0x3 0x0>; /* PC28 periph C */ + <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C */ }; pinctrl_usart1_sck: usart1_sck-0 { atmel,pins = - <2 28 0x3 0x0>; /* PC29 periph C */ + <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */ }; }; usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - <0 7 0x1 0x1 /* PA7 periph A with pullup */ - 0 8 0x1 0x0>; /* PA8 periph A */ + <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ }; pinctrl_uart2_rts: uart2_rts-0 { atmel,pins = - <1 0 0x2 0x0>; /* PB0 periph B */ + <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ }; pinctrl_uart2_cts: uart2_cts-0 { atmel,pins = - <1 1 0x2 0x0>; /* PB1 periph B */ + <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ }; pinctrl_usart2_sck: usart2_sck-0 { atmel,pins = - <1 2 0x2 0x0>; /* PB2 periph B */ + <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */ }; }; usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - <2 22 0x2 0x1 /* PC22 periph B with pullup */ - 2 23 0x2 0x0>; /* PC23 periph B */ + <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */ + AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */ }; pinctrl_usart3_rts: usart3_rts-0 { atmel,pins = - <2 24 0x2 0x0>; /* PC24 periph B */ + <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ }; pinctrl_usart3_cts: usart3_cts-0 { atmel,pins = - <2 25 0x2 0x0>; /* PC25 periph B */ + <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ }; pinctrl_usart3_sck: usart3_sck-0 { atmel,pins = - <2 26 0x2 0x0>; /* PC26 periph B */ + <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */ }; }; uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - <2 8 0x3 0x0 /* PC8 periph C */ - 2 9 0x3 0x1>; /* PC9 periph C with pullup */ + <AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC8 periph C */ + AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC9 periph C with pullup */ }; }; uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - <2 16 0x3 0x0 /* PC16 periph C */ - 2 17 0x3 0x1>; /* PC17 periph C with pullup */ + <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC16 periph C */ + AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC17 periph C with pullup */ }; }; nand { pinctrl_nand: nand-0 { atmel,pins = - <3 0 0x1 0x0 /* PD0 periph A Read Enable */ - 3 1 0x1 0x0 /* PD1 periph A Write Enable */ - 3 2 0x1 0x0 /* PD2 periph A Address Latch Enable */ - 3 3 0x1 0x0 /* PD3 periph A Command Latch Enable */ - 3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */ - 3 5 0x0 0x1 /* PD5 gpio RDY/BUSY pin pull_up */ - 3 6 0x1 0x0 /* PD6 periph A Data bit 0 */ - 3 7 0x1 0x0 /* PD7 periph A Data bit 1 */ - 3 8 0x1 0x0 /* PD8 periph A Data bit 2 */ - 3 9 0x1 0x0 /* PD9 periph A Data bit 3 */ - 3 10 0x1 0x0 /* PD10 periph A Data bit 4 */ - 3 11 0x1 0x0 /* PD11 periph A Data bit 5 */ - 3 12 0x1 0x0 /* PD12 periph A Data bit 6 */ - 3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */ + <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */ + AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A Write Enable */ + AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A Address Latch Enable */ + AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A Command Latch Enable */ + AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD4 gpio Chip Enable pin pull_up */ + AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY/BUSY pin pull_up */ + AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */ + AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A Data bit 1 */ + AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A Data bit 2 */ + AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A Data bit 3 */ + AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A Data bit 4 */ + AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A Data bit 5 */ + AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD12 periph A Data bit 6 */ + AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */ }; pinctrl_nand_16bits: nand_16bits-0 { atmel,pins = - <3 14 0x1 0x0 /* PD14 periph A Data bit 8 */ - 3 15 0x1 0x0 /* PD15 periph A Data bit 9 */ - 3 16 0x1 0x0 /* PD16 periph A Data bit 10 */ - 3 17 0x1 0x0 /* PD17 periph A Data bit 11 */ - 3 18 0x1 0x0 /* PD18 periph A Data bit 12 */ - 3 19 0x1 0x0 /* PD19 periph A Data bit 13 */ - 3 20 0x1 0x0 /* PD20 periph A Data bit 14 */ - 3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */ + <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A Data bit 8 */ + AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A Data bit 9 */ + AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD16 periph A Data bit 10 */ + AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A Data bit 11 */ + AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD18 periph A Data bit 12 */ + AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD19 periph A Data bit 13 */ + AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */ + AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */ }; }; macb0 { pinctrl_macb0_rmii: macb0_rmii-0 { atmel,pins = - <1 0 0x1 0x0 /* PB0 periph A */ - 1 1 0x1 0x0 /* PB1 periph A */ - 1 2 0x1 0x0 /* PB2 periph A */ - 1 3 0x1 0x0 /* PB3 periph A */ - 1 4 0x1 0x0 /* PB4 periph A */ - 1 5 0x1 0x0 /* PB5 periph A */ - 1 6 0x1 0x0 /* PB6 periph A */ - 1 7 0x1 0x0 /* PB7 periph A */ - 1 9 0x1 0x0 /* PB9 periph A */ - 1 10 0x1 0x0>; /* PB10 periph A */ + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ }; pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { atmel,pins = - <1 8 0x1 0x0 /* PB8 periph A */ - 1 11 0x1 0x0 /* PB11 periph A */ - 1 12 0x1 0x0 /* PB12 periph A */ - 1 13 0x1 0x0 /* PB13 periph A */ - 1 14 0x1 0x0 /* PB14 periph A */ - 1 15 0x1 0x0 /* PB15 periph A */ - 1 16 0x1 0x0 /* PB16 periph A */ - 1 17 0x1 0x0>; /* PB17 periph A */ + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */ + AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ }; }; mmc0 { pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { atmel,pins = - <0 17 0x1 0x0 /* PA17 periph A */ - 0 16 0x1 0x1 /* PA16 periph A with pullup */ - 0 15 0x1 0x1>; /* PA15 periph A with pullup */ + <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ }; pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { atmel,pins = - <0 18 0x1 0x1 /* PA18 periph A with pullup */ - 0 19 0x1 0x1 /* PA19 periph A with pullup */ - 0 20 0x1 0x1>; /* PA20 periph A with pullup */ + <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ }; }; mmc1 { pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { atmel,pins = - <0 13 0x2 0x0 /* PA13 periph B */ - 0 12 0x2 0x1 /* PA12 periph B with pullup */ - 0 11 0x2 0x1>; /* PA11 periph B with pullup */ + <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA13 periph B */ + AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ + AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA11 periph B with pullup */ }; pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { atmel,pins = - <0 2 0x2 0x1 /* PA2 periph B with pullup */ - 0 3 0x2 0x1 /* PA3 periph B with pullup */ - 0 4 0x2 0x1>; /* PA4 periph B with pullup */ + <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA2 periph B with pullup */ + AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA3 periph B with pullup */ + AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA4 periph B with pullup */ }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx-0 { atmel,pins = - <0 24 0x2 0x0 /* PA24 periph B */ - 0 25 0x2 0x0 /* PA25 periph B */ - 0 26 0x2 0x0>; /* PA26 periph B */ + <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ + AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ + AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ }; pinctrl_ssc0_rx: ssc0_rx-0 { atmel,pins = - <0 27 0x2 0x0 /* PA27 periph B */ - 0 28 0x2 0x0 /* PA28 periph B */ - 0 29 0x2 0x0>; /* PA29 periph B */ + <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ + AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ + AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ }; }; spi0 { pinctrl_spi0: spi0-0 { atmel,pins = - <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */ - 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */ - 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */ + <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ }; }; spi1 { pinctrl_spi1: spi1-0 { atmel,pins = - <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */ - 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */ - 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */ + <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ + AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ + AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ }; }; i2c0 { pinctrl_i2c0: i2c0-0 { atmel,pins = - <0 30 0x1 0x0 /* PA30 periph A I2C0 data */ - 0 31 0x1 0x0>; /* PA31 periph A I2C0 clock */ + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A I2C0 data */ + AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A I2C0 clock */ }; }; i2c1 { pinctrl_i2c1: i2c1-0 { atmel,pins = - <2 0 0x3 0x0 /* PC0 periph C I2C1 data */ - 2 1 0x3 0x0>; /* PC1 periph C I2C1 clock */ + <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */ + AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC1 periph C I2C1 clock */ }; }; i2c2 { pinctrl_i2c2: i2c2-0 { atmel,pins = - <1 4 0x2 0x0 /* PB4 periph B I2C2 data */ - 1 5 0x2 0x0>; /* PB5 periph B I2C2 clock */ + <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B I2C2 data */ + AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B I2C2 clock */ }; }; i2c_gpio0 { pinctrl_i2c_gpio0: i2c_gpio0-0 { atmel,pins = - <0 30 0x0 0x2 /* PA30 gpio multidrive I2C0 data */ - 0 31 0x0 0x2>; /* PA31 gpio multidrive I2C0 clock */ + <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA30 gpio multidrive I2C0 data */ + AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA31 gpio multidrive I2C0 clock */ }; }; i2c_gpio1 { pinctrl_i2c_gpio1: i2c_gpio1-0 { atmel,pins = - <2 0 0x0 0x2 /* PC0 gpio multidrive I2C1 data */ - 2 1 0x0 0x2>; /* PC1 gpio multidrive I2C1 clock */ + <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */ + AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PC1 gpio multidrive I2C1 clock */ }; }; i2c_gpio2 { pinctrl_i2c_gpio2: i2c_gpio2-0 { atmel,pins = - <1 4 0x0 0x2 /* PB4 gpio multidrive I2C2 data */ - 1 5 0x0 0x2>; /* PB5 gpio multidrive I2C2 clock */ + <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PB4 gpio multidrive I2C2 data */ + AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB5 gpio multidrive I2C2 clock */ + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + tcb1 { + pinctrl_tcb1_tclk0: tcb1_tclk0-0 { + atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tclk1: tcb1_tclk1-0 { + atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tclk2: tcb1_tclk2-0 { + atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa0: tcb1_tioa0-0 { + atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa1: tcb1_tioa1-0 { + atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa2: tcb1_tioa2-0 { + atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob0: tcb1_tiob0-0 { + atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob1: tcb1_tiob1-0 { + atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob2: tcb1_tiob2-0 { + atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; }; }; pioA: gpio@fffff400 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -424,7 +508,7 @@ pioB: gpio@fffff600 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff600 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; #gpio-lines = <19>; @@ -435,7 +519,7 @@ pioC: gpio@fffff800 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff800 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -445,7 +529,7 @@ pioD: gpio@fffffa00 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffffa00 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; #gpio-lines = <22>; @@ -457,7 +541,7 @@ ssc0: ssc@f0010000 { compatible = "atmel,at91sam9g45-ssc"; reg = <0xf0010000 0x4000>; - interrupts = <28 4 5>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; @@ -466,8 +550,8 @@ mmc0: mmc@f0008000 { compatible = "atmel,hsmci"; reg = <0xf0008000 0x600>; - interrupts = <12 4 0>; - dmas = <&dma0 1 0>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; @@ -477,8 +561,8 @@ mmc1: mmc@f000c000 { compatible = "atmel,hsmci"; reg = <0xf000c000 0x600>; - interrupts = <26 4 0>; - dmas = <&dma1 1 0>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; @@ -488,7 +572,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; status = "disabled"; @@ -497,7 +581,7 @@ usart0: serial@f801c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf801c000 0x200>; - interrupts = <5 4 5>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; status = "disabled"; @@ -506,7 +590,7 @@ usart1: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x200>; - interrupts = <6 4 5>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; status = "disabled"; @@ -515,7 +599,7 @@ usart2: serial@f8024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x200>; - interrupts = <7 4 5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; status = "disabled"; @@ -524,7 +608,7 @@ macb0: ethernet@f802c000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xf802c000 0x100>; - interrupts = <24 4 3>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_rmii>; status = "disabled"; @@ -533,16 +617,16 @@ macb1: ethernet@f8030000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xf8030000 0x100>; - interrupts = <27 4 3>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; status = "disabled"; }; i2c0: i2c@f8010000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8010000 0x100>; - interrupts = <9 4 6>; - dmas = <&dma0 1 7>, - <&dma0 1 8>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(8)>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; @@ -554,9 +638,9 @@ i2c1: i2c@f8014000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8014000 0x100>; - interrupts = <10 4 6>; - dmas = <&dma1 1 5>, - <&dma1 1 6>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>, + <&dma1 1 AT91_DMA_CFG_PER_ID(6)>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; @@ -568,9 +652,9 @@ i2c2: i2c@f8018000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8018000 0x100>; - interrupts = <11 4 6>; - dmas = <&dma0 1 9>, - <&dma0 1 10>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(10)>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; @@ -579,10 +663,28 @@ status = "disabled"; }; + uart0: serial@f8040000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8040000 0x200>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "disabled"; + }; + + uart1: serial@f8044000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8044000 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "disabled"; + }; + adc0: adc@f804c000 { compatible = "atmel,at91sam9260-adc"; reg = <0xf804c000 0x100>; - interrupts = <19 4 0>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; atmel,adc-use-external; atmel,adc-channels-used = <0xffff>; atmel,adc-vref = <3300>; @@ -625,7 +727,10 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xf0000000 0x100>; - interrupts = <13 4 3>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(2)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; status = "disabled"; @@ -636,16 +741,87 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xf0004000 0x100>; - interrupts = <14 4 3>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>, + <&dma1 1 AT91_DMA_CFG_PER_ID(2)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; status = "disabled"; }; + usb2: gadget@f803c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9rl-udc"; + reg = <0x00500000 0x80000 + 0xf803c000 0x400>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + + ep0 { + reg = <0>; + atmel,fifo-size = <64>; + atmel,nb-banks = <1>; + }; + + ep1 { + reg = <1>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep2 { + reg = <2>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep3 { + reg = <3>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep4 { + reg = <4>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep5 { + reg = <5>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep6 { + reg = <6>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + }; + + watchdog@fffffe40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffe40 0x10>; + status = "disabled"; + }; + rtc@fffffeb0 { - compatible = "atmel,at91rm9200-rtc"; + compatible = "atmel,at91sam9x5-rtc"; reg = <0xfffffeb0 0x40>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; status = "disabled"; }; }; @@ -664,8 +840,8 @@ atmel,nand-cmd-offset = <22>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioD 5 0 - &pioD 4 0 + gpios = <&pioD 5 GPIO_ACTIVE_HIGH + &pioD 4 GPIO_ACTIVE_HIGH 0 >; status = "disabled"; @@ -674,22 +850,22 @@ usb0: ohci@00600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; - interrupts = <22 4 2>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; usb1: ehci@00700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; - interrupts = <22 4 2>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; }; i2c@0 { compatible = "i2c-gpio"; - gpios = <&pioA 30 0 /* sda */ - &pioA 31 0 /* scl */ + gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ + &pioA 31 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; @@ -703,8 +879,8 @@ i2c@1 { compatible = "i2c-gpio"; - gpios = <&pioC 0 0 /* sda */ - &pioC 1 0 /* scl */ + gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ + &pioC 1 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; @@ -718,8 +894,8 @@ i2c@2 { compatible = "i2c-gpio"; - gpios = <&pioB 4 0 /* sda */ - &pioB 5 0 /* scl */ + gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ + &pioB 5 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi index 347a74a857f6..4a5ee5cc115a 100644 --- a/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi @@ -28,7 +28,7 @@ pinctrl@fffff400 { 1wire_cm { pinctrl_1wire_cm: 1wire_cm-0 { - atmel,pins = <1 18 0x0 0x2>; /* PB18 multidrive, conflicts with led */ + atmel,pins = <AT91_PIOB 18 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB18 multidrive, conflicts with led */ }; }; }; @@ -75,19 +75,19 @@ pb18 { label = "pb18"; - gpios = <&pioB 18 1>; + gpios = <&pioB 18 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; pd21 { label = "pd21"; - gpios = <&pioD 21 0>; + gpios = <&pioD 21 GPIO_ACTIVE_HIGH>; }; }; 1wire_cm { compatible = "w1-gpio"; - gpios = <&pioB 18 0>; + gpios = <&pioB 18 GPIO_ACTIVE_HIGH>; linux,open-drain; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_1wire_cm>; diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi index 1fa48d2bfd80..b753855b2058 100644 --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi @@ -6,7 +6,7 @@ * * Licensed under GPLv2 or later. */ -/include/ "at91sam9x5cm.dtsi" +#include "at91sam9x5cm.dtsi" / { model = "Atmel AT91SAM9X5-EK"; @@ -27,7 +27,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioD 15 0>; + cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; }; }; @@ -40,7 +40,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioD 14 0>; + cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; }; }; @@ -52,6 +52,11 @@ status = "okay"; }; + usb2: gadget@f803c000 { + atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + i2c0: i2c@f8010000 { status = "okay"; }; @@ -60,14 +65,14 @@ mmc0 { pinctrl_board_mmc0: mmc0-board { atmel,pins = - <3 15 0x0 0x5>; /* PD15 gpio CD pin pull up and deglitch */ + <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */ }; }; mmc1 { pinctrl_board_mmc1: mmc1-board { atmel,pins = - <3 14 0x0 0x5>; /* PD14 gpio CD pin pull up and deglitch */ + <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD14 gpio CD pin pull up and deglitch */ }; }; }; @@ -81,13 +86,17 @@ reg = <0>; }; }; + + watchdog@fffffe40 { + status = "okay"; + }; }; usb0: ohci@00600000 { status = "okay"; num-ports = <2>; - atmel,vbus-gpio = <&pioD 19 1 - &pioD 20 1 + atmel,vbus-gpio = <&pioD 19 GPIO_ACTIVE_LOW + &pioD 20 GPIO_ACTIVE_LOW >; }; diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index 7d1a27949c13..9866cd736dee 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -613,7 +613,7 @@ }; rtc-iobg { - compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; + compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x80030000 0x10000>; diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts index 248067cf7069..67ec524098b5 100644 --- a/arch/arm/boot/dts/bcm11351-brt.dts +++ b/arch/arm/boot/dts/bcm11351-brt.dts @@ -13,7 +13,7 @@ /dts-v1/; -/include/ "bcm11351.dtsi" +#include "bcm11351.dtsi" / { model = "BCM11351 BRT board"; @@ -27,4 +27,21 @@ status = "okay"; }; + sdio0: sdio@0x3f180000 { + max-frequency = <48000000>; + status = "okay"; + }; + + sdio1: sdio@0x3f190000 { + non-removable; + max-frequency = <48000000>; + status = "okay"; + }; + + sdio3: sdio@0x3f1b0000 { + max-frequency = <48000000>; + status = "okay"; + }; + + }; diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 41b2c6c33f09..c0cdf66f8964 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -11,7 +11,10 @@ * GNU General Public License for more details. */ -/include/ "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +#include "skeleton.dtsi" / { model = "BCM11351 SoC"; @@ -33,7 +36,7 @@ smc@0x3404c000 { compatible = "bcm,bcm11351-smc", "bcm,kona-smc"; - reg = <0x3404c000 0x400>; //1 KiB in SRAM + reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ }; uart@3e000000 { @@ -41,23 +44,51 @@ status = "disabled"; reg = <0x3e000000 0x1000>; clock-frequency = <13000000>; - interrupts = <0x0 67 0x4>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; }; L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0x3ff20000 0x1000>; - cache-unified; - cache-level = <2>; + compatible = "bcm,bcm11351-a2-pl310-cache"; + reg = <0x3ff20000 0x1000>; + cache-unified; + cache-level = <2>; }; timer@35006000 { compatible = "bcm,kona-timer"; reg = <0x35006000 0x1000>; - interrupts = <0x0 7 0x4>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <32768>; }; + sdio0: sdio@0x3f180000 { + compatible = "bcm,kona-sdhci"; + reg = <0x3f180000 0x10000>; + interrupts = <0x0 77 0x4>; + status = "disabled"; + }; + + sdio1: sdio@0x3f190000 { + compatible = "bcm,kona-sdhci"; + reg = <0x3f190000 0x10000>; + interrupts = <0x0 76 0x4>; + status = "disabled"; + }; + + sdio2: sdio@0x3f1a0000 { + compatible = "bcm,kona-sdhci"; + reg = <0x3f1a0000 0x10000>; + interrupts = <0x0 74 0x4>; + status = "disabled"; + }; + + sdio3: sdio@0x3f1b0000 { + compatible = "bcm,kona-sdhci"; + reg = <0x3f1b0000 0x10000>; + interrupts = <0x0 73 0x4>; + status = "disabled"; + }; + }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index aafda174a605..6e9deb786a7d 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -8,6 +8,17 @@ memory { reg = <0 0x10000000>; }; + + leds { + compatible = "gpio-leds"; + + act { + label = "ACT"; + gpios = <&gpio 16 1>; + default-state = "keep"; + linux,default-trigger = "heartbeat"; + }; + }; }; &gpio { diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index f0052dccf9a8..1e12aeff403b 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -44,6 +44,7 @@ reg = <0x7e201000 0x1000>; interrupts = <2 25>; clock-frequency = <3000000>; + arm,primecell-periphid = <0x00241011>; }; gpio: gpio { diff --git a/arch/arm/boot/dts/ccu8540.dts b/arch/arm/boot/dts/ccu8540.dts new file mode 100644 index 000000000000..48ff03441f5a --- /dev/null +++ b/arch/arm/boot/dts/ccu8540.dts @@ -0,0 +1,41 @@ +/* + * Copyright 2013 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "dbx5x0.dtsi" + +/ { + model = "ST-Ericsson U8540 platform with Device Tree"; + compatible = "st-ericsson,ccu8540", "st-ericsson,u8540"; + + memory@0 { + reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>; + }; + + soc { + prcmu@80157000 { + reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x3000>; + reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; + }; + + uart@80120000 { + status = "okay"; + }; + + uart@80121000 { + status = "okay"; + }; + + uart@80007000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/ccu9540.dts b/arch/arm/boot/dts/ccu9540.dts index 04305463f00d..ed29ec7288e4 100644 --- a/arch/arm/boot/dts/ccu9540.dts +++ b/arch/arm/boot/dts/ccu9540.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "dbx5x0.dtsi" +#include "dbx5x0.dtsi" / { model = "ST-Ericsson CCU9540 platform with Device Tree"; @@ -20,7 +20,7 @@ reg = <0x00000000 0x20000000>; }; - soc-u9500 { + soc { uart@80120000 { status = "okay"; }; @@ -52,7 +52,7 @@ // WLAN SDIO channel sdi1_per2@80118000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; + max-frequency = <100000000>; bus-width = <4>; status = "okay"; diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts index 422fdb3fcfc1..e750ab9086d5 100644 --- a/arch/arm/boot/dts/da850-enbw-cmc.dts +++ b/arch/arm/boot/dts/da850-enbw-cmc.dts @@ -10,7 +10,7 @@ * option) any later version. */ /dts-v1/; -/include/ "da850.dtsi" +#include "da850.dtsi" / { compatible = "enbw,cmc", "ti,da850"; diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index c914357c0d89..5bce7cc55cf3 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -8,7 +8,7 @@ * Free Software Foundation, version 2. */ /dts-v1/; -/include/ "da850.dtsi" +#include "da850.dtsi" / { compatible = "ti,da850-evm", "ti,da850"; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 2c88313d2c7a..d70ba5504481 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -7,7 +7,7 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { arm { @@ -37,7 +37,7 @@ #size-cells = <0>; pinctrl-single,bit-per-mux; pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; + pinctrl-single,function-mask = <0xf>; status = "disabled"; nand_cs3_pins: pinmux_nand_pins { diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index b6bc4ff17f26..a1529455f081 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -9,10 +9,11 @@ * http://www.gnu.org/copyleft/gpl.html */ -/include/ "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include "skeleton.dtsi" / { - soc-u9500 { + soc { #address-cells = <1>; #size-cells = <1>; compatible = "stericsson,db8500"; @@ -31,33 +32,33 @@ L2: l2-cache { compatible = "arm,pl310-cache"; reg = <0xa0412000 0x1000>; - interrupts = <0 13 4>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-level = <2>; }; pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 7 0x4>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; }; timer@a0410600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xa0410600 0x20>; - interrupts = <1 13 0x304>; + interrupts = <1 13 0x304>; /* IRQ level high per-CPU */ }; rtc@80154000 { compatible = "arm,rtc-pl031", "arm,primecell"; reg = <0x80154000 0x1000>; - interrupts = <0 18 0x4>; + interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; }; gpio0: gpio@8012e000 { compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8012e000 0x80>; - interrupts = <0 119 0x4>; + interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -70,7 +71,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8012e080 0x80>; - interrupts = <0 120 0x4>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -83,7 +84,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8000e000 0x80>; - interrupts = <0 121 0x4>; + interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -96,7 +97,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8000e080 0x80>; - interrupts = <0 122 0x4>; + interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -109,7 +110,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8000e100 0x80>; - interrupts = <0 123 0x4>; + interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -122,7 +123,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8000e180 0x80>; - interrupts = <0 124 0x4>; + interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -135,7 +136,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8011e000 0x80>; - interrupts = <0 125 0x4>; + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -148,7 +149,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8011e080 0x80>; - interrupts = <0 126 0x4>; + interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -161,7 +162,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0xa03fe000 0x80>; - interrupts = <0 127 0x4>; + interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -171,29 +172,61 @@ }; pinctrl { - compatible = "stericsson,nmk-pinctrl"; + compatible = "stericsson,db8500-pinctrl"; prcm = <&prcmu>; }; - usb@a03e0000 { + usb_per5@a03e0000 { compatible = "stericsson,db8500-musb", "mentor,musb"; reg = <0xa03e0000 0x10000>; - interrupts = <0 23 0x4>; - }; - - dma-controller@801C0000 { - compatible = "stericsson,db8500-dma40", - "stericsson,dma40"; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + + dr_mode = "otg"; + + dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ + <&dma 38 0 0x0>, /* Logical - MemToDev */ + <&dma 37 0 0x2>, /* Logical - DevToMem */ + <&dma 37 0 0x0>, /* Logical - MemToDev */ + <&dma 36 0 0x2>, /* Logical - DevToMem */ + <&dma 36 0 0x0>, /* Logical - MemToDev */ + <&dma 19 0 0x2>, /* Logical - DevToMem */ + <&dma 19 0 0x0>, /* Logical - MemToDev */ + <&dma 18 0 0x2>, /* Logical - DevToMem */ + <&dma 18 0 0x0>, /* Logical - MemToDev */ + <&dma 17 0 0x2>, /* Logical - DevToMem */ + <&dma 17 0 0x0>, /* Logical - MemToDev */ + <&dma 16 0 0x2>, /* Logical - DevToMem */ + <&dma 16 0 0x0>, /* Logical - MemToDev */ + <&dma 39 0 0x2>, /* Logical - DevToMem */ + <&dma 39 0 0x0>; /* Logical - MemToDev */ + + dma-names = "iep_1_9", "oep_1_9", + "iep_2_10", "oep_2_10", + "iep_3_11", "oep_3_11", + "iep_4_12", "oep_4_12", + "iep_5_13", "oep_5_13", + "iep_6_14", "oep_6_14", + "iep_7_15", "oep_7_15", + "iep_8", "oep_8"; + }; + + dma: dma-controller@801C0000 { + compatible = "stericsson,db8500-dma40", "stericsson,dma40"; reg = <0x801C0000 0x1000 0x40010000 0x800>; - interrupts = <0 25 0x4>; + reg-names = "base", "lcpa"; + interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; + + #dma-cells = <3>; + memcpy-channels = <56 57 58 59 60>; }; prcmu: prcmu@80157000 { compatible = "stericsson,db8500-prcmu"; reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; - interrupts = <0 47 0x4>; + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <1>; interrupt-controller; @@ -208,7 +241,8 @@ thermal@801573c0 { compatible = "stericsson,db8500-thermal"; reg = <0x801573c0 0x40>; - interrupts = <21 0x4>, <22 0x4>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, + <22 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; status = "disabled"; }; @@ -322,21 +356,26 @@ ab8500 { compatible = "stericsson,ab8500"; interrupt-parent = <&intc>; - interrupts = <0 40 0x4>; + interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; + ab8500_gpio: ab8500-gpio { + gpio-controller; + #gpio-cells = <2>; + }; + ab8500-rtc { compatible = "stericsson,ab8500-rtc"; - interrupts = <17 0x4 - 18 0x4>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH + 18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "60S", "ALARM"; }; ab8500-gpadc { compatible = "stericsson,ab8500-gpadc"; - interrupts = <32 0x4 - 39 0x4>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH + 39 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "HW_CONV_END", "SW_CONV_END"; vddadc-supply = <&ab8500_ldo_tvout_reg>; }; @@ -369,13 +408,13 @@ ab8500_usb { compatible = "stericsson,ab8500-usb"; - interrupts = < 90 0x4 - 96 0x4 - 14 0x4 - 15 0x4 - 79 0x4 - 74 0x4 - 75 0x4>; + interrupts = < 90 IRQ_TYPE_LEVEL_HIGH + 96 IRQ_TYPE_LEVEL_HIGH + 14 IRQ_TYPE_LEVEL_HIGH + 15 IRQ_TYPE_LEVEL_HIGH + 79 IRQ_TYPE_LEVEL_HIGH + 74 IRQ_TYPE_LEVEL_HIGH + 75 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ID_WAKEUP_R", "ID_WAKEUP_F", "VBUS_DET_F", @@ -383,15 +422,15 @@ "USB_LINK_STATUS", "USB_ADP_PROBE_PLUG", "USB_ADP_PROBE_UNPLUG"; - vddulpivio18-supply = <&ab8500_ldo_initcore_reg>; + vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; v-ape-supply = <&db8500_vape_reg>; musb_1v8-supply = <&db8500_vsmps2_reg>; }; ab8500-ponkey { compatible = "stericsson,ab8500-poweron-key"; - interrupts = <6 0x4 - 7 0x4>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH + 7 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; }; @@ -410,6 +449,11 @@ codec: ab8500-codec { compatible = "stericsson,ab8500-codec"; + V-AUD-supply = <&ab8500_ldo_audio_reg>; + V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; + V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; + V-DMIC-supply = <&ab8500_ldo_dmic_reg>; + stericsson,earpeice-cmv = <950>; /* Units in mV. */ }; @@ -441,8 +485,8 @@ }; // supply for v-intcore12; VINTCORE12 LDO - ab8500_ldo_initcore_reg: ab8500_ldo_initcore { - regulator-compatible = "ab8500_ldo_initcore"; + ab8500_ldo_intcore_reg: ab8500_ldo_intcore { + regulator-compatible = "ab8500_ldo_intcore"; }; // supply for tvout; gpadc; TVOUT LDO @@ -460,14 +504,14 @@ regulator-compatible = "ab8500_ldo_audio"; }; - // supply for v-anamic1 VAMic1-LDO + // supply for v-anamic1 VAMIC1 LDO ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { regulator-compatible = "ab8500_ldo_anamic1"; }; // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 - ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { - regulator-compatible = "ab8500_ldo_amamic2"; + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { + regulator-compatible = "ab8500_ldo_anamic2"; }; // supply for v-dmic; VDMIC LDO @@ -486,7 +530,7 @@ i2c@80004000 { compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80004000 0x1000>; - interrupts = <0 21 0x4>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; arm,primecell-periphid = <0x180024>; #address-cells = <1>; @@ -499,7 +543,7 @@ i2c@80122000 { compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80122000 0x1000>; - interrupts = <0 22 0x4>; + interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; arm,primecell-periphid = <0x180024>; #address-cells = <1>; @@ -512,7 +556,7 @@ i2c@80128000 { compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80128000 0x1000>; - interrupts = <0 55 0x4>; + interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; arm,primecell-periphid = <0x180024>; #address-cells = <1>; @@ -525,7 +569,7 @@ i2c@80110000 { compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80110000 0x1000>; - interrupts = <0 12 0x4>; + interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; arm,primecell-periphid = <0x180024>; #address-cells = <1>; @@ -538,7 +582,7 @@ i2c@8012a000 { compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x8012a000 0x1000>; - interrupts = <0 51 0x4>; + interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; arm,primecell-periphid = <0x180024>; #address-cells = <1>; @@ -551,82 +595,114 @@ ssp@80002000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x80002000 0x1000>; - interrupts = <0 14 0x4>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; - - // Add one of these for each child device - cs-gpios = <&gpio0 31 0x4 &gpio4 14 0x4 &gpio4 16 0x4 - &gpio6 22 0x4 &gpio7 0 0x4>; - }; uart@80120000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x80120000 0x1000>; - interrupts = <0 11 0x4>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ + <&dma 13 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + status = "disabled"; }; + uart@80121000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x80121000 0x1000>; - interrupts = <0 19 0x4>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ + <&dma 12 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + status = "disabled"; }; + uart@80007000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x80007000 0x1000>; - interrupts = <0 26 0x4>; + interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ + <&dma 11 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + status = "disabled"; }; sdi0_per1@80126000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80126000 0x1000>; - interrupts = <0 60 0x4>; + interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ + <&dma 29 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + status = "disabled"; }; sdi1_per2@80118000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80118000 0x1000>; - interrupts = <0 50 0x4>; + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ + <&dma 32 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + status = "disabled"; }; sdi2_per3@80005000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80005000 0x1000>; - interrupts = <0 41 0x4>; + interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ + <&dma 28 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + status = "disabled"; }; sdi3_per2@80119000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80119000 0x1000>; - interrupts = <0 59 0x4>; + interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; sdi4_per2@80114000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80114000 0x1000>; - interrupts = <0 99 0x4>; + interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ + <&dma 42 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + status = "disabled"; }; sdi5_per3@80008000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80008000 0x1000>; - interrupts = <0 100 0x4>; + interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; msp0: msp@80123000 { compatible = "stericsson,ux500-msp-i2s"; reg = <0x80123000 0x1000>; - interrupts = <0 31 0x4>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; status = "disabled"; }; @@ -634,7 +710,7 @@ msp1: msp@80124000 { compatible = "stericsson,ux500-msp-i2s"; reg = <0x80124000 0x1000>; - interrupts = <0 62 0x4>; + interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; status = "disabled"; }; @@ -643,7 +719,7 @@ msp2: msp@80117000 { compatible = "stericsson,ux500-msp-i2s"; reg = <0x80117000 0x1000>; - interrupts = <0 98 0x4>; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; status = "disabled"; }; @@ -651,7 +727,7 @@ msp3: msp@80125000 { compatible = "stericsson,ux500-msp-i2s"; reg = <0x80125000 0x1000>; - interrupts = <0 62 0x4>; + interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; status = "disabled"; }; @@ -686,5 +762,20 @@ status = "disabled"; }; + + cryp@a03cb000 { + compatible = "stericsson,ux500-cryp"; + reg = <0xa03cb000 0x1000>; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; + + v-ape-supply = <&db8500_vape_reg>; + }; + + hash@a03c2000 { + compatible = "stericsson,ux500-hash"; + reg = <0xa03c2000 0x1000>; + + v-ape-supply = <&db8500_vape_reg>; + }; }; }; diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 7e3065abd751..5cae2ab69762 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -44,11 +44,60 @@ gpio = <&gpio0 1 0>; }; }; + + clocks { + /* 25MHz reference crystal */ + ref25: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + }; }; &uart0 { status = "okay"; }; &sata0 { status = "okay"; }; -&i2c0 { status = "okay"; }; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + si5351: clock-generator { + compatible = "silabs,si5351a-msop"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + /* connect xtal input to 25MHz reference */ + clocks = <&ref25>; + + /* connect xtal input as source of pll0 and pll1 */ + silabs,pll-source = <0 0>, <1 0>; + + clkout0 { + reg = <0>; + silabs,drive-strength = <8>; + silabs,multisynth-source = <0>; + silabs,clock-source = <0>; + silabs,pll-master; + }; + + clkout1 { + reg = <1>; + silabs,drive-strength = <8>; + silabs,multisynth-source = <1>; + silabs,clock-source = <0>; + silabs,pll-master; + }; + + clkout2 { + reg = <2>; + silabs,multisynth-source = <1>; + silabs,clock-source = <0>; + }; + }; +}; &sdio0 { status = "okay"; diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts index 1ea9d34460a4..143b6d25bc80 100644 --- a/arch/arm/boot/dts/ethernut5.dts +++ b/arch/arm/boot/dts/ethernut5.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ /dts-v1/; -/include/ "at91sam9260.dtsi" +#include "at91sam9260.dtsi" / { model = "Ethernut 5"; @@ -40,7 +40,7 @@ }; usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 0>; + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; }; @@ -52,7 +52,7 @@ status = "okay"; gpios = <0 - &pioC 14 0 + &pioC 14 GPIO_ACTIVE_HIGH 0 >; diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts index 96e50f569433..4d829685fdfb 100644 --- a/arch/arm/boot/dts/evk-pro3.dts +++ b/arch/arm/boot/dts/evk-pro3.dts @@ -9,7 +9,7 @@ /dts-v1/; -/include/ "ge863-pro3.dtsi" +#include "ge863-pro3.dtsi" / { model = "Telit EVK-PRO3 for Telit GE863-PRO3"; @@ -31,7 +31,7 @@ }; usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 0>; + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -50,4 +50,4 @@ status = "okay"; }; -};
\ No newline at end of file +}; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 359694c78918..3f94fe8e3706 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -19,7 +19,7 @@ * published by the Free Software Foundation. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { interrupt-parent = <&gic>; @@ -160,6 +160,8 @@ reg = <0x13400000 0x10000>; interrupts = <0 94 0>; samsung,power-domain = <&pd_mfc>; + clocks = <&clock 170>, <&clock 273>; + clock-names = "sclk_mfc", "mfc"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 524b90846df5..382d8c7e2906 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -15,7 +15,7 @@ */ /dts-v1/; -/include/ "exynos4210.dtsi" +#include "exynos4210.dtsi" / { model = "Insignal Origen evaluation board based on Exynos4210"; @@ -41,6 +41,10 @@ enable-active-high; }; + tmu@100C0000 { + status = "okay"; + }; + sdhci@12530000 { bus-width = <4>; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; @@ -83,6 +87,150 @@ status = "okay"; }; + i2c@13860000 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + pinctrl-0 = <&i2c0_bus>; + pinctrl-names = "default"; + + max8997_pmic@66 { + compatible = "maxim,max8997-pmic"; + reg = <0x66>; + interrupt-parent = <&gpx0>; + interrupts = <4 0>, <3 0>; + + max8997,pmic-buck1-dvs-voltage = <1350000>; + max8997,pmic-buck2-dvs-voltage = <1100000>; + max8997,pmic-buck5-dvs-voltage = <1200000>; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ABB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDD_ALIVE_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "VMIPI_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDD_RTC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD_AUD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "VADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo9_reg: LDO9 { + regulator-name = "DVDD_SWB_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "VDD_PLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD_AUD_3V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo14_reg: LDO14 { + regulator-name = "AVDD18_SWB_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "VDD_SWB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo21_reg: LDO21 { + regulator-name = "VDD_MIF_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "VDD_ARM_1.2V"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_INT_1.1V"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_G3D_1.1V"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDDQ_M1M2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "VDD_LCD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + }; + gpio_keys { compatible = "gpio-keys"; #address-cells = <1>; @@ -143,4 +291,25 @@ clock-frequency = <24000000>; }; }; + + fimd@11c00000 { + pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>; + pinctrl-names = "default"; + status = "okay"; + }; + + display-timings { + native-mode = <&timing0>; + timing0: timing { + clock-frequency = <50000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <64>; + hback-porch = <16>; + hsync-len = <48>; + vback-porch = <64>; + vfront-porch = <16>; + vsync-len = <3>; + }; + }; }; diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index 55a2efb763d1..553bceae8967 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -330,6 +330,95 @@ samsung,pin-pud = <3>; samsung,pin-drv = <0>; }; + + pwm0_out: pwm0-out { + samsung,pins = "gpd0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpd0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm2_out: pwm2-out { + samsung,pins = "gpd0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm3_out: pwm3-out { + samsung,pins = "gpd0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + lcd_ctrl: lcd-ctrl { + samsung,pins = "gpd0-0", "gpd0-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + lcd_sync: lcd-sync { + samsung,pins = "gpf0-0", "gpf0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + lcd_en: lcd-en { + samsung,pins = "gpe3-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + lcd_clk: lcd-clk { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + lcd_data16: lcd-data-width16 { + samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", + "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", + "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + lcd_data18: lcd-data-width18 { + samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", + "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", + "gpf3-2", "gpf3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + lcd_data24: lcd-data-width24 { + samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", + "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; }; pinctrl@11000000 { diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 91332b72acf5..9c01b718d29d 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -15,7 +15,7 @@ */ /dts-v1/; -/include/ "exynos4210.dtsi" +#include "exynos4210.dtsi" / { model = "Samsung smdkv310 evaluation board based on Exynos4210"; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 9a14484c7bb1..94eebffe3044 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -13,7 +13,7 @@ */ /dts-v1/; -/include/ "exynos4210.dtsi" +#include "exynos4210.dtsi" / { model = "Samsung Trats based on Exynos4210"; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 345cdb51dcb7..889cdada1ce9 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -13,7 +13,7 @@ */ /dts-v1/; -/include/ "exynos4210.dtsi" +#include "exynos4210.dtsi" / { model = "Samsung Universal C210 based on Exynos4210 rev0"; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 54710de82908..b7f358a93bcb 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -19,8 +19,8 @@ * published by the Free Software Foundation. */ -/include/ "exynos4.dtsi" -/include/ "exynos4210-pinctrl.dtsi" +#include "exynos4.dtsi" +#include "exynos4210-pinctrl.dtsi" / { compatible = "samsung,exynos4210"; @@ -112,12 +112,17 @@ interrupt-parent = <&combiner>; reg = <0x100C0000 0x100>; interrupts = <2 4>; + clocks = <&clock 383>; + clock-names = "tmu_apbif"; + status = "disabled"; }; g2d@12800000 { compatible = "samsung,s5pv210-g2d"; reg = <0x12800000 0x1000>; interrupts = <0 89 0>; + clocks = <&clock 177>, <&clock 277>; + clock-names = "sclk_fimg2d", "fimg2d"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index c0f60f49cea6..6f34d7f6ba7e 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -17,7 +17,7 @@ * published by the Free Software Foundation. */ -/include/ "exynos4x12.dtsi" +#include "exynos4x12.dtsi" / { compatible = "samsung,exynos4212"; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 53bc8bf77984..46c678ee119c 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -12,7 +12,7 @@ */ /dts-v1/; -/include/ "exynos4412.dtsi" +#include "exynos4412.dtsi" / { model = "Hardkernel ODROID-X board based on Exynos4412"; @@ -43,6 +43,7 @@ #size-cells = <0>; pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; pinctrl-names = "default"; + vmmc-supply = <&ldo20_reg &buck8_reg>; status = "okay"; num-slots = <1>; @@ -78,6 +79,7 @@ bus-width = <4>; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; pinctrl-names = "default"; + vmmc-supply = <&ldo4_reg &ldo21_reg>; status = "okay"; }; @@ -108,4 +110,199 @@ clock-frequency = <24000000>; }; }; + + i2c@13860000 { + pinctrl-0 = <&i2c0_bus>; + pinctrl-names = "default"; + status = "okay"; + + max77686: pmic@09 { + compatible = "maxim,max77686"; + reg = <0x09>; + + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDDQ_M1_2_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "VDDQ_EXT_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDDQ_MMC2_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "VDDQ_MMC1_3_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD10_MPLL_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD10_XPLL_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD18_ABB1_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD33_USB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "VDDQ_C2C_W_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD18_ABB0_2_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD10_HSIC_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD18_HSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo20_reg: LDO20 { + regulator-name = "LDO20_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + ldo21_reg: LDO21 { + regulator-name = "LDO21_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo25_reg: LDO25 { + regulator-name = "VDDQ_LCD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-microvolt-offset = <50000>; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDDQ_CKEM1_2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "BUCK6_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "BUCK7_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "BUCK8_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 1c21bad32ca9..7993641cb32a 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -13,7 +13,7 @@ */ /dts-v1/; -/include/ "exynos4412.dtsi" +#include "exynos4412.dtsi" / { model = "Insignal Origen evaluation board based on Exynos4412"; @@ -36,6 +36,72 @@ enable-active-high; }; + pinctrl@11000000 { + keypad_rows: keypad-rows { + samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + keypad_cols: keypad-cols { + samsung,pins = "gpx1-0", "gpx1-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; + + keypad@100A0000 { + samsung,keypad-num-rows = <3>; + samsung,keypad-num-columns = <2>; + linux,keypad-no-autorepeat; + linux,keypad-wakeup; + pinctrl-0 = <&keypad_rows &keypad_cols>; + pinctrl-names = "default"; + status = "okay"; + + key_home { + keypad,row = <0>; + keypad,column = <0>; + linux,code = <102>; + }; + + key_down { + keypad,row = <0>; + keypad,column = <1>; + linux,code = <108>; + }; + + key_up { + keypad,row = <1>; + keypad,column = <0>; + linux,code = <103>; + }; + + key_menu { + keypad,row = <1>; + keypad,column = <1>; + linux,code = <139>; + }; + + key_back { + keypad,row = <2>; + keypad,column = <0>; + linux,code = <158>; + }; + + key_enter { + keypad,row = <2>; + keypad,column = <1>; + linux,code = <28>; + }; + }; + + g2d@10800000 { + status = "okay"; + }; + sdhci@12530000 { bus-width = <4>; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index dd564310d4a5..ad316a1ee9e0 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -13,7 +13,7 @@ */ /dts-v1/; -/include/ "exynos4412.dtsi" +#include "exynos4412.dtsi" / { model = "Samsung SMDK evaluation board based on Exynos4412"; @@ -31,8 +31,91 @@ status = "okay"; }; - g2d@10800000 { + pinctrl@11000000 { + keypad_rows: keypad-rows { + samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + keypad_cols: keypad-cols { + samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", + "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; + + keypad@100A0000 { + samsung,keypad-num-rows = <3>; + samsung,keypad-num-columns = <8>; + linux,keypad-no-autorepeat; + linux,keypad-wakeup; + pinctrl-0 = <&keypad_rows &keypad_cols>; + pinctrl-names = "default"; status = "okay"; + + key_1 { + keypad,row = <1>; + keypad,column = <3>; + linux,code = <2>; + }; + + key_2 { + keypad,row = <1>; + keypad,column = <4>; + linux,code = <3>; + }; + + key_3 { + keypad,row = <1>; + keypad,column = <5>; + linux,code = <4>; + }; + + key_4 { + keypad,row = <1>; + keypad,column = <6>; + linux,code = <5>; + }; + + key_5 { + keypad,row = <1>; + keypad,column = <7>; + linux,code = <6>; + }; + + key_A { + keypad,row = <2>; + keypad,column = <6>; + linux,code = <30>; + }; + + key_B { + keypad,row = <2>; + keypad,column = <7>; + linux,code = <48>; + }; + + key_C { + keypad,row = <0>; + keypad,column = <5>; + linux,code = <46>; + }; + + key_D { + keypad,row = <2>; + keypad,column = <5>; + linux,code = <32>; + }; + + key_E { + keypad,row = <0>; + keypad,column = <7>; + linux,code = <18>; + }; }; sdhci@12530000 { diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 270b389e0a1b..e743e677a9e2 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -17,7 +17,7 @@ * published by the Free Software Foundation. */ -/include/ "exynos4x12.dtsi" +#include "exynos4x12.dtsi" / { compatible = "samsung,exynos4412"; diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index 099cec79e2ae..704290f7c5c0 100644 --- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi @@ -778,62 +778,6 @@ samsung,pin-drv = <3>; }; - keypad_col0: keypad-col0 { - samsung,pins = "gpl2-0"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - keypad_col1: keypad-col1 { - samsung,pins = "gpl2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - keypad_col2: keypad-col2 { - samsung,pins = "gpl2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - keypad_col3: keypad-col3 { - samsung,pins = "gpl2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - keypad_col4: keypad-col4 { - samsung,pins = "gpl2-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - keypad_col5: keypad-col5 { - samsung,pins = "gpl2-5"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - keypad_col6: keypad-col6 { - samsung,pins = "gpl2-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - keypad_col7: keypad-col7 { - samsung,pins = "gpl2-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - cam_port_b: cam-port-b { samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index e3380a7a285c..01da194ba329 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -17,8 +17,8 @@ * published by the Free Software Foundation. */ -/include/ "exynos4.dtsi" -/include/ "exynos4x12-pinctrl.dtsi" +#include "exynos4.dtsi" +#include "exynos4x12-pinctrl.dtsi" / { aliases { @@ -28,14 +28,6 @@ pinctrl3 = &pinctrl_3; }; - combiner:interrupt-controller@10440000 { - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>; - }; - clock: clock-controller@0x10030000 { compatible = "samsung,exynos4412-clock"; reg = <0x10030000 0x20000>; @@ -77,6 +69,8 @@ compatible = "samsung,exynos4212-g2d"; reg = <0x10800000 0x1000>; interrupts = <0 89 0>; + clocks = <&clock 177>, <&clock 277>; + clock-names = "sclk_fimg2d", "fimg2d"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi new file mode 100644 index 000000000000..f65e124c04a6 --- /dev/null +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -0,0 +1,111 @@ +/* + * Samsung's Exynos5 SoC series common device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular + * SoCs from Exynos5 series can include this file and provide values for SoCs + * specfic bindings. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + combiner:interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + samsung,combiner-nr = <32>; + reg = <0x10440000 0x1000>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, + <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, + <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + }; + + gic:interrupt-controller@10481000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x1000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + dwmmc_0: dwmmc0@12200000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 75 0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + dwmmc_1: dwmmc1@12210000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 76 0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + dwmmc_2: dwmmc2@12220000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + serial@12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 51 0>; + }; + + serial@12C10000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C10000 0x100>; + interrupts = <0 52 0>; + }; + + serial@12C20000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C20000 0x100>; + interrupts = <0 53 0>; + }; + + serial@12C30000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C30000 0x100>; + interrupts = <0 54 0>; + }; + + rtc { + compatible = "samsung,s3c6410-rtc"; + reg = <0x101E0000 0x100>; + interrupts = <0 43 0>, <0 44 0>; + status = "disabled"; + }; + + watchdog { + compatible = "samsung,s3c2410-wdt"; + reg = <0x101D0000 0x100>; + interrupts = <0 42 0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 02cfc76d002f..abc7272c7afd 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "exynos5250.dtsi" +#include "exynos5250.dtsi" / { model = "Insignal Arndale evaluation board based on EXYNOS5250"; @@ -449,4 +449,35 @@ clock-frequency = <24000000>; }; }; + + dp-controller { + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <4>; + }; + + fimd: fimd@14400000 { + display-timings { + native-mode = <&timing0>; + timing0: timing@0 { + /* 2560x1600 DP panel */ + clock-frequency = <50000>; + hactive = <2560>; + vactive = <1600>; + hfront-porch = <48>; + hback-porch = <80>; + hsync-len = <32>; + vback-porch = <16>; + vfront-porch = <8>; + vsync-len = <6>; + }; + }; + }; + + rtc { + status = "okay"; + }; }; diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index d1650fb34c0a..724a22f9b1c8 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -553,6 +553,13 @@ samsung,pin-pud = <0>; samaung,pin-drv = <0>; }; + + dp_hpd: dp_hpd { + samsung,pins = "gpx0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samaung,pin-drv = <0>; + }; }; pinctrl@13400000 { @@ -763,7 +770,7 @@ }; }; - pinctrl@03680000 { + pinctrl@03860000 { gpz: gpz { gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 3e0c792e2767..35a66dee4011 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "exynos5250.dtsi" +#include "exynos5250.dtsi" / { model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; @@ -37,6 +37,30 @@ }; }; + vdd:fixed-regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + dbvdd:fixed-regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "dbvdd-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + spkvdd:fixed-regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "spkvdd-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + i2c@12C70000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <20000>; @@ -47,8 +71,17 @@ }; wm8994: wm8994@1a { - compatible = "wlf,wm8994"; - reg = <0x1a>; + compatible = "wlf,wm8994"; + reg = <0x1a>; + + gpio-controller; + #gpio-cells = <2>; + + AVDD2-supply = <&vdd>; + CPVDD-supply = <&vdd>; + DBVDD-supply = <&dbvdd>; + SPKVDD1-supply = <&spkvdd>; + SPKVDD2-supply = <&spkvdd>; }; }; @@ -224,6 +257,9 @@ samsung,color-depth = <1>; samsung,link-rate = <0x0a>; samsung,lane-count = <4>; + + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd>; }; display-timings { diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index d449feb7e143..e79331dba12d 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -9,8 +9,8 @@ */ /dts-v1/; -/include/ "exynos5250.dtsi" -/include/ "cros5250-common.dtsi" +#include "exynos5250.dtsi" +#include "cros5250-common.dtsi" / { model = "Google Snow"; @@ -171,6 +171,10 @@ }; }; + rtc { + status = "okay"; + }; + /* * On Snow we've got SIP WiFi and so can keep drive strengths low to * reduce EMI. diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 98dfc3ea5c0b..41cd625b6020 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -17,12 +17,13 @@ * published by the Free Software Foundation. */ -/include/ "skeleton.dtsi" -/include/ "exynos5250-pinctrl.dtsi" +#include "exynos5.dtsi" +#include "exynos5250-pinctrl.dtsi" + +#include <dt-bindings/clk/exynos-audss-clk.h> / { compatible = "samsung,exynos5250"; - interrupt-parent = <&gic>; aliases { spi0 = &spi_0; @@ -51,9 +52,20 @@ pinctrl3 = &pinctrl_3; }; - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; }; pd_gsc: gsc-power-domain@0x10044000 { @@ -72,15 +84,10 @@ #clock-cells = <1>; }; - gic:interrupt-controller@10481000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x1000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; + clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5250-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; }; timer { @@ -91,22 +98,6 @@ <1 10 0xf08>; }; - combiner:interrupt-controller@10440000 { - compatible = "samsung,exynos4210-combiner"; - #interrupt-cells = <2>; - interrupt-controller; - samsung,combiner-nr = <32>; - reg = <0x10440000 0x1000>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, - <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; - }; - mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; @@ -161,16 +152,13 @@ interrupts = <0 50 0>; }; - pinctrl_3: pinctrl@03680000 { + pinctrl_3: pinctrl@03860000 { compatible = "samsung,exynos5250-pinctrl"; - reg = <0x0368000 0x1000>; + reg = <0x03860000 0x1000>; interrupts = <0 47 0>; }; watchdog { - compatible = "samsung,s3c2410-wdt"; - reg = <0x101D0000 0x100>; - interrupts = <0 42 0>; clocks = <&clock 336>; clock-names = "watchdog"; }; @@ -183,12 +171,8 @@ }; rtc { - compatible = "samsung,s3c6410-rtc"; - reg = <0x101E0000 0x100>; - interrupts = <0 43 0>, <0 44 0>; clocks = <&clock 337>; clock-names = "rtc"; - status = "disabled"; }; tmu@10060000 { @@ -200,33 +184,21 @@ }; serial@12C00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = <0 51 0>; clocks = <&clock 289>, <&clock 146>; clock-names = "uart", "clk_uart_baud0"; }; serial@12C10000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C10000 0x100>; - interrupts = <0 52 0>; clocks = <&clock 290>, <&clock 147>; clock-names = "uart", "clk_uart_baud0"; }; serial@12C20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C20000 0x100>; - interrupts = <0 53 0>; clocks = <&clock 291>, <&clock 148>; clock-names = "uart", "clk_uart_baud0"; }; serial@12C30000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C30000 0x100>; - interrupts = <0 54 0>; clocks = <&clock 292>, <&clock 149>; clock-names = "uart", "clk_uart_baud0"; }; @@ -405,31 +377,19 @@ }; dwmmc_0: dwmmc0@12200000 { - compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12200000 0x1000>; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; clocks = <&clock 280>, <&clock 139>; clock-names = "biu", "ciu"; }; dwmmc_1: dwmmc1@12210000 { - compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12210000 0x1000>; - interrupts = <0 76 0>; - #address-cells = <1>; - #size-cells = <0>; clocks = <&clock 281>, <&clock 140>; clock-names = "biu", "ciu"; }; dwmmc_2: dwmmc2@12220000 { - compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12220000 0x1000>; - interrupts = <0 77 0>; - #address-cells = <1>; - #size-cells = <0>; clocks = <&clock 282>, <&clock 141>; clock-names = "biu", "ciu"; }; @@ -451,6 +411,10 @@ &pdma0 9 &pdma0 8>; dma-names = "tx", "rx", "tx-sec"; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; samsung,supports-6ch; samsung,supports-rstclr; samsung,supports-secdai; @@ -465,6 +429,8 @@ dmas = <&pdma1 12 &pdma1 11>; dma-names = "tx", "rx"; + clocks = <&clock 307>, <&clock 157>; + clock-names = "iis", "i2s_opclk0"; pinctrl-names = "default"; pinctrl-0 = <&i2s1_bus>; }; @@ -475,10 +441,42 @@ dmas = <&pdma0 12 &pdma0 11>; dma-names = "tx", "rx"; + clocks = <&clock 308>, <&clock 158>; + clock-names = "iis", "i2s_opclk0"; pinctrl-names = "default"; pinctrl-0 = <&i2s2_bus>; }; + usb@12000000 { + compatible = "samsung,exynos5250-dwusb3"; + clocks = <&clock 286>; + clock-names = "usbdrd30"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dwc3 { + compatible = "synopsys,dwc3"; + reg = <0x12000000 0x10000>; + interrupts = <0 72 0>; + usb-phy = <&usb2_phy &usb3_phy>; + }; + }; + + usb3_phy: usbphy@12100000 { + compatible = "samsung,exynos5250-usb3phy"; + reg = <0x12100000 0x100>; + clocks = <&clock 1>, <&clock 286>; + clock-names = "ext_xtal", "usbdrd30"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbphy-sys { + reg = <0x10040704 0x8>; + }; + }; + usb@12110000 { compatible = "samsung,exynos4210-ehci"; reg = <0x12110000 0x100>; @@ -497,6 +495,21 @@ clock-names = "usbhost"; }; + usb2_phy: usbphy@12130000 { + compatible = "samsung,exynos5250-usb2phy"; + reg = <0x12130000 0x100>; + clocks = <&clock 1>, <&clock 285>; + clock-names = "ext_xtal", "usbhost"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbphy-sys { + reg = <0x10040704 0x8>, + <0x10050230 0x4>; + }; + }; + amba { #address-cells = <1>; #size-cells = <1>; @@ -606,6 +619,8 @@ reg = <0x145b0000 0x1000>; interrupts = <10 3>; interrupt-parent = <&combiner>; + clocks = <&clock 342>; + clock-names = "dp"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi new file mode 100644 index 000000000000..5848c425ae4d --- /dev/null +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -0,0 +1,680 @@ +/* + * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + pinctrl@13400000 { + gpy7: gpy7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <23 0>, <24 0>, <25 0>, <25 1>, + <26 0>, <26 1>, <27 0>, <27 1>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <28 0>, <28 1>, <29 0>, <29 1>, + <30 0>, <30 1>, <31 0>, <31 1>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pinctrl@13410000 { + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpc0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpc0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpc0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpc0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpc1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpc1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpc1-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_int: sd1-int { + samsung,pins = "gpd1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpc1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus8: sd1-bus-width8 { + samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpc2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpc2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpc2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpc2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + }; + + pinctrl@14000000 { + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj4: gpj4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + cam_gpio_a: cam-gpio-a { + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", + "gpe1-0", "gpe1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_gpio_b: cam-gpio-b { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_i2c2_bus: cam-i2c2-bus { + samsung,pins = "gpf0-4", "gpf0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + cam_spi1_bus: cam-spi1-bus { + samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_i2c1_bus: cam-i2c1-bus { + samsung,pins = "gpf0-2", "gpf0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_i2c0_bus: cam-i2c0-bus { + samsung,pins = "gpf0-0", "gpf0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_spi0_bus: cam-spi0-bus { + samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_bayrgb_bus: cam-bayrgb-bus { + samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", + "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", + "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", + "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", + "gpg2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl@14010000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb4: gpb4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph0: gph0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart3_data: uart3-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c4_hs_bus: i2c4-hs-bus { + samsung,pins = "gpa2-0", "gpa2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c5_hs_bus: i2c5-hs-bus { + samsung,pins = "gpa2-2", "gpa2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2s2_bus: i2s2-bus { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", + "gpb1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm2_bus: pcm2-bus { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", + "gpb1-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spdif_bus: spdif-bus { + samsung,pins = "gpb1-0", "gpb1-1"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; + samsung,pin-function = <5>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c6_hs_bus: i2c6-hs-bus { + samsung,pins = "gpb1-3", "gpb1-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c7_hs_bus: i2c7-hs-bus { + samsung,pins = "gpb2-2", "gpb2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c8_hs_bus: i2c8-hs-bus { + samsung,pins = "gpb3-4", "gpb3-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c9_hs_bus: i2c9-hs-bus { + samsung,pins = "gpb3-6", "gpb3-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c10_hs_bus: i2c10-hs-bus { + samsung,pins = "gpb4-0", "gpb4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl@03860000 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4", "gpz-5", "gpz-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts new file mode 100644 index 000000000000..08607df6a180 --- /dev/null +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -0,0 +1,33 @@ +/* + * SAMSUNG SMDK5420 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos5420.dtsi" + +/ { + model = "Samsung SMDK5420 board based on EXYNOS5420"; + compatible = "samsung,smdk5420", "samsung,exynos5420"; + + memory { + reg = <0x20000000 0x80000000>; + }; + + chosen { + bootargs = "console=ttySAC2,115200 init=/linuxrc"; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi new file mode 100644 index 000000000000..8c54c4b74f0e --- /dev/null +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -0,0 +1,148 @@ +/* + * SAMSUNG EXYNOS5420 SoC device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. + * EXYNOS5420 based board files can include this file and provide + * values for board specfic bindings. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "exynos5.dtsi" +/include/ "exynos5420-pinctrl.dtsi" +/ { + compatible = "samsung,exynos5420"; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + pinctrl4 = &pinctrl_4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + clock-frequency = <1800000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + clock-frequency = <1800000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + clock-frequency = <1800000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + clock-frequency = <1800000000>; + }; + }; + + clock: clock-controller@0x10010000 { + compatible = "samsung,exynos5420-clock"; + reg = <0x10010000 0x30000>; + #clock-cells = <1>; + }; + + mct@101C0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x101C0000 0x800>; + interrupt-controller; + #interrups-cells = <1>; + interrupt-parent = <&mct_map>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>; + clocks = <&clock 1>, <&clock 315>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &combiner 23 3>, + <1 &combiner 23 4>, + <2 &combiner 25 2>, + <3 &combiner 25 3>, + <4 &gic 0 120 0>, + <5 &gic 0 121 0>, + <6 &gic 0 122 0>, + <7 &gic 0 123 0>; + }; + }; + + pinctrl_0: pinctrl@13400000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x13400000 0x1000>; + interrupts = <0 45 0>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; + }; + + pinctrl_1: pinctrl@13410000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x13410000 0x1000>; + interrupts = <0 78 0>; + }; + + pinctrl_2: pinctrl@14000000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x14000000 0x1000>; + interrupts = <0 46 0>; + }; + + pinctrl_3: pinctrl@14010000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x14010000 0x1000>; + interrupts = <0 50 0>; + }; + + pinctrl_4: pinctrl@03860000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x03860000 0x1000>; + interrupts = <0 47 0>; + }; + + serial@12C00000 { + clocks = <&clock 257>, <&clock 128>; + clock-names = "uart", "clk_uart_baud0"; + }; + + serial@12C10000 { + clocks = <&clock 258>, <&clock 129>; + clock-names = "uart", "clk_uart_baud0"; + }; + + serial@12C20000 { + clocks = <&clock 259>, <&clock 130>; + clock-names = "uart", "clk_uart_baud0"; + }; + + serial@12C30000 { + clocks = <&clock 260>, <&clock 131>; + clock-names = "uart", "clk_uart_baud0"; + }; +}; diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts index ef747b52b674..5b22508050da 100644 --- a/arch/arm/boot/dts/exynos5440-sd5v1.dts +++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts @@ -10,14 +10,14 @@ */ /dts-v1/; -/include/ "exynos5440.dtsi" +#include "exynos5440.dtsi" / { model = "SAMSUNG SD5v1 board based on EXYNOS5440"; compatible = "samsung,sd5v1", "samsung,exynos5440"; chosen { - bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200"; + bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; }; fixed-rate-clocks { diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts index d55042beb5c5..ede772741f81 100644 --- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts @@ -10,18 +10,53 @@ */ /dts-v1/; -/include/ "exynos5440.dtsi" +#include "exynos5440.dtsi" / { model = "SAMSUNG SSDK5440 board based on EXYNOS5440"; compatible = "samsung,ssdk5440", "samsung,exynos5440"; chosen { - bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200"; + bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; }; - spi { - status = "disabled"; + spi_0: spi@D0000 { + + flash: w25q128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128"; + spi-max-frequency = <15625000>; + reg = <0>; + controller-data { + samsung,spi-feedback-delay = <0>; + }; + + partition@00000 { + label = "BootLoader"; + reg = <0x60000 0x80000>; + read-only; + }; + + partition@e0000 { + label = "Recovery-Kernel"; + reg = <0xe0000 0x300000>; + read-only; + }; + + partition@3e0000 { + label = "CRAM-FS"; + reg = <0x3e0000 0x700000>; + read-only; + }; + + partition@ae0000 { + label = "User-Data"; + reg = <0xae0000 0x520000>; + }; + + }; + }; fixed-rate-clocks { @@ -30,4 +65,12 @@ clock-frequency = <50000000>; }; }; + + pcie@290000 { + reset-gpio = <&pin_ctrl 5 0>; + }; + + pcie@2a0000 { + reset-gpio = <&pin_ctrl 22 0>; + }; }; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index f6b1c8973845..ff7f5d855845 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -9,13 +9,17 @@ * published by the Free Software Foundation. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { compatible = "samsung,exynos5440"; interrupt-parent = <&gic>; + aliases { + spi0 = &spi_0; + }; + clock: clock-controller@0x160000 { compatible = "samsung,exynos5440-clock"; reg = <0x160000 0x1000>; @@ -38,18 +42,22 @@ #size-cells = <0>; cpu@0 { + device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; }; cpu@1 { + device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; }; cpu@2 { + device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <2>; }; cpu@3 { + device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <3>; }; @@ -79,8 +87,13 @@ interrupts = <0 57 0>; operating-points = < /* KHz uV */ + 1500000 1100000 + 1400000 1075000 + 1300000 1050000 1200000 1025000 + 1100000 1000000 1000000 975000 + 900000 950000 800000 925000 >; }; @@ -101,19 +114,19 @@ clock-names = "uart", "clk_uart_baud0"; }; - spi { - compatible = "samsung,exynos4210-spi"; - reg = <0xD0000 0x1000>; + spi_0: spi@D0000 { + compatible = "samsung,exynos5440-spi"; + reg = <0xD0000 0x100>; interrupts = <0 4 0>; - tx-dma-channel = <&pdma0 5>; /* preliminary */ - rx-dma-channel = <&pdma0 4>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; + samsung,spi-src-clk = <0>; + num-cs = <1>; clocks = <&clock 21>, <&clock 16>; clock-names = "spi", "spi_busclk0"; }; - pinctrl { + pin_ctrl: pinctrl { compatible = "samsung,exynos5440-pinctrl"; reg = <0xE0000 0x1000>; interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, @@ -184,28 +197,6 @@ compatible = "arm,amba-bus"; interrupt-parent = <&gic>; ranges; - - pdma0: pdma@00121000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121000 0x1000>; - interrupts = <0 46 0>; - clocks = <&clock 8>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@00120000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x120000 0x1000>; - interrupts = <0 47 0>; - clocks = <&clock 8>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; }; rtc { @@ -214,6 +205,67 @@ interrupts = <0 17 0>, <0 16 0>; clocks = <&clock 21>; clock-names = "rtc"; - status = "disabled"; + }; + + sata@210000 { + compatible = "snps,exynos5440-ahci"; + reg = <0x210000 0x10000>; + interrupts = <0 30 0>; + clocks = <&clock 23>; + clock-names = "sata"; + }; + + ohci@220000 { + compatible = "samsung,exynos5440-ohci"; + reg = <0x220000 0x1000>; + interrupts = <0 29 0>; + clocks = <&clock 24>; + clock-names = "usbhost"; + }; + + ehci@221000 { + compatible = "samsung,exynos5440-ehci"; + reg = <0x221000 0x1000>; + interrupts = <0 29 0>; + clocks = <&clock 24>; + clock-names = "usbhost"; + }; + + pcie@290000 { + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; + reg = <0x290000 0x1000 + 0x270000 0x1000 + 0x271000 0x40>; + interrupts = <0 20 0>, <0 21 0>, <0 22 0>; + clocks = <&clock 28>, <&clock 27>; + clock-names = "pcie", "pcie_bus"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ + 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 53>; + }; + + pcie@2a0000 { + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; + reg = <0x2a0000 0x1000 + 0x272000 0x1000 + 0x271040 0x40>; + interrupts = <0 23 0>, <0 24 0>, <0 25 0>; + clocks = <&clock 29>, <&clock 27>; + clock-names = "pcie", "pcie_bus"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ + 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 56>; }; }; diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi index 17136fc7a516..230099bb31c8 100644 --- a/arch/arm/boot/dts/ge863-pro3.dtsi +++ b/arch/arm/boot/dts/ge863-pro3.dtsi @@ -7,7 +7,7 @@ * Licensed under GPLv2 or later. */ -/include/ "at91sam9260.dtsi" +#include "at91sam9260.dtsi" / { clocks { diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi index c0bc426952ea..9db41b9d8358 100644 --- a/arch/arm/boot/dts/href.dtsi +++ b/arch/arm/boot/dts/href.dtsi @@ -9,7 +9,8 @@ * http://www.gnu.org/copyleft/gpl.html */ -/include/ "dbx5x0.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include "dbx5x0.dtsi" / { memory { @@ -27,7 +28,7 @@ }; }; - soc-u9500 { + soc { uart@80120000 { status = "okay"; }; @@ -45,14 +46,14 @@ compatible = "tc3589x"; reg = <0x42>; interrupt-parent = <&gpio6>; - interrupts = <25 0x1>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; interrupt-controller; #interrupt-cells = <2>; tc3589x_gpio: tc3589x_gpio { compatible = "tc3589x-gpio"; - interrupts = <0 0x1>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; interrupt-controller; #interrupt-cells = <2>; @@ -63,17 +64,43 @@ }; i2c@80128000 { - lp5521@0x33 { - compatible = "lp5521"; + lp5521@33 { + compatible = "national,lp5521"; reg = <0x33>; + label = "lp5521_pri"; + clock-mode = /bits/ 8 <2>; + chan0 { + led-cur = /bits/ 8 <0x2f>; + max-cur = /bits/ 8 <0x5f>; + }; + chan1 { + led-cur = /bits/ 8 <0x2f>; + max-cur = /bits/ 8 <0x5f>; + }; + chan2 { + led-cur = /bits/ 8 <0x2f>; + max-cur = /bits/ 8 <0x5f>; + }; }; - - lp5521@0x34 { - compatible = "lp5521"; + lp5521@34 { + compatible = "national,lp5521"; reg = <0x34>; + label = "lp5521_sec"; + clock-mode = /bits/ 8 <2>; + chan0 { + led-cur = /bits/ 8 <0x2f>; + max-cur = /bits/ 8 <0x5f>; + }; + chan1 { + led-cur = /bits/ 8 <0x2f>; + max-cur = /bits/ 8 <0x5f>; + }; + chan2 { + led-cur = /bits/ 8 <0x2f>; + max-cur = /bits/ 8 <0x5f>; + }; }; - - bh1780@0x29 { + bh1780@29 { compatible = "rohm,bh1780gli"; reg = <0x33>; }; @@ -82,7 +109,7 @@ // External Micro SD slot sdi0_per1@80126000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; + max-frequency = <100000000>; bus-width = <4>; mmc-cap-sd-highspeed; mmc-cap-mmc-highspeed; @@ -97,7 +124,7 @@ // WLAN SDIO channel sdi1_per2@80118000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; + max-frequency = <100000000>; bus-width = <4>; status = "okay"; @@ -106,7 +133,7 @@ // PoP:ed eMMC sdi2_per3@80005000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; + max-frequency = <100000000>; bus-width = <8>; mmc-cap-mmc-highspeed; @@ -116,7 +143,7 @@ // On-board eMMC sdi4_per2@80114000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; + max-frequency = <100000000>; bus-width = <8>; mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux2_reg>; @@ -236,7 +263,7 @@ regulator-name = "V-MMC-SD"; }; - ab8500_ldo_initcore_reg: ab8500_ldo_initcore { + ab8500_ldo_intcore_reg: ab8500_ldo_intcore { regulator-name = "V-INTCORE"; }; @@ -256,7 +283,7 @@ regulator-name = "V-AMIC1"; }; - ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { regulator-name = "V-AMIC2"; }; diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts index c2d274815923..c6bb07df2d1d 100644 --- a/arch/arm/boot/dts/hrefprev60.dts +++ b/arch/arm/boot/dts/hrefprev60.dts @@ -10,9 +10,9 @@ */ /dts-v1/; -/include/ "dbx5x0.dtsi" -/include/ "href.dtsi" -/include/ "stuib.dtsi" +#include "dbx5x0.dtsi" +#include "href.dtsi" +#include "stuib.dtsi" / { model = "ST-Ericsson HREF (pre-v60) platform with Device Tree"; @@ -24,7 +24,7 @@ }; }; - soc-u9500 { + soc { prcmu@80157000 { ab8500@5 { ab8500-gpio { @@ -41,7 +41,7 @@ }; i2c@80110000 { - bu21013_tp@0x5c { + bu21013_tp@5c { reset-gpio = <&tc3589x_gpio 13 0x4>; }; }; diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index 2b587a74b813..3d580d6447f9 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -10,9 +10,9 @@ */ /dts-v1/; -/include/ "dbx5x0.dtsi" -/include/ "href.dtsi" -/include/ "stuib.dtsi" +#include "dbx5x0.dtsi" +#include "href.dtsi" +#include "stuib.dtsi" / { model = "ST-Ericsson HREF (v60+) platform with Device Tree"; @@ -24,7 +24,7 @@ }; }; - soc-u9500 { + soc { i2c@80110000 { bu21013_tp@0x5c { reset-gpio = <&gpio4 15 0x4>; @@ -34,7 +34,7 @@ // External Micro SD slot sdi0_per1@80126000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; + max-frequency = <100000000>; bus-width = <4>; mmc-cap-sd-highspeed; mmc-cap-mmc-highspeed; @@ -48,7 +48,7 @@ // WLAN SDIO channel sdi1_per2@80118000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; + max-frequency = <100000000>; bus-width = <4>; status = "okay"; @@ -57,7 +57,7 @@ // PoP:ed eMMC sdi2_per3@80005000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; + max-frequency = <100000000>; bus-width = <8>; mmc-cap-mmc-highspeed; @@ -67,7 +67,7 @@ // On-board eMMC sdi4_per2@80114000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; + max-frequency = <100000000>; bus-width = <8>; mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux2_reg>; @@ -172,7 +172,7 @@ regulator-name = "V-MMC-SD"; }; - ab8500_ldo_initcore_reg: ab8500_ldo_initcore { + ab8500_ldo_intcore_reg: ab8500_ldo_intcore { regulator-name = "V-INTCORE"; }; @@ -192,7 +192,7 @@ regulator-name = "V-AMIC1"; }; - ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { regulator-name = "V-AMIC2"; }; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 73fd7d0887b5..587ceef81e45 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -23,8 +23,12 @@ }; cpus { - cpu@0 { - compatible = "arm,arm926ejs"; + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; }; }; diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index d2550e0bca24..701153992c69 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -141,8 +141,8 @@ #size-cells = <0>; compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; reg = <0x43fa4000 0x4000>; - clocks = <&clks 62>; - clock-names = "ipg"; + clocks = <&clks 62>, <&clks 62>; + clock-names = "ipg", "per"; interrupts = <14>; status = "disabled"; }; @@ -182,8 +182,8 @@ compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; reg = <0x50004000 0x4000>; interrupts = <0>; - clocks = <&clks 80>; - clock-names = "ipg"; + clocks = <&clks 80>, <&clks 80>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -210,8 +210,8 @@ #size-cells = <0>; compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; reg = <0x50010000 0x4000>; - clocks = <&clks 79>; - clock-names = "ipg"; + clocks = <&clks 79>, <&clks 79>; + clock-names = "ipg", "per"; interrupts = <13>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts new file mode 100644 index 000000000000..e7ed9786920a --- /dev/null +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -0,0 +1,37 @@ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx27-phytec-phycore-som.dts" + +/ { + model = "Phytec pcm970"; + compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27"; +}; + +&cspi1 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>; +}; + +&sdhci2 { + bus-width = <4>; + cd-gpios = <&gpio3 29 0>; + wp-gpios = <&gpio3 28 0>; + vmmc-supply = <&vmmc1_reg>; + status = "okay"; +}; + +&uart1 { + fsl,uart-has-rtscts; +}; + +&uart2 { + fsl,uart-has-rtscts; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts new file mode 100644 index 000000000000..f0105651869d --- /dev/null +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts @@ -0,0 +1,179 @@ +/* + * Copyright 2012 Sascha Hauer, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx27.dtsi" + +/ { + model = "Phytec pcm038"; + compatible = "phytec,imx27-pcm038", "fsl,imx27"; + + memory { + reg = <0x0 0x0>; + }; + + soc { + aipi@10000000 { /* aipi1 */ + serial@1000a000 { + status = "okay"; + }; + + i2c@1001d000 { + clock-frequency = <400000>; + status = "okay"; + at24@52 { + compatible = "at,24c32"; + pagesize = <32>; + reg = <0x52>; + }; + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + lm75@4a { + compatible = "national,lm75"; + reg = <0x4a>; + }; + }; + }; + + aipi@10020000 { /* aipi2 */ + ethernet@1002b000 { + phy-reset-gpios = <&gpio3 30 0>; + status = "okay"; + }; + }; + }; + + nor_flash@c0000000 { + compatible = "cfi-flash"; + bank-width = <2>; + reg = <0xc0000000 0x02000000>; + linux,mtd-name = "physmap-flash.0"; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&cspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 28 0>; + status = "okay"; + + pmic: mc13783@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mc13783"; + spi-max-frequency = <20000000>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <23 0x4>; + fsl,mc13xxx-uses-adc; + fsl,mc13xxx-uses-rtc; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + sw1b_reg: sw1b { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + sw2a_reg: sw2a { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + sw2b_reg: sw2b { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vaudio_reg: vaudio { + regulator-always-on; + regulator-boot-on; + }; + + violo_reg: violo { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + viohi_reg: viohi { + regulator-always-on; + regulator-boot-on; + }; + + vgen_reg: vgen { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vrf1_reg: vrf1 { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vrf2_reg: vrf2 { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc1_reg: vmmc1 { + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3000000>; + }; + + gpo1_reg: gpo1 { }; + + pwgt1spi_reg: pwgt1spi { + regulator-always-on; + }; + }; + }; +}; + +&nfc { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts deleted file mode 100644 index fe64e3a91df0..000000000000 --- a/arch/arm/boot/dts/imx27-phytec-phycore.dts +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Phytec pcm038"; - compatible = "phytec,imx27-pcm038", "fsl,imx27"; - - memory { - reg = <0x0 0x0>; - }; - - soc { - aipi@10000000 { /* aipi1 */ - serial@1000a000 { - fsl,uart-has-rtscts; - status = "okay"; - }; - - serial@1000b000 { - fsl,uart-has-rtscts; - status = "okay"; - }; - - serial@1000c000 { - fsl,uart-has-rtscts; - status = "okay"; - }; - - i2c@1001d000 { - clock-frequency = <400000>; - status = "okay"; - at24@52 { - compatible = "at,24c32"; - pagesize = <32>; - reg = <0x52>; - }; - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - lm75@4a { - compatible = "national,lm75"; - reg = <0x4a>; - }; - }; - }; - - aipi@10020000 { /* aipi2 */ - ethernet@1002b000 { - status = "okay"; - }; - }; - }; - - nor_flash@c0000000 { - compatible = "cfi-flash"; - bank-width = <2>; - reg = <0xc0000000 0x02000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index ff4bd4873edf..0695264ddf1b 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -25,6 +25,9 @@ gpio3 = &gpio4; gpio4 = &gpio5; gpio5 = &gpio6; + spi0 = &cspi1; + spi1 = &cspi2; + spi2 = &cspi3; }; avic: avic-interrupt-controller@e0000000 { @@ -58,6 +61,16 @@ reg = <0x10000000 0x20000>; ranges; + dma: dma@10001000 { + compatible = "fsl,imx27-dma"; + reg = <0x10001000 0x1000>; + interrupts = <32>; + clocks = <&clks 50>, <&clks 70>; + clock-names = "ipg", "ahb"; + #dma-cells = <1>; + #dma-channels = <16>; + }; + wdog: wdog@10002000 { compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; reg = <0x10002000 0x1000>; @@ -89,6 +102,14 @@ clock-names = "ipg", "per"; }; + pwm0: pwm@10006000 { + compatible = "fsl,imx27-pwm"; + reg = <0x10006000 0x1000>; + interrupts = <23>; + clocks = <&clks 34>, <&clks 61>; + clock-names = "ipg", "per"; + }; + uart1: serial@1000a000 { compatible = "fsl,imx27-uart", "fsl,imx21-uart"; reg = <0x1000a000 0x1000>; @@ -131,7 +152,7 @@ compatible = "fsl,imx27-cspi"; reg = <0x1000e000 0x1000>; interrupts = <16>; - clocks = <&clks 53>, <&clks 0>; + clocks = <&clks 53>, <&clks 53>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -142,7 +163,7 @@ compatible = "fsl,imx27-cspi"; reg = <0x1000f000 0x1000>; interrupts = <15>; - clocks = <&clks 52>, <&clks 0>; + clocks = <&clks 52>, <&clks 52>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -157,6 +178,28 @@ status = "disabled"; }; + sdhci1: sdhci@10013000 { + compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; + reg = <0x10013000 0x1000>; + interrupts = <11>; + clocks = <&clks 30>, <&clks 60>; + clock-names = "ipg", "per"; + dmas = <&dma 7>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + sdhci2: sdhci@10014000 { + compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; + reg = <0x10014000 0x1000>; + interrupts = <10>; + clocks = <&clks 29>, <&clks 60>; + clock-names = "ipg", "per"; + dmas = <&dma 6>; + dma-names = "rx-tx"; + status = "disabled"; + }; + gpio1: gpio@10015000 { compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; reg = <0x10015000 0x100>; @@ -223,7 +266,7 @@ compatible = "fsl,imx27-cspi"; reg = <0x10017000 0x1000>; interrupts = <6>; - clocks = <&clks 51>, <&clks 0>; + clocks = <&clks 51>, <&clks 51>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -272,6 +315,17 @@ status = "disabled"; }; + sdhci3: sdhci@1001e000 { + compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; + reg = <0x1001e000 0x1000>; + interrupts = <9>; + clocks = <&clks 28>, <&clks 60>; + clock-names = "ipg", "per"; + dmas = <&dma 36>; + dma-names = "rx-tx"; + status = "disabled"; + }; + gpt6: timer@1001f000 { compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; reg = <0x1001f000 0x1000>; @@ -288,6 +342,21 @@ reg = <0x10020000 0x20000>; ranges; + coda: coda@10023000 { + compatible = "fsl,imx27-vpu"; + reg = <0x10023000 0x0200>; + interrupts = <53>; + clocks = <&clks 57>, <&clks 66>; + clock-names = "per", "ahb"; + iram = <&iram>; + }; + + clks: ccm@10027000{ + compatible = "fsl,imx27-ccm"; + reg = <0x10027000 0x1000>; + #clock-cells = <1>; + }; + fec: ethernet@1002b000 { compatible = "fsl,imx27-fec"; reg = <0x1002b000 0x4000>; @@ -296,19 +365,16 @@ clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; - - clks: ccm@10027000{ - compatible = "fsl,imx27-ccm"; - reg = <0x10027000 0x1000>; - #clock-cells = <1>; - }; }; + iram: iram@ffff4c00 { + compatible = "mmio-sram"; + reg = <0xffff4c00 0xb400>; + }; nfc: nand@d8000000 { #address-cells = <1>; #size-cells = <1>; - compatible = "fsl,imx27-nand"; reg = <0xd8000000 0x1000>; interrupts = <29>; diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts index 3d905d16cbec..b602494c152b 100644 --- a/arch/arm/boot/dts/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/imx28-apf28dev.dts @@ -103,6 +103,7 @@ apbx@80040000 { lradc@80050000 { + fsl,lradc-touchscreen-wires = <4>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts index 1594694532b9..94c4476972c3 100644 --- a/arch/arm/boot/dts/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/imx28-cfa10036.dts @@ -45,6 +45,17 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + usb0_otg_cfa10036: otg-10036@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0142 /* MX28_PAD_GPMI_READY0__USB0_ID */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; ssp0: ssp@80010000 { @@ -58,12 +69,6 @@ }; apbx@80040000 { - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pins_a>; - status = "okay"; - }; - duart: serial@80074000 { pinctrl-names = "default"; pinctrl-0 = <&duart_pins_b>; @@ -73,15 +78,30 @@ i2c0: i2c@80058000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_b>; + clock-frequency = <400000>; status = "okay"; - ssd1307: oled@3c { - compatible = "solomon,ssd1307fb-i2c"; + ssd1306: oled@3c { + compatible = "solomon,ssd1306fb-i2c"; reg = <0x3c>; - pwms = <&pwm 4 3000>; reset-gpios = <&gpio2 7 0>; + solomon,height = <32>; + solomon,width = <128>; + solomon,page-offset = <0>; }; }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_otg_cfa10036>; + status = "okay"; }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 063e62059890..04b2f769ffbd 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -33,7 +33,7 @@ 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */ 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ - 0x3173 /* MX28_PAD_LCD_RESET__GPIO_3_23 */ + 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -166,8 +166,8 @@ apbx@80040000 { pwm: pwm@80064000 { - pinctrl-names = "default", "default"; - pinctrl-1 = <&pwm3_pins_b>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_b>; status = "okay"; }; @@ -265,7 +265,7 @@ gpio-sck = <&gpio2 16 0>; gpio-mosi = <&gpio2 17 0>; gpio-miso = <&gpio2 18 0>; - cs-gpios = <&gpio3 23 0>; + cs-gpios = <&gpio3 5 0>; num-chipselects = <1>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts new file mode 100644 index 000000000000..158111244122 --- /dev/null +++ b/arch/arm/boot/dts/imx28-cfa10055.dts @@ -0,0 +1,179 @@ +/* + * Copyright 2013 Crystalfontz America, Inc. + * Free Electrons + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * The CFA-10055 is an expansion board for the CFA-10036 module and + * CFA-10037, thus we need to include the CFA-10037 DTS. + */ +/include/ "imx28-cfa10037.dts" + +/ { + model = "Crystalfontz CFA-10055 Board"; + compatible = "crystalfontz,cfa10055", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; + + apb@80000000 { + apbh@80000000 { + pinctrl@80018000 { + pinctrl-names = "default", "default"; + pinctrl-1 = <&hog_pins_cfa10055 + &hog_pins_cfa10055_pullup>; + + hog_pins_cfa10055: hog-10055@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + hog_pins_cfa10055_pullup: hog-10055-pullup@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + spi2_pins_cfa10055: spi2-cfa10055@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ + 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ + 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + lcdif_18bit_pins_cfa10055: lcdif-18bit@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ + 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ + 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ + 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ + 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ + 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ + 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ + 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ + 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ + 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ + 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ + 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ + 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ + 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ + 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ + 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ + 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ + 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + lcdif_pins_cfa10055: lcdif-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_18bit_pins_cfa10055 + &lcdif_pins_cfa10055>; + display = <&display>; + status = "okay"; + + display: display { + bits-per-pixel = <32>; + bus-width = <18>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9216000>; + hactive = <320>; + vactive = <480>; + hback-porch = <2>; + hfront-porch = <2>; + vback-porch = <2>; + vfront-porch = <2>; + hsync-len = <15>; + vsync-len = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + }; + }; + + apbx@80040000 { + lradc@80050000 { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; + }; + + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_b>; + status = "okay"; + }; + }; + }; + + spi2 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_cfa10055>; + status = "okay"; + gpio-sck = <&gpio2 16 0>; + gpio-mosi = <&gpio2 17 0>; + gpio-miso = <&gpio2 18 0>; + cs-gpios = <&gpio3 5 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + hx8357: hx8357@0 { + compatible = "himax,hx8357b", "himax,hx8357"; + reg = <0>; + spi-max-frequency = <100000>; + spi-cpol; + spi-cpha; + gpios-reset = <&gpio3 30 0>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 3 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; +}; diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts new file mode 100644 index 000000000000..2da713cdb42a --- /dev/null +++ b/arch/arm/boot/dts/imx28-cfa10057.dts @@ -0,0 +1,191 @@ +/* + * Copyright 2013 Crystalfontz America, Inc. + * Copyright 2012 Free Electrons + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * The CFA-10057 is an expansion board for the CFA-10036 module, thus we + * need to include the CFA-10036 DTS. + */ +/include/ "imx28-cfa10036.dts" + +/ { + model = "Crystalfontz CFA-10057 Board"; + compatible = "crystalfontz,cfa10057", "crystalfontz,cfa10036", "fsl,imx28"; + + apb@80000000 { + apbh@80000000 { + pinctrl@80018000 { + pinctrl-names = "default", "default"; + pinctrl-1 = <&hog_pins_cfa10057 + &hog_pins_cfa10057_pullup>; + + hog_pins_cfa10057: hog-10057@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ + 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + hog_pins_cfa10057_pullup: hog-10057-pullup@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */ + 0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */ + 0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */ + 0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */ + 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + lcdif_18bit_pins_cfa10057: lcdif-18bit@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ + 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ + 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ + 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ + 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ + 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ + 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ + 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ + 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ + 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ + 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ + 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ + 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ + 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ + 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ + 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ + 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ + 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + lcdif_pins_cfa10057: lcdif-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_18bit_pins_cfa10057 + &lcdif_pins_cfa10057>; + display = <&display>; + status = "okay"; + + display: display { + bits-per-pixel = <32>; + bus-width = <18>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <30000000>; + hactive = <480>; + vactive = <800>; + hfront-porch = <12>; + hback-porch = <2>; + vfront-porch = <5>; + vback-porch = <3>; + hsync-len = <2>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + }; + }; + + apbx@80040000 { + lradc@80050000 { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; + }; + + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_b>; + status = "okay"; + }; + + i2c1: i2c@8005a000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + usbphy1: usbphy@8007e000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb1: usb@80090000 { + vbus-supply = <®_usb1_vbus>; + pinctrl-0 = <&usbphy1_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_usb1_vbus: usb1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 7 1>; + }; + }; + + ahb@80080000 { + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio2 21 0>; + phy-reset-duration = <100>; + status = "okay"; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 3 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; +}; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 5aa44e05c9f5..880df2f13be8 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -220,7 +220,19 @@ auart0: serial@8006a000 { pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; + }; + + auart1: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_pins_a>; + status = "okay"; + }; + + auart2: serial@8006e000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart2_2pins_b>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 600f7cb51f3e..195451bf7706 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -32,8 +32,12 @@ }; cpus { - cpu@0 { - compatible = "arm,arm926ejs"; + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; }; }; @@ -330,6 +334,17 @@ fsl,pull-up = <0>; }; + auart2_2pins_b: auart2-2pins@1 { + reg = <1>; + fsl,pinmux-ids = < + 0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */ + 0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + auart3_pins_a: auart3@0 { reg = <0>; fsl,pinmux-ids = < @@ -354,6 +369,28 @@ fsl,pull-up = <0>; }; + auart3_2pins_b: auart3-2pins@1 { + reg = <1>; + fsl,pinmux-ids = < + 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ + 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart4_2pins_a: auart4@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2181 /* MX28_PAD_SSP3_SCK__AUART4_TX */ + 0x2191 /* MX28_PAD_SSP3_MOSI__AUART4_RX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + mac0_pins_a: mac0@0 { reg = <0>; fsl,pinmux-ids = < @@ -669,7 +706,7 @@ }; digctl@8001c000 { - compatible = "fsl,imx28-digctl"; + compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; reg = <0x8001c000 0x2000>; interrupts = <89>; status = "disabled"; diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts index 2bcf6981d490..8f7f9ac0b989 100644 --- a/arch/arm/boot/dts/imx51-apf51.dts +++ b/arch/arm/boot/dts/imx51-apf51.dts @@ -45,6 +45,13 @@ status = "okay"; }; +&nfc { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3_2>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 21bb786c5b31..25764b505a61 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -175,10 +175,20 @@ }; }; + usbphy0: usbphy@0 { + compatible = "usb-nop-xceiv"; + clocks = <&clks 124>; + clock-names = "main_clk"; + status = "okay"; + }; + usbotg: usb@73f80000 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80000 0x0200>; interrupts = <18>; + clocks = <&clks 108>; + fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -186,6 +196,8 @@ compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80200 0x0200>; interrupts = <14>; + clocks = <&clks 108>; + fsl,usbmisc = <&usbmisc 1>; status = "disabled"; }; @@ -193,6 +205,8 @@ compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80400 0x0200>; interrupts = <16>; + clocks = <&clks 108>; + fsl,usbmisc = <&usbmisc 2>; status = "disabled"; }; @@ -200,9 +214,18 @@ compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80600 0x0200>; interrupts = <17>; + clocks = <&clks 108>; + fsl,usbmisc = <&usbmisc 3>; status = "disabled"; }; + usbmisc: usbmisc@73f80800 { + #index-cells = <1>; + compatible = "fsl,imx51-usbmisc"; + reg = <0x73f80800 0x200>; + clocks = <&clks 108>; + }; + gpio1: gpio@73f84000 { compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; reg = <0x73f84000 0x4000>; @@ -631,7 +654,7 @@ compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; reg = <0x83fc0000 0x4000>; interrupts = <38>; - clocks = <&clks 55>, <&clks 0>; + clocks = <&clks 55>, <&clks 55>; clock-names = "ipg", "per"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts new file mode 100644 index 000000000000..7d304d02ed38 --- /dev/null +++ b/arch/arm/boot/dts/imx53-m53evk.dts @@ -0,0 +1,259 @@ +/* + * Copyright (C) 2013 Marek Vasut <marex@denx.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx53.dtsi" + +/ { + model = "DENX M53EVK"; + compatible = "denx,imx53-m53evk", "fsl,imx53"; + + memory { + reg = <0x70000000 0x20000000>; + }; + + soc { + display@di1 { + compatible = "fsl,imx-parallel-display"; + crtcs = <&ipu 1>; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp2_1>; + + display-timings { + 800x480p60 { + native-mode; + clock-frequency = <31500000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <88>; + hsync-len = <128>; + vback-porch = <33>; + vfront-porch = <9>; + vsync-len = <3>; + vsync-active = <1>; + }; + }; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 3000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_gpio>; + + user1 { + label = "user1"; + gpios = <&gpio2 8 0>; + linux,default-trigger = "heartbeat"; + }; + + user2 { + label = "user2"; + gpios = <&gpio2 9 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p2v: 3p2v { + compatible = "regulator-fixed"; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + }; + + sound { + compatible = "fsl,imx53-m53evk-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx53-m53evk-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Ext Spk", "LINE_OUT"; + mux-int-port = <2>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_2>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2_1>; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_1>; + cd-gpios = <&gpio1 1 0>; + wp-gpios = <&gpio1 9 0>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; + phy-mode = "rmii"; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_2>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p2v>; + VDDIO-supply = <®_3p2v>; + clocks = <&clks 150>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_2>; + clock-frequency = <400000>; + status = "okay"; + + stmpe610@41 { + compatible = "st,stmpe610"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41>; + id = <0>; + blocks = <0x5>; + interrupts = <6 0x0>; + interrupt-parent = <&gpio7>; + irq-trigger = <0x1>; + + stmpe_touchscreen { + compatible = "stmpe,ts"; + reg = <0>; + ts,sample-time = <4>; + ts,mod-12b = <1>; + ts,ref-sel = <0>; + ts,adc-freq = <1>; + ts,ave-ctrl = <3>; + ts,touch-det-delay = <3>; + ts,settling = <4>; + ts,fraction-z = <7>; + ts,i-drive = <1>; + }; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@68 { + compatible = "stm,m41t62"; + reg = <0x68>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_1>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 + MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 + MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 + + >; + }; + + led_pin_gpio: led_gpio@0 { + fsl,pins = < + MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000 + MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 + >; + }; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand_1>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_1>; + status = "okay"; +}; + +&ssi2 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_2>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts index 445a01119cc5..aaa33bc99f78 100644 --- a/arch/arm/boot/dts/imx53-mba53.dts +++ b/arch/arm/boot/dts/imx53-mba53.dts @@ -16,27 +16,81 @@ / { model = "TQ MBa53 starter kit"; compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; + + reg_backlight: fixed@0 { + compatible = "regulator-fixed"; + regulator-name = "lcd-supply"; + gpio = <&gpio2 5 0>; + startup-delay-us = <5000>; + enable-active-low; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 50000 0 0>; + brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>; + default-brightness-level = <10>; + enable-gpios = <&gpio7 7 0>; + power-supply = <®_backlight>; + }; + + disp1: display@disp1 { + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp1_1>; + crtcs = <&ipu 1>; + interface-pix-fmt = "rgb24"; + status = "disabled"; + }; + + reg_3p2v: 3p2v { + compatible = "regulator-fixed"; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + + sound { + compatible = "tq,imx53-mba53-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx53-mba53-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <5>; + }; +}; + +&ldb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_1>; + status = "disabled"; }; &iomuxc { lvds1 { pinctrl_lvds1_1: lvds1-grp1 { fsl,pins = < - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000 - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000 - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000 - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000 - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000 + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 >; }; pinctrl_lvds1_2: lvds1-grp2 { fsl,pins = < - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000 - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000 - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000 - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000 - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000 + MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 + MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 + MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 + MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 + MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 >; }; }; @@ -44,33 +98,44 @@ disp1 { pinctrl_disp1_1: disp1-grp1 { fsl,pins = < - MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x10000 /* DISP1_DRDY */ - MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x10000 /* DISP1_HSYNC */ - MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x10000 /* DISP1_VSYNC */ - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000 - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000 - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000 - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000 - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000 - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000 - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000 - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000 - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000 - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000 - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000 - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000 - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000 - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000 - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x10000 - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x10000 - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x10000 - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x10000 - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x10000 - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x10000 - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x10000 - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x10000 - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x10000 - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x10000 + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */ + MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */ + MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */ + MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */ + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000 + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000 + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000 + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000 + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000 + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000 + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000 + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000 + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000 + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000 + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000 + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000 + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000 + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000 + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000 + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000 + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000 + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000 + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000 + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000 + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000 + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000 + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000 + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000 + >; + }; + }; + + tve { + pinctrl_vga_sync_1: vgasync-grp1 { + fsl,pins = < + /* VGA_VSYNC, HSYNC with max drive strength */ + MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6 + MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6 >; }; }; @@ -80,16 +145,27 @@ status = "okay"; }; +&audmux { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_1>; +}; + &i2c2 { codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + clocks = <&clks 150>; + VDDA-supply = <®_3p2v>; + VDDIO-supply = <®_3p2v>; }; expander: pca9554@20 { compatible = "pca9554"; reg = <0x20>; interrupts = <109>; + #gpio-cells = <2>; + gpio-controller; }; sensor2: lm75@49 { @@ -99,6 +175,7 @@ }; &fec { + phy-reset-gpios = <&gpio7 6 0>; status = "okay"; }; @@ -114,10 +191,24 @@ status = "okay"; }; +&usbotg { + dr_mode = "host"; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + &uart1 { status = "okay"; }; +&ssi2 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + &uart2 { status = "okay"; }; @@ -133,3 +224,13 @@ &i2c3 { status = "okay"; }; + +&tve { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vga_sync_1>; + ddc = <&i2c3>; + fsl,tve-mode = "vga"; + fsl,hsync-pin = <4>; + fsl,vsync-pin = <6>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 8f0e9ae0e3e6..512a1f608253 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -21,6 +21,33 @@ reg = <0x70000000 0x40000000>; }; + display@di0 { + compatible = "fsl,imx-parallel-display"; + crtcs = <&ipu 0>; + interface-pix-fmt = "rgb565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp0_1>; + status = "disabled"; + display-timings { + claawvga { + native-mode; + clock-frequency = <27000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <60>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -147,6 +174,7 @@ reg = <0x0a>; VDDA-supply = <®_3p2v>; VDDIO-supply = <®_3p2v>; + clocks = <&clks 150>; }; }; @@ -268,3 +296,11 @@ phy-reset-gpios = <&gpio7 6 0>; status = "okay"; }; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi index 38bed3ed7c1a..abd72af545bf 100644 --- a/arch/arm/boot/dts/imx53-tqma53.dtsi +++ b/arch/arm/boot/dts/imx53-tqma53.dtsi @@ -35,7 +35,9 @@ &esdhc2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2_1>; + pinctrl-0 = <&pinctrl_esdhc2_1>, + <&pinctrl_tqma53_esdhc2_2>; + vmmc-supply = <®_3p3v>; wp-gpios = <&gpio1 2 0>; cd-gpios = <&gpio1 4 0>; status = "disabled"; @@ -69,14 +71,22 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; + esdhc2_2 { + pinctrl_tqma53_esdhc2_2: esdhc2-tqma53-grp2 { + fsl,pins = < + MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */ + MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */ + >; + }; + }; + i2s { pinctrl_i2s_1: i2s-grp1 { fsl,pins = < - MX53_PAD_GPIO_19__GPIO4_5 0x10000 /* I2S_MCLK */ - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x10000 /* I2S_SCLK */ - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x10000 /* I2S_DOUT */ - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x10000 /* I2S_LRCLK */ - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x10000 /* I2S_DIN */ + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 /* I2S_SCLK */ + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 /* I2S_DOUT */ + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 /* I2S_LRCLK */ + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 /* I2S_DIN */ >; }; }; @@ -84,16 +94,17 @@ hog { pinctrl_hog: hoggrp { fsl,pins = < - MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x10000 /* VSYNC */ - MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x10000 /* HSYNC */ - MX53_PAD_PATA_DA_1__GPIO7_7 0x10000 /* LCD_BLT_EN */ - MX53_PAD_PATA_DA_2__GPIO7_8 0x10000 /* LCD_RESET */ - MX53_PAD_PATA_DATA5__GPIO2_5 0x10000 /* LCD_POWER */ - MX53_PAD_PATA_DATA6__GPIO2_6 0x10000 /* PMIC_INT */ - MX53_PAD_PATA_DATA14__GPIO2_14 0x10000 /* CSI_RST */ - MX53_PAD_PATA_DATA15__GPIO2_15 0x10000 /* CSI_PWDN */ - MX53_PAD_GPIO_0__GPIO1_0 0x10000 /* SYSTEM_DOWN */ - MX53_PAD_GPIO_3__GPIO1_3 0x10000 + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */ + MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */ + MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */ + MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */ + MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */ + MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */ + MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */ + MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */ + MX53_PAD_GPIO_3__GPIO1_3 0x80000000 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */ + MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */ >; }; }; @@ -149,7 +160,7 @@ reg = <0x8>; fsl,mc13xxx-uses-rtc; interrupt-parent = <&gpio2>; - interrupts = <6 8>; /* PDATA_DATA6, low active */ + interrupts = <6 4>; /* PATA_DATA6, active high */ }; sensor1: lm75@48 { diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi new file mode 100644 index 000000000000..f494766700a3 --- /dev/null +++ b/arch/arm/boot/dts/imx53-tx53.dtsi @@ -0,0 +1,122 @@ +/* + * Copyright 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "imx53.dtsi" + +/ { + model = "Ka-Ro TX53"; + compatible = "karo,tx53", "fsl,imx53"; + + memory { + reg = <0x70000000 0x40000000>; /* Up to 1GiB */ + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_2>; + status = "disabled"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2_1>; + status = "disabled"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_2>; + status = "disabled"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_2>; + status = "disabled"; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2_1>; + status = "disabled"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; + phy-mode = "rmii"; + status = "disabled"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_2>; + status = "disabled"; +}; + +&owire { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_owire_1>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2_1>; + status = "disabled"; +}; + +&ssi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_1>; + status = "disabled"; +}; + +&ssi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_2>; + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_2>, + <&pinctrl_uart1_3>; + fsl,uart-has-rtscts; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_2>; + fsl,uart-has-rtscts; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; + fsl,uart-has-rtscts; + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 845982eaac22..3895fbba8fce 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -27,6 +27,9 @@ gpio4 = &gpio5; gpio5 = &gpio6; gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; }; tzic: tz-interrupt-controller@0fffc000 { @@ -163,10 +166,27 @@ }; }; + usbphy0: usbphy@0 { + compatible = "usb-nop-xceiv"; + clocks = <&clks 124>; + clock-names = "main_clk"; + status = "okay"; + }; + + usbphy1: usbphy@1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks 125>; + clock-names = "main_clk"; + status = "okay"; + }; + usbotg: usb@53f80000 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80000 0x0200>; interrupts = <18>; + clocks = <&clks 108>; + fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -174,6 +194,9 @@ compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80200 0x0200>; interrupts = <14>; + clocks = <&clks 108>; + fsl,usbmisc = <&usbmisc 1>; + fsl,usbphy = <&usbphy1>; status = "disabled"; }; @@ -181,6 +204,8 @@ compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80400 0x0200>; interrupts = <16>; + clocks = <&clks 108>; + fsl,usbmisc = <&usbmisc 2>; status = "disabled"; }; @@ -188,9 +213,18 @@ compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80600 0x0200>; interrupts = <17>; + clocks = <&clks 108>; + fsl,usbmisc = <&usbmisc 3>; status = "disabled"; }; + usbmisc: usbmisc@53f80800 { + #index-cells = <1>; + compatible = "fsl,imx53-usbmisc"; + reg = <0x53f80800 0x200>; + clocks = <&clks 108>; + }; + gpio1: gpio@53f84000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53f84000 0x4000>; @@ -267,6 +301,24 @@ MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 >; }; + + pinctrl_audmux_2: audmuxgrp-2 { + fsl,pins = < + MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 + MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 + MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 + MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 + >; + }; + + pinctrl_audmux_3: audmuxgrp-3 { + fsl,pins = < + MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000 + MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000 + MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000 + MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000 + >; + }; }; fec { @@ -284,6 +336,29 @@ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 >; }; + + pinctrl_fec_2: fecgrp-2 { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + MX53_PAD_KEY_ROW1__FEC_COL 0x80000000 + MX53_PAD_KEY_COL3__FEC_CRS 0x80000000 + MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000 + MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000 + MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000 + MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000 + MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000 + MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000 + >; + }; }; csi { @@ -312,6 +387,22 @@ MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 >; }; + + pinctrl_csi_2: csigrp-2 { + fsl,pins = < + MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5 + MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5 + MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 + MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5 + MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5 + MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5 + MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5 + MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5 + MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5 + MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5 + MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5 + >; + }; }; cspi { @@ -322,6 +413,14 @@ MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 >; }; + + pinctrl_cspi_2: cspigrp-2 { + fsl,pins = < + MX53_PAD_EIM_D22__CSPI_MISO 0x1d5 + MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5 + MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5 + >; + }; }; ecspi1 { @@ -332,6 +431,27 @@ MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 >; }; + + pinctrl_ecspi1_2: ecspi1grp-2 { + fsl,pins = < + MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000 + MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000 + MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 + MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 + MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 + MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000 + >; + }; + }; + + ecspi2 { + pinctrl_ecspi2_1: ecspi2grp-1 { + fsl,pins = < + MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000 + MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000 + MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000 + >; + }; }; esdhc1 { @@ -406,6 +526,13 @@ MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 >; }; + + pinctrl_can1_3: can1grp-3 { + fsl,pins = < + MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 + MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 + >; + }; }; can2 { @@ -424,6 +551,13 @@ MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 >; }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 + MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 + >; + }; }; i2c2 { @@ -433,6 +567,13 @@ MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 >; }; + + pinctrl_i2c2_2: i2c2grp-2 { + fsl,pins = < + MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 + MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 + >; + }; }; i2c3 { @@ -444,6 +585,119 @@ }; }; + ipu_disp0 { + pinctrl_ipu_disp0_1: ipudisp0grp-1 { + fsl,pins = < + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 + >; + }; + }; + + ipu_disp1 { + pinctrl_ipu_disp1_1: ipudisp1grp-1 { + fsl,pins = < + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 + MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 + MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 + MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 + MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 + MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 + MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 + MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 + >; + }; + }; + + ipu_disp2 { + pinctrl_ipu_disp2_1: ipudisp2grp-1 { + fsl,pins = < + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 + MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 + MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 + MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 + MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 + MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 + >; + }; + }; + + nand { + pinctrl_nand_1: nandgrp-1 { + fsl,pins = < + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 + >; + }; + }; + owire { pinctrl_owire_1: owiregrp-1 { fsl,pins = < @@ -452,6 +706,22 @@ }; }; + pwm1 { + pinctrl_pwm1_1: pwm1grp-1 { + fsl,pins = < + MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 + >; + }; + }; + + pwm2 { + pinctrl_pwm2_1: pwm2grp-1 { + fsl,pins = < + MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 + >; + }; + }; + uart1 { pinctrl_uart1_1: uart1grp-1 { fsl,pins = < @@ -466,6 +736,13 @@ MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5 >; }; + + pinctrl_uart1_3: uart1grp-3 { + fsl,pins = < + MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5 + MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5 + >; + }; }; uart2 { @@ -475,6 +752,15 @@ MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 >; }; + + pinctrl_uart2_2: uart2grp-2 { + fsl,pins = < + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 + MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5 + MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5 + >; + }; }; uart3 { @@ -513,7 +799,6 @@ >; }; }; - }; gpr: iomuxc-gpr@53fa8000 { @@ -714,7 +999,7 @@ compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; reg = <0x63fc0000 0x4000>; interrupts = <38>; - clocks = <&clks 55>, <&clks 0>; + clocks = <&clks 55>, <&clks 55>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -781,6 +1066,16 @@ clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; + + tve: tve@63ff0000 { + compatible = "fsl,imx53-tve"; + reg = <0x63ff0000 0x1000>; + interrupts = <92>; + clocks = <&clks 69>, <&clks 116>; + clock-names = "tve", "di_sel"; + crtcs = <&ipu 1>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts index 7adcec360213..95da71185a4a 100644 --- a/arch/arm/boot/dts/imx6dl-sabreauto.dts +++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts @@ -28,4 +28,12 @@ >; }; }; + + ecspi1 { + pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { + fsl,pins = < + MX6DL_PAD_EIM_D19__GPIO3_IO19 0x80000000 + >; + }; + }; }; diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts index 7efb05db4783..8989df2b89e5 100644 --- a/arch/arm/boot/dts/imx6dl-sabresd.dts +++ b/arch/arm/boot/dts/imx6dl-sabresd.dts @@ -29,6 +29,7 @@ MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 + MX6DL_PAD_GPIO_0__CCM_CLKO1 0x130b0 >; }; }; diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 5bcdf3a90bb3..2b3ecd679350 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -18,12 +18,14 @@ cpu@0 { compatible = "arm,cortex-a9"; + device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; }; cpu@1 { compatible = "arm,cortex-a9"; + device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; }; @@ -35,6 +37,27 @@ compatible = "fsl,imx6dl-iomuxc"; reg = <0x020e0000 0x4000>; + audmux { + pinctrl_audmux_2: audmux-2 { + fsl,pins = < + MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 + MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 + MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 + MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + >; + }; + }; + enet { pinctrl_enet_1: enetgrp-1 { fsl,pins = < @@ -78,6 +101,39 @@ }; }; + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + }; + + i2c1 { + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + }; + uart1 { pinctrl_uart1_1: uart1grp-1 { fsl,pins = < @@ -149,6 +205,64 @@ }; }; + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1 + MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 + /* data */ + MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 + MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 + MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 + MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 + MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 + MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 + MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 + MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 + MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 + MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 + MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 + MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 + MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 + MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 + MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 + MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 + /* address */ + MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 + MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 + MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 + MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 + MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 + MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 + MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 + MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 + MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + + }; }; diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts new file mode 100644 index 000000000000..7d37ec60d58d --- /dev/null +++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts @@ -0,0 +1,34 @@ +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q-phytec-pfla02.dtsi" + +/ { + model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board"; + compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q"; +}; + +&fec { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi new file mode 100644 index 000000000000..f5e1981025ed --- /dev/null +++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi @@ -0,0 +1,74 @@ +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx6q.dtsi" + +/ { + model = "Phytec phyFLEX-i.MX6 Ouad"; + compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x80000000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000 + >; + }; + }; + + pfla02 { + pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 { + fsl,pins = < + MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 + MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 + >; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_3>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 23 0>; + status = "disabled"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_1>; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_2>; + cd-gpios = <&gpio1 4 0>; + wp-gpios = <&gpio1 2 0>; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_2 + &pinctrl_usdhc3_pfla02>; + cd-gpios = <&gpio1 27 0>; + wp-gpios = <&gpio1 29 0>; + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts index 49d6f2831ec9..09a75807bc6d 100644 --- a/arch/arm/boot/dts/imx6q-sabreauto.dts +++ b/arch/arm/boot/dts/imx6q-sabreauto.dts @@ -32,4 +32,12 @@ >; }; }; + + ecspi1 { + pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { + fsl,pins = < + MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 + >; + }; + }; }; diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index 442051350225..0038228c508c 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts @@ -33,6 +33,7 @@ MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000 MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000 MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000 + MX6Q_PAD_GPIO_0__CCM_CLKO1 0x130b0 >; }; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 21e675848bd1..ba09dc32324e 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -18,6 +18,7 @@ cpu@0 { compatible = "arm,cortex-a9"; + device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; operating-points = < @@ -39,18 +40,21 @@ cpu@1 { compatible = "arm,cortex-a9"; + device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; }; cpu@2 { compatible = "arm,cortex-a9"; + device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; }; cpu@3 { compatible = "arm,cortex-a9"; + device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; }; @@ -157,6 +161,27 @@ MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 >; }; + + pinctrl_enet_3: enetgrp-3 { + fsl,pins = < + MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + >; + }; }; gpmi-nand { @@ -168,8 +193,6 @@ MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000 MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 - MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1 MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1 MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1 @@ -192,6 +215,13 @@ MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 >; }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; }; i2c2 { @@ -268,6 +298,17 @@ MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059 >; }; + + pinctrl_usdhc2_2: usdhc2grp-2 { + fsl,pins = < + MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; }; usdhc3 { @@ -325,6 +366,65 @@ >; }; }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6Q_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weimnorgrp-1 { + fsl,pins = < + MX6Q_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6Q_PAD_EIM_RW__EIM_RW 0xb0b1 + MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 + /* data */ + MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0 + MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0 + MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0 + MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0 + MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0 + MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0 + MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0 + MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0 + MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0 + MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0 + MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0 + MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0 + MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0 + MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0 + MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0 + MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0 + /* address */ + MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1 + MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1 + MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1 + MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1 + MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1 + MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1 + MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1 + MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1 + MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + + }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 4d237cffcc41..e994011220e7 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -16,6 +16,22 @@ }; }; +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>; + status = "disabled"; /* pin conflict with WEIM NOR */ + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet_2>; @@ -23,6 +39,12 @@ status = "okay"; }; +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4_1>; @@ -36,3 +58,22 @@ wp-gpios = <&gpio1 13 0>; status = "okay"; }; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x08000000>; + status = "disabled"; /* pin conflict with SPI NOR */ + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index e21f6a89cf0f..6e5dfdb32416 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -26,6 +26,13 @@ gpio = <&gpio3 22 0>; enable-active-high; }; + + reg_audio: wm8962_supply { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply"; + gpio = <&gpio4 10 0>; + enable-active-high; + }; }; gpio-keys { @@ -43,6 +50,31 @@ linux,code = <114>; /* KEY_VOLUMEDOWN */ }; }; + + sound { + compatible = "fsl,imx6q-sabresd-wm8962", + "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + ssi-controller = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "MICBIAS", "AMIC", + "IN3R", "MICBIAS", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC"; + mux-int-port = <2>; + mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_2>; + status = "okay"; }; &fec { @@ -52,6 +84,40 @@ status = "okay"; }; +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_2>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks 169>; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0013 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x8014 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; +}; + +&ssi2 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_1>; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 9e8296e4c343..f21d259080fd 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -106,6 +106,8 @@ interrupts = <0 92 0x04>; cache-unified; cache-level = <2>; + arm,tag-latency = <4 2 3>; + arm,data-latency = <4 2 3>; }; pmu { @@ -638,7 +640,7 @@ status = "disabled"; }; - usbmisc: usbmisc: usbmisc@02184800 { + usbmisc: usbmisc@02184800 { #index-cells = <1>; compatible = "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; @@ -742,9 +744,11 @@ reg = <0x021b4000 0x4000>; }; - weim@021b8000 { + weim: weim@021b8000 { + compatible = "fsl,imx6q-weim"; reg = <0x021b8000 0x4000>; interrupts = <0 14 0x04>; + clocks = <&clks 196>; }; ocotp@021bc000 { @@ -752,11 +756,6 @@ reg = <0x021bc000 0x4000>; }; - ocotp@021c0000 { - reg = <0x021c0000 0x4000>; - interrupts = <0 21 0x04>; - }; - tzasc@021d0000 { /* TZASC1 */ reg = <0x021d0000 0x4000>; interrupts = <0 108 0x04>; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts new file mode 100644 index 000000000000..2886a590823d --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6sl.dtsi" + +/ { + model = "Freescale i.MX6 SoloLite EVK Board"; + compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; + + memory { + reg = <0x80000000 0x40000000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; + phy-mode = "rmii"; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 + MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059 + MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059 + MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059 + MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 + >; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_1>; + bus-width = <8>; + cd-gpios = <&gpio4 7 0>; + wp-gpios = <&gpio4 6 0>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + cd-gpios = <&gpio5 0 0>; + wp-gpios = <&gpio4 29 0>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + cd-gpios = <&gpio3 22 0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi new file mode 100644 index 000000000000..c5e5da02d7e3 --- /dev/null +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -0,0 +1,779 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include "skeleton.dtsi" +#include "imx6sl-pinfunc.h" +#include <dt-bindings/clock/imx6sl-clock.h> + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x0>; + next-level-cache = <&L2>; + }; + }; + + intc: interrupt-controller@00a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil { + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + osc { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + L2: l2-cache@00a02000 { + compatible = "arm,pl310-cache"; + reg = <0x00a02000 0x1000>; + interrupts = <0 92 0x04>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <4 2 3>; + arm,data-latency = <4 2 3>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 94 0x04>; + }; + + aips1: aips-bus@02000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba: spba-bus@02000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif: spdif@02004000 { + reg = <0x02004000 0x4000>; + interrupts = <0 52 0x04>; + }; + + ecspi1: ecspi@02008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = <0 31 0x04>; + clocks = <&clks IMX6SL_CLK_ECSPI1>, + <&clks IMX6SL_CLK_ECSPI1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: ecspi@0200c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = <0 32 0x04>; + clocks = <&clks IMX6SL_CLK_ECSPI2>, + <&clks IMX6SL_CLK_ECSPI2>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: ecspi@02010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = <0 33 0x04>; + clocks = <&clks IMX6SL_CLK_ECSPI3>, + <&clks IMX6SL_CLK_ECSPI3>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi4: ecspi@02014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = <0 34 0x04>; + clocks = <&clks IMX6SL_CLK_ECSPI4>, + <&clks IMX6SL_CLK_ECSPI4>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart5: serial@02018000 { + compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; + reg = <0x02018000 0x4000>; + interrupts = <0 30 0x04>; + clocks = <&clks IMX6SL_CLK_UART>, + <&clks IMX6SL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@02020000 { + compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = <0 26 0x04>; + clocks = <&clks IMX6SL_CLK_UART>, + <&clks IMX6SL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@02024000 { + compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; + reg = <0x02024000 0x4000>; + interrupts = <0 27 0x04>; + clocks = <&clks IMX6SL_CLK_UART>, + <&clks IMX6SL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ssi1: ssi@02028000 { + compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi"; + reg = <0x02028000 0x4000>; + interrupts = <0 46 0x04>; + clocks = <&clks IMX6SL_CLK_SSI1>; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + ssi2: ssi@0202c000 { + compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi"; + reg = <0x0202c000 0x4000>; + interrupts = <0 47 0x04>; + clocks = <&clks IMX6SL_CLK_SSI2>; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + ssi3: ssi@02030000 { + compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi"; + reg = <0x02030000 0x4000>; + interrupts = <0 48 0x04>; + clocks = <&clks IMX6SL_CLK_SSI3>; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + uart3: serial@02034000 { + compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; + reg = <0x02034000 0x4000>; + interrupts = <0 28 0x04>; + clocks = <&clks IMX6SL_CLK_UART>, + <&clks IMX6SL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart4: serial@02038000 { + compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; + reg = <0x02038000 0x4000>; + interrupts = <0 29 0x04>; + clocks = <&clks IMX6SL_CLK_UART>, + <&clks IMX6SL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + pwm1: pwm@02080000 { + #pwm-cells = <2>; + compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = <0 83 0x04>; + clocks = <&clks IMX6SL_CLK_PWM1>, + <&clks IMX6SL_CLK_PWM1>; + clock-names = "ipg", "per"; + }; + + pwm2: pwm@02084000 { + #pwm-cells = <2>; + compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = <0 84 0x04>; + clocks = <&clks IMX6SL_CLK_PWM2>, + <&clks IMX6SL_CLK_PWM2>; + clock-names = "ipg", "per"; + }; + + pwm3: pwm@02088000 { + #pwm-cells = <2>; + compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = <0 85 0x04>; + clocks = <&clks IMX6SL_CLK_PWM3>, + <&clks IMX6SL_CLK_PWM3>; + clock-names = "ipg", "per"; + }; + + pwm4: pwm@0208c000 { + #pwm-cells = <2>; + compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = <0 86 0x04>; + clocks = <&clks IMX6SL_CLK_PWM4>, + <&clks IMX6SL_CLK_PWM4>; + clock-names = "ipg", "per"; + }; + + gpt: gpt@02098000 { + compatible = "fsl,imx6sl-gpt"; + reg = <0x02098000 0x4000>; + interrupts = <0 55 0x04>; + clocks = <&clks IMX6SL_CLK_GPT>, + <&clks IMX6SL_CLK_GPT_SERIAL>; + clock-names = "ipg", "per"; + }; + + gpio1: gpio@0209c000 { + compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = <0 66 0x04 0 67 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@020a0000 { + compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = <0 68 0x04 0 69 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@020a4000 { + compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = <0 70 0x04 0 71 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@020a8000 { + compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = <0 72 0x04 0 73 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@020ac000 { + compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = <0 74 0x04 0 75 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + kpp: kpp@020b8000 { + reg = <0x020b8000 0x4000>; + interrupts = <0 82 0x04>; + }; + + wdog1: wdog@020bc000 { + compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = <0 80 0x04>; + clocks = <&clks IMX6SL_CLK_DUMMY>; + }; + + wdog2: wdog@020c0000 { + compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = <0 81 0x04>; + clocks = <&clks IMX6SL_CLK_DUMMY>; + status = "disabled"; + }; + + clks: ccm@020c4000 { + compatible = "fsl,imx6sl-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <0 87 0x04 0 88 0x04>; + #clock-cells = <1>; + }; + + anatop: anatop@020c8000 { + compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus"; + reg = <0x020c8000 0x1000>; + interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; + + regulator-1p1@110 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1375000>; + regulator-always-on; + anatop-reg-offset = <0x110>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <4>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1375000>; + }; + + regulator-3p0@120 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + }; + + regulator-2p5@130 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + anatop-reg-offset = <0x130>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2100000>; + anatop-max-voltage = <2850000>; + }; + + reg_arm: regulator-vddcore@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "cpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_pu: regulator-vddpu@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <9>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <26>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_soc: regulator-vddsoc@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <28>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + }; + + usbphy1: usbphy@020c9000 { + compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = <0 44 0x04>; + clocks = <&clks IMX6SL_CLK_USBPHY1>; + }; + + usbphy2: usbphy@020ca000 { + compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = <0 45 0x04>; + clocks = <&clks IMX6SL_CLK_USBPHY2>; + }; + + snvs@020cc000 { + compatible = "fsl,sec-v4.0-mon", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x020cc000 0x4000>; + + snvs-rtc-lp@34 { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + reg = <0x34 0x58>; + interrupts = <0 19 0x04 0 20 0x04>; + }; + }; + + epit1: epit@020d0000 { + reg = <0x020d0000 0x4000>; + interrupts = <0 56 0x04>; + }; + + epit2: epit@020d4000 { + reg = <0x020d4000 0x4000>; + interrupts = <0 57 0x04>; + }; + + src: src@020d8000 { + compatible = "fsl,imx6sl-src", "fsl,imx51-src"; + reg = <0x020d8000 0x4000>; + interrupts = <0 91 0x04 0 96 0x04>; + #reset-cells = <1>; + }; + + gpc: gpc@020dc000 { + compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupts = <0 89 0x04>; + }; + + iomuxc: iomuxc@020e0000 { + compatible = "fsl,imx6sl-iomuxc"; + reg = <0x020e0000 0x4000>; + + fec { + pinctrl_fec_1: fecgrp-1 { + fsl,pins = < + MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 + MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 + MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 + MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 + MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 + MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 + MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 + MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 + MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8 + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 + >; + }; + }; + + usdhc1 { + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + }; + + usdhc3 { + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + }; + }; + + csi: csi@020e4000 { + reg = <0x020e4000 0x4000>; + interrupts = <0 7 0x04>; + }; + + spdc: spdc@020e8000 { + reg = <0x020e8000 0x4000>; + interrupts = <0 6 0x04>; + }; + + sdma: sdma@020ec000 { + compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = <0 2 0x04>; + clocks = <&clks IMX6SL_CLK_SDMA>, + <&clks IMX6SL_CLK_SDMA>; + clock-names = "ipg", "ahb"; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin"; + }; + + pxp: pxp@020f0000 { + reg = <0x020f0000 0x4000>; + interrupts = <0 98 0x04>; + }; + + epdc: epdc@020f4000 { + reg = <0x020f4000 0x4000>; + interrupts = <0 97 0x04>; + }; + + lcdif: lcdif@020f8000 { + reg = <0x020f8000 0x4000>; + interrupts = <0 39 0x04>; + }; + + dcp: dcp@020fc000 { + reg = <0x020fc000 0x4000>; + interrupts = <0 99 0x04>; + }; + }; + + aips2: aips-bus@02100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + usbotg1: usb@02184000 { + compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = <0 43 0x04>; + clocks = <&clks IMX6SL_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + status = "disabled"; + }; + + usbotg2: usb@02184200 { + compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = <0 40 0x04>; + clocks = <&clks IMX6SL_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + status = "disabled"; + }; + + usbh: usb@02184400 { + compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; + reg = <0x02184400 0x200>; + interrupts = <0 42 0x04>; + clocks = <&clks IMX6SL_CLK_USBOH3>; + fsl,usbmisc = <&usbmisc 2>; + status = "disabled"; + }; + + usbmisc: usbmisc@02184800 { + #index-cells = <1>; + compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + clocks = <&clks IMX6SL_CLK_USBOH3>; + }; + + fec: ethernet@02188000 { + compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; + reg = <0x02188000 0x4000>; + interrupts = <0 114 0x04>; + clocks = <&clks IMX6SL_CLK_ENET_REF>, + <&clks IMX6SL_CLK_ENET_REF>; + clock-names = "ipg", "ahb"; + status = "disabled"; + }; + + usdhc1: usdhc@02190000 { + compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = <0 22 0x04>; + clocks = <&clks IMX6SL_CLK_USDHC1>, + <&clks IMX6SL_CLK_USDHC1>, + <&clks IMX6SL_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: usdhc@02194000 { + compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = <0 23 0x04>; + clocks = <&clks IMX6SL_CLK_USDHC2>, + <&clks IMX6SL_CLK_USDHC2>, + <&clks IMX6SL_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: usdhc@02198000 { + compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; + reg = <0x02198000 0x4000>; + interrupts = <0 24 0x04>; + clocks = <&clks IMX6SL_CLK_USDHC3>, + <&clks IMX6SL_CLK_USDHC3>, + <&clks IMX6SL_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc4: usdhc@0219c000 { + compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; + reg = <0x0219c000 0x4000>; + interrupts = <0 25 0x04>; + clocks = <&clks IMX6SL_CLK_USDHC4>, + <&clks IMX6SL_CLK_USDHC4>, + <&clks IMX6SL_CLK_USDHC4>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + i2c1: i2c@021a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = <0 36 0x04>; + clocks = <&clks IMX6SL_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@021a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = <0 37 0x04>; + clocks = <&clks IMX6SL_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@021a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = <0 38 0x04>; + clocks = <&clks IMX6SL_CLK_I2C3>; + status = "disabled"; + }; + + mmdc: mmdc@021b0000 { + compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + }; + + rngb: rngb@021b4000 { + reg = <0x021b4000 0x4000>; + interrupts = <0 5 0x04>; + }; + + weim: weim@021b8000 { + reg = <0x021b8000 0x4000>; + interrupts = <0 14 0x04>; + }; + + ocotp: ocotp@021bc000 { + compatible = "fsl,imx6sl-ocotp"; + reg = <0x021bc000 0x4000>; + }; + + audmux: audmux@021d8000 { + compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux"; + reg = <0x021d8000 0x4000>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index c9c3fa344647..b6b82eca8d1e 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -39,6 +39,47 @@ valid-mask = <0x003fffff>; }; + pci: pciv3@62000000 { + compatible = "v3,v360epc-pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x62000000 0x10000>; + interrupt-parent = <&pic>; + interrupts = <17>; /* Bus error IRQ */ + ranges = <0x00000000 0 0x61000000 /* config space */ + 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */ + 0x01000000 0 0x0 /* I/O space */ + 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */ + 0x02000000 0 0x00000000 /* non-prefectable memory */ + 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */ + 0x42000000 0 0x10000000 /* prefetchable memory */ + 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */ + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = < + /* IDSEL 9 */ + 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ + 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ + 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ + 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ + /* IDSEL 10 */ + 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ + 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ + 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ + 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ + /* IDSEL 11 */ + 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ + 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ + 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ + 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ + /* IDSEL 12 */ + 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ + 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ + 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ + 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ + >; + }; + fpga { /* * The Integator/AP predates the idea to have magic numbers diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts new file mode 100644 index 000000000000..1334b42c6b77 --- /dev/null +++ b/arch/arm/boot/dts/keystone.dts @@ -0,0 +1,117 @@ +/* + * Copyright 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +/include/ "skeleton.dtsi" + +/ { + model = "Texas Instruments Keystone 2 SoC"; + compatible = "ti,keystone-evm"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + }; + + memory { + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; + }; + + gic: interrupt-controller { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + #address-cells = <1>; + interrupt-controller; + reg = <0x0 0x02561000 0x0 0x1000>, + <0x0 0x02562000 0x0 0x2000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0x308>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <0 20 0xf01>, + <0 21 0xf01>, + <0 22 0xf01>, + <0 23 0xf01>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ti,keystone","simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0x0 0x0 0xc0000000>; + + rstctrl: reset-controller { + compatible = "ti,keystone-reset"; + reg = <0x023100e8 4>; /* pll reset control reg */ + }; + + uart0: serial@02530c00 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02530c00 0x100>; + clock-frequency = <133120000>; + interrupts = <0 277 0xf01>; + }; + + uart1: serial@02531000 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02531000 0x100>; + clock-frequency = <133120000>; + interrupts = <0 280 0xf01>; + }; + + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index d6c9d65cbaeb..1e5bef0bead7 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -40,5 +40,64 @@ marvell,function = "sdio"; }; }; + + pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + }; + + rtc@10300 { + compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <53>; + clocks = <&gate_clk 7>; + }; + + sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <21>; + clocks = <&gate_clk 14>, <&gate_clk 15>; + clock-names = "0", "1"; + status = "disabled"; + }; + + mvsdio@90000 { + compatible = "marvell,orion-sdio"; + reg = <0x90000 0x200>; + interrupts = <28>; + clocks = <&gate_clk 4>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 23991e45bc55..a63a11137262 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -49,6 +49,34 @@ }; }; + rtc@10300 { + compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <53>; + clocks = <&gate_clk 7>; + }; + + sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <21>; + clocks = <&gate_clk 14>, <&gate_clk 15>; + clock-names = "0", "1"; + status = "disabled"; + }; + + mvsdio@90000 { + compatible = "marvell,orion-sdio"; + reg = <0x90000 0x200>; + interrupts = <28>; + clocks = <&gate_clk 4>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; + thermal@10078 { compatible = "marvell,kirkwood-thermal"; reg = <0x10078 0x4>; @@ -65,5 +93,53 @@ clocks = <&gate_clk 7>; status = "disabled"; }; + + pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x00044000 0x00044000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 10>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 18>; + status = "disabled"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 5f21d4e427b0..00c48d26de68 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts @@ -18,10 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - pinctrl-0 = < &pmx_spi &pmx_uart0 - &pmx_cloudbox_sata0 >; - pinctrl-names = "default"; - pmx_cloudbox_sata0: pmx-cloudbox-sata0 { marvell,pins = "mpp15"; marvell,function = "sata0"; @@ -29,16 +25,22 @@ }; serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; clock-frequency = <166666667>; status = "okay"; }; sata@80000 { + pinctrl-0 = <&pmx_cloudbox_sata0>; + pinctrl-names = "default"; status = "okay"; nr-ports = <1>; }; spi@10600 { + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; status = "okay"; flash@0 { diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts new file mode 100644 index 000000000000..9d777edd1f36 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts @@ -0,0 +1,30 @@ +/* + * Marvell DB-88F6281-BP Development Board Setup + * + * Saeed Bishara <saeed@marvell.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +/include/ "kirkwood-db.dtsi" +/include/ "kirkwood-6281.dtsi" + +/ { + model = "Marvell DB-88F6281-BP Development Board"; + compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts new file mode 100644 index 000000000000..f4c852886d23 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts @@ -0,0 +1,34 @@ +/* + * Marvell DB-88F6282-BP Development Board Setup + * + * Saeed Bishara <saeed@marvell.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +/include/ "kirkwood-db.dtsi" +/include/ "kirkwood-6282.dtsi" + +/ { + model = "Marvell DB-88F6282-BP Development Board"; + compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + ocp@f1000000 { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + + pcie@2,0 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi new file mode 100644 index 000000000000..c87cfb816120 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-db.dtsi @@ -0,0 +1,89 @@ +/* + * Marvell DB-{88F6281,88F6282}-BP Development Board Setup + * + * Saeed Bishara <saeed@marvell.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions that are common between the 6281 + * and 6282 variants of the Marvell Kirkwood Development Board. + */ + +/include/ "kirkwood.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + ocp@f1000000 { + pinctrl@10000 { + pmx_sdio_gpios: pmx-sdio-gpios { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + clock-frequency = <200000000>; + status = "ok"; + }; + + nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + chip-delay = <25>; + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x400000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x1fb00000>; + }; + }; + + sata@80000 { + nr-ports = <2>; + status = "okay"; + }; + + ehci@50000 { + status = "okay"; + }; + + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio_gpios>; + pinctrl-names = "default"; + wp-gpios = <&gpio1 5 0>; + cd-gpios = <&gpio1 6 0>; + status = "okay"; + }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts index c9c44b2f62d7..14d4ceea3057 100644 --- a/arch/arm/boot/dts/kirkwood-dns320.dts +++ b/arch/arm/boot/dts/kirkwood-dns320.dts @@ -17,6 +17,11 @@ gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_320 + &pmx_led_red_left_hdd &pmx_led_red_right_hdd + &pmx_led_white_usb>; + pinctrl-names = "default"; + blue-power { label = "dns320:blue:power"; gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */ @@ -46,6 +51,8 @@ }; serial@12100 { + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts index e4e4930dc5cf..63872570e6ce 100644 --- a/arch/arm/boot/dts/kirkwood-dns325.dts +++ b/arch/arm/boot/dts/kirkwood-dns325.dts @@ -17,6 +17,11 @@ gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325 + &pmx_led_red_left_hdd &pmx_led_red_right_hdd + &pmx_led_white_usb>; + pinctrl-names = "default"; + white-power { label = "dns325:white:power"; gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */ diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index 6875ac00c174..0afe1d07c803 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -9,6 +9,10 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_button_power &pmx_button_unmount + &pmx_button_reset>; + pinctrl-names = "default"; + button@1 { label = "Power button"; linux,code = <116>; @@ -29,6 +33,8 @@ gpio_fan { /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */ compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>; + pinctrl-names = "default"; gpios = <&gpio1 14 1 &gpio1 13 1>; gpio-fan,speed-map = <0 0 @@ -38,27 +44,17 @@ gpio_poweroff { compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_power_off>; + pinctrl-names = "default"; gpios = <&gpio1 4 0>; }; ocp@f1000000 { pinctrl: pinctrl@10000 { - pinctrl-0 = < &pmx_nand &pmx_uart1 - &pmx_sata0 &pmx_sata1 - &pmx_led_power - &pmx_led_red_right_hdd - &pmx_led_red_left_hdd - &pmx_led_red_usb_325 - &pmx_button_power - &pmx_led_red_usb_320 - &pmx_power_off &pmx_power_back_on - &pmx_power_sata0 &pmx_power_sata1 - &pmx_present_sata0 &pmx_present_sata1 - &pmx_led_white_usb &pmx_fan_tacho - &pmx_fan_high_speed &pmx_fan_low_speed - &pmx_button_unmount &pmx_button_reset - &pmx_temp_alarm >; + pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0 + &pmx_present_sata1 &pmx_fan_tacho + &pmx_temp_alarm>; pinctrl-names = "default"; pmx_sata0: pmx-sata0 { @@ -147,11 +143,15 @@ }; }; sata@80000 { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; status = "okay"; nr-ports = <2>; }; nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; status = "okay"; chip-delay = <35>; @@ -192,6 +192,8 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; + pinctrl-names = "default"; sata0_power: regulator@1 { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index 0196cf6b0ef2..7714742bb8d8 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -18,11 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_usb_power_enable - &pmx_led_green &pmx_led_orange >; - pinctrl-names = "default"; - pmx_usb_power_enable: pmx-usb-power-enable { marvell,pins = "mpp29"; marvell,function = "gpio"; @@ -62,6 +57,8 @@ }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_green &pmx_led_orange>; + pinctrl-names = "default"; health { label = "status:green:health"; @@ -77,6 +74,8 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; usb_power: regulator@1 { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts index 289e51d86372..36c7ba38d500 100644 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts @@ -18,12 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_spi - &pmx_led_bluetooth &pmx_led_wifi - &pmx_led_wifi_ap >; - pinctrl-names = "default"; - pmx_led_bluetooth: pmx-led-bluetooth { marvell,pins = "mpp47"; marvell,function = "gpio"; @@ -43,6 +37,8 @@ spi@10600 { status = "okay"; + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; m25p40@0 { #address-cells = <1>; @@ -79,11 +75,15 @@ pinctrl-names = "default"; status = "okay"; /* No CD or WP GPIOs */ + broken-cd; }; }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi + &pmx_led_wifi_ap >; + pinctrl-names = "default"; bluetooth { label = "dreamplug:blue:bluetooth"; diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index c3573be7b92c..31caa6405065 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -18,15 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange - &pmx_led_left_cap_0 &pmx_led_left_cap_1 - &pmx_led_left_cap_2 &pmx_led_left_cap_3 - &pmx_led_right_cap_0 &pmx_led_right_cap_1 - &pmx_led_right_cap_2 &pmx_led_right_cap_3 - >; - pinctrl-names = "default"; - pmx_usb_power_enable: pmx-usb-power-enable { marvell,pins = "mpp29"; marvell,function = "gpio"; @@ -109,6 +100,13 @@ }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_orange + &pmx_led_left_cap_0 &pmx_led_left_cap_1 + &pmx_led_left_cap_2 &pmx_led_left_cap_3 + &pmx_led_right_cap_0 &pmx_led_right_cap_1 + &pmx_led_right_cap_2 &pmx_led_right_cap_3 + >; + pinctrl-names = "default"; health { label = "status:green:health"; @@ -156,6 +154,8 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; usb_power: regulator@1 { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 44fd97dfc1f3..1e642f39b154 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -18,11 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g - &pmx_led_wmode_r &pmx_led_wmode_g >; - pinctrl-names = "default"; - pmx_led_health_r: pmx-led-health-r { marvell,pins = "mpp46"; marvell,function = "gpio"; @@ -72,11 +67,16 @@ mvsdio@90000 { status = "okay"; + /* No CD or WP GPIOs */ + broken-cd; }; }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g + &pmx_led_wmode_r &pmx_led_wmode_g >; + pinctrl-names = "default"; health-r { label = "guruplug:red:health"; diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index 5335b1aa8601..20c4b081f420 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -18,13 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_nand - &pmx_led_os_red &pmx_power_off - &pmx_led_os_green &pmx_led_usb_transfer - &pmx_button_reset &pmx_button_usb_copy >; - pinctrl-names = "default"; - pmx_led_os_red: pmx-led-os-red { marvell,pins = "mpp22"; marvell,function = "gpio"; @@ -61,6 +54,8 @@ nand@3000000 { status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; partition@0 { label = "u-boot"; @@ -84,6 +79,9 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>; + pinctrl-names = "default"; + button@1 { label = "USB Copy"; linux,code = <133>; @@ -97,6 +95,9 @@ }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green + &pmx_led_usb_transfer>; + pinctrl-names = "default"; green-os { label = "ib62x0:green:os"; @@ -114,6 +115,8 @@ }; gpio_poweroff { compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_power_off>; + pinctrl-names = "default"; gpios = <&gpio0 24 0>; }; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 12ccf74ac3c4..441204e8abc6 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -20,51 +20,43 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_gpio_12 &pmx_gpio_35 - &pmx_gpio_41 &pmx_gpio_42 - &pmx_gpio_43 &pmx_gpio_44 - &pmx_gpio_45 &pmx_gpio_46 - &pmx_gpio_47 &pmx_gpio_48 >; - pinctrl-names = "default"; - - pmx_gpio_12: pmx-gpio-12 { + pmx_button_reset: pmx-button-reset { marvell,pins = "mpp12"; marvell,function = "gpio"; }; - pmx_gpio_35: pmx-gpio-35 { + pmx_button_otb: pmx-button-otb { marvell,pins = "mpp35"; marvell,function = "gpio"; }; - pmx_gpio_41: pmx-gpio-41 { + pmx_led_level: pmx-led-level { marvell,pins = "mpp41"; marvell,function = "gpio"; }; - pmx_gpio_42: pmx-gpio-42 { + pmx_led_power_blue: pmx-led-power-blue { marvell,pins = "mpp42"; marvell,function = "gpio"; }; - pmx_gpio_43: pmx-gpio-43 { + pmx_led_power_red: pmx-power-red { marvell,pins = "mpp43"; marvell,function = "gpio"; }; - pmx_gpio_44: pmx-gpio-44 { + pmx_led_usb1: pmx-led-usb1 { marvell,pins = "mpp44"; marvell,function = "gpio"; }; - pmx_gpio_45: pmx-gpio-45 { + pmx_led_usb2: pmx-led-usb2 { marvell,pins = "mpp45"; marvell,function = "gpio"; }; - pmx_gpio_46: pmx-gpio-46 { + pmx_led_usb3: pmx-led-usb3 { marvell,pins = "mpp46"; marvell,function = "gpio"; }; - pmx_gpio_47: pmx-gpio-47 { + pmx_led_usb4: pmx-led-usb4 { marvell,pins = "mpp47"; marvell,function = "gpio"; }; - pmx_gpio_48: pmx-gpio-48 { + pmx_led_otb: pmx-led-otb { marvell,pins = "mpp48"; marvell,function = "gpio"; }; @@ -109,10 +101,23 @@ reg = <0x980000 0x1f400000>; }; }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_level &pmx_led_power_blue + &pmx_led_power_red &pmx_led_usb1 + &pmx_led_usb2 &pmx_led_usb3 + &pmx_led_usb4 &pmx_led_otb >; + pinctrl-names = "default"; led-level { label = "led_level"; @@ -154,6 +159,9 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = < &pmx_button_reset &pmx_button_otb >; + pinctrl-names = "default"; + button@1 { label = "OTB Button"; linux,code = <133>; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 3694e94f6e99..00a7bfe5e83b 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -18,12 +18,7 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_button_reset &pmx_button_power - &pmx_led_backup &pmx_led_power - &pmx_button_otb &pmx_led_rebuild - &pmx_led_health - &pmx_led_sata_brt_ctrl_1 + pinctrl-0 = < &pmx_led_sata_brt_ctrl_1 &pmx_led_sata_brt_ctrl_2 &pmx_led_backup_brt_ctrl_1 &pmx_led_backup_brt_ctrl_2 @@ -151,6 +146,9 @@ }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_backup &pmx_led_power + &pmx_led_rebuild &pmx_led_health >; + pinctrl-names = "default"; power_led { label = "status:white:power_led"; @@ -174,6 +172,11 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_button_reset &pmx_button_power + &pmx_button_otb>; + pinctrl-names = "default"; + + Power { label = "Power Button"; linux,code = <116>; diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts index 0bdce0ad7277..c3f036b86cca 100644 --- a/arch/arm/boot/dts/kirkwood-is2.dts +++ b/arch/arm/boot/dts/kirkwood-is2.dts @@ -13,6 +13,8 @@ ocp@f1000000 { sata@80000 { + pinctrl-0 = <&pmx_ns2_sata0>; + pinctrl-names = "default"; status = "okay"; nr-ports = <1>; }; diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index 5bbd0542cdd3..5d9f5ea78700 100644 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts @@ -18,9 +18,7 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_nand &pmx_i2c_gpio_sda - &pmx_i2c_gpio_scl >; + pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >; pinctrl-names = "default"; pmx_i2c_gpio_sda: pmx-gpio-sda { @@ -38,8 +36,17 @@ }; nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; status = "ok"; chip-delay = <25>; }; }; + + i2c@0 { + compatible = "i2c-gpio"; + gpios = < &gpio0 8 0 /* sda */ + &gpio0 9 0 >; /* scl */ + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + }; }; diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 37d45c4f88fb..31b17f5b9d28 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -8,16 +8,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_power_hdd &pmx_usb_vbus - &pmx_fan_low &pmx_fan_high - &pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_fan_lock &pmx_button_function - &pmx_power_switch &pmx_power_auto_switch - &pmx_led_function_blue >; - pinctrl-names = "default"; - pmx_power_hdd: pmx-power-hdd { marvell,pins = "mpp10"; marvell,function = "gpo"; @@ -112,6 +102,10 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_button_function &pmx_power_switch + &pmx_power_auto_switch>; + pinctrl-names = "default"; + button@1 { label = "Function Button"; linux,code = <357>; @@ -133,6 +127,10 @@ gpio_leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm + &pmx_led_info &pmx_led_power + &pmx_led_function_blue>; + pinctrl-names = "default"; led@1 { label = "lsxl:blue:func"; @@ -163,6 +161,8 @@ gpio_fan { compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; + pinctrl-names = "default"; gpios = <&gpio0 19 1 &gpio0 18 1>; gpio-fan,speed-map = <0 3 @@ -172,10 +172,16 @@ alarm-gpios = <&gpio1 8 0>; }; + restart_poweroff { + compatible = "restart-poweroff"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>; + pinctrl-names = "default"; usb_power: regulator@1 { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 758824118a9a..6179333fd71f 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -18,16 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_nand &pmx_uart0 - &pmx_led_health - &pmx_sata0 &pmx_sata1 - &pmx_led_user1o - &pmx_led_user1g &pmx_led_user0o - &pmx_led_user0g &pmx_led_misc - >; - pinctrl-names = "default"; - pmx_led_health: pmx-led-health { marvell,pins = "mpp7"; marvell,function = "gpo"; @@ -91,9 +81,13 @@ serial@12000 { status = "ok"; + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; }; nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; status = "okay"; partition@0 { @@ -127,22 +121,37 @@ }; sata@80000 { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; nr-ports = <2>; status = "okay"; - }; mvsdio@90000 { pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; pinctrl-names = "default"; status = "okay"; - cd-gpios = <&gpio1 15 0>; + cd-gpios = <&gpio1 15 1>; /* No WP GPIO */ }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_health + &pmx_led_user1o + &pmx_led_user1g &pmx_led_user0o + &pmx_led_user0g &pmx_led_misc + >; + pinctrl-names = "default"; health { label = "status:green:health"; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index 1ca66ab83ad6..ad6ade7d9191 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -18,18 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_uart0 - &pmx_button_power - &pmx_button_backup - &pmx_button_reset - &pmx_led_blue_power - &pmx_led_blue_activity - &pmx_led_blue_disk1 - &pmx_led_blue_disk2 - &pmx_led_blue_backup >; - pinctrl-names = "default"; - pmx_button_power: pmx-button-power { marvell,pins = "mpp47"; marvell,function = "gpio"; @@ -74,6 +62,8 @@ }; serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; status = "okay"; }; @@ -111,10 +101,22 @@ status = "okay"; nr-ports = <2>; }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_activity + &pmx_led_blue_disk1 &pmx_led_blue_disk2 + &pmx_led_blue_backup >; + pinctrl-names = "default"; power_led { label = "status:blue:power_led"; @@ -143,6 +145,10 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_button_power &pmx_button_backup + &pmx_button_reset>; + pinctrl-names = "default"; + button@1 { label = "Power Button"; linux,code = <116>; /* KEY_POWER */ diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index 6affd924fe11..2afac0405816 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi @@ -8,10 +8,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - pinctrl-0 = < &pmx_spi &pmx_twsi0 &pmx_uart0 - &pmx_ns2_sata0 &pmx_ns2_sata1>; - pinctrl-names = "default"; - pmx_ns2_sata0: pmx-ns2-sata0 { marvell,pins = "mpp21"; marvell,function = "sata0"; @@ -23,10 +19,14 @@ }; serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; status = "okay"; }; spi@10600 { + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; status = "okay"; flash@0 { @@ -45,6 +45,8 @@ }; i2c@11000 { + pinctrl-0 = <&pmx_twsi0>; + pinctrl-names = "default"; status = "okay"; eeprom@50 { diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts index f2d36ecf36d8..b50e93d7796c 100644 --- a/arch/arm/boot/dts/kirkwood-ns2.dts +++ b/arch/arm/boot/dts/kirkwood-ns2.dts @@ -13,6 +13,8 @@ ocp@f1000000 { sata@80000 { + pinctrl-0 = <&pmx_ns2_sata0>; + pinctrl-names = "default"; status = "okay"; nr-ports = <1>; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts index b02eb4ea1bb4..af8259fe8955 100644 --- a/arch/arm/boot/dts/kirkwood-ns2lite.dts +++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts @@ -13,6 +13,8 @@ ocp@f1000000 { sata@80000 { + pinctrl-0 = <&pmx_ns2_sata0>; + pinctrl-names = "default"; status = "okay"; nr-ports = <1>; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts index bcec4d6cada7..85f24d227e17 100644 --- a/arch/arm/boot/dts/kirkwood-ns2max.dts +++ b/arch/arm/boot/dts/kirkwood-ns2max.dts @@ -13,6 +13,8 @@ ocp@f1000000 { sata@80000 { + pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>; + pinctrl-names = "default"; status = "okay"; nr-ports = <2>; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts index adab1ab25733..329e530bffe7 100644 --- a/arch/arm/boot/dts/kirkwood-ns2mini.dts +++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts @@ -14,6 +14,8 @@ ocp@f1000000 { sata@80000 { + pinctrl-0 = <&pmx_ns2_sata0>; + pinctrl-names = "default"; status = "okay"; nr-ports = <1>; }; diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index a7412b937a8a..69003598f5fa 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "kirkwood.dtsi" +/include/ "kirkwood-6281.dtsi" / { model = "ZyXEL NSA310"; @@ -17,22 +18,7 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - pinctrl-0 = < &pmx_led_esata_green - &pmx_led_esata_red - &pmx_led_usb_green - &pmx_led_usb_red - &pmx_usb_power_off - &pmx_led_sys_green - &pmx_led_sys_red - &pmx_btn_reset - &pmx_btn_copy - &pmx_led_copy_green - &pmx_led_copy_red - &pmx_led_hdd_green - &pmx_led_hdd_red - &pmx_unknown - &pmx_btn_power - &pmx_pwr_off >; + pinctrl-0 = <&pmx_unknown>; pinctrl-names = "default"; pmx_led_esata_green: pmx-led-esata-green { @@ -176,12 +162,22 @@ reg = <0x5040000 0x2fc0000>; }; }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio_keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; + pinctrl-names = "default"; button@1 { label = "Power Button"; @@ -202,6 +198,12 @@ gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red + &pmx_led_usb_green &pmx_led_usb_red + &pmx_led_sys_green &pmx_led_sys_red + &pmx_led_copy_green &pmx_led_copy_red + &pmx_led_hdd_green &pmx_led_hdd_red>; + pinctrl-names = "default"; green-sys { label = "nsa310:green:sys"; @@ -247,6 +249,8 @@ gpio_poweroff { compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_pwr_off>; + pinctrl-names = "default"; gpios = <&gpio1 16 0>; }; @@ -254,6 +258,8 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_off>; + pinctrl-names = "default"; usb0_power_off: regulator@1 { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index d27f7245f8e7..38dc8517d777 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -19,15 +19,21 @@ ocp@f1000000 { serial@12000 { status = "ok"; + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; }; serial@12100 { status = "ok"; + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; }; nand@3000000 { chip-delay = <25>; status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; partition@0 { label = "uboot"; @@ -67,6 +73,8 @@ i2c@11100 { status = "okay"; + pinctrl-0 = <&pmx_twsi1>; + pinctrl-names = "default"; s35390a: s35390a@30 { compatible = "s35390a"; @@ -75,16 +83,7 @@ }; pinctrl: pinctrl@10000 { - pinctrl-0 = < &pmx_nand &pmx_uart0 - &pmx_uart1 &pmx_twsi1 - &pmx_dip_sw0 &pmx_dip_sw1 - &pmx_dip_sw2 &pmx_dip_sw3 - &pmx_gpio_0 &pmx_gpio_1 - &pmx_gpio_2 &pmx_gpio_3 - &pmx_gpio_4 &pmx_gpio_5 - &pmx_gpio_6 &pmx_gpio_7 - &pmx_led_red &pmx_led_green - &pmx_led_yellow >; + pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; pinctrl-names = "default"; pmx_uart0: pmx-uart0 { @@ -104,63 +103,14 @@ marvell,function = "sysrst"; }; - pmx_dip_sw0: pmx-dip-sw0 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_dip_sw1: pmx-dip-sw1 { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_dip_sw2: pmx-dip-sw2 { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_dip_sw3: pmx-dip-sw3 { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - pmx_gpio_0: pmx-gpio-0 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_gpio_1: pmx-gpio-1 { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - - pmx_gpio_2: pmx-gpio-2 { - marvell,pins = "mpp26"; + pmx_dip_switches: pmx-dip-switches { + marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23"; marvell,function = "gpio"; }; - pmx_gpio_3: pmx-gpio-3 { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - pmx_gpio_4: pmx-gpio-4 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_gpio_5: pmx-gpio-5 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_gpio_6: pmx-gpio-6 { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; - - pmx_gpio_7: pmx-gpio-7 { - marvell,pins = "mpp31"; + pmx_gpio_header: pmx-gpio-header { + marvell,pins = "mpp24", "mpp25", "mpp26", "mpp27", + "mpp28", "mpp29", "mpp30", "mpp31"; marvell,function = "gpio"; }; @@ -174,18 +124,8 @@ marvell,function = "gpio"; }; - pmx_led_red: pmx-led-red { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_green: pmx-led-green { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_led_yellow: pmx-led-yellow { - marvell,pins = "mpp43"; + pmx_leds: pmx-leds { + marvell,pins = "mpp41", "mpp42", "mpp43"; marvell,function = "gpio"; }; }; @@ -193,6 +133,8 @@ gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_leds>; + pinctrl-names = "default"; led-red { label = "obsa6:red:stat"; @@ -209,4 +151,18 @@ gpios = <&gpio1 11 1>; }; }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_gpio_init>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + label = "Init Button"; + linux,code = <116>; + gpios = <&gpio1 6 0>; + }; + }; }; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi new file mode 100644 index 000000000000..f7143f128504 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi @@ -0,0 +1,93 @@ +/* + * kirkwood-sheevaplug-common.dts - Common parts for Sheevaplugs + * + * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com> + * + * Licensed under GPLv2 + */ + +/include/ "kirkwood.dtsi" +/include/ "kirkwood-6281.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + pmx_led_red: pmx-led-red { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_led_blue: pmx-led-blue { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + pmx_sdio_wp: pmx-sdio-wp { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; + serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + status = "okay"; + }; + + nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@500000 { + label = "root"; + reg = <0x0500000 0x1fb00000>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 29 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts new file mode 100644 index 000000000000..f620ce48de97 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts @@ -0,0 +1,43 @@ +/* + * kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug + * + * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com> + * + * Licensed under GPLv2 + */ + +/dts-v1/; + +/include/ "kirkwood-sheevaplug-common.dtsi" + +/ { + model = "Globalscale Technologies eSATA SheevaPlug"; + compatible = "globalscale,sheevaplug-esata-rev13", "globalscale,sheevaplug-esata", "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; + pinctrl-names = "default"; + status = "okay"; + cd-gpios = <&gpio1 12 1>; + wp-gpios = <&gpio1 15 0>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_blue>; + pinctrl-names = "default"; + + health { + label = "sheevaplug:blue:health"; + gpios = <&gpio1 17 1>; + linux,default-trigger = "default-on"; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts new file mode 100644 index 000000000000..bf1dff251432 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts @@ -0,0 +1,43 @@ +/* + * kirkwood-sheevaplug-esata.dts - Device tree file for Sheevaplug + * + * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com> + * + * Licensed under GPLv2 + */ + +/dts-v1/; + +/include/ "kirkwood-sheevaplug-common.dtsi" + +/ { + model = "Globalscale Technologies SheevaPlug"; + compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio>; + pinctrl-names = "default"; + status = "okay"; + /* No CD or WP GPIOs */ + broken-cd; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_blue &pmx_led_red>; + pinctrl-names = "default"; + + health { + label = "sheevaplug:blue:health"; + gpios = <&gpio1 17 1>; + linux,default-trigger = "default-on"; + }; + + misc { + label = "sheevaplug:red:misc"; + gpios = <&gpio1 14 1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index 66eb45b00b25..f2052d7bc10f 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts @@ -19,18 +19,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { /* - * GPIO LED layout - * - * /-SYS_LED(2) - * | - * | /-DISK_LED - * | | - * | | /-WLAN_LED(2) - * | | | - * [SW] [*] [*] [*] - */ - - /* * Switch positions * * /-SW_LEFT(2) @@ -41,19 +29,8 @@ * | | | * PS [L] [I] [R] LEDS */ - pinctrl-0 = < &pmx_led_disk_yellow - &pmx_sata0_pwr_enable - &pmx_led_sys_red - &pmx_led_sys_blue - &pmx_led_wifi_green - &pmx_sw_left - &pmx_sw_right - &pmx_sw_idle - &pmx_sw_left2 - &pmx_led_wifi_yellow - &pmx_uart0 - &pmx_nand - &pmx_twsi0 >; + pinctrl-0 = <&pmx_sw_left &pmx_sw_right + &pmx_sw_idle &pmx_sw_left2>; pinctrl-names = "default"; pmx_led_disk_yellow: pmx-led-disk-yellow { @@ -109,10 +86,14 @@ serial@12000 { status = "ok"; + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; }; nand@3000000 { status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; partition@0 { label = "u-boot"; @@ -147,6 +128,8 @@ i2c@11000 { status = "ok"; + pinctrl-0 = <&pmx_twsi0>; + pinctrl-names = "default"; }; mvsdio@90000 { @@ -154,11 +137,28 @@ pinctrl-names = "default"; status = "okay"; /* No CD or WP GPIOs */ + broken-cd; }; }; gpio-leds { + /* + * GPIO LED layout + * + * /-SYS_LED(2) + * | + * | /-DISK_LED + * | | + * | | /-WLAN_LED(2) + * | | | + * [SW] [*] [*] [*] + */ + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_disk_yellow &pmx_led_sys_red + &pmx_led_sys_blue &pmx_led_wifi_green + &pmx_led_wifi_yellow>; + pinctrl-names = "default"; disk { label = "topkick:yellow:disk"; @@ -187,6 +187,8 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_sata0_pwr_enable>; + pinctrl-names = "default"; sata0_power: regulator@1 { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts index 8295c833887f..6dd1038e4de4 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts @@ -1,16 +1,14 @@ /dts-v1/; -/include/ "kirkwood-ts219.dtsi" +/include/ "kirkwood.dtsi" /include/ "kirkwood-6281.dtsi" +/include/ "kirkwood-ts219.dtsi" / { ocp@f1000000 { pinctrl: pinctrl@10000 { - pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi - &pmx_twsi0 &pmx_sata0 &pmx_sata1 - &pmx_ram_size &pmx_reset_button - &pmx_USB_copy_button &pmx_board_id>; + pinctrl-0 = <&pmx_ram_size &pmx_board_id>; pinctrl-names = "default"; pmx_ram_size: pmx-ram-size { @@ -38,6 +36,9 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; + pinctrl-names = "default"; + button@1 { label = "USB Copy"; linux,code = <133>; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index df3f95dfba33..6fdc5ffcaae5 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts @@ -1,16 +1,14 @@ /dts-v1/; -/include/ "kirkwood-ts219.dtsi" +/include/ "kirkwood.dtsi" /include/ "kirkwood-6282.dtsi" +/include/ "kirkwood-ts219.dtsi" / { ocp@f1000000 { pinctrl: pinctrl@10000 { - pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi - &pmx_twsi0 &pmx_sata0 &pmx_sata1 - &pmx_ram_size &pmx_reset_button - &pmx_USB_copy_button &pmx_board_id>; + pinctrl-0 = <&pmx_ram_size &pmx_board_id>; pinctrl-names = "default"; pmx_ram_size: pmx-ram-size { @@ -32,12 +30,23 @@ marvell,function = "gpio"; }; }; + pcie-controller { + status = "okay"; + + pcie@2,0 { + status = "okay"; + }; + }; + }; gpio_keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; + pinctrl-names = "default"; + button@1 { label = "USB Copy"; linux,code = <133>; diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 64ea27cb3298..0c9a94cd666c 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@ -1,5 +1,3 @@ -/include/ "kirkwood.dtsi" - / { model = "QNAP TS219 family"; compatible = "qnap,ts219", "marvell,kirkwood"; @@ -17,6 +15,8 @@ i2c@11000 { status = "okay"; clock-frequency = <400000>; + pinctrl-0 = <&pmx_twsi0>; + pinctrl-names = "default"; s35390a: s35390a@30 { compatible = "s35390a"; @@ -26,13 +26,24 @@ serial@12000 { clock-frequency = <200000000>; status = "okay"; + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; }; serial@12100 { clock-frequency = <200000000>; status = "okay"; + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; + }; + poweroff@12100 { + compatible = "qnap,power-off"; + reg = <0x12000 0x100>; + clocks = <&gate_clk 7>; }; spi@10600 { status = "okay"; + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; m25p128@0 { #address-cells = <1>; @@ -71,8 +82,17 @@ }; }; sata@80000 { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; status = "okay"; nr-ports = <2>; }; + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index fada7e6d24d8..9809fc1f105c 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -4,6 +4,18 @@ compatible = "marvell,kirkwood"; interrupt-parent = <&intc>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,feroceon"; + clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; + clock-names = "cpu_clk", "ddrclk", "powersave"; + }; + }; + aliases { gpio0 = &gpio0; gpio1 = &gpio1; @@ -18,7 +30,9 @@ ocp@f1000000 { compatible = "simple-bus"; - ranges = <0x00000000 0xf1000000 0x4000000 + ranges = <0x00000000 0xf1000000 0x0100000 + 0xe0000000 0xe0000000 0x8100000 /* PCIE */ + 0xf4000000 0xf4000000 0x0000400 0xf5000000 0xf5000000 0x0000400>; #address-cells = <1>; #size-cells = <1>; @@ -71,13 +85,6 @@ status = "disabled"; }; - rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - spi@10600 { compatible = "marvell,orion-spi"; #address-cells = <1>; @@ -151,15 +158,6 @@ status = "okay"; }; - sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - status = "disabled"; - }; - nand@3000000 { #address-cells = <1>; #size-cells = <1>; @@ -167,7 +165,7 @@ ale = <1>; bank-width = <1>; compatible = "marvell,orion-nand"; - reg = <0x3000000 0x400>; + reg = <0xf4000000 0x400>; chip-delay = <25>; /* set partition map and/or chip-delay in board dts */ clocks = <&gate_clk 7>; @@ -194,13 +192,5 @@ clocks = <&gate_clk 17>; status = "okay"; }; - - mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - status = "disabled"; - }; }; }; diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts index b4dc3ed9a3ec..02df1914a47c 100644 --- a/arch/arm/boot/dts/kizbox.dts +++ b/arch/arm/boot/dts/kizbox.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ /dts-v1/; -/include/ "at91sam9g20.dtsi" +#include "at91sam9g20.dtsi" / { @@ -94,26 +94,26 @@ led1g { label = "led1:green"; - gpios = <&pioB 0 1>; + gpios = <&pioB 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; led1r { label = "led1:red"; - gpios = <&pioB 1 1>; + gpios = <&pioB 1 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; led2g { label = "led2:green"; - gpios = <&pioB 2 1>; + gpios = <&pioB 2 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; default-state = "on"; }; led2r { label = "led2:red"; - gpios = <&pioB 3 1>; + gpios = <&pioB 3 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; }; @@ -125,16 +125,16 @@ reset { label = "reset"; - gpios = <&pioB 30 1>; + gpios = <&pioB 30 GPIO_ACTIVE_LOW>; linux,code = <0x100>; gpio-key,wakeup; }; mode { label = "mode"; - gpios = <&pioB 31 1>; + gpios = <&pioB 31 GPIO_ACTIVE_LOW>; linux,code = <0x101>; gpio-key,wakeup; }; }; -};
\ No newline at end of file +}; diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 1582f484a867..3abebb75fc57 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -18,8 +18,12 @@ interrupt-parent = <&mic>; cpus { - cpu@0 { - compatible = "arm,arm926ejs"; + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; }; }; diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts index 317300875f34..ccf9ea242f72 100644 --- a/arch/arm/boot/dts/mpa1600.dts +++ b/arch/arm/boot/dts/mpa1600.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2 only */ /dts-v1/; -/include/ "at91rm9200.dtsi" +#include "at91rm9200.dtsi" / { model = "Phontech MPA 1600"; @@ -62,7 +62,7 @@ monitor_mute { label = "Monitor mute"; - gpios = <&pioC 1 1>; + gpios = <&pioC 1 GPIO_ACTIVE_LOW>; linux,code = <113>; }; }; diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts index 9bf49b3826ea..cdc010e0f93e 100644 --- a/arch/arm/boot/dts/msm8660-surf.dts +++ b/arch/arm/boot/dts/msm8660-surf.dts @@ -15,7 +15,7 @@ < 0x02081000 0x1000 >; }; - timer@2000004 { + timer@2000000 { compatible = "qcom,scss-timer", "qcom,msm-timer"; interrupts = <1 0 0x301>, <1 1 0x301>, @@ -26,7 +26,18 @@ cpu-offset = <0x40000>; }; - serial@19c400000 { + msmgpio: gpio@800000 { + compatible = "qcom,msm-gpio"; + reg = <0x00800000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpio = <173>; + interrupts = <0 32 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + serial@19c40000 { compatible = "qcom,msm-hsuart", "qcom,msm-uart"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts index 2e4d87a125d6..db2060c46540 100644 --- a/arch/arm/boot/dts/msm8960-cdp.dts +++ b/arch/arm/boot/dts/msm8960-cdp.dts @@ -26,7 +26,18 @@ cpu-offset = <0x80000>; }; - serial@19c400000 { + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpio = <150>; + interrupts = <0 32 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + }; + + serial@16440000 { compatible = "qcom,msm-hsuart", "qcom,msm-uart"; reg = <0x16440000 0x1000>, <0x16400000 0x1000>; diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi new file mode 100644 index 000000000000..9565199bce7a --- /dev/null +++ b/arch/arm/boot/dts/nspire-classic.dtsi @@ -0,0 +1,74 @@ +/* + * linux/arch/arm/boot/nspire-classic.dts + * + * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ + +/include/ "nspire.dtsi" + +&lcd { + lcd-type = "classic"; +}; + +&fast_timer { + /* compatible = "lsi,zevio-timer"; */ + reg = <0x90010000 0x1000>, <0x900A0010 0x8>; +}; + +&uart { + compatible = "ns16550"; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb_pclk>; + no-loopback-test; +}; + +&timer0 { + /* compatible = "lsi,zevio-timer"; */ + reg = <0x900C0000 0x1000>, <0x900A0018 0x8>; +}; + +&timer1 { + compatible = "lsi,zevio-timer"; + reg = <0x900D0000 0x1000>, <0x900A0020 0x8>; +}; + +&keypad { + active-low; + +}; + +&base_clk { + compatible = "lsi,nspire-classic-clock"; +}; + +&ahb_clk { + compatible = "lsi,nspire-classic-ahb-divider"; +}; + +/ { + memory { + device_type = "memory"; + reg = <0x10000000 0x2000000>; /* 32 MB */ + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + + intc: interrupt-controller@DC000000 { + compatible = "lsi,zevio-intc"; + interrupt-controller; + reg = <0xDC000000 0x1000>; + #interrupt-cells = <1>; + }; + }; + chosen { + bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0"; + }; +}; diff --git a/arch/arm/boot/dts/nspire-clp.dts b/arch/arm/boot/dts/nspire-clp.dts new file mode 100644 index 000000000000..fa5a044656de --- /dev/null +++ b/arch/arm/boot/dts/nspire-clp.dts @@ -0,0 +1,45 @@ +/* + * linux/arch/arm/boot/nspire-clp.dts + * + * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ +/dts-v1/; + +/include/ "nspire-classic.dtsi" + +&keypad { + linux,keymap = < + 0x0000001c 0x0001001c 0x00020039 + 0x0004002c 0x00050034 0x00060015 + 0x0007000b 0x0008002d 0x01000033 + 0x0101004e 0x01020011 0x01030004 + 0x0104002f 0x01050003 0x01060016 + 0x01070002 0x01080014 0x02000062 + 0x0201000c 0x0202001f 0x02030007 + 0x02040013 0x02050006 0x02060010 + 0x02070005 0x02080019 0x03000027 + 0x03010037 0x03020018 0x0303000a + 0x03040031 0x03050009 0x03060032 + 0x03070008 0x03080026 0x04000028 + 0x04010035 0x04020025 0x04040024 + 0x04060017 0x04080023 0x05000028 + 0x05020022 0x0503001b 0x05040021 + 0x0505001a 0x05060012 0x0507006f + 0x05080020 0x0509002a 0x0601001c + 0x0602002e 0x06030068 0x06040030 + 0x0605006d 0x0606001e 0x06070001 + 0x0608002b 0x0609000f 0x07000067 + 0x0702006a 0x0704006c 0x07060069 + 0x0707000e 0x0708001d 0x070a000d + >; +}; + +/ { + model = "TI-NSPIRE Clickpad"; + compatible = "ti,nspire-clp"; +}; diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts new file mode 100644 index 000000000000..375b924f60d8 --- /dev/null +++ b/arch/arm/boot/dts/nspire-cx.dts @@ -0,0 +1,112 @@ +/* + * linux/arch/arm/boot/nspire-cx.dts + * + * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ +/dts-v1/; + +/include/ "nspire.dtsi" + +&lcd { + lcd-type = "cx"; +}; + +&fast_timer { + /* compatible = "arm,sp804", "arm,primecell"; */ +}; + +&uart { + compatible = "arm,pl011", "arm,primecell"; + + clocks = <&uart_clk>, <&apb_pclk>; + clock-names = "uart_clk", "apb_pclk"; +}; + +&timer0 { + compatible = "arm,sp804", "arm,primecell"; +}; + +&timer1 { + compatible = "arm,sp804", "arm,primecell"; +}; + +&base_clk { + compatible = "lsi,nspire-cx-clock"; +}; + +&ahb_clk { + compatible = "lsi,nspire-cx-ahb-divider"; +}; + +&keypad { + linux,keymap = < + 0x0000001c 0x0001001c 0x00040039 + 0x0005002c 0x00060015 0x0007000b + 0x0008000f 0x0100002d 0x01010011 + 0x0102002f 0x01030004 0x01040016 + 0x01050014 0x0106001f 0x01070002 + 0x010a006a 0x02000013 0x02010010 + 0x02020019 0x02030007 0x02040018 + 0x02050031 0x02060032 0x02070005 + 0x02080028 0x0209006c 0x03000026 + 0x03010025 0x03020024 0x0303000a + 0x03040017 0x03050023 0x03060022 + 0x03070008 0x03080035 0x03090069 + 0x04000021 0x04010012 0x04020020 + 0x0404002e 0x04050030 0x0406001e + 0x0407000d 0x04080037 0x04090067 + 0x05010038 0x0502000c 0x0503001b + 0x05040034 0x0505001a 0x05060006 + 0x05080027 0x0509000e 0x050a006f + 0x0600002b 0x0602004e 0x06030068 + 0x06040003 0x0605006d 0x06060009 + 0x06070001 0x0609000f 0x0708002a + 0x0709001d 0x070a0033 >; +}; + +/ { + model = "TI-NSPIRE CX"; + compatible = "ti,nspire-cx"; + + memory { + device_type = "memory"; + reg = <0x10000000 0x4000000>; /* 64 MB */ + }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + + intc: interrupt-controller@DC000000 { + compatible = "arm,pl190-vic"; + interrupt-controller; + reg = <0xDC000000 0x1000>; + #interrupt-cells = <1>; + }; + + apb@90000000 { + #address-cells = <1>; + #size-cells = <1>; + + i2c@90050000 { + compatible = "snps,designware-i2c"; + reg = <0x90050000 0x1000>; + interrupts = <20>; + }; + }; + }; + chosen { + bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0"; + }; +}; diff --git a/arch/arm/boot/dts/nspire-tp.dts b/arch/arm/boot/dts/nspire-tp.dts new file mode 100644 index 000000000000..621391ce6ed6 --- /dev/null +++ b/arch/arm/boot/dts/nspire-tp.dts @@ -0,0 +1,44 @@ +/* + * linux/arch/arm/boot/nspire-tp.dts + * + * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ +/dts-v1/; + +/include/ "nspire-classic.dtsi" + +&keypad { + linux,keymap = < + 0x0000001c 0x0001001c 0x00040039 + 0x0005002c 0x00060015 0x0007000b + 0x0008000f 0x0100002d 0x01010011 + 0x0102002f 0x01030004 0x01040016 + 0x01050014 0x0106001f 0x01070002 + 0x010a006a 0x02000013 0x02010010 + 0x02020019 0x02030007 0x02040018 + 0x02050031 0x02060032 0x02070005 + 0x02080028 0x0209006c 0x03000026 + 0x03010025 0x03020024 0x0303000a + 0x03040017 0x03050023 0x03060022 + 0x03070008 0x03080035 0x03090069 + 0x04000021 0x04010012 0x04020020 + 0x0404002e 0x04050030 0x0406001e + 0x0407000d 0x04080037 0x04090067 + 0x05010038 0x0502000c 0x0503001b + 0x05040034 0x0505001a 0x05060006 + 0x05080027 0x0509000e 0x050a006f + 0x0600002b 0x0602004e 0x06030068 + 0x06040003 0x0605006d 0x06060009 + 0x06070001 0x0609000f 0x0708002a + 0x0709001d 0x070a0033 >; +}; + +/ { + model = "TI-NSPIRE Touchpad"; + compatible = "ti,nspire-tp"; +}; diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi new file mode 100644 index 000000000000..a22ffe633b49 --- /dev/null +++ b/arch/arm/boot/dts/nspire.dtsi @@ -0,0 +1,175 @@ +/* + * linux/arch/arm/boot/nspire.dtsi + * + * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&intc>; + + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + bootrom: bootrom@00000000 { + reg = <0x00000000 0x80000>; + }; + + sram: sram@A4000000 { + device = "memory"; + reg = <0xA4000000 0x20000>; + }; + + timer_clk: timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + base_clk: base_clk { + #clock-cells = <0>; + reg = <0x900B0024 0x4>; + }; + + ahb_clk: ahb_clk { + #clock-cells = <0>; + reg = <0x900B0024 0x4>; + clocks = <&base_clk>; + }; + + apb_pclk: apb_pclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&ahb_clk>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + spi: spi@A9000000 { + reg = <0xA9000000 0x1000>; + }; + + usb0: usb@B0000000 { + reg = <0xB0000000 0x1000>; + interrupts = <8>; + }; + + usb1: usb@B4000000 { + reg = <0xB4000000 0x1000>; + interrupts = <9>; + status = "disabled"; + }; + + lcd: lcd@C0000000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0xC0000000 0x1000>; + interrupts = <21>; + + clocks = <&apb_pclk>; + clock-names = "apb_pclk"; + }; + + adc: adc@C4000000 { + reg = <0xC4000000 0x1000>; + interrupts = <11>; + }; + + tdes: crypto@C8010000 { + reg = <0xC8010000 0x1000>; + }; + + sha256: crypto@CC000000 { + reg = <0xCC000000 0x1000>; + }; + + apb@90000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + clock-ranges; + ranges; + + gpio: gpio@90000000 { + reg = <0x90000000 0x1000>; + interrupts = <7>; + }; + + fast_timer: timer@90010000 { + reg = <0x90010000 0x1000>; + interrupts = <17>; + }; + + uart: serial@90020000 { + reg = <0x90020000 0x1000>; + interrupts = <1>; + }; + + timer0: timer@900C0000 { + reg = <0x900C0000 0x1000>; + + clocks = <&timer_clk>; + }; + + timer1: timer@900D0000 { + reg = <0x900D0000 0x1000>; + interrupts = <19>; + + clocks = <&timer_clk>; + }; + + watchdog: watchdog@90060000 { + compatible = "arm,amba-primecell"; + reg = <0x90060000 0x1000>; + interrupts = <3>; + }; + + rtc: rtc@90090000 { + reg = <0x90090000 0x1000>; + interrupts = <4>; + }; + + misc: misc@900A0000 { + reg = <0x900A0000 0x1000>; + }; + + pwr: pwr@900B0000 { + reg = <0x900B0000 0x1000>; + interrupts = <15>; + }; + + keypad: input@900E0000 { + compatible = "ti,nspire-keypad"; + reg = <0x900E0000 0x1000>; + interrupts = <16>; + + scan-interval = <1000>; + row-delay = <200>; + + clocks = <&apb_pclk>; + }; + + contrast: contrast@900F0000 { + reg = <0x900F0000 0x1000>; + }; + + led: led@90110000 { + reg = <0x90110000 0x1000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index 37aa7487d4d8..a2bfcde858a6 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi @@ -8,7 +8,10 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/omap.h> + +#include "skeleton.dtsi" / { compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; @@ -21,8 +24,12 @@ }; cpus { - cpu@0 { + #address-cells = <0>; + #size-cells = <0>; + + cpu { compatible = "arm,arm1136jf-s"; + device_type = "cpu"; }; }; diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts index 68282ee13e26..224c08f472f4 100644 --- a/arch/arm/boot/dts/omap2420-h4.dts +++ b/arch/arm/boot/dts/omap2420-h4.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap2420.dtsi" +#include "omap2420.dtsi" / { model = "TI OMAP2420 H4 board"; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index da5b285b73be..c8f9c55169ea 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -8,7 +8,7 @@ * kind, whether express or implied. */ -/include/ "omap2.dtsi" +#include "omap2.dtsi" / { compatible = "ti,omap2420", "ti,omap2"; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 054bc4439568..c535a5a2b27f 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -8,7 +8,7 @@ * kind, whether express or implied. */ -/include/ "omap2.dtsi" +#include "omap2.dtsi" / { compatible = "ti,omap2430", "ti,omap2"; diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 3046d1f81be0..afdb16417d4e 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap36xx.dtsi" +#include "omap36xx.dtsi" / { model = "TI OMAP3 BeagleBoard xM"; @@ -29,13 +29,13 @@ heartbeat { label = "beagleboard::usr0"; - gpios = <&gpio5 22 0>; /* 150 -> D6 LED */ + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ linux,default-trigger = "heartbeat"; }; mmc { label = "beagleboard::usr1"; - gpios = <&gpio5 21 0>; /* 149 -> D7 LED */ + gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ linux,default-trigger = "mmc0"; }; }; @@ -57,6 +57,26 @@ ti,mcbsp = <&mcbsp2>; ti,codec = <&twl_audio>; }; + + gpio_keys { + compatible = "gpio-keys"; + + user { + label = "user"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + linux,code = <0x114>; + gpio-key,wakeup; + }; + + }; +}; + +&omap3_pmx_wkup { + gpio1_pins: pinmux_gpio1_pins { + pinctrl-single,pins = < + 0x0e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */ + >; + }; }; &i2c1 { @@ -75,7 +95,8 @@ }; }; -/include/ "twl4030.dtsi" +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" &i2c2 { clock-frequency = <400000>; @@ -126,3 +147,22 @@ mode = <3>; power = <50>; }; + +&omap3_pmx_core { + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ + >; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_pins>; +}; diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 6eec69997607..dfd83103657a 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap34xx.dtsi" +#include "omap34xx.dtsi" / { model = "TI OMAP3 BeagleBoard"; @@ -28,18 +28,18 @@ compatible = "gpio-leds"; pmu_stat { label = "beagleboard::pmu_stat"; - gpios = <&twl_gpio 19 0>; /* LEDB */ + gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ }; heartbeat { label = "beagleboard::usr0"; - gpios = <&gpio5 22 0>; /* 150 -> D6 LED */ + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ linux,default-trigger = "heartbeat"; }; mmc { label = "beagleboard::usr1"; - gpios = <&gpio5 21 0>; /* 149 -> D7 LED */ + gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ linux,default-trigger = "mmc0"; }; }; @@ -71,6 +71,26 @@ reset-supply = <&hsusb2_reset>; vcc-supply = <&hsusb2_power>; }; + + gpio_keys { + compatible = "gpio-keys"; + + user { + label = "user"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + linux,code = <0x114>; + gpio-key,wakeup; + }; + + }; +}; + +&omap3_pmx_wkup { + gpio1_pins: pinmux_gpio1_pins { + pinctrl-single,pins = < + 0x14 (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ + >; + }; }; &omap3_pmx_core { @@ -81,18 +101,25 @@ hsusbb2_pins: pinmux_hsusbb2_pins { pinctrl-single,pins = < - 0x5c0 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */ - 0x5c2 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */ - 0x5c4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */ - 0x5c6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */ - 0x5c8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */ - 0x5cA 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */ - 0x1a4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */ - 0x1a6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */ - 0x1a8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */ - 0x1aa 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */ - 0x1ac 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */ - 0x1ae 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */ + 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_clk */ + 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_stp */ + 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dir */ + 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_nxt */ + 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat0 */ + 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat1 */ + 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat2 */ + 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat3 */ + 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat4 */ + 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat5 */ + 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat6 */ + 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat7 */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; }; @@ -107,7 +134,8 @@ }; }; -/include/ "twl4030.dtsi" +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" &mmc1 { vmmc-supply = <&vmmc1>; @@ -142,3 +170,13 @@ */ ti,pulldowns = <0x03a1c4>; }; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_pins>; +}; diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts index 8a5cdcc6debd..af32eff9f4b7 100644 --- a/arch/arm/boot/dts/omap3-devkit8000.dts +++ b/arch/arm/boot/dts/omap3-devkit8000.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap34xx.dtsi" +#include "omap34xx.dtsi" / { model = "TimLL OMAP3 Devkit8000"; compatible = "timll,omap3-devkit8000", "ti,omap3"; @@ -22,21 +22,21 @@ heartbeat { label = "devkit8000::led1"; - gpios = <&gpio6 26 0>; /* 186 -> LED1 */ + gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* 186 -> LED1 */ default-state = "on"; linux,default-trigger = "heartbeat"; }; mmc { label = "devkit8000::led2"; - gpios = <&gpio6 3 0>; /* 163 -> LED2 */ + gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 -> LED2 */ default-state = "on"; linux,default-trigger = "none"; }; usr { label = "devkit8000::led3"; - gpios = <&gpio6 4 0>; /* 164 -> LED3 */ + gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* 164 -> LED3 */ default-state = "on"; linux,default-trigger = "usr"; }; @@ -80,7 +80,8 @@ status = "disabled"; }; -/include/ "twl4030.dtsi" +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" &mmc1 { vmmc-supply = <&vmmc1>; diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index 96d1c206a57b..7d4329d179c4 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap34xx.dtsi" +#include "omap34xx.dtsi" / { model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)"; @@ -28,7 +28,7 @@ compatible = "gpio-leds"; ledb { label = "omap3evm::ledb"; - gpios = <&twl_gpio 19 0>; /* LEDB */ + gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ linux,default-trigger = "default-on"; }; }; @@ -44,7 +44,8 @@ }; }; -/include/ "twl4030.dtsi" +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" &i2c2 { clock-frequency = <400000>; diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index f8fe3b748c3e..bc48b114eae6 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "omap34xx.dtsi" +#include "omap34xx.dtsi" / { memory { @@ -29,37 +29,43 @@ &omap3_pmx_core { uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - 0x152 0x100 /* uart1_rx.uart1_rx INPUT | MODE0 */ - 0x14c 0 /* uart1_tx.uart1_tx OUTPUT | MODE0 */ + 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ + 0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */ >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < - 0x14a 0x100 /* uart2_rx.uart2_rx INPUT | MODE0 */ - 0x148 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */ + 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < - 0x16e 0x100 /* uart3_rx.uart3_rx INPUT | MODE0 */ - 0x170 0 /* uart3_tx.uart3_tx OUTPUT | MODE0 */ + 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0x114 0x0118 /* sdmmc1_clk.sdmmc1_clk INPUT PULLUP | MODE 0 */ - 0x116 0x0118 /* sdmmc1_cmd.sdmmc1_cmd INPUT PULLUP | MODE 0 */ - 0x118 0x0118 /* sdmmc1_dat0.sdmmc1_dat0 INPUT PULLUP | MODE 0 */ - 0x11a 0x0118 /* sdmmc1_dat1.sdmmc1_dat1 INPUT PULLUP | MODE 0 */ - 0x11c 0x0118 /* sdmmc1_dat2.sdmmc1_dat2 INPUT PULLUP | MODE 0 */ - 0x11e 0x0118 /* sdmmc1_dat3.sdmmc1_dat3 INPUT PULLUP | MODE 0 */ - 0x120 0x0100 /* sdmmc1_dat4.sdmmc1_dat4 INPUT | MODE 0 */ - 0x122 0x0100 /* sdmmc1_dat5.sdmmc1_dat5 INPUT | MODE 0 */ - 0x124 0x0100 /* sdmmc1_dat6.sdmmc1_dat6 INPUT | MODE 0 */ - 0x126 0x0100 /* sdmmc1_dat7.sdmmc1_dat7 INPUT | MODE 0 */ + 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + 0x120 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ + 0x122 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ + 0x124 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ + 0x126 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ + >; + }; + + smsc911x_pins: pinmux_smsc911x_pins { + pinctrl-single,pins = < + 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ >; }; }; @@ -80,7 +86,8 @@ }; }; -/include/ "twl4030.dtsi" +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" &i2c2 { clock-frequency = <400000>; diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts index e2b98490cc9a..e8c48284587c 100644 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ b/arch/arm/boot/dts/omap3-igep0020.dts @@ -9,7 +9,7 @@ * published by the Free Software Foundation. */ -/include/ "omap3-igep.dtsi" +#include "omap3-igep.dtsi" / { model = "IGEPv2"; @@ -19,27 +19,39 @@ compatible = "gpio-leds"; boot { label = "omap3:green:boot"; - gpios = <&gpio1 26 0>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; default-state = "on"; }; user0 { label = "omap3:red:user0"; - gpios = <&gpio1 27 0>; + gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; default-state = "off"; }; user1 { label = "omap3:red:user1"; - gpios = <&gpio1 28 0>; + gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; default-state = "off"; }; user2 { label = "omap3:green:user1"; - gpios = <&twl_gpio 19 1>; + gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; }; }; + + vddvario: regulator-vddvario { + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; + }; + + vdd33a: regulator-vdd33a { + compatible = "regulator-fixed"; + regulator-name = "vdd33a"; + regulator-always-on; + }; }; &i2c3 { @@ -54,3 +66,92 @@ reg = <0x50>; }; }; + +&gpmc { + ranges = <0 0 0x00000000 0x20000000>, + <5 0 0x2c000000 0x01000000>; + + nand@0,0 { + linux,mtd-name= "micron,mt29c4g96maz"; + reg = <0 0 0>; + nand-bus-width = <16>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SPL"; + reg = <0 0x100000>; + }; + partition@0x80000 { + label = "U-Boot"; + reg = <0x100000 0x180000>; + }; + partition@0x1c0000 { + label = "Environment"; + reg = <0x280000 0x100000>; + }; + partition@0x280000 { + label = "Kernel"; + reg = <0x380000 0x300000>; + }; + partition@0x780000 { + label = "Filesystem"; + reg = <0x680000 0x1f980000>; + }; + }; + + ethernet@5,0 { + pinctrl-names = "default"; + pinctrl-0 = <&smsc911x_pins>; + compatible = "smsc,lan9221", "smsc,lan9115"; + reg = <5 0 0xff>; + bank-width = <2>; + + gpmc,mux-add-data; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <186>; + gpmc,cs-wr-off-ns = <186>; + gpmc,adv-on-ns = <12>; + gpmc,adv-rd-off-ns = <48>; + gpmc,adv-wr-off-ns = <48>; + gpmc,oe-on-ns = <54>; + gpmc,oe-off-ns = <168>; + gpmc,we-on-ns = <54>; + gpmc,we-off-ns = <168>; + gpmc,rd-cycle-ns = <186>; + gpmc,wr-cycle-ns = <186>; + gpmc,access-ns = <114>; + gpmc,page-burst-access-ns = <6>; + gpmc,bus-turnaround-ns = <12>; + gpmc,cycle2cycle-delay-ns = <18>; + gpmc,wr-data-mux-bus-ns = <90>; + gpmc,wr-access-ns = <186>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + + interrupt-parent = <&gpio6>; + interrupts = <16 8>; + vmmc-supply = <&vddvario>; + vmmc_aux-supply = <&vdd33a>; + reg-io-width = <4>; + + smsc,save-mac-address; + }; +}; diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts index 9dc48d262ffb..644d05383836 100644 --- a/arch/arm/boot/dts/omap3-igep0030.dts +++ b/arch/arm/boot/dts/omap3-igep0030.dts @@ -9,7 +9,7 @@ * published by the Free Software Foundation. */ -/include/ "omap3-igep.dtsi" +#include "omap3-igep.dtsi" / { model = "IGEP COM Module"; @@ -19,26 +19,76 @@ compatible = "gpio-leds"; boot { label = "omap3:green:boot"; - gpios = <&twl_gpio 13 1>; + gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; default-state = "on"; }; user0 { label = "omap3:red:user0"; - gpios = <&twl_gpio 18 1>; /* LEDA */ + gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ default-state = "off"; }; user1 { label = "omap3:green:user1"; - gpios = <&twl_gpio 19 1>; /* LEDB */ + gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */ default-state = "off"; }; user2 { label = "omap3:red:user1"; - gpios = <&gpio1 16 1>; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; default-state = "off"; }; }; }; + +&gpmc { + ranges = <0 0 0x00000000 0x20000000>; + + nand@0,0 { + linux,mtd-name= "micron,mt29c4g96maz"; + reg = <0 0 0>; + nand-bus-width = <16>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SPL"; + reg = <0 0x100000>; + }; + partition@0x80000 { + label = "U-Boot"; + reg = <0x100000 0x180000>; + }; + partition@0x1c0000 { + label = "Environment"; + reg = <0x280000 0x100000>; + }; + partition@0x280000 { + label = "Kernel"; + reg = <0x380000 0x300000>; + }; + partition@0x780000 { + label = "Filesystem"; + reg = <0x680000 0x1f980000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi index a626c50041f6..8f1abec78275 100644 --- a/arch/arm/boot/dts/omap3-overo.dtsi +++ b/arch/arm/boot/dts/omap3-overo.dtsi @@ -11,7 +11,7 @@ */ /dts-v1/; -/include/ "omap34xx.dtsi" +#include "omap34xx.dtsi" / { pwmleds { @@ -21,6 +21,7 @@ label = "overo:blue:COM"; pwms = <&twl_pwmled 1 7812500>; max-brightness = <127>; + linux,default-trigger = "mmc0"; }; }; @@ -49,7 +50,8 @@ }; }; -/include/ "twl4030.dtsi" +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" /* i2c2 pins are used for gpio */ &i2c2 { @@ -77,3 +79,17 @@ mode = <3>; power = <50>; }; + +&omap3_pmx_core { + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts index a13d12de77ff..7e4ad2aec37a 100644 --- a/arch/arm/boot/dts/omap3-tobi.dts +++ b/arch/arm/boot/dts/omap3-tobi.dts @@ -10,7 +10,7 @@ * Tobi expansion board is manufactured by Gumstix Inc. */ -/include/ "omap3-overo.dtsi" +#include "omap3-overo.dtsi" / { model = "TI OMAP3 Gumstix Overo on Tobi"; @@ -20,10 +20,58 @@ compatible = "gpio-leds"; heartbeat { label = "overo:red:gpio21"; - gpios = <&gpio1 21 0>; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; }; + + vddvario: regulator-vddvario { + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; + }; + + vdd33a: regulator-vdd33a { + compatible = "regulator-fixed"; + regulator-name = "vdd33a"; + regulator-always-on; + }; +}; + +&gpmc { + ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */ + + ethernet@5,0 { + compatible = "smsc,lan9221", "smsc,lan9115"; + reg = <5 0 0xff>; + bank-width = <2>; + + gpmc,mux-add-data; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <42>; + gpmc,cs-wr-off-ns = <36>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <12>; + gpmc,adv-wr-off-ns = <12>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <42>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <36>; + gpmc,rd-cycle-ns = <60>; + gpmc,wr-cycle-ns = <54>; + gpmc,access-ns = <36>; + gpmc,page-burst-access-ns = <0>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wr-data-mux-bus-ns = <18>; + gpmc,wr-access-ns = <42>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ + reg-io-width = <4>; + }; }; &i2c3 { diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 82a404da1c0d..7d95cda1fae4 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -8,7 +8,11 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/omap.h> + +#include "skeleton.dtsi" / { compatible = "ti,omap3430", "ti,omap3"; @@ -21,8 +25,13 @@ }; cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { compatible = "arm,cortex-a8"; + device_type = "cpu"; + reg = <0x0>; }; }; @@ -516,7 +525,7 @@ usb_otg_hs: usb_otg_hs@480ab000 { compatible = "ti,omap3-musb"; reg = <0x480ab000 0x1000>; - interrupts = <0 92 0x4>, <0 93 0x4>; + interrupts = <92>, <93>; interrupt-names = "mc", "dma"; ti,hwmods = "usb_otg_hs"; multipoint = <1>; diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts index 144ae43453c4..e2249bcc3e63 100644 --- a/arch/arm/boot/dts/omap3430-sdp.dts +++ b/arch/arm/boot/dts/omap3430-sdp.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap34xx.dtsi" +#include "omap34xx.dtsi" / { model = "TI OMAP3430 SDP"; @@ -28,7 +28,8 @@ }; }; -/include/ "twl4030.dtsi" +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" &mmc1 { vmmc-supply = <&vmmc1>; @@ -105,7 +106,6 @@ nand-bus-width = <8>; ti,nand-ecc-opt = "sw"; - gpmc,device-nand; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <36>; gpmc,cs-wr-off-ns = <36>; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index 75ed4ae2e631..5355d6173748 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -8,7 +8,7 @@ * kind, whether express or implied. */ -/include/ "omap3.dtsi" +#include "omap3.dtsi" / { cpus { diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index f3447bc1b032..f8b3765eb9be 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -8,7 +8,7 @@ * kind, whether express or implied. */ -/include/ "omap3.dtsi" +#include "omap3.dtsi" / { aliases { diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts index e30cdf0f5ac1..133f1b74e8ae 100644 --- a/arch/arm/boot/dts/omap4-panda-a4.dts +++ b/arch/arm/boot/dts/omap4-panda-a4.dts @@ -7,14 +7,14 @@ */ /dts-v1/; -/include/ "omap443x.dtsi" -/include/ "omap4-panda-common.dtsi" +#include "omap443x.dtsi" +#include "omap4-panda-common.dtsi" /* Pandaboard Rev A4+ have external pullups on SCL & SDA */ &dss_hdmi_pins { pinctrl-single,pins = < - 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ - 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */ - 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */ + 0x5a (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + 0x5c (PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + 0x5e (PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ >; }; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 03bd60deb52b..faa95b5b242e 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -5,7 +5,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -/include/ "elpida_ecb240abacn.dtsi" +#include "elpida_ecb240abacn.dtsi" / { model = "TI OMAP4 PandaBoard"; @@ -16,17 +16,22 @@ reg = <0x80000000 0x40000000>; /* 1 GB */ }; - leds { + leds: leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = < + &led_wkgpio_pins + >; + heartbeat { label = "pandaboard::status1"; - gpios = <&gpio1 7 0>; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; mmc { label = "pandaboard::status2"; - gpios = <&gpio1 8 0>; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; }; }; @@ -54,85 +59,180 @@ "AFML", "Line In", "AFMR", "Line In"; }; + + /* + * Temp hack: Need to be replaced with the proper gpio-controlled + * reset driver as soon it will be merged. + * http://thread.gmane.org/gmane.linux.drivers.devicetree/36830 + */ + /* HS USB Port 1 RESET */ + hsusb1_reset: hsusb1_reset_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb1_reset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 30 0>; /* gpio_62 */ + startup-delay-us = <70000>; + enable-active-high; + }; + + /* HS USB Port 1 Power */ + hsusb1_power: hsusb1_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 1 0>; /* gpio_1 */ + startup-delay-us = <70000>; + enable-active-high; + /* + * boot-on is required along with always-on as the + * regulator framework doesn't enable the regulator + * if boot-on is not there. + */ + regulator-always-on; + regulator-boot-on; + }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + reset-supply = <&hsusb1_reset>; + vcc-supply = <&hsusb1_power>; + /** + * FIXME: + * put the right clock phandle here when available + * clocks = <&auxclk3>; + * clock-names = "main_clk"; + */ + clock-frequency = <19200000>; + }; +}; + +&omap4_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6030_wkup_pins + >; + + twl6030_wkup_pins: pinmux_twl6030_wkup_pins { + pinctrl-single,pins = < + 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ + >; + }; }; &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < + &twl6030_pins &twl6040_pins &mcpdm_pins &mcbsp1_pins &dss_hdmi_pins &tpd12s015_pins + &hsusbb1_pins >; + twl6030_pins: pinmux_twl6030_pins { + pinctrl-single,pins = < + 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ + >; + }; + twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < - 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ - 0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */ + 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ + 0x160 (PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ >; }; mcpdm_pins: pinmux_mcpdm_pins { pinctrl-single,pins = < - 0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */ - 0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */ - 0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */ - 0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */ - 0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */ + 0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ + 0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ + 0xca (PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ + 0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ + 0xce (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ >; }; mcbsp1_pins: pinmux_mcbsp1_pins { pinctrl-single,pins = < - 0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */ - 0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */ - 0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */ - 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */ + 0xbe (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ + 0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ + 0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ + 0xc4 (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ >; }; dss_hdmi_pins: pinmux_dss_hdmi_pins { pinctrl-single,pins = < - 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ - 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */ - 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */ + 0x5a (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + 0x5c (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + 0x5e (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ >; }; tpd12s015_pins: pinmux_tpd12s015_pins { pinctrl-single,pins = < - 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */ - 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */ - 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */ + 0x22 (PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ + 0x48 (PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ + >; + }; + + hsusbb1_pins: pinmux_hsusbb1_pins { + pinctrl-single,pins = < + 0x82 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ + 0x84 (PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ + 0x86 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ + 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ + 0x8a (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ + 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ + 0x8e (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ + 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ + 0x92 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ + 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ + 0x96 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ + 0x98 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < - 0xe2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */ - 0xe4 0x118 /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */ + 0xe2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + 0xe4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < - 0xe6 0x118 /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */ - 0xe8 0x118 /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */ + 0xe6 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ + 0xe8 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ >; }; i2c3_pins: pinmux_i2c3_pins { pinctrl-single,pins = < - 0xea 0x118 /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */ - 0xec 0x118 /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */ + 0xea (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + 0xec (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; i2c4_pins: pinmux_i2c4_pins { pinctrl-single,pins = < - 0xee 0x118 /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */ - 0xf0 0x118 /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */ + 0xee (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ + 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ + >; + }; +}; + +&omap4_pmx_wkup { + led_wkgpio_pins: pinmux_leds_wkpins { + pinctrl-single,pins = < + 0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */ + 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ >; }; }; @@ -145,18 +245,18 @@ twl: twl@48 { reg = <0x48>; - /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ - interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ + /* IRQ# = 7 */ + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ interrupt-parent = <&gic>; }; twl6040: twl@4b { compatible = "ti,twl6040"; reg = <0x4b>; - /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ - interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */ + /* IRQ# = 119 */ + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ interrupt-parent = <&gic>; - ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */ + ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */ vio-supply = <&v1v8>; v2v1-supply = <&v2v1>; @@ -164,7 +264,7 @@ }; }; -/include/ "twl6030.dtsi" +#include "twl6030.dtsi" &i2c2 { pinctrl-names = "default"; @@ -249,3 +349,11 @@ mode = <3>; power = <50>; }; + +&usbhshost { + port1-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; +}; diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index f1d8c217ce12..56c435468e94 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -7,8 +7,8 @@ */ /dts-v1/; -/include/ "omap4460.dtsi" -/include/ "omap4-panda-common.dtsi" +#include "omap4460.dtsi" +#include "omap4-panda-common.dtsi" /* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ &sound { @@ -29,8 +29,36 @@ /* PandaboardES has external pullups on SCL & SDA */ &dss_hdmi_pins { pinctrl-single,pins = < - 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ - 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */ - 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */ + 0x5a (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + 0x5c (PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + 0x5e (PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ >; }; + +&omap4_pmx_core { + led_gpio_pins: gpio_led_pmx { + pinctrl-single,pins = < + 0xb6 (PIN_OUTPUT | MUX_MODE3) /* gpio_110 */ + >; + }; +}; + +&led_wkgpio_pins { + pinctrl-single,pins = < + 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ + >; +}; + +&leds { + pinctrl-0 = < + &led_gpio_pins + &led_wkgpio_pins + >; + + heartbeat { + gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; + }; + mmc { + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts index f8b221f0168e..6189a8b77d7f 100644 --- a/arch/arm/boot/dts/omap4-panda.dts +++ b/arch/arm/boot/dts/omap4-panda.dts @@ -7,5 +7,5 @@ */ /dts-v1/; -/include/ "omap443x.dtsi" -/include/ "omap4-panda-common.dtsi" +#include "omap443x.dtsi" +#include "omap4-panda-common.dtsi" diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts index b4a40ffbce31..aad5dda0f469 100644 --- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts +++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts @@ -5,13 +5,13 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -/include/ "omap4-sdp.dts" +#include "omap4-sdp.dts" /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */ &dss_hdmi_pins { pinctrl-single,pins = < - 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ - 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */ - 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */ + 0x5a (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + 0x5c (PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + 0x5e (PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ >; }; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index a35d9cd58063..7951b4ea500a 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -7,8 +7,8 @@ */ /dts-v1/; -/include/ "omap443x.dtsi" -/include/ "elpida_ecb240abacn.dtsi" +#include "omap443x.dtsi" +#include "elpida_ecb240abacn.dtsi" / { model = "TI OMAP4 SDP board"; @@ -41,42 +41,42 @@ compatible = "gpio-leds"; debug0 { label = "omap4:green:debug0"; - gpios = <&gpio2 29 0>; /* 61 */ + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */ }; debug1 { label = "omap4:green:debug1"; - gpios = <&gpio1 30 0>; /* 30 */ + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */ }; debug2 { label = "omap4:green:debug2"; - gpios = <&gpio1 7 0>; /* 7 */ + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */ }; debug3 { label = "omap4:green:debug3"; - gpios = <&gpio1 8 0>; /* 8 */ + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */ }; debug4 { label = "omap4:green:debug4"; - gpios = <&gpio2 18 0>; /* 50 */ + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */ }; user1 { label = "omap4:blue:user"; - gpios = <&gpio6 9 0>; /* 169 */ + gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */ }; user2 { label = "omap4:red:user"; - gpios = <&gpio6 10 0>; /* 170 */ + gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */ }; user3 { label = "omap4:green:user"; - gpios = <&gpio5 11 0>; /* 139 */ + gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */ }; }; @@ -142,9 +142,23 @@ }; }; +&omap4_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6030_wkup_pins + >; + + twl6030_wkup_pins: pinmux_twl6030_wkup_pins { + pinctrl-single,pins = < + 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ + >; + }; +}; + &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < + &twl6030_pins &twl6040_pins &mcpdm_pins &dmic_pins @@ -156,123 +170,129 @@ uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < - 0xd8 0x118 /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */ - 0xda 0 /* uart2_rts.uart2_rts OUTPUT | MODE0 */ - 0xdc 0x118 /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */ - 0xde 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */ + 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ + 0xda (PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ + 0xdc (PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ + 0xde (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < - 0x100 0x118 /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */ - 0x102 0 /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */ - 0x104 0x100 /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */ - 0x106 0 /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ + 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ + 0x102 (PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ + 0x104 (PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + 0x106 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; uart4_pins: pinmux_uart4_pins { pinctrl-single,pins = < - 0x11c 0x100 /* uart4_rx.uart4_rx INPUT | MODE0 */ - 0x11e 0 /* uart4_tx.uart4_tx OUTPUT | MODE0 */ + 0x11c (PIN_INPUT | MUX_MODE0) /* uart4_rx.uart4_rx */ + 0x11e (PIN_OUTPUT | MUX_MODE0) /* uart4_tx.uart4_tx */ + >; + }; + + twl6030_pins: pinmux_twl6030_pins { + pinctrl-single,pins = < + 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ >; }; twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < - 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ - 0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */ + 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ + 0x160 (PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ >; }; mcpdm_pins: pinmux_mcpdm_pins { pinctrl-single,pins = < - 0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */ - 0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */ - 0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */ - 0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */ - 0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */ + 0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ + 0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ + 0xca (PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ + 0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ + 0xce (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ >; }; dmic_pins: pinmux_dmic_pins { pinctrl-single,pins = < - 0xd0 0 /* abe_dmic_clk1.abe_dmic_clk1 OUTPUT | MODE0 */ - 0xd2 0x100 /* abe_dmic_din1.abe_dmic_din1 INPUT | MODE0 */ - 0xd4 0x100 /* abe_dmic_din2.abe_dmic_din2 INPUT | MODE0 */ - 0xd6 0x100 /* abe_dmic_din3.abe_dmic_din3 INPUT | MODE0 */ + 0xd0 (PIN_OUTPUT | MUX_MODE0) /* abe_dmic_clk1.abe_dmic_clk1 */ + 0xd2 (PIN_INPUT | MUX_MODE0) /* abe_dmic_din1.abe_dmic_din1 */ + 0xd4 (PIN_INPUT | MUX_MODE0) /* abe_dmic_din2.abe_dmic_din2 */ + 0xd6 (PIN_INPUT | MUX_MODE0) /* abe_dmic_din3.abe_dmic_din3 */ >; }; mcbsp1_pins: pinmux_mcbsp1_pins { pinctrl-single,pins = < - 0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */ - 0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */ - 0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */ - 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */ + 0xbe (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ + 0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ + 0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ + 0xc4 (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ >; }; mcbsp2_pins: pinmux_mcbsp2_pins { pinctrl-single,pins = < - 0xb6 0x100 /* abe_mcbsp2_clkx.abe_mcbsp2_clkx INPUT | MODE0 */ - 0xb8 0x108 /* abe_mcbsp2_dr.abe_mcbsp2_dr INPUT PULLDOWN | MODE0 */ - 0xba 0x8 /* abe_mcbsp2_dx.abe_mcbsp2_dx OUTPUT PULLDOWN | MODE0 */ - 0xbc 0x100 /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */ + 0xb6 (PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */ + 0xb8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dr.abe_mcbsp2_dr */ + 0xba (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dx.abe_mcbsp2_dx */ + 0xbc (PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx.abe_mcbsp2_fsx */ >; }; mcspi1_pins: pinmux_mcspi1_pins { pinctrl-single,pins = < - 0xf2 0x100 /* mcspi1_clk.mcspi1_clk INPUT | MODE0 */ - 0xf4 0x100 /* mcspi1_somi.mcspi1_somi INPUT | MODE0 */ - 0xf6 0x100 /* mcspi1_simo.mcspi1_simo INPUT | MODE0 */ - 0xf8 0x100 /* mcspi1_cs0.mcspi1_cs0 INPUT | MODE0*/ + 0xf2 (PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + 0xf4 (PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + 0xf6 (PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + 0xf8 (PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ >; }; dss_hdmi_pins: pinmux_dss_hdmi_pins { pinctrl-single,pins = < - 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ - 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */ - 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */ + 0x5a (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + 0x5c (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + 0x5e (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ >; }; tpd12s015_pins: pinmux_tpd12s015_pins { pinctrl-single,pins = < - 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */ - 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */ - 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */ + 0x22 (PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ + 0x48 (PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < - 0xe2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */ - 0xe4 0x118 /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */ + 0xe2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + 0xe4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < - 0xe6 0x118 /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */ - 0xe8 0x118 /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */ + 0xe6 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ + 0xe8 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ >; }; i2c3_pins: pinmux_i2c3_pins { pinctrl-single,pins = < - 0xea 0x118 /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */ - 0xec 0x118 /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */ + 0xea (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + 0xec (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; i2c4_pins: pinmux_i2c4_pins { pinctrl-single,pins = < - 0xee 0x118 /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */ - 0xf0 0x118 /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */ + 0xee (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ + 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ >; }; }; @@ -286,7 +306,7 @@ twl: twl@48 { reg = <0x48>; /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ - interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ interrupt-parent = <&gic>; }; @@ -294,7 +314,7 @@ compatible = "ti,twl6040"; reg = <0x4b>; /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ - interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */ + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ interrupt-parent = <&gic>; ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */ @@ -316,7 +336,7 @@ }; }; -/include/ "twl6030.dtsi" +#include "twl6030.dtsi" &i2c2 { pinctrl-names = "default"; @@ -375,7 +395,7 @@ spi-max-frequency = <24000000>; reg = <0>; interrupt-parent = <&gpio2>; - interrupts = <2 8>; /* gpio line 34, low triggered */ + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */ vdd-supply = <&vdd_eth>; }; }; diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts index 7e04103779c4..b41269e871dd 100644 --- a/arch/arm/boot/dts/omap4-var-som.dts +++ b/arch/arm/boot/dts/omap4-var-som.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap443x.dtsi" +#include "omap443x.dtsi" / { model = "Variscite OMAP4 SOM"; @@ -34,12 +34,12 @@ twl: twl@48 { reg = <0x48>; /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ - interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ interrupt-parent = <&gic>; }; }; -/include/ "twl6030.dtsi" +#include "twl6030.dtsi" &i2c2 { clock-frequency = <400000>; @@ -68,7 +68,7 @@ spi-max-frequency = <24000000>; reg = <0>; interrupt-parent = <&gpio6>; - interrupts = <11 8>; /* gpio line 171, low triggered */ + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio line 171 */ vdd-supply = <&vdd_eth>; }; }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 2a5642882c8a..22d9f2b593d4 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -6,15 +6,11 @@ * published by the Free Software Foundation. */ -/* - * Carveout for multimedia usecases - * It should be the last 48MB of the first 512MB memory part - * In theory, it should not even exist. That zone should be reserved - * dynamically during the .reserve callback. - */ -/memreserve/ 0x9d000000 0x03000000; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/omap.h> -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { compatible = "ti,omap4430", "ti,omap4"; @@ -28,13 +24,20 @@ }; cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { compatible = "arm,cortex-a9"; + device_type = "cpu"; next-level-cache = <&L2>; + reg = <0x0>; }; cpu@1 { compatible = "arm,cortex-a9"; + device_type = "cpu"; next-level-cache = <&L2>; + reg = <0x1>; }; }; @@ -56,7 +59,7 @@ local-timer@0x48240600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x48240600 0x20>; - interrupts = <1 13 0x304>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; }; /* @@ -97,8 +100,8 @@ reg = <0x44000000 0x1000>, <0x44800000 0x2000>, <0x45000000 0x1000>; - interrupts = <0 9 0x4>, - <0 10 0x4>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; counter32k: counter@4a304000 { compatible = "ti,omap-counter32k"; @@ -126,10 +129,10 @@ sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; - interrupts = <0 12 0x4>, - <0 13 0x4>, - <0 14 0x4>, - <0 15 0x4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; #dma-channels = <32>; #dma-requests = <127>; @@ -138,7 +141,7 @@ gpio1: gpio@4a310000 { compatible = "ti,omap4-gpio"; reg = <0x4a310000 0x200>; - interrupts = <0 29 0x4>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "gpio1"; ti,gpio-always-on; gpio-controller; @@ -150,7 +153,7 @@ gpio2: gpio@48055000 { compatible = "ti,omap4-gpio"; reg = <0x48055000 0x200>; - interrupts = <0 30 0x4>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; @@ -161,7 +164,7 @@ gpio3: gpio@48057000 { compatible = "ti,omap4-gpio"; reg = <0x48057000 0x200>; - interrupts = <0 31 0x4>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; @@ -172,7 +175,7 @@ gpio4: gpio@48059000 { compatible = "ti,omap4-gpio"; reg = <0x48059000 0x200>; - interrupts = <0 32 0x4>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; @@ -183,7 +186,7 @@ gpio5: gpio@4805b000 { compatible = "ti,omap4-gpio"; reg = <0x4805b000 0x200>; - interrupts = <0 33 0x4>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "gpio5"; gpio-controller; #gpio-cells = <2>; @@ -194,7 +197,7 @@ gpio6: gpio@4805d000 { compatible = "ti,omap4-gpio"; reg = <0x4805d000 0x200>; - interrupts = <0 34 0x4>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "gpio6"; gpio-controller; #gpio-cells = <2>; @@ -207,7 +210,7 @@ reg = <0x50000000 0x1000>; #address-cells = <2>; #size-cells = <1>; - interrupts = <0 20 0x4>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; @@ -216,7 +219,7 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; reg = <0x4806a000 0x100>; - interrupts = <0 72 0x4>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; @@ -224,7 +227,7 @@ uart2: serial@4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; - interrupts = <0 73 0x4>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; @@ -232,7 +235,7 @@ uart3: serial@48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; - interrupts = <0 74 0x4>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; @@ -240,7 +243,7 @@ uart4: serial@4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; - interrupts = <0 70 0x4>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; @@ -248,7 +251,7 @@ i2c1: i2c@48070000 { compatible = "ti,omap4-i2c"; reg = <0x48070000 0x100>; - interrupts = <0 56 0x4>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; @@ -257,7 +260,7 @@ i2c2: i2c@48072000 { compatible = "ti,omap4-i2c"; reg = <0x48072000 0x100>; - interrupts = <0 57 0x4>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; @@ -266,7 +269,7 @@ i2c3: i2c@48060000 { compatible = "ti,omap4-i2c"; reg = <0x48060000 0x100>; - interrupts = <0 61 0x4>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; @@ -275,7 +278,7 @@ i2c4: i2c@48350000 { compatible = "ti,omap4-i2c"; reg = <0x48350000 0x100>; - interrupts = <0 62 0x4>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c4"; @@ -284,7 +287,7 @@ mcspi1: spi@48098000 { compatible = "ti,omap4-mcspi"; reg = <0x48098000 0x200>; - interrupts = <0 65 0x4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi1"; @@ -304,7 +307,7 @@ mcspi2: spi@4809a000 { compatible = "ti,omap4-mcspi"; reg = <0x4809a000 0x200>; - interrupts = <0 66 0x4>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi2"; @@ -319,7 +322,7 @@ mcspi3: spi@480b8000 { compatible = "ti,omap4-mcspi"; reg = <0x480b8000 0x200>; - interrupts = <0 91 0x4>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi3"; @@ -331,7 +334,7 @@ mcspi4: spi@480ba000 { compatible = "ti,omap4-mcspi"; reg = <0x480ba000 0x200>; - interrupts = <0 48 0x4>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi4"; @@ -343,7 +346,7 @@ mmc1: mmc@4809c000 { compatible = "ti,omap4-hsmmc"; reg = <0x4809c000 0x400>; - interrupts = <0 83 0x4>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; @@ -354,7 +357,7 @@ mmc2: mmc@480b4000 { compatible = "ti,omap4-hsmmc"; reg = <0x480b4000 0x400>; - interrupts = <0 86 0x4>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc2"; ti,needs-special-reset; dmas = <&sdma 47>, <&sdma 48>; @@ -364,7 +367,7 @@ mmc3: mmc@480ad000 { compatible = "ti,omap4-hsmmc"; reg = <0x480ad000 0x400>; - interrupts = <0 94 0x4>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc3"; ti,needs-special-reset; dmas = <&sdma 77>, <&sdma 78>; @@ -374,7 +377,7 @@ mmc4: mmc@480d1000 { compatible = "ti,omap4-hsmmc"; reg = <0x480d1000 0x400>; - interrupts = <0 96 0x4>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc4"; ti,needs-special-reset; dmas = <&sdma 57>, <&sdma 58>; @@ -384,7 +387,7 @@ mmc5: mmc@480d5000 { compatible = "ti,omap4-hsmmc"; reg = <0x480d5000 0x400>; - interrupts = <0 59 0x4>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc5"; ti,needs-special-reset; dmas = <&sdma 59>, <&sdma 60>; @@ -394,7 +397,7 @@ wdt2: wdt@4a314000 { compatible = "ti,omap4-wdt", "ti,omap3-wdt"; reg = <0x4a314000 0x80>; - interrupts = <0 80 0x4>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "wd_timer2"; }; @@ -403,7 +406,7 @@ reg = <0x40132000 0x7f>, /* MPU private access */ <0x49032000 0x7f>; /* L3 Interconnect */ reg-names = "mpu", "dma"; - interrupts = <0 112 0x4>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mcpdm"; dmas = <&sdma 65>, <&sdma 66>; @@ -415,7 +418,7 @@ reg = <0x4012e000 0x7f>, /* MPU private access */ <0x4902e000 0x7f>; /* L3 Interconnect */ reg-names = "mpu", "dma"; - interrupts = <0 114 0x4>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "dmic"; dmas = <&sdma 67>; dma-names = "up_link"; @@ -426,7 +429,7 @@ reg = <0x40122000 0xff>, /* MPU private access */ <0x49022000 0xff>; /* L3 Interconnect */ reg-names = "mpu", "dma"; - interrupts = <0 17 0x4>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp1"; @@ -440,7 +443,7 @@ reg = <0x40124000 0xff>, /* MPU private access */ <0x49024000 0xff>; /* L3 Interconnect */ reg-names = "mpu", "dma"; - interrupts = <0 22 0x4>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp2"; @@ -454,7 +457,7 @@ reg = <0x40126000 0xff>, /* MPU private access */ <0x49026000 0xff>; /* L3 Interconnect */ reg-names = "mpu", "dma"; - interrupts = <0 23 0x4>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp3"; @@ -467,7 +470,7 @@ compatible = "ti,omap4-mcbsp"; reg = <0x48096000 0xff>; /* L4 Interconnect */ reg-names = "mpu"; - interrupts = <0 16 0x4>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp4"; @@ -479,7 +482,7 @@ keypad: keypad@4a31c000 { compatible = "ti,omap4-keypad"; reg = <0x4a31c000 0x80>; - interrupts = <0 120 0x4>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; reg-names = "mpu"; ti,hwmods = "kbd"; }; @@ -487,7 +490,7 @@ emif1: emif@4c000000 { compatible = "ti,emif-4d"; reg = <0x4c000000 0x100>; - interrupts = <0 110 0x4>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "emif1"; phy-type = <1>; hw-caps-read-idle-ctrl; @@ -498,7 +501,7 @@ emif2: emif@4d000000 { compatible = "ti,emif-4d"; reg = <0x4d000000 0x100>; - interrupts = <0 111 0x4>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "emif2"; phy-type = <1>; hw-caps-read-idle-ctrl; @@ -523,7 +526,7 @@ timer1: timer@4a318000 { compatible = "ti,omap3430-timer"; reg = <0x4a318000 0x80>; - interrupts = <0 37 0x4>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer1"; ti,timer-alwon; }; @@ -531,21 +534,21 @@ timer2: timer@48032000 { compatible = "ti,omap3430-timer"; reg = <0x48032000 0x80>; - interrupts = <0 38 0x4>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer2"; }; timer3: timer@48034000 { compatible = "ti,omap4430-timer"; reg = <0x48034000 0x80>; - interrupts = <0 39 0x4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer3"; }; timer4: timer@48036000 { compatible = "ti,omap4430-timer"; reg = <0x48036000 0x80>; - interrupts = <0 40 0x4>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer4"; }; @@ -553,7 +556,7 @@ compatible = "ti,omap4430-timer"; reg = <0x40138000 0x80>, <0x49038000 0x80>; - interrupts = <0 41 0x4>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer5"; ti,timer-dsp; }; @@ -562,7 +565,7 @@ compatible = "ti,omap4430-timer"; reg = <0x4013a000 0x80>, <0x4903a000 0x80>; - interrupts = <0 42 0x4>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer6"; ti,timer-dsp; }; @@ -571,7 +574,7 @@ compatible = "ti,omap4430-timer"; reg = <0x4013c000 0x80>, <0x4903c000 0x80>; - interrupts = <0 43 0x4>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer7"; ti,timer-dsp; }; @@ -580,7 +583,7 @@ compatible = "ti,omap4430-timer"; reg = <0x4013e000 0x80>, <0x4903e000 0x80>; - interrupts = <0 44 0x4>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer8"; ti,timer-pwm; ti,timer-dsp; @@ -589,7 +592,7 @@ timer9: timer@4803e000 { compatible = "ti,omap4430-timer"; reg = <0x4803e000 0x80>; - interrupts = <0 45 0x4>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer9"; ti,timer-pwm; }; @@ -597,7 +600,7 @@ timer10: timer@48086000 { compatible = "ti,omap3430-timer"; reg = <0x48086000 0x80>; - interrupts = <0 46 0x4>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer10"; ti,timer-pwm; }; @@ -605,7 +608,7 @@ timer11: timer@48088000 { compatible = "ti,omap4430-timer"; reg = <0x48088000 0x80>; - interrupts = <0 47 0x4>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer11"; ti,timer-pwm; }; @@ -613,7 +616,7 @@ usbhstll: usbhstll@4a062000 { compatible = "ti,usbhs-tll"; reg = <0x4a062000 0x1000>; - interrupts = <0 78 0x4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "usb_tll_hs"; }; @@ -629,14 +632,14 @@ compatible = "ti,ohci-omap3", "usb-ohci"; reg = <0x4a064800 0x400>; interrupt-parent = <&gic>; - interrupts = <0 76 0x4>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; }; usbhsehci: ehci@4a064c00 { compatible = "ti,ehci-omap", "usb-ehci"; reg = <0x4a064c00 0x400>; interrupt-parent = <&gic>; - interrupts = <0 77 0x4>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -651,7 +654,7 @@ usb_otg_hs: usb_otg_hs@4a0ab000 { compatible = "ti,omap4-musb"; reg = <0x4a0ab000 0x7ff>; - interrupts = <0 92 0x4>, <0 93 0x4>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mc", "dma"; ti,hwmods = "usb_otg_hs"; usb-phy = <&usb2_phy>; diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi index cccf39af4925..bcf455efe18d 100644 --- a/arch/arm/boot/dts/omap443x.dtsi +++ b/arch/arm/boot/dts/omap443x.dtsi @@ -8,7 +8,7 @@ * kind, whether express or implied. */ -/include/ "omap4.dtsi" +#include "omap4.dtsi" / { cpus { @@ -24,4 +24,10 @@ clock-latency = <300000>; /* From legacy driver */ }; }; + + bandgap { + reg = <0x4a002260 0x4 + 0x4a00232C 0x4>; + compatible = "ti,omap4430-bandgap"; + }; }; diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi index 2cf227c86099..c2f0f39b5a24 100644 --- a/arch/arm/boot/dts/omap4460.dtsi +++ b/arch/arm/boot/dts/omap4460.dtsi @@ -7,7 +7,7 @@ * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ -/include/ "omap4.dtsi" +#include "omap4.dtsi" / { cpus { @@ -25,8 +25,17 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 54 0x4>, - <0 55 0x4>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "debugss"; }; + + bandgap { + reg = <0x4a002260 0x4 + 0x4a00232C 0x4 + 0x4a002378 0x18>; + compatible = "ti,omap4460-bandgap"; + interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */ + gpios = <&gpio3 22 0>; /* tshut */ + }; }; diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts deleted file mode 100644 index 982acd19477d..000000000000 --- a/arch/arm/boot/dts/omap5-evm.dts +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -/include/ "omap5.dtsi" -/include/ "samsung_k3pe0e000b.dtsi" - -/ { - model = "TI OMAP5 EVM board"; - compatible = "ti,omap5-evm", "ti,omap5"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x7F000000>; /* 2032 MB */ - }; - - vmmcsd_fixed: fixedregulator-mmcsd { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - -}; - -&omap5_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &twl6040_pins - &mcpdm_pins - &dmic_pins - &mcbsp1_pins - &mcbsp2_pins - >; - - twl6040_pins: pinmux_twl6040_pins { - pinctrl-single,pins = < - 0x18a 0x6 /* perslimbus2_clock.gpio5_145 OUTPUT | MODE6 */ - >; - }; - - mcpdm_pins: pinmux_mcpdm_pins { - pinctrl-single,pins = < - 0x142 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */ - 0x15c 0x108 /* abemcpdm_ul_data.abemcpdm_ul_data INPUT PULLDOWN | MODE0 */ - 0x15e 0x108 /* abemcpdm_dl_data.abemcpdm_dl_data INPUT PULLDOWN | MODE0 */ - 0x160 0x118 /* abemcpdm_frame.abemcpdm_frame INPUT PULLUP | MODE0 */ - 0x162 0x108 /* abemcpdm_lb_clk.abemcpdm_lb_clk INPUT PULLDOWN | MODE0 */ - >; - }; - - dmic_pins: pinmux_dmic_pins { - pinctrl-single,pins = < - 0x144 0x100 /* abedmic_din1.abedmic_din1 INPUT | MODE0 */ - 0x146 0x100 /* abedmic_din2.abedmic_din2 INPUT | MODE0 */ - 0x148 0x100 /* abedmic_din3.abedmic_din3 INPUT | MODE0 */ - 0x14a 0 /* abedmic_clk1.abedmic_clk1 OUTPUT | MODE0 */ - >; - }; - - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,pins = < - 0x14c 0x101 /* abedmic_clk2.abemcbsp1_fsx INPUT | MODE1 */ - 0x14e 0x9 /* abedmic_clk3.abemcbsp1_dx OUTPUT PULLDOWN | MODE1 */ - 0x150 0x101 /* abeslimbus1_clock.abemcbsp1_clkx INPUT | MODE0 */ - 0x152 0x109 /* abeslimbus1_data.abemcbsp1_dr INPUT PULLDOWN | MODE1 */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - 0x154 0x108 /* abemcbsp2_dr.abemcbsp2_dr INPUT PULLDOWN | MODE0 */ - 0x156 0x8 /* abemcbsp2_dx.abemcbsp2_dx OUTPUT PULLDOWN | MODE0 */ - 0x158 0x100 /* abemcbsp2_fsx.abemcbsp2_fsx INPUT | MODE0 */ - 0x15a 0x100 /* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - 0x1b2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */ - 0x1b4 0x118 /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - 0x178 0x100 /* i2c2_scl INPUTENABLE | MODE0 */ - 0x17a 0x100 /* i2c2_sda INPUTENABLE | MODE0 */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - 0x13a 0x100 /* i2c3_scl INPUTENABLE | MODE0 */ - 0x13c 0x100 /* i2c3_sda INPUTENABLE | MODE0 */ - >; - }; - - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - 0xb8 0x100 /* i2c4_scl INPUTENABLE | MODE0 */ - 0xba 0x100 /* i2c4_sda INPUTENABLE | MODE0 */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - 0x184 0x100 /* i2c5_scl INPUTENABLE | MODE0 */ - 0x186 0x100 /* i2c5_sda INPUTENABLE | MODE0 */ - >; - }; - - mcspi2_pins: pinmux_mcspi2_pins { - pinctrl-single,pins = < - 0xbc 0x100 /* MCSPI2_CLK INPUTENABLE | MODE0 */ - 0xbe 0x100 /* MCSPI2_SIMO INPUTENABLE | MODE0 */ - 0xc0 0x118 /* MCSPI2_SOMI PULLUP | INPUTENABLE | MODE0*/ - 0xc2 0x0 /* MCSPI2_CS MODE0*/ - >; - }; - - mcspi3_pins: pinmux_mcspi3_pins { - pinctrl-single,pins = < - 0x78 0x101 /* MCSPI2_SOMI INPUTENABLE | MODE1 */ - 0x7a 0x101 /* MCSPI2_CS INPUTENABLE | MODE1 */ - 0x7c 0x101 /* MCSPI2_SIMO INPUTENABLE | MODE1 */ - 0x7e 0x101 /* MCSPI2_CLK INPUTENABLE | MODE1 */ - >; - }; - - mcspi4_pins: pinmux_mcspi4_pins { - pinctrl-single,pins = < - 0x164 0x101 /* MCSPI2_CLK INPUTENABLE | MODE1 */ - 0x168 0x101 /* MCSPI2_SIMO INPUTENABLE | MODE1 */ - 0x16a 0x101 /* MCSPI2_SOMI INPUTENABLE | MODE1 */ - 0x16c 0x101 /* MCSPI2_CS INPUTENABLE | MODE1 */ - >; - }; -}; - -&mmc1 { - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - bus-width = <4>; - ti,non-removable; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; - - /* Pressure Sensor */ - bmp085@77 { - compatible = "bosch,bmp085"; - reg = <0x77>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; - - /* Temperature Sensor */ - tmp102@48{ - compatible = "ti,tmp102"; - reg = <0x48>; - }; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - - clock-frequency = <400000>; -}; - -&keypad { - keypad,num-rows = <8>; - keypad,num-columns = <8>; - linux,keymap = <0x02020073 /* VOLUP */ - 0x02030072 /* VOLDOWM */ - 0x020400e7 /* SEND */ - 0x02050066 /* HOME */ - 0x0206006b /* END */ - 0x020700d9>; /* SEARCH */ - linux,input-no-autorepeat; -}; - -&mcbsp3 { - status = "disabled"; -}; - -&emif1 { - cs1-used; - device-handle = <&samsung_K3PE0E000B>; -}; - -&emif2 { - cs1-used; - device-handle = <&samsung_K3PE0E000B>; -}; - -&mcspi1 { - -}; - -&mcspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi2_pins>; -}; - -&mcspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi3_pins>; -}; - -&mcspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi4_pins>; -}; diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts new file mode 100644 index 000000000000..08b72678abff --- /dev/null +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -0,0 +1,485 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap5.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "TI OMAP5 uEVM board"; + compatible = "ti,omap5-uevm", "ti,omap5"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x7F000000>; /* 2032 MB */ + }; + + vmmcsd_fixed: fixedregulator-mmcsd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + /* HS USB Port 2 RESET */ + hsusb2_reset: hsusb2_reset_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_reset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 HUB_NRESET */ + startup-delay-us = <70000>; + enable-active-high; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-supply = <&hsusb2_reset>; + /** + * FIXME + * Put the right clock phandle here when available + * clocks = <&auxclk1>; + * clock-names = "main_clk"; + */ + clock-frequency = <19200000>; + }; + + /* HS USB Port 3 RESET */ + hsusb3_reset: hsusb3_reset_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb3_reset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* gpio3_79 ETH_NRESET */ + startup-delay-us = <70000>; + enable-active-high; + }; + + /* HS USB Host PHY on PORT 3 */ + hsusb3_phy: hsusb3_phy { + compatible = "usb-nop-xceiv"; + reset-supply = <&hsusb3_reset>; + }; + + leds { + compatible = "gpio-leds"; + led@1 { + label = "omap5:blue:usr1"; + gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; +}; + +&omap5_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6040_pins + &mcpdm_pins + &dmic_pins + &mcbsp1_pins + &mcbsp2_pins + &usbhost_pins + &led_gpio_pins + >; + + twl6040_pins: pinmux_twl6040_pins { + pinctrl-single,pins = < + 0x18a (PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ + >; + }; + + mcpdm_pins: pinmux_mcpdm_pins { + pinctrl-single,pins = < + 0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ + 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */ + 0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */ + 0x160 (PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */ + 0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */ + >; + }; + + dmic_pins: pinmux_dmic_pins { + pinctrl-single,pins = < + 0x144 (PIN_INPUT | MUX_MODE0) /* abedmic_din1.abedmic_din1 */ + 0x146 (PIN_INPUT | MUX_MODE0) /* abedmic_din2.abedmic_din2 */ + 0x148 (PIN_INPUT | MUX_MODE0) /* abedmic_din3.abedmic_din3 */ + 0x14a (PIN_OUTPUT | MUX_MODE0) /* abedmic_clk1.abedmic_clk1 */ + >; + }; + + mcbsp1_pins: pinmux_mcbsp1_pins { + pinctrl-single,pins = < + 0x14c (PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ + 0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */ + 0x150 (PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */ + 0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */ + >; + }; + + mcbsp2_pins: pinmux_mcbsp2_pins { + pinctrl-single,pins = < + 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */ + 0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */ + 0x158 (PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */ + 0x15a (PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x1b2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + i2c5_pins: pinmux_i2c5_pins { + pinctrl-single,pins = < + 0x184 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */ + 0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */ + >; + }; + + mcspi2_pins: pinmux_mcspi2_pins { + pinctrl-single,pins = < + 0xbc (PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ + 0xbe (PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ + 0xc0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ + 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs */ + >; + }; + + mcspi3_pins: pinmux_mcspi3_pins { + pinctrl-single,pins = < + 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ + 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ + 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ + 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ + >; + }; + + mcspi4_pins: pinmux_mcspi4_pins { + pinctrl-single,pins = < + 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ + 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ + 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ + 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ + >; + }; + + usbhost_pins: pinmux_usbhost_pins { + pinctrl-single,pins = < + 0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ + 0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ + + 0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ + 0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ + + 0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */ + 0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */ + >; + }; + + led_gpio_pins: pinmux_led_gpio_pins { + pinctrl-single,pins = < + 0x196 (PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */ + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x60 (PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */ + 0x62 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */ + 0x64 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */ + 0x66 (PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x19a (PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */ + 0x19c (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */ + >; + }; + + uart5_pins: pinmux_uart5_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */ + 0x172 (PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */ + 0x174 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */ + 0x176 (PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */ + >; + }; + +}; + +&omap5_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = < + &usbhost_wkup_pins + >; + + usbhost_wkup_pins: pinmux_usbhost_wkup_pins { + pinctrl-single,pins = < + 0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ + >; + }; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + ti,non-removable; +}; + +&mmc3 { + bus-width = <4>; + ti,non-removable; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + palmas: palmas@48 { + compatible = "ti,palmas"; + interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ + interrupt-parent = <&gic>; + reg = <0x48>; + interrupt-controller; + #interrupt-cells = <2>; + + palmas_pmic { + compatible = "ti,palmas-pmic"; + interrupt-parent = <&palmas>; + interrupts = <14 IRQ_TYPE_NONE>; + interrupt-name = "short-irq"; + + ti,ldo6-vibrator; + + regulators { + smps123_reg: smps123 { + regulator-name = "smps123"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + regulator-name = "smps45"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1310000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + regulator-name = "smps6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + smps7_reg: smps7 { + regulator-name = "smps7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8_reg: smps8 { + regulator-name = "smps8"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1310000>; + regulator-always-on; + regulator-boot-on; + }; + + smps9_reg: smps9 { + regulator-name = "smps9"; + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + regulator-always-on; + regulator-boot-on; + ti,smps-range = <0x80>; + }; + + smps10_reg: smps10 { + regulator-name = "smps10"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo7_reg: ldo7 { + regulator-name = "ldo7"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "ldo8"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: ldo9 { + regulator-name = "ldo9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + regulator-name = "ldousb"; + regulator-min-microvolt = <3250000>; + regulator-max-microvolt = <3250000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + + clock-frequency = <400000>; +}; + +&mcbsp3 { + status = "disabled"; +}; + +&usbhshost { + port2-mode = "ehci-hsic"; + port3-mode = "ehci-hsic"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy &hsusb3_phy>; +}; + +&mcspi1 { + +}; + +&mcspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi2_pins>; +}; + +&mcspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi3_pins>; +}; + +&mcspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi4_pins>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins>; +}; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 3dd7ff825828..e643620417a9 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -7,15 +7,11 @@ * Based on "omap4.dtsi" */ -/* - * Carveout for multimedia usecases - * It should be the last 48MB of the first 512MB memory part - * In theory, it should not even exist. That zone should be reserved - * dynamically during the .reserve callback. - */ -/memreserve/ 0x9d000000 0x03000000; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/omap.h> -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { #address-cells = <1>; @@ -34,21 +30,28 @@ }; cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; compatible = "arm,cortex-a15"; + reg = <0x0>; }; cpu@1 { + device_type = "cpu"; compatible = "arm,cortex-a15"; + reg = <0x1>; }; }; timer { compatible = "arm,armv7-timer"; - /* PPI secure/nonsecure IRQ, active low level-sensitive */ - interrupts = <1 13 0x308>, - <1 14 0x308>, - <1 11 0x308>, - <1 10 0x308>; + /* PPI secure/nonsecure IRQ */ + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; clock-frequency = <6144000>; }; @@ -90,8 +93,8 @@ reg = <0x44000000 0x2000>, <0x44800000 0x3000>, <0x45000000 0x4000>; - interrupts = <0 9 0x4>, - <0 10 0x4>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; counter32k: counter@4ae04000 { compatible = "ti,omap-counter32k"; @@ -119,10 +122,10 @@ sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; - interrupts = <0 12 0x4>, - <0 13 0x4>, - <0 14 0x4>, - <0 15 0x4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; #dma-channels = <32>; #dma-requests = <127>; @@ -131,7 +134,7 @@ gpio1: gpio@4ae10000 { compatible = "ti,omap4-gpio"; reg = <0x4ae10000 0x200>; - interrupts = <0 29 0x4>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "gpio1"; ti,gpio-always-on; gpio-controller; @@ -143,7 +146,7 @@ gpio2: gpio@48055000 { compatible = "ti,omap4-gpio"; reg = <0x48055000 0x200>; - interrupts = <0 30 0x4>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; @@ -154,7 +157,7 @@ gpio3: gpio@48057000 { compatible = "ti,omap4-gpio"; reg = <0x48057000 0x200>; - interrupts = <0 31 0x4>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; @@ -165,7 +168,7 @@ gpio4: gpio@48059000 { compatible = "ti,omap4-gpio"; reg = <0x48059000 0x200>; - interrupts = <0 32 0x4>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; @@ -176,7 +179,7 @@ gpio5: gpio@4805b000 { compatible = "ti,omap4-gpio"; reg = <0x4805b000 0x200>; - interrupts = <0 33 0x4>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "gpio5"; gpio-controller; #gpio-cells = <2>; @@ -187,7 +190,7 @@ gpio6: gpio@4805d000 { compatible = "ti,omap4-gpio"; reg = <0x4805d000 0x200>; - interrupts = <0 34 0x4>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "gpio6"; gpio-controller; #gpio-cells = <2>; @@ -198,7 +201,7 @@ gpio7: gpio@48051000 { compatible = "ti,omap4-gpio"; reg = <0x48051000 0x200>; - interrupts = <0 35 0x4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "gpio7"; gpio-controller; #gpio-cells = <2>; @@ -209,7 +212,7 @@ gpio8: gpio@48053000 { compatible = "ti,omap4-gpio"; reg = <0x48053000 0x200>; - interrupts = <0 121 0x4>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "gpio8"; gpio-controller; #gpio-cells = <2>; @@ -222,7 +225,7 @@ reg = <0x50000000 0x1000>; #address-cells = <2>; #size-cells = <1>; - interrupts = <0 20 0x4>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; @@ -231,7 +234,7 @@ i2c1: i2c@48070000 { compatible = "ti,omap4-i2c"; reg = <0x48070000 0x100>; - interrupts = <0 56 0x4>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; @@ -240,7 +243,7 @@ i2c2: i2c@48072000 { compatible = "ti,omap4-i2c"; reg = <0x48072000 0x100>; - interrupts = <0 57 0x4>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; @@ -249,7 +252,7 @@ i2c3: i2c@48060000 { compatible = "ti,omap4-i2c"; reg = <0x48060000 0x100>; - interrupts = <0 61 0x4>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; @@ -258,7 +261,7 @@ i2c4: i2c@4807a000 { compatible = "ti,omap4-i2c"; reg = <0x4807a000 0x100>; - interrupts = <0 62 0x4>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c4"; @@ -267,7 +270,7 @@ i2c5: i2c@4807c000 { compatible = "ti,omap4-i2c"; reg = <0x4807c000 0x100>; - interrupts = <0 60 0x4>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c5"; @@ -276,7 +279,7 @@ mcspi1: spi@48098000 { compatible = "ti,omap4-mcspi"; reg = <0x48098000 0x200>; - interrupts = <0 65 0x4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi1"; @@ -296,7 +299,7 @@ mcspi2: spi@4809a000 { compatible = "ti,omap4-mcspi"; reg = <0x4809a000 0x200>; - interrupts = <0 66 0x4>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi2"; @@ -311,7 +314,7 @@ mcspi3: spi@480b8000 { compatible = "ti,omap4-mcspi"; reg = <0x480b8000 0x200>; - interrupts = <0 91 0x4>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi3"; @@ -323,7 +326,7 @@ mcspi4: spi@480ba000 { compatible = "ti,omap4-mcspi"; reg = <0x480ba000 0x200>; - interrupts = <0 48 0x4>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi4"; @@ -335,7 +338,7 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; reg = <0x4806a000 0x100>; - interrupts = <0 72 0x4>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; @@ -343,7 +346,7 @@ uart2: serial@4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; - interrupts = <0 73 0x4>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; @@ -351,7 +354,7 @@ uart3: serial@48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; - interrupts = <0 74 0x4>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; @@ -359,7 +362,7 @@ uart4: serial@4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; - interrupts = <0 70 0x4>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; @@ -367,7 +370,7 @@ uart5: serial@48066000 { compatible = "ti,omap4-uart"; reg = <0x48066000 0x100>; - interrupts = <0 105 0x4>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart5"; clock-frequency = <48000000>; }; @@ -375,7 +378,7 @@ uart6: serial@48068000 { compatible = "ti,omap4-uart"; reg = <0x48068000 0x100>; - interrupts = <0 106 0x4>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart6"; clock-frequency = <48000000>; }; @@ -383,7 +386,7 @@ mmc1: mmc@4809c000 { compatible = "ti,omap4-hsmmc"; reg = <0x4809c000 0x400>; - interrupts = <0 83 0x4>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; @@ -394,7 +397,7 @@ mmc2: mmc@480b4000 { compatible = "ti,omap4-hsmmc"; reg = <0x480b4000 0x400>; - interrupts = <0 86 0x4>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc2"; ti,needs-special-reset; dmas = <&sdma 47>, <&sdma 48>; @@ -404,7 +407,7 @@ mmc3: mmc@480ad000 { compatible = "ti,omap4-hsmmc"; reg = <0x480ad000 0x400>; - interrupts = <0 94 0x4>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc3"; ti,needs-special-reset; dmas = <&sdma 77>, <&sdma 78>; @@ -414,7 +417,7 @@ mmc4: mmc@480d1000 { compatible = "ti,omap4-hsmmc"; reg = <0x480d1000 0x400>; - interrupts = <0 96 0x4>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc4"; ti,needs-special-reset; dmas = <&sdma 57>, <&sdma 58>; @@ -424,7 +427,7 @@ mmc5: mmc@480d5000 { compatible = "ti,omap4-hsmmc"; reg = <0x480d5000 0x400>; - interrupts = <0 59 0x4>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc5"; ti,needs-special-reset; dmas = <&sdma 59>, <&sdma 60>; @@ -442,7 +445,7 @@ reg = <0x40132000 0x7f>, /* MPU private access */ <0x49032000 0x7f>; /* L3 Interconnect */ reg-names = "mpu", "dma"; - interrupts = <0 112 0x4>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mcpdm"; dmas = <&sdma 65>, <&sdma 66>; @@ -454,7 +457,7 @@ reg = <0x4012e000 0x7f>, /* MPU private access */ <0x4902e000 0x7f>; /* L3 Interconnect */ reg-names = "mpu", "dma"; - interrupts = <0 114 0x4>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "dmic"; dmas = <&sdma 67>; dma-names = "up_link"; @@ -465,7 +468,7 @@ reg = <0x40122000 0xff>, /* MPU private access */ <0x49022000 0xff>; /* L3 Interconnect */ reg-names = "mpu", "dma"; - interrupts = <0 17 0x4>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp1"; @@ -479,7 +482,7 @@ reg = <0x40124000 0xff>, /* MPU private access */ <0x49024000 0xff>; /* L3 Interconnect */ reg-names = "mpu", "dma"; - interrupts = <0 22 0x4>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp2"; @@ -493,7 +496,7 @@ reg = <0x40126000 0xff>, /* MPU private access */ <0x49026000 0xff>; /* L3 Interconnect */ reg-names = "mpu", "dma"; - interrupts = <0 23 0x4>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp3"; @@ -505,7 +508,7 @@ timer1: timer@4ae18000 { compatible = "ti,omap5430-timer"; reg = <0x4ae18000 0x80>; - interrupts = <0 37 0x4>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer1"; ti,timer-alwon; }; @@ -513,21 +516,21 @@ timer2: timer@48032000 { compatible = "ti,omap5430-timer"; reg = <0x48032000 0x80>; - interrupts = <0 38 0x4>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer2"; }; timer3: timer@48034000 { compatible = "ti,omap5430-timer"; reg = <0x48034000 0x80>; - interrupts = <0 39 0x4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer3"; }; timer4: timer@48036000 { compatible = "ti,omap5430-timer"; reg = <0x48036000 0x80>; - interrupts = <0 40 0x4>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer4"; }; @@ -535,16 +538,17 @@ compatible = "ti,omap5430-timer"; reg = <0x40138000 0x80>, <0x49038000 0x80>; - interrupts = <0 41 0x4>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer5"; ti,timer-dsp; + ti,timer-pwm; }; timer6: timer@4013a000 { compatible = "ti,omap5430-timer"; reg = <0x4013a000 0x80>, <0x4903a000 0x80>; - interrupts = <0 42 0x4>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer6"; ti,timer-dsp; ti,timer-pwm; @@ -554,7 +558,7 @@ compatible = "ti,omap5430-timer"; reg = <0x4013c000 0x80>, <0x4903c000 0x80>; - interrupts = <0 43 0x4>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer7"; ti,timer-dsp; }; @@ -563,7 +567,7 @@ compatible = "ti,omap5430-timer"; reg = <0x4013e000 0x80>, <0x4903e000 0x80>; - interrupts = <0 44 0x4>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer8"; ti,timer-dsp; ti,timer-pwm; @@ -572,21 +576,23 @@ timer9: timer@4803e000 { compatible = "ti,omap5430-timer"; reg = <0x4803e000 0x80>; - interrupts = <0 45 0x4>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer9"; + ti,timer-pwm; }; timer10: timer@48086000 { compatible = "ti,omap5430-timer"; reg = <0x48086000 0x80>; - interrupts = <0 46 0x4>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer10"; + ti,timer-pwm; }; timer11: timer@48088000 { compatible = "ti,omap5430-timer"; reg = <0x48088000 0x80>; - interrupts = <0 47 0x4>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer11"; ti,timer-pwm; }; @@ -594,7 +600,7 @@ wdt2: wdt@4ae14000 { compatible = "ti,omap5-wdt", "ti,omap3-wdt"; reg = <0x4ae14000 0x80>; - interrupts = <0 80 0x4>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "wd_timer2"; }; @@ -603,7 +609,7 @@ ti,hwmods = "emif1"; phy-type = <2>; /* DDR PHY type: Intelli PHY */ reg = <0x4c000000 0x400>; - interrupts = <0 110 0x4>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; hw-caps-read-idle-ctrl; hw-caps-ll-interface; hw-caps-temp-alert; @@ -614,7 +620,7 @@ ti,hwmods = "emif2"; phy-type = <2>; /* DDR PHY type: Intelli PHY */ reg = <0x4d000000 0x400>; - interrupts = <0 111 0x4>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; hw-caps-read-idle-ctrl; hw-caps-ll-interface; hw-caps-temp-alert; @@ -632,7 +638,7 @@ compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss"; reg = <0x4a020000 0x1000>; - interrupts = <0 93 4>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; @@ -640,7 +646,7 @@ dwc3@4a030000 { compatible = "synopsys,dwc3"; reg = <0x4a030000 0x1000>; - interrupts = <0 92 4>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; usb-phy = <&usb2_phy>, <&usb3_phy>; tx-fifo-resize; }; @@ -667,5 +673,44 @@ ctrl-module = <&omap_control_usb>; }; }; + + usbhstll: usbhstll@4a062000 { + compatible = "ti,usbhs-tll"; + reg = <0x4a062000 0x1000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "usb_tll_hs"; + }; + + usbhshost: usbhshost@4a064000 { + compatible = "ti,usbhs-host"; + reg = <0x4a064000 0x800>; + ti,hwmods = "usb_host_hs"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbhsohci: ohci@4a064800 { + compatible = "ti,ohci-omap3", "usb-ohci"; + reg = <0x4a064800 0x400>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + }; + + usbhsehci: ehci@4a064c00 { + compatible = "ti,ehci-omap", "usb-ehci"; + reg = <0x4a064c00 0x400>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + bandgap@4a0021e0 { + reg = <0x4a0021e0 0xc + 0x4a00232c 0xc + 0x4a002380 0x2c + 0x4a0023C0 0x3c>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + compatible = "ti,omap5430-bandgap"; + }; }; }; diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi index f0a8c2068ea7..533919e96eae 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi @@ -18,13 +18,13 @@ #size-cells = <1>; cpus { - #address-cells = <1>; + #address-cells = <0>; #size-cells = <0>; - cpu@0 { - compatible = "arm,1176jz-s"; + cpu { + compatible = "arm,arm1176jz-s"; + device_type = "cpu"; clock-frequency = <400000000>; - reg = <0>; d-cache-line-size = <32>; d-cache-size = <32768>; i-cache-line-size = <32>; diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi index daa962d191e6..ab3e80085511 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi @@ -18,13 +18,13 @@ #size-cells = <1>; cpus { - #address-cells = <1>; + #address-cells = <0>; #size-cells = <0>; - cpu@0 { - compatible = "arm,1176jz-s"; + cpu { + compatible = "arm,arm1176jz-s"; + device_type = "cpu"; cpu-clock = <&arm_clk>, "cpu"; - reg = <0>; d-cache-line-size = <32>; d-cache-size = <32768>; i-cache-line-size = <32>; diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts index 387fedb58988..33ffabe9c4c8 100644 --- a/arch/arm/boot/dts/pm9g45.dts +++ b/arch/arm/boot/dts/pm9g45.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ /dts-v1/; -/include/ "at91sam9g45.dtsi" +#include "at91sam9g45.dtsi" / { model = "Ronetix pm9g45"; @@ -42,15 +42,15 @@ board { pinctrl_board_nand: nand0-board { atmel,pins = - <3 3 0x0 0x1 /* PD3 gpio RDY pin pull_up*/ - 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */ + <AT91_PIOD 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD3 gpio RDY pin pull_up*/ + AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ }; }; mmc { pinctrl_board_mmc: mmc0-board { atmel,pins = - <3 6 0x0 0x5>; /* PD6 gpio CD pin pull_up and deglitch */ + <AT91_PIOD 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD6 gpio CD pin pull_up and deglitch */ }; }; }; @@ -64,7 +64,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioD 6 0>; + cd-gpios = <&pioD 6 GPIO_ACTIVE_HIGH>; }; }; @@ -81,8 +81,8 @@ nand-on-flash-bbt; pinctrl-0 = <&pinctrl_board_nand>; - gpios = <&pioD 3 0 - &pioC 14 0 + gpios = <&pioD 3 GPIO_ACTIVE_HIGH + &pioC 14 GPIO_ACTIVE_HIGH 0 >; @@ -134,13 +134,13 @@ led0 { label = "led0"; - gpios = <&pioD 0 1>; + gpios = <&pioD 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "nand-disk"; }; led1 { label = "led1"; - gpios = <&pioD 31 0>; + gpios = <&pioD 31 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; @@ -152,13 +152,13 @@ right { label = "SW4"; - gpios = <&pioE 7 1>; + gpios = <&pioE 7 GPIO_ACTIVE_LOW>; linux,code = <106>; }; up { label = "SW3"; - gpios = <&pioE 8 1>; + gpios = <&pioE 8 GPIO_ACTIVE_LOW>; linux,code = <103>; }; }; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 3329719a9412..05e9489cf95c 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -18,6 +18,8 @@ #size-cells = <0>; cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; reg = <0x0>; d-cache-line-size = <32>; i-cache-line-size = <32>; @@ -608,7 +610,7 @@ }; rtc-iobg { - compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; + compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x80030000 0x10000>; diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index f18aad35e8b3..a5e90f078aa9 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -23,8 +23,11 @@ }; cpus { - cpu@0 { - compatible = "arm,xscale"; + #address-cells = <0>; + #size-cells = <0>; + cpu { + compatible = "marvell,xscale"; + device_type = "cpu"; }; }; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index fde2a337d1ff..4ff2019c0e30 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -37,12 +37,6 @@ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <1 9 0xf04>; - - gic-cpuif@4 { - compatible = "arm,gic-cpuif"; - cpuif-id = <4>; - cpu = <&cpu0>; - }; }; timer { diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts new file mode 100644 index 000000000000..09ea22c26359 --- /dev/null +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -0,0 +1,45 @@ +/* + * Reference Device Tree Source for the armadillo 800 eva board + * + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +/include/ "r8a7740.dtsi" + +/ { + model = "armadillo 800 eva reference"; + compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740"; + + chosen { + bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw"; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + +}; + +&i2c0 { + touchscreen: st1232@55 { + compatible = "sitronix,st1232"; + reg = <0x55>; + interrupt-parent = <&irqpin1>; + interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */ + }; +}; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 798fa35c0005..24e930643821 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -14,8 +14,129 @@ compatible = "renesas,r8a7740"; cpus { + #address-cells = <1>; + #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x0>; }; }; + + gic: interrupt-controller@c2800000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xc2800000 0x1000>, + <0xc2000000 0x1000>; + }; + + /* irqpin0: IRQ0 - IRQ7 */ + irqpin0: irqpin@e6900000 { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900000 4>, + <0xe6900010 4>, + <0xe6900020 1>, + <0xe6900040 1>, + <0xe6900060 1>; + interrupt-parent = <&gic>; + interrupts = <0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4>; + }; + + /* irqpin1: IRQ8 - IRQ15 */ + irqpin1: irqpin@e6900004 { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900004 4>, + <0xe6900014 4>, + <0xe6900024 1>, + <0xe6900044 1>, + <0xe6900064 1>; + interrupt-parent = <&gic>; + interrupts = <0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4>; + }; + + /* irqpin2: IRQ16 - IRQ23 */ + irqpin2: irqpin@e6900008 { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900008 4>, + <0xe6900018 4>, + <0xe6900028 1>, + <0xe6900048 1>, + <0xe6900068 1>; + interrupt-parent = <&gic>; + interrupts = <0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4>; + }; + + /* irqpin3: IRQ24 - IRQ31 */ + irqpin3: irqpin@e690000c { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe690000c 4>, + <0xe690001c 4>, + <0xe690002c 1>, + <0xe690004c 1>, + <0xe690006c 1>; + interrupt-parent = <&gic>; + interrupts = <0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4 + 0 149 0x4>; + }; + + i2c0: i2c@fff20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; + reg = <0xfff20000 0x425>; + interrupt-parent = <&gic>; + interrupts = <0 201 0x4 + 0 202 0x4 + 0 203 0x4 + 0 204 0x4>; + }; + + i2c1: i2c@e6c20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; + reg = <0xe6c20000 0x425>; + interrupt-parent = <&gic>; + interrupts = <0 70 0x4 + 0 71 0x4 + 0 72 0x4 + 0 73 0x4>; + }; }; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index fe5c6f213271..7f146c6bf756 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -48,6 +48,23 @@ <0xf0000100 0x100>; }; + irqpin0: irqpin@fe780010 { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xfe78001c 4>, + <0xfe780010 4>, + <0xfe780024 4>, + <0xfe780044 4>, + <0xfe780064 4>; + interrupt-parent = <&gic>; + interrupts = <0 27 0x4 + 0 28 0x4 + 0 29 0x4 + 0 30 0x4>; + sense-bitfield-width = <2>; + }; + i2c0: i2c@0xffc70000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 7a1711027e41..339d9b11721c 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -36,12 +36,6 @@ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <1 9 0xf04>; - - gic-cpuif@4 { - compatible = "arm,gic-cpuif"; - cpuif-id = <4>; - cpu = <&cpu0>; - }; }; timer { diff --git a/arch/arm/boot/dts/rk3066a-clocks.dtsi b/arch/arm/boot/dts/rk3066a-clocks.dtsi new file mode 100644 index 000000000000..6e307fc4c451 --- /dev/null +++ b/arch/arm/boot/dts/rk3066a-clocks.dtsi @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * This is a dummy clock, to be used as placeholder on + * other mux clocks when a specific parent clock is not + * yet implemented. It should be dropped when the driver + * is complete. + */ + dummy: dummy { + compatible = "fixed-clock"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + + dummy48m: dummy48m { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + dummy150m: dummy150m { + compatible = "fixed-clock"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + clk_gates0: gate-clk@200000d0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d0 0x4>; + clocks = <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_core_periph", "gate_cpu_gpll", + "gate_ddrphy", "gate_aclk_cpu", + "gate_hclk_cpu", "gate_pclk_cpu", + "gate_atclk_cpu", "gate_i2s0", + "gate_i2s0_frac", "gate_i2s1", + "gate_i2s1_frac", "gate_i2s2", + "gate_i2s2_frac", "gate_spdif", + "gate_spdif_frac", "gate_testclk"; + + #clock-cells = <1>; + }; + + clk_gates1: gate-clk@200000d4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d4 0x4>; + clocks = <&xin24m>, <&xin24m>, + <&xin24m>, <&dummy>, + <&dummy>, <&xin24m>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>; + + clock-output-names = + "gate_timer0", "gate_timer1", + "gate_timer2", "gate_jtag", + "gate_aclk_lcdc1_src", "gate_otgphy0", + "gate_otgphy1", "gate_ddr_gpll", + "gate_uart0", "gate_frac_uart0", + "gate_uart1", "gate_frac_uart1", + "gate_uart2", "gate_frac_uart2", + "gate_uart3", "gate_frac_uart3"; + + #clock-cells = <1>; + }; + + clk_gates2: gate-clk@200000d8 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d8 0x4>; + clocks = <&clk_gates2 1>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&clk_gates2 3>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy48m>, + <&dummy>, <&dummy48m>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_periph_src", "gate_aclk_periph", + "gate_hclk_periph", "gate_pclk_periph", + "gate_smc", "gate_mac", + "gate_hsadc", "gate_hsadc_frac", + "gate_saradc", "gate_spi0", + "gate_spi1", "gate_mmc0", + "gate_mac_lbtest", "gate_mmc1", + "gate_emmc", "gate_tsadc"; + + #clock-cells = <1>; + }; + + clk_gates3: gate-clk@200000dc { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000dc 0x4>; + clocks = <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_aclk_lcdc0_src", "gate_dclk_lcdc0", + "gate_dclk_lcdc1", "gate_pclkin_cif0", + "gate_pclkin_cif1", "reserved", + "reserved", "gate_cif0_out", + "gate_cif1_out", "gate_aclk_vepu", + "gate_hclk_vepu", "gate_aclk_vdpu", + "gate_hclk_vdpu", "gate_gpu_src", + "reserved", "gate_xin27m"; + + #clock-cells = <1>; + }; + + clk_gates4: gate-clk@200000e0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e0 0x4>; + clocks = <&clk_gates2 2>, <&clk_gates2 3>, + <&clk_gates2 1>, <&clk_gates2 1>, + <&clk_gates2 1>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates2 2>, + <&clk_gates0 4>, <&clk_gates0 4>, + <&clk_gates0 3>, <&clk_gates0 3>, + <&clk_gates0 3>, <&clk_gates2 3>, + <&clk_gates0 4>; + + clock-output-names = + "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix", + "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix", + "gate_aclk_pei_niu", "gate_hclk_usb_peri", + "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri", + "gate_hclk_cpubus", "gate_hclk_ahb2apb", + "gate_aclk_strc_sys", "gate_aclk_l2mem_con", + "gate_aclk_intmem", "gate_pclk_tsadc", + "gate_hclk_hdmi"; + + #clock-cells = <1>; + }; + + clk_gates5: gate-clk@200000e4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e4 0x4>; + clocks = <&clk_gates0 3>, <&clk_gates2 1>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates0 4>, <&clk_gates0 5>, + <&clk_gates2 1>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates4 5>, + <&clk_gates4 5>, <&dummy>; + + clock-output-names = + "gate_aclk_dmac1", "gate_aclk_dmac2", + "gate_pclk_efuse", "gate_pclk_tzpc", + "gate_pclk_grf", "gate_pclk_pmu", + "gate_hclk_rom", "gate_pclk_ddrupctl", + "gate_aclk_smc", "gate_hclk_nandc", + "gate_hclk_mmc0", "gate_hclk_mmc1", + "gate_hclk_emmc", "gate_hclk_otg0", + "gate_hclk_otg1", "gate_aclk_gpu"; + + #clock-cells = <1>; + }; + + clk_gates6: gate-clk@200000e8 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e8 0x4>; + clocks = <&clk_gates3 0>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates1 4>, + <&clk_gates0 4>, <&clk_gates3 0>, + <&clk_gates0 4>, <&clk_gates1 4>, + <&clk_gates3 0>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates1 4>, + <&clk_gates0 4>, <&clk_gates3 0>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_aclk_lcdc0", "gate_hclk_lcdc0", + "gate_hclk_lcdc1", "gate_aclk_lcdc1", + "gate_hclk_cif0", "gate_aclk_cif0", + "gate_hclk_cif1", "gate_aclk_cif1", + "gate_aclk_ipp", "gate_hclk_ipp", + "gate_hclk_rga", "gate_aclk_rga", + "gate_hclk_vio_bus", "gate_aclk_vio0", + "gate_aclk_vcodec", "gate_shclk_vio_h2h"; + + #clock-cells = <1>; + }; + + clk_gates7: gate-clk@200000ec { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000ec 0x4>; + clocks = <&clk_gates2 2>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates2 3>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&clk_gates2 3>, <&clk_gates2 3>; + + clock-output-names = + "gate_hclk_emac", "gate_hclk_spdif", + "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch", + "gate_hclk_i2s_8ch", "gate_hclk_hsadc", + "gate_hclk_pidf", "gate_pclk_timer0", + "gate_pclk_timer1", "gate_pclk_timer2", + "gate_pclk_pwm01", "gate_pclk_pwm23", + "gate_pclk_spi0", "gate_pclk_spi1", + "gate_pclk_saradc", "gate_pclk_wdt"; + + #clock-cells = <1>; + }; + + clk_gates8: gate-clk@200000f0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000f0 0x4>; + clocks = <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&clk_gates2 3>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&dummy>, <&clk_gates0 5>; + + clock-output-names = + "gate_pclk_uart0", "gate_pclk_uart1", + "gate_pclk_uart2", "gate_pclk_uart3", + "gate_pclk_i2c0", "gate_pclk_i2c1", + "gate_pclk_i2c2", "gate_pclk_i2c3", + "gate_pclk_i2c4", "gate_pclk_gpio0", + "gate_pclk_gpio1", "gate_pclk_gpio2", + "gate_pclk_gpio3", "gate_pclk_gpio4", + "reserved", "gate_pclk_gpio6"; + + #clock-cells = <1>; + }; + + clk_gates9: gate-clk@200000f4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000f4 0x4>; + clocks = <&dummy>, <&clk_gates0 5>, + <&dummy>, <&dummy>, + <&dummy>, <&clk_gates1 4>, + <&clk_gates0 5>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>; + + clock-output-names = + "gate_clk_core_dbg", "gate_pclk_dbg", + "gate_clk_trace", "gate_atclk", + "gate_clk_l2c", "gate_aclk_vio1", + "gate_pclk_publ", "gate_aclk_intmem0", + "gate_aclk_intmem1", "gate_aclk_intmem2", + "gate_aclk_intmem3"; + + #clock-cells = <1>; + }; + }; + +}; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi new file mode 100644 index 000000000000..56bfac93d3f6 --- /dev/null +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "skeleton.dtsi" +#include "rk3066a-clocks.dtsi" + +/ { + compatible = "rockchip,rk3066a"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x1>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@1013d000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1013d000 0x1000>, + <0x1013c100 0x0100>; + }; + + L2: l2-cache-controller@10138000 { + compatible = "arm,pl310-cache"; + reg = <0x10138000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + local-timer@1013c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1013c600 0x20>; + interrupts = <GIC_PPI 13 0x304>; + clocks = <&dummy150m>; + }; + + timer@20038000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x20038000 0x100>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates1 0>, <&clk_gates7 7>; + clock-names = "timer", "pclk"; + }; + + timer@2003a000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2003a000 0x100>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates1 1>, <&clk_gates7 8>; + clock-names = "timer", "pclk"; + }; + + timer@2000e000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2000e000 0x100>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates1 2>, <&clk_gates7 9>; + clock-names = "timer", "pclk"; + }; + + pinctrl@20008000 { + compatible = "rockchip,rk3066a-pinctrl"; + reg = <0x20008000 0x150>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 9>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 10>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 11>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 12>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 13>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio6@2000a000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2000a000 0x100>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 15>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_default: pcfg_pull_default { + bias-pull-pin-default; + }; + + pcfg_pull_none: pcfg_pull_none { + bias-disable; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_cmd: sd0-cmd { + rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_cd: sd0-cd { + rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_wp: sd0-wp { + rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_bus1: sd0-bus-width1 { + rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_bus4: sd0-bus-width4 { + rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_cmd: sd1-cmd { + rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_cd: sd1-cd { + rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_wp: sd1-wp { + rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_bus1: sd1-bus-width1 { + rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_bus4: sd1-bus-width4 { + rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + }; + + uart0: serial@10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 8>; + status = "disabled"; + }; + + uart1: serial@10126000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10126000 0x400>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 10>; + status = "disabled"; + }; + + uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 12>; + status = "disabled"; + }; + + uart3: serial@20068000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20068000 0x400>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 14>; + status = "disabled"; + }; + + dwmmc@10214000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10214000 0x1000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&clk_gates5 10>, <&clk_gates2 11>; + clock-names = "biu", "ciu"; + + status = "disabled"; + }; + + dwmmc@10218000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10218000 0x1000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&clk_gates5 11>, <&clk_gates2 13>; + clock-names = "biu", "ciu"; + + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi new file mode 100644 index 000000000000..527e3193817f --- /dev/null +++ b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi @@ -0,0 +1,173 @@ +/* + * Samsung S3C2416 pinctrl settings + * + * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&pinctrl_0 { + /* + * Pin banks + */ + + gpa: gpa { + gpio-controller; + #gpio-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc: gpc { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd: gpd { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe: gpe { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf: gpf { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg: gpg { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph: gph { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj: gpj { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk: gpk { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl: gpl { + gpio-controller; + #gpio-cells = <2>; + }; + + gpm: gpm { + gpio-controller; + #gpio-cells = <2>; + }; + + /* + * Pin groups + */ + + uart0_data: uart0-data { + samsung,pins = "gph-0", "gph-1"; + samsung,pin-function = <2>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gph-8", "gph-9"; + samsung,pin-function = <2>; + }; + + uart1_data: uart1-data { + samsung,pins = "gph-2", "gph-3"; + samsung,pin-function = <2>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gph-10", "gph-11"; + samsung,pin-function = <2>; + }; + + uart2_data: uart2-data { + samsung,pins = "gph-4", "gph-5"; + samsung,pin-function = <2>; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gph-6", "gph-7"; + samsung,pin-function = <2>; + }; + + uart3_data: uart3-data { + samsung,pins = "gph-6", "gph-7"; + samsung,pin-function = <2>; + }; + + extuart_clk: extuart-clk { + samsung,pins = "gph-12"; + samsung,pin-function = <2>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpe-14", "gpe-15"; + samsung,pin-function = <2>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpe-11", "gpe-12", "gpe-13"; + samsung,pin-function = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpe-5"; + samsung,pin-function = <2>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpe-6"; + samsung,pin-function = <2>; + }; + + sd0_bus1: sd0-bus1 { + samsung,pins = "gpe-7"; + samsung,pin-function = <2>; + }; + + sd0_bus4: sd0-bus4 { + samsung,pins = "gpe-8", "gpe-9", "gpe-10"; + samsung,pin-function = <2>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpl-8"; + samsung,pin-function = <2>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpl-9"; + samsung,pin-function = <2>; + }; + + sd1_bus1: sd1-bus1 { + samsung,pins = "gpl-0"; + samsung,pin-function = <2>; + }; + + sd1_bus4: sd1-bus4 { + samsung,pins = "gpl-1", "gpl-2", "gpl-3"; + samsung,pin-function = <2>; + }; +}; diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts new file mode 100644 index 000000000000..59594cf15998 --- /dev/null +++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts @@ -0,0 +1,72 @@ +/* + * SAMSUNG SMDK2416 board device tree source + * + * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include "s3c2416.dtsi" + +/ { + model = "SMDK2416"; + compatible = "samsung,s3c2416"; + + memory { + reg = <0x30000000 0x4000000>; + }; + + serial@50000000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_data>, <&uart0_fctl>; + }; + + serial@50004000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_data>, <&uart1_fctl>; + }; + + serial@50008000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_data>; + }; + + serial@5000C000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_data>; + }; + + watchdog@53000000 { + status = "okay"; + }; + + rtc@57000000 { + status = "okay"; + }; + + sdhci@4AC00000 { + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, + <&sd0_bus1>, <&sd0_bus4>; + bus-width = <4>; + cd-gpios = <&gpf 1 0>; + cd-inverted; + status = "okay"; + }; + + sdhci@4A800000 { + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, + <&sd1_bus1>, <&sd1_bus4>; + bus-width = <4>; + broken-cd; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi new file mode 100644 index 000000000000..e6555bdd81b8 --- /dev/null +++ b/arch/arm/boot/dts/s3c2416.dtsi @@ -0,0 +1,79 @@ +/* + * Samsung's S3C2416 SoC device tree source + * + * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "s3c24xx.dtsi" +#include "s3c2416-pinctrl.dtsi" + +/ { + model = "Samsung S3C2416 SoC"; + compatible = "samsung,s3c2416"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ejs"; + }; + }; + + interrupt-controller@4a000000 { + compatible = "samsung,s3c2416-irq"; + }; + + pinctrl@56000000 { + compatible = "samsung,s3c2416-pinctrl"; + }; + + serial@50000000 { + compatible = "samsung,s3c2440-uart"; + }; + + serial@50004000 { + compatible = "samsung,s3c2440-uart"; + }; + + serial@50008000 { + compatible = "samsung,s3c2440-uart"; + }; + + serial@5000C000 { + compatible = "samsung,s3c2440-uart"; + reg = <0x5000C000 0x4000>; + interrupts = <1 18 24 4>, <1 18 25 4>; + status = "disabled"; + }; + + sdhci@4AC00000 { + compatible = "samsung,s3c6410-sdhci"; + reg = <0x4AC00000 0x100>; + interrupts = <0 0 21 3>; + status = "disabled"; + }; + + sdhci@4A800000 { + compatible = "samsung,s3c6410-sdhci"; + reg = <0x4A800000 0x100>; + interrupts = <0 0 20 3>; + status = "disabled"; + }; + + watchdog@53000000 { + interrupts = <1 9 27 3>; + }; + + rtc@57000000 { + compatible = "samsung,s3c2416-rtc"; + }; + + i2c@54000000 { + compatible = "samsung,s3c2440-i2c"; + }; +}; diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi new file mode 100644 index 000000000000..2d1d7dc9418a --- /dev/null +++ b/arch/arm/boot/dts/s3c24xx.dtsi @@ -0,0 +1,92 @@ +/* + * Samsung's S3C24XX family device tree source + * + * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "skeleton.dtsi" + +/ { + compatible = "samsung,s3c24xx"; + interrupt-parent = <&intc>; + + aliases { + pinctrl0 = &pinctrl_0; + }; + + intc:interrupt-controller@4a000000 { + compatible = "samsung,s3c2410-irq"; + reg = <0x4a000000 0x100>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + pinctrl_0: pinctrl@56000000 { + reg = <0x56000000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,s3c2410-wakeup-eint"; + interrupts = <0 0 0 3>, + <0 0 1 3>, + <0 0 2 3>, + <0 0 3 3>, + <0 0 4 4>, + <0 0 5 4>; + }; + }; + + timer@51000000 { + compatible = "samsung,s3c2410-pwm"; + reg = <0x51000000 0x1000>; + interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>; + #pwm-cells = <4>; + }; + + serial@50000000 { + compatible = "samsung,s3c2410-uart"; + reg = <0x50000000 0x4000>; + interrupts = <1 28 0 4>, <1 28 1 4>; + status = "disabled"; + }; + + serial@50004000 { + compatible = "samsung,s3c2410-uart"; + reg = <0x50004000 0x4000>; + interrupts = <1 23 3 4>, <1 23 4 4>; + status = "disabled"; + }; + + serial@50008000 { + compatible = "samsung,s3c2410-uart"; + reg = <0x50008000 0x4000>; + interrupts = <1 15 6 4>, <1 15 7 4>; + status = "disabled"; + }; + + watchdog@53000000 { + compatible = "samsung,s3c2410-wdt"; + reg = <0x53000000 0x100>; + interrupts = <0 0 9 3>; + status = "disabled"; + }; + + rtc@57000000 { + compatible = "samsung,s3c2410-rtc"; + reg = <0x57000000 0x100>; + interrupts = <0 0 30 3>, <0 0 8 3>; + status = "disabled"; + }; + + i2c@54000000 { + compatible = "samsung,s3c2410-i2c"; + reg = <0x54000000 0x100>; + interrupts = <0 0 27 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 2e643ea51cce..a1d5e25a6698 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -8,7 +8,11 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/dma/at91.h> +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Atmel SAMA5D3 family SoC"; @@ -35,8 +39,12 @@ ssc1 = &ssc1; }; cpus { + #address-cells = <1>; + #size-cells = <0>; cpu@0 { + device_type = "cpu"; compatible = "arm,cortex-a5"; + reg = <0x0>; }; }; @@ -59,8 +67,8 @@ mmc0: mmc@f0000000 { compatible = "atmel,hsmci"; reg = <0xf0000000 0x600>; - interrupts = <21 4 0>; - dmas = <&dma0 2 0>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; @@ -72,14 +80,12 @@ spi0: spi@f0004000 { #address-cells = <1>; #size-cells = <0>; - compatible = "atmel,at91sam9x5-spi"; + compatible = "atmel,at91rm9200-spi"; reg = <0xf0004000 0x100>; - interrupts = <24 4 3>; - cs-gpios = <&pioD 13 0 - &pioD 14 0 /* conflicts with SCK0 and CANRX0 */ - &pioD 15 0 /* conflicts with CTS0 and CANTX0 */ - &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */ - >; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; status = "disabled"; @@ -88,7 +94,7 @@ ssc0: ssc@f0008000 { compatible = "atmel,at91sam9g45-ssc"; reg = <0xf0008000 0x4000>; - interrupts = <38 4 4>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; @@ -97,7 +103,7 @@ can0: can@f000c000 { compatible = "atmel,at91sam9x5-can"; reg = <0xf000c000 0x300>; - interrupts = <40 4 3>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_rx_tx>; status = "disabled"; @@ -106,15 +112,15 @@ tcb0: timer@f0010000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf0010000 0x100>; - interrupts = <26 4 0>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; }; i2c0: i2c@f0014000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf0014000 0x4000>; - interrupts = <18 4 6>; - dmas = <&dma0 2 7>, - <&dma0 2 8>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; @@ -126,9 +132,9 @@ i2c1: i2c@f0018000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf0018000 0x4000>; - interrupts = <19 4 6>; - dmas = <&dma0 2 9>, - <&dma0 2 10>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; @@ -140,7 +146,7 @@ usart0: serial@f001c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf001c000 0x100>; - interrupts = <12 4 5>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; status = "disabled"; @@ -149,16 +155,16 @@ usart1: serial@f0020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf0020000 0x100>; - interrupts = <13 4 5>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; status = "disabled"; }; macb0: ethernet@f0028000 { - compatible = "cnds,pc302-gem", "cdns,gem"; + compatible = "cdns,pc302-gem", "cdns,gem"; reg = <0xf0028000 0x100>; - interrupts = <34 4 3>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; status = "disabled"; @@ -167,15 +173,15 @@ isi: isi@f0034000 { compatible = "atmel,at91sam9g45-isi"; reg = <0xf0034000 0x4000>; - interrupts = <37 4 5>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; status = "disabled"; }; mmc1: mmc@f8000000 { compatible = "atmel,hsmci"; reg = <0xf8000000 0x600>; - interrupts = <22 4 0>; - dmas = <&dma1 2 0>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; @@ -187,8 +193,8 @@ mmc2: mmc@f8004000 { compatible = "atmel,hsmci"; reg = <0xf8004000 0x600>; - interrupts = <23 4 0>; - dmas = <&dma1 2 1>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; dma-names = "rxtx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; @@ -200,14 +206,12 @@ spi1: spi@f8008000 { #address-cells = <1>; #size-cells = <0>; - compatible = "atmel,at91sam9x5-spi"; + compatible = "atmel,at91rm9200-spi"; reg = <0xf8008000 0x100>; - interrupts = <25 4 3>; - cs-gpios = <&pioC 25 0 - &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */ - &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */ - &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */ - >; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; status = "disabled"; @@ -216,7 +220,7 @@ ssc1: ssc@f800c000 { compatible = "atmel,at91sam9g45-ssc"; reg = <0xf800c000 0x4000>; - interrupts = <39 4 4>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; status = "disabled"; @@ -225,7 +229,7 @@ can1: can@f8010000 { compatible = "atmel,at91sam9x5-can"; reg = <0xf8010000 0x300>; - interrupts = <41 4 3>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_rx_tx>; }; @@ -233,13 +237,13 @@ tcb1: timer@f8014000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8014000 0x100>; - interrupts = <27 4 0>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; }; adc0: adc@f8018000 { compatible = "atmel,at91sam9260-adc"; reg = <0xf8018000 0x100>; - interrupts = <29 4 5>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = < &pinctrl_adc0_adtrg @@ -293,7 +297,7 @@ tsadcc: tsadcc@f8018000 { compatible = "atmel,at91sam9x5-tsadcc"; reg = <0xf8018000 0x4000>; - interrupts = <29 4 5>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; atmel,tsadcc_clock = <300000>; atmel,filtering_average = <0x03>; atmel,pendet_debounce = <0x08>; @@ -305,9 +309,9 @@ i2c2: i2c@f801c000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf801c000 0x4000>; - interrupts = <20 4 6>; - dmas = <&dma1 2 11>, - <&dma1 2 12>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; @@ -317,7 +321,7 @@ usart2: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x100>; - interrupts = <14 4 5>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; status = "disabled"; @@ -326,7 +330,7 @@ usart3: serial@f8024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x100>; - interrupts = <15 4 5>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; status = "disabled"; @@ -335,7 +339,7 @@ macb1: ethernet@f802c000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xf802c000 0x100>; - interrupts = <35 4 3>; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb1_rmii>; status = "disabled"; @@ -344,7 +348,7 @@ sha@f8034000 { compatible = "atmel,sam9g46-sha"; reg = <0xf8034000 0x100>; - interrupts = <42 4 0>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; }; aes@f8038000 { @@ -356,20 +360,20 @@ tdes@f803c000 { compatible = "atmel,sam9g46-tdes"; reg = <0xf803c000 0x100>; - interrupts = <44 4 0>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; }; dma0: dma-controller@ffffe600 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffe600 0x200>; - interrupts = <30 4 0>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; }; dma1: dma-controller@ffffe800 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffe800 0x200>; - interrupts = <31 4 0>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; }; @@ -381,7 +385,7 @@ dbgu: serial@ffffee00 { compatible = "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; - interrupts = <2 4 7>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; status = "disabled"; @@ -413,202 +417,202 @@ adc0 { pinctrl_adc0_adtrg: adc0_adtrg { atmel,pins = - <3 19 0x1 0x0>; /* PD19 periph A ADTRG */ + <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */ }; pinctrl_adc0_ad0: adc0_ad0 { atmel,pins = - <3 20 0x1 0x0>; /* PD20 periph A AD0 */ + <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */ }; pinctrl_adc0_ad1: adc0_ad1 { atmel,pins = - <3 21 0x1 0x0>; /* PD21 periph A AD1 */ + <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */ }; pinctrl_adc0_ad2: adc0_ad2 { atmel,pins = - <3 22 0x1 0x0>; /* PD22 periph A AD2 */ + <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */ }; pinctrl_adc0_ad3: adc0_ad3 { atmel,pins = - <3 23 0x1 0x0>; /* PD23 periph A AD3 */ + <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */ }; pinctrl_adc0_ad4: adc0_ad4 { atmel,pins = - <3 24 0x1 0x0>; /* PD24 periph A AD4 */ + <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */ }; pinctrl_adc0_ad5: adc0_ad5 { atmel,pins = - <3 25 0x1 0x0>; /* PD25 periph A AD5 */ + <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */ }; pinctrl_adc0_ad6: adc0_ad6 { atmel,pins = - <3 26 0x1 0x0>; /* PD26 periph A AD6 */ + <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */ }; pinctrl_adc0_ad7: adc0_ad7 { atmel,pins = - <3 27 0x1 0x0>; /* PD27 periph A AD7 */ + <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */ }; pinctrl_adc0_ad8: adc0_ad8 { atmel,pins = - <3 28 0x1 0x0>; /* PD28 periph A AD8 */ + <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */ }; pinctrl_adc0_ad9: adc0_ad9 { atmel,pins = - <3 29 0x1 0x0>; /* PD29 periph A AD9 */ + <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */ }; pinctrl_adc0_ad10: adc0_ad10 { atmel,pins = - <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */ + <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */ }; pinctrl_adc0_ad11: adc0_ad11 { atmel,pins = - <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */ + <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */ }; }; can0 { pinctrl_can0_rx_tx: can0_rx_tx { atmel,pins = - <3 14 0x3 0x0 /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ - 3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ + <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ + AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ }; }; can1 { pinctrl_can1_rx_tx: can1_rx_tx { atmel,pins = - <1 14 0x2 0x0 /* PB14 periph B RX, conflicts with GCRS */ - 1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */ + <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */ + AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */ }; }; dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <1 30 0x1 0x0 /* PB30 periph A */ - 1 31 0x1 0x1>; /* PB31 periph A with pullup */ + <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */ + AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */ }; }; i2c0 { pinctrl_i2c0: i2c0-0 { atmel,pins = - <0 30 0x1 0x0 /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ - 0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ + AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ }; }; i2c1 { pinctrl_i2c1: i2c1-0 { atmel,pins = - <2 26 0x2 0x0 /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ - 2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ + <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ + AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ }; }; isi { pinctrl_isi: isi-0 { atmel,pins = - <0 16 0x3 0x0 /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ - 0 17 0x3 0x0 /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ - 0 18 0x3 0x0 /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ - 0 19 0x3 0x0 /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ - 0 20 0x3 0x0 /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ - 0 21 0x3 0x0 /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ - 0 22 0x3 0x0 /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ - 0 23 0x3 0x0 /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ - 2 30 0x3 0x0 /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ - 0 31 0x3 0x0 /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ - 0 30 0x3 0x0 /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ - 2 29 0x3 0x0 /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ - 2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ + <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ + AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ + AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ + AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ + AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ + AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ + AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ + AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ + AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ + AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ + AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ + AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ + AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ }; pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { atmel,pins = - <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */ + <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */ }; }; lcd { pinctrl_lcd: lcd-0 { atmel,pins = - <0 24 0x1 0x0 /* PA24 periph A LCDPWM */ - 0 26 0x1 0x0 /* PA26 periph A LCDVSYNC */ - 0 27 0x1 0x0 /* PA27 periph A LCDHSYNC */ - 0 25 0x1 0x0 /* PA25 periph A LCDDISP */ - 0 29 0x1 0x0 /* PA29 periph A LCDDEN */ - 0 28 0x1 0x0 /* PA28 periph A LCDPCK */ - 0 0 0x1 0x0 /* PA0 periph A LCDD0 pin */ - 0 1 0x1 0x0 /* PA1 periph A LCDD1 pin */ - 0 2 0x1 0x0 /* PA2 periph A LCDD2 pin */ - 0 3 0x1 0x0 /* PA3 periph A LCDD3 pin */ - 0 4 0x1 0x0 /* PA4 periph A LCDD4 pin */ - 0 5 0x1 0x0 /* PA5 periph A LCDD5 pin */ - 0 6 0x1 0x0 /* PA6 periph A LCDD6 pin */ - 0 7 0x1 0x0 /* PA7 periph A LCDD7 pin */ - 0 8 0x1 0x0 /* PA8 periph A LCDD8 pin */ - 0 9 0x1 0x0 /* PA9 periph A LCDD9 pin */ - 0 10 0x1 0x0 /* PA10 periph A LCDD10 pin */ - 0 11 0x1 0x0 /* PA11 periph A LCDD11 pin */ - 0 12 0x1 0x0 /* PA12 periph A LCDD12 pin */ - 0 13 0x1 0x0 /* PA13 periph A LCDD13 pin */ - 0 14 0x1 0x0 /* PA14 periph A LCDD14 pin */ - 0 15 0x1 0x0 /* PA15 periph A LCDD15 pin */ - 2 14 0x3 0x0 /* PC14 periph C LCDD16 pin */ - 2 13 0x3 0x0 /* PC13 periph C LCDD17 pin */ - 2 12 0x3 0x0 /* PC12 periph C LCDD18 pin */ - 2 11 0x3 0x0 /* PC11 periph C LCDD19 pin */ - 2 10 0x3 0x0 /* PC10 periph C LCDD20 pin */ - 2 15 0x3 0x0 /* PC15 periph C LCDD21 pin */ - 4 27 0x3 0x0 /* PE27 periph C LCDD22 pin */ - 4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */ + <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */ + AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */ + AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */ + AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */ + AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */ + AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */ + AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */ + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */ + AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */ + AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */ + AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */ + AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */ + AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */ + AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */ + AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */ + AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */ }; }; macb0 { pinctrl_macb0_data_rgmii: macb0_data_rgmii { atmel,pins = - <1 0 0x1 0x0 /* PB0 periph A GTX0, conflicts with PWMH0 */ - 1 1 0x1 0x0 /* PB1 periph A GTX1, conflicts with PWML0 */ - 1 2 0x1 0x0 /* PB2 periph A GTX2, conflicts with TK1 */ - 1 3 0x1 0x0 /* PB3 periph A GTX3, conflicts with TF1 */ - 1 4 0x1 0x0 /* PB4 periph A GRX0, conflicts with PWMH1 */ - 1 5 0x1 0x0 /* PB5 periph A GRX1, conflicts with PWML1 */ - 1 6 0x1 0x0 /* PB6 periph A GRX2, conflicts with TD1 */ - 1 7 0x1 0x0>; /* PB7 periph A GRX3, conflicts with RK1 */ + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */ }; pinctrl_macb0_data_gmii: macb0_data_gmii { atmel,pins = - <1 19 0x2 0x0 /* PB19 periph B GTX4, conflicts with MCI1_CDA */ - 1 20 0x2 0x0 /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ - 1 21 0x2 0x0 /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ - 1 22 0x2 0x0 /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ - 1 23 0x2 0x0 /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ - 1 24 0x2 0x0 /* PB24 periph B GRX5, conflicts with MCI1_CK */ - 1 25 0x2 0x0 /* PB25 periph B GRX6, conflicts with SCK1 */ - 1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */ + <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */ + AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ + AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ + AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ + AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ + AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */ + AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */ + AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */ }; pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { atmel,pins = - <1 8 0x1 0x0 /* PB8 periph A GTXCK, conflicts with PWMH2 */ - 1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ - 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ - 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ - 1 16 0x1 0x0 /* PB16 periph A GMDC */ - 1 17 0x1 0x0 /* PB17 periph A GMDIO */ - 1 18 0x1 0x0>; /* PB18 periph A G125CK */ + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ + AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */ }; pinctrl_macb0_signal_gmii: macb0_signal_gmii { atmel,pins = - <1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ - 1 10 0x1 0x0 /* PB10 periph A GTXER, conflicts with RF1 */ - 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ - 1 12 0x1 0x0 /* PB12 periph A GRXDV, conflicts with PWMH3 */ - 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ - 1 14 0x1 0x0 /* PB14 periph A GCRS, conflicts with CANRX1 */ - 1 15 0x1 0x0 /* PB15 periph A GCOL, conflicts with CANTX1 */ - 1 16 0x1 0x0 /* PB16 periph A GMDC */ - 1 17 0x1 0x0 /* PB17 periph A GMDIO */ - 1 27 0x2 0x0>; /* PB27 periph B G125CKO */ + <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ + AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */ + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ + AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */ }; }; @@ -616,252 +620,251 @@ macb1 { pinctrl_macb1_rmii: macb1_rmii-0 { atmel,pins = - <2 0 0x1 0x0 /* PC0 periph A ETX0, conflicts with TIOA3 */ - 2 1 0x1 0x0 /* PC1 periph A ETX1, conflicts with TIOB3 */ - 2 2 0x1 0x0 /* PC2 periph A ERX0, conflicts with TCLK3 */ - 2 3 0x1 0x0 /* PC3 periph A ERX1, conflicts with TIOA4 */ - 2 4 0x1 0x0 /* PC4 periph A ETXEN, conflicts with TIOB4 */ - 2 5 0x1 0x0 /* PC5 periph A ECRSDV,conflicts with TCLK4 */ - 2 6 0x1 0x0 /* PC6 periph A ERXER, conflicts with TIOA5 */ - 2 7 0x1 0x0 /* PC7 periph A EREFCK, conflicts with TIOB5 */ - 2 8 0x1 0x0 /* PC8 periph A EMDC, conflicts with TCLK5 */ - 2 9 0x1 0x0>; /* PC9 periph A EMDIO */ + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */ + AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */ }; }; mmc0 { pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { atmel,pins = - <3 9 0x1 0x0 /* PD9 periph A MCI0_CK */ - 3 0 0x1 0x1 /* PD0 periph A MCI0_CDA with pullup */ - 3 1 0x1 0x1>; /* PD1 periph A MCI0_DA0 with pullup */ + <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */ + AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */ + AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */ }; pinctrl_mmc0_dat1_3: mmc0_dat1_3 { atmel,pins = - <3 2 0x1 0x1 /* PD2 periph A MCI0_DA1 with pullup */ - 3 3 0x1 0x1 /* PD3 periph A MCI0_DA2 with pullup */ - 3 4 0x1 0x1>; /* PD4 periph A MCI0_DA3 with pullup */ + <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */ + AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */ + AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */ }; pinctrl_mmc0_dat4_7: mmc0_dat4_7 { atmel,pins = - <3 5 0x1 0x1 /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ - 3 6 0x1 0x1 /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ - 3 7 0x1 0x1 /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ - 3 8 0x1 0x1>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ + <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ + AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ + AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ + AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ }; }; mmc1 { pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { atmel,pins = - <1 24 0x1 0x0 /* PB24 periph A MCI1_CK, conflicts with GRX5 */ - 1 19 0x1 0x1 /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ - 1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ + <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */ + AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ + AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ }; pinctrl_mmc1_dat1_3: mmc1_dat1_3 { atmel,pins = - <1 21 0x1 0x1 /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ - 1 22 0x1 0x1 /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ - 1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ + <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ + AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ + AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ }; }; mmc2 { pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { atmel,pins = - <2 15 0x1 0x0 /* PC15 periph A MCI2_CK, conflicts with PCK2 */ - 2 10 0x1 0x1 /* PC10 periph A MCI2_CDA with pullup */ - 2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */ + <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */ }; pinctrl_mmc2_dat1_3: mmc2_dat1_3 { atmel,pins = - <2 12 0x1 0x0 /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ - 2 13 0x1 0x0 /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ - 2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ + <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ + AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ }; }; nand0 { pinctrl_nand0_ale_cle: nand0_ale_cle-0 { atmel,pins = - <4 21 0x1 0x1 /* PE21 periph A with pullup */ - 4 22 0x1 0x1>; /* PE22 periph A with pullup */ + <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */ + AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */ }; }; - pioA: gpio@fffff200 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x100>; - interrupts = <6 4 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pioB: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x100>; - interrupts = <7 4 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pioC: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x100>; - interrupts = <8 4 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pioD: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x100>; - interrupts = <9 4 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pioE: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x100>; - interrupts = <10 4 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - }; - spi0 { pinctrl_spi0: spi0-0 { atmel,pins = - <3 10 0x1 0x0 /* PD10 periph A SPI0_MISO pin */ - 3 11 0x1 0x0 /* PD11 periph A SPI0_MOSI pin */ - 3 12 0x1 0x0 /* PD12 periph A SPI0_SPCK pin */ - 3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */ + <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */ + AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */ + AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */ }; }; spi1 { pinctrl_spi1: spi1-0 { atmel,pins = - <2 22 0x1 0x0 /* PC22 periph A SPI1_MISO pin */ - 2 23 0x1 0x0 /* PC23 periph A SPI1_MOSI pin */ - 2 24 0x1 0x0 /* PC24 periph A SPI1_SPCK pin */ - 2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */ + <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */ + AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */ + AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */ }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx { atmel,pins = - <2 16 0x1 0x0 /* PC16 periph A TK0 */ - 2 17 0x1 0x0 /* PC17 periph A TF0 */ - 2 18 0x1 0x0>; /* PC18 periph A TD0 */ + <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */ + AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */ + AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */ }; pinctrl_ssc0_rx: ssc0_rx { atmel,pins = - <2 19 0x1 0x0 /* PC19 periph A RK0 */ - 2 20 0x1 0x0 /* PC20 periph A RF0 */ - 2 21 0x1 0x0>; /* PC21 periph A RD0 */ + <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */ + AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */ + AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */ }; }; ssc1 { pinctrl_ssc1_tx: ssc1_tx { atmel,pins = - <1 2 0x2 0x0 /* PB2 periph B TK1, conflicts with GTX2 */ - 1 3 0x2 0x0 /* PB3 periph B TF1, conflicts with GTX3 */ - 1 6 0x2 0x0>; /* PB6 periph B TD1, conflicts with TD1 */ + <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */ + AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */ + AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */ }; pinctrl_ssc1_rx: ssc1_rx { atmel,pins = - <1 7 0x2 0x0 /* PB7 periph B RK1, conflicts with EREFCK */ - 1 10 0x2 0x0 /* PB10 periph B RF1, conflicts with GTXER */ - 1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */ + <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */ + AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */ + AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */ }; }; uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - <2 29 0x1 0x0 /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ - 2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ + <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ + AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ }; }; uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - <0 30 0x2 0x0 /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ - 0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ + <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ + AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ }; }; usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - <3 17 0x1 0x0 /* PD17 periph A */ - 3 18 0x1 0x1>; /* PD18 periph A with pullup */ + <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */ + AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */ }; pinctrl_usart0_rts_cts: usart0_rts_cts-0 { atmel,pins = - <3 15 0x1 0x0 /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ - 3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ + <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ + AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ }; }; usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - <1 28 0x1 0x0 /* PB28 periph A */ - 1 29 0x1 0x1>; /* PB29 periph A with pullup */ + <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */ + AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */ }; pinctrl_usart1_rts_cts: usart1_rts_cts-0 { atmel,pins = - <1 26 0x1 0x0 /* PB26 periph A, conflicts with GRX7 */ - 1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */ + <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */ + AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */ }; }; usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - <4 25 0x2 0x0 /* PE25 periph B, conflicts with A25 */ - 4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */ + <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */ + AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */ }; pinctrl_usart2_rts_cts: usart2_rts_cts-0 { atmel,pins = - <4 23 0x2 0x0 /* PE23 periph B, conflicts with A23 */ - 4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */ + <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */ + AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */ }; }; usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - <4 18 0x2 0x0 /* PE18 periph B, conflicts with A18 */ - 4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */ + <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */ + AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */ }; pinctrl_usart3_rts_cts: usart3_rts_cts-0 { atmel,pins = - <4 16 0x2 0x0 /* PE16 periph B, conflicts with A16 */ - 4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */ + <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */ + AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */ }; }; + + + pioA: gpio@fffff200 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x100>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pioB: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pioC: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pioD: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pioE: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmc: pmc@fffffc00 { @@ -877,7 +880,7 @@ pit: timer@fffffe30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; - interrupts = <3 4 5>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; }; watchdog@fffffe40 { @@ -889,7 +892,7 @@ rtc@fffffeb0 { compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffeb0 0x30>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; }; @@ -899,7 +902,7 @@ compatible = "atmel,at91sam9rl-udc"; reg = <0x00500000 0x100000 0xf8030000 0x4000>; - interrupts = <33 4 2>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; ep0 { @@ -1011,14 +1014,14 @@ usb1: ohci@00600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; - interrupts = <32 4 2>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; usb2: ehci@00700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; - interrupts = <32 4 2>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; @@ -1034,7 +1037,7 @@ 0xffffc000 0x00000070 /* NFC HSMC regs */ 0x00200000 0x00100000 /* NFC SRAM banks */ >; - interrupts = <5 4 6>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; atmel,nand-addr-offset = <21>; atmel,nand-cmd-offset = <22>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts index fa5d216f1db7..027bac7510b6 100644 --- a/arch/arm/boot/dts/sama5d31ek.dts +++ b/arch/arm/boot/dts/sama5d31ek.dts @@ -7,8 +7,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "sama5d3xmb.dtsi" -/include/ "sama5d3xdm.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" / { model = "Atmel SAMA5D31-EK"; @@ -41,7 +41,7 @@ leds { d3 { label = "d3"; - gpios = <&pioE 24 0>; + gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts index c38c9433d7a5..99bd0c8e0471 100644 --- a/arch/arm/boot/dts/sama5d33ek.dts +++ b/arch/arm/boot/dts/sama5d33ek.dts @@ -7,8 +7,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "sama5d3xmb.dtsi" -/include/ "sama5d3xdm.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" / { model = "Atmel SAMA5D33-EK"; diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts index 6bebfcdcb1d1..fb8ee11cf282 100644 --- a/arch/arm/boot/dts/sama5d34ek.dts +++ b/arch/arm/boot/dts/sama5d34ek.dts @@ -7,8 +7,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "sama5d3xmb.dtsi" -/include/ "sama5d3xdm.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" / { model = "Atmel SAMA5D34-EK"; @@ -51,7 +51,7 @@ leds { d3 { label = "d3"; - gpios = <&pioE 24 0>; + gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts index a488fc4e9777..509a53d9cc7b 100644 --- a/arch/arm/boot/dts/sama5d35ek.dts +++ b/arch/arm/boot/dts/sama5d35ek.dts @@ -7,7 +7,7 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "sama5d3xmb.dtsi" +#include "sama5d3xmb.dtsi" / { model = "Atmel SAMA5D35-EK"; @@ -48,7 +48,7 @@ pb_user1 { label = "pb_user1"; - gpios = <&pioE 27 0>; + gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; linux,code = <0x100>; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 1f8ed404626c..1f8050813a54 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -6,7 +6,7 @@ * * Licensed under GPLv2 or later. */ -/include/ "sama5d3.dtsi" +#include "sama5d3.dtsi" / { compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5"; @@ -32,6 +32,10 @@ ahb { apb { + spi0: spi@f0004000 { + cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; + }; + macb0: ethernet@f0028000 { phy-mode = "rgmii"; }; @@ -85,7 +89,7 @@ d2 { label = "d2"; - gpios = <&pioE 25 1>; /* PE25, conflicts with A25, RXD2 */ + gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */ }; }; }; diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi index 4b8830eb2060..1c296d6b2f2a 100644 --- a/arch/arm/boot/dts/sama5d3xdm.dtsi +++ b/arch/arm/boot/dts/sama5d3xdm.dtsi @@ -33,7 +33,7 @@ board { pinctrl_qt1070_irq: qt1070_irq { atmel,pins = - <4 31 0x0 0x5>; /* PE31 GPIO with pull up deglith */ + <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE31 GPIO with pull up deglith */ }; }; }; diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index 661d7ca9c309..8a9e05d8a4b8 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -6,7 +6,7 @@ * * Licensed under GPLv2 or later. */ -/include/ "sama5d3xcm.dtsi" +#include "sama5d3xcm.dtsi" / { compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; @@ -20,7 +20,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioD 17 0>; + cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; }; }; @@ -62,7 +62,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioD 18 0>; + cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; }; }; @@ -87,32 +87,32 @@ board { pinctrl_mmc0_cd: mmc0_cd { atmel,pins = - <3 17 0x0 0x5>; /* PD17 GPIO with pullup deglitch */ + <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD17 GPIO with pullup deglitch */ }; pinctrl_mmc1_cd: mmc1_cd { atmel,pins = - <3 18 0x0 0x5>; /* PD18 GPIO with pullup deglitch */ + <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD18 GPIO with pullup deglitch */ }; pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { atmel,pins = - <3 30 0x2 0x0>; /* PD30 periph B */ + <AT91_PIOD 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD30 periph B */ }; pinctrl_isi_reset: isi_reset-0 { atmel,pins = - <4 24 0x0 0x0>; /* PE24 gpio */ + <AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE24 gpio */ }; pinctrl_isi_power: isi_power-0 { atmel,pins = - <4 29 0x0 0x0>; /* PE29 gpio */ + <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE29 gpio */ }; pinctrl_usba_vbus: usba_vbus { atmel,pins = - <3 29 0x0 0x4>; /* PD29 GPIO with deglitch */ + <AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PD29 GPIO with deglitch */ }; }; }; @@ -127,7 +127,7 @@ }; usb0: gadget@00500000 { - atmel,vbus-gpio = <&pioD 29 0>; + atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; @@ -135,9 +135,9 @@ usb1: ohci@00600000 { num-ports = <3>; - atmel,vbus-gpio = <&pioD 25 0 - &pioD 26 1 - &pioD 27 1 + atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH + &pioD 26 GPIO_ACTIVE_LOW + &pioD 27 GPIO_ACTIVE_LOW >; status = "okay"; }; diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi index 677fc603f8b3..7bf020ecadf5 100644 --- a/arch/arm/boot/dts/sh7372.dtsi +++ b/arch/arm/boot/dts/sh7372.dtsi @@ -14,8 +14,13 @@ compatible = "renesas,sh7372"; cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { compatible = "arm,cortex-a8"; + device_type = "cpu"; + reg = <0x0>; }; }; }; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 5972abb55f9c..b6f759e830ed 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -18,6 +18,19 @@ model = "KZM-A9-GT"; compatible = "renesas,kzm9g-reference", "renesas,sh73a0"; + cpus { + cpu@0 { + cpu0-supply = <&vdd_dvfs>; + operating-points = < + /* kHz uV */ + 1196000 1315000 + 598000 1175000 + 398667 1065000 + >; + voltage-tolerance = <1>; /* 1% */ + }; + }; + chosen { bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200"; }; @@ -59,6 +72,79 @@ }; }; +&i2c0 { + as3711@40 { + compatible = "ams,as3711"; + reg = <0x40>; + + regulators { + vdd_dvfs: sd1 { + regulator-name = "1.315V CPU"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + sd2 { + regulator-name = "1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + sd4 { + regulator-name = "1.215V"; + regulator-min-microvolt = <1215000>; + regulator-max-microvolt = <1235000>; + regulator-always-on; + regulator-boot-on; + }; + ldo2 { + regulator-name = "2.8V CPU"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + ldo3 { + regulator-name = "3.0V CPU"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + ldo4 { + regulator-name = "2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + ldo5 { + regulator-name = "2.8V #2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + ldo7 { + regulator-name = "1.15V CPU"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + ldo8 { + regulator-name = "1.15V CPU #2"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + &mmcif { bus-width = <8>; vmmc-supply = <®_1p8v>; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index ec40bf78289e..b97750256003 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -119,7 +119,7 @@ 0 32 0x4>; }; - i2c0: i2c@0xe6820000 { + i2c0: i2c@e6820000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,rmobile-iic"; @@ -131,7 +131,7 @@ 0 170 0x4>; }; - i2c1: i2c@0xe6822000 { + i2c1: i2c@e6822000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,rmobile-iic"; @@ -143,7 +143,7 @@ 0 54 0x4>; }; - i2c2: i2c@0xe6824000 { + i2c2: i2c@e6824000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,rmobile-iic"; @@ -155,7 +155,7 @@ 0 174 0x4>; }; - i2c3: i2c@0xe6826000 { + i2c3: i2c@e6826000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,rmobile-iic"; @@ -167,7 +167,7 @@ 0 186 0x4>; }; - i2c4: i2c@0xe6828000 { + i2c4: i2c@e6828000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,rmobile-iic"; @@ -179,7 +179,7 @@ 0 190 0x4>; }; - mmcif: mmcif@0x10010000 { + mmcif: mmcif@e6bd0000 { compatible = "renesas,sh-mmcif"; reg = <0xe6bd0000 0x100>; interrupt-parent = <&gic>; @@ -189,7 +189,7 @@ status = "disabled"; }; - sdhi0: sdhi@0xee100000 { + sdhi0: sdhi@ee100000 { compatible = "renesas,r8a7740-sdhi"; reg = <0xee100000 0x100>; interrupt-parent = <&gic>; @@ -201,7 +201,7 @@ }; /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ - sdhi1: sdhi@0xee120000 { + sdhi1: sdhi@ee120000 { compatible = "renesas,r8a7740-sdhi"; reg = <0xee120000 0x100>; interrupt-parent = <&gic>; @@ -212,7 +212,7 @@ status = "disabled"; }; - sdhi2: sdhi@0xee140000 { + sdhi2: sdhi@ee140000 { compatible = "renesas,r8a7740-sdhi"; reg = <0xee140000 0x100>; interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index db5db24fd544..49824be66845 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "dbx5x0.dtsi" +#include "dbx5x0.dtsi" / { model = "Calao Systems Snowball platform with device tree"; @@ -22,12 +22,13 @@ en_3v3_reg: en_3v3 { compatible = "regulator-fixed"; - regulator-name = "en-3v3-fixed-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio0 26 0x4>; // 26 - startup-delay-us = <5000>; - enable-active-high; + regulator-name = "en-3v3-fixed-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* AB8500 GPIOs start from 1 - offset 25 is GPIO26. */ + gpio = <&ab8500_gpio 25 0x4>; + startup-delay-us = <5000>; + enable-active-high; }; gpio_keys { @@ -82,7 +83,7 @@ }; }; - soc-u9500 { + soc { sound { compatible = "stericsson,snd-soc-mop500"; @@ -99,40 +100,13 @@ status = "okay"; }; - prcmu@80157000 { - thermal@801573c0 { - num-trips = <4>; - - trip0-temp = <70000>; - trip0-type = "active"; - trip0-cdev-num = <1>; - trip0-cdev-name0 = "thermal-cpufreq-0"; - - trip1-temp = <75000>; - trip1-type = "active"; - trip1-cdev-num = <1>; - trip1-cdev-name0 = "thermal-cpufreq-0"; - - trip2-temp = <80000>; - trip2-type = "active"; - trip2-cdev-num = <1>; - trip2-cdev-name0 = "thermal-cpufreq-0"; - - trip3-temp = <85000>; - trip3-type = "critical"; - trip3-cdev-num = <0>; - - status = "okay"; - }; - }; - external-bus@50000000 { status = "okay"; ethernet@0 { compatible = "smsc,lan9115"; reg = <0 0x10000>; - interrupts = <12 0x1>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; interrupt-parent = <&gpio4>; vdd33a-supply = <&en_3v3_reg>; vddvario-supply = <&db8500_vape_reg>; @@ -146,13 +120,21 @@ }; }; + vmmci: regulator-gpio { + gpios = <&gpio6 25 0x4>; + enable-gpio = <&gpio7 4 0x4>; + + status = "okay"; + }; + // External Micro SD slot sdi0_per1@80126000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; + max-frequency = <100000000>; bus-width = <4>; mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux3_reg>; + vqmmc-supply = <&vmmci>; cd-gpios = <&gpio6 26 0x4>; // 218 cd-inverted; @@ -163,7 +145,7 @@ // On-board eMMC sdi4_per2@80114000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; + max-frequency = <100000000>; bus-width = <8>; mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux2_reg>; @@ -197,15 +179,15 @@ }; i2c@80128000 { - lp5521@0x33 { + lp5521@33 { // compatible = "lp5521"; reg = <0x33>; }; - lp5521@0x34 { + lp5521@34 { // compatible = "lp5521"; reg = <0x34>; }; - bh1780@0x29 { + bh1780@29 { // compatible = "rohm,bh1780gli"; reg = <0x33>; }; @@ -298,6 +280,31 @@ }; }; + thermal@801573c0 { + num-trips = <4>; + + trip0-temp = <70000>; + trip0-type = "active"; + trip0-cdev-num = <1>; + trip0-cdev-name0 = "thermal-cpufreq-0"; + + trip1-temp = <75000>; + trip1-type = "active"; + trip1-cdev-num = <1>; + trip1-cdev-name0 = "thermal-cpufreq-0"; + + trip2-temp = <80000>; + trip2-type = "active"; + trip2-cdev-num = <1>; + trip2-cdev-name0 = "thermal-cpufreq-0"; + + trip3-temp = <85000>; + trip3-type = "critical"; + trip3-cdev-num = <0>; + + status = "okay"; + }; + ab8500 { ab8500-gpio { compatible = "stericsson,ab8500-gpio"; @@ -316,7 +323,7 @@ regulator-name = "V-MMC-SD"; }; - ab8500_ldo_initcore_reg: ab8500_ldo_initcore { + ab8500_ldo_intcore_reg: ab8500_ldo_intcore { regulator-name = "V-INTCORE"; }; @@ -336,7 +343,7 @@ regulator-name = "V-AMIC1"; }; - ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { regulator-name = "V-AMIC2"; }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 16a6e13e08b4..bee62a2cf6d6 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -23,6 +23,7 @@ aliases { ethernet0 = &gmac0; + ethernet1 = &gmac1; serial0 = &uart0; serial1 = &uart1; timer0 = &timer0; @@ -94,6 +95,12 @@ compatible = "fixed-clock"; }; + f2s_periph_ref_clk: f2s_periph_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <10000000>; + }; + main_pll: main_pll { #address-cells = <1>; #size-cells = <0>; @@ -235,16 +242,222 @@ reg = <0xD4>; }; }; + + mpu_periph_clk: mpu_periph_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mpuclk>; + fixed-divider = <4>; + }; + + mpu_l2_ram_clk: mpu_l2_ram_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mpuclk>; + fixed-divider = <2>; + }; + + l4_main_clk: l4_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + clk-gate = <0x60 0>; + }; + + l3_main_clk: l3_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + }; + + l3_mp_clk: l3_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 0 2>; + clk-gate = <0x60 1>; + }; + + l3_sp_clk: l3_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 2 2>; + }; + + l4_mp_clk: l4_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 4 3>; + clk-gate = <0x60 2>; + }; + + l4_sp_clk: l4_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 7 3>; + clk-gate = <0x60 3>; + }; + + dbg_at_clk: dbg_at_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 0 2>; + clk-gate = <0x60 4>; + }; + + dbg_clk: dbg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 2 2>; + clk-gate = <0x60 5>; + }; + + dbg_trace_clk: dbg_trace_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x6C 0 3>; + clk-gate = <0x60 6>; + }; + + dbg_timer_clk: dbg_timer_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + clk-gate = <0x60 7>; + }; + + cfg_clk: cfg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_s2f_usr0_clk>; + clk-gate = <0x60 8>; + }; + + s2f_user0_clk: s2f_user0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_s2f_usr0_clk>; + clk-gate = <0x60 9>; + }; + + emac_0_clk: emac_0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac0_clk>; + clk-gate = <0xa0 0>; + }; + + emac_1_clk: emac_1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac1_clk>; + clk-gate = <0xa0 1>; + }; + + usb_mp_clk: usb_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 2>; + div-reg = <0xa4 0 3>; + }; + + spi_m_clk: spi_m_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 3>; + div-reg = <0xa4 3 3>; + }; + + can0_clk: can0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 4>; + div-reg = <0xa4 6 3>; + }; + + can1_clk: can1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 5>; + div-reg = <0xa4 9 3>; + }; + + gpio_db_clk: gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 6>; + div-reg = <0xa8 0 24>; + }; + + s2f_user1_clk: s2f_user1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&s2f_usr1_clk>; + clk-gate = <0xa0 7>; + }; + + sdmmc_clk: sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 8>; + }; + + nand_x_clk: nand_x_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 9>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 10>; + fixed-divider = <4>; + }; + + qspi_clk: qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; + clk-gate = <0xa0 11>; + }; }; }; - gmac0: stmmac@ff700000 { + gmac0: ethernet@ff700000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; reg = <0xff700000 0x2000>; interrupts = <0 115 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - phy-mode = "gmii"; + clocks = <&emac0_clk>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gmac1: ethernet@ff702000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + reg = <0xff702000 0x2000>; + interrupts = <0 120 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac1_clk>; + clock-names = "stmmaceth"; + status = "disabled"; }; L2: l2-cache@fffef000 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts index 2495958f1016..973999d2c697 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts @@ -32,6 +32,13 @@ reg = <0x0 0x40000000>; /* 1GB */ }; + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; + soc { clkmgr@ffd04000 { clocks { @@ -41,6 +48,12 @@ }; }; + ethernet@ff702000 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + status = "okay"; + }; + timer0@ffc08000 { clock-frequency = <100000000>; }; diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index 0bf035d607f0..d1ec0cab2dee 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -41,6 +41,11 @@ }; }; + ethernet@ff700000 { + phy-mode = "gmii"; + status = "okay"; + }; + timer0@ffc08000 { clock-frequency = <7000000>; }; diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi index 45597fd91050..4382547df58a 100644 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ b/arch/arm/boot/dts/spear13xx.dtsi @@ -22,12 +22,14 @@ cpu@0 { compatible = "arm,cortex-a9"; + device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; }; cpu@1 { compatible = "arm,cortex-a9"; + device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; }; diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi index c2a852d43c48..f0e3fcf8e323 100644 --- a/arch/arm/boot/dts/spear3xx.dtsi +++ b/arch/arm/boot/dts/spear3xx.dtsi @@ -17,8 +17,12 @@ interrupt-parent = <&vic>; cpus { - cpu@0 { - compatible = "arm,arm926ejs"; + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; }; }; diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi index 19f99dc4115e..9f60a7b6a42b 100644 --- a/arch/arm/boot/dts/spear600.dtsi +++ b/arch/arm/boot/dts/spear600.dtsi @@ -15,8 +15,12 @@ compatible = "st,spear600"; cpus { - cpu@0 { - compatible = "arm,arm926ejs"; + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; }; }; diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st-pincfg.h new file mode 100644 index 000000000000..8c45d85ac13e --- /dev/null +++ b/arch/arm/boot/dts/st-pincfg.h @@ -0,0 +1,71 @@ +#ifndef _ST_PINCFG_H_ +#define _ST_PINCFG_H_ + +/* Alternate functions */ +#define ALT1 1 +#define ALT2 2 +#define ALT3 3 +#define ALT4 4 +#define ALT5 5 +#define ALT6 6 +#define ALT7 7 + +/* Output enable */ +#define OE (1 << 27) +/* Pull Up */ +#define PU (1 << 26) +/* Open Drain */ +#define OD (1 << 26) +#define RT (1 << 23) +#define INVERTCLK (1 << 22) +#define CLKNOTDATA (1 << 21) +#define DOUBLE_EDGE (1 << 20) +#define CLK_A (0 << 18) +#define CLK_B (1 << 18) +#define CLK_C (2 << 18) +#define CLK_D (3 << 18) + +/* User-frendly defines for Pin Direction */ + /* oe = 0, pu = 0, od = 0 */ +#define IN (0) + /* oe = 0, pu = 1, od = 0 */ +#define IN_PU (PU) + /* oe = 1, pu = 0, od = 0 */ +#define OUT (OE) + /* oe = 1, pu = 0, od = 1 */ +#define BIDIR (OE | OD) + /* oe = 1, pu = 1, od = 1 */ +#define BIDIR_PU (OE | PU | OD) + +/* RETIME_TYPE */ +/* + * B Mode + * Bypass retime with optional delay parameter + */ +#define BYPASS (0) +/* + * R0, R1, R0D, R1D modes + * single-edge data non inverted clock, retime data with clk + */ +#define SE_NICLK_IO (RT) +/* + * RIV0, RIV1, RIV0D, RIV1D modes + * single-edge data inverted clock, retime data with clk + */ +#define SE_ICLK_IO (RT | INVERTCLK) +/* + * R0E, R1E, R0ED, R1ED modes + * double-edge data, retime data with clk + */ +#define DE_IO (RT | DOUBLE_EDGE) +/* + * CIV0, CIV1 modes with inverted clock + * Retiming the clk pins will park clock & reduce the noise within the core. + */ +#define ICLK (RT | CLKNOTDATA | INVERTCLK) +/* + * CLK0, CLK1 modes with non-inverted clock + * Retiming the clk pins will park clock & reduce the noise within the core. + */ +#define NICLK (RT | CLKNOTDATA) +#endif /* _ST_PINCFG_H_ */ diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts index b28fbf3408e3..16c3888b7b15 100644 --- a/arch/arm/boot/dts/ste-nomadik-s8815.dts +++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts @@ -14,17 +14,92 @@ bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; }; + /* This is where the interrupt is routed on the S8815 board */ + external-bus@34000000 { + ethernet@300 { + interrupt-parent = <&gpio3>; + interrupts = <8 0x1>; + }; + }; + + src@101e0000 { + /* These chrystal drivers are not used on this board */ + disable-sxtalo; + disable-mxtalo; + }; + + pinctrl { + /* Hog CD pins */ + pinctrl-names = "default"; + pinctrl-0 = <&cd_default_mode>; + + mmcsd-cd { + cd_default_mode: cd_default { + cd_default_cfg1 { + /* CD input GPIO */ + ste,pins = "GPIO111_H21"; + ste,input = <0>; + }; + cd_default_cfg2 { + /* CD GPIO biasing */ + ste,pins = "GPIO112_J21"; + ste,output = <0>; + }; + }; + }; + user-led { + user_led_default_mode: user_led_default { + user_led_default_cfg { + ste,pins = "GPIO2_C5"; + ste,output = <1>; + }; + }; + }; + user-button { + user_button_default_mode: user_button_default { + user_button_default_cfg { + ste,pins = "GPIO3_A4"; + ste,input = <0>; + }; + }; + }; + }; + /* Custom board node with GPIO pins to active etc */ usb-s8815 { /* The S8815 is using this very GPIO pin for the SMSC91x IRQs */ ethernet-gpio { - gpios = <&gpio3 19 0x1>; - interrupts = <19 0x1>; - interrupt-parent = <&gpio3>; + gpios = <&gpio3 8 0x1>; }; /* This will bias the MMC/SD card detect line */ mmcsd-gpio { gpios = <&gpio3 16 0x1>; }; }; + + /* The user LED on the board is set up to be used for heartbeat */ + leds { + compatible = "gpio-leds"; + user-led { + label = "user_led"; + gpios = <&gpio0 2 0x1>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_default_mode>; + }; + }; + + /* User key mapped in as "escape" */ + gpio-keys { + compatible = "gpio-keys"; + user-button { + label = "user_button"; + gpios = <&gpio0 3 0x1>; + linux,code = <1>; /* KEY_ESC */ + gpio-key,wakeup; + pinctrl-names = "default"; + pinctrl-0 = <&user_button_default_mode>; + }; + }; }; diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index 4a4aab395141..a3acfa7b3dc9 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -21,18 +21,23 @@ cache-level = <2>; }; - mtu0 { + mtu0: mtu@101e2000 { /* Nomadik system timer */ + compatible = "st,nomadik-mtu"; reg = <0x101e2000 0x1000>; interrupt-parent = <&vica>; interrupts = <4>; + clocks = <&timclk>, <&pclk>; + clock-names = "timclk", "apb_pclk"; }; - mtu1 { + mtu1: mtu@101e3000 { /* Secondary timer */ reg = <0x101e3000 0x1000>; interrupt-parent = <&vica>; interrupts = <5>; + clocks = <&timclk>, <&pclk>; + clock-names = "timclk", "apb_pclk"; }; gpio0: gpio@101e4000 { @@ -45,6 +50,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <0>; + clocks = <&pclk>; }; gpio1: gpio@101e5000 { @@ -57,6 +63,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <1>; + clocks = <&pclk>; }; gpio2: gpio@101e6000 { @@ -69,6 +76,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <2>; + clocks = <&pclk>; }; gpio3: gpio@101e7000 { @@ -81,10 +89,544 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <3>; + clocks = <&pclk>; }; pinctrl { - compatible = "stericsson,nmk-pinctrl-stn8815"; + compatible = "stericsson,stn8815-pinctrl"; + /* Pin configurations */ + uart0 { + uart0_default_mux: uart0_mux { + u0_default_mux { + ste,function = "u0"; + ste,pins = "u0_a_1"; + }; + }; + }; + uart1 { + uart1_default_mux: uart1_mux { + u1_default_mux { + ste,function = "u1"; + ste,pins = "u1_a_1"; + }; + }; + }; + mmcsd { + mmcsd_default_mux: mmcsd_mux { + mmcsd_default_mux { + ste,function = "mmcsd"; + ste,pins = "mmcsd_a_1"; + }; + }; + mmcsd_default_mode: mmcsd_default { + mmcsd_default_cfg1 { + /* MCCLK */ + ste,pins = "GPIO8_B10"; + ste,output = <0>; + }; + mmcsd_default_cfg2 { + /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */ + ste,pins = "GPIO10_C11", "GPIO15_A12", + "GPIO16_C13"; + ste,output = <1>; + }; + mmcsd_default_cfg3 { + /* MCCMD, MCDAT3-0, MCMSFBCLK */ + ste,pins = "GPIO9_A10", "GPIO11_B11", + "GPIO12_A11", "GPIO13_C12", + "GPIO14_B12", "GPIO24_C15"; + ste,input = <1>; + }; + }; + }; + i2c0 { + i2c0_default_mode: i2c0_default { + i2c0_default_cfg { + ste,pins = "GPIO62_D3", "GPIO63_D2"; + ste,input = <1>; + }; + }; + }; + i2c1 { + i2c1_default_mode: i2c1_default { + i2c1_default_cfg { + ste,pins = "GPIO53_L4", "GPIO54_L3"; + ste,input = <1>; + }; + }; + }; + i2c2 { + i2c2_default_mode: i2c2_default { + i2c2_default_cfg { + ste,pins = "GPIO73_C21", "GPIO74_C20"; + ste,input = <1>; + }; + }; + }; + }; + + src: src@101e0000 { + compatible = "stericsson,nomadik-src"; + reg = <0x101e0000 0x1000>; + disable-sxtalo; + disable-mxtalo; + + /* + * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz + * that is parent of TIMCLK, PLL1 and PLL2 + */ + mxtal: mxtal@19.2M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + /* + * The 2.4 MHz TIMCLK reference clock is active at + * boot time, this is actually the MXTALCLK @19.2 MHz + * divided by 8. This clock is used by the timers and + * watchdog. See page 105 ff. + */ + timclk: timclk@2.4M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <8>; + clock-mult = <1>; + clocks = <&mxtal>; + }; + + /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */ + pll1: pll1@0 { + #clock-cells = <0>; + compatible = "st,nomadik-pll-clock"; + pll-id = <1>; + clocks = <&mxtal>; + }; + + /* HCLK divides the PLL1 with 1,2,3 or 4 */ + hclk: hclk@0 { + #clock-cells = <0>; + compatible = "st,nomadik-hclk-clock"; + clocks = <&pll1>; + }; + /* The PCLK domain uses HCLK right off */ + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&hclk>; + }; + + /* PLL2 is usually 864 MHz and divided into a few fixed rates */ + pll2: pll2@0 { + #clock-cells = <0>; + compatible = "st,nomadik-pll-clock"; + pll-id = <2>; + clocks = <&mxtal>; + }; + clk216: clk216@216M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <4>; + clock-mult = <1>; + clocks = <&pll2>; + }; + clk108: clk108@108M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&clk216>; + }; + clk72: clk72@72M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + /* The data sheet does not say how this is derived */ + clock-div = <12>; + clock-mult = <1>; + clocks = <&pll2>; + }; + clk48: clk48@48M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + /* The data sheet does not say how this is derived */ + clock-div = <18>; + clock-mult = <1>; + clocks = <&pll2>; + }; + clk27: clk27@27M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <4>; + clock-mult = <1>; + clocks = <&clk108>; + }; + + /* This apparently exists as well */ + ulpiclk: ulpiclk@60M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <60000000>; + }; + + /* + * IP AMBA bus clocks, driving the bus side of the + * peripheral clocking, clock gates. + */ + + hclkdma0: hclkdma0@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <0>; + clocks = <&hclk>; + }; + hclksmc: hclksmc@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <1>; + clocks = <&hclk>; + }; + hclksdram: hclksdram@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <2>; + clocks = <&hclk>; + }; + hclkdma1: hclkdma1@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <3>; + clocks = <&hclk>; + }; + hclkclcd: hclkclcd@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <4>; + clocks = <&hclk>; + }; + pclkirda: pclkirda@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <5>; + clocks = <&pclk>; + }; + pclkssp: pclkssp@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <6>; + clocks = <&pclk>; + }; + pclkuart0: pclkuart0@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <7>; + clocks = <&pclk>; + }; + pclksdi: pclksdi@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <8>; + clocks = <&pclk>; + }; + pclki2c0: pclki2c0@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <9>; + clocks = <&pclk>; + }; + pclki2c1: pclki2c1@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <10>; + clocks = <&pclk>; + }; + pclkuart1: pclkuart1@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <11>; + clocks = <&pclk>; + }; + pclkmsp0: pclkmsp0@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <12>; + clocks = <&pclk>; + }; + hclkusb: hclkusb@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <13>; + clocks = <&hclk>; + }; + hclkdif: hclkdif@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <14>; + clocks = <&hclk>; + }; + hclksaa: hclksaa@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <15>; + clocks = <&hclk>; + }; + hclksva: hclksva@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <16>; + clocks = <&hclk>; + }; + pclkhsi: pclkhsi@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <17>; + clocks = <&pclk>; + }; + pclkxti: pclkxti@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <18>; + clocks = <&pclk>; + }; + pclkuart2: pclkuart2@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <19>; + clocks = <&pclk>; + }; + pclkmsp1: pclkmsp1@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <20>; + clocks = <&pclk>; + }; + pclkmsp2: pclkmsp2@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <21>; + clocks = <&pclk>; + }; + pclkowm: pclkowm@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <22>; + clocks = <&pclk>; + }; + hclkhpi: hclkhpi@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <23>; + clocks = <&hclk>; + }; + pclkske: pclkske@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <24>; + clocks = <&pclk>; + }; + pclkhsem: pclkhsem@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <25>; + clocks = <&pclk>; + }; + hclk3d: hclk3d@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <26>; + clocks = <&hclk>; + }; + hclkhash: hclkhash@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <27>; + clocks = <&hclk>; + }; + hclkcryp: hclkcryp@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <28>; + clocks = <&hclk>; + }; + pclkmshc: pclkmshc@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <29>; + clocks = <&pclk>; + }; + hclkusbm: hclkusbm@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <30>; + clocks = <&hclk>; + }; + hclkrng: hclkrng@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <31>; + clocks = <&hclk>; + }; + + /* IP kernel clocks */ + clcdclk: clcdclk@0 { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <36>; + clocks = <&clk72 &clk48>; + }; + irdaclk: irdaclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <37>; + clocks = <&clk48>; + }; + sspiclk: sspiclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <38>; + clocks = <&clk48>; + }; + uart0clk: uart0clk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <39>; + clocks = <&clk48>; + }; + sdiclk: sdiclk@48M { + /* Also called MCCLK in some documents */ + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <40>; + clocks = <&clk48>; + }; + i2c0clk: i2c0clk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <41>; + clocks = <&clk48>; + }; + i2c1clk: i2c1clk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <42>; + clocks = <&clk48>; + }; + uart1clk: uart1clk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <43>; + clocks = <&clk48>; + }; + mspclk0: mspclk0@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <44>; + clocks = <&clk48>; + }; + usbclk: usbclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <45>; + clocks = <&clk48>; /* 48 MHz not ULPI */ + }; + difclk: difclk@72M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <46>; + clocks = <&clk72>; + }; + ipi2cclk: ipi2cclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <47>; + clocks = <&clk48>; /* Guess */ + }; + ipbmcclk: ipbmcclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <48>; + clocks = <&clk48>; /* Guess */ + }; + hsiclkrx: hsiclkrx@216M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <49>; + clocks = <&clk216>; + }; + hsiclktx: hsiclktx@108M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <50>; + clocks = <&clk108>; + }; + uart2clk: uart2clk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <51>; + clocks = <&clk48>; + }; + mspclk1: mspclk1@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <52>; + clocks = <&clk48>; + }; + mspclk2: mspclk2@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <53>; + clocks = <&clk48>; + }; + owmclk: owmclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <54>; + clocks = <&clk48>; /* Guess */ + }; + skeclk: skeclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <56>; + clocks = <&clk48>; /* Guess */ + }; + x3dclk: x3dclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <58>; + clocks = <&clk48>; /* Guess */ + }; + pclkmsp3: pclkmsp3@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <59>; + clocks = <&pclk>; + }; + mspclk3: mspclk3@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <60>; + clocks = <&clk48>; + }; + mshcclk: mshcclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <61>; + clocks = <&clk48>; /* Guess */ + }; + usbmclk: usbmclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <62>; + /* Stated as "48 MHz not ULPI clock" */ + clocks = <&clk48>; + }; + rngcclk: rngcclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <63>; + clocks = <&clk48>; /* Guess */ + }; }; /* A NAND flash of 128 MiB */ @@ -97,6 +639,7 @@ <0x41000000 0x2000>, /* NAND Base ADDR */ <0x40800000 0x2000>; /* NAND Base CMD */ reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; + clocks = <&hclksmc>; status = "okay"; partition@0 { @@ -144,6 +687,8 @@ <&gpio1 30 0>; /* scl */ #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_default_mode>; stw4811@2d { compatible = "st,stw4811"; @@ -158,6 +703,8 @@ <&gpio1 21 0>; /* scl */ #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_default_mode>; camera@2d { compatible = "st,camera"; @@ -180,6 +727,9 @@ <&gpio2 9 0>; /* scl */ #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_default_mode>; + stw4811@2d { compatible = "st,stw4811-usb"; reg = <0x2d>; @@ -211,6 +761,10 @@ reg = <0x101fd000 0x1000>; interrupt-parent = <&vica>; interrupts = <12>; + clocks = <&uart0clk>, <&pclkuart0>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_default_mux>; }; uart1: uart@101fb000 { @@ -218,6 +772,10 @@ reg = <0x101fb000 0x1000>; interrupt-parent = <&vica>; interrupts = <17>; + clocks = <&uart1clk>, <&pclkuart1>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_default_mux>; }; uart2: uart@101f2000 { @@ -225,17 +783,23 @@ reg = <0x101f2000 0x1000>; interrupt-parent = <&vica>; interrupts = <28>; + clocks = <&uart2clk>, <&pclkuart2>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; rng: rng@101b0000 { compatible = "arm,primecell"; reg = <0x101b0000 0x1000>; + clocks = <&rngcclk>, <&hclkrng>; + clock-names = "rng", "apb_pclk"; }; rtc: rtc@101e8000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x101e8000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; interrupt-parent = <&vica>; interrupts = <10>; }; @@ -243,6 +807,8 @@ mmcsd: sdi@101f6000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x101f6000 0x1000>; + clocks = <&sdiclk>, <&pclksdi>; + clock-names = "mclk", "apb_pclk"; interrupt-parent = <&vica>; interrupts = <22>; max-frequency = <48000000>; @@ -251,6 +817,8 @@ mmc-cap-sd-highspeed; cd-gpios = <&gpio3 15 0x1>; cd-inverted; + pinctrl-names = "default"; + pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; }; }; }; diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts new file mode 100644 index 000000000000..8a1032c1ffc9 --- /dev/null +++ b/arch/arm/boot/dts/ste-u300.dts @@ -0,0 +1,473 @@ +/* + * Device Tree for the ST-Ericsson U300 Machine and SoC + */ + +/dts-v1/; +/include/ "skeleton.dtsi" + +/ { + model = "ST-Ericsson U300"; + compatible = "stericsson,u300"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk"; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + memory { + reg = <0x48000000 0x03c00000>; + }; + + s365 { + compatible = "stericsson,s365"; + vana15-supply = <&ab3100_ldo_d_reg>; + syscon = <&syscon>; + }; + + syscon: syscon@c0011000 { + compatible = "stericsson,u300-syscon", "syscon"; + reg = <0xc0011000 0x1000>; + clk32: app_32_clk@32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + pll13: pll13@13M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + /* Slow bridge clocks under PLL13 */ + slow_clk: slow_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <0>; + clocks = <&pll13>; + }; + uart0_clk: uart0_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <1>; + clocks = <&slow_clk>; + }; + gpio_clk: gpio_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <4>; + clocks = <&slow_clk>; + }; + rtc_clk: rtc_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <6>; + clocks = <&slow_clk>; + }; + apptimer_clk: app_tmr_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <7>; + clocks = <&slow_clk>; + }; + acc_tmr_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <8>; + clocks = <&slow_clk>; + }; + pll208: pll208@208M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <208000000>; + }; + app208: app_208_clk@208M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&pll208>; + }; + cpu_clk@208M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <3>; + clocks = <&app208>; + }; + app104: app_104_clk@104M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&pll208>; + }; + semi_clk@104M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <9>; + clocks = <&app104>; + }; + app52: app_52_clk@52M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <4>; + clock-mult = <1>; + clocks = <&pll208>; + }; + /* AHB subsystem clocks */ + ahb_clk: ahb_subsys_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <10>; + clocks = <&app52>; + }; + intcon_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <12>; + clocks = <&ahb_clk>; + }; + emif_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <5>; + clocks = <&ahb_clk>; + }; + dmac_clk: dmac_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <4>; + clocks = <&app52>; + }; + fsmc_clk: fsmc_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <6>; + clocks = <&app52>; + }; + xgam_clk: xgam_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <8>; + clocks = <&app52>; + }; + app26: app_26_clk@26M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&app52>; + }; + /* Fast bridge clocks */ + fast_clk: fast_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <0>; + clocks = <&app26>; + }; + i2c0_clk: i2c0_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <1>; + clocks = <&fast_clk>; + }; + i2c1_clk: i2c1_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <2>; + clocks = <&fast_clk>; + }; + mmc_pclk: mmc_p_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <5>; + clocks = <&fast_clk>; + }; + mmc_mclk: mmc_mclk { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-mclk"; + clocks = <&mmc_pclk>; + }; + spi_clk: spi_p_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <6>; + clocks = <&fast_clk>; + }; + }; + + timer: timer@c0014000 { + compatible = "stericsson,u300-apptimer"; + reg = <0xc0014000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <24 25 26 27>; + clocks = <&apptimer_clk>; + }; + + gpio: gpio@c0016000 { + compatible = "stericsson,gpio-coh901"; + reg = <0xc0016000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <0 1 2 18 21 22 23>; + clocks = <&gpio_clk>; + interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pinctrl: pinctrl@c0011000 { + compatible = "stericsson,pinctrl-u300"; + reg = <0xc0011000 0x1000>; + }; + + watchdog: watchdog@c0012000 { + compatible = "stericsson,coh901327"; + reg = <0xc0012000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <3>; + clocks = <&clk32>; + }; + + rtc: rtc@c0017000 { + compatible = "stericsson,coh901331"; + reg = <0xc0017000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <10>; + clocks = <&rtc_clk>; + }; + + dmac: dma-controller@c00020000 { + compatible = "stericsson,coh901318"; + reg = <0xc0020000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <2>; + #dma-cells = <1>; + dma-channels = <40>; + clocks = <&dmac_clk>; + }; + + /* A NAND flash of 128 MiB */ + fsmc: flash@40000000 { + compatible = "stericsson,fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x9f800000 0x1000>, /* FSMC Register*/ + <0x80000000 0x4000>, /* NAND Base DATA */ + <0x80020000 0x4000>, /* NAND Base ADDR */ + <0x80010000 0x4000>; /* NAND Base CMD */ + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; + nand-skip-bbtscan; + clocks = <&fsmc_clk>; + + partition@0 { + label = "boot records"; + reg = <0x0 0x20000>; + }; + partition@20000 { + label = "free"; + reg = <0x20000 0x7e0000>; + }; + partition@800000 { + label = "platform"; + reg = <0x800000 0xf800000>; + }; + }; + + i2c0: i2c@c0004000 { + compatible = "st,ddci2c"; + reg = <0xc0004000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <8>; + clocks = <&i2c0_clk>; + #address-cells = <1>; + #size-cells = <0>; + ab3100: ab3100@0x48 { + compatible = "stericsson,ab3100"; + reg = <0x48>; + interrupt-parent = <&vica>; + interrupts = <0>; /* EXT0 IRQ */ + ab3100-regulators { + compatible = "stericsson,ab3100-regulators"; + ab3100_ldo_a_reg: ab3100_ldo_a { + regulator-compatible = "ab3100_ldo_a"; + startup-delay-us = <200>; + regulator-always-on; + regulator-boot-on; + }; + ab3100_ldo_c_reg: ab3100_ldo_c { + regulator-compatible = "ab3100_ldo_c"; + startup-delay-us = <200>; + }; + ab3100_ldo_d_reg: ab3100_ldo_d { + regulator-compatible = "ab3100_ldo_d"; + startup-delay-us = <200>; + }; + ab3100_ldo_e_reg: ab3100_ldo_e { + regulator-compatible = "ab3100_ldo_e"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <200>; + regulator-always-on; + regulator-boot-on; + }; + ab3100_ldo_f_reg: ab3100_ldo_f { + regulator-compatible = "ab3100_ldo_f"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + startup-delay-us = <600>; + regulator-always-on; + regulator-boot-on; + }; + ab3100_ldo_g_reg: ab3100_ldo_g { + regulator-compatible = "ab3100_ldo_g"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2850000>; + startup-delay-us = <400>; + }; + ab3100_ldo_h_reg: ab3100_ldo_h { + regulator-compatible = "ab3100_ldo_h"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2750000>; + startup-delay-us = <200>; + }; + ab3100_ldo_k_reg: ab3100_ldo_k { + regulator-compatible = "ab3100_ldo_k"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2750000>; + startup-delay-us = <200>; + }; + ab3100_ext_reg: ab3100_ext { + regulator-compatible = "ab3100_ext"; + }; + ab3100_buck_reg: ab3100_buck { + regulator-compatible = "ab3100_buck"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <1000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + + i2c1: i2c@c0005000 { + compatible = "st,ddci2c"; + reg = <0xc0005000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <9>; + clocks = <&i2c1_clk>; + #address-cells = <1>; + #size-cells = <0>; + fwcam0: fwcam@0x10 { + reg = <0x10>; + }; + fwcam1: fwcam@0x5d { + reg = <0x5d>; + }; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vica: interrupt-controller@a0001000 { + compatible = "arm,versatile-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xa0001000 0x20>; + }; + + vicb: interrupt-controller@a0002000 { + compatible = "arm,versatile-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xa0002000 0x20>; + }; + + uart0: serial@c0013000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xc0013000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <22>; + clocks = <&uart0_clk>, <&uart0_clk>; + clock-names = "apb_pclk", "uart0_clk"; + dmas = <&dmac 17 &dmac 18>; + dma-names = "tx", "rx"; + }; + + uart1: serial@c0007000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xc0007000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <20>; + dmas = <&dmac 38 &dmac 39>; + dma-names = "tx", "rx"; + }; + + mmcsd: mmcsd@c0001000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0xc0001000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <6 7>; + clocks = <&mmc_pclk>, <&mmc_mclk>; + clock-names = "apb_pclk", "mclk"; + max-frequency = <24000000>; + bus-width = <4>; // SD-card slot + mmc-cap-mmc-highspeed; + mmc-cap-sd-highspeed; + cd-gpios = <&gpio 12 0x4>; + cd-inverted; + vmmc-supply = <&ab3100_ldo_g_reg>; + dmas = <&dmac 14>; + dma-names = "rx"; + }; + + spi: ssp@c0006000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xc0006000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <23>; + clocks = <&spi_clk>, <&spi_clk>; + clock-names = "apb_pclk", "spi_clk"; + dmas = <&dmac 27 &dmac 28>; + dma-names = "tx", "rx"; + num-cs = <3>; + #address-cells = <1>; + #size-cells = <0>; + spi-dummy@1 { + compatible = "arm,pl022-dummy"; + reg = <1>; + spi-max-frequency = <20000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih415-b2000.dts b/arch/arm/boot/dts/stih415-b2000.dts new file mode 100644 index 000000000000..d4af53160435 --- /dev/null +++ b/arch/arm/boot/dts/stih415-b2000.dts @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +/dts-v1/; +#include "stih415.dtsi" +#include "stih41x-b2000.dtsi" +/ { + model = "STiH415 B2000 Board"; + compatible = "st,stih415", "st,stih415-b2000"; +}; diff --git a/arch/arm/boot/dts/stih415-b2020.dts b/arch/arm/boot/dts/stih415-b2020.dts new file mode 100644 index 000000000000..442b019e9a3a --- /dev/null +++ b/arch/arm/boot/dts/stih415-b2020.dts @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +/dts-v1/; +#include "stih415.dtsi" +#include "stih41x-b2020.dtsi" +/ { + model = "STiH415 B2020 Board"; + compatible = "st,stih415", "st,stih415-b2020"; +}; diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi new file mode 100644 index 000000000000..174c799df741 --- /dev/null +++ b/arch/arm/boot/dts/stih415-clock.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/ { + clocks { + /* + * Fixed 30MHz oscillator input to SoC + */ + CLK_SYSIN: CLK_SYSIN { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + }; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: arm_periph_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <500000000>; + }; + + /* + * Bootloader initialized system infrastructure clock for + * serial devices. + */ + CLKS_ICN_REG_0: CLKS_ICN_REG_0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi new file mode 100644 index 000000000000..1d322b24d1e4 --- /dev/null +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +#include "st-pincfg.h" +/ { + + aliases { + gpio0 = &PIO0; + gpio1 = &PIO1; + gpio2 = &PIO2; + gpio3 = &PIO3; + gpio4 = &PIO4; + gpio5 = &PIO5; + gpio6 = &PIO6; + gpio7 = &PIO7; + gpio8 = &PIO8; + gpio9 = &PIO9; + gpio10 = &PIO10; + gpio11 = &PIO11; + gpio12 = &PIO12; + gpio13 = &PIO13; + gpio14 = &PIO14; + gpio15 = &PIO15; + gpio16 = &PIO16; + gpio17 = &PIO17; + gpio18 = &PIO18; + gpio19 = &PIO100; + gpio20 = &PIO101; + gpio21 = &PIO102; + gpio22 = &PIO103; + gpio23 = &PIO104; + gpio24 = &PIO105; + gpio25 = &PIO106; + gpio26 = &PIO107; + }; + + soc { + pin-controller-sbc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih415-sbc-pinctrl"; + st,syscfg = <&syscfg_sbc>; + ranges = <0 0xfe610000 0x5000>; + + PIO0: gpio@fe610000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO0"; + }; + PIO1: gpio@fe611000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO1"; + }; + PIO2: gpio@fe612000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO2"; + }; + PIO3: gpio@fe613000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO3"; + }; + PIO4: gpio@fe614000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO4"; + }; + + sbc_serial1 { + pinctrl_sbc_serial1:sbc_serial1 { + st,pins { + tx = <&PIO2 6 ALT3 OUT>; + rx = <&PIO2 7 ALT3 IN>; + }; + }; + }; + }; + + pin-controller-front { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih415-front-pinctrl"; + st,syscfg = <&syscfg_front>; + ranges = <0 0xfee00000 0x8000>; + + PIO5: gpio@fee00000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO5"; + }; + PIO6: gpio@fee01000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO6"; + }; + PIO7: gpio@fee02000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO7"; + }; + PIO8: gpio@fee03000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO8"; + }; + PIO9: gpio@fee04000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO9"; + }; + PIO10: gpio@fee05000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x5000 0x100>; + st,bank-name = "PIO10"; + }; + PIO11: gpio@fee06000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x6000 0x100>; + st,bank-name = "PIO11"; + }; + PIO12: gpio@fee07000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x7000 0x100>; + st,bank-name = "PIO12"; + }; + }; + + pin-controller-rear { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih415-rear-pinctrl"; + st,syscfg = <&syscfg_rear>; + ranges = <0 0xfe820000 0x8000>; + + PIO13: gpio@fe820000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO13"; + }; + PIO14: gpio@fe821000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO14"; + }; + PIO15: gpio@fe822000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO15"; + }; + PIO16: gpio@fe823000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO16"; + }; + PIO17: gpio@fe824000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO17"; + }; + PIO18: gpio@fe825000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x5000 0x100>; + st,bank-name = "PIO18"; + }; + + serial2 { + pinctrl_serial2: serial2-0 { + st,pins { + tx = <&PIO17 4 ALT2 OUT>; + rx = <&PIO17 5 ALT2 IN>; + }; + }; + }; + }; + + pin-controller-left { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih415-left-pinctrl"; + st,syscfg = <&syscfg_left>; + ranges = <0 0xfd6b0000 0x3000>; + + PIO100: gpio@fd6b0000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO100"; + }; + PIO101: gpio@fd6b1000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO101"; + }; + PIO102: gpio@fd6b2000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO102"; + }; + }; + + pin-controller-right { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih415-right-pinctrl"; + st,syscfg = <&syscfg_right>; + ranges = <0 0xfd330000 0x5000>; + + PIO103: gpio@fd330000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO103"; + }; + PIO104: gpio@fd331000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO104"; + }; + PIO105: gpio@fd332000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO105"; + }; + PIO106: gpio@fd333000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO106"; + }; + PIO107: gpio@fd334000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO107"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi new file mode 100644 index 000000000000..74ab8ded4b49 --- /dev/null +++ b/arch/arm/boot/dts/stih415.dtsi @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +#include "stih41x.dtsi" +#include "stih415-clock.dtsi" +#include "stih415-pinctrl.dtsi" +/ { + + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xfffe2000 0x1000>; + arm,data-latency = <3 2 2>; + arm,tag-latency = <1 1 1>; + cache-unified; + cache-level = <2>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + compatible = "simple-bus"; + + syscfg_sbc: sbc-syscfg@fe600000{ + compatible = "st,stih415-sbc-syscfg", "syscon"; + reg = <0xfe600000 0xb4>; + }; + + syscfg_front: front-syscfg@fee10000{ + compatible = "st,stih415-front-syscfg", "syscon"; + reg = <0xfee10000 0x194>; + }; + + syscfg_rear: rear-syscfg@fe830000{ + compatible = "st,stih415-rear-syscfg", "syscon"; + reg = <0xfe830000 0x190>; + }; + + /* MPE syscfgs */ + syscfg_left: left-syscfg@fd690000{ + compatible = "st,stih415-left-syscfg", "syscon"; + reg = <0xfd690000 0x78>; + }; + + syscfg_right: right-syscfg@fd320000{ + compatible = "st,stih415-right-syscfg", "syscon"; + reg = <0xfd320000 0x180>; + }; + + syscfg_system: system-syscfg@fdde0000 { + compatible = "st,stih415-system-syscfg", "syscon"; + reg = <0xfdde0000 0x15c>; + }; + + syscfg_lpm: lpm-syscfg@fe4b5100{ + compatible = "st,stih415-lpm-syscfg", "syscon"; + reg = <0xfe4b5100 0x08>; + }; + + serial2: serial@fed32000 { + compatible = "st,asc"; + status = "disabled"; + reg = <0xfed32000 0x2c>; + interrupts = <0 197 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_serial2>; + clocks = <&CLKS_ICN_REG_0>; + }; + + /* SBC comms block ASCs in SASG1 */ + sbc_serial1: serial@fe531000 { + compatible = "st,asc"; + status = "disabled"; + reg = <0xfe531000 0x2c>; + interrupts = <0 210 0>; + clocks = <&CLK_SYSIN>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_serial1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih416-b2000.dts b/arch/arm/boot/dts/stih416-b2000.dts new file mode 100644 index 000000000000..a5eb6eee10bf --- /dev/null +++ b/arch/arm/boot/dts/stih416-b2000.dts @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +/dts-v1/; +#include "stih416.dtsi" +#include "stih41x-b2000.dtsi" + +/ { + compatible = "st,stih416", "st,stih416-b2000"; + model = "STiH416 B2000"; +}; diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts new file mode 100644 index 000000000000..276f28da573a --- /dev/null +++ b/arch/arm/boot/dts/stih416-b2020.dts @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +/dts-v1/; +#include "stih416.dtsi" +#include "stih41x-b2020.dtsi" +/ { + model = "STiH416 B2020"; + compatible = "st,stih416", "st,stih416-b2020"; + +}; diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi new file mode 100644 index 000000000000..7026bf1158d8 --- /dev/null +++ b/arch/arm/boot/dts/stih416-clock.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2013 STMicroelectronics R&D Limited + * <stlinux-devel@stlinux.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/ { + clocks { + /* + * Fixed 30MHz oscillator inputs to SoC + */ + CLK_SYSIN: CLK_SYSIN { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + clock-output-names = "CLK_SYSIN"; + }; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: arm_periph_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <600000000>; + }; + + /* + * Bootloader initialized system infrastructure clock for + * serial devices. + */ + CLK_S_ICN_REG_0: clockgenA0@4 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "CLK_S_ICN_REG_0"; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi new file mode 100644 index 000000000000..957b21a71b4b --- /dev/null +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -0,0 +1,295 @@ + +/* + * Copyright (C) 2013 STMicroelectronics Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +#include "st-pincfg.h" +/ { + + aliases { + gpio0 = &PIO0; + gpio1 = &PIO1; + gpio2 = &PIO2; + gpio3 = &PIO3; + gpio4 = &PIO4; + gpio5 = &PIO40; + gpio6 = &PIO5; + gpio7 = &PIO6; + gpio8 = &PIO7; + gpio9 = &PIO8; + gpio10 = &PIO9; + gpio11 = &PIO10; + gpio12 = &PIO11; + gpio13 = &PIO12; + gpio14 = &PIO30; + gpio15 = &PIO31; + gpio16 = &PIO13; + gpio17 = &PIO14; + gpio18 = &PIO15; + gpio19 = &PIO16; + gpio20 = &PIO17; + gpio21 = &PIO18; + gpio22 = &PIO100; + gpio23 = &PIO101; + gpio24 = &PIO102; + gpio25 = &PIO103; + gpio26 = &PIO104; + gpio27 = &PIO105; + gpio28 = &PIO106; + gpio29 = &PIO107; + }; + + soc { + pin-controller-sbc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih416-sbc-pinctrl"; + st,syscfg = <&syscfg_sbc>; + ranges = <0 0xfe610000 0x6000>; + + PIO0: gpio@fe610000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO0"; + }; + PIO1: gpio@fe611000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO1"; + }; + PIO2: gpio@fe612000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO2"; + }; + PIO3: gpio@fe613000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO3"; + }; + PIO4: gpio@fe614000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO4"; + }; + PIO40: gpio@fe615000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x5000 0x100>; + st,bank-name = "PIO40"; + st,retime-pin-mask = <0x7f>; + }; + + sbc_serial1 { + pinctrl_sbc_serial1: sbc_serial1 { + st,pins { + tx = <&PIO2 6 ALT3 OUT>; + rx = <&PIO2 7 ALT3 IN>; + }; + }; + }; + }; + + pin-controller-front { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih416-front-pinctrl"; + st,syscfg = <&syscfg_front>; + ranges = <0 0xfee00000 0x10000>; + + PIO5: gpio@fee00000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO5"; + }; + PIO6: gpio@fee01000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO6"; + }; + PIO7: gpio@fee02000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO7"; + }; + PIO8: gpio@fee03000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO8"; + }; + PIO9: gpio@fee04000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO9"; + }; + PIO10: gpio@fee05000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x5000 0x100>; + st,bank-name = "PIO10"; + }; + PIO11: gpio@fee06000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x6000 0x100>; + st,bank-name = "PIO11"; + }; + PIO12: gpio@fee07000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x7000 0x100>; + st,bank-name = "PIO12"; + }; + PIO30: gpio@fee08000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x8000 0x100>; + st,bank-name = "PIO30"; + }; + PIO31: gpio@fee09000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x9000 0x100>; + st,bank-name = "PIO31"; + }; + }; + + pin-controller-rear { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih416-rear-pinctrl"; + st,syscfg = <&syscfg_rear>; + ranges = <0 0xfe820000 0x6000>; + + PIO13: gpio@fe820000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO13"; + }; + PIO14: gpio@fe821000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO14"; + }; + PIO15: gpio@fe822000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO15"; + }; + PIO16: gpio@fe823000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO16"; + }; + PIO17: gpio@fe824000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO17"; + }; + PIO18: gpio@fe825000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x5000 0x100>; + st,bank-name = "PIO18"; + st,retime-pin-mask = <0xf>; + }; + + serial2 { + pinctrl_serial2: serial2-0 { + st,pins { + tx = <&PIO17 4 ALT2 OUT>; + rx = <&PIO17 5 ALT2 IN>; + output-enable = <&PIO11 3 ALT2 OUT>; + }; + }; + }; + }; + + pin-controller-fvdp-fe { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih416-fvdp-fe-pinctrl"; + st,syscfg = <&syscfg_fvdp_fe>; + ranges = <0 0xfd6b0000 0x3000>; + + PIO100: gpio@fd6b0000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO100"; + }; + PIO101: gpio@fd6b1000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO101"; + }; + PIO102: gpio@fd6b2000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO102"; + }; + }; + + pin-controller-fvdp-lite { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih416-fvdp-lite-pinctrl"; + st,syscfg = <&syscfg_fvdp_lite>; + ranges = <0 0xfd330000 0x5000>; + + PIO103: gpio@fd330000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO103"; + }; + PIO104: gpio@fd331000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO104"; + }; + PIO105: gpio@fd332000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO105"; + }; + PIO106: gpio@fd333000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO106"; + }; + + PIO107: gpio@fd334000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO107"; + st,retime-pin-mask = <0xf>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi new file mode 100644 index 000000000000..3cecd9689a49 --- /dev/null +++ b/arch/arm/boot/dts/stih416.dtsi @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2012 STMicroelectronics Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +#include "stih41x.dtsi" +#include "stih416-clock.dtsi" +#include "stih416-pinctrl.dtsi" +/ { + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xfffe2000 0x1000>; + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + cache-unified; + cache-level = <2>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + compatible = "simple-bus"; + + syscfg_sbc:sbc-syscfg@fe600000{ + compatible = "st,stih416-sbc-syscfg", "syscon"; + reg = <0xfe600000 0x1000>; + }; + + syscfg_front:front-syscfg@fee10000{ + compatible = "st,stih416-front-syscfg", "syscon"; + reg = <0xfee10000 0x1000>; + }; + + syscfg_rear:rear-syscfg@fe830000{ + compatible = "st,stih416-rear-syscfg", "syscon"; + reg = <0xfe830000 0x1000>; + }; + + /* MPE */ + syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{ + compatible = "st,stih416-fvdp-fe-syscfg", "syscon"; + reg = <0xfddf0000 0x1000>; + }; + + syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{ + compatible = "st,stih416-fvdp-lite-syscfg", "syscon"; + reg = <0xfd6a0000 0x1000>; + }; + + syscfg_cpu:cpu-syscfg@fdde0000{ + compatible = "st,stih416-cpu-syscfg", "syscon"; + reg = <0xfdde0000 0x1000>; + }; + + syscfg_compo:compo-syscfg@fd320000{ + compatible = "st,stih416-compo-syscfg", "syscon"; + reg = <0xfd320000 0x1000>; + }; + + syscfg_transport:transport-syscfg@fd690000{ + compatible = "st,stih416-transport-syscfg", "syscon"; + reg = <0xfd690000 0x1000>; + }; + + syscfg_lpm:lpm-syscfg@fe4b5100{ + compatible = "st,stih416-lpm-syscfg", "syscon"; + reg = <0xfe4b5100 0x8>; + }; + + serial2: serial@fed32000{ + compatible = "st,asc"; + status = "disabled"; + reg = <0xfed32000 0x2c>; + interrupts = <0 197 0>; + clocks = <&CLK_S_ICN_REG_0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_serial2>; + }; + + /* SBC_UART1 */ + sbc_serial1: serial@fe531000 { + compatible = "st,asc"; + status = "disabled"; + reg = <0xfe531000 0x2c>; + interrupts = <0 210 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_serial1>; + clocks = <&CLK_SYSIN>; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi new file mode 100644 index 000000000000..8e694d2b8f5b --- /dev/null +++ b/arch/arm/boot/dts/stih41x-b2000.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +/ { + + memory{ + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyAS0,115200"; + linux,stdout-path = &serial2; + }; + + aliases { + ttyAS0 = &serial2; + }; + + soc { + serial2: serial@fed32000 { + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + fp_led { + #gpio-cells = <1>; + label = "Front Panel LED"; + gpios = <&PIO105 7>; + linux,default-trigger = "heartbeat"; + }; + }; + + }; +}; diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi new file mode 100644 index 000000000000..133e18143b1b --- /dev/null +++ b/arch/arm/boot/dts/stih41x-b2020.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +/ { + memory{ + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + chosen { + bootargs = "console=ttyAS0,115200"; + linux,stdout-path = &sbc_serial1; + }; + + aliases { + ttyAS0 = &sbc_serial1; + }; + soc { + sbc_serial1: serial@fe531000 { + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + red { + #gpio-cells = <1>; + label = "Front Panel LED"; + gpios = <&PIO4 1>; + linux,default-trigger = "heartbeat"; + }; + green { + gpios = <&PIO4 7>; + default-state = "off"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi new file mode 100644 index 000000000000..7321403cab8a --- /dev/null +++ b/arch/arm/boot/dts/stih41x.dtsi @@ -0,0 +1,38 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + intc: interrupt-controller@fffe1000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfffe1000 0x1000>, + <0xfffe0100 0x100>; + }; + + scu@fffe0000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xfffe0000 0x1000>; + }; + + timer@fffe0200 { + interrupt-parent = <&intc>; + compatible = "arm,cortex-a9-global-timer"; + reg = <0xfffe0200 0x100>; + interrupts = <1 11 0x04>; + clocks = <&arm_periph_clk>; + }; +}; diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi index 615392a75676..524e33240ad4 100644 --- a/arch/arm/boot/dts/stuib.dtsi +++ b/arch/arm/boot/dts/stuib.dtsi @@ -9,13 +9,15 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include <dt-bindings/interrupt-controller/irq.h> + / { - soc-u9500 { + soc { i2c@80004000 { stmpe1601: stmpe1601@40 { compatible = "st,stmpe1601"; reg = <0x40>; - interrupts = <26 0x2>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; interrupt-parent = <&gpio6>; interrupt-controller; @@ -52,26 +54,26 @@ }; i2c@80110000 { - bu21013_tp@0x5c { - compatible = "rhom,bu21013_tp"; + bu21013_tp@5c { + compatible = "rohm,bu21013_tp"; reg = <0x5c>; touch-gpio = <&gpio2 20 0x4>; avdd-supply = <&ab8500_ldo_aux1_reg>; - rhom,touch-max-x = <384>; - rhom,touch-max-y = <704>; - rhom,flip-y; + rohm,touch-max-x = <384>; + rohm,touch-max-y = <704>; + rohm,flip-y; }; - bu21013_tp@0x5d { - compatible = "rhom,bu21013_tp"; + bu21013_tp@5d { + compatible = "rohm,bu21013_tp"; reg = <0x5d>; touch-gpio = <&gpio2 20 0x4>; avdd-supply = <&ab8500_ldo_aux1_reg>; - rhom,touch-max-x = <384>; - rhom,touch-max-y = <704>; - rhom,flip-y; + rohm,touch-max-x = <384>; + rohm,touch-max-y = <704>; + rohm,flip-y; }; }; }; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index b70fe0db6bb7..0e22a285dfe0 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -41,6 +41,18 @@ pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; }; leds { diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index 4a7c35d6726a..078ed7f618d7 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -22,8 +22,8 @@ bootargs = "earlyprintk console=ttyS0,115200"; }; - soc { - uart0: uart@01c28000 { + soc@01c20000 { + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index e7ef619a70a2..82e03d22f913 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -16,8 +16,12 @@ interrupt-parent = <&intc>; cpus { + #address-cells = <1>; + #size-cells = <0>; cpu@0 { + device_type = "cpu"; compatible = "arm,cortex-a8"; + reg = <0x0>; }; }; @@ -173,8 +177,10 @@ pio: pinctrl@01c20800 { compatible = "allwinner,sun4i-a10-pinctrl"; reg = <0x01c20800 0x400>; + interrupts = <28>; clocks = <&apb0_gates 5>; gpio-controller; + interrupt-controller; #address-cells = <1>; #size-cells = <0>; #gpio-cells = <3>; @@ -199,6 +205,27 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "i2c0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PB18", "PB19"; + allwinner,function = "i2c1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PB20", "PB21"; + allwinner,function = "i2c2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { @@ -292,5 +319,32 @@ clocks = <&apb1_gates 23>; status = "disabled"; }; + + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <7>; + clocks = <&apb1_gates 0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <8>; + clocks = <&apb1_gates 1>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <9>; + clocks = <&apb1_gates 2>; + clock-frequency = <100000>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts new file mode 100644 index 000000000000..64dc0c42c43a --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -0,0 +1,76 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun5i-a10s.dtsi" + +/ { + model = "Olimex A10s-Olinuxino Micro"; + compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s"; + + soc@01c20000 { + emac: ethernet@01c0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; + }; + + mdio@01c0b080 { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + pinctrl@01c20800 { + led_pins_olinuxino: led_pins@0 { + allwinner,pins = "PE3"; + allwinner,function = "gpio_out"; + allwinner,drive = <1>; + allwinner,pull = <0>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + uart2: serial@01c28800 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a>; + status = "okay"; + }; + + uart3: serial@01c28c00 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_a>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxino>; + + green { + label = "a10s-olinuxino-micro:green:usr"; + gpios = <&pio 4 3 0>; + default-state = "on"; + }; + }; +}; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi new file mode 100644 index 000000000000..2307ce827ae0 --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -0,0 +1,286 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&intc>; + + cpus { + cpu@0 { + compatible = "arm,cortex-a8"; + }; + }; + + memory { + reg = <0x40000000 0x20000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * This is a dummy clock, to be used as placeholder on + * other mux clocks when a specific parent clock is not + * yet implemented. It should be dropped when the driver + * is complete. + */ + dummy: dummy { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + osc24M: osc24M@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-osc-clk"; + reg = <0x01c20050 0x4>; + clock-frequency = <24000000>; + }; + + osc32k: osc32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + pll1: pll1@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + }; + + /* dummy is 200M */ + cpu: cpu@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-cpu-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; + }; + + axi: axi@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-axi-clk"; + reg = <0x01c20054 0x4>; + clocks = <&cpu>; + }; + + axi_gates: axi_gates@01c2005c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-axi-gates-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&axi>; + clock-output-names = "axi_dram"; + }; + + ahb: ahb@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&axi>; + }; + + ahb_gates: ahb_gates@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-ahb-gates-clk"; + reg = <0x01c20060 0x8>; + clocks = <&ahb>; + clock-output-names = "ahb_usb0", "ahb_ehci0", + "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", + "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", + "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", + "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", + "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", + "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", + "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", + "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", + "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", + "ahb_de_fe1", "ahb_mp", "ahb_mali400"; + }; + + apb0: apb0@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb>; + }; + + apb0_gates: apb0_gates@01c20068 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-apb0-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb0>; + clock-output-names = "apb0_codec", "apb0_spdif", + "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", + "apb0_ir1", "apb0_keypad"; + }; + + /* dummy is pll62 */ + apb1_mux: apb1_mux@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-apb1-mux-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc24M>, <&dummy>, <&osc32k>; + }; + + apb1: apb1@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&apb1_mux>; + }; + + apb1_gates: apb1_gates@01c2006c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-apb1-gates-clk"; + reg = <0x01c2006c 0x4>; + clocks = <&apb1>; + clock-output-names = "apb1_i2c0", "apb1_i2c1", + "apb1_i2c2", "apb1_can", "apb1_scr", + "apb1_ps20", "apb1_ps21", "apb1_uart0", + "apb1_uart1", "apb1_uart2", "apb1_uart3", + "apb1_uart4", "apb1_uart5", "apb1_uart6", + "apb1_uart7"; + }; + }; + + soc@01c20000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01c20000 0x300000>; + ranges; + + emac: ethernet@01c0b000 { + compatible = "allwinner,sun4i-emac"; + reg = <0x01c0b000 0x1000>; + interrupts = <55>; + clocks = <&ahb_gates 17>; + status = "disabled"; + }; + + mdio@01c0b080 { + compatible = "allwinner,sun4i-mdio"; + reg = <0x01c0b080 0x14>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + intc: interrupt-controller@01c20400 { + compatible = "allwinner,sun4i-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl@01c20800 { + compatible = "allwinner,sun5i-a10s-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <28>; + clocks = <&apb0_gates 5>; + gpio-controller; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <3>; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PB19", "PB20"; + allwinner,function = "uart0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart2_pins_a: uart2@0 { + allwinner,pins = "PC18", "PC19"; + allwinner,function = "uart2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart3_pins_a: uart3@0 { + allwinner,pins = "PG9", "PG10"; + allwinner,function = "uart3"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + emac_pins_a: emac0@0 { + allwinner,pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + allwinner,function = "emac"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + timer@01c20c00 { + compatible = "allwinner,sun4i-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <22>; + clocks = <&osc24M>; + }; + + wdt: watchdog@01c20c90 { + compatible = "allwinner,sun4i-wdt"; + reg = <0x01c20c90 0x10>; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 16>; + status = "disabled"; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 17>; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 18>; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 19>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 3ca55067f868..80497e376706 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -37,6 +37,24 @@ pinctrl-0 = <&uart1_pins_b>; status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + }; }; leds { diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 31fa38f8cc98..7363211daf84 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -17,8 +17,12 @@ interrupt-parent = <&intc>; cpus { + #address-cells = <1>; + #size-cells = <0>; cpu@0 { + device_type = "cpu"; compatible = "arm,cortex-a8"; + reg = <0x0>; }; }; @@ -95,20 +99,15 @@ ahb_gates: ahb_gates@01c20060 { #clock-cells = <1>; - compatible = "allwinner,sun4i-ahb-gates-clk"; + compatible = "allwinner,sun5i-a13-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; - clock-output-names = "ahb_usb0", "ahb_ehci0", - "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", - "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", - "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", - "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", - "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", - "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", - "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", - "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", - "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", - "ahb_de_fe1", "ahb_mp", "ahb_mali400"; + clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", + "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", + "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", + "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer", + "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be", + "ahb_de_fe", "ahb_iep", "ahb_mali400"; }; apb0: apb0@01c20054 { @@ -120,15 +119,13 @@ apb0_gates: apb0_gates@01c20068 { #clock-cells = <1>; - compatible = "allwinner,sun4i-apb0-gates-clk"; + compatible = "allwinner,sun5i-a13-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; - clock-output-names = "apb0_codec", "apb0_spdif", - "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", - "apb0_ir1", "apb0_keypad"; + clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; }; - /* dummy is pll62 */ + /* dummy is pll6 */ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-apb1-mux-clk"; @@ -145,15 +142,11 @@ apb1_gates: apb1_gates@01c2006c { #clock-cells = <1>; - compatible = "allwinner,sun4i-apb1-gates-clk"; + compatible = "allwinner,sun5i-a13-apb1-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb1>; clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_can", "apb1_scr", - "apb1_ps20", "apb1_ps21", "apb1_uart0", - "apb1_uart1", "apb1_uart2", "apb1_uart3", - "apb1_uart4", "apb1_uart5", "apb1_uart6", - "apb1_uart7"; + "apb1_i2c2", "apb1_uart1", "apb1_uart3"; }; }; @@ -174,8 +167,10 @@ pio: pinctrl@01c20800 { compatible = "allwinner,sun5i-a13-pinctrl"; reg = <0x01c20800 0x400>; + interrupts = <28>; clocks = <&apb0_gates 5>; gpio-controller; + interrupt-controller; #address-cells = <1>; #size-cells = <0>; #gpio-cells = <3>; @@ -193,6 +188,27 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "i2c0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PB15", "PB16"; + allwinner,function = "i2c1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PB17", "PB18"; + allwinner,function = "i2c2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { @@ -226,5 +242,32 @@ clocks = <&apb1_gates 19>; status = "disabled"; }; + + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <7>; + clocks = <&apb1_gates 0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <8>; + clocks = <&apb1_gates 1>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <9>; + clocks = <&apb1_gates 2>; + clock-frequency = <100000>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 72c1f27af7f3..cb640eb6c932 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "tegra114.dtsi" +#include "tegra114.dtsi" / { model = "NVIDIA Tegra114 Dalmore evaluation board"; @@ -727,6 +727,16 @@ battery-name = "battery"; sbs,i2c-retry-count = <2>; sbs,poll-retry-count = <100>; + power-supplies = <&charger>; + }; + + rt5640: rt5640 { + compatible = "realtek,rt5640"; + reg = <0x1c>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>; + realtek,ldo1-en-gpios = + <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; }; }; @@ -748,7 +758,7 @@ compatible = "ti,tps65090"; reg = <0x48>; interrupt-parent = <&gpio>; - interrupts = <72 0x04>; /* gpio PJ0 */ + interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>; vsys1-supply = <&vdd_ac_bat_reg>; vsys2-supply = <&vdd_ac_bat_reg>; @@ -763,6 +773,11 @@ vsys-l1-supply = <&vdd_ac_bat_reg>; vsys-l2-supply = <&vdd_ac_bat_reg>; + charger: charger { + compatible = "ti,tps65090-charger"; + ti,enable-low-current-chrg; + }; + regulators { tps65090_dcdc1_reg: dcdc1 { regulator-name = "vdd-sys-5v0"; @@ -823,12 +838,28 @@ }; }; + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + spi-flash@0 { + compatible = "winbond,w25q32dw"; + reg = <0>; + spi-max-frequency = <20000000>; + }; + }; + pmc { nvidia,invert-interrupt; }; + ahub { + i2s@70080400 { + status = "okay"; + }; + }; + sdhci@78000400 { - cd-gpios = <&gpio 170 1>; /* gpio PV2 */ + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; bus-width = <4>; status = "okay"; }; @@ -873,7 +904,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; enable-active-high; - gpio = <&gpio 61 0>; /* GPIO PH5 */ + gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; }; lcd_bl_en_reg: regulator@2 { @@ -883,7 +914,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio 58 0>; /* GPIO PH2 */ + gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; }; usb1_vbus_reg: regulator@3 { @@ -893,7 +924,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio 108 0>; /* GPIO PN4 */ + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; gpio-open-drain; vin-supply = <&tps65090_dcdc1_reg>; }; @@ -905,7 +936,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio 86 0>; /* GPIO PK6 */ + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; gpio-open-drain; vin-supply = <&tps65090_dcdc1_reg>; }; @@ -917,8 +948,32 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio 81 0>; /* GPIO PK1 */ + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; vin-supply = <&tps65090_dcdc1_reg>; }; }; + + sound { + compatible = "nvidia,tegra-audio-rt5640-dalmore", + "nvidia,tegra-audio-rt5640"; + nvidia,model = "NVIDIA Tegra Dalmore"; + + nvidia,audio-routing = + "Headphones", "HPOR", + "Headphones", "HPOL", + "Speakers", "SPORP", + "Speakers", "SPORN", + "Speakers", "SPOLP", + "Speakers", "SPOLN"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&rt5640>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; + + clocks = <&tegra_car TEGRA114_CLK_PLL_A>, + <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA114_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; }; diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts index 6bbc8efae9c0..d5f8d3e0bde2 100644 --- a/arch/arm/boot/dts/tegra114-pluto.dts +++ b/arch/arm/boot/dts/tegra114-pluto.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "tegra114.dtsi" +#include "tegra114.dtsi" / { model = "NVIDIA Tegra114 Pluto evaluation board"; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 629415ffd8dc..abf6c40d28c6 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -1,4 +1,8 @@ -/include/ "skeleton.dtsi" +#include <dt-bindings/clock/tegra114-car.h> +#include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include "skeleton.dtsi" / { compatible = "nvidia,tegra114"; @@ -19,19 +23,20 @@ <0x50042000 0x1000>, <0x50044000 0x2000>, <0x50046000 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; timer@60005000 { compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; reg = <0x60005000 0x400>; - interrupts = <0 0 0x04 - 0 1 0x04 - 0 41 0x04 - 0 42 0x04 - 0 121 0x04 - 0 122 0x04>; - clocks = <&tegra_car 5>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_TIMER>; }; tegra_car: clock { @@ -43,39 +48,39 @@ apbdma: dma { compatible = "nvidia,tegra114-apbdma"; reg = <0x6000a000 0x1400>; - interrupts = <0 104 0x04 - 0 105 0x04 - 0 106 0x04 - 0 107 0x04 - 0 108 0x04 - 0 109 0x04 - 0 110 0x04 - 0 111 0x04 - 0 112 0x04 - 0 113 0x04 - 0 114 0x04 - 0 115 0x04 - 0 116 0x04 - 0 117 0x04 - 0 118 0x04 - 0 119 0x04 - 0 128 0x04 - 0 129 0x04 - 0 130 0x04 - 0 131 0x04 - 0 132 0x04 - 0 133 0x04 - 0 134 0x04 - 0 135 0x04 - 0 136 0x04 - 0 137 0x04 - 0 138 0x04 - 0 139 0x04 - 0 140 0x04 - 0 141 0x04 - 0 142 0x04 - 0 143 0x04>; - clocks = <&tegra_car 34>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_APBDMA>; }; ahb: ahb { @@ -86,14 +91,14 @@ gpio: gpio { compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; reg = <0x6000d000 0x1000>; - interrupts = <0 32 0x04 - 0 33 0x04 - 0 34 0x04 - 0 35 0x04 - 0 55 0x04 - 0 87 0x04 - 0 89 0x04 - 0 125 0x04>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; @@ -118,57 +123,57 @@ compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; reg-shift = <2>; - interrupts = <0 36 0x04>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 8>; status = "disabled"; - clocks = <&tegra_car 6>; + clocks = <&tegra_car TEGRA114_CLK_UARTA>; }; uartb: serial@70006040 { compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; reg = <0x70006040 0x40>; reg-shift = <2>; - interrupts = <0 37 0x04>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 9>; status = "disabled"; - clocks = <&tegra_car 192>; + clocks = <&tegra_car TEGRA114_CLK_UARTB>; }; uartc: serial@70006200 { compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; reg = <0x70006200 0x100>; reg-shift = <2>; - interrupts = <0 46 0x04>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 10>; status = "disabled"; - clocks = <&tegra_car 55>; + clocks = <&tegra_car TEGRA114_CLK_UARTC>; }; uartd: serial@70006300 { compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; reg = <0x70006300 0x100>; reg-shift = <2>; - interrupts = <0 90 0x04>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 19>; status = "disabled"; - clocks = <&tegra_car 65>; + clocks = <&tegra_car TEGRA114_CLK_UARTD>; }; pwm: pwm { compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; - clocks = <&tegra_car 17>; + clocks = <&tegra_car TEGRA114_CLK_PWM>; status = "disabled"; }; i2c@7000c000 { compatible = "nvidia,tegra114-i2c"; reg = <0x7000c000 0x100>; - interrupts = <0 38 0x04>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 12>; + clocks = <&tegra_car TEGRA114_CLK_I2C1>; clock-names = "div-clk"; status = "disabled"; }; @@ -176,10 +181,10 @@ i2c@7000c400 { compatible = "nvidia,tegra114-i2c"; reg = <0x7000c400 0x100>; - interrupts = <0 84 0x04>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 54>; + clocks = <&tegra_car TEGRA114_CLK_I2C2>; clock-names = "div-clk"; status = "disabled"; }; @@ -187,10 +192,10 @@ i2c@7000c500 { compatible = "nvidia,tegra114-i2c"; reg = <0x7000c500 0x100>; - interrupts = <0 92 0x04>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 67>; + clocks = <&tegra_car TEGRA114_CLK_I2C3>; clock-names = "div-clk"; status = "disabled"; }; @@ -198,10 +203,10 @@ i2c@7000c700 { compatible = "nvidia,tegra114-i2c"; reg = <0x7000c700 0x100>; - interrupts = <0 120 0x04>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 103>; + clocks = <&tegra_car TEGRA114_CLK_I2C4>; clock-names = "div-clk"; status = "disabled"; }; @@ -209,10 +214,10 @@ i2c@7000d000 { compatible = "nvidia,tegra114-i2c"; reg = <0x7000d000 0x100>; - interrupts = <0 53 0x04>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 47>; + clocks = <&tegra_car TEGRA114_CLK_I2C5>; clock-names = "div-clk"; status = "disabled"; }; @@ -220,11 +225,11 @@ spi@7000d400 { compatible = "nvidia,tegra114-spi"; reg = <0x7000d400 0x200>; - interrupts = <0 59 0x04>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 15>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 41>; + clocks = <&tegra_car TEGRA114_CLK_SBC1>; clock-names = "spi"; status = "disabled"; }; @@ -232,11 +237,11 @@ spi@7000d600 { compatible = "nvidia,tegra114-spi"; reg = <0x7000d600 0x200>; - interrupts = <0 82 0x04>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 16>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 44>; + clocks = <&tegra_car TEGRA114_CLK_SBC2>; clock-names = "spi"; status = "disabled"; }; @@ -244,11 +249,11 @@ spi@7000d800 { compatible = "nvidia,tegra114-spi"; reg = <0x7000d800 0x200>; - interrupts = <0 83 0x04>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 46>; + clocks = <&tegra_car TEGRA114_CLK_SBC3>; clock-names = "spi"; status = "disabled"; }; @@ -256,11 +261,11 @@ spi@7000da00 { compatible = "nvidia,tegra114-spi"; reg = <0x7000da00 0x200>; - interrupts = <0 93 0x04>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 18>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 68>; + clocks = <&tegra_car TEGRA114_CLK_SBC4>; clock-names = "spi"; status = "disabled"; }; @@ -268,11 +273,11 @@ spi@7000dc00 { compatible = "nvidia,tegra114-spi"; reg = <0x7000dc00 0x200>; - interrupts = <0 94 0x04>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 27>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 104>; + clocks = <&tegra_car TEGRA114_CLK_SBC5>; clock-names = "spi"; status = "disabled"; }; @@ -280,11 +285,11 @@ spi@7000de00 { compatible = "nvidia,tegra114-spi"; reg = <0x7000de00 0x200>; - interrupts = <0 79 0x04>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 28>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 105>; + clocks = <&tegra_car TEGRA114_CLK_SBC6>; clock-names = "spi"; status = "disabled"; }; @@ -292,22 +297,22 @@ rtc { compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; - interrupts = <0 2 0x04>; - clocks = <&tegra_car 4>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_RTC>; }; kbc { compatible = "nvidia,tegra114-kbc"; reg = <0x7000e200 0x100>; - interrupts = <0 85 0x04>; - clocks = <&tegra_car 36>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_KBC>; status = "disabled"; }; pmc { compatible = "nvidia,tegra114-pmc"; reg = <0x7000e400 0x400>; - clocks = <&tegra_car 261>, <&clk32k_in>; + clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; }; @@ -322,35 +327,106 @@ nvidia,ahb = <&ahb>; }; + ahub { + compatible = "nvidia,tegra114-ahub"; + reg = <0x70080000 0x200>, + <0x70080200 0x100>, + <0x70081000 0x200>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>, + <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>, + <&apbdma 12>, <&apbdma 13>, <&apbdma 14>, + <&apbdma 29>; + clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, + <&tegra_car TEGRA114_CLK_APBIF>, + <&tegra_car TEGRA114_CLK_I2S0>, + <&tegra_car TEGRA114_CLK_I2S1>, + <&tegra_car TEGRA114_CLK_I2S2>, + <&tegra_car TEGRA114_CLK_I2S3>, + <&tegra_car TEGRA114_CLK_I2S4>, + <&tegra_car TEGRA114_CLK_DAM0>, + <&tegra_car TEGRA114_CLK_DAM1>, + <&tegra_car TEGRA114_CLK_DAM2>, + <&tegra_car TEGRA114_CLK_SPDIF_IN>, + <&tegra_car TEGRA114_CLK_AMX>, + <&tegra_car TEGRA114_CLK_ADX>; + clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + "i2s3", "i2s4", "dam0", "dam1", "dam2", + "spdif_in", "amx", "adx"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + tegra_i2s0: i2s@70080300 { + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; + reg = <0x70080300 0x100>; + nvidia,ahub-cif-ids = <4 4>; + clocks = <&tegra_car TEGRA114_CLK_I2S0>; + status = "disabled"; + }; + + tegra_i2s1: i2s@70080400 { + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; + reg = <0x70080400 0x100>; + nvidia,ahub-cif-ids = <5 5>; + clocks = <&tegra_car TEGRA114_CLK_I2S1>; + status = "disabled"; + }; + + tegra_i2s2: i2s@70080500 { + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; + reg = <0x70080500 0x100>; + nvidia,ahub-cif-ids = <6 6>; + clocks = <&tegra_car TEGRA114_CLK_I2S2>; + status = "disabled"; + }; + + tegra_i2s3: i2s@70080600 { + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; + reg = <0x70080600 0x100>; + nvidia,ahub-cif-ids = <7 7>; + clocks = <&tegra_car TEGRA114_CLK_I2S3>; + status = "disabled"; + }; + + tegra_i2s4: i2s@70080700 { + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; + reg = <0x70080700 0x100>; + nvidia,ahub-cif-ids = <8 8>; + clocks = <&tegra_car TEGRA114_CLK_I2S4>; + status = "disabled"; + }; + }; + sdhci@78000000 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000000 0x200>; - interrupts = <0 14 0x04>; - clocks = <&tegra_car 14>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; status = "disable"; }; sdhci@78000200 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000200 0x200>; - interrupts = <0 15 0x04>; - clocks = <&tegra_car 9>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; status = "disable"; }; sdhci@78000400 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000400 0x200>; - interrupts = <0 19 0x04>; - clocks = <&tegra_car 69>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; status = "disable"; }; sdhci@78000600 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000600 0x200>; - interrupts = <0 31 0x04>; - clocks = <&tegra_car 15>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; status = "disable"; }; @@ -385,9 +461,14 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = + <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; }; diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index a573b94b7c93..2fcb3f2ca160 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -1,4 +1,4 @@ -/include/ "tegra20.dtsi" +#include "tegra20.dtsi" / { model = "Toradex Colibri T20 512MB"; @@ -14,7 +14,8 @@ pll-supply = <&hdmi_pll_reg>; nvidia,ddc-i2c-bus = <&i2c_ddc>; - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; }; }; @@ -217,7 +218,7 @@ pmic: tps6586x@34 { compatible = "ti,tps6586x"; reg = <0x34>; - interrupts = <0 86 0x4>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; ti,system-power-controller; @@ -443,17 +444,25 @@ ac97: ac97 { status = "okay"; - nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ - nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */ + nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) + GPIO_ACTIVE_HIGH>; + nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0) + GPIO_ACTIVE_HIGH>; }; usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + + usb-phy@c5004000 { + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; }; sdhci@c8000600 { - cd-gpios = <&gpio 23 1>; /* gpio PC7 */ + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; }; clocks { @@ -483,7 +492,9 @@ nvidia,ac97-controller = <&ac97>; - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; @@ -510,7 +521,7 @@ enable-active-high; regulator-boot-on; regulator-always-on; - gpio = <&gpio 217 0>; + gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index e7d5de4e00b9..d9f89cd879a7 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "tegra20.dtsi" +#include "tegra20.dtsi" / { model = "NVIDIA Tegra20 Harmony evaluation board"; @@ -18,7 +18,8 @@ pll-supply = <&hdmi_pll_reg>; nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; }; }; @@ -262,7 +263,7 @@ compatible = "wlf,wm8903"; reg = <0x1a>; interrupt-parent = <&gpio>; - interrupts = <187 0x04>; + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; @@ -290,7 +291,7 @@ pmic: tps6586x@34 { compatible = "ti,tps6586x"; reg = <0x34>; - interrupts = <0 86 0x4>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; ti,system-power-controller; @@ -428,32 +429,43 @@ status = "okay"; }; + usb-phy@c5000000 { + status = "okay"; + }; + usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + + usb-phy@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; }; usb@c5008000 { status = "okay"; }; - usb-phy@c5004400 { - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + usb-phy@c5008000 { + status = "okay"; }; sdhci@c8000200 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 155 0>; /* gpio PT3 */ + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; sdhci@c8000600 { status = "okay"; - cd-gpios = <&gpio 58 1>; /* gpio PH2 */ - wp-gpios = <&gpio 59 0>; /* gpio PH3 */ - power-gpios = <&gpio 70 0>; /* gpio PI6 */ + cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; bus-width = <8>; }; @@ -475,7 +487,7 @@ power { label = "Power"; - gpios = <&gpio 170 1>; /* gpio PV2, active low */ + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; linux,code = <116>; /* KEY_POWER */ gpio-key,wakeup; }; @@ -618,7 +630,7 @@ regulator-name = "vdd_1v5"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 0>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; regulator@2 { @@ -627,7 +639,7 @@ regulator-name = "vdd_1v2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 0>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -637,7 +649,7 @@ regulator-name = "vdd_1v05"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; - gpio = <&pmic 2 0>; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; enable-active-high; /* Hack until board-harmony-pcie.c is removed */ status = "disabled"; @@ -649,7 +661,7 @@ regulator-name = "vdd_pnl"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&gpio 22 0>; /* gpio PC6 */ + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -659,7 +671,7 @@ regulator-name = "vdd_bl"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&gpio 176 0>; /* gpio PW0 */ + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; enable-active-high; }; }; @@ -682,12 +694,17 @@ nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&wm8903>; - nvidia,spkr-en-gpios = <&wm8903 2 0>; - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ - nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) + GPIO_ACTIVE_HIGH>; + nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) + GPIO_ACTIVE_HIGH>; + nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) + GPIO_ACTIVE_HIGH>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts index 52f1103907d7..f2222bd74eab 100644 --- a/arch/arm/boot/dts/tegra20-iris-512.dts +++ b/arch/arm/boot/dts/tegra20-iris-512.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "tegra20-colibri-512.dtsi" +#include "tegra20-colibri-512.dtsi" / { model = "Toradex Colibri T20 512MB on Iris"; @@ -38,13 +38,20 @@ usb@c5000000 { status = "okay"; - dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; }; usb@c5008000 { status = "okay"; }; + usb-phy@c5008000 { + status = "okay"; + }; + serial@70006000 { status = "okay"; }; @@ -73,7 +80,7 @@ regulator-max-microvolt = <5000000>; regulator-boot-on; regulator-always-on; - gpio = <&gpio 178 0>; + gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; }; vcc_sd_reg: regulator@1 { diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index ace23437da89..7580578903cf 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "tegra20-tamonten.dtsi" +#include "tegra20-tamonten.dtsi" / { model = "Avionic Design Medcom-Wide board"; @@ -15,7 +15,7 @@ compatible = "wlf,wm8903"; reg = <0x1a>; interrupt-parent = <&gpio>; - interrupts = <187 0x04>; + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; @@ -56,10 +56,12 @@ nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&wm8903>; - nvidia,spkr-en-gpios = <&wm8903 2 0>; - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index e3e0c9977df4..cfd12763b1b2 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "tegra20.dtsi" +#include "tegra20.dtsi" / { model = "Toshiba AC100 / Dynabook AZ"; @@ -18,7 +18,8 @@ pll-supply = <&hdmi_pll_reg>; nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; }; }; @@ -270,13 +271,14 @@ nvec { compatible = "nvidia,nvec"; reg = <0x7000c500 0x100>; - interrupts = <0 92 0x04>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-frequency = <80000>; - request-gpios = <&gpio 170 0>; /* gpio PV2 */ + request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; slave-addr = <138>; - clocks = <&tegra_car 67>, <&tegra_car 124>; + clocks = <&tegra_car TEGRA20_CLK_I2C3>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; }; @@ -287,7 +289,7 @@ pmic: tps6586x@34 { compatible = "ti,tps6586x"; reg = <0x34>; - interrupts = <0 86 0x4>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -427,24 +429,35 @@ status = "okay"; }; + usb-phy@c5000000 { + status = "okay"; + }; + usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) + GPIO_ACTIVE_LOW>; + }; + + usb-phy@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) + GPIO_ACTIVE_LOW>; }; usb@c5008000 { status = "okay"; }; - usb-phy@c5004400 { - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ + usb-phy@c5008000 { + status = "okay"; }; sdhci@c8000000 { status = "okay"; - cd-gpios = <&gpio 173 1>; /* gpio PV5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 169 0>; /* gpio PV1 */ + cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; @@ -472,7 +485,7 @@ power { label = "Power"; - gpios = <&gpio 79 1>; /* gpio PJ7, active low */ + gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; linux,code = <116>; /* KEY_POWER */ gpio-key,wakeup; }; @@ -483,7 +496,7 @@ wifi { label = "wifi-led"; - gpios = <&gpio 24 0>; /* gpio PD0 */ + gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; linux,default-trigger = "rfkill0"; }; }; @@ -520,9 +533,12 @@ nvidia,audio-codec = <&alc5632>; nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) + GPIO_ACTIVE_HIGH>; - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts index 1a17cc30bb9d..d7a358a6a647 100644 --- a/arch/arm/boot/dts/tegra20-plutux.dts +++ b/arch/arm/boot/dts/tegra20-plutux.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "tegra20-tamonten.dtsi" +#include "tegra20-tamonten.dtsi" / { model = "Avionic Design Plutux board"; @@ -17,7 +17,7 @@ compatible = "wlf,wm8903"; reg = <0x1a>; interrupt-parent = <&gpio>; - interrupts = <187 0x04>; + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; @@ -50,10 +50,12 @@ nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&wm8903>; - nvidia,spkr-en-gpios = <&wm8903 2 0>; - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index cee4c34010fe..ab177b406b78 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "tegra20.dtsi" +#include "tegra20.dtsi" / { model = "NVIDIA Seaboard"; @@ -18,7 +18,8 @@ pll-supply = <&hdmi_pll_reg>; nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; }; }; @@ -313,7 +314,7 @@ compatible = "wlf,wm8903"; reg = <0x1a>; interrupt-parent = <&gpio>; - interrupts = <187 0x04>; + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; @@ -328,14 +329,14 @@ compatible = "isil,isl29018"; reg = <0x44>; interrupt-parent = <&gpio>; - interrupts = <202 0x04>; /* GPIO PZ2 */ + interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; }; gyrometer@68 { compatible = "invn,mpu3050"; reg = <0x68>; interrupt-parent = <&gpio>; - interrupts = <204 0x04>; /* gpio PZ4 */ + interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -388,7 +389,7 @@ pmic: tps6586x@34 { compatible = "ti,tps6586x"; reg = <0x34>; - interrupts = <0 86 0x4>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; ti,system-power-controller; @@ -511,7 +512,7 @@ compatible = "ak,ak8975"; reg = <0xc>; interrupt-parent = <&gpio>; - interrupts = <109 0x04>; /* gpio PN5 */ + interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -565,35 +566,48 @@ usb@c5000000 { status = "okay"; - nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <&vbus_reg>; dr_mode = "otg"; }; usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + + usb-phy@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; }; usb@c5008000 { status = "okay"; }; - usb-phy@c5004400 { - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + usb-phy@c5008000 { + status = "okay"; }; sdhci@c8000000 { status = "okay"; - power-gpios = <&gpio 86 0>; /* gpio PK6 */ + power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; sdhci@c8000400 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 70 0>; /* gpio PI6 */ + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; @@ -621,14 +635,14 @@ power { label = "Power"; - gpios = <&gpio 170 1>; /* gpio PV2, active low */ + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; linux,code = <116>; /* KEY_POWER */ gpio-key,wakeup; }; lid { label = "Lid"; - gpios = <&gpio 23 0>; /* gpio PC7 */ + gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; linux,input-type = <5>; /* EV_SW */ linux,code = <0>; /* SW_LID */ debounce-interval = <1>; @@ -795,7 +809,7 @@ regulator-name = "vdd_1v5"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 0>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; regulator@2 { @@ -804,9 +818,18 @@ regulator-name = "vdd_1v2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 0>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + vbus_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_vbus_wup1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 24 0>; /* PD0 */ + }; }; sound { @@ -827,10 +850,12 @@ nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&wm8903>; - nvidia,spkr-en-gpios = <&wm8903 2 0>; - nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */ + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 50b3ec16b93a..c54faae7cfb3 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -1,4 +1,4 @@ -/include/ "tegra20.dtsi" +#include "tegra20.dtsi" / { model = "Avionic Design Tamonten SOM"; @@ -14,7 +14,8 @@ pll-supply = <&hdmi_pll_reg>; nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; }; }; @@ -321,7 +322,7 @@ pmic: tps6586x@34 { compatible = "ti,tps6586x"; reg = <0x34>; - interrupts = <0 86 0x4>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; ti,system-power-controller; @@ -470,9 +471,13 @@ status = "okay"; }; + usb-phy@c5008000 { + status = "okay"; + }; + sdhci@c8000600 { - cd-gpios = <&gpio 58 1>; /* gpio PH2 */ - wp-gpios = <&gpio 59 0>; /* gpio PH3 */ + cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; bus-width = <4>; status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index 742f0b38d21d..c572c43751b1 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "tegra20-tamonten.dtsi" +#include "tegra20-tamonten.dtsi" / { model = "Avionic Design Tamonten Evaluation Carrier"; @@ -17,7 +17,7 @@ compatible = "wlf,wm8903"; reg = <0x1a>; interrupt-parent = <&gpio>; - interrupts = <187 0x04>; + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; @@ -50,10 +50,13 @@ nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&wm8903>; - nvidia,spkr-en-gpios = <&wm8903 2 0>; - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) + GPIO_ACTIVE_HIGH>; - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 9cc78a15d739..170159910455 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "tegra20.dtsi" +#include "tegra20.dtsi" / { model = "Compulab TrimSlice board"; @@ -18,7 +18,8 @@ pll-supply = <&hdmi_pll_reg>; nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; }; }; @@ -311,20 +312,32 @@ usb@c5000000 { status = "okay"; - nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */ + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + }; + + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <&vbus_reg>; }; usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) + GPIO_ACTIVE_LOW>; + }; + + usb-phy@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) + GPIO_ACTIVE_LOW>; }; usb@c5008000 { status = "okay"; }; - usb-phy@c5004400 { - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ + usb-phy@c5008000 { + status = "okay"; }; sdhci@c8000000 { @@ -334,8 +347,8 @@ sdhci@c8000600 { status = "okay"; - cd-gpios = <&gpio 121 1>; /* gpio PP1 */ - wp-gpios = <&gpio 122 0>; /* gpio PP2 */ + cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; @@ -357,7 +370,7 @@ power { label = "Power"; - gpios = <&gpio 190 1>; /* gpio PX6, active low */ + gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; linux,code = <116>; /* KEY_POWER */ gpio-key,wakeup; }; @@ -365,7 +378,7 @@ poweroff { compatible = "gpio-poweroff"; - gpios = <&gpio 191 1>; /* gpio PX7, active low */ + gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; }; regulators { @@ -390,6 +403,15 @@ regulator-max-microvolt = <1800000>; regulator-always-on; }; + + vbus_reg: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 170 0>; /* PV2 */ + }; }; sound { @@ -397,7 +419,9 @@ nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&codec>; - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index dd38f1f03834..7f8c28d1121f 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "tegra20.dtsi" +#include "tegra20.dtsi" / { model = "NVIDIA Tegra20 Ventana evaluation board"; @@ -18,7 +18,8 @@ pll-supply = <&hdmi_pll_reg>; nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; }; }; @@ -310,7 +311,7 @@ compatible = "wlf,wm8903"; reg = <0x1a>; interrupt-parent = <&gpio>; - interrupts = <187 0x04>; + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; @@ -325,7 +326,7 @@ compatible = "isil,isl29018"; reg = <0x44>; interrupt-parent = <&gpio>; - interrupts = <202 0x04>; /*gpio PZ2 */ + interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -371,7 +372,7 @@ pmic: tps6586x@34 { compatible = "ti,tps6586x"; reg = <0x34>; - interrupts = <0 86 0x4>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; ti,system-power-controller; @@ -505,31 +506,42 @@ status = "okay"; }; + usb-phy@c5000000 { + status = "okay"; + }; + usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + + usb-phy@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; }; usb@c5008000 { status = "okay"; }; - usb-phy@c5004400 { - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + usb-phy@c5008000 { + status = "okay"; }; sdhci@c8000000 { status = "okay"; - power-gpios = <&gpio 86 0>; /* gpio PK6 */ + power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; sdhci@c8000400 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 70 0>; /* gpio PI6 */ + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; @@ -557,7 +569,7 @@ power { label = "Power"; - gpios = <&gpio 170 1>; /* gpio PV2, active low */ + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; linux,code = <116>; /* KEY_POWER */ gpio-key,wakeup; }; @@ -583,7 +595,7 @@ regulator-name = "vdd_1v5"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 0>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; regulator@2 { @@ -592,7 +604,7 @@ regulator-name = "vdd_1v2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 0>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -602,7 +614,7 @@ regulator-name = "vdd_pnl"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&gpio 22 0>; /* gpio PC6 */ + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -612,7 +624,7 @@ regulator-name = "vdd_bl"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&gpio 176 0>; /* gpio PW0 */ + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; enable-active-high; }; }; @@ -635,12 +647,16 @@ nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&wm8903>; - nvidia,spkr-en-gpios = <&wm8903 2 0>; - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */ - nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) + GPIO_ACTIVE_HIGH>; + nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) + GPIO_ACTIVE_HIGH>; - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index d2567f83aaff..ea078ab8edeb 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "tegra20.dtsi" +#include "tegra20.dtsi" / { model = "NVIDIA Tegra20 Whistler evaluation board"; @@ -18,7 +18,8 @@ pll-supply = <&hdmi_pll_reg>; nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; }; }; @@ -281,7 +282,7 @@ max8907@3c { compatible = "maxim,max8907"; reg = <0x3c>; - interrupts = <0 86 0x4>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; maxim,system-power-controller; @@ -508,18 +509,28 @@ usb@c5000000 { status = "okay"; - nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ + nvidia,vbus-gpio = <&tca6416 0 GPIO_ACTIVE_HIGH>; + }; + + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <&vbus1_reg>; }; usb@c5008000 { status = "okay"; - nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ + nvidia,vbus-gpio = <&tca6416 1 GPIO_ACTIVE_HIGH>; + }; + + usb-phy@c5008000 { + status = "okay"; + vbus-supply = <&vbus3_reg>; }; sdhci@c8000400 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ - wp-gpios = <&gpio 173 0>; /* gpio PV5 */ + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; bus-width = <8>; }; @@ -568,6 +579,24 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; + + vbus1_reg: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vbus1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ + }; + + vbus3_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vbus3"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ + }; }; sound { @@ -584,7 +613,9 @@ nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&codec>; - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 56a91106041b..9653fd8288d2 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -1,4 +1,8 @@ -/include/ "skeleton.dtsi" +#include <dt-bindings/clock/tegra20-car.h> +#include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include "skeleton.dtsi" / { compatible = "nvidia,tegra20"; @@ -15,9 +19,9 @@ host1x { compatible = "nvidia,tegra20-host1x", "simple-bus"; reg = <0x50000000 0x00024000>; - interrupts = <0 65 0x04 /* mpcore syncpt */ - 0 67 0x04>; /* mpcore general */ - clocks = <&tegra_car 28>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ + clocks = <&tegra_car TEGRA20_CLK_HOST1X>; #address-cells = <1>; #size-cells = <1>; @@ -27,49 +31,50 @@ mpe { compatible = "nvidia,tegra20-mpe"; reg = <0x54040000 0x00040000>; - interrupts = <0 68 0x04>; - clocks = <&tegra_car 60>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_MPE>; }; vi { compatible = "nvidia,tegra20-vi"; reg = <0x54080000 0x00040000>; - interrupts = <0 69 0x04>; - clocks = <&tegra_car 100>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_VI>; }; epp { compatible = "nvidia,tegra20-epp"; reg = <0x540c0000 0x00040000>; - interrupts = <0 70 0x04>; - clocks = <&tegra_car 19>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_EPP>; }; isp { compatible = "nvidia,tegra20-isp"; reg = <0x54100000 0x00040000>; - interrupts = <0 71 0x04>; - clocks = <&tegra_car 23>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_ISP>; }; gr2d { compatible = "nvidia,tegra20-gr2d"; reg = <0x54140000 0x00040000>; - interrupts = <0 72 0x04>; - clocks = <&tegra_car 21>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_GR2D>; }; gr3d { compatible = "nvidia,tegra20-gr3d"; reg = <0x54180000 0x00040000>; - clocks = <&tegra_car 24>; + clocks = <&tegra_car TEGRA20_CLK_GR3D>; }; dc@54200000 { compatible = "nvidia,tegra20-dc"; reg = <0x54200000 0x00040000>; - interrupts = <0 73 0x04>; - clocks = <&tegra_car 27>, <&tegra_car 121>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_DISP1>, + <&tegra_car TEGRA20_CLK_PLL_P>; clock-names = "disp1", "parent"; rgb { @@ -80,8 +85,9 @@ dc@54240000 { compatible = "nvidia,tegra20-dc"; reg = <0x54240000 0x00040000>; - interrupts = <0 74 0x04>; - clocks = <&tegra_car 26>, <&tegra_car 121>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_DISP2>, + <&tegra_car TEGRA20_CLK_PLL_P>; clock-names = "disp2", "parent"; rgb { @@ -92,8 +98,9 @@ hdmi { compatible = "nvidia,tegra20-hdmi"; reg = <0x54280000 0x00040000>; - interrupts = <0 75 0x04>; - clocks = <&tegra_car 51>, <&tegra_car 117>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_HDMI>, + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; clock-names = "hdmi", "parent"; status = "disabled"; }; @@ -101,15 +108,15 @@ tvo { compatible = "nvidia,tegra20-tvo"; reg = <0x542c0000 0x00040000>; - interrupts = <0 76 0x04>; - clocks = <&tegra_car 102>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_TVO>; status = "disabled"; }; dsi { compatible = "nvidia,tegra20-dsi"; reg = <0x54300000 0x00040000>; - clocks = <&tegra_car 48>; + clocks = <&tegra_car TEGRA20_CLK_DSI>; status = "disabled"; }; }; @@ -117,8 +124,9 @@ timer@50004600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x50040600 0x20>; - interrupts = <1 13 0x304>; - clocks = <&tegra_car 132>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&tegra_car TEGRA20_CLK_TWD>; }; intc: interrupt-controller { @@ -141,11 +149,11 @@ timer@60005000 { compatible = "nvidia,tegra20-timer"; reg = <0x60005000 0x60>; - interrupts = <0 0 0x04 - 0 1 0x04 - 0 41 0x04 - 0 42 0x04>; - clocks = <&tegra_car 5>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_TIMER>; }; tegra_car: clock { @@ -157,23 +165,23 @@ apbdma: dma { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; - interrupts = <0 104 0x04 - 0 105 0x04 - 0 106 0x04 - 0 107 0x04 - 0 108 0x04 - 0 109 0x04 - 0 110 0x04 - 0 111 0x04 - 0 112 0x04 - 0 113 0x04 - 0 114 0x04 - 0 115 0x04 - 0 116 0x04 - 0 117 0x04 - 0 118 0x04 - 0 119 0x04>; - clocks = <&tegra_car 34>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_APBDMA>; }; ahb { @@ -184,13 +192,13 @@ gpio: gpio { compatible = "nvidia,tegra20-gpio"; reg = <0x6000d000 0x1000>; - interrupts = <0 32 0x04 - 0 33 0x04 - 0 34 0x04 - 0 35 0x04 - 0 55 0x04 - 0 87 0x04 - 0 89 0x04>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; @@ -213,27 +221,27 @@ tegra_ac97: ac97 { compatible = "nvidia,tegra20-ac97"; reg = <0x70002000 0x200>; - interrupts = <0 81 0x04>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 12>; - clocks = <&tegra_car 3>; + clocks = <&tegra_car TEGRA20_CLK_AC97>; status = "disabled"; }; tegra_i2s1: i2s@70002800 { compatible = "nvidia,tegra20-i2s"; reg = <0x70002800 0x200>; - interrupts = <0 13 0x04>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 2>; - clocks = <&tegra_car 11>; + clocks = <&tegra_car TEGRA20_CLK_I2S1>; status = "disabled"; }; tegra_i2s2: i2s@70002a00 { compatible = "nvidia,tegra20-i2s"; reg = <0x70002a00 0x200>; - interrupts = <0 3 0x04>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 1>; - clocks = <&tegra_car 18>; + clocks = <&tegra_car TEGRA20_CLK_I2S2>; status = "disabled"; }; @@ -248,9 +256,9 @@ compatible = "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; reg-shift = <2>; - interrupts = <0 36 0x04>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 8>; - clocks = <&tegra_car 6>; + clocks = <&tegra_car TEGRA20_CLK_UARTA>; status = "disabled"; }; @@ -258,9 +266,9 @@ compatible = "nvidia,tegra20-uart"; reg = <0x70006040 0x40>; reg-shift = <2>; - interrupts = <0 37 0x04>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 9>; - clocks = <&tegra_car 96>; + clocks = <&tegra_car TEGRA20_CLK_UARTB>; status = "disabled"; }; @@ -268,9 +276,9 @@ compatible = "nvidia,tegra20-uart"; reg = <0x70006200 0x100>; reg-shift = <2>; - interrupts = <0 46 0x04>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 10>; - clocks = <&tegra_car 55>; + clocks = <&tegra_car TEGRA20_CLK_UARTC>; status = "disabled"; }; @@ -278,9 +286,9 @@ compatible = "nvidia,tegra20-uart"; reg = <0x70006300 0x100>; reg-shift = <2>; - interrupts = <0 90 0x04>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 19>; - clocks = <&tegra_car 65>; + clocks = <&tegra_car TEGRA20_CLK_UARTD>; status = "disabled"; }; @@ -288,9 +296,9 @@ compatible = "nvidia,tegra20-uart"; reg = <0x70006400 0x100>; reg-shift = <2>; - interrupts = <0 91 0x04>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 20>; - clocks = <&tegra_car 66>; + clocks = <&tegra_car TEGRA20_CLK_UARTE>; status = "disabled"; }; @@ -298,24 +306,25 @@ compatible = "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; - clocks = <&tegra_car 17>; + clocks = <&tegra_car TEGRA20_CLK_PWM>; status = "disabled"; }; rtc { compatible = "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; - interrupts = <0 2 0x04>; - clocks = <&tegra_car 4>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_RTC>; }; i2c@7000c000 { compatible = "nvidia,tegra20-i2c"; reg = <0x7000c000 0x100>; - interrupts = <0 38 0x04>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 12>, <&tegra_car 124>; + clocks = <&tegra_car TEGRA20_CLK_I2C1>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -323,21 +332,22 @@ spi@7000c380 { compatible = "nvidia,tegra20-sflash"; reg = <0x7000c380 0x80>; - interrupts = <0 39 0x04>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 11>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 43>; + clocks = <&tegra_car TEGRA20_CLK_SPI>; status = "disabled"; }; i2c@7000c400 { compatible = "nvidia,tegra20-i2c"; reg = <0x7000c400 0x100>; - interrupts = <0 84 0x04>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 54>, <&tegra_car 124>; + clocks = <&tegra_car TEGRA20_CLK_I2C2>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -345,10 +355,11 @@ i2c@7000c500 { compatible = "nvidia,tegra20-i2c"; reg = <0x7000c500 0x100>; - interrupts = <0 92 0x04>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 67>, <&tegra_car 124>; + clocks = <&tegra_car TEGRA20_CLK_I2C3>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -356,10 +367,11 @@ i2c@7000d000 { compatible = "nvidia,tegra20-i2c-dvc"; reg = <0x7000d000 0x200>; - interrupts = <0 53 0x04>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 47>, <&tegra_car 124>; + clocks = <&tegra_car TEGRA20_CLK_DVC>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -367,59 +379,59 @@ spi@7000d400 { compatible = "nvidia,tegra20-slink"; reg = <0x7000d400 0x200>; - interrupts = <0 59 0x04>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 15>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 41>; + clocks = <&tegra_car TEGRA20_CLK_SBC1>; status = "disabled"; }; spi@7000d600 { compatible = "nvidia,tegra20-slink"; reg = <0x7000d600 0x200>; - interrupts = <0 82 0x04>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 16>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 44>; + clocks = <&tegra_car TEGRA20_CLK_SBC2>; status = "disabled"; }; spi@7000d800 { compatible = "nvidia,tegra20-slink"; reg = <0x7000d800 0x200>; - interrupts = <0 83 0x04>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 46>; + clocks = <&tegra_car TEGRA20_CLK_SBC3>; status = "disabled"; }; spi@7000da00 { compatible = "nvidia,tegra20-slink"; reg = <0x7000da00 0x200>; - interrupts = <0 93 0x04>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 18>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 68>; + clocks = <&tegra_car TEGRA20_CLK_SBC4>; status = "disabled"; }; kbc { compatible = "nvidia,tegra20-kbc"; reg = <0x7000e200 0x100>; - interrupts = <0 85 0x04>; - clocks = <&tegra_car 36>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_KBC>; status = "disabled"; }; pmc { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; - clocks = <&tegra_car 110>, <&clk32k_in>; + clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; }; @@ -427,7 +439,7 @@ compatible = "nvidia,tegra20-mc"; reg = <0x7000f000 0x024 0x7000f03c 0x3c4>; - interrupts = <0 77 0x04>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; }; iommu { @@ -446,89 +458,114 @@ usb@c5000000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5000000 0x4000>; - interrupts = <0 20 0x04>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; nvidia,has-legacy-mode; - clocks = <&tegra_car 22>; + clocks = <&tegra_car TEGRA20_CLK_USBD>; nvidia,needs-double-reset; nvidia,phy = <&phy1>; status = "disabled"; }; - phy1: usb-phy@c5000400 { + phy1: usb-phy@c5000000 { compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5000400 0x3c00>; + reg = <0xc5000000 0x4000 0xc5000000 0x4000>; phy_type = "utmi"; + clocks = <&tegra_car TEGRA20_CLK_USBD>, + <&tegra_car TEGRA20_CLK_PLL_U>, + <&tegra_car TEGRA20_CLK_CLK_M>, + <&tegra_car TEGRA20_CLK_USBD>; + clock-names = "reg", "pll_u", "timer", "utmi-pads"; nvidia,has-legacy-mode; - clocks = <&tegra_car 22>, <&tegra_car 127>; - clock-names = "phy", "pll_u"; + hssync_start_delay = <9>; + idle_wait_delay = <17>; + elastic_limit = <16>; + term_range_adj = <6>; + xcvr_setup = <9>; + xcvr_lsfslew = <1>; + xcvr_lsrslew = <1>; + status = "disabled"; }; usb@c5004000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5004000 0x4000>; - interrupts = <0 21 0x04>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; phy_type = "ulpi"; - clocks = <&tegra_car 58>; + clocks = <&tegra_car TEGRA20_CLK_USB2>; nvidia,phy = <&phy2>; status = "disabled"; }; - phy2: usb-phy@c5004400 { + phy2: usb-phy@c5004000 { compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5004400 0x3c00>; + reg = <0xc5004000 0x4000>; phy_type = "ulpi"; - clocks = <&tegra_car 93>, <&tegra_car 127>; - clock-names = "phy", "pll_u"; + clocks = <&tegra_car TEGRA20_CLK_USB2>, + <&tegra_car TEGRA20_CLK_PLL_U>, + <&tegra_car TEGRA20_CLK_CDEV2>; + clock-names = "reg", "pll_u", "ulpi-link"; + status = "disabled"; }; usb@c5008000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5008000 0x4000>; - interrupts = <0 97 0x04>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; - clocks = <&tegra_car 59>; + clocks = <&tegra_car TEGRA20_CLK_USB3>; nvidia,phy = <&phy3>; status = "disabled"; }; - phy3: usb-phy@c5008400 { + phy3: usb-phy@c5008000 { compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5008400 0x3c00>; + reg = <0xc5008000 0x4000 0xc5000000 0x4000>; phy_type = "utmi"; - clocks = <&tegra_car 22>, <&tegra_car 127>; - clock-names = "phy", "pll_u"; + clocks = <&tegra_car TEGRA20_CLK_USB3>, + <&tegra_car TEGRA20_CLK_PLL_U>, + <&tegra_car TEGRA20_CLK_CLK_M>, + <&tegra_car TEGRA20_CLK_USBD>; + clock-names = "reg", "pll_u", "timer", "utmi-pads"; + hssync_start_delay = <9>; + idle_wait_delay = <17>; + elastic_limit = <16>; + term_range_adj = <6>; + xcvr_setup = <9>; + xcvr_lsfslew = <2>; + xcvr_lsrslew = <2>; + status = "disabled"; }; sdhci@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; - interrupts = <0 14 0x04>; - clocks = <&tegra_car 14>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; status = "disabled"; }; sdhci@c8000200 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000200 0x200>; - interrupts = <0 15 0x04>; - clocks = <&tegra_car 9>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; status = "disabled"; }; sdhci@c8000400 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000400 0x200>; - interrupts = <0 19 0x04>; - clocks = <&tegra_car 69>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; status = "disabled"; }; sdhci@c8000600 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000600 0x200>; - interrupts = <0 31 0x04>; - clocks = <&tegra_car 15>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; status = "disabled"; }; @@ -551,7 +588,7 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 56 0x04 - 0 57 0x04>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index b732f7c13a66..87c5f7b7c271 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1,13 +1,13 @@ /dts-v1/; -/include/ "tegra30.dtsi" +#include "tegra30.dtsi" / { model = "NVIDIA Tegra30 Beaver evaluation board"; compatible = "nvidia,beaver", "nvidia,tegra30"; memory { - reg = <0x80000000 0x80000000>; + reg = <0x80000000 0x7ff00000>; }; pinmux { @@ -116,6 +116,15 @@ status = "okay"; clock-frequency = <100000>; + rt5640: rt5640 { + compatible = "realtek,rt5640"; + reg = <0x1c>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>; + realtek,ldo1-en-gpios = + <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; + }; + tps62361 { compatible = "ti,tps62361"; reg = <0x60>; @@ -133,7 +142,7 @@ compatible = "ti,tps65911"; reg = <0x2d>; - interrupts = <0 86 0x4>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; interrupt-controller; @@ -264,9 +273,9 @@ sdhci@78000000 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ - wp-gpios = <&gpio 155 0>; /* gpio PT3 */ - power-gpios = <&gpio 31 0>; /* gpio PD7 */ + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; @@ -312,7 +321,7 @@ regulator-boot-on; regulator-always-on; enable-active-high; - gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */ + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; ddr_reg: regulator@2 { @@ -324,7 +333,7 @@ regulator-always-on; regulator-boot-on; enable-active-high; - gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */ + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; vin-supply = <&vdd_5v_in_reg>; }; @@ -337,7 +346,7 @@ regulator-always-on; regulator-boot-on; enable-active-high; - gpio = <&gpio 30 0>; /* gpio PD6 */ + gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; vin-supply = <&vdd_5v_in_reg>; }; @@ -348,7 +357,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio 68 0>; /* GPIO PI4 */ + gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; gpio-open-drain; vin-supply = <&vdd_5v_in_reg>; }; @@ -360,7 +369,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio 63 0>; /* GPIO PH7 */ + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; gpio-open-drain; vin-supply = <&vdd_5v_in_reg>; }; @@ -374,7 +383,7 @@ regulator-always-on; regulator-boot-on; enable-active-high; - gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */ + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; vin-supply = <&vdd_5v_in_reg>; }; @@ -387,8 +396,41 @@ regulator-always-on; regulator-boot-on; enable-active-high; - gpio = <&gpio 95 0>; /* gpio PL7 */ + gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; vin-supply = <&sys_3v3_reg>; }; }; + + gpio-leds { + compatible = "gpio-leds"; + + gpled1 { + label = "LED1"; /* CR5A1 (blue) */ + gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>; + }; + gpled2 { + label = "LED2"; /* CR4A2 (green) */ + gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-rt5640-beaver", + "nvidia,tegra-audio-rt5640"; + nvidia,model = "NVIDIA Tegra Beaver"; + + nvidia,audio-routing = + "Headphones", "HPOR", + "Headphones", "HPOL"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&rt5640>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts index e392bd2dab9b..1082c5ed90d1 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "tegra30-cardhu.dtsi" +#include "tegra30-cardhu.dtsi" /* This dts file support the cardhu A02 version of board */ @@ -22,7 +22,7 @@ regulator-always-on; regulator-boot-on; enable-active-high; - gpio = <&pmic 6 0>; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; }; sys_3v3_reg: regulator@101 { @@ -34,7 +34,7 @@ regulator-always-on; regulator-boot-on; enable-active-high; - gpio = <&pmic 7 0>; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; }; usb1_vbus_reg: regulator@102 { @@ -44,7 +44,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio 68 0>; /* GPIO PI4 */ + gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; gpio-open-drain; vin-supply = <&vdd_5v0_reg>; }; @@ -56,7 +56,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio 63 0>; /* GPIO PH7 */ + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; gpio-open-drain; vin-supply = <&vdd_5v0_reg>; }; @@ -68,7 +68,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&pmic 2 0>; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; }; vdd_bl_reg: regulator@105 { @@ -80,13 +80,13 @@ regulator-always-on; regulator-boot-on; enable-active-high; - gpio = <&gpio 83 0>; /* GPIO PK3 */ + gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; }; }; sdhci@78000400 { status = "okay"; - power-gpios = <&gpio 28 0>; /* gpio PD4 */ + power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts index d0db6c7e774f..bf012bddaafb 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "tegra30-cardhu.dtsi" +#include "tegra30-cardhu.dtsi" /* This dts file support the cardhu A04 and later versions of board */ @@ -22,7 +22,7 @@ regulator-always-on; regulator-boot-on; enable-active-high; - gpio = <&pmic 7 0>; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; }; sys_3v3_reg: regulator@101 { @@ -34,7 +34,7 @@ regulator-always-on; regulator-boot-on; enable-active-high; - gpio = <&pmic 6 0>; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; }; usb1_vbus_reg: regulator@102 { @@ -44,7 +44,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio 238 0>; /* GPIO PDD6 */ + gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; gpio-open-drain; vin-supply = <&vdd_5v0_reg>; }; @@ -56,7 +56,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio 236 0>; /* GPIO PDD4 */ + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; gpio-open-drain; vin-supply = <&vdd_5v0_reg>; }; @@ -68,7 +68,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&pmic 8 0>; + gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; }; vdd_bl_reg: regulator@105 { @@ -80,7 +80,7 @@ regulator-always-on; regulator-boot-on; enable-active-high; - gpio = <&gpio 234 0>; /* GPIO PDD2 */ + gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; }; vdd_bl2_reg: regulator@106 { @@ -92,13 +92,13 @@ regulator-always-on; regulator-boot-on; enable-active-high; - gpio = <&gpio 232 0>; /* GPIO PDD0 */ + gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; }; }; sdhci@78000400 { status = "okay"; - power-gpios = <&gpio 27 0>; /* gpio PD3 */ + power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 01b4c26fad96..f65b53d32416 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -1,4 +1,4 @@ -/include/ "tegra30.dtsi" +#include "tegra30.dtsi" /** * This file contains common DT entry for all fab version of Cardhu. @@ -146,7 +146,7 @@ compatible = "isil,isl29028"; reg = <0x44>; interrupt-parent = <&gpio>; - interrupts = <88 0x04>; /*gpio PL0 */ + interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -163,7 +163,7 @@ compatible = "wlf,wm8903"; reg = <0x1a>; interrupt-parent = <&gpio>; - interrupts = <179 0x04>; /* gpio PW3 */ + interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; @@ -190,7 +190,7 @@ compatible = "ti,tps65911"; reg = <0x2d>; - interrupts = <0 86 0x4>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; interrupt-controller; @@ -318,9 +318,9 @@ sdhci@78000000 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ - wp-gpios = <&gpio 155 0>; /* gpio PT3 */ - power-gpios = <&gpio 31 0>; /* gpio PD7 */ + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; @@ -364,7 +364,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; enable-active-high; - gpio = <&gpio 220 0>; /* gpio PBB4 */ + gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; vin-supply = <&vio_reg>; }; @@ -377,7 +377,7 @@ regulator-boot-on; regulator-always-on; enable-active-high; - gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */ + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; emmc_3v3_reg: regulator@3 { @@ -389,7 +389,7 @@ regulator-always-on; regulator-boot-on; enable-active-high; - gpio = <&gpio 25 0>; /* gpio PD1 */ + gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; vin-supply = <&sys_3v3_reg>; }; @@ -400,7 +400,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; - gpio = <&gpio 30 0>; /* gpio PD6 */ + gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; }; pex_hvdd_3v3_reg: regulator@5 { @@ -410,7 +410,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; - gpio = <&gpio 95 0>; /* gpio PL7 */ + gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; vin-supply = <&sys_3v3_reg>; }; @@ -421,7 +421,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; enable-active-high; - gpio = <&gpio 142 0>; /* gpio PR6 */ + gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; vin-supply = <&sys_3v3_reg>; }; @@ -432,7 +432,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; enable-active-high; - gpio = <&gpio 143 0>; /* gpio PR7 */ + gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; vin-supply = <&sys_3v3_reg>; }; @@ -443,7 +443,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; - gpio = <&gpio 144 0>; /* gpio PS0 */ + gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; vin-supply = <&sys_3v3_reg>; }; @@ -456,7 +456,7 @@ regulator-always-on; regulator-boot-on; enable-active-high; - gpio = <&gpio 24 0>; /* gpio PD0 */ + gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; vin-supply = <&sys_3v3_reg>; }; @@ -467,7 +467,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; - gpio = <&gpio 94 0>; /* gpio PL6 */ + gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; vin-supply = <&sys_3v3_reg>; }; @@ -480,7 +480,7 @@ regulator-always-on; regulator-boot-on; enable-active-high; - gpio = <&gpio 92 0>; /* gpio PL4 */ + gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; vin-supply = <&sys_3v3_reg>; }; @@ -491,7 +491,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio 152 0>; /* GPIO PT0 */ + gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; gpio-open-drain; vin-supply = <&vdd_5v0_reg>; }; @@ -515,10 +515,13 @@ nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&wm8903>; - nvidia,spkr-en-gpios = <&wm8903 2 0>; - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) + GPIO_ACTIVE_HIGH>; - clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>; + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 15ded605142a..d8783f0fae63 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -1,4 +1,8 @@ -/include/ "skeleton.dtsi" +#include <dt-bindings/clock/tegra30-car.h> +#include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include "skeleton.dtsi" / { compatible = "nvidia,tegra30"; @@ -15,9 +19,9 @@ host1x { compatible = "nvidia,tegra30-host1x", "simple-bus"; reg = <0x50000000 0x00024000>; - interrupts = <0 65 0x04 /* mpcore syncpt */ - 0 67 0x04>; /* mpcore general */ - clocks = <&tegra_car 28>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ + clocks = <&tegra_car TEGRA30_CLK_HOST1X>; #address-cells = <1>; #size-cells = <1>; @@ -27,36 +31,36 @@ mpe { compatible = "nvidia,tegra30-mpe"; reg = <0x54040000 0x00040000>; - interrupts = <0 68 0x04>; - clocks = <&tegra_car 60>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_MPE>; }; vi { compatible = "nvidia,tegra30-vi"; reg = <0x54080000 0x00040000>; - interrupts = <0 69 0x04>; - clocks = <&tegra_car 164>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_VI>; }; epp { compatible = "nvidia,tegra30-epp"; reg = <0x540c0000 0x00040000>; - interrupts = <0 70 0x04>; - clocks = <&tegra_car 19>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_EPP>; }; isp { compatible = "nvidia,tegra30-isp"; reg = <0x54100000 0x00040000>; - interrupts = <0 71 0x04>; - clocks = <&tegra_car 23>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_ISP>; }; gr2d { compatible = "nvidia,tegra30-gr2d"; reg = <0x54140000 0x00040000>; - interrupts = <0 72 0x04>; - clocks = <&tegra_car 21>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_GR2D>; }; gr3d { @@ -69,8 +73,9 @@ dc@54200000 { compatible = "nvidia,tegra30-dc"; reg = <0x54200000 0x00040000>; - interrupts = <0 73 0x04>; - clocks = <&tegra_car 27>, <&tegra_car 179>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_DISP1>, + <&tegra_car TEGRA30_CLK_PLL_P>; clock-names = "disp1", "parent"; rgb { @@ -81,8 +86,9 @@ dc@54240000 { compatible = "nvidia,tegra30-dc"; reg = <0x54240000 0x00040000>; - interrupts = <0 74 0x04>; - clocks = <&tegra_car 26>, <&tegra_car 179>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_DISP2>, + <&tegra_car TEGRA30_CLK_PLL_P>; clock-names = "disp2", "parent"; rgb { @@ -93,8 +99,9 @@ hdmi { compatible = "nvidia,tegra30-hdmi"; reg = <0x54280000 0x00040000>; - interrupts = <0 75 0x04>; - clocks = <&tegra_car 51>, <&tegra_car 189>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_HDMI>, + <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; clock-names = "hdmi", "parent"; status = "disabled"; }; @@ -102,15 +109,15 @@ tvo { compatible = "nvidia,tegra30-tvo"; reg = <0x542c0000 0x00040000>; - interrupts = <0 76 0x04>; - clocks = <&tegra_car 169>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_TVO>; status = "disabled"; }; dsi { compatible = "nvidia,tegra30-dsi"; reg = <0x54300000 0x00040000>; - clocks = <&tegra_car 48>; + clocks = <&tegra_car TEGRA30_CLK_DSIA>; status = "disabled"; }; }; @@ -118,8 +125,9 @@ timer@50004600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x50040600 0x20>; - interrupts = <1 13 0xf04>; - clocks = <&tegra_car 214>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&tegra_car TEGRA30_CLK_TWD>; }; intc: interrupt-controller { @@ -142,13 +150,13 @@ timer@60005000 { compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; reg = <0x60005000 0x400>; - interrupts = <0 0 0x04 - 0 1 0x04 - 0 41 0x04 - 0 42 0x04 - 0 121 0x04 - 0 122 0x04>; - clocks = <&tegra_car 5>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_TIMER>; }; tegra_car: clock { @@ -160,39 +168,39 @@ apbdma: dma { compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1400>; - interrupts = <0 104 0x04 - 0 105 0x04 - 0 106 0x04 - 0 107 0x04 - 0 108 0x04 - 0 109 0x04 - 0 110 0x04 - 0 111 0x04 - 0 112 0x04 - 0 113 0x04 - 0 114 0x04 - 0 115 0x04 - 0 116 0x04 - 0 117 0x04 - 0 118 0x04 - 0 119 0x04 - 0 128 0x04 - 0 129 0x04 - 0 130 0x04 - 0 131 0x04 - 0 132 0x04 - 0 133 0x04 - 0 134 0x04 - 0 135 0x04 - 0 136 0x04 - 0 137 0x04 - 0 138 0x04 - 0 139 0x04 - 0 140 0x04 - 0 141 0x04 - 0 142 0x04 - 0 143 0x04>; - clocks = <&tegra_car 34>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_APBDMA>; }; ahb: ahb { @@ -203,14 +211,14 @@ gpio: gpio { compatible = "nvidia,tegra30-gpio"; reg = <0x6000d000 0x1000>; - interrupts = <0 32 0x04 - 0 33 0x04 - 0 34 0x04 - 0 35 0x04 - 0 55 0x04 - 0 87 0x04 - 0 89 0x04 - 0 125 0x04>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; @@ -235,9 +243,9 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; reg-shift = <2>; - interrupts = <0 36 0x04>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 8>; - clocks = <&tegra_car 6>; + clocks = <&tegra_car TEGRA30_CLK_UARTA>; status = "disabled"; }; @@ -245,9 +253,9 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006040 0x40>; reg-shift = <2>; - interrupts = <0 37 0x04>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 9>; - clocks = <&tegra_car 160>; + clocks = <&tegra_car TEGRA30_CLK_UARTB>; status = "disabled"; }; @@ -255,9 +263,9 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006200 0x100>; reg-shift = <2>; - interrupts = <0 46 0x04>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 10>; - clocks = <&tegra_car 55>; + clocks = <&tegra_car TEGRA30_CLK_UARTC>; status = "disabled"; }; @@ -265,9 +273,9 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006300 0x100>; reg-shift = <2>; - interrupts = <0 90 0x04>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 19>; - clocks = <&tegra_car 65>; + clocks = <&tegra_car TEGRA30_CLK_UARTD>; status = "disabled"; }; @@ -275,9 +283,9 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006400 0x100>; reg-shift = <2>; - interrupts = <0 91 0x04>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 20>; - clocks = <&tegra_car 66>; + clocks = <&tegra_car TEGRA30_CLK_UARTE>; status = "disabled"; }; @@ -285,24 +293,25 @@ compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; - clocks = <&tegra_car 17>; + clocks = <&tegra_car TEGRA30_CLK_PWM>; status = "disabled"; }; rtc { compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; - interrupts = <0 2 0x04>; - clocks = <&tegra_car 4>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_RTC>; }; i2c@7000c000 { compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000c000 0x100>; - interrupts = <0 38 0x04>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 12>, <&tegra_car 182>; + clocks = <&tegra_car TEGRA30_CLK_I2C1>, + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -310,10 +319,11 @@ i2c@7000c400 { compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000c400 0x100>; - interrupts = <0 84 0x04>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 54>, <&tegra_car 182>; + clocks = <&tegra_car TEGRA30_CLK_I2C2>, + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -321,10 +331,11 @@ i2c@7000c500 { compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000c500 0x100>; - interrupts = <0 92 0x04>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 67>, <&tegra_car 182>; + clocks = <&tegra_car TEGRA30_CLK_I2C3>, + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -332,10 +343,11 @@ i2c@7000c700 { compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000c700 0x100>; - interrupts = <0 120 0x04>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 103>, <&tegra_car 182>; + clocks = <&tegra_car TEGRA30_CLK_I2C4>, + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -343,10 +355,11 @@ i2c@7000d000 { compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000d000 0x100>; - interrupts = <0 53 0x04>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 47>, <&tegra_car 182>; + clocks = <&tegra_car TEGRA30_CLK_I2C5>, + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -354,81 +367,81 @@ spi@7000d400 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000d400 0x200>; - interrupts = <0 59 0x04>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 15>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 41>; + clocks = <&tegra_car TEGRA30_CLK_SBC1>; status = "disabled"; }; spi@7000d600 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000d600 0x200>; - interrupts = <0 82 0x04>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 16>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 44>; + clocks = <&tegra_car TEGRA30_CLK_SBC2>; status = "disabled"; }; spi@7000d800 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000d800 0x200>; - interrupts = <0 83 0x04>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 46>; + clocks = <&tegra_car TEGRA30_CLK_SBC3>; status = "disabled"; }; spi@7000da00 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000da00 0x200>; - interrupts = <0 93 0x04>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 18>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 68>; + clocks = <&tegra_car TEGRA30_CLK_SBC4>; status = "disabled"; }; spi@7000dc00 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000dc00 0x200>; - interrupts = <0 94 0x04>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 27>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 104>; + clocks = <&tegra_car TEGRA30_CLK_SBC5>; status = "disabled"; }; spi@7000de00 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000de00 0x200>; - interrupts = <0 79 0x04>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 28>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 105>; + clocks = <&tegra_car TEGRA30_CLK_SBC6>; status = "disabled"; }; kbc { compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; reg = <0x7000e200 0x100>; - interrupts = <0 85 0x04>; - clocks = <&tegra_car 36>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_KBC>; status = "disabled"; }; pmc { compatible = "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>; - clocks = <&tegra_car 218>, <&clk32k_in>; + clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; }; @@ -438,7 +451,7 @@ 0x7000f03c 0x1b4 0x7000f200 0x028 0x7000f284 0x17c>; - interrupts = <0 77 0x04>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; }; iommu { @@ -455,12 +468,19 @@ compatible = "nvidia,tegra30-ahub"; reg = <0x70080000 0x200 0x70080200 0x100>; - interrupts = <0 103 0x04>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 1>; - clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>, - <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>, - <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>, - <&tegra_car 110>, <&tegra_car 162>; + clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, + <&tegra_car TEGRA30_CLK_APBIF>, + <&tegra_car TEGRA30_CLK_I2S0>, + <&tegra_car TEGRA30_CLK_I2S1>, + <&tegra_car TEGRA30_CLK_I2S2>, + <&tegra_car TEGRA30_CLK_I2S3>, + <&tegra_car TEGRA30_CLK_I2S4>, + <&tegra_car TEGRA30_CLK_DAM0>, + <&tegra_car TEGRA30_CLK_DAM1>, + <&tegra_car TEGRA30_CLK_DAM2>, + <&tegra_car TEGRA30_CLK_SPDIF_IN>; clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", "i2s3", "i2s4", "dam0", "dam1", "dam2", "spdif_in"; @@ -472,7 +492,7 @@ compatible = "nvidia,tegra30-i2s"; reg = <0x70080300 0x100>; nvidia,ahub-cif-ids = <4 4>; - clocks = <&tegra_car 30>; + clocks = <&tegra_car TEGRA30_CLK_I2S0>; status = "disabled"; }; @@ -480,7 +500,7 @@ compatible = "nvidia,tegra30-i2s"; reg = <0x70080400 0x100>; nvidia,ahub-cif-ids = <5 5>; - clocks = <&tegra_car 11>; + clocks = <&tegra_car TEGRA30_CLK_I2S1>; status = "disabled"; }; @@ -488,7 +508,7 @@ compatible = "nvidia,tegra30-i2s"; reg = <0x70080500 0x100>; nvidia,ahub-cif-ids = <6 6>; - clocks = <&tegra_car 18>; + clocks = <&tegra_car TEGRA30_CLK_I2S2>; status = "disabled"; }; @@ -496,7 +516,7 @@ compatible = "nvidia,tegra30-i2s"; reg = <0x70080600 0x100>; nvidia,ahub-cif-ids = <7 7>; - clocks = <&tegra_car 101>; + clocks = <&tegra_car TEGRA30_CLK_I2S3>; status = "disabled"; }; @@ -504,7 +524,7 @@ compatible = "nvidia,tegra30-i2s"; reg = <0x70080700 0x100>; nvidia,ahub-cif-ids = <8 8>; - clocks = <&tegra_car 102>; + clocks = <&tegra_car TEGRA30_CLK_I2S4>; status = "disabled"; }; }; @@ -512,32 +532,32 @@ sdhci@78000000 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000000 0x200>; - interrupts = <0 14 0x04>; - clocks = <&tegra_car 14>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; status = "disabled"; }; sdhci@78000200 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000200 0x200>; - interrupts = <0 15 0x04>; - clocks = <&tegra_car 9>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; status = "disabled"; }; sdhci@78000400 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000400 0x200>; - interrupts = <0 19 0x04>; - clocks = <&tegra_car 69>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; status = "disabled"; }; sdhci@78000600 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000600 0x200>; - interrupts = <0 31 0x04>; - clocks = <&tegra_car 15>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; status = "disabled"; }; @@ -572,9 +592,9 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 144 0x04 - 0 145 0x04 - 0 146 0x04 - 0 147 0x04>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm/boot/dts/tny_a9260.dts b/arch/arm/boot/dts/tny_a9260.dts index 367a16dcd5ef..dabe232216b4 100644 --- a/arch/arm/boot/dts/tny_a9260.dts +++ b/arch/arm/boot/dts/tny_a9260.dts @@ -6,8 +6,8 @@ * Licensed under GPLv2. */ /dts-v1/; -/include/ "at91sam9260.dtsi" -/include/ "tny_a9260_common.dtsi" +#include "at91sam9260.dtsi" +#include "tny_a9260_common.dtsi" / { model = "Calao TNY A9260"; diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts index dee9c571306b..0751a6a979a8 100644 --- a/arch/arm/boot/dts/tny_a9263.dts +++ b/arch/arm/boot/dts/tny_a9263.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2 only */ /dts-v1/; -/include/ "at91sam9263.dtsi" +#include "at91sam9263.dtsi" / { model = "Calao TNY A9263"; @@ -38,7 +38,7 @@ }; usb1: gadget@fff78000 { - atmel,vbus-gpio = <&pioB 11 0>; + atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/tny_a9g20.dts b/arch/arm/boot/dts/tny_a9g20.dts index e1ab64c72dba..8456d70bb42b 100644 --- a/arch/arm/boot/dts/tny_a9g20.dts +++ b/arch/arm/boot/dts/tny_a9g20.dts @@ -6,8 +6,8 @@ * Licensed under GPLv2. */ /dts-v1/; -/include/ "at91sam9g20.dtsi" -/include/ "tny_a9260_common.dtsi" +#include "at91sam9g20.dtsi" +#include "tny_a9260_common.dtsi" / { model = "Calao TNY A9G20"; diff --git a/arch/arm/boot/dts/twl4030_omap3.dtsi b/arch/arm/boot/dts/twl4030_omap3.dtsi new file mode 100644 index 000000000000..c353ef0a6ac7 --- /dev/null +++ b/arch/arm/boot/dts/twl4030_omap3.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2013 Linaro, Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&twl { + pinctrl-names = "default"; + pinctrl-0 = <&twl4030_pins>; +}; + +&omap3_pmx_core { + /* + * On most OMAP3 platforms, the twl4030 IRQ line is connected + * to the SYS_NIRQ line on OMAP. Therefore, configure the + * defaults for the SYS_NIRQ pin here. + */ + twl4030_pins: pinmux_twl4030_pins { + pinctrl-single,pins = < + 0x1b0 (PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ + >; + }; +}; diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts index 296216058c11..de0c24f5210a 100644 --- a/arch/arm/boot/dts/usb_a9260.dts +++ b/arch/arm/boot/dts/usb_a9260.dts @@ -6,8 +6,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9260.dtsi" -/include/ "usb_a9260_common.dtsi" +#include "at91sam9260.dtsi" +#include "usb_a9260_common.dtsi" / { model = "Calao USB A9260"; @@ -20,4 +20,13 @@ memory { reg = <0x20000000 0x4000000>; }; + + ahb { + apb { + shdwc@fffffd10 { + atmel,wakeup-counter = <10>; + atmel,wakeup-rtt-timer; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi index e70d229baef5..285977682cf3 100644 --- a/arch/arm/boot/dts/usb_a9260_common.dtsi +++ b/arch/arm/boot/dts/usb_a9260_common.dtsi @@ -30,7 +30,7 @@ }; usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 0>; + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; }; @@ -93,7 +93,7 @@ user_led { label = "user_led"; - gpios = <&pioB 21 1>; + gpios = <&pioB 21 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; }; @@ -105,7 +105,7 @@ user_pb { label = "user_pb"; - gpios = <&pioB 10 1>; + gpios = <&pioB 10 GPIO_ACTIVE_LOW>; linux,code = <28>; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index 6fe05ccb6203..290e60383baf 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2 only */ /dts-v1/; -/include/ "at91sam9263.dtsi" +#include "at91sam9263.dtsi" / { model = "Calao USB A9263"; @@ -43,10 +43,24 @@ }; usb1: gadget@fff78000 { - atmel,vbus-gpio = <&pioB 11 0>; + atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; status = "okay"; }; + spi0: spi@fffa4000 { + cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + reg = <0>; + spi-max-frequency = <15000000>; + }; + }; + + shdwc@fffffd10 { + atmel,wakeup-counter = <10>; + atmel,wakeup-rtt-timer; + }; }; nand0: nand@40000000 { @@ -107,7 +121,7 @@ user_led { label = "user_led"; - gpios = <&pioB 21 0>; + gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; @@ -119,7 +133,7 @@ user_pb { label = "user_pb"; - gpios = <&pioB 10 1>; + gpios = <&pioB 10 GPIO_ACTIVE_LOW>; linux,code = <28>; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi index ad3eca17c436..5b0ffc1a0b24 100644 --- a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi +++ b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi @@ -28,39 +28,39 @@ user_led1 { label = "user_led1"; - gpios = <&pioB 20 1>; + gpios = <&pioB 20 GPIO_ACTIVE_LOW>; }; /* * led already used by mother board but active as high * user_led2 { * label = "user_led2"; -* gpios = <&pioB 21 1>; +* gpios = <&pioB 21 GPIO_ACTIVE_LOW>; * }; */ user_led3 { label = "user_led3"; - gpios = <&pioB 22 1>; + gpios = <&pioB 22 GPIO_ACTIVE_LOW>; }; user_led4 { label = "user_led4"; - gpios = <&pioB 23 1>; + gpios = <&pioB 23 GPIO_ACTIVE_LOW>; }; red { label = "red"; - gpios = <&pioB 24 1>; + gpios = <&pioB 24 GPIO_ACTIVE_LOW>; }; orange { label = "orange"; - gpios = <&pioB 30 1>; + gpios = <&pioB 30 GPIO_ACTIVE_LOW>; }; green { label = "green"; - gpios = <&pioB 31 1>; + gpios = <&pioB 31 GPIO_ACTIVE_LOW>; }; }; @@ -71,25 +71,25 @@ user_pb1 { label = "user_pb1"; - gpios = <&pioB 25 1>; + gpios = <&pioB 25 GPIO_ACTIVE_LOW>; linux,code = <0x100>; }; user_pb2 { label = "user_pb2"; - gpios = <&pioB 13 1>; + gpios = <&pioB 13 GPIO_ACTIVE_LOW>; linux,code = <0x101>; }; user_pb3 { label = "user_pb3"; - gpios = <&pioA 26 1>; + gpios = <&pioA 26 GPIO_ACTIVE_LOW>; linux,code = <0x102>; }; user_pb4 { label = "user_pb4"; - gpios = <&pioC 9 1>; + gpios = <&pioC 9 GPIO_ACTIVE_LOW>; linux,code = <0x103>; }; }; diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts index 2dacb16ce4ae..ec77cf8f9695 100644 --- a/arch/arm/boot/dts/usb_a9g20.dts +++ b/arch/arm/boot/dts/usb_a9g20.dts @@ -6,25 +6,9 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9g20.dtsi" -/include/ "usb_a9260_common.dtsi" +#include "usb_a9g20_common.dtsi" / { model = "Calao USB A9G20"; compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - i2c@0 { - rv3029c2@56 { - compatible = "rv3029c2"; - reg = <0x56>; - }; - }; }; diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/usb_a9g20_common.dtsi new file mode 100644 index 000000000000..0b3b36182fe5 --- /dev/null +++ b/arch/arm/boot/dts/usb_a9g20_common.dtsi @@ -0,0 +1,27 @@ +/* + * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board + * + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Licensed under GPLv2 or later. + */ + +#include "at91sam9g20.dtsi" +#include "usb_a9260_common.dtsi" + +/ { + chosen { + bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + i2c@0 { + rv3029c2@56 { + compatible = "rv3029c2"; + reg = <0x56>; + }; + }; +}; diff --git a/arch/arm/boot/dts/usb_a9g20_lpw.dts b/arch/arm/boot/dts/usb_a9g20_lpw.dts new file mode 100644 index 000000000000..f8cb1b9a01c5 --- /dev/null +++ b/arch/arm/boot/dts/usb_a9g20_lpw.dts @@ -0,0 +1,31 @@ +/* + * usb_a9g20_lpw.dts - Device Tree file for Caloa USB A9G20 Low Power board + * + * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "usb_a9g20_common.dtsi" + +/ { + model = "Calao USB A9G20 Low Power"; + compatible = "calao,usb-a9g20-lpw", "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; + + ahb { + apb { + spi1: spi@fffcc000 { + cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + mmc-slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3200 3400>; + spi-max-frequency = <25000000>; + interrupt-parent = <&pioC>; + interrupts = <4 IRQ_TYPE_EDGE_BOTH>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/vf610-pinfunc.h b/arch/arm/boot/dts/vf610-pinfunc.h new file mode 100644 index 000000000000..1ee681f7ce2f --- /dev/null +++ b/arch/arm/boot/dts/vf610-pinfunc.h @@ -0,0 +1,810 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_VF610_PINFUNC_H +#define __DTS_VF610_PINFUNC_H + +/* + * The pin function ID for VF610 is a tuple of: + * <mux_reg input_reg mux_mode input_val> + */ + +#define ALT0 0x0 +#define ALT1 0x1 +#define ALT2 0x2 +#define ALT3 0x3 +#define ALT4 0x4 +#define ALT5 0x5 +#define ALT6 0x6 +#define ALT7 0x7 + + +#define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 +#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 +#define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0 +#define VF610_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0 +#define VF610_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0 +#define VF610_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0 +#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0 +#define VF610_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0 +#define VF610_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0 +#define VF610_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0 +#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0 +#define VF610_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0 +#define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1 +#define VF610_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0 +#define VF610_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0 +#define VF610_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0 +#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0 +#define VF610_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0 +#define VF610_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0 +#define VF610_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0 +#define VF610_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0 +#define VF610_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0 +#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0 +#define VF610_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0 +#define VF610_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0 +#define VF610_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0 +#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0 +#define VF610_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1 +#define VF610_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0 +#define VF610_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0 +#define VF610_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0 +#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0 +#define VF610_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0 +#define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0 +#define VF610_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0 +#define VF610_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0 +#define VF610_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0 +#define VF610_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0 +#define VF610_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0 +#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0 +#define VF610_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0 +#define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0 +#define VF610_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0 +#define VF610_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0 +#define VF610_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0 +#define VF610_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0 +#define VF610_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0 +#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0 +#define VF610_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0 +#define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0 +#define VF610_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0 +#define VF610_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0 +#define VF610_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0 +#define VF610_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0 +#define VF610_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0 +#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0 +#define VF610_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0 +#define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0 +#define VF610_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0 +#define VF610_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0 +#define VF610_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0 +#define VF610_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0 +#define VF610_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0 +#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0 +#define VF610_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0 +#define VF610_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0 +#define VF610_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0 +#define VF610_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0 +#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0 +#define VF610_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0 +#define VF610_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0 +#define VF610_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0 +#define VF610_PAD_PTA22__GPIO_12 0x030 0x000 ALT0 0x0 +#define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0 +#define VF610_PAD_PTA22__SAI2_RX_DATA 0x030 0x368 ALT5 0x0 +#define VF610_PAD_PTA22__I2C2_SCL 0x030 0x34C ALT6 0x0 +#define VF610_PAD_PTA22__DCU1_TAG 0x030 0x000 ALT7 0x0 +#define VF610_PAD_PTA23__GPIO_13 0x034 0x000 ALT0 0x0 +#define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0 +#define VF610_PAD_PTA23__SAI2_RX_SYNC 0x034 0x36C ALT5 0x0 +#define VF610_PAD_PTA23__I2C2_SDA 0x034 0x350 ALT6 0x0 +#define VF610_PAD_PTA23__DCU1_DE 0x034 0x000 ALT7 0x0 +#define VF610_PAD_PTA24__GPIO_14 0x038 0x000 ALT0 0x0 +#define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0 +#define VF610_PAD_PTA24__USB1_VBUS_EN 0x038 0x000 ALT2 0x0 +#define VF610_PAD_PTA24__ESDHC1_CLK 0x038 0x000 ALT5 0x0 +#define VF610_PAD_PTA24__DCU1_TCON4 0x038 0x000 ALT6 0x0 +#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL 0x038 0x000 ALT7 0x0 +#define VF610_PAD_PTA25__GPIO_15 0x03C 0x000 ALT0 0x0 +#define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0 +#define VF610_PAD_PTA25__USB1_VBUS_OC 0x03C 0x000 ALT2 0x0 +#define VF610_PAD_PTA25__ESDHC1_CMD 0x03C 0x000 ALT5 0x0 +#define VF610_PAD_PTA25__DCU1_TCON5 0x03C 0x000 ALT6 0x0 +#define VF610_PAD_PTA26__GPIO_16 0x040 0x000 ALT0 0x0 +#define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0 +#define VF610_PAD_PTA26__SAI3_TX_BCLK 0x040 0x000 ALT2 0x0 +#define VF610_PAD_PTA26__ESDHC1_DAT0 0x040 0x000 ALT5 0x0 +#define VF610_PAD_PTA26__DCU1_TCON6 0x040 0x000 ALT6 0x0 +#define VF610_PAD_PTA27__GPIO_17 0x044 0x000 ALT0 0x0 +#define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0 +#define VF610_PAD_PTA27__SAI3_RX_BCLK 0x044 0x000 ALT2 0x0 +#define VF610_PAD_PTA27__ESDHC1_DAT1 0x044 0x000 ALT5 0x0 +#define VF610_PAD_PTA27__DCU1_TCON7 0x044 0x000 ALT6 0x0 +#define VF610_PAD_PTA28__GPIO_18 0x048 0x000 ALT0 0x0 +#define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0 +#define VF610_PAD_PTA28__SAI3_RX_DATA 0x048 0x000 ALT2 0x0 +#define VF610_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0 +#define VF610_PAD_PTA28__UART4_TX 0x048 0x000 ALT4 0x0 +#define VF610_PAD_PTA28__ESDHC1_DATA2 0x048 0x000 ALT5 0x0 +#define VF610_PAD_PTA28__DCU1_TCON8 0x048 0x000 ALT6 0x0 +#define VF610_PAD_PTA29__GPIO_19 0x04C 0x000 ALT0 0x0 +#define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0 +#define VF610_PAD_PTA29__SAI3_TX_DATA 0x04C 0x000 ALT2 0x0 +#define VF610_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0 +#define VF610_PAD_PTA29__UART4_RX 0x04C 0x000 ALT4 0x0 +#define VF610_PAD_PTA29__ESDHC1_DAT3 0x04C 0x000 ALT5 0x0 +#define VF610_PAD_PTA29__DCU1_TCON9 0x04C 0x000 ALT6 0x0 +#define VF610_PAD_PTA30__GPIO_20 0x050 0x000 ALT0 0x0 +#define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0 +#define VF610_PAD_PTA30__SAI3_RX_SYNC 0x050 0x000 ALT2 0x0 +#define VF610_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0 +#define VF610_PAD_PTA30__UART4_RTS 0x050 0x000 ALT4 0x0 +#define VF610_PAD_PTA30__I2C3_SCL 0x050 0x000 ALT5 0x0 +#define VF610_PAD_PTA30__UART3_TX 0x050 0x394 ALT7 0x1 +#define VF610_PAD_PTA31__GPIO_21 0x054 0x000 ALT0 0x0 +#define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0 +#define VF610_PAD_PTA31__SAI3_TX_SYNC 0x054 0x000 ALT2 0x0 +#define VF610_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0 +#define VF610_PAD_PTA31__UART4_CTS 0x054 0x000 ALT4 0x0 +#define VF610_PAD_PTA31__I2C3_SDA 0x054 0x000 ALT5 0x0 +#define VF610_PAD_PTA31__UART3_RX 0x054 0x390 ALT7 0x1 +#define VF610_PAD_PTB0__GPIO_22 0x058 0x000 ALT0 0x0 +#define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0 +#define VF610_PAD_PTB0__ADC0_SE2 0x058 0x000 ALT2 0x0 +#define VF610_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0 +#define VF610_PAD_PTB0__LCD34 0x058 0x000 ALT4 0x0 +#define VF610_PAD_PTB0__SAI2_RX_BCLK 0x058 0x364 ALT5 0x1 +#define VF610_PAD_PTB0__VIU_DATA18 0x058 0x000 ALT6 0x0 +#define VF610_PAD_PTB0__QSPI1_A_QPCS0 0x058 0x000 ALT7 0x0 +#define VF610_PAD_PTB1__GPIO_23 0x05C 0x000 ALT0 0x0 +#define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0 +#define VF610_PAD_PTB1__ADC0_SE3 0x05C 0x000 ALT2 0x0 +#define VF610_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0 +#define VF610_PAD_PTB1__LCD35 0x05C 0x000 ALT4 0x0 +#define VF610_PAD_PTB1__SAI2_RX_DATA 0x05C 0x368 ALT5 0x1 +#define VF610_PAD_PTB1__VIU_DATA19 0x05C 0x000 ALT6 0x0 +#define VF610_PAD_PTB1__QSPI1_A_DATA3 0x05C 0x000 ALT7 0x0 +#define VF610_PAD_PTB2__GPIO_24 0x060 0x000 ALT0 0x0 +#define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0 +#define VF610_PAD_PTB2__ADC1_SE2 0x060 0x000 ALT2 0x0 +#define VF610_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0 +#define VF610_PAD_PTB2__LCD36 0x060 0x000 ALT4 0x0 +#define VF610_PAD_PTB2__SAI2_RX_SYNC 0x060 0x36C ALT5 0x1 +#define VF610_PAD_PTB2__VIDEO_IN0_DATA20 0x060 0x000 ALT6 0x0 +#define VF610_PAD_PTB2__QSPI1_A_DATA2 0x060 0x000 ALT7 0x0 +#define VF610_PAD_PTB3__GPIO_25 0x064 0x000 ALT0 0x0 +#define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0 +#define VF610_PAD_PTB3__ADC1_SE3 0x064 0x000 ALT2 0x0 +#define VF610_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0 +#define VF610_PAD_PTB3__LCD37 0x064 0x000 ALT4 0x0 +#define VF610_PAD_PTB3__VIU_DATA21 0x064 0x000 ALT6 0x0 +#define VF610_PAD_PTB3__QSPI1_A_DATA1 0x064 0x000 ALT7 0x0 +#define VF610_PAD_PTB4__GPIO_26 0x068 0x000 ALT0 0x0 +#define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0 +#define VF610_PAD_PTB4__UART1_TX 0x068 0x380 ALT2 0x0 +#define VF610_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0 +#define VF610_PAD_PTB4__LCD38 0x068 0x000 ALT4 0x0 +#define VF610_PAD_PTB4__VIU_FID 0x068 0x3A8 ALT5 0x0 +#define VF610_PAD_PTB4__VIU_DATA22 0x068 0x000 ALT6 0x0 +#define VF610_PAD_PTB4__QSPI1_A_DATA0 0x068 0x000 ALT7 0x0 +#define VF610_PAD_PTB5__GPIO_27 0x06C 0x000 ALT0 0x0 +#define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0 +#define VF610_PAD_PTB5__UART1_RX 0x06C 0x37C ALT2 0x0 +#define VF610_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0 +#define VF610_PAD_PTB5__LCD39 0x06C 0x000 ALT4 0x0 +#define VF610_PAD_PTB5__VIU_DE 0x06C 0x3A4 ALT5 0x0 +#define VF610_PAD_PTB5__QSPI1_A_DQS 0x06C 0x000 ALT7 0x0 +#define VF610_PAD_PTB6__GPIO_28 0x070 0x000 ALT0 0x0 +#define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0 +#define VF610_PAD_PTB6__UART1_RTS 0x070 0x000 ALT2 0x0 +#define VF610_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0 +#define VF610_PAD_PTB6__LCD_LCD40 0x070 0x000 ALT4 0x0 +#define VF610_PAD_PTB6__FB_CLKOUT 0x070 0x000 ALT5 0x0 +#define VF610_PAD_PTB6__VIU_HSYNC 0x070 0x000 ALT6 0x0 +#define VF610_PAD_PTB6__UART2_TX 0x070 0x38C ALT7 0x0 +#define VF610_PAD_PTB7__GPIO_29 0x074 0x000 ALT0 0x0 +#define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0 +#define VF610_PAD_PTB7__UART1_CTS 0x074 0x378 ALT2 0x0 +#define VF610_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0 +#define VF610_PAD_PTB7__LCD41 0x074 0x000 ALT4 0x0 +#define VF610_PAD_PTB7__VIU_VSYNC 0x074 0x000 ALT6 0x0 +#define VF610_PAD_PTB7__UART2_RX 0x074 0x388 ALT7 0x0 +#define VF610_PAD_PTB8__GPIO_30 0x078 0x000 ALT0 0x0 +#define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0 +#define VF610_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1 +#define VF610_PAD_PTB8__VIU_DE 0x078 0x3A4 ALT5 0x1 +#define VF610_PAD_PTB8__DCU1_R6 0x078 0x000 ALT7 0x0 +#define VF610_PAD_PTB9__GPIO_31 0x07C 0x000 ALT0 0x0 +#define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0 +#define VF610_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1 +#define VF610_PAD_PTB9__DCU1_R7 0x07C 0x000 ALT7 0x0 +#define VF610_PAD_PTB10__GPIO_32 0x080 0x000 ALT0 0x0 +#define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0 +#define VF610_PAD_PTB10__DCU0_TCON4 0x080 0x000 ALT4 0x0 +#define VF610_PAD_PTB10__VIU_DE 0x080 0x3A4 ALT5 0x2 +#define VF610_PAD_PTB10__CKO1 0x080 0x000 ALT6 0x0 +#define VF610_PAD_PTB10__ENET_TS_CLKIN 0x080 0x2F4 ALT7 0x1 +#define VF610_PAD_PTB11__GPIO_33 0x084 0x000 ALT0 0x0 +#define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0 +#define VF610_PAD_PTB11__DCU0_TCON5 0x084 0x000 ALT4 0x0 +#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B 0x084 0x000 ALT5 0x0 +#define VF610_PAD_PTB11__CKO2 0x084 0x000 ALT6 0x0 +#define VF610_PAD_PTB11_ENET0_1588_TMR0 0x084 0x304 ALT7 0x0 +#define VF610_PAD_PTB12__GPIO_34 0x088 0x000 ALT0 0x0 +#define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0 +#define VF610_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0 +#define VF610_PAD_PTB12__DCU0_TCON6 0x088 0x000 ALT4 0x0 +#define VF610_PAD_PTB12__FB_AD1 0x088 0x000 ALT5 0x0 +#define VF610_PAD_PTB12__NMI 0x088 0x000 ALT6 0x0 +#define VF610_PAD_PTB12__ENET0_1588_TMR1 0x088 0x308 ALT7 0x0 +#define VF610_PAD_PTB13__GPIO_35 0x08C 0x000 ALT0 0x0 +#define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0 +#define VF610_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0 +#define VF610_PAD_PTB13__DCU0_TCON7 0x08C 0x000 ALT4 0x0 +#define VF610_PAD_PTB13__FB_AD0 0x08C 0x000 ALT5 0x0 +#define VF610_PAD_PTB13__TRACE_CTL 0x08C 0x000 ALT6 0x0 +#define VF610_PAD_PTB14__GPIO_36 0x090 0x000 ALT0 0x0 +#define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0 +#define VF610_PAD_PTB14__I2C0_SCL 0x090 0x33C ALT2 0x1 +#define VF610_PAD_PTB14__DCU0_TCON8 0x090 0x000 ALT4 0x0 +#define VF610_PAD_PTB14__DCU1_PCLK 0x090 0x000 ALT7 0x0 +#define VF610_PAD_PTB15__GPIO_37 0x094 0x000 ALT0 0x0 +#define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0 +#define VF610_PAD_PTB15__I2C0_SDA 0x094 0x340 ALT2 0x1 +#define VF610_PAD_PTB15__DCU0_TCON9 0x094 0x000 ALT4 0x0 +#define VF610_PAD_PTB15__VIU_PIX_CLK 0x094 0x3AC ALT7 0x0 +#define VF610_PAD_PTB16__GPIO_38 0x098 0x000 ALT0 0x0 +#define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0 +#define VF610_PAD_PTB16__I2C1_SCL 0x098 0x344 ALT2 0x1 +#define VF610_PAD_PTB16__DCU0_TCON10 0x098 0x000 ALT4 0x0 +#define VF610_PAD_PTB17__GPIO_39 0x09C 0x000 ALT0 0x0 +#define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0 +#define VF610_PAD_PTB17__I2C1_SDA 0x09C 0x348 ALT2 0x1 +#define VF610_PAD_PTB17__DCU0_TCON11 0x09C 0x000 ALT4 0x0 +#define VF610_PAD_PTB18__GPIO_40 0x0A0 0x000 ALT0 0x0 +#define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0 +#define VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x0A0 0x2EC ALT2 0x2 +#define VF610_PAD_PTB18__VIU_DATA9 0x0A0 0x000 ALT6 0x0 +#define VF610_PAD_PTB19__GPIO_41 0x0A4 0x000 ALT0 0x0 +#define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0 +#define VF610_PAD_PTB19__VIU_DATA10 0x0A4 0x000 ALT6 0x0 +#define VF610_PAD_PTB20__GPIO_42 0x0A8 0x000 ALT0 0x0 +#define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0 +#define VF610_PAD_PTB20__LCD42 0x0A8 0x000 ALT4 0x0 +#define VF610_PAD_PTB20__VIU_DATA11 0x0A8 0x000 ALT6 0x0 +#define VF610_PAD_PTB21__GPIO_43 0x0AC 0x000 ALT0 0x0 +#define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0 +#define VF610_PAD_PTB21__LCD43 0x0AC 0x000 ALT4 0x0 +#define VF610_PAD_PTB21__VIU_DATA12 0x0AC 0x000 ALT6 0x0 +#define VF610_PAD_PTB21__DCU1_PCLK 0x0AC 0x000 ALT7 0x0 +#define VF610_PAD_PTB22__GPIO_44 0x0B0 0x000 ALT0 0x0 +#define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0 +#define VF610_PAD_PTB22__VLCD 0x0B0 0x000 ALT4 0x0 +#define VF610_PAD_PTB22__VIU_FID 0x0B0 0x3A8 ALT5 0x1 +#define VF610_PAD_PTC0__GPIO_45 0x0B4 0x000 ALT0 0x0 +#define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0 +#define VF610_PAD_PTC0__FTM1_CH0 0x0B4 0x32C ALT2 0x1 +#define VF610_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0 +#define VF610_PAD_PTC0__ESAI_SCKT 0x0B4 0x310 ALT4 0x0 +#define VF610_PAD_PTC0__ESDHC0_CLK 0x0B4 0x000 ALT5 0x0 +#define VF610_PAD_PTC0__VIU_DATA0 0x0B4 0x000 ALT6 0x0 +#define VF610_PAD_PTC0__SRC_RCON18 0x0B4 0x398 ALT7 0x0 +#define VF610_PAD_PTC1__GPIO_46 0x0B8 0x000 ALT0 0x0 +#define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0 +#define VF610_PAD_PTC1__FTM1_CH1 0x0B8 0x330 ALT2 0x1 +#define VF610_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0 +#define VF610_PAD_PTC1__ESAI_FST 0x0B8 0x30C ALT4 0x0 +#define VF610_PAD_PTC1__ESDHC0_CMD 0x0B8 0x000 ALT5 0x0 +#define VF610_PAD_PTC1__VIU_DATA1 0x0B8 0x000 ALT6 0x0 +#define VF610_PAD_PTC1__SRC_RCON19 0x0B8 0x39C ALT7 0x0 +#define VF610_PAD_PTC2__GPIO_47 0x0BC 0x000 ALT0 0x0 +#define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0 +#define VF610_PAD_PTC2__UART1_TX 0x0BC 0x380 ALT2 0x1 +#define VF610_PAD_PTC2__ESAI_SDO0 0x0BC 0x314 ALT4 0x0 +#define VF610_PAD_PTC2__ESDHC0_DAT0 0x0BC 0x000 ALT5 0x0 +#define VF610_PAD_PTC2__VIU_DATA2 0x0BC 0x000 ALT6 0x0 +#define VF610_PAD_PTC2__SRC_RCON20 0x0BC 0x3A0 ALT7 0x0 +#define VF610_PAD_PTC3__GPIO_48 0x0C0 0x000 ALT0 0x0 +#define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0 +#define VF610_PAD_PTC3__UART1_RX 0x0C0 0x37C ALT2 0x1 +#define VF610_PAD_PTC3__ESAI_SDO1 0x0C0 0x318 ALT4 0x0 +#define VF610_PAD_PTC3__ESDHC0_DAT1 0x0C0 0x000 ALT5 0x0 +#define VF610_PAD_PTC3__VIU_DATA3 0x0C0 0x000 ALT6 0x0 +#define VF610_PAD_PTC3__DCU0_R0 0x0C0 0x000 ALT7 0x0 +#define VF610_PAD_PTC4__GPIO_49 0x0C4 0x000 ALT0 0x0 +#define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0 +#define VF610_PAD_PTC4__UART1_RTS 0x0C4 0x000 ALT2 0x0 +#define VF610_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0 +#define VF610_PAD_PTC4__ESAI_SDO2 0x0C4 0x31C ALT4 0x0 +#define VF610_PAD_PTC4__ESDHC0_DAT2 0x0C4 0x000 ALT5 0x0 +#define VF610_PAD_PTC4__VIU_DATA4 0x0C4 0x000 ALT6 0x0 +#define VF610_PAD_PTC4__DCU0_R1 0x0C4 0x000 ALT7 0x0 +#define VF610_PAD_PTC5__GPIO_50 0x0C8 0x000 ALT0 0x0 +#define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0 +#define VF610_PAD_PTC5__UART1_CTS 0x0C8 0x378 ALT2 0x1 +#define VF610_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0 +#define VF610_PAD_PTC5__ESAI_SDO3 0x0C8 0x320 ALT4 0x0 +#define VF610_PAD_PTC5__ESDHC0_DAT3 0x0C8 0x000 ALT5 0x0 +#define VF610_PAD_PTC5__VIU_DATA5 0x0C8 0x000 ALT6 0x0 +#define VF610_PAD_PTC5__DCU0_G0 0x0C8 0x000 ALT7 0x0 +#define VF610_PAD_PTC6__GPIO_51 0x0CC 0x000 ALT0 0x0 +#define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0 +#define VF610_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0 +#define VF610_PAD_PTC6__ESAI_SDI0 0x0CC 0x328 ALT4 0x0 +#define VF610_PAD_PTC6__ESDHC0_WP 0x0CC 0x000 ALT5 0x0 +#define VF610_PAD_PTC6__VIU_DATA6 0x0CC 0x000 ALT6 0x0 +#define VF610_PAD_PTC6__DCU0_G1 0x0CC 0x000 ALT7 0x0 +#define VF610_PAD_PTC7__GPIO_52 0x0D0 0x000 ALT0 0x0 +#define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0 +#define VF610_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0 +#define VF610_PAD_PTC7__ESAI_SDI1 0x0D0 0x324 ALT4 0x0 +#define VF610_PAD_PTC7__VIU_DATA7 0x0D0 0x000 ALT6 0x0 +#define VF610_PAD_PTC7__DCU0_B0 0x0D0 0x000 ALT7 0x0 +#define VF610_PAD_PTC8__GPIO_53 0x0D4 0x000 ALT0 0x0 +#define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0 +#define VF610_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0 +#define VF610_PAD_PTC8__VIU_DATA8 0x0D4 0x000 ALT6 0x0 +#define VF610_PAD_PTC8__DCU0_B1 0x0D4 0x000 ALT7 0x0 +#define VF610_PAD_PTC9__GPIO_54 0x0D8 0x000 ALT0 0x0 +#define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0 +#define VF610_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1 +#define VF610_PAD_PTC9__MLB_CLK 0x0D8 0x354 ALT6 0x1 +#define VF610_PAD_PTC9__DEBUG_OUT0 0x0D8 0x000 ALT7 0x0 +#define VF610_PAD_PTC10__GPIO_55 0x0DC 0x000 ALT0 0x0 +#define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0 +#define VF610_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1 +#define VF610_PAD_PTC10__MLB_SIGNAL 0x0DC 0x35C ALT6 0x1 +#define VF610_PAD_PTC10__DEBUG_OUT1 0x0DC 0x000 ALT7 0x0 +#define VF610_PAD_PTC11__GPIO_56 0x0E0 0x000 ALT0 0x0 +#define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0 +#define VF610_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1 +#define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1 +#define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0 +#define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0 +#define VF610_PAD_PTC12__ENET_RMII_RXD1 0x0E4 0x000 ALT1 0x0 +#define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1 +#define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1 +#define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0 +#define VF610_PAD_PTC13__GPIO_58 0x0E8 0x000 ALT0 0x0 +#define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0 +#define VF610_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1 +#define VF610_PAD_PTC13__SAI2_RX_BCLK 0x0E8 0x364 ALT5 0x2 +#define VF610_PAD_PTC13__DEBUG_OUT4 0x0E8 0x000 ALT7 0x0 +#define VF610_PAD_PTC14__GPIO_59 0x0EC 0x000 ALT0 0x0 +#define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0 +#define VF610_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1 +#define VF610_PAD_PTC14__UART5_TX 0x0EC 0x000 ALT4 0x0 +#define VF610_PAD_PTC14__SAI2_RX_DATA 0x0EC 0x368 ALT5 0x2 +#define VF610_PAD_PTC14__ADC0_SE6 0x0EC 0x000 ALT6 0x0 +#define VF610_PAD_PTC14__DEBUG_OUT5 0x0EC 0x000 ALT7 0x0 +#define VF610_PAD_PTC15__GPIO_60 0x0F0 0x000 ALT0 0x0 +#define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0 +#define VF610_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1 +#define VF610_PAD_PTC15__UART5_RX 0x0F0 0x000 ALT4 0x0 +#define VF610_PAD_PTC15__SAI2_TX_DATA 0x0F0 0x000 ALT5 0x0 +#define VF610_PAD_PTC15__ADC0_SE7 0x0F0 0x000 ALT6 0x0 +#define VF610_PAD_PTC15__DEBUG_OUT6 0x0F0 0x000 ALT7 0x0 +#define VF610_PAD_PTC16__GPIO_61 0x0F4 0x000 ALT0 0x0 +#define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0 +#define VF610_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1 +#define VF610_PAD_PTC16__UART5_RTS 0x0F4 0x000 ALT4 0x0 +#define VF610_PAD_PTC16__SAI2_RX_SYNC 0x0F4 0x36C ALT5 0x2 +#define VF610_PAD_PTC16__ADC1_SE6 0x0F4 0x000 ALT6 0x0 +#define VF610_PAD_PTC16__DEBUG_OUT7 0x0F4 0x000 ALT7 0x0 +#define VF610_PAD_PTC17__GPIO_62 0x0F8 0x000 ALT0 0x0 +#define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0 +#define VF610_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0 +#define VF610_PAD_PTC17__UART5_CTS 0x0F8 0x000 ALT4 0x0 +#define VF610_PAD_PTC17__SAI2_TX_SYNC 0x0F8 0x374 ALT5 0x1 +#define VF610_PAD_PTC17__USB1_SOF_PULSE 0x0F8 0x000 ALT6 0x0 +#define VF610_PAD_PTC17__DEBUG_OUT8 0x0F8 0x000 ALT7 0x0 +#define VF610_PAD_PTD31__GPIO_63 0x0FC 0x000 ALT0 0x0 +#define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0 +#define VF610_PAD_PTD31__NF_IO15 0x0FC 0x000 ALT2 0x0 +#define VF610_PAD_PTD31__FTM3_CH0 0x0FC 0x000 ALT4 0x0 +#define VF610_PAD_PTD31__DSPI2_CS1 0x0FC 0x000 ALT5 0x0 +#define VF610_PAD_PTD31__DEBUG_OUT9 0x0FC 0x000 ALT7 0x0 +#define VF610_PAD_PTD30__GPIO_64 0x100 0x000 ALT0 0x0 +#define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0 +#define VF610_PAD_PTD30__NF_IO14 0x100 0x000 ALT2 0x0 +#define VF610_PAD_PTD30__FTM3_CH1 0x100 0x000 ALT4 0x0 +#define VF610_PAD_PTD30__DSPI2_CS0 0x100 0x000 ALT5 0x0 +#define VF610_PAD_PTD30__DEBUG_OUT10 0x100 0x000 ALT7 0x0 +#define VF610_PAD_PTD29__GPIO_65 0x104 0x000 ALT0 0x0 +#define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0 +#define VF610_PAD_PTD29__NF_IO13 0x104 0x000 ALT2 0x0 +#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0 +#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0 +#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0 +#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 +#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0 +#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0 +#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1 +#define VF610_PAD_PTD28__FTM3_CH3 0x108 0x000 ALT4 0x0 +#define VF610_PAD_PTD28__DSPI2_SOUT 0x108 0x000 ALT5 0x0 +#define VF610_PAD_PTD28__DEBUG_OUT12 0x108 0x000 ALT7 0x0 +#define VF610_PAD_PTD27__GPIO_67 0x10C 0x000 ALT0 0x0 +#define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0 +#define VF610_PAD_PTD27__NF_IO11 0x10C 0x000 ALT2 0x0 +#define VF610_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1 +#define VF610_PAD_PTD27__FTM3_CH4 0x10C 0x000 ALT4 0x0 +#define VF610_PAD_PTD27__DSPI2_SCK 0x10C 0x000 ALT5 0x0 +#define VF610_PAD_PTD27__DEBUG_OUT13 0x10C 0x000 ALT7 0x0 +#define VF610_PAD_PTD26__GPIO_68 0x110 0x000 ALT0 0x0 +#define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0 +#define VF610_PAD_PTD26__NF_IO10 0x110 0x000 ALT2 0x0 +#define VF610_PAD_PTD26__FTM3_CH5 0x110 0x000 ALT4 0x0 +#define VF610_PAD_PTD26__ESDHC1_WP 0x110 0x000 ALT5 0x0 +#define VF610_PAD_PTD26__DEBUG_OUT14 0x110 0x000 ALT7 0x0 +#define VF610_PAD_PTD25__GPIO_69 0x114 0x000 ALT0 0x0 +#define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0 +#define VF610_PAD_PTD25__NF_IO9 0x114 0x000 ALT2 0x0 +#define VF610_PAD_PTD25__FTM3_CH6 0x114 0x000 ALT4 0x0 +#define VF610_PAD_PTD25__DEBUG_OUT15 0x114 0x000 ALT7 0x0 +#define VF610_PAD_PTD24__GPIO_70 0x118 0x000 ALT0 0x0 +#define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0 +#define VF610_PAD_PTD24__NF_IO8 0x118 0x000 ALT2 0x0 +#define VF610_PAD_PTD24__FTM3_CH7 0x118 0x000 ALT4 0x0 +#define VF610_PAD_PTD24__DEBUG_OUT16 0x118 0x000 ALT7 0x0 +#define VF610_PAD_PTD23__GPIO_71 0x11C 0x000 ALT0 0x0 +#define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0 +#define VF610_PAD_PTD23__NF_IO7 0x11C 0x000 ALT2 0x0 +#define VF610_PAD_PTD23__FTM2_CH0 0x11C 0x000 ALT3 0x0 +#define VF610_PAD_PTD23__ENET0_1588_TMR0 0x11C 0x304 ALT4 0x1 +#define VF610_PAD_PTD23__ESDHC0_DAT4 0x11C 0x000 ALT5 0x0 +#define VF610_PAD_PTD23__UART2_TX 0x11C 0x38C ALT6 0x1 +#define VF610_PAD_PTD23__DCU1_R3 0x11C 0x000 ALT7 0x0 +#define VF610_PAD_PTD22__GPIO_72 0x120 0x000 ALT0 0x0 +#define VF610_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0 +#define VF610_PAD_PTD22__NF_IO6 0x120 0x000 ALT2 0x0 +#define VF610_PAD_PTD22__FTM2_CH1 0x120 0x000 ALT3 0x0 +#define VF610_PAD_PTD22__ENET0_1588_TMR1 0x120 0x308 ALT4 0x1 +#define VF610_PAD_PTD22__ESDHC0_DAT5 0x120 0x000 ALT5 0x0 +#define VF610_PAD_PTD22__UART2_RX 0x120 0x388 ALT6 0x1 +#define VF610_PAD_PTD22__DCU1_R4 0x120 0x000 ALT7 0x0 +#define VF610_PAD_PTD21__GPIO_73 0x124 0x000 ALT0 0x0 +#define VF610_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0 +#define VF610_PAD_PTD21__NF_IO5 0x124 0x000 ALT2 0x0 +#define VF610_PAD_PTD21__ENET0_1588_TMR2 0x124 0x000 ALT4 0x0 +#define VF610_PAD_PTD21__ESDHC0_DAT6 0x124 0x000 ALT5 0x0 +#define VF610_PAD_PTD21__UART2_RTS 0x124 0x000 ALT6 0x0 +#define VF610_PAD_PTD21__DCU1_R5 0x124 0x000 ALT7 0x0 +#define VF610_PAD_PTD20__GPIO_74 0x128 0x000 ALT0 0x0 +#define VF610_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0 +#define VF610_PAD_PTD20__NF_IO4 0x128 0x000 ALT2 0x0 +#define VF610_PAD_PTD20__ENET0_1588_TMR3 0x128 0x000 ALT4 0x0 +#define VF610_PAD_PTD20__ESDHC0_DAT7 0x128 0x000 ALT5 0x0 +#define VF610_PAD_PTD20__UART2_CTS 0x128 0x384 ALT6 0x0 +#define VF610_PAD_PTD20__DCU1_R0 0x128 0x000 ALT7 0x0 +#define VF610_PAD_PTD19__GPIO_75 0x12C 0x000 ALT0 0x0 +#define VF610_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0 +#define VF610_PAD_PTD19__NF_IO3 0x12C 0x000 ALT2 0x0 +#define VF610_PAD_PTD19__ESAI_SCKR 0x12C 0x000 ALT3 0x0 +#define VF610_PAD_PTD19__I2C0_SCL 0x12C 0x33C ALT4 0x2 +#define VF610_PAD_PTD19__FTM2_QD_PHA 0x12C 0x000 ALT5 0x0 +#define VF610_PAD_PTD19__DCU1_R1 0x12C 0x000 ALT7 0x0 +#define VF610_PAD_PTD18__GPIO_76 0x130 0x000 ALT0 0x0 +#define VF610_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0 +#define VF610_PAD_PTD18__NF_IO2 0x130 0x000 ALT2 0x0 +#define VF610_PAD_PTD18__ESAI_FSR 0x130 0x000 ALT3 0x0 +#define VF610_PAD_PTD18__I2C0_SDA 0x130 0x340 ALT4 0x2 +#define VF610_PAD_PTD18__FTM2_QD_PHB 0x130 0x000 ALT5 0x0 +#define VF610_PAD_PTD18__DCU1_G0 0x130 0x000 ALT7 0x0 +#define VF610_PAD_PTD17__GPIO_77 0x134 0x000 ALT0 0x0 +#define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0 +#define VF610_PAD_PTD17__NF_IO1 0x134 0x000 ALT2 0x0 +#define VF610_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0 +#define VF610_PAD_PTD17__I2C1_SCL 0x134 0x344 ALT4 0x2 +#define VF610_PAD_PTD17__DCU1_G1 0x134 0x000 ALT7 0x0 +#define VF610_PAD_PTD16__GPIO_78 0x138 0x000 ALT0 0x0 +#define VF610_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0 +#define VF610_PAD_PTD16__NF_IO0 0x138 0x000 ALT2 0x0 +#define VF610_PAD_PTD16__ESAI_HCKT 0x138 0x000 ALT3 0x0 +#define VF610_PAD_PTD16__I2C1_SDA 0x138 0x348 ALT4 0x2 +#define VF610_PAD_PTD16__DCU1_G2 0x138 0x000 ALT7 0x0 +#define VF610_PAD_PTD0__GPIO_79 0x13C 0x000 ALT0 0x0 +#define VF610_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0 +#define VF610_PAD_PTD0__UART2_TX 0x13C 0x38C ALT2 0x2 +#define VF610_PAD_PTD0__FB_AD15 0x13C 0x000 ALT4 0x0 +#define VF610_PAD_PTD0__SPDIF_EXTCLK 0x13C 0x000 ALT5 0x0 +#define VF610_PAD_PTD0__DEBUG_OUT17 0x13C 0x000 ALT7 0x0 +#define VF610_PAD_PTD1__GPIO_80 0x140 0x000 ALT0 0x0 +#define VF610_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0 +#define VF610_PAD_PTD1__UART2_RX 0x140 0x388 ALT2 0x2 +#define VF610_PAD_PTD1__FB_AD14 0x140 0x000 ALT4 0x0 +#define VF610_PAD_PTD1__SPDIF_IN1 0x140 0x000 ALT5 0x0 +#define VF610_PAD_PTD1__DEBUG_OUT18 0x140 0x000 ALT7 0x0 +#define VF610_PAD_PTD2__GPIO_81 0x144 0x000 ALT0 0x0 +#define VF610_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0 +#define VF610_PAD_PTD2__UART2_RTS 0x144 0x000 ALT2 0x0 +#define VF610_PAD_PTD2__DSPI1_CS3 0x144 0x000 ALT3 0x0 +#define VF610_PAD_PTD2__FB_AD13 0x144 0x000 ALT4 0x0 +#define VF610_PAD_PTD2__SPDIF_OUT1 0x144 0x000 ALT5 0x0 +#define VF610_PAD_PTD2__DEBUG_OUT19 0x144 0x000 ALT7 0x0 +#define VF610_PAD_PTD3__GPIO_82 0x148 0x000 ALT0 0x0 +#define VF610_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0 +#define VF610_PAD_PTD3__UART2_CTS 0x148 0x384 ALT2 0x1 +#define VF610_PAD_PTD3__DSPI1_CS2 0x148 0x000 ALT3 0x0 +#define VF610_PAD_PTD3__FB_AD12 0x148 0x000 ALT4 0x0 +#define VF610_PAD_PTD3__SPDIF_PLOCK 0x148 0x000 ALT5 0x0 +#define VF610_PAD_PTD3__DEBUG_OUT20 0x148 0x000 ALT7 0x0 +#define VF610_PAD_PTD4__GPIO_83 0x14C 0x000 ALT0 0x0 +#define VF610_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0 +#define VF610_PAD_PTD4__DSPI1_CS1 0x14C 0x000 ALT3 0x0 +#define VF610_PAD_PTD4__FB_AD11 0x14C 0x000 ALT4 0x0 +#define VF610_PAD_PTD4__SPDIF_SRCLK 0x14C 0x000 ALT5 0x0 +#define VF610_PAD_PTD4__DEBUG_OUT21 0x14C 0x000 ALT7 0x0 +#define VF610_PAD_PTD5__GPIO_84 0x150 0x000 ALT0 0x0 +#define VF610_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0 +#define VF610_PAD_PTD5__DSPI1_CS0 0x150 0x300 ALT3 0x1 +#define VF610_PAD_PTD5__FB_AD10 0x150 0x000 ALT4 0x0 +#define VF610_PAD_PTD5__DEBUG_OUT22 0x150 0x000 ALT7 0x0 +#define VF610_PAD_PTD6__GPIO_85 0x154 0x000 ALT0 0x0 +#define VF610_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0 +#define VF610_PAD_PTD6__DSPI1_SIN 0x154 0x2FC ALT3 0x1 +#define VF610_PAD_PTD6__FB_AD9 0x154 0x000 ALT4 0x0 +#define VF610_PAD_PTD6__DEBUG_OUT23 0x154 0x000 ALT7 0x0 +#define VF610_PAD_PTD7__GPIO_86 0x158 0x000 ALT0 0x0 +#define VF610_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0 +#define VF610_PAD_PTD7__DSPI1_SOUT 0x158 0x000 ALT3 0x0 +#define VF610_PAD_PTD7__FB_AD8 0x158 0x000 ALT4 0x0 +#define VF610_PAD_PTD7__DEBUG_OUT24 0x158 0x000 ALT7 0x0 +#define VF610_PAD_PTD8__GPIO_87 0x15C 0x000 ALT0 0x0 +#define VF610_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0 +#define VF610_PAD_PTD8__FB_CLKOUT 0x15C 0x000 ALT2 0x0 +#define VF610_PAD_PTD8__DSPI1_SCK 0x15C 0x2F8 ALT3 0x1 +#define VF610_PAD_PTD8__FB_AD7 0x15C 0x000 ALT4 0x0 +#define VF610_PAD_PTD8__DEBUG_OUT25 0x15C 0x000 ALT7 0x0 +#define VF610_PAD_PTD9__GPIO_88 0x160 0x000 ALT0 0x0 +#define VF610_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0 +#define VF610_PAD_PTD9__DSPI3_CS1 0x160 0x000 ALT2 0x0 +#define VF610_PAD_PTD9__FB_AD6 0x160 0x000 ALT4 0x0 +#define VF610_PAD_PTD9__SAI1_TX_SYNC 0x160 0x360 ALT6 0x0 +#define VF610_PAD_PTD9__DCU1_B0 0x160 0x000 ALT7 0x0 +#define VF610_PAD_PTD10__GPIO_89 0x164 0x000 ALT0 0x0 +#define VF610_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0 +#define VF610_PAD_PTD10__DSPI3_CS0 0x164 0x000 ALT2 0x0 +#define VF610_PAD_PTD10__FB_AD5 0x164 0x000 ALT4 0x0 +#define VF610_PAD_PTD10__DCU1_B1 0x164 0x000 ALT7 0x0 +#define VF610_PAD_PTD11__GPIO_90 0x168 0x000 ALT0 0x0 +#define VF610_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0 +#define VF610_PAD_PTD11__DSPI3_SIN 0x168 0x000 ALT2 0x0 +#define VF610_PAD_PTD11__FB_AD4 0x168 0x000 ALT4 0x0 +#define VF610_PAD_PTD11__DEBUG_OUT26 0x168 0x000 ALT7 0x0 +#define VF610_PAD_PTD12__GPIO_91 0x16C 0x000 ALT0 0x0 +#define VF610_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0 +#define VF610_PAD_PTD12__DSPI3_SOUT 0x16C 0x000 ALT2 0x0 +#define VF610_PAD_PTD12__FB_AD3 0x16C 0x000 ALT4 0x0 +#define VF610_PAD_PTD12__DEBUG_OUT27 0x16C 0x000 ALT7 0x0 +#define VF610_PAD_PTD13__GPIO_92 0x170 0x000 ALT0 0x0 +#define VF610_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0 +#define VF610_PAD_PTD13__DSPI3_SCK 0x170 0x000 ALT2 0x0 +#define VF610_PAD_PTD13__FB_AD2 0x170 0x000 ALT4 0x0 +#define VF610_PAD_PTD13__DEBUG_OUT28 0x170 0x000 ALT7 0x0 +#define VF610_PAD_PTB23__GPIO_93 0x174 0x000 ALT0 0x0 +#define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0 +#define VF610_PAD_PTB23__UART1_TX 0x174 0x380 ALT2 0x2 +#define VF610_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1 +#define VF610_PAD_PTB23__FB_MUXED_ALE 0x174 0x000 ALT4 0x0 +#define VF610_PAD_PTB23__FB_TS_B 0x174 0x000 ALT5 0x0 +#define VF610_PAD_PTB23__UART3_RTS 0x174 0x000 ALT6 0x0 +#define VF610_PAD_PTB23__DCU1_G3 0x174 0x000 ALT7 0x0 +#define VF610_PAD_PTB24__GPIO_94 0x178 0x000 ALT0 0x0 +#define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0 +#define VF610_PAD_PTB24__UART1_RX 0x178 0x37C ALT2 0x2 +#define VF610_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1 +#define VF610_PAD_PTB24__FB_MUXED_TSIZ0 0x178 0x000 ALT4 0x0 +#define VF610_PAD_PTB24__NF_WE_B 0x178 0x000 ALT5 0x0 +#define VF610_PAD_PTB24__UART3_CTS 0x178 0x000 ALT6 0x0 +#define VF610_PAD_PTB24__DCU1_G4 0x178 0x000 ALT7 0x0 +#define VF610_PAD_PTB25__GPIO_95 0x17C 0x000 ALT0 0x0 +#define VF610_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0 +#define VF610_PAD_PTB25__UART1_RTS 0x17C 0x000 ALT2 0x0 +#define VF610_PAD_PTB25__SRC_RCON20 0x17C 0x3A0 ALT3 0x1 +#define VF610_PAD_PTB25__FB_CS1_B 0x17C 0x000 ALT4 0x0 +#define VF610_PAD_PTB25__NF_CE0_B 0x17C 0x000 ALT5 0x0 +#define VF610_PAD_PTB25__DCU1_G5 0x17C 0x000 ALT7 0x0 +#define VF610_PAD_PTB26__GPIO_96 0x180 0x000 ALT0 0x0 +#define VF610_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0 +#define VF610_PAD_PTB26__UART1_CTS 0x180 0x378 ALT2 0x2 +#define VF610_PAD_PTB26__SRC_RCON21 0x180 0x000 ALT3 0x0 +#define VF610_PAD_PTB26__FB_CS0_B 0x180 0x000 ALT4 0x0 +#define VF610_PAD_PTB26__NF_CE1_B 0x180 0x000 ALT5 0x0 +#define VF610_PAD_PTB26__DCU1_G6 0x180 0x000 ALT7 0x0 +#define VF610_PAD_PTB27__GPIO_97 0x184 0x000 ALT0 0x0 +#define VF610_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0 +#define VF610_PAD_PTB27__SRC_RCON22 0x184 0x000 ALT3 0x0 +#define VF610_PAD_PTB27__FB_OE_B 0x184 0x000 ALT4 0x0 +#define VF610_PAD_PTB27__FB_MUXED_TBST_B 0x184 0x000 ALT5 0x0 +#define VF610_PAD_PTB27__NF_RE_B 0x184 0x000 ALT6 0x0 +#define VF610_PAD_PTB27__DCU1_G7 0x184 0x000 ALT7 0x0 +#define VF610_PAD_PTB28__GPIO_98 0x188 0x000 ALT0 0x0 +#define VF610_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0 +#define VF610_PAD_PTB28__SRC_RCON23 0x188 0x000 ALT3 0x0 +#define VF610_PAD_PTB28__FB_RW_B 0x188 0x000 ALT4 0x0 +#define VF610_PAD_PTB28__DCU1_B6 0x188 0x000 ALT7 0x0 +#define VF610_PAD_PTC26__GPIO_99 0x18C 0x000 ALT0 0x0 +#define VF610_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0 +#define VF610_PAD_PTC26__DSPI0_CS5 0x18C 0x000 ALT2 0x0 +#define VF610_PAD_PTC26__SRC_RCON24 0x18C 0x000 ALT3 0x0 +#define VF610_PAD_PTC26__FB_TA_B 0x18C 0x000 ALT4 0x0 +#define VF610_PAD_PTC26__NF_RB_B 0x18C 0x000 ALT5 0x0 +#define VF610_PAD_PTC26__DCU1_B7 0x18C 0x000 ALT7 0x0 +#define VF610_PAD_PTC27__GPIO_100 0x190 0x000 ALT0 0x0 +#define VF610_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0 +#define VF610_PAD_PTC27__DSPI0_CS4 0x190 0x000 ALT2 0x0 +#define VF610_PAD_PTC27__SRC_RCON25 0x190 0x000 ALT3 0x0 +#define VF610_PAD_PTC27__FB_BE3_B 0x190 0x000 ALT4 0x0 +#define VF610_PAD_PTC27__FB_CS3_B 0x190 0x000 ALT5 0x0 +#define VF610_PAD_PTC27__NF_ALE 0x190 0x000 ALT6 0x0 +#define VF610_PAD_PTC27__DCU1_B2 0x190 0x000 ALT7 0x0 +#define VF610_PAD_PTC28__GPIO_101 0x194 0x000 ALT0 0x0 +#define VF610_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0 +#define VF610_PAD_PTC28__DSPI0_CS3 0x194 0x000 ALT2 0x0 +#define VF610_PAD_PTC28__SRC_RCON26 0x194 0x000 ALT3 0x0 +#define VF610_PAD_PTC28__FB_BE2_B 0x194 0x000 ALT4 0x0 +#define VF610_PAD_PTC28__FB_CS2_B 0x194 0x000 ALT5 0x0 +#define VF610_PAD_PTC28__NF_CLE 0x194 0x000 ALT6 0x0 +#define VF610_PAD_PTC28__DCU1_B3 0x194 0x000 ALT7 0x0 +#define VF610_PAD_PTC29__GPIO_102 0x198 0x000 ALT0 0x0 +#define VF610_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0 +#define VF610_PAD_PTC29__DSPI0_CS2 0x198 0x000 ALT2 0x0 +#define VF610_PAD_PTC29__SRC_RCON27 0x198 0x000 ALT3 0x0 +#define VF610_PAD_PTC29__FB_BE1_B 0x198 0x000 ALT4 0x0 +#define VF610_PAD_PTC29__FB_MUXED_TSIZE1 0x198 0x000 ALT5 0x0 +#define VF610_PAD_PTC29__DCU1_B4 0x198 0x000 ALT7 0x0 +#define VF610_PAD_PTC30__GPIO_103 0x19C 0x000 ALT0 0x0 +#define VF610_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0 +#define VF610_PAD_PTC30__DSPI1_CS2 0x19C 0x000 ALT2 0x0 +#define VF610_PAD_PTC30__SRC_RCON28 0x19C 0x000 ALT3 0x0 +#define VF610_PAD_PTC30__FB_MUXED_BE0_B 0x19C 0x000 ALT4 0x0 +#define VF610_PAD_PTC30__FB_TSIZ0 0x19C 0x000 ALT5 0x0 +#define VF610_PAD_PTC30__ADC0_SE5 0x19C 0x000 ALT6 0x0 +#define VF610_PAD_PTC30__DCU1_B5 0x19C 0x000 ALT7 0x0 +#define VF610_PAD_PTC31__GPIO_104 0x1A0 0x000 ALT0 0x0 +#define VF610_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1 +#define VF610_PAD_PTC31__SRC_RCON29 0x1A0 0x000 ALT3 0x0 +#define VF610_PAD_PTC31__ADC1_SE5 0x1A0 0x000 ALT6 0x0 +#define VF610_PAD_PTC31__DCU1_B6 0x1A0 0x000 ALT7 0x0 +#define VF610_PAD_PTE0__GPIO_105 0x1A4 0x000 ALT0 0x0 +#define VF610_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0 +#define VF610_PAD_PTE0__SRC_BMODE1 0x1A4 0x000 ALT2 0x0 +#define VF610_PAD_PTE0__LCD0 0x1A4 0x000 ALT4 0x0 +#define VF610_PAD_PTE0__DEBUG_OUT29 0x1A4 0x000 ALT7 0x0 +#define VF610_PAD_PTE1__GPIO_106 0x1A8 0x000 ALT0 0x0 +#define VF610_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0 +#define VF610_PAD_PTE1__SRC_BMODE0 0x1A8 0x000 ALT2 0x0 +#define VF610_PAD_PTE1__LCD1 0x1A8 0x000 ALT4 0x0 +#define VF610_PAD_PTE1__DEBUG_OUT30 0x1A8 0x000 ALT7 0x0 +#define VF610_PAD_PTE2__GPIO_107 0x1AC 0x000 ALT0 0x0 +#define VF610_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0 +#define VF610_PAD_PTE2__LCD2 0x1AC 0x000 ALT4 0x0 +#define VF610_PAD_PTE2__DEBUG_OUT31 0x1AC 0x000 ALT7 0x0 +#define VF610_PAD_PTE3__GPIO_108 0x1B0 0x000 ALT0 0x0 +#define VF610_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0 +#define VF610_PAD_PTE3__LCD3 0x1B0 0x000 ALT4 0x0 +#define VF610_PAD_PTE3__DEBUG_OUT32 0x1B0 0x000 ALT7 0x0 +#define VF610_PAD_PTE4__GPIO_109 0x1B4 0x000 ALT0 0x0 +#define VF610_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0 +#define VF610_PAD_PTE4__LCD4 0x1B4 0x000 ALT4 0x0 +#define VF610_PAD_PTE4__DEBUG_OUT33 0x1B4 0x000 ALT7 0x0 +#define VF610_PAD_PTE5__GPIO_110 0x1B8 0x000 ALT0 0x0 +#define VF610_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0 +#define VF610_PAD_PTE5__LCD5 0x1B8 0x000 ALT4 0x0 +#define VF610_PAD_PTE5__DEBUG_OUT34 0x1B8 0x000 ALT7 0x0 +#define VF610_PAD_PTE6__GPIO_111 0x1BC 0x000 ALT0 0x0 +#define VF610_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0 +#define VF610_PAD_PTE6__LCD6 0x1BC 0x000 ALT4 0x0 +#define VF610_PAD_PTE6__DEBUG_OUT35 0x1BC 0x000 ALT7 0x0 +#define VF610_PAD_PTE7__GPIO_112 0x1C0 0x000 ALT0 0x0 +#define VF610_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0 +#define VF610_PAD_PTE7__SRC_RCON0 0x1C0 0x000 ALT3 0x0 +#define VF610_PAD_PTE7__LCD7 0x1C0 0x000 ALT4 0x0 +#define VF610_PAD_PTE7__DEBUG_OUT36 0x1C0 0x000 ALT7 0x0 +#define VF610_PAD_PTE8__GPIO_113 0x1C4 0x000 ALT0 0x0 +#define VF610_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0 +#define VF610_PAD_PTE8__SRC_RCON1 0x1C4 0x000 ALT3 0x0 +#define VF610_PAD_PTE8__LCD8 0x1C4 0x000 ALT4 0x0 +#define VF610_PAD_PTE8__DEBUG_OUT37 0x1C4 0x000 ALT7 0x0 +#define VF610_PAD_PTE9__GPIO_114 0x1C8 0x000 ALT0 0x0 +#define VF610_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0 +#define VF610_PAD_PTE9__SRC_RCON2 0x1C8 0x000 ALT3 0x0 +#define VF610_PAD_PTE9__LCD9 0x1C8 0x000 ALT4 0x0 +#define VF610_PAD_PTE9__DEBUG_OUT38 0x1C8 0x000 ALT7 0x0 +#define VF610_PAD_PTE10__GPIO_115 0x1CC 0x000 ALT0 0x0 +#define VF610_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0 +#define VF610_PAD_PTE10__SRC_RCON3 0x1CC 0x000 ALT3 0x0 +#define VF610_PAD_PTE10__LCD10 0x1CC 0x000 ALT4 0x0 +#define VF610_PAD_PTE10__DEBUG_OUT39 0x1CC 0x000 ALT7 0x0 +#define VF610_PAD_PTE11__GPIO_116 0x1D0 0x000 ALT0 0x0 +#define VF610_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0 +#define VF610_PAD_PTE11__SRC_RCON4 0x1D0 0x000 ALT3 0x0 +#define VF610_PAD_PTE11__LCD11 0x1D0 0x000 ALT4 0x0 +#define VF610_PAD_PTE11__DEBUG_OUT40 0x1D0 0x000 ALT7 0x0 +#define VF610_PAD_PTE12__GPIO_117 0x1D4 0x000 ALT0 0x0 +#define VF610_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0 +#define VF610_PAD_PTE12__DSPI1_CS3 0x1D4 0x000 ALT2 0x0 +#define VF610_PAD_PTE12__SRC_RCON5 0x1D4 0x000 ALT3 0x0 +#define VF610_PAD_PTE12__LCD12 0x1D4 0x000 ALT4 0x0 +#define VF610_PAD_PTE12__LPT_ALT0 0x1D4 0x000 ALT7 0x0 +#define VF610_PAD_PTE13__GPIO_118 0x1D8 0x000 ALT0 0x0 +#define VF610_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0 +#define VF610_PAD_PTE13__LCD13 0x1D8 0x000 ALT4 0x0 +#define VF610_PAD_PTE13__DEBUG_OUT41 0x1D8 0x000 ALT7 0x0 +#define VF610_PAD_PTE14__GPIO_119 0x1DC 0x000 ALT0 0x0 +#define VF610_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0 +#define VF610_PAD_PTE14__LCD14 0x1DC 0x000 ALT4 0x0 +#define VF610_PAD_PTE14__DEBUG_OUT42 0x1DC 0x000 ALT7 0x0 +#define VF610_PAD_PTE15__GPIO_120 0x1E0 0x000 ALT0 0x0 +#define VF610_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0 +#define VF610_PAD_PTE15__SRC_RCON6 0x1E0 0x000 ALT3 0x0 +#define VF610_PAD_PTE15__LCD15 0x1E0 0x000 ALT4 0x0 +#define VF610_PAD_PTE15__DEBUG_OUT43 0x1E0 0x000 ALT7 0x0 +#define VF610_PAD_PTE16__GPIO_121 0x1E4 0x000 ALT0 0x0 +#define VF610_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0 +#define VF610_PAD_PTE16__SRC_RCON7 0x1E4 0x000 ALT3 0x0 +#define VF610_PAD_PTE16__LCD16 0x1E4 0x000 ALT4 0x0 +#define VF610_PAD_PTE17__GPIO_122 0x1E8 0x000 ALT0 0x0 +#define VF610_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0 +#define VF610_PAD_PTE17__SRC_RCON8 0x1E8 0x000 ALT3 0x0 +#define VF610_PAD_PTE17__LCD17 0x1E8 0x000 ALT4 0x0 +#define VF610_PAD_PTE18__GPIO_123 0x1EC 0x000 ALT0 0x0 +#define VF610_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0 +#define VF610_PAD_PTE18__SRC_RCON9 0x1EC 0x000 ALT3 0x0 +#define VF610_PAD_PTE18__LCD18 0x1EC 0x000 ALT4 0x0 +#define VF610_PAD_PTE19__GPIO_124 0x1F0 0x000 ALT0 0x0 +#define VF610_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0 +#define VF610_PAD_PTE19__SRC_RCON10 0x1F0 0x000 ALT3 0x0 +#define VF610_PAD_PTE19__LCD19 0x1F0 0x000 ALT4 0x0 +#define VF610_PAD_PTE19__I2C0_SCL 0x1F0 0x33C ALT5 0x3 +#define VF610_PAD_PTE20__GPIO_125 0x1F4 0x000 ALT0 0x0 +#define VF610_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0 +#define VF610_PAD_PTE20__SRC_RCON11 0x1F4 0x000 ALT3 0x0 +#define VF610_PAD_PTE20__LCD20 0x1F4 0x000 ALT4 0x0 +#define VF610_PAD_PTE20__I2C0_SDA 0x1F4 0x340 ALT5 0x3 +#define VF610_PAD_PTE20__EWM_IN 0x1F4 0x000 ALT7 0x0 +#define VF610_PAD_PTE21__GPIO_126 0x1F8 0x000 ALT0 0x0 +#define VF610_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0 +#define VF610_PAD_PTE21__LCD21 0x1F8 0x000 ALT4 0x0 +#define VF610_PAD_PTE22__GPIO_127 0x1FC 0x000 ALT0 0x0 +#define VF610_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0 +#define VF610_PAD_PTE22__LCD22 0x1FC 0x000 ALT4 0x0 +#define VF610_PAD_PTE23__GPIO_128 0x200 0x000 ALT0 0x0 +#define VF610_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0 +#define VF610_PAD_PTE23__SRC_RCON12 0x200 0x000 ALT3 0x0 +#define VF610_PAD_PTE23__LCD23 0x200 0x000 ALT4 0x0 +#define VF610_PAD_PTE24__GPIO_129 0x204 0x000 ALT0 0x0 +#define VF610_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0 +#define VF610_PAD_PTE24__SRC_RCON13 0x204 0x000 ALT3 0x0 +#define VF610_PAD_PTE24__LCD24 0x204 0x000 ALT4 0x0 +#define VF610_PAD_PTE25__GPIO_130 0x208 0x000 ALT0 0x0 +#define VF610_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0 +#define VF610_PAD_PTE25__SRC_RCON14 0x208 0x000 ALT3 0x0 +#define VF610_PAD_PTE25__LCD25 0x208 0x000 ALT4 0x0 +#define VF610_PAD_PTE26__GPIO_131 0x20C 0x000 ALT0 0x0 +#define VF610_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0 +#define VF610_PAD_PTE26__SRC_RCON15 0x20C 0x000 ALT3 0x0 +#define VF610_PAD_PTE26__LCD26 0x20C 0x000 ALT4 0x0 +#define VF610_PAD_PTE27__GPIO_132 0x210 0x000 ALT0 0x0 +#define VF610_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0 +#define VF610_PAD_PTE27__SRC_RCON16 0x210 0x000 ALT3 0x0 +#define VF610_PAD_PTE27__LCD27 0x210 0x000 ALT4 0x0 +#define VF610_PAD_PTE27__I2C1_SCL 0x210 0x344 ALT5 0x3 +#define VF610_PAD_PTE28__GPIO_133 0x214 0x000 ALT0 0x0 +#define VF610_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0 +#define VF610_PAD_PTE28__SRC_RCON17 0x214 0x000 ALT3 0x0 +#define VF610_PAD_PTE28__LCD28 0x214 0x000 ALT4 0x0 +#define VF610_PAD_PTE28__I2C1_SDA 0x214 0x348 ALT5 0x3 +#define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0 +#define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 +#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1 + +#endif diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts new file mode 100644 index 000000000000..b3905f5bcaf9 --- /dev/null +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -0,0 +1,57 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "VF610 Tower Board"; + compatible = "fsl,vf610-twr", "fsl,vf610"; + + chosen { + bootargs = "console=ttyLP1,115200"; + }; + + memory { + reg = <0x80000000 0x8000000>; + }; + + clocks { + audio_ext { + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + enet_ext { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + +}; + +&fec0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec0_1>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1_1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi new file mode 100644 index 000000000000..e1eb7dadda80 --- /dev/null +++ b/arch/arm/boot/dts/vf610.dtsi @@ -0,0 +1,464 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include "skeleton.dtsi" +#include "vf610-pinfunc.h" +#include <dt-bindings/clock/vf610-clock.h> + +/ { + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a5"; + device_type = "cpu"; + reg = <0x0>; + next-level-cache = <&L2>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + sxosc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + fxosc { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + aips0: aips-bus@40000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + reg = <0x40000000 0x70000>; + ranges; + + intc: interrupt-controller@40002000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + reg = <0x40003000 0x1000>, + <0x40002100 0x100>; + }; + + L2: l2-cache@40006000 { + compatible = "arm,pl310-cache"; + reg = <0x40006000 0x1000>; + cache-unified; + cache-level = <2>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <2 2 2>; + }; + + uart0: serial@40027000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x40027000 0x1000>; + interrupts = <0 61 0x00>; + clocks = <&clks VF610_CLK_UART0>; + clock-names = "ipg"; + status = "disabled"; + }; + + uart1: serial@40028000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x40028000 0x1000>; + interrupts = <0 62 0x04>; + clocks = <&clks VF610_CLK_UART1>; + clock-names = "ipg"; + status = "disabled"; + }; + + uart2: serial@40029000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x40029000 0x1000>; + interrupts = <0 63 0x04>; + clocks = <&clks VF610_CLK_UART2>; + clock-names = "ipg"; + status = "disabled"; + }; + + uart3: serial@4002a000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x4002a000 0x1000>; + interrupts = <0 64 0x04>; + clocks = <&clks VF610_CLK_UART3>; + clock-names = "ipg"; + status = "disabled"; + }; + + sai2: sai@40031000 { + compatible = "fsl,vf610-sai"; + reg = <0x40031000 0x1000>; + interrupts = <0 86 0x04>; + clocks = <&clks VF610_CLK_SAI2>; + clock-names = "sai"; + status = "disabled"; + }; + + pit: pit@40037000 { + compatible = "fsl,vf610-pit"; + reg = <0x40037000 0x1000>; + interrupts = <0 39 0x04>; + clocks = <&clks VF610_CLK_PIT>; + clock-names = "pit"; + }; + + wdog@4003e000 { + compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; + reg = <0x4003e000 0x1000>; + clocks = <&clks VF610_CLK_WDT>; + clock-names = "wdog"; + }; + + qspi0: quadspi@40044000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-qspi"; + reg = <0x40044000 0x1000>; + interrupts = <0 24 0x04>; + clocks = <&clks VF610_CLK_QSPI0_EN>, + <&clks VF610_CLK_QSPI0>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + iomuxc: iomuxc@40048000 { + compatible = "fsl,vf610-iomuxc"; + reg = <0x40048000 0x1000>; + #gpio-range-cells = <3>; + + /* functions and groups pins */ + + dcu0 { + pinctrl_dcu0_1: dcu0grp_1 { + fsl,pins = < + VF610_PAD_PTB8__GPIO_30 0x42 + VF610_PAD_PTE0__DCU0_HSYNC 0x42 + VF610_PAD_PTE1__DCU0_VSYNC 0x42 + VF610_PAD_PTE2__DCU0_PCLK 0x42 + VF610_PAD_PTE4__DCU0_DE 0x42 + VF610_PAD_PTE5__DCU0_R0 0x42 + VF610_PAD_PTE6__DCU0_R1 0x42 + VF610_PAD_PTE7__DCU0_R2 0x42 + VF610_PAD_PTE8__DCU0_R3 0x42 + VF610_PAD_PTE9__DCU0_R4 0x42 + VF610_PAD_PTE10__DCU0_R5 0x42 + VF610_PAD_PTE11__DCU0_R6 0x42 + VF610_PAD_PTE12__DCU0_R7 0x42 + VF610_PAD_PTE13__DCU0_G0 0x42 + VF610_PAD_PTE14__DCU0_G1 0x42 + VF610_PAD_PTE15__DCU0_G2 0x42 + VF610_PAD_PTE16__DCU0_G3 0x42 + VF610_PAD_PTE17__DCU0_G4 0x42 + VF610_PAD_PTE18__DCU0_G5 0x42 + VF610_PAD_PTE19__DCU0_G6 0x42 + VF610_PAD_PTE20__DCU0_G7 0x42 + VF610_PAD_PTE21__DCU0_B0 0x42 + VF610_PAD_PTE22__DCU0_B1 0x42 + VF610_PAD_PTE23__DCU0_B2 0x42 + VF610_PAD_PTE24__DCU0_B3 0x42 + VF610_PAD_PTE25__DCU0_B4 0x42 + VF610_PAD_PTE26__DCU0_B5 0x42 + VF610_PAD_PTE27__DCU0_B6 0x42 + VF610_PAD_PTE28__DCU0_B7 0x42 + >; + }; + }; + + dspi0 { + pinctrl_dspi0_1: dspi0grp_1 { + fsl,pins = < + VF610_PAD_PTB19__DSPI0_CS0 0x1182 + VF610_PAD_PTB20__DSPI0_SIN 0x1181 + VF610_PAD_PTB21__DSPI0_SOUT 0x1182 + VF610_PAD_PTB22__DSPI0_SCK 0x1182 + >; + }; + }; + + esdhc1 { + pinctrl_esdhc1_1: esdhc1grp_1 { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTA7__GPIO_134 0x219d + >; + }; + }; + + fec0 { + pinctrl_fec0_1: fec0grp_1 { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 + VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 + VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 + VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 + VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 + VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 + VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 + VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 + VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 + >; + }; + }; + + fec1 { + pinctrl_fec1_1: fec1grp_1 { + fsl,pins = < + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + }; + + i2c0 { + pinctrl_i2c0_1: i2c0grp_1 { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x30d3 + VF610_PAD_PTB15__I2C0_SDA 0x30d3 + >; + }; + }; + + pwm0 { + pinctrl_pwm0_1: pwm0grp_1 { + fsl,pins = < + VF610_PAD_PTB0__FTM0_CH0 0x1582 + VF610_PAD_PTB1__FTM0_CH1 0x1582 + VF610_PAD_PTB2__FTM0_CH2 0x1582 + VF610_PAD_PTB3__FTM0_CH3 0x1582 + VF610_PAD_PTB6__FTM0_CH6 0x1582 + VF610_PAD_PTB7__FTM0_CH7 0x1582 + >; + }; + }; + + qspi0 { + pinctrl_qspi0_1: qspi0grp_1 { + fsl,pins = < + VF610_PAD_PTD0__QSPI0_A_QSCK 0x307b + VF610_PAD_PTD1__QSPI0_A_CS0 0x307f + VF610_PAD_PTD2__QSPI0_A_DATA3 0x3073 + VF610_PAD_PTD3__QSPI0_A_DATA2 0x3073 + VF610_PAD_PTD4__QSPI0_A_DATA1 0x3073 + VF610_PAD_PTD5__QSPI0_A_DATA0 0x307b + VF610_PAD_PTD7__QSPI0_B_QSCK 0x307b + VF610_PAD_PTD8__QSPI0_B_CS0 0x307f + VF610_PAD_PTD9__QSPI0_B_DATA3 0x3073 + VF610_PAD_PTD10__QSPI0_B_DATA2 0x3073 + VF610_PAD_PTD11__QSPI0_B_DATA1 0x3073 + VF610_PAD_PTD12__QSPI0_B_DATA0 0x307b + >; + }; + }; + + sai2 { + pinctrl_sai2_1: sai2grp_1 { + fsl,pins = < + VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed + VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee + VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed + VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed + VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed + VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed + VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp_1 { + fsl,pins = < + VF610_PAD_PTB4__UART1_TX 0x21a2 + VF610_PAD_PTB5__UART1_RX 0x21a1 + >; + }; + }; + + usbvbus { + pinctrl_usbvbus_1: usbvbusgrp_1 { + fsl,pins = < + VF610_PAD_PTA24__USB1_VBUS_EN 0x219c + VF610_PAD_PTA16__USB0_VBUS_EN 0x219c + >; + }; + }; + + }; + + gpio1: gpio@40049000 { + compatible = "fsl,vf610-gpio"; + reg = <0x40049000 0x1000 0x400ff000 0x40>; + interrupts = <0 107 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 0 32>; + }; + + gpio2: gpio@4004a000 { + compatible = "fsl,vf610-gpio"; + reg = <0x4004a000 0x1000 0x400ff040 0x40>; + interrupts = <0 108 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 32 32>; + }; + + gpio3: gpio@4004b000 { + compatible = "fsl,vf610-gpio"; + reg = <0x4004b000 0x1000 0x400ff080 0x40>; + interrupts = <0 109 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 64 32>; + }; + + gpio4: gpio@4004c000 { + compatible = "fsl,vf610-gpio"; + reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; + interrupts = <0 110 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 96 32>; + }; + + gpio5: gpio@4004d000 { + compatible = "fsl,vf610-gpio"; + reg = <0x4004d000 0x1000 0x400ff100 0x40>; + interrupts = <0 111 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 128 7>; + }; + + anatop@40050000 { + compatible = "fsl,vf610-anatop"; + reg = <0x40050000 0x1000>; + }; + + i2c0: i2c@40066000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x40066000 0x1000>; + interrupts =<0 71 0x04>; + clocks = <&clks VF610_CLK_I2C0>; + clock-names = "ipg"; + status = "disabled"; + }; + + clks: ccm@4006b000 { + compatible = "fsl,vf610-ccm"; + reg = <0x4006b000 0x1000>; + #clock-cells = <1>; + }; + }; + + aips1: aips-bus@40080000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40080000 0x80000>; + ranges; + + uart4: serial@400a9000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x400a9000 0x1000>; + interrupts = <0 65 0x04>; + clocks = <&clks VF610_CLK_UART4>; + clock-names = "ipg"; + status = "disabled"; + }; + + uart5: serial@400aa000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x400aa000 0x1000>; + interrupts = <0 66 0x04>; + clocks = <&clks VF610_CLK_UART5>; + clock-names = "ipg"; + status = "disabled"; + }; + + fec0: ethernet@400d0000 { + compatible = "fsl,mvf600-fec"; + reg = <0x400d0000 0x1000>; + interrupts = <0 78 0x04>; + clocks = <&clks VF610_CLK_ENET>, + <&clks VF610_CLK_ENET>, + <&clks VF610_CLK_ENET>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; + }; + + fec1: ethernet@400d1000 { + compatible = "fsl,mvf600-fec"; + reg = <0x400d1000 0x1000>; + interrupts = <0 79 0x04>; + clocks = <&clks VF610_CLK_ENET>, + <&clks VF610_CLK_ENET>, + <&clks VF610_CLK_ENET>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts index 877b33afa7ed..87f33310e2bc 100644 --- a/arch/arm/boot/dts/vt8500-bv07.dts +++ b/arch/arm/boot/dts/vt8500-bv07.dts @@ -30,3 +30,7 @@ }; }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi index 4a4b96f6827e..51d0e912c8f5 100644 --- a/arch/arm/boot/dts/vt8500.dtsi +++ b/arch/arm/boot/dts/vt8500.dtsi @@ -11,6 +11,23 @@ / { compatible = "via,vt8500"; + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -111,32 +128,36 @@ reg = <0xd8050400 0x100>; }; - uart@d8200000 { + uart0: serial@d8200000 { compatible = "via,vt8500-uart"; reg = <0xd8200000 0x1040>; interrupts = <32>; clocks = <&clkuart0>; + status = "disabled"; }; - uart@d82b0000 { + uart1: serial@d82b0000 { compatible = "via,vt8500-uart"; reg = <0xd82b0000 0x1040>; interrupts = <33>; clocks = <&clkuart1>; + status = "disabled"; }; - uart@d8210000 { + uart2: serial@d8210000 { compatible = "via,vt8500-uart"; reg = <0xd8210000 0x1040>; interrupts = <47>; clocks = <&clkuart2>; + status = "disabled"; }; - uart@d82c0000 { + uart3: serial@d82c0000 { compatible = "via,vt8500-uart"; reg = <0xd82c0000 0x1040>; interrupts = <50>; clocks = <&clkuart3>; + status = "disabled"; }; rtc@d8100000 { diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts index edd2cec3d37f..e3e6b9eb09d0 100644 --- a/arch/arm/boot/dts/wm8505-ref.dts +++ b/arch/arm/boot/dts/wm8505-ref.dts @@ -30,3 +30,7 @@ }; }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index b2bf359e852f..a1a854b8a454 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -12,11 +12,24 @@ compatible = "wm,wm8505"; cpus { - cpu@0 { - compatible = "arm,arm926ejs"; + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; }; }; + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -68,6 +81,13 @@ clock-frequency = <25000000>; }; + plla: plla { + #clock-cells = <0>; + compatible = "via,vt8500-pll-clock"; + clocks = <&ref25>; + reg = <0x200>; + }; + pllb: pllb { #clock-cells = <0>; compatible = "via,vt8500-pll-clock"; @@ -75,6 +95,48 @@ reg = <0x204>; }; + pllc: pllc { + #clock-cells = <0>; + compatible = "via,vt8500-pll-clock"; + clocks = <&ref25>; + reg = <0x208>; + }; + + plld: plld { + #clock-cells = <0>; + compatible = "via,vt8500-pll-clock"; + clocks = <&ref25>; + reg = <0x20c>; + }; + + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x350>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + clkuart0: uart0 { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; @@ -163,46 +225,52 @@ reg = <0xd8050400 0x100>; }; - uart@d8200000 { + uart0: serial@d8200000 { compatible = "via,vt8500-uart"; reg = <0xd8200000 0x1040>; interrupts = <32>; clocks = <&clkuart0>; + status = "disabled"; }; - uart@d82b0000 { + uart1: serial@d82b0000 { compatible = "via,vt8500-uart"; reg = <0xd82b0000 0x1040>; interrupts = <33>; clocks = <&clkuart1>; + status = "disabled"; }; - uart@d8210000 { + uart2: serial@d8210000 { compatible = "via,vt8500-uart"; reg = <0xd8210000 0x1040>; interrupts = <47>; clocks = <&clkuart2>; + status = "disabled"; }; - uart@d82c0000 { + uart3: serial@d82c0000 { compatible = "via,vt8500-uart"; reg = <0xd82c0000 0x1040>; interrupts = <50>; clocks = <&clkuart3>; + status = "disabled"; }; - uart@d8370000 { + uart4: serial@d8370000 { compatible = "via,vt8500-uart"; reg = <0xd8370000 0x1040>; interrupts = <31>; clocks = <&clkuart4>; + status = "disabled"; }; - uart@d8380000 { + uart5: serial@d8380000 { compatible = "via,vt8500-uart"; reg = <0xd8380000 0x1040>; interrupts = <30>; clocks = <&clkuart5>; + status = "disabled"; }; rtc@d8100000 { diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts index 61671a0d9ede..dd0d1b602388 100644 --- a/arch/arm/boot/dts/wm8650-mid.dts +++ b/arch/arm/boot/dts/wm8650-mid.dts @@ -32,3 +32,6 @@ }; }; +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi index dd8464eeb40d..7525982262ac 100644 --- a/arch/arm/boot/dts/wm8650.dtsi +++ b/arch/arm/boot/dts/wm8650.dtsi @@ -11,6 +11,21 @@ / { compatible = "wm,wm8650"; + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -77,6 +92,55 @@ reg = <0x204>; }; + pllc: pllc { + #clock-cells = <0>; + compatible = "wm,wm8650-pll-clock"; + clocks = <&ref25>; + reg = <0x208>; + }; + + plld: plld { + #clock-cells = <0>; + compatible = "wm,wm8650-pll-clock"; + clocks = <&ref25>; + reg = <0x20c>; + }; + + plle: plle { + #clock-cells = <0>; + compatible = "wm,wm8650-pll-clock"; + clocks = <&ref25>; + reg = <0x210>; + }; + + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x320>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + clkuart0: uart0 { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; @@ -93,14 +157,7 @@ enable-bit = <2>; }; - arm: arm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plla>; - divisor-reg = <0x300>; - }; - - sdhc: sdhc { + clksdhc: sdhc { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; clocks = <&pllb>; @@ -140,18 +197,20 @@ reg = <0xd8050400 0x100>; }; - uart@d8200000 { + uart0: serial@d8200000 { compatible = "via,vt8500-uart"; reg = <0xd8200000 0x1040>; interrupts = <32>; clocks = <&clkuart0>; + status = "disabled"; }; - uart@d82b0000 { + uart1: serial@d82b0000 { compatible = "via,vt8500-uart"; reg = <0xd82b0000 0x1040>; interrupts = <33>; clocks = <&clkuart1>; + status = "disabled"; }; rtc@d8100000 { diff --git a/arch/arm/boot/dts/wm8750-apc8750.dts b/arch/arm/boot/dts/wm8750-apc8750.dts new file mode 100644 index 000000000000..37e4a408bf39 --- /dev/null +++ b/arch/arm/boot/dts/wm8750-apc8750.dts @@ -0,0 +1,30 @@ +/* + * wm8750-apc8750.dts + * - Device tree file for VIA APC8750 + * + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> + * + * Licensed under GPLv2 or later + */ + +/dts-v1/; +/include/ "wm8750.dtsi" + +/ { + model = "VIA APC8750"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&i2c>; + + i2c: i2c { + wm,pins = <168 169 170 171>; + wm,function = <2>; /* alt */ + wm,pull = <2>; /* pull-up */ + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi new file mode 100644 index 000000000000..557a9c2ace49 --- /dev/null +++ b/arch/arm/boot/dts/wm8750.dtsi @@ -0,0 +1,347 @@ +/* + * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC + * + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> + * + * Licensed under GPLv2 or later + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "wm,wm8750"; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm1176ej-s"; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc0>; + + intc0: interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; + + /* Secondary IC cascaded to intc0 */ + intc1: interrupt-controller@d8150000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xD8150000 0x10000>; + interrupts = <56 57 58 59 60 61 62 63>; + }; + + pinctrl: pinctrl@d8110000 { + compatible = "wm,wm8750-pinctrl"; + reg = <0xd8110000 0x10000>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pmc@d8130000 { + compatible = "via,vt8500-pmc"; + reg = <0xd8130000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref24: ref24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + ref25: ref25M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + plla: plla { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x200>; + }; + + pllb: pllb { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x204>; + }; + + pllc: pllc { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x208>; + }; + + plld: plld { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x20C>; + }; + + plle: plle { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x210>; + }; + + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x320>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + + clkuart0: uart0 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <24>; + }; + + clkuart1: uart1 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <25>; + }; + + clkuart2: uart2 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <26>; + }; + + clkuart3: uart3 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <27>; + }; + + clkuart4: uart4 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <28>; + }; + + clkuart5: uart5 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <29>; + }; + + clkpwm: pwm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x350>; + enable-reg = <0x250>; + enable-bit = <17>; + }; + + clksdhc: sdhc { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x330>; + divisor-mask = <0x3f>; + enable-reg = <0x250>; + enable-bit = <0>; + }; + + clki2c0: i2c0clk { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x3A0>; + enable-reg = <0x250>; + enable-bit = <8>; + }; + + clki2c1: i2c1clk { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x3A4>; + enable-reg = <0x250>; + enable-bit = <9>; + }; + }; + }; + + pwm: pwm@d8220000 { + #pwm-cells = <3>; + compatible = "via,vt8500-pwm"; + reg = <0xd8220000 0x100>; + clocks = <&clkpwm>; + }; + + timer@d8130100 { + compatible = "via,vt8500-timer"; + reg = <0xd8130100 0x28>; + interrupts = <36>; + }; + + ehci@d8007900 { + compatible = "via,vt8500-ehci"; + reg = <0xd8007900 0x200>; + interrupts = <26>; + }; + + uhci@d8007b00 { + compatible = "platform-uhci"; + reg = <0xd8007b00 0x200>; + interrupts = <26>; + }; + + uhci@d8008d00 { + compatible = "platform-uhci"; + reg = <0xd8008d00 0x200>; + interrupts = <26>; + }; + + uart0: serial@d8200000 { + compatible = "via,vt8500-uart"; + reg = <0xd8200000 0x1040>; + interrupts = <32>; + clocks = <&clkuart0>; + status = "disabled"; + }; + + uart1: serial@d82b0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82b0000 0x1040>; + interrupts = <33>; + clocks = <&clkuart1>; + status = "disabled"; + }; + + uart2: serial@d8210000 { + compatible = "via,vt8500-uart"; + reg = <0xd8210000 0x1040>; + interrupts = <47>; + clocks = <&clkuart2>; + status = "disabled"; + }; + + uart3: serial@d82c0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82c0000 0x1040>; + interrupts = <50>; + clocks = <&clkuart3>; + status = "disabled"; + }; + + uart4: serial@d8370000 { + compatible = "via,vt8500-uart"; + reg = <0xd8370000 0x1040>; + interrupts = <30>; + clocks = <&clkuart4>; + status = "disabled"; + }; + + uart5: serial@d8380000 { + compatible = "via,vt8500-uart"; + reg = <0xd8380000 0x1040>; + interrupts = <43>; + clocks = <&clkuart5>; + status = "disabled"; + }; + + rtc@d8100000 { + compatible = "via,vt8500-rtc"; + reg = <0xd8100000 0x10000>; + interrupts = <48>; + }; + + sdhc@d800a000 { + compatible = "wm,wm8505-sdhc"; + reg = <0xd800a000 0x1000>; + interrupts = <20 21>; + clocks = <&clksdhc>; + bus-width = <4>; + sdon-inverted; + }; + + i2c_0: i2c@d8280000 { + compatible = "wm,wm8505-i2c"; + reg = <0xd8280000 0x1000>; + interrupts = <19>; + clocks = <&clki2c0>; + clock-frequency = <400000>; + }; + + i2c_1: i2c@d8320000 { + compatible = "wm,wm8505-i2c"; + reg = <0xd8320000 0x1000>; + interrupts = <18>; + clocks = <&clki2c1>; + clock-frequency = <400000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/wm8850-w70v2.dts index 32d22532cd6c..90e913fb64be 100644 --- a/arch/arm/boot/dts/wm8850-w70v2.dts +++ b/arch/arm/boot/dts/wm8850-w70v2.dts @@ -41,3 +41,7 @@ }; }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi index fc790d0aee66..d98386dd2882 100644 --- a/arch/arm/boot/dts/wm8850.dtsi +++ b/arch/arm/boot/dts/wm8850.dtsi @@ -11,6 +11,17 @@ / { compatible = "wm,wm8850"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x0>; + }; + }; + aliases { serial0 = &uart0; serial1 = &uart1; @@ -72,18 +83,81 @@ plla: plla { #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref24>; reg = <0x200>; }; pllb: pllb { #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref24>; reg = <0x204>; }; + pllc: pllc { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref24>; + reg = <0x208>; + }; + + plld: plld { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref24>; + reg = <0x20c>; + }; + + plle: plle { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref24>; + reg = <0x210>; + }; + + pllf: pllf { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref24>; + reg = <0x214>; + }; + + pllg: pllg { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref24>; + reg = <0x218>; + }; + + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x320>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + clkuart0: uart0 { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; @@ -178,32 +252,36 @@ interrupts = <26>; }; - uart0: uart@d8200000 { + uart0: serial@d8200000 { compatible = "via,vt8500-uart"; reg = <0xd8200000 0x1040>; interrupts = <32>; clocks = <&clkuart0>; + status = "disabled"; }; - uart1: uart@d82b0000 { + uart1: serial@d82b0000 { compatible = "via,vt8500-uart"; reg = <0xd82b0000 0x1040>; interrupts = <33>; clocks = <&clkuart1>; + status = "disabled"; }; - uart2: uart@d8210000 { + uart2: serial@d8210000 { compatible = "via,vt8500-uart"; reg = <0xd8210000 0x1040>; interrupts = <47>; clocks = <&clkuart2>; + status = "disabled"; }; - uart3: uart@d82c0000 { + uart3: serial@d82c0000 { compatible = "via,vt8500-uart"; reg = <0xd82c0000 0x1040>; interrupts = <50>; clocks = <&clkuart3>; + status = "disabled"; }; rtc@d8100000 { diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 14fb2e609bab..6f54a64850eb 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -49,16 +49,20 @@ uart0: uart@e0000000 { compatible = "xlnx,xuartps"; + status = "disabled"; + clocks = <&clkc 23>, <&clkc 40>; + clock-names = "ref_clk", "aper_clk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; - clocks = <&uart_clk 0>; }; uart1: uart@e0001000 { compatible = "xlnx,xuartps"; + status = "disabled"; + clocks = <&clkc 24>, <&clkc 41>; + clock-names = "ref_clk", "aper_clk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; - clocks = <&uart_clk 1>; }; slcr: slcr@f8000000 { @@ -69,50 +73,21 @@ #address-cells = <1>; #size-cells = <0>; - ps_clk: ps_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* clock-frequency set in board-specific file */ - clock-output-names = "ps_clk"; - }; - armpll: armpll { - #clock-cells = <0>; - compatible = "xlnx,zynq-pll"; - clocks = <&ps_clk>; - reg = <0x100 0x110>; - clock-output-names = "armpll"; - }; - ddrpll: ddrpll { - #clock-cells = <0>; - compatible = "xlnx,zynq-pll"; - clocks = <&ps_clk>; - reg = <0x104 0x114>; - clock-output-names = "ddrpll"; - }; - iopll: iopll { - #clock-cells = <0>; - compatible = "xlnx,zynq-pll"; - clocks = <&ps_clk>; - reg = <0x108 0x118>; - clock-output-names = "iopll"; - }; - uart_clk: uart_clk { - #clock-cells = <1>; - compatible = "xlnx,zynq-periph-clock"; - clocks = <&iopll &armpll &ddrpll>; - reg = <0x154>; - clock-output-names = "uart0_ref_clk", - "uart1_ref_clk"; - }; - cpu_clk: cpu_clk { + clkc: clkc { #clock-cells = <1>; - compatible = "xlnx,zynq-cpu-clock"; - clocks = <&iopll &armpll &ddrpll>; - reg = <0x120 0x1C4>; - clock-output-names = "cpu_6x4x", - "cpu_3x2x", - "cpu_2x", - "cpu_1x"; + compatible = "xlnx,ps7-clkc"; + ps-clk-frequency = <33333333>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", + "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", + "dci", "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", + "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", + "dma", "usb0_aper", "usb1_aper", "gem0_aper", + "gem1_aper", "sdio0_aper", "sdio1_aper", + "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", + "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", + "gpio_aper", "lqspi_aper", "smc_aper", "swdt", + "dbg_trc", "dbg_apb"; }; }; }; @@ -121,9 +96,8 @@ interrupt-parent = <&intc>; interrupts = < 0 10 4 0 11 4 0 12 4 >; compatible = "cdns,ttc"; + clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; - clocks = <&cpu_clk 3>; - clock-names = "cpu_1x"; clock-ranges; }; @@ -131,9 +105,8 @@ interrupt-parent = <&intc>; interrupts = < 0 37 4 0 38 4 0 39 4 >; compatible = "cdns,ttc"; + clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; - clocks = <&cpu_clk 3>; - clock-names = "cpu_1x"; clock-ranges; }; scutimer: scutimer@f8f00600 { @@ -141,7 +114,7 @@ interrupts = < 1 13 0x301 >; compatible = "arm,cortex-a9-twd-timer"; reg = < 0xf8f00600 0x20 >; - clocks = <&cpu_clk 1>; + clocks = <&clkc 4>; } ; }; }; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 86f44d5b0265..21aea99a067b 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -24,11 +24,11 @@ }; chosen { - bootargs = "console=ttyPS1,115200 earlyprintk"; + bootargs = "console=ttyPS0,115200 earlyprintk"; }; }; -&ps_clk { - clock-frequency = <33333330>; +&uart1 { + status = "okay"; }; diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts new file mode 100644 index 000000000000..79009e0b74b9 --- /dev/null +++ b/arch/arm/boot/dts/zynq-zc706.dts @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2011 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * Copyright (C) 2013 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Zynq ZC706 Development Board"; + compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; + + chosen { + bootargs = "console=ttyPS0,115200 earlyprintk"; + }; + +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts new file mode 100644 index 000000000000..d6acf2b1cdf4 --- /dev/null +++ b/arch/arm/boot/dts/zynq-zed.dts @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2011 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * Copyright (C) 2013 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Zynq Zed Development Board"; + compatible = "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x20000000>; + }; + + chosen { + bootargs = "console=ttyPS0,115200 earlyprintk"; + }; + +}; + +&uart1 { + status = "okay"; +}; |
