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Diffstat (limited to 'Documentation/devicetree/bindings')
51 files changed, 2112 insertions, 21 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpu-capacity.txt b/Documentation/devicetree/bindings/arm/cpu-capacity.txt new file mode 100644 index 000000000000..7809fbe0cdb7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-capacity.txt @@ -0,0 +1,236 @@ +========================================== +ARM CPUs capacity bindings +========================================== + +========================================== +1 - Introduction +========================================== + +ARM systems may be configured to have cpus with different power/performance +characteristics within the same chip. In this case, additional information has +to be made available to the kernel for it to be aware of such differences and +take decisions accordingly. + +========================================== +2 - CPU capacity definition +========================================== + +CPU capacity is a number that provides the scheduler information about CPUs +heterogeneity. Such heterogeneity can come from micro-architectural differences +(e.g., ARM big.LITTLE systems) or maximum frequency at which CPUs can run +(e.g., SMP systems with multiple frequency domains). Heterogeneity in this +context is about differing performance characteristics; this binding tries to +capture a first-order approximation of the relative performance of CPUs. + +CPU capacities are obtained by running a suitable benchmark. This binding makes +no guarantees on the validity or suitability of any particular benchmark, the +final capacity should, however, be: + +* A "single-threaded" or CPU affine benchmark +* Divided by the running frequency of the CPU executing the benchmark +* Not subject to dynamic frequency scaling of the CPU + +For the time being we however advise usage of the Dhrystone benchmark. What +above thus becomes: + +CPU capacities are obtained by running the Dhrystone benchmark on each CPU at +max frequency (with caches enabled). The obtained DMIPS score is then divided +by the frequency (in MHz) at which the benchmark has been run, so that +DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest +score obtained in the system. + +========================================== +3 - capacity-dmips-mhz +========================================== + +capacity-dmips-mhz is an optional cpu node [1] property: u32 value +representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the +maximum frequency available to the cpu is then used to calculate the capacity +value internally used by the kernel. + +capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu +node, it has to be specified for every other cpu nodes, or the system will +fall back to the default capacity value for every CPU. If cpufreq is not +available, final capacities are calculated by directly using capacity-dmips- +mhz values (normalized w.r.t. the highest value found while parsing the DT). + +=========================================== +4 - Examples +=========================================== + +Example 1 (ARM 64-bit, 6-cpu system, two clusters): +capacities-dmips-mhz are scaled w.r.t. 1024 (cpu@0 and cpu@1) +supposing cluster0@max-freq=1100 and custer1@max-freq=850, +final capacities are 1024 for cluster0 and 446 for cluster1 + +cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&A57_0>; + }; + core1 { + cpu = <&A57_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&A53_0>; + }; + core1 { + cpu = <&A53_1>; + }; + core2 { + cpu = <&A53_2>; + }; + core3 { + cpu = <&A53_3>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <100>; + exit-latency-us = <250>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + local-timer-stop; + entry-latency-us = <800>; + exit-latency-us = <700>; + min-residency-us = <2500>; + }; + }; + + A57_0: cpu@0 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A57_L2>; + clocks = <&scpi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; + }; + + A57_1: cpu@1 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x0 0x1>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A57_L2>; + clocks = <&scpi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; + }; + + A53_0: cpu@100 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; + }; + + A53_1: cpu@101 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x101>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; + }; + + A53_2: cpu@102 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x102>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; + }; + + A53_3: cpu@103 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x103>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; + }; + + A57_L2: l2-cache0 { + compatible = "cache"; + }; + + A53_L2: l2-cache1 { + compatible = "cache"; + }; +}; + +Example 2 (ARM 32-bit, 4-cpu system, two clusters, + cpus 0,1@1GHz, cpus 2,3@500MHz): +capacities-dmips-mhz are scaled w.r.t. 2 (cpu@0 and cpu@1), this means that first +cpu@0 and cpu@1 are twice fast than cpu@2 and cpu@3 (at the same frequency) + +cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + capacity-dmips-mhz = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + capacity-dmips-mhz = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x100>; + capacity-dmips-mhz = <1>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x101>; + capacity-dmips-mhz = <1>; + }; +}; + +=========================================== +5 - References +=========================================== + +[1] ARM Linux Kernel documentation - CPUs bindings + Documentation/devicetree/bindings/arm/cpus.txt diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index e6782d50cbcd..c1dcf4cade2e 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -241,6 +241,14 @@ nodes to be present and contain the properties described below. # List of phandles to idle state nodes supported by this cpu [3]. + - capacity-dmips-mhz + Usage: Optional + Value type: <u32> + Definition: + # u32 value representing CPU capacity [3] in + DMIPS/MHz, relative to highest capacity-dmips-mhz + in the system. + - rockchip,pmu Usage: optional for systems that have an "enable-method" property value of "rockchip,rk3066-smp" @@ -464,3 +472,5 @@ cpus { [2] arm/msm/qcom,kpss-acc.txt [3] ARM Linux kernel documentation - idle states bindings Documentation/devicetree/bindings/arm/idle-states.txt +[3] ARM Linux kernel documentation - cpu capacity bindings + Documentation/devicetree/bindings/arm/cpu-capacity.txt diff --git a/Documentation/devicetree/bindings/display/ht16k33.txt b/Documentation/devicetree/bindings/display/ht16k33.txt new file mode 100644 index 000000000000..8e5b30b87754 --- /dev/null +++ b/Documentation/devicetree/bindings/display/ht16k33.txt @@ -0,0 +1,42 @@ +Holtek ht16k33 RAM mapping 16*8 LED controller driver with keyscan +------------------------------------------------------------------------------- + +Required properties: +- compatible: "holtek,ht16k33" +- reg: I2C slave address of the chip. +- interrupt-parent: A phandle pointing to the interrupt controller + serving the interrupt for this chip. +- interrupts: Interrupt specification for the key pressed interrupt. +- refresh-rate-hz: Display update interval in HZ. +- debounce-delay-ms: Debouncing interval time in milliseconds. +- linux,keymap: The keymap for keys as described in the binding + document (devicetree/bindings/input/matrix-keymap.txt). + +Optional properties: +- linux,no-autorepeat: Disable keyrepeat. +- default-brightness-level: Initial brightness level [0-15] (default: 15). + +Example: + +&i2c1 { + ht16k33: ht16k33@70 { + compatible = "holtek,ht16k33"; + reg = <0x70>; + refresh-rate-hz = <20>; + debounce-delay-ms = <50>; + interrupt-parent = <&gpio4>; + interrupts = <5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; + linux,keymap = < + MATRIX_KEY(2, 0, KEY_F6) + MATRIX_KEY(3, 0, KEY_F8) + MATRIX_KEY(4, 0, KEY_F10) + MATRIX_KEY(5, 0, KEY_F4) + MATRIX_KEY(6, 0, KEY_F2) + MATRIX_KEY(2, 1, KEY_F5) + MATRIX_KEY(3, 1, KEY_F7) + MATRIX_KEY(4, 1, KEY_F9) + MATRIX_KEY(5, 1, KEY_F3) + MATRIX_KEY(6, 1, KEY_F1) + >; + }; +}; diff --git a/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt b/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt index af0b903de293..dfc14f71e81f 100644 --- a/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt +++ b/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt @@ -5,7 +5,10 @@ connected to a GPIO pin. Required properties: - compatible: Should be "linux,extcon-usb-gpio" + +Either one of id-gpio or vbus-gpio must be present. Both can be present as well. - id-gpio: gpio for USB ID pin. See gpio binding. +- vbus-gpio: gpio for USB VBUS pin. Example: Examples of extcon-usb-gpio node in dra7-evm.dts as listed below: extcon_usb1 { diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt new file mode 100644 index 000000000000..3b32ba15a717 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt @@ -0,0 +1,494 @@ +FPGA Region Device Tree Binding + +Alan Tull 2016 + + CONTENTS + - Introduction + - Terminology + - Sequence + - FPGA Region + - Supported Use Models + - Device Tree Examples + - Constraints + + +Introduction +============ + +FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in +the Device Tree. FPGA Regions provide a way to program FPGAs under device tree +control. + +This device tree binding document hits some of the high points of FPGA usage and +attempts to include terminology used by both major FPGA manufacturers. This +document isn't a replacement for any manufacturers specifications for FPGA +usage. + + +Terminology +=========== + +Full Reconfiguration + * The entire FPGA is programmed. + +Partial Reconfiguration (PR) + * A section of an FPGA is reprogrammed while the rest of the FPGA is not + affected. + * Not all FPGA's support PR. + +Partial Reconfiguration Region (PRR) + * Also called a "reconfigurable partition" + * A PRR is a specific section of a FPGA reserved for reconfiguration. + * A base (or static) FPGA image may create a set of PRR's that later may + be independently reprogrammed many times. + * The size and specific location of each PRR is fixed. + * The connections at the edge of each PRR are fixed. The image that is loaded + into a PRR must fit and must use a subset of the region's connections. + * The busses within the FPGA are split such that each region gets its own + branch that may be gated independently. + +Persona + * Also called a "partial bit stream" + * An FPGA image that is designed to be loaded into a PRR. There may be + any number of personas designed to fit into a PRR, but only one at at time + may be loaded. + * A persona may create more regions. + +FPGA Bridge + * FPGA Bridges gate bus signals between a host and FPGA. + * FPGA Bridges should be disabled while the FPGA is being programmed to + prevent spurious signals on the cpu bus and to the soft logic. + * FPGA bridges may be actual hardware or soft logic on an FPGA. + * During Full Reconfiguration, hardware bridges between the host and FPGA + will be disabled. + * During Partial Reconfiguration of a specific region, that region's bridge + will be used to gate the busses. Traffic to other regions is not affected. + * In some implementations, the FPGA Manager transparantly handles gating the + buses, eliminating the need to show the hardware FPGA bridges in the + device tree. + * An FPGA image may create a set of reprogrammable regions, each having its + own bridge and its own split of the busses in the FPGA. + +FPGA Manager + * An FPGA Manager is a hardware block that programs an FPGA under the control + of a host processor. + +Base Image + * Also called the "static image" + * An FPGA image that is designed to do full reconfiguration of the FPGA. + * A base image may set up a set of partial reconfiguration regions that may + later be reprogrammed. + + ---------------- ---------------------------------- + | Host CPU | | FPGA | + | | | | + | ----| | ----------- -------- | + | | H | | |==>| Bridge0 |<==>| PRR0 | | + | | W | | | ----------- -------- | + | | | | | | + | | B |<=====>|<==| ----------- -------- | + | | R | | |==>| Bridge1 |<==>| PRR1 | | + | | I | | | ----------- -------- | + | | D | | | | + | | G | | | ----------- -------- | + | | E | | |==>| Bridge2 |<==>| PRR2 | | + | ----| | ----------- -------- | + | | | | + ---------------- ---------------------------------- + +Figure 1: An FPGA set up with a base image that created three regions. Each +region (PRR0-2) gets its own split of the busses that is independently gated by +a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be +reprogrammed independently while the rest of the system continues to function. + + +Sequence +======== + +When a DT overlay that targets a FPGA Region is applied, the FPGA Region will +do the following: + + 1. Disable appropriate FPGA bridges. + 2. Program the FPGA using the FPGA manager. + 3. Enable the FPGA bridges. + 4. The Device Tree overlay is accepted into the live tree. + 5. Child devices are populated. + +When the overlay is removed, the child nodes will be removed and the FPGA Region +will disable the bridges. + + +FPGA Region +=========== + +FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA +Region brings together the elements needed to program on a running system and +add the child devices: + + * FPGA Manager + * FPGA Bridges + * image-specific information needed to to the programming. + * child nodes + +The intended use is that a Device Tree overlay (DTO) can be used to reprogram an +FPGA while an operating system is running. + +An FPGA Region that exists in the live Device Tree reflects the current state. +If the live tree shows a "firmware-name" property or child nodes under a FPGA +Region, the FPGA already has been programmed. A DTO that targets a FPGA Region +and adds the "firmware-name" property is taken as a request to reprogram the +FPGA. After reprogramming is successful, the overlay is accepted into the live +tree. + +The base FPGA Region in the device tree represents the FPGA and supports full +reconfiguration. It must include a phandle to an FPGA Manager. The base +FPGA region will be the child of one of the hardware bridges (the bridge that +allows register access) between the cpu and the FPGA. If there are more than +one bridge to control during FPGA programming, the region will also contain a +list of phandles to the additional hardware FPGA Bridges. + +For partial reconfiguration (PR), each PR region will have an FPGA Region. +These FPGA regions are children of FPGA bridges which are then children of the +base FPGA region. The "Full Reconfiguration to add PRR's" example below shows +this. + +If an FPGA Region does not specify a FPGA Manager, it will inherit the FPGA +Manager specified by its ancestor FPGA Region. This supports both the case +where the same FPGA Manager is used for all of a FPGA as well the case where +a different FPGA Manager is used for each region. + +FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents +shutting down bridges that are upstream from the other active regions while one +region is getting reconfigured (see Figure 1 above). During PR, the FPGA's +hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges +within the static image of the FPGA. + +Required properties: +- compatible : should contain "fpga-region" +- fpga-mgr : should contain a phandle to an FPGA Manager. Child FPGA Regions + inherit this property from their ancestor regions. A fpga-mgr property + in a region will override any inherited FPGA manager. +- #address-cells, #size-cells, ranges : must be present to handle address space + mapping for child nodes. + +Optional properties: +- firmware-name : should contain the name of an FPGA image file located on the + firmware search path. If this property shows up in a live device tree + it indicates that the FPGA has already been programmed with this image. + If this property is in an overlay targeting a FPGA region, it is a + request to program the FPGA with that image. +- fpga-bridges : should contain a list of phandles to FPGA Bridges that must be + controlled during FPGA programming along with the parent FPGA bridge. + This property is optional if the FPGA Manager handles the bridges. + If the fpga-region is the child of a fpga-bridge, the list should not + contain the parent bridge. +- partial-fpga-config : boolean, set if partial reconfiguration is to be done, + otherwise full reconfiguration is done. +- external-fpga-config : boolean, set if the FPGA has already been configured + prior to OS boot up. +- region-unfreeze-timeout-us : The maximum time in microseconds to wait for + bridges to successfully become enabled after the region has been + programmed. +- region-freeze-timeout-us : The maximum time in microseconds to wait for + bridges to successfully become disabled before the region has been + programmed. +- child nodes : devices in the FPGA after programming. + +In the example below, when an overlay is applied targeting fpga-region0, +fpga_mgr is used to program the FPGA. Two bridges are controlled during +programming: the parent fpga_bridge0 and fpga_bridge1. Because the region is +the child of fpga_bridge0, only fpga_bridge1 needs to be specified in the +fpga-bridges property. During programming, these bridges are disabled, the +firmware specified in the overlay is loaded to the FPGA using the FPGA manager +specified in the region. If FPGA programming succeeds, the bridges are +reenabled and the overlay makes it into the live device tree. The child devices +are then populated. If FPGA programming fails, the bridges are left disabled +and the overlay is rejected. The overlay's ranges property maps the lwhps +bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by +the two child devices. + +Example: +Base tree contains: + + fpga_mgr: fpga-mgr@ff706000 { + compatible = "altr,socfpga-fpga-mgr"; + reg = <0xff706000 0x1000 + 0xffb90000 0x20>; + interrupts = <0 175 4>; + }; + + fpga_bridge0: fpga-bridge@ff400000 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + reg = <0xff400000 0x100000>; + resets = <&rst LWHPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + fpga_region0: fpga-region0 { + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr>; + }; + }; + + fpga_bridge1: fpga-bridge@ff500000 { + compatible = "altr,socfpga-hps2fpga-bridge"; + reg = <0xff500000 0x10000>; + resets = <&rst HPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + }; + +Overlay contains: + +/dts-v1/ /plugin/; +/ { + fragment@0 { + target = <&fpga_region0>; + #address-cells = <1>; + #size-cells = <1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <1>; + + firmware-name = "soc_system.rbf"; + fpga-bridges = <&fpga_bridge1>; + ranges = <0x20000 0xff200000 0x100000>, + <0x0 0xc0000000 0x20000000>; + + gpio@10040 { + compatible = "altr,pio-1.0"; + reg = <0x10040 0x20>; + altr,gpio-bank-width = <4>; + #gpio-cells = <2>; + clocks = <2>; + gpio-controller; + }; + + onchip-memory { + device_type = "memory"; + compatible = "altr,onchipmem-15.1"; + reg = <0x0 0x10000>; + }; + }; + }; +}; + + +Supported Use Models +==================== + +In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and +a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some +uses are specific to a FPGA device. + + * No FPGA Bridges + In this case, the FPGA Manager which programs the FPGA also handles the + bridges behind the scenes. No FPGA Bridge devices are needed for full + reconfiguration. + + * Full reconfiguration with hardware bridges + In this case, there are hardware bridges between the processor and FPGA that + need to be controlled during full reconfiguration. Before the overlay is + applied, the live DT must include the FPGA Manager, FPGA Bridges, and a + FPGA Region. The FPGA Region is the child of the bridge that allows + register access to the FPGA. Additional bridges may be listed in a + fpga-bridges property in the FPGA region or in the device tree overlay. + + * Partial reconfiguration with bridges in the FPGA + In this case, the FPGA will have one or more PRR's that may be programmed + separately while the rest of the FPGA can remain active. To manage this, + bridges need to exist in the FPGA that can gate the buses going to each FPGA + region while the buses are enabled for other sections. Before any partial + reconfiguration can be done, a base FPGA image must be loaded which includes + PRR's with FPGA bridges. The device tree should have a FPGA region for each + PRR. + +Device Tree Examples +==================== + +The intention of this section is to give some simple examples, focusing on +the placement of the elements detailed above, especially: + * FPGA Manager + * FPGA Bridges + * FPGA Region + * ranges + * target-path or target + +For the purposes of this section, I'm dividing the Device Tree into two parts, +each with its own requirements. The two parts are: + * The live DT prior to the overlay being added + * The DT overlay + +The live Device Tree must contain an FPGA Region, an FPGA Manager, and any FPGA +Bridges. The FPGA Region's "fpga-mgr" property specifies the manager by phandle +to handle programming the FPGA. If the FPGA Region is the child of another FPGA +Region, the parent's FPGA Manager is used. If FPGA Bridges need to be involved, +they are specified in the FPGA Region by the "fpga-bridges" property. During +FPGA programming, the FPGA Region will disable the bridges that are in its +"fpga-bridges" list and will re-enable them after FPGA programming has +succeeded. + +The Device Tree Overlay will contain: + * "target-path" or "target" + The insertion point where the the contents of the overlay will go into the + live tree. target-path is a full path, while target is a phandle. + * "ranges" + The address space mapping from processor to FPGA bus(ses). + * "firmware-name" + Specifies the name of the FPGA image file on the firmware search + path. The search path is described in the firmware class documentation. + * "partial-fpga-config" + This binding is a boolean and should be present if partial reconfiguration + is to be done. + * child nodes corresponding to hardware that will be loaded in this region of + the FPGA. + +Device Tree Example: Full Reconfiguration without Bridges +========================================================= + +Live Device Tree contains: + fpga_mgr0: fpga-mgr@f8007000 { + compatible = "xlnx,zynq-devcfg-1.0"; + reg = <0xf8007000 0x100>; + interrupt-parent = <&intc>; + interrupts = <0 8 4>; + clocks = <&clkc 12>; + clock-names = "ref_clk"; + syscon = <&slcr>; + }; + + fpga_region0: fpga-region0 { + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr0>; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + }; + +DT Overlay contains: +/dts-v1/ /plugin/; +/ { +fragment@0 { + target = <&fpga_region0>; + #address-cells = <1>; + #size-cells = <1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <1>; + + firmware-name = "zynq-gpio.bin"; + + gpio1: gpio@40000000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = <0x40000000 0x10000>; + gpio-controller; + #gpio-cells = <0x2>; + xlnx,gpio-width= <0x6>; + }; + }; +}; + +Device Tree Example: Full Reconfiguration to add PRR's +====================================================== + +The base FPGA Region is specified similar to the first example above. + +This example programs the FPGA to have two regions that can later be partially +configured. Each region has its own bridge in the FPGA fabric. + +DT Overlay contains: +/dts-v1/ /plugin/; +/ { + fragment@0 { + target = <&fpga_region0>; + #address-cells = <1>; + #size-cells = <1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <1>; + + firmware-name = "base.rbf"; + + fpga-bridge@4400 { + compatible = "altr,freeze-bridge"; + reg = <0x4400 0x10>; + + fpga_region1: fpga-region1 { + compatible = "fpga-region"; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + }; + }; + + fpga-bridge@4420 { + compatible = "altr,freeze-bridge"; + reg = <0x4420 0x10>; + + fpga_region2: fpga-region2 { + compatible = "fpga-region"; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + }; + }; + }; + }; +}; + +Device Tree Example: Partial Reconfiguration +============================================ + +This example reprograms one of the PRR's set up in the previous example. + +The sequence that occurs when this overlay is similar to the above, the only +differences are that the FPGA is partially reconfigured due to the +"partial-fpga-config" boolean and the only bridge that is controlled during +programming is the FPGA based bridge of fpga_region1. + +/dts-v1/ /plugin/; +/ { + fragment@0 { + target = <&fpga_region1>; + #address-cells = <1>; + #size-cells = <1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <1>; + + firmware-name = "soc_image2.rbf"; + partial-fpga-config; + + gpio@10040 { + compatible = "altr,pio-1.0"; + reg = <0x10040 0x20>; + clocks = <0x2>; + altr,gpio-bank-width = <0x4>; + resetvalue = <0x0>; + #gpio-cells = <0x2>; + gpio-controller; + }; + }; + }; +}; + +Constraints +=========== + +It is beyond the scope of this document to fully describe all the FPGA design +constraints required to make partial reconfiguration work[1] [2] [3], but a few +deserve quick mention. + +A persona must have boundary connections that line up with those of the partion +or region it is designed to go into. + +During programming, transactions through those connections must be stopped and +the connections must be held at a fixed logic level. This can be achieved by +FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration. + +-- +[1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf +[2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf +[3] http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf diff --git a/Documentation/devicetree/bindings/hwmon/mcp3021.txt b/Documentation/devicetree/bindings/hwmon/mcp3021.txt new file mode 100644 index 000000000000..294318ba6914 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/mcp3021.txt @@ -0,0 +1,21 @@ +mcp3021 properties + +Required properties: +- compatible: Must be one of the following: + - "microchip,mcp3021" for mcp3021 + - "microchip,mcp3221" for mcp3221 +- reg: I2C address + +Optional properties: + +- reference-voltage-microvolt + Reference voltage in microvolt (uV) + +Example: + +mcp3021@4d { + compatible = "microchip,mcp3021"; + reg = <0x4d>; + + reference-voltage-microvolt = <4500000>; /* 4.5 V */ +}; diff --git a/Documentation/devicetree/bindings/hwmon/tmp108.txt b/Documentation/devicetree/bindings/hwmon/tmp108.txt new file mode 100644 index 000000000000..8c4b10df86d9 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/tmp108.txt @@ -0,0 +1,14 @@ +TMP108 temperature sensor +------------------------- + +This device supports I2C only. + +Requires node properties: +- compatible : "ti,tmp108" +- reg : the I2C address of the device. This is 0x48, 0x49, 0x4a, or 0x4b. + +Example: + tmp108@48 { + compatible = "ti,tmp108"; + reg = <0x48>; + }; diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index fbbad6446741..df720ca00fcf 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -39,11 +39,13 @@ dallas,ds75 Digital Thermometer and Thermostat dlg,da9053 DA9053: flexible system level PMIC with multicore support dlg,da9063 DA9063: system PMIC for quad-core application processors domintech,dmard09 DMARD09: 3-axis Accelerometer +domintech,dmard10 DMARD10: 3-axis Accelerometer epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer fsl,mc13892 MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51 +fsl,mma7660 MMA7660FC: 3-Axis Orientation/Motion Detection Sensor fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer fsl,mpl3115 MPL3115: Absolute Digital Pressure Sensor fsl,mpr121 MPR121: Proximity Capacitive Touch Sensor Controller @@ -57,6 +59,7 @@ maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface mc,rv3029c2 Real Time Clock Module with I2C-Bus mcube,mc3230 mCube 3-axis 8-bit digital accelerometer +memsic,mxc6225 MEMSIC 2-axis 8-bit digital accelerometer microchip,mcp4531-502 Microchip 7-bit Single I2C Digital Potentiometer (5k) microchip,mcp4531-103 Microchip 7-bit Single I2C Digital Potentiometer (10k) microchip,mcp4531-503 Microchip 7-bit Single I2C Digital Potentiometer (50k) @@ -121,6 +124,11 @@ microchip,mcp4662-502 Microchip 8-bit Dual I2C Digital Potentiometer with NV Mem microchip,mcp4662-103 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k) microchip,mcp4662-503 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k) microchip,mcp4662-104 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k) +microchip,tc654 PWM Fan Speed Controller With Fan Fault Detection +microchip,tc655 PWM Fan Speed Controller With Fan Fault Detection +miramems,da226 MiraMEMS DA226 2-axis 14-bit digital accelerometer +miramems,da280 MiraMEMS DA280 3-axis 14-bit digital accelerometer +miramems,da311 MiraMEMS DA311 3-axis 12-bit digital accelerometer national,lm63 Temperature sensor with integrated fan control national,lm75 I2C TEMP SENSOR national,lm80 Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor @@ -146,6 +154,7 @@ ricoh,rv5c387a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) sgx,vz89x SGX Sensortech VZ89X Sensors sii,s35390a 2-wire CMOS real-time clock +silabs,si7020 Relative Humidity and Temperature Sensors skyworks,sky81452 Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply st,24c256 i2c serial eeprom (24cxx) st,m41t00 Serial real-time clock (RTC) diff --git a/Documentation/devicetree/bindings/iio/adc/envelope-detector.txt b/Documentation/devicetree/bindings/iio/adc/envelope-detector.txt new file mode 100644 index 000000000000..27544bdd4478 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/envelope-detector.txt @@ -0,0 +1,54 @@ +Bindings for ADC envelope detector using a DAC and a comparator + +The DAC is used to find the peak level of an alternating voltage input +signal by a binary search using the output of a comparator wired to +an interrupt pin. Like so: + _ + | \ + input +------>-------|+ \ + | \ + .-------. | }---. + | | | / | + | dac|-->--|- / | + | | |_/ | + | | | + | | | + | irq|------<-------' + | | + '-------' + +Required properties: +- compatible: Should be "axentia,tse850-envelope-detector" +- io-channels: Channel node of the dac to be used for comparator input. +- io-channel-names: Should be "dac". +- interrupt specification for one client interrupt, + see ../../interrupt-controller/interrupts.txt for details. +- interrupt-names: Should be "comp". + +Example: + + &i2c { + dpot: mcp4651-104@28 { + compatible = "microchip,mcp4651-104"; + reg = <0x28>; + #io-channel-cells = <1>; + }; + }; + + dac: dac { + compatible = "dpot-dac"; + vref-supply = <®_3v3>; + io-channels = <&dpot 0>; + io-channel-names = "dpot"; + #io-channel-cells = <1>; + }; + + envelope-detector { + compatible = "axentia,tse850-envelope-detector"; + io-channels = <&dac 0>; + io-channel-names = "dac"; + + interrupt-parent = <&gpio>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "comp"; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt new file mode 100644 index 000000000000..49ed82e89870 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt @@ -0,0 +1,83 @@ +STMicroelectronics STM32 ADC device driver + +STM32 ADC is a successive approximation analog-to-digital converter. +It has several multiplexed input channels. Conversions can be performed +in single, continuous, scan or discontinuous mode. Result of the ADC is +stored in a left-aligned or right-aligned 32-bit data register. +Conversions can be launched in software or using hardware triggers. + +The analog watchdog feature allows the application to detect if the input +voltage goes beyond the user-defined, higher or lower thresholds. + +Each STM32 ADC block can have up to 3 ADC instances. + +Each instance supports two contexts to manage conversions, each one has its +own configurable sequence and trigger: +- regular conversion can be done in sequence, running in background +- injected conversions have higher priority, and so have the ability to + interrupt regular conversion sequence (either triggered in SW or HW). + Regular sequence is resumed, in case it has been interrupted. + +Contents of a stm32 adc root node: +----------------------------------- +Required properties: +- compatible: Should be "st,stm32f4-adc-core". +- reg: Offset and length of the ADC block register set. +- interrupts: Must contain the interrupt for ADC block. +- clocks: Clock for the analog circuitry (common to all ADCs). +- clock-names: Must be "adc". +- interrupt-controller: Identifies the controller node as interrupt-parent +- vref-supply: Phandle to the vref input analog reference voltage. +- #interrupt-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; + +Optional properties: +- A pinctrl state named "default" for each ADC channel may be defined to set + inX ADC pins in mode of operation for analog input on external pin. + +Contents of a stm32 adc child node: +----------------------------------- +An ADC block node should contain at least one subnode, representing an +ADC instance available on the machine. + +Required properties: +- compatible: Should be "st,stm32f4-adc". +- reg: Offset of ADC instance in ADC block (e.g. may be 0x0, 0x100, 0x200). +- clocks: Input clock private to this ADC instance. +- interrupt-parent: Phandle to the parent interrupt controller. +- interrupts: IRQ Line for the ADC (e.g. may be 0 for adc@0, 1 for adc@100 or + 2 for adc@200). +- st,adc-channels: List of single-ended channels muxed for this ADC. + It can have up to 16 channels, numbered from 0 to 15 (resp. for in0..in15). +- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in + Documentation/devicetree/bindings/iio/iio-bindings.txt + +Example: + adc: adc@40012000 { + compatible = "st,stm32f4-adc-core"; + reg = <0x40012000 0x400>; + interrupts = <18>; + clocks = <&rcc 0 168>; + clock-names = "adc"; + vref-supply = <®_vref>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&adc3_in8_pin>; + + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "st,stm32f4-adc"; + #io-channel-cells = <1>; + reg = <0x0>; + clocks = <&rcc 0 168>; + interrupt-parent = <&adc>; + interrupts = <0>; + st,adc-channels = <8>; + }; + ... + other adc child nodes follow... + }; diff --git a/Documentation/devicetree/bindings/iio/adc/ti-adc161s626.txt b/Documentation/devicetree/bindings/iio/adc/ti-adc161s626.txt index 9ed2315781e4..3d25011f0c99 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti-adc161s626.txt +++ b/Documentation/devicetree/bindings/iio/adc/ti-adc161s626.txt @@ -3,6 +3,7 @@ Required properties: - compatible: Should be "ti,adc141s626" or "ti,adc161s626" - reg: spi chip select number for the device + - vdda-supply: supply voltage to VDDA pin Recommended properties: - spi-max-frequency: Definition as per @@ -11,6 +12,7 @@ Recommended properties: Example: adc@0 { compatible = "ti,adc161s626"; + vdda-supply = <&vdda_fixed>; reg = <0>; spi-max-frequency = <4300000>; }; diff --git a/Documentation/devicetree/bindings/iio/dac/dpot-dac.txt b/Documentation/devicetree/bindings/iio/dac/dpot-dac.txt new file mode 100644 index 000000000000..fdf47a01bfef --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/dpot-dac.txt @@ -0,0 +1,41 @@ +Bindings for DAC emulation using a digital potentiometer + +It is assumed that the dpot is used as a voltage divider between the +current dpot wiper setting and the maximum resistance of the dpot. The +divided voltage is provided by a vref regulator. + + .------. + .-----------. | | + | vref |--' .---. + | regulator |--. | | + '-----------' | | d | + | | p | + | | o | wiper + | | t |<---------+ + | | | + | '---' dac output voltage + | | + '------+------------+ + +Required properties: +- compatible: Should be "dpot-dac" +- vref-supply: The regulator supplying the voltage divider. +- io-channels: Channel node of the dpot to be used for the voltage division. +- io-channel-names: Should be "dpot". + +Example: + + &i2c { + dpot: mcp4651-503@28 { + compatible = "microchip,mcp4651-503"; + reg = <0x28>; + #io-channel-cells = <1>; + }; + }; + + dac { + compatible = "dpot-dac"; + vref-supply = <®_3v3>; + io-channels = <&dpot 0>; + io-channel-names = "dpot"; + }; diff --git a/Documentation/devicetree/bindings/iio/dac/mcp4725.txt b/Documentation/devicetree/bindings/iio/dac/mcp4725.txt new file mode 100644 index 000000000000..1bc6c093fbfe --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/mcp4725.txt @@ -0,0 +1,35 @@ +Microchip mcp4725 and mcp4726 DAC device driver + +Required properties: + - compatible: Must be "microchip,mcp4725" or "microchip,mcp4726" + - reg: Should contain the DAC I2C address + - vdd-supply: Phandle to the Vdd power supply. This supply is used as a + voltage reference on mcp4725. It is used as a voltage reference on + mcp4726 if there is no vref-supply specified. + +Optional properties (valid only for mcp4726): + - vref-supply: Optional phandle to the Vref power supply. Vref pin is + used as a voltage reference when this supply is specified. + - microchip,vref-buffered: Boolean to enable buffering of the external + Vref pin. This boolean is not valid without the vref-supply. Quoting + the datasheet: This is offered in cases where the reference voltage + does not have the current capability not to drop its voltage when + connected to the internal resistor ladder circuit. + +Examples: + + /* simple mcp4725 */ + mcp4725@60 { + compatible = "microchip,mcp4725"; + reg = <0x60>; + vdd-supply = <&vdac_vdd>; + }; + + /* mcp4726 with the buffered external reference voltage */ + mcp4726@60 { + compatible = "microchip,mcp4726"; + reg = <0x60>; + vdd-supply = <&vdac_vdd>; + vref-supply = <&vdac_vref>; + microchip,vref-buffered; + }; diff --git a/Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.txt b/Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.txt new file mode 100644 index 000000000000..b0d3b59966bc --- /dev/null +++ b/Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.txt @@ -0,0 +1,46 @@ +Invensense MPU-3050 Gyroscope device tree bindings + +Required properties: + - compatible : should be "invensense,mpu3050" + - reg : the I2C address of the sensor + +Optional properties: + - interrupt-parent : should be the phandle for the interrupt controller + - interrupts : interrupt mapping for the trigger interrupt from the + internal oscillator. The following IRQ modes are supported: + IRQ_TYPE_EDGE_RISING, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH and + IRQ_TYPE_LEVEL_LOW. The driver should detect and configure the hardware + for the desired interrupt type. + - vdd-supply : supply regulator for the main power voltage. + - vlogic-supply : supply regulator for the signal voltage. + - mount-matrix : see iio/mount-matrix.txt + +Optional subnodes: + - The MPU-3050 will pass through and forward the I2C signals from the + incoming I2C bus, alternatively drive traffic to a slave device (usually + an accelerometer) on its own initiative. Therefore is supports a subnode + i2c gate node. For details see: i2c/i2c-gate.txt + +Example: + +mpu3050@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + interrupt-parent = <&foo>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&bar>; + vlogic-supply = <&baz>; + + /* External I2C interface */ + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + fnord@18 { + compatible = "fnord"; + reg = <0x18>; + interrupt-parent = <&foo>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/iio/humidity/hts221.txt b/Documentation/devicetree/bindings/iio/humidity/hts221.txt new file mode 100644 index 000000000000..b20ab9c12080 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/humidity/hts221.txt @@ -0,0 +1,22 @@ +* HTS221 STM humidity + temperature sensor + +Required properties: +- compatible: should be "st,hts221" +- reg: i2c address of the sensor / spi cs line + +Optional properties: +- interrupt-parent: should be the phandle for the interrupt controller +- interrupts: interrupt mapping for IRQ. It should be configured with + flags IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_EDGE_RISING. + + Refer to interrupt-controller/interrupts.txt for generic interrupt + client node bindings. + +Example: + +hts221@5f { + compatible = "st,hts221"; + reg = <0x5f>; + interrupt-parent = <&gpio0>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; +}; diff --git a/Documentation/devicetree/bindings/iio/light/isl29018.txt b/Documentation/devicetree/bindings/iio/light/isl29018.txt new file mode 100644 index 000000000000..425ab459e209 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/light/isl29018.txt @@ -0,0 +1,28 @@ +* ISL 29018/29023/29035 I2C ALS, Proximity, and Infrared sensor + +Required properties: + + - compatible: Should be one of + "isil,isl29018" + "isil,isl29023" + "isil,isl29035" + - reg: the I2C address of the device + +Optional properties: + + - interrupt-parent: should be the phandle for the interrupt controller + - interrupts: the sole interrupt generated by the device + + Refer to interrupt-controller/interrupts.txt for generic interrupt client + node bindings. + + - vcc-supply: phandle to the regulator that provides power to the sensor. + +Example: + +isl29018@44 { + compatible = "isil,isl29018"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/Documentation/devicetree/bindings/iio/light/tsl2583.txt b/Documentation/devicetree/bindings/iio/light/tsl2583.txt new file mode 100644 index 000000000000..8e2066c83f70 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/light/tsl2583.txt @@ -0,0 +1,26 @@ +* TAOS TSL 2580/2581/2583 ALS sensor + +Required properties: + + - compatible: Should be one of + "amstaos,tsl2580" + "amstaos,tsl2581" + "amstaos,tsl2583" + - reg: the I2C address of the device + +Optional properties: + + - interrupt-parent: should be the phandle for the interrupt controller + - interrupts: the sole interrupt generated by the device + + Refer to interrupt-controller/interrupts.txt for generic interrupt client + node bindings. + + - vcc-supply: phandle to the regulator that provides power to the sensor. + +Example: + +tsl2581@29 { + compatible = "amstaos,tsl2581"; + reg = <0x29>; +}; diff --git a/Documentation/devicetree/bindings/iio/potentiostat/lmp91000.txt b/Documentation/devicetree/bindings/iio/potentiostat/lmp91000.txt new file mode 100644 index 000000000000..b9b621e94cd7 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/potentiostat/lmp91000.txt @@ -0,0 +1,30 @@ +* Texas Instruments LMP91000 potentiostat + +http://www.ti.com/lit/ds/symlink/lmp91000.pdf + +Required properties: + + - compatible: should be "ti,lmp91000" + - reg: the I2C address of the device + - io-channels: the phandle of the iio provider + + - ti,external-tia-resistor: if the property ti,tia-gain-ohm is not defined this + needs to be set to signal that an external resistor value is being used. + +Optional properties: + + - ti,tia-gain-ohm: ohm value of the internal resistor for the transimpedance + amplifier. Must be 2750, 3500, 7000, 14000, 35000, 120000, or 350000 ohms. + + - ti,rload-ohm: ohm value of the internal resistor load applied to the gas + sensor. Must be 10, 33, 50, or 100 (default) ohms. + +Example: + +lmp91000@48 { + compatible = "ti,lmp91000"; + reg = <0x48>; + ti,tia-gain-ohm = <7500>; + ti,rload = <100>; + io-channels = <&adc>; +}; diff --git a/Documentation/devicetree/bindings/iio/st-sensors.txt b/Documentation/devicetree/bindings/iio/st-sensors.txt index e41fe340162b..c040c9ad1889 100644 --- a/Documentation/devicetree/bindings/iio/st-sensors.txt +++ b/Documentation/devicetree/bindings/iio/st-sensors.txt @@ -42,6 +42,7 @@ Accelerometers: - st,lsm303agr-accel - st,lis2dh12-accel - st,h3lis331dl-accel +- st,lng2dm-accel Gyroscopes: - st,l3g4200d-gyro diff --git a/Documentation/devicetree/bindings/nvmem/brcm,ocotp.txt b/Documentation/devicetree/bindings/nvmem/brcm,ocotp.txt new file mode 100644 index 000000000000..6462e12d8de6 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/brcm,ocotp.txt @@ -0,0 +1,17 @@ +Broadcom OTP memory controller + +Required Properties: +- compatible: "brcm,ocotp" for the first generation Broadcom OTPC which is used + in Cygnus and supports 32 bit read/write. Use "brcm,ocotp-v2" for the second + generation Broadcom OTPC which is used in SoC's such as Stingray and supports + 64-bit read/write. +- reg: Base address of the OTP controller. +- brcm,ocotp-size: Amount of memory available, in 32 bit words + +Example: + +otp: otp@0301c800 { + compatible = "brcm,ocotp"; + reg = <0x0301c800 0x2c>; + brcm,ocotp-size = <2048>; +}; diff --git a/Documentation/devicetree/bindings/nvmem/lpc1850-otp.txt b/Documentation/devicetree/bindings/nvmem/lpc1850-otp.txt new file mode 100644 index 000000000000..853b6a754644 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/lpc1850-otp.txt @@ -0,0 +1,20 @@ +* NXP LPC18xx OTP memory + +Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices. + +Required properties: + - compatible: Should be "nxp,lpc1850-otp" + - reg: Must contain an entry with the physical base address and length + for each entry in reg-names. + - address-cells: must be set to 1. + - size-cells: must be set to 1. + +See nvmem.txt for more information. + +Example: + otp: otp@40045000 { + compatible = "nxp,lpc1850-otp"; + reg = <0x40045000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/phy/meson-usb2-phy.txt b/Documentation/devicetree/bindings/phy/meson8b-usb2-phy.txt index 9da5ea234154..5fa73b9d20f5 100644 --- a/Documentation/devicetree/bindings/phy/meson-usb2-phy.txt +++ b/Documentation/devicetree/bindings/phy/meson8b-usb2-phy.txt @@ -1,4 +1,4 @@ -* Amlogic USB2 PHY +* Amlogic Meson8b and GXBB USB2 PHY Required properties: - compatible: Depending on the platform this should be one of: @@ -16,10 +16,10 @@ Optional properties: Example: -usb0_phy: usb_phy@0 { +usb0_phy: usb-phy@c0000000 { compatible = "amlogic,meson-gxbb-usb2-phy"; #phy-cells = <0>; - reg = <0x0 0x0 0x0 0x20>; + reg = <0x0 0xc0000000 0x0 0x20>; resets = <&reset RESET_USB_OTG>; clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; clock-names = "usb_general", "usb"; diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt index bf2411f366e5..2a42a323fa1a 100644 --- a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt +++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt @@ -6,6 +6,7 @@ Main node required properties: - compatible : value should be as follows: (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset + (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset - sas-addr : array of 8 bytes for host SAS address - reg : Address and length of the SAS register - hisilicon,sas-syscon: phandle of syscon used for sas control diff --git a/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt b/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt new file mode 100644 index 000000000000..5b9b38f578bb --- /dev/null +++ b/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt @@ -0,0 +1,88 @@ +Devicetree bindings for the Axentia TSE-850 audio complex + +Required properties: + - compatible: "axentia,tse850-pcm5142" + - axentia,ssc-controller: The phandle of the atmel SSC controller used as + cpu dai. + - axentia,audio-codec: The phandle of the PCM5142 codec. + - axentia,add-gpios: gpio specifier that controls the mixer. + - axentia,loop1-gpios: gpio specifier that controls loop relays on channel 1. + - axentia,loop2-gpios: gpio specifier that controls loop relays on channel 2. + - axentia,ana-supply: Regulator that supplies the output amplifier. Must + support voltages in the 2V - 20V range, in 1V steps. + +The schematics explaining the gpios are as follows: + + loop1 relays + IN1 +---o +------------+ o---+ OUT1 + \ / + + + + | / | + +--o +--. | + | add | | + | V | + | .---. | + DAC +----------->|Sum|---+ + | '---' | + | | + + + + + IN2 +---o--+------------+--o---+ OUT2 + loop2 relays + +The 'loop1' gpio pin controlls two relays, which are either in loop position, +meaning that input and output are directly connected, or they are in mixer +position, meaning that the signal is passed through the 'Sum' mixer. Similarly +for 'loop2'. + +In the above, the 'loop1' relays are inactive, thus feeding IN1 to the mixer +(if 'add' is active) and feeding the mixer output to OUT1. The 'loop2' relays +are active, short-cutting the TSE-850 from channel 2. IN1, IN2, OUT1 and OUT2 +are TSE-850 connectors and DAC is the PCB name of the (filtered) output from +the PCM5142 codec. + +Example: + + &i2c { + codec: pcm5142@4c { + compatible = "ti,pcm5142"; + + reg = <0x4c>; + + AVDD-supply = <®_3v3>; + DVDD-supply = <®_3v3>; + CPVDD-supply = <®_3v3>; + + clocks = <&sck>; + + pll-in = <3>; + pll-out = <6>; + }; + }; + + ana: ana-reg { + compatible = "pwm-regulator"; + + regulator-name = "ANA"; + + pwms = <&pwm0 2 1000 PWM_POLARITY_INVERTED>; + pwm-dutycycle-unit = <1000>; + pwm-dutycycle-range = <100 1000>; + + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <20000000>; + regulator-ramp-delay = <1000>; + }; + + sound { + compatible = "axentia,tse850-pcm5142"; + + axentia,ssc-controller = <&ssc0>; + axentia,audio-codec = <&codec>; + + axentia,add-gpios = <&pioA 8 GPIO_ACTIVE_LOW>; + axentia,loop1-gpios = <&pioA 10 GPIO_ACTIVE_LOW>; + axentia,loop2-gpios = <&pioA 11 GPIO_ACTIVE_LOW>; + + axentia,ana-supply = <&ana>; + }; diff --git a/Documentation/devicetree/bindings/sound/cs35l34.txt b/Documentation/devicetree/bindings/sound/cs35l34.txt new file mode 100644 index 000000000000..b218ead2e68e --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cs35l34.txt @@ -0,0 +1,64 @@ +CS35L34 Speaker Amplifier + +Required properties: + + - compatible : "cirrus,cs35l34" + + - reg : the I2C address of the device for I2C. + + - VA-supply, VP-supply : power supplies for the device, + as covered in + Documentation/devicetree/bindings/regulator/regulator.txt. + + - cirrus,boost-vtge-millivolt : Boost Voltage Value. Configures the boost + converter's output voltage in mV. The range is from VP to 8V with + increments of 100mV. + + - cirrus,boost-nanohenry: Inductor value for boost converter. The value is + in nH and they can be values of 1000nH, 1100nH, 1200nH, 1500nH, and 2200nH. + +Optional properties: + + - reset-gpios: GPIO used to reset the amplifier. + + - interrupt-parent : Specifies the phandle of the interrupt controller to + which the IRQs from CS35L34 are delivered to. + - interrupts : IRQ line info CS35L34. + (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + for further information relating to interrupt properties) + + - cirrus,boost-peak-milliamp : Boost converter peak current limit in mA. The + range starts at 1200mA and goes to a maximum of 3840mA with increments of + 80mA. The default value is 2480mA. + + - cirrus,i2s-sdinloc : ADSP SDIN I2S channel location. Indicates whether the + received mono data is in the left or right portion of the I2S frame + according to the AD0 pin or directly via this configuration. + 0x0 (Default) = Selected by AD0 input (if AD0 = LOW, use left channel), + 0x2 = Left, + 0x1 = Selected by the inversion of the AD0 input (if AD0 = LOW, use right + channel), + 0x3 = Right. + + - cirrus,gain-zc-disable: Boolean property. If set, the gain change will take + effect without waiting for a zero cross. + + - cirrus,tdm-rising-edge: Boolean property. If set, data is on the rising edge of + SCLK. Otherwise, data is on the falling edge of SCLK. + + +Example: + +cs35l34: cs35l34@40 { + compatible = "cirrus,cs35l34"; + reg = <0x40>; + + interrupt-parent = <&gpio8>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&gpio 10 0>; + + cirrus,boost-vtge-milltvolt = <8000>; /* 8V */ + cirrus,boost-ind-nanohenry = <1000>; /* 1uH */ + cirrus,boost-peak-milliamp = <3000>; /* 3A */ +}; diff --git a/Documentation/devicetree/bindings/sound/cs42l42.txt b/Documentation/devicetree/bindings/sound/cs42l42.txt new file mode 100644 index 000000000000..9a2c5e2423d5 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cs42l42.txt @@ -0,0 +1,110 @@ +CS42L42 audio CODEC + +Required properties: + + - compatible : "cirrus,cs42l42" + + - reg : the I2C address of the device for I2C. + + - VP-supply, VCP-supply, VD_FILT-supply, VL-supply, VA-supply : + power supplies for the device, as covered in + Documentation/devicetree/bindings/regulator/regulator.txt. + +Optional properties: + + - reset-gpios : a GPIO spec for the reset pin. If specified, it will be + deasserted before communication to the codec starts. + + - interrupt-parent : Specifies the phandle of the interrupt controller to + which the IRQs from CS42L42 are delivered to. + + - interrupts : IRQ line info CS42L42. + (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + for further information relating to interrupt properties) + + - cirrus,ts-inv : Boolean property. For jacks that invert the tip sense + polarity. Normal jacks will short tip sense pin to HS1 when headphones are + plugged in and leave tip sense floating when not plugged in. Inverting jacks + short tip sense when unplugged and float when plugged in. + + 0 = (Default) Non-inverted + 1 = Inverted + + - cirrus,ts-dbnc-rise : Debounce the rising edge of TIP_SENSE_PLUG. With no + debounce, the tip sense pin might be noisy on a plug event. + + 0 - 0ms, + 1 - 125ms, + 2 - 250ms, + 3 - 500ms, + 4 - 750ms, + 5 - (Default) 1s, + 6 - 1.25s, + 7 - 1.5s, + + - cirrus,ts-dbnc-fall : Debounce the falling edge of TIP_SENSE_UNPLUG. + With no debounce, the tip sense pin might be noisy on an unplug event. + + 0 - 0ms, + 1 - 125ms, + 2 - 250ms, + 3 - 500ms, + 4 - 750ms, + 5 - (Default) 1s, + 6 - 1.25s, + 7 - 1.5s, + + - cirrus,btn-det-init-dbnce : This sets how long the driver sleeps after + enabling button detection interrupts. After auto-detection and before + servicing button interrupts, the HS bias needs time to settle. If you + don't wait, there is possibility for erroneous button interrupt. + + 0ms - 200ms, + Default = 100ms + + - cirrus,btn-det-event-dbnce : This sets how long the driver delays after + receiving a button press interrupt. With level detect interrupts, you want + to wait a small amount of time to make sure the button press is making a + clean connection with the bias resistors. + + 0ms - 20ms, + Default = 10ms + + - cirrus,bias-lvls : For a level-detect headset button scheme, each button + will bias the mic pin to a certain voltage. To determine which button was + pressed, the driver will compare this biased voltage to sequential, + decreasing voltages and will stop when a comparator is tripped, + indicating a comparator voltage < bias voltage. This value represents a + percentage of the internally generated HS bias voltage. For different + hardware setups, a designer might want to tweak this. This is an array of + descending values for the comparator voltage. + + Array of 4 values + Each 0-63 + < x1 x2 x3 x4 > + Default = < 15 8 4 1> + + +Example: + +cs42l42: cs42l42@48 { + compatible = "cirrus,cs42l42"; + reg = <0x48>; + VA-supply = <&dummy_vreg>; + VP-supply = <&dummy_vreg>; + VCP-supply = <&dummy_vreg>; + VD_FILT-supply = <&dummy_vreg>; + VL-supply = <&dummy_vreg>; + + reset-gpios = <&axi_gpio_0 1 0>; + interrupt-parent = <&gpio0>; + interrupts = <55 8> + + cirrus,ts-inv = <0x00>; + cirrus,ts-dbnc-rise = <0x05>; + cirrus,ts-dbnc-fall = <0x00>; + cirrus,btn-det-init-dbnce = <100>; + cirrus,btn-det-event-dbnce = <10>; + cirrus,bias-lvls = <0x0F 0x08 0x04 0x01>; + cirrus,hs-bias-ramp-rate = <0x02>; +};
\ No newline at end of file diff --git a/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt b/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt index 55b53e1fd72c..e0b6165c9cfc 100644 --- a/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt +++ b/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt @@ -43,7 +43,7 @@ mcbsp0: mcbsp@1d10000 { <0x00310000 0x1000>; reg-names = "mpu", "dat"; interrupts = <97 98>; - interrupts-names = "rx", "tx"; + interrupt-names = "rx", "tx"; dmas = <&edma0 3 1 &edma0 2 1>; dma-names = "tx", "rx"; diff --git a/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt b/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt index d9d8635ff94c..6a4aadc4ce06 100644 --- a/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt +++ b/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt @@ -44,8 +44,7 @@ Required dai-link subnodes: Required CPU/CODEC subnodes properties: -link-name : Name of the dai link. --sound-dai : phandle and port of CPU/CODEC --capture-dai : phandle and port of CPU/CODEC +-sound-dai : phandle/s and port of CPU/CODEC Example: @@ -73,7 +72,7 @@ sound: sound { sound-dai = <&lpass MI2S_PRIMARY>; }; codec { - sound-dai = <&wcd_codec 0>; + sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; }; }; diff --git a/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt new file mode 100644 index 000000000000..ccb401cfef9d --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt @@ -0,0 +1,85 @@ +msm8916 analog audio CODEC + +Bindings for codec Analog IP which is integrated in pmic pm8916, + +## Bindings for codec core on pmic: + +Required properties + - compatible = "qcom,pm8916-wcd-analog-codec"; + - reg: represents the slave base address provided to the peripheral. + - interrupt-parent : The parent interrupt controller. + - interrupts: List of interrupts in given SPMI peripheral. + - interrupt-names: Names specified to above list of interrupts in same + order. List of supported interrupt names are: + "cdc_spk_cnp_int" - Speaker click and pop interrupt. + "cdc_spk_clip_int" - Speaker clip interrupt. + "cdc_spk_ocp_int" - Speaker over current protect interrupt. + "mbhc_ins_rem_det1" - jack insert removal detect interrupt 1. + "mbhc_but_rel_det" - button release interrupt. + "mbhc_but_press_det" - button press event + "mbhc_ins_rem_det" - jack insert removal detect interrupt. + "mbhc_switch_int" - multi button headset interrupt. + "cdc_ear_ocp_int" - Earphone over current protect interrupt. + "cdc_hphr_ocp_int" - Headphone R over current protect interrupt. + "cdc_hphl_ocp_det" - Headphone L over current protect interrupt. + "cdc_ear_cnp_int" - earphone cnp interrupt. + "cdc_hphr_cnp_int" - hphr click and pop interrupt. + "cdc_hphl_cnp_int" - hphl click and pop interrupt. + + - clocks: Handle to mclk. + - clock-names: should be "mclk" + - vdd-cdc-io-supply: phandle to VDD_CDC_IO regulator DT node. + - vdd-cdc-tx-rx-cx-supply: phandle to VDD_CDC_TX/RX/CX regulator DT node. + - vdd-micbias-supply: phandle of VDD_MICBIAS supply's regulator DT node. + +Optional Properties: +- qcom,micbias1-ext-cap: boolean, present if micbias1 has external capacitor + connected. +- qcom,micbias2-ext-cap: boolean, present if micbias2 has external capacitor + connected. + +Example: + +spmi_bus { + ... + audio-codec@f000{ + compatible = "qcom,pm8916-wcd-analog-codec"; + reg = <0xf000 0x200>; + reg-names = "pmic-codec-core"; + clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "mclk"; + interrupt-parent = <&spmi_bus>; + interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, + <0x1 0xf0 0x1 IRQ_TYPE_NONE>, + <0x1 0xf0 0x2 IRQ_TYPE_NONE>, + <0x1 0xf0 0x3 IRQ_TYPE_NONE>, + <0x1 0xf0 0x4 IRQ_TYPE_NONE>, + <0x1 0xf0 0x5 IRQ_TYPE_NONE>, + <0x1 0xf0 0x6 IRQ_TYPE_NONE>, + <0x1 0xf0 0x7 IRQ_TYPE_NONE>, + <0x1 0xf1 0x0 IRQ_TYPE_NONE>, + <0x1 0xf1 0x1 IRQ_TYPE_NONE>, + <0x1 0xf1 0x2 IRQ_TYPE_NONE>, + <0x1 0xf1 0x3 IRQ_TYPE_NONE>, + <0x1 0xf1 0x4 IRQ_TYPE_NONE>, + <0x1 0xf1 0x5 IRQ_TYPE_NONE>; + interrupt-names = "cdc_spk_cnp_int", + "cdc_spk_clip_int", + "cdc_spk_ocp_int", + "mbhc_ins_rem_det1", + "mbhc_but_rel_det", + "mbhc_but_press_det", + "mbhc_ins_rem_det", + "mbhc_switch_int", + "cdc_ear_ocp_int", + "cdc_hphr_ocp_int", + "cdc_hphl_ocp_det", + "cdc_ear_cnp_int", + "cdc_hphr_cnp_int", + "cdc_hphl_cnp_int"; + VDD-CDC-IO-supply = <&pm8916_l5>; + VDD-CDC-TX-RX-CX-supply = <&pm8916_l5>; + VDD-MICBIAS-supply = <&pm8916_l13>; + #sound-dai-cells = <1>; + }; +}; diff --git a/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital.txt b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital.txt new file mode 100644 index 000000000000..1c8e4cb25176 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital.txt @@ -0,0 +1,20 @@ +msm8916 digital audio CODEC + +## Bindings for codec core in lpass: + +Required properties + - compatible = "qcom,msm8916-wcd-digital-codec"; + - reg: address space for lpass codec. + - clocks: Handle to mclk and ahbclk + - clock-names: should be "mclk", "ahbix-clk". + +Example: + +audio-codec@771c000{ + compatible = "qcom,msm8916-wcd-digital-codec"; + reg = <0x0771c000 0x400>; + clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "ahbix-clk", "mclk"; + #sound-dai-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/sound/rt5514.txt b/Documentation/devicetree/bindings/sound/rt5514.txt index 9cabfc18cb57..929ca6756b02 100644 --- a/Documentation/devicetree/bindings/sound/rt5514.txt +++ b/Documentation/devicetree/bindings/sound/rt5514.txt @@ -13,6 +13,9 @@ Optional properties: - clocks: The phandle of the master clock to the CODEC - clock-names: Should be "mclk" +- realtek,dmic-init-delay-ms + Set the DMIC initial delay (ms) to wait it ready. + Pins on the device (for linking into audio routes) for RT5514: * DMIC1L diff --git a/Documentation/devicetree/bindings/sound/rt5663.txt b/Documentation/devicetree/bindings/sound/rt5663.txt index 7d3c974c6e2e..70eaeaed2b18 100644 --- a/Documentation/devicetree/bindings/sound/rt5663.txt +++ b/Documentation/devicetree/bindings/sound/rt5663.txt @@ -1,10 +1,10 @@ -RT5663/RT5668 audio CODEC +RT5663 audio CODEC This device supports I2C only. Required properties: -- compatible : One of "realtek,rt5663" or "realtek,rt5668". +- compatible : "realtek,rt5663". - reg : The I2C address of the device. @@ -12,7 +12,7 @@ Required properties: Optional properties: -Pins on the device (for linking into audio routes) for RT5663/RT5668: +Pins on the device (for linking into audio routes) for RT5663: * IN1P * IN1N diff --git a/Documentation/devicetree/bindings/sound/rt5665.txt b/Documentation/devicetree/bindings/sound/rt5665.txt new file mode 100755 index 000000000000..419c89219681 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rt5665.txt @@ -0,0 +1,68 @@ +RT5665/RT5666/RT5668 audio CODEC + +This device supports I2C only. + +Required properties: + +- compatible : One of "realtek,rt5665", "realtek,rt5666" or "realtek,rt5668". + +- reg : The I2C address of the device. + +- interrupts : The CODEC's interrupt output. + +Optional properties: + +- realtek,in1-differential +- realtek,in2-differential +- realtek,in3-differential +- realtek,in4-differential + Boolean. Indicate MIC1/2/3/4 input are differential, rather than single-ended. + +- realtek,dmic1-data-pin + 0: dmic1 is not used + 1: using GPIO4 pin as dmic1 data pin + 2: using IN2N pin as dmic2 data pin + +- realtek,dmic2-data-pin + 0: dmic2 is not used + 1: using GPIO5 pin as dmic2 data pin + 2: using IN2P pin as dmic2 data pin + +- realtek,jd-src + 0: No JD is used + 1: using JD1 as JD source + +- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin. + +Pins on the device (for linking into audio routes) for RT5659/RT5658: + + * DMIC L1 + * DMIC R1 + * DMIC L2 + * DMIC R2 + * IN1P + * IN1N + * IN2P + * IN2N + * IN3P + * IN3N + * IN4P + * IN4N + * HPOL + * HPOR + * LOUTL + * LOUTR + * MONOOUT + * PDML + * PDMR + +Example: + +rt5659 { + compatible = "realtek,rt5665"; + reg = <0x1b>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>; + realtek,ldo1-en-gpios = + <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; +}; diff --git a/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt b/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt new file mode 100644 index 000000000000..94442e5673b3 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt @@ -0,0 +1,38 @@ +Samsung Exynos5433 TM2(E) audio complex with WM5110 codec + +Required properties: + + - compatible : "samsung,tm2-audio" + - model : the user-visible name of this sound complex + - audio-codec : the phandle of the wm5110 audio codec node, + as described in ../mfd/arizona.txt + - i2s-controller : the phandle of the I2S controller + - audio-amplifier : the phandle of the MAX98504 amplifier + - samsung,audio-routing : a list of the connections between audio components; + each entry is a pair of strings, the first being the + connection's sink, the second being the connection's + source; valid names for sources and sinks are the + WM5110's and MAX98504's pins and the jacks on the + board: HP, SPK, Main Mic, Sub Mic, Third Mic, + Headset Mic + - mic-bias-gpios : GPIO pin that enables the Main Mic bias regulator + + +Example: + +sound { + compatible = "samsung,tm2-audio"; + audio-codec = <&wm5110>; + i2s-controller = <&i2s0>; + audio-amplifier = <&max98504>; + mic-bias-gpios = <&gpr3 2 0>; + model = "wm5110"; + samsung,audio-routing = + "HP", "HPOUT1L", + "HP", "HPOUT1R", + "SPK", "SPKOUT", + "SPKOUT", "HPOUT2L", + "SPKOUT", "HPOUT2R", + "Main Mic", "MICBIAS2", + "IN1R", "Main Mic"; +}; diff --git a/Documentation/devicetree/bindings/sound/sun4i-codec.txt b/Documentation/devicetree/bindings/sound/sun4i-codec.txt index 0dce690f78f5..3033bd8aab0f 100644 --- a/Documentation/devicetree/bindings/sound/sun4i-codec.txt +++ b/Documentation/devicetree/bindings/sound/sun4i-codec.txt @@ -1,8 +1,12 @@ * Allwinner A10 Codec Required properties: -- compatible: must be either "allwinner,sun4i-a10-codec" or - "allwinner,sun7i-a20-codec" +- compatible: must be one of the following compatibles: + - "allwinner,sun4i-a10-codec" + - "allwinner,sun6i-a31-codec" + - "allwinner,sun7i-a20-codec" + - "allwinner,sun8i-a23-codec" + - "allwinner,sun8i-h3-codec" - reg: must contain the registers location and length - interrupts: must contain the codec interrupt - dmas: DMA channels for tx and rx dma. See the DMA client binding, @@ -17,6 +21,43 @@ Required properties: Optional properties: - allwinner,pa-gpios: gpio to enable external amplifier +Required properties for the following compatibles: + - "allwinner,sun6i-a31-codec" + - "allwinner,sun8i-a23-codec" + - "allwinner,sun8i-h3-codec" +- resets: phandle to the reset control for this device +- allwinner,audio-routing: A list of the connections between audio components. + Each entry is a pair of strings, the first being the + connection's sink, the second being the connection's + source. Valid names include: + + Audio pins on the SoC: + "HP" + "HPCOM" + "LINEIN" + "LINEOUT" (not on sun8i-a23) + "MIC1" + "MIC2" + "MIC3" (sun6i-a31 only) + + Microphone biases from the SoC: + "HBIAS" + "MBIAS" + + Board connectors: + "Headphone" + "Headset Mic" + "Line In" + "Line Out" + "Mic" + "Speaker" + +Required properties for the following compatibles: + - "allwinner,sun8i-a23-codec" + - "allwinner,sun8i-h3-codec" +- allwinner,codec-analog-controls: A phandle to the codec analog controls + block in the PRCM. + Example: codec: codec@01c22c00 { #sound-dai-cells = <0>; @@ -28,3 +69,23 @@ codec: codec@01c22c00 { dmas = <&dma 0 19>, <&dma 0 19>; dma-names = "rx", "tx"; }; + +codec: codec@01c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-codec"; + reg = <0x01c22c00 0x98>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>; + clock-names = "apb", "codec"; + resets = <&ccu RST_APB1_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + allwinner,audio-routing = + "Headphone", "HP", + "Speaker", "LINEOUT", + "LINEIN", "Line In", + "MIC1", "MBIAS", + "MIC1", "Mic", + "MIC2", "HBIAS", + "MIC2", "Headset Mic"; +}; diff --git a/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt b/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt new file mode 100644 index 000000000000..779b735781ba --- /dev/null +++ b/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt @@ -0,0 +1,16 @@ +* Allwinner Codec Analog Controls + +Required properties: +- compatible: must be one of the following compatibles: + - "allwinner,sun8i-a23-codec-analog" + - "allwinner,sun8i-h3-codec-analog" + +Required properties if not a sub-node of the PRCM node: +- reg: must contain the registers location and length + +Example: +prcm: prcm@01f01400 { + codec_analog: codec-analog { + compatible = "allwinner,sun8i-a23-codec-analog"; + }; +}; diff --git a/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt b/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt index 9340d2ddcc54..6fbba562eaa7 100644 --- a/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt +++ b/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt @@ -12,6 +12,7 @@ Required properties: "ti,tlv320aic3120" - TLV320AIC3120 (mono speaker amp, MiniDSP) "ti,tlv320aic3111" - TLV320AIC3111 (stereo speaker amp, MiniDSP) "ti,tlv320dac3100" - TLV320DAC3100 (no ADC, mono speaker amp, no MiniDSP) + "ti,tlv320dac3101" - TLV320DAC3101 (no ADC, stereo speaker amp, no MiniDSP) - reg - <int> - I2C slave address - HPVDD-supply, SPRVDD-supply, SPLVDD-supply, AVDD-supply, IOVDD-supply, diff --git a/Documentation/devicetree/bindings/sound/wm8580.txt b/Documentation/devicetree/bindings/sound/wm8580.txt index 7d9821f348da..78fce9b14954 100644 --- a/Documentation/devicetree/bindings/sound/wm8580.txt +++ b/Documentation/devicetree/bindings/sound/wm8580.txt @@ -1,10 +1,10 @@ -WM8580 audio CODEC +WM8580 and WM8581 audio CODEC This device supports I2C only. Required properties: - - compatible : "wlf,wm8580" + - compatible : "wlf,wm8580", "wlf,wm8581" - reg : the I2C address of the device. diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt index aa005c1d10d9..da6614c63796 100644 --- a/Documentation/devicetree/bindings/spi/sh-msiof.txt +++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt @@ -10,6 +10,7 @@ Required properties: "renesas,msiof-r8a7792" (R-Car V2H) "renesas,msiof-r8a7793" (R-Car M2-N) "renesas,msiof-r8a7794" (R-Car E2) + "renesas,msiof-r8a7796" (R-Car M3-W) "renesas,msiof-sh73a0" (SH-Mobile AG5) - reg : A list of offsets and lengths of the register sets for the device. diff --git a/Documentation/devicetree/bindings/spi/spi-armada-3700.txt b/Documentation/devicetree/bindings/spi/spi-armada-3700.txt new file mode 100644 index 000000000000..1564aa8c02cd --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-armada-3700.txt @@ -0,0 +1,25 @@ +* Marvell Armada 3700 SPI Controller + +Required Properties: + +- compatible: should be "marvell,armada-3700-spi" +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: The interrupt number. The interrupt specifier format depends on + the interrupt controller and of its driver. +- clocks: Must contain the clock source, usually from the North Bridge clocks. +- num-cs: The number of chip selects that is supported by this SPI Controller +- #address-cells: should be 1. +- #size-cells: should be 0. + +Example: + + spi0: spi@10600 { + compatible = "marvell,armada-3700-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10600 0x5d>; + clocks = <&nb_perih_clk 7>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <4>; + }; diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt new file mode 100644 index 000000000000..225ace1d0c65 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt @@ -0,0 +1,19 @@ +* Freescale Low Power SPI (LPSPI) for i.MX + +Required properties: +- compatible : + - "fsl,imx7ulp-spi" for LPSPI compatible with the one integrated on i.MX7ULP soc +- reg : address and length of the lpspi master registers +- interrupt-parent : core interrupt controller +- interrupts : lpspi interrupt +- clocks : lpspi clock specifier + +Examples: + +lpspi2: lpspi@40290000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x40290000 0x10000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_LPSPI2>; +}; diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt index 21de73db6a05..2ec99b86b622 100644 --- a/Documentation/devicetree/bindings/spi/spi-sun6i.txt +++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt @@ -1,7 +1,7 @@ -Allwinner A31 SPI controller +Allwinner A31/H3 SPI controller Required properties: -- compatible: Should be "allwinner,sun6i-a31-spi". +- compatible: Should be "allwinner,sun6i-a31-spi" or "allwinner,sun8i-h3-spi". - reg: Should contain register location and length. - interrupts: Should contain interrupt. - clocks: phandle to the clocks feeding the SPI controller. Two are @@ -12,6 +12,11 @@ Required properties: - resets: phandle to the reset controller asserting this device in reset +Optional properties: +- dmas: DMA specifiers for rx and tx dma. See the DMA client binding, + Documentation/devicetree/bindings/dma/dma.txt +- dma-names: DMA request names should include "rx" and "tx" if present. + Example: spi1: spi@01c69000 { @@ -22,3 +27,19 @@ spi1: spi@01c69000 { clock-names = "ahb", "mod"; resets = <&ahb1_rst 21>; }; + +spi0: spi@01c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; +}; diff --git a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt index 070baf4d7d97..b6b5130e5f65 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt +++ b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt @@ -7,8 +7,11 @@ To bind UFS PHY with UFS host controller, the controller node should contain a phandle reference to UFS PHY node. Required properties: -- compatible : compatible list, contains "qcom,ufs-phy-qmp-20nm" - or "qcom,ufs-phy-qmp-14nm" according to the relevant phy in use. +- compatible : compatible list, contains one of the following - + "qcom,ufs-phy-qmp-20nm" for 20nm ufs phy, + "qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy, + "qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy + present on MSM8996 chipset. - reg : should contain PHY register address space (mandatory), - reg-names : indicates various resources passed to driver (via reg proptery) by name. Required "reg-names" is "phy_mem". diff --git a/Documentation/devicetree/bindings/usb/da8xx-usb.txt b/Documentation/devicetree/bindings/usb/da8xx-usb.txt new file mode 100644 index 000000000000..ccb844aba7d4 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/da8xx-usb.txt @@ -0,0 +1,43 @@ +TI DA8xx MUSB +~~~~~~~~~~~~~ +For DA8xx/OMAP-L1x/AM17xx/AM18xx platforms. + +Required properties: +~~~~~~~~~~~~~~~~~~~~ + - compatible : Should be set to "ti,da830-musb". + + - reg: Offset and length of the USB controller register set. + + - interrupts: The USB interrupt number. + + - interrupt-names: Should be set to "mc". + + - dr_mode: The USB operation mode. Should be one of "host", "peripheral" or "otg". + + - phys: Phandle for the PHY device + + - phy-names: Should be "usb-phy" + +Optional properties: +~~~~~~~~~~~~~~~~~~~~ + - vbus-supply: Phandle to a regulator providing the USB bus power. + +Example: + usb_phy: usb-phy { + compatible = "ti,da830-usb-phy"; + #phy-cells = <0>; + status = "okay"; + }; + usb0: usb@200000 { + compatible = "ti,da830-musb"; + reg = <0x00200000 0x10000>; + interrupts = <58>; + interrupt-names = "mc"; + + dr_mode = "host"; + vbus-supply = <&usb_vbus>; + phys = <&usb_phy 0>; + phy-names = "usb-phy"; + + status = "okay"; + }; diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt index 2c30a5479069..6c7c2bce6d0c 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.txt +++ b/Documentation/devicetree/bindings/usb/dwc2.txt @@ -12,6 +12,7 @@ Required properties: - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs; - "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs; - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs; + - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs; - snps,dwc2: A generic DWC2 USB controller with default parameters. - reg : Should contain 1 register range (address and length) - interrupts : Should contain 1 interrupt @@ -25,11 +26,13 @@ Optional properties: Refer to phy/phy-bindings.txt for generic phy consumer properties - dr_mode: shall be one of "host", "peripheral" and "otg" Refer to usb/generic.txt -- g-use-dma: enable dma usage in gadget driver. - g-rx-fifo-size: size of rx fifo size in gadget mode. - g-np-tx-fifo-size: size of non-periodic tx fifo size in gadget mode. - g-tx-fifo-size: size of periodic tx fifo per endpoint (except ep0) in gadget mode. +Deprecated properties: +- g-use-dma: gadget DMA mode is automatically detected + Example: usb@101c0000 { diff --git a/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt b/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt new file mode 100644 index 000000000000..e049d199bf0d --- /dev/null +++ b/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt @@ -0,0 +1,87 @@ +The device node for Mediatek USB3.0 DRD controller + +Required properties: + - compatible : should be "mediatek,mt8173-mtu3" + - reg : specifies physical base address and size of the registers + - reg-names: should be "mac" for device IP and "ippc" for IP port control + - interrupts : interrupt used by the device IP + - power-domains : a phandle to USB power domain node to control USB's + mtcmos + - vusb33-supply : regulator of USB avdd3.3v + - clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names + - clock-names : must contain "sys_ck" for clock of controller; + "wakeup_deb_p0" and "wakeup_deb_p1" are optional, they are + depends on "mediatek,enable-wakeup" + - phys : a list of phandle + phy specifier pairs + - dr_mode : should be one of "host", "peripheral" or "otg", + refer to usb/generic.txt + +Optional properties: + - #address-cells, #size-cells : should be '2' if the device has sub-nodes + with 'reg' property + - ranges : allows valid 1:1 translation between child's address space and + parent's address space + - extcon : external connector for vbus and idpin changes detection, needed + when supports dual-role mode. + - vbus-supply : reference to the VBUS regulator, needed when supports + dual-role mode. + - pinctl-names : a pinctrl state named "default" must be defined, + "id_float" and "id_ground" are optinal which depends on + "mediatek,enable-manual-drd" + - pinctrl-0 : pin control group + See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt + + - maximum-speed : valid arguments are "super-speed", "high-speed" and + "full-speed"; refer to usb/generic.txt + - enable-manual-drd : supports manual dual-role switch via debugfs; usually + used when receptacle is TYPE-A and also wants to support dual-role + mode. + - mediatek,enable-wakeup : supports ip sleep wakeup used by host mode + - mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup + control register, it depends on "mediatek,enable-wakeup". + +Sub-nodes: +The xhci should be added as subnode to mtu3 as shown in the following example +if host mode is enabled. The DT binding details of xhci can be found in: +Documentation/devicetree/bindings/usb/mt8173-xhci.txt + +Example: +ssusb: usb@11271000 { + compatible = "mediatek,mt8173-mtu3"; + reg = <0 0x11271000 0 0x3000>, + <0 0x11280700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; + phys = <&phy_port0 PHY_TYPE_USB3>, + <&phy_port1 PHY_TYPE_USB2>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; + clocks = <&topckgen CLK_TOP_USB30_SEL>, + <&pericfg CLK_PERI_USB0>, + <&pericfg CLK_PERI_USB1>; + clock-names = "sys_ck", + "wakeup_deb_p0", + "wakeup_deb_p1"; + vusb33-supply = <&mt6397_vusb_reg>; + vbus-supply = <&usb_p0_vbus>; + extcon = <&extcon_usb>; + dr_mode = "otg"; + mediatek,enable-wakeup; + mediatek,syscon-wakeup = <&pericfg>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host: xhci@11270000 { + compatible = "mediatek,mt8173-xhci"; + reg = <0 0x11270000 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; + clocks = <&topckgen CLK_TOP_USB30_SEL>; + clock-names = "sys_ck"; + vusb33-supply = <&mt6397_vusb_reg>; + status = "disabled"; + }; +}; diff --git a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt index b3a7ffa48852..2a930bd52b94 100644 --- a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt +++ b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt @@ -2,10 +2,18 @@ MT8173 xHCI The device node for Mediatek SOC USB3.0 host controller +There are two scenarios: the first one only supports xHCI driver; +the second one supports dual-role mode, and the host is based on xHCI +driver. Take account of backward compatibility, we divide bindings +into two parts. + +1st: only supports xHCI driver +------------------------------------------------------------------------ + Required properties: - compatible : should contain "mediatek,mt8173-xhci" - - reg : specifies physical base address and size of the registers, - the first one for MAC, the second for IPPC + - reg : specifies physical base address and size of the registers + - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control - interrupts : interrupt used by the controller - power-domains : a phandle to USB power domain node to control USB's mtcmos @@ -27,12 +35,16 @@ Optional properties: control register, it depends on "mediatek,wakeup-src". - vbus-supply : reference to the VBUS regulator; - usb3-lpm-capable : supports USB3.0 LPM + - pinctrl-names : a pinctrl state named "default" must be defined + - pinctrl-0 : pin control group + See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt Example: usb30: usb@11270000 { compatible = "mediatek,mt8173-xhci"; reg = <0 0x11270000 0 0x1000>, <0 0x11280700 0 0x0100>; + reg-names = "mac", "ippc"; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; clocks = <&topckgen CLK_TOP_USB30_SEL>, @@ -49,3 +61,41 @@ usb30: usb@11270000 { mediatek,syscon-wakeup = <&pericfg>; mediatek,wakeup-src = <1>; }; + +2nd: dual-role mode with xHCI driver +------------------------------------------------------------------------ + +In the case, xhci is added as subnode to mtu3. An example and the DT binding +details of mtu3 can be found in: +Documentation/devicetree/bindings/usb/mtu3.txt + +Required properties: + - compatible : should contain "mediatek,mt8173-xhci" + - reg : specifies physical base address and size of the registers + - reg-names: should be "mac" for xHCI MAC + - interrupts : interrupt used by the host controller + - power-domains : a phandle to USB power domain node to control USB's + mtcmos + - vusb33-supply : regulator of USB avdd3.3v + + - clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names + - clock-names : must be + "sys_ck": for clock of xHCI MAC + +Optional properties: + - vbus-supply : reference to the VBUS regulator; + - usb3-lpm-capable : supports USB3.0 LPM + +Example: +usb30: usb@11270000 { + compatible = "mediatek,mt8173-xhci"; + reg = <0 0x11270000 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; + clocks = <&topckgen CLK_TOP_USB30_SEL>; + clock-names = "sys_ck"; + vusb33-supply = <&mt6397_vusb_reg>; + usb3-lpm-capable; +}; diff --git a/Documentation/devicetree/bindings/usb/ohci-da8xx.txt b/Documentation/devicetree/bindings/usb/ohci-da8xx.txt new file mode 100644 index 000000000000..2dc8f67eda39 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ohci-da8xx.txt @@ -0,0 +1,23 @@ +DA8XX USB OHCI controller + +Required properties: + + - compatible: Should be "ti,da830-ohci" + - reg: Should contain one register range i.e. start and length + - interrupts: Description of the interrupt line + - phys: Phandle for the PHY device + - phy-names: Should be "usb-phy" + +Optional properties: + - vbus-supply: phandle of regulator that controls vbus power / over-current + +Example: + +ohci: usb@0225000 { + compatible = "ti,da830-ohci"; + reg = <0x225000 0x1000>; + interrupts = <59>; + phys = <&usb_phy 1>; + phy-names = "usb-phy"; + vbus-supply = <®_usb_ohci>; +}; diff --git a/Documentation/devicetree/bindings/usb/s3c2410-usb.txt b/Documentation/devicetree/bindings/usb/s3c2410-usb.txt new file mode 100644 index 000000000000..e45b38ce2986 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/s3c2410-usb.txt @@ -0,0 +1,22 @@ +Samsung S3C2410 and compatible SoC USB controller + +OHCI + +Required properties: + - compatible: should be "samsung,s3c2410-ohci" for USB host controller + - reg: address and lenght of the controller memory mapped region + - interrupts: interrupt number for the USB OHCI controller + - clocks: Should reference the bus and host clocks + - clock-names: Should contain two strings + "usb-bus-host" for the USB bus clock + "usb-host" for the USB host clock + +Example: + +usb0: ohci@49000000 { + compatible = "samsung,s3c2410-ohci"; + reg = <0x49000000 0x100>; + interrupts = <0 0 26 3>; + clocks = <&clocks UCLK>, <&clocks HCLK_USBH>; + clock-names = "usb-bus-host", "usb-host"; +}; diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt index 966885c636d0..0b7d8576001c 100644 --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt @@ -11,6 +11,7 @@ Required properties: - "renesas,xhci-r8a7791" for r8a7791 SoC - "renesas,xhci-r8a7793" for r8a7793 SoC - "renesas,xhci-r8a7795" for r8a7795 SoC + - "renesas,xhci-r8a7796" for r8a7796 SoC - "renesas,rcar-gen2-xhci" for a generic R-Car Gen2 compatible device - "renesas,rcar-gen3-xhci" for a generic R-Car Gen3 compatible device - "xhci-platform" (deprecated) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index d9c51d7f4aac..98371753a08f 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -39,6 +39,7 @@ auo AU Optronics Corporation auvidea Auvidea GmbH avago Avago Technologies avic Shanghai AVIC Optoelectronics Co., Ltd. +axentia Axentia Technologies AB axis Axis Communications AB boe BOE Technology Group Co., Ltd. bosch Bosch Sensortec GmbH @@ -126,6 +127,7 @@ hitex Hitex Development Tools holt Holt Integrated Circuits, Inc. honeywell Honeywell hp Hewlett Packard +holtek Holtek Semiconductor, Inc. i2se I2SE GmbH ibm International Business Machines (IBM) idt Integrated Device Technologies, Inc. @@ -160,16 +162,19 @@ lltc Linear Technology Corporation lsi LSI Corp. (LSI Logic) marvell Marvell Technology Group Ltd. maxim Maxim Integrated Products +mcube mCube meas Measurement Specialties mediatek MediaTek Inc. melexis Melexis N.V. melfas MELFAS Inc. +memsic MEMSIC Inc. merrii Merrii Technology Co., Ltd. micrel Micrel Inc. microchip Microchip Technology Inc. microcrystal Micro Crystal AG micron Micron Technology Inc. minix MINIX Technology Ltd. +miramems MiraMEMS Sensing Technology Co., Ltd. mitsubishi Mitsubishi Electric Corporation mosaixtech Mosaix Technologies, Inc. moxa Moxa |
