diff options
Diffstat (limited to 'Documentation/devicetree/bindings/sound')
15 files changed, 550 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/sound/adi,adau17x1.txt b/Documentation/devicetree/bindings/sound/adi,adau17x1.txt index 8dbce0e18dda..1447dec28125 100644 --- a/Documentation/devicetree/bindings/sound/adi,adau17x1.txt +++ b/Documentation/devicetree/bindings/sound/adi,adau17x1.txt @@ -13,6 +13,11 @@ Required properties: - reg: The i2c address. Value depends on the state of ADDR0 and ADDR1, as wired in hardware. +Optional properties: + - clock-names: If provided must be "mclk". + - clocks: phandle + clock-specifiers for the clock that provides + the audio master clock for the device. + Examples: #include <dt-bindings/sound/adau17x1.h> @@ -20,5 +25,8 @@ Examples: adau1361@38 { compatible = "adi,adau1761"; reg = <0x38>; + + clock-names = "mclk"; + clocks = <&audio_clock>; }; }; diff --git a/Documentation/devicetree/bindings/sound/adi,adau7002.txt b/Documentation/devicetree/bindings/sound/adi,adau7002.txt new file mode 100644 index 000000000000..f144ee1abf85 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/adi,adau7002.txt @@ -0,0 +1,19 @@ +Analog Devices ADAU7002 Stereo PDM-to-I2S/TDM Converter + +Required properties: + + - compatible: Must be "adi,adau7002" + +Optional properties: + + - IOVDD-supply: Phandle and specifier for the power supply providing the IOVDD + supply as covered in Documentation/devicetree/bindings/regulator/regulator.txt + + If this property is not present it is assumed that the supply pin is + hardwired to always on. + +Example: + adau7002: pdm-to-i2s { + compatible = "adi,adau7002"; + IOVDD-supply = <&supply>; + }; diff --git a/Documentation/devicetree/bindings/sound/brcm,cygnus-audio.txt b/Documentation/devicetree/bindings/sound/brcm,cygnus-audio.txt new file mode 100644 index 000000000000..b139e66d2a11 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/brcm,cygnus-audio.txt @@ -0,0 +1,67 @@ +BROADCOM Cygnus Audio I2S/TDM/SPDIF controller + +Required properties: + - compatible : "brcm,cygnus-audio" + - #address-cells: 32bit valued, 1 cell. + - #size-cells: 32bit valued, 0 cell. + - reg : Should contain audio registers location and length + - reg-names: names of the registers listed in "reg" property + Valid names are "aud" and "i2s_in". "aud" contains a + set of DMA, I2S_OUT and SPDIF registers. "i2s_in" contains + a set of I2S_IN registers. + - clocks: PLL and leaf clocks used by audio ports + - assigned-clocks: PLL and leaf clocks + - assigned-clock-parents: parent clocks of the assigned clocks + (usually the PLL) + - assigned-clock-rates: List of clock frequencies of the + assigned clocks + - clock-names: names of 3 leaf clocks used by audio ports + Valid names are "ch0_audio", "ch1_audio", "ch2_audio" + - interrupts: audio DMA interrupt number + +SSP Subnode properties: +- reg: The index of ssp port interface to use + Valid value are 0, 1, 2, or 3 (for spdif) + +Example: + cygnus_audio: audio@180ae000 { + compatible = "brcm,cygnus-audio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x180ae000 0xafd>, <0x180aec00 0x1f8>; + reg-names = "aud", "i2s_in"; + clocks = <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>, + <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>, + <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>; + assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>, + <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>, + <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>, + <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>; + assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>; + assigned-clock-rates = <1769470191>, + <0>, + <0>, + <0>; + clock-names = "ch0_audio", "ch1_audio", "ch2_audio"; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + + ssp0: ssp_port@0 { + reg = <0>; + status = "okay"; + }; + + ssp1: ssp_port@1 { + reg = <1>; + status = "disabled"; + }; + + ssp2: ssp_port@2 { + reg = <2>; + status = "disabled"; + }; + + spdif: spdif_port@3 { + reg = <3>; + status = "disabled"; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/bt-sco.txt b/Documentation/devicetree/bindings/sound/bt-sco.txt index 29b8e5d40203..641edf75e184 100644 --- a/Documentation/devicetree/bindings/sound/bt-sco.txt +++ b/Documentation/devicetree/bindings/sound/bt-sco.txt @@ -4,7 +4,7 @@ This device support generic Bluetooth SCO link. Required properties: - - compatible : "delta,dfbmcs320" + - compatible : "delta,dfbmcs320" or "linux,bt-sco" Example: diff --git a/Documentation/devicetree/bindings/sound/cs35l33.txt b/Documentation/devicetree/bindings/sound/cs35l33.txt new file mode 100644 index 000000000000..acfb47525b49 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cs35l33.txt @@ -0,0 +1,126 @@ +CS35L33 Speaker Amplifier + +Required properties: + + - compatible : "cirrus,cs35l33" + + - reg : the I2C address of the device for I2C + + - VA-supply, VP-supply : power supplies for the device, + as covered in + Documentation/devicetree/bindings/regulator/regulator.txt. + +Optional properties: + + - reset-gpios : gpio used to reset the amplifier + + - interrupt-parent : Specifies the phandle of the interrupt controller to + which the IRQs from CS35L33 are delivered to. + - interrupts : IRQ line info CS35L33. + (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + for further information relating to interrupt properties) + + - cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is + 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with + a value of 1 and will increase at a step size of 100mV until a maximum of + 8000mV. + + - cirrus,ramp-rate : On power up, it affects the time from when the power + up sequence begins to the time the audio reaches a full-scale output. + On power down, it affects the time from when the power-down sequence + begins to when the amplifier disables the PWM outputs. If this property + is not set then soft ramping will be disabled and ramp time would be + 20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms, + 60ms,100ms,175ms respectively for 48KHz sample rate. + + - cirrus,boost-ipk : The maximum current allowed for the boost converter. + The range starts at 1850000uA and goes to a maximum of 3600000uA + with a step size of 15625uA. The default is 2500000uA. + + - cirrus,imon-adc-scale : Configures the scaling of data bits from the IMON + ADC data word. This property can be set as a value of 0 for bits 15 down + to 0, 6 for 21 down to 6, 7, for 22 down to 7, 8 for 23 down to 8. + + +Optional H/G Algorithm sub-node: + +The cs35l33 node can have a single "cirrus,hg-algo" sub-node that will enable +the internal H/G Algorithm. + + - cirrus,hg-algo : Sub-node for internal Class H/G algorithm that + controls the amplifier supplies. + +Optional properties for the "cirrus,hg-algo" sub-node: + + - cirrus,mem-depth : Memory depth for the Class H/G algorithm measured in + LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory + depths will be 1, 4, 8, 16 LRCLK cycles. The default is 16 LRCLK cycles. + + cirrus,release-rate : The number of consecutive LRCLK periods before + allowing release condition tracking updates. The number of LRCLK periods + start at 3 to a maximum of 255. + + - cirrus,ldo-thld : Configures the signal threshold at which the PWM output + stage enters LDO operation. Starts as a default value of 50mV for a value + of 1 and increases with a step size of 50mV to a maximum of 750mV (value of + 0xF). + + - cirrus,ldo-path-disable : This is a boolean property. If present, the H/G + algorithm uses the max detection path. If not present, the LDO + detection path is used. + + - cirrus,ldo-entry-delay : The LDO entry delay in milliseconds before the H/G + algorithm switches to the LDO voltage. This property can be set to values + from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms. + The default is 100ms. + + - cirrus,vp-hg-auto : This is a boolean property. When set, class H/G VPhg + automatic updating is enabled. + + - cirrus,vp-hg : Class H/G algorithm VPhg. Controls the H/G algorithm's + reference to the VP voltage for when to start generating a boosted VBST. + The reference voltage starts at 3000mV with a value of 0x3 and is increased + by 100mV per step to a maximum of 5500mV. + + - cirrus,vp-hg-rate : The rate (number of LRCLK periods) at which the VPhg is + allowed to increase to a higher voltage when using VPhg automatic + tracking. This property can be set to values from 0 to 3 with rates of 128 + periods, 2048 periods, 32768 periods, and 524288 periods. + The default is 32768 periods. + + - cirrus,vp-hg-va : VA calculation reference for automatic VPhg tracking + using VPMON. This property can be set to values from 0 to 6 starting at + 1800mV with a step size of 50mV up to a maximum value of 1750mV. + Default is 1800mV. + +Example: + +cs35l33: cs35l33@40 { + compatible = "cirrus,cs35l33"; + reg = <0x40>; + + VA-supply = <&ldo5_reg>; + VP-supply = <&ldo5_reg>; + + interrupt-parent = <&gpio8>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&cs47l91 34 0>; + + cirrus,ramp-rate = <0x0>; + cirrus,boost-ctl = <0x30>; /* VBST = 8000mV */ + cirrus,boost-ipk = <0xE0>; /* 3600mA */ + cirrus,imon-adc-scale = <0> /* Bits 15 down to 0 */ + + cirrus,hg-algo { + cirrus,mem-depth = <0x3>; + cirrus,release-rate = <0x3>; + cirrus,ldo-thld = <0x1>; + cirrus,ldo-path-disable = <0x0>; + cirrus,ldo-entry-delay=<0x4>; + cirrus,vp-hg-auto; + cirrus,vp-hg=<0xF>; + cirrus,vp-hg-rate=<0x2>; + cirrus,vp-hg-va=<0x0>; + }; +}; diff --git a/Documentation/devicetree/bindings/sound/cs53l30.txt b/Documentation/devicetree/bindings/sound/cs53l30.txt new file mode 100644 index 000000000000..4dbfb8274cd9 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cs53l30.txt @@ -0,0 +1,44 @@ +CS53L30 audio CODEC + +Required properties: + + - compatible : "cirrus,cs53l30" + + - reg : the I2C address of the device + + - VA-supply, VP-supply : power supplies for the device, + as covered in Documentation/devicetree/bindings/regulator/regulator.txt. + +Optional properties: + + - reset-gpios : a GPIO spec for the reset pin. + + - mute-gpios : a GPIO spec for the MUTE pin. The active state can be either + GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW, which would be handled + by the driver automatically. + + - cirrus,micbias-lvl : Set the output voltage level on the MICBIAS Pin. + 0 = Hi-Z + 1 = 1.80 V + 2 = 2.75 V + + - cirrus,use-sdout2 : This is a boolean property. If present, it indicates + the hardware design connects both SDOUT1 and SDOUT2 + pins to output data. Otherwise, it indicates that + only SDOUT1 is connected for data output. + * CS53l30 supports 4-channel data output in the same + * frame using two different ways: + * 1) Normal I2S mode on two data pins -- each SDOUT + * carries 2-channel data in the same time. + * 2) TDM mode on one signle data pin -- SDOUT1 carries + * 4-channel data per frame. + +Example: + +codec: cs53l30@48 { + compatible = "cirrus,cs53l30"; + reg = <0x48>; + reset-gpios = <&gpio 54 0>; + VA-supply = <&cs53l30_va>; + VP-supply = <&cs53l30_vp>; +}; diff --git a/Documentation/devicetree/bindings/sound/designware-i2s.txt b/Documentation/devicetree/bindings/sound/designware-i2s.txt index 7bb54247f8e8..6a536d570e29 100644 --- a/Documentation/devicetree/bindings/sound/designware-i2s.txt +++ b/Documentation/devicetree/bindings/sound/designware-i2s.txt @@ -12,6 +12,10 @@ Required properties: one for receive. - dma-names : "tx" for the transmit channel, "rx" for the receive channel. +Optional properties: + - interrupts: The interrupt line number for the I2S controller. Add this + parameter if the I2S controller that you are using does not support DMA. + For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties please check: * resource-names.txt diff --git a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt index ceaef5126989..f749e2744824 100644 --- a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt +++ b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt @@ -58,7 +58,7 @@ Required properties: * DMIC (stands for Digital Microphone Jack) Note: The "Mic Jack" and "AMIC" are redundant while - coexsiting in order to support the old bindings + coexisting in order to support the old bindings of wm8962 and sgtl5000. Optional properties: diff --git a/Documentation/devicetree/bindings/sound/max98504.txt b/Documentation/devicetree/bindings/sound/max98504.txt new file mode 100644 index 000000000000..583ed5fdfb28 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/max98504.txt @@ -0,0 +1,44 @@ +Maxim MAX98504 class D mono speaker amplifier + +This device supports I2C control interface and an IRQ output signal. It features +a PCM and PDM digital audio interface (DAI) and a differential analog input. + +Required properties: + + - compatible : "maxim,max98504" + - reg : should contain the I2C slave device address + - DVDD-supply, DIOVDD-supply, PVDD-supply: power supplies for the device, + as covered in ../regulator/regulator.txt + - interrupts : should specify the interrupt line the device is connected to, + as described in ../interrupt-controller/interrupts.txt + +Optional properties: + + - maxim,brownout-threshold - the PVDD brownout threshold, the value must be + from 0, 1...21 range, corresponding to 2.6V, 2.65V...3.65V voltage range + - maxim,brownout-attenuation - the brownout attenuation to the speaker gain + applied during the "attack hold" and "timed hold" phase, the value must be + from 0...6 (dB) range + - maxim,brownout-attack-hold-ms - the brownout attack hold phase time in ms, + 0...255 (VBATBROWN_ATTK_HOLD, register 0x0018) + - maxim,brownout-timed-hold-ms - the brownout timed hold phase time in ms, + 0...255 (VBATBROWN_TIME_HOLD, register 0x0019) + - maxim,brownout-release-rate-ms - the brownout release phase step time in ms, + 0...255 (VBATBROWN_RELEASE, register 0x001A) + +The default value when the above properties are not specified is 0, +the maxim,brownout-threshold property must be specified to actually enable +the PVDD brownout protection. + +Example: + + max98504@31 { + compatible = "maxim,max98504"; + reg = <0x31>; + interrupt-parent = <&gpio_bank_0>; + interrupts = <2 0>; + + DVDD-supply = <®ulator>; + DIOVDD-supply = <®ulator>; + PVDD-supply = <®ulator>; +}; diff --git a/Documentation/devicetree/bindings/sound/max9860.txt b/Documentation/devicetree/bindings/sound/max9860.txt new file mode 100644 index 000000000000..e0d4e95e31b3 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/max9860.txt @@ -0,0 +1,28 @@ +MAX9860 Mono Audio Voice Codec + +Required properties: + + - compatible : "maxim,max9860" + + - reg : the I2C address of the device + + - AVDD-supply, DVDD-supply and DVDDIO-supply : power supplies for + the device, as covered in bindings/regulator/regulator.txt + + - clock-names : Required element: "mclk". + + - clocks : A clock specifier for the clock connected as MCLK. + +Examples: + + max9860: max9860@10 { + compatible = "maxim,max9860"; + reg = <0x10>; + + AVDD-supply = <®_1v8>; + DVDD-supply = <®_1v8>; + DVDDIO-supply = <®_3v0>; + + clock-names = "mclk"; + clocks = <&pck2>; + }; diff --git a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt new file mode 100644 index 000000000000..3e623a724e55 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt @@ -0,0 +1,150 @@ +Mediatek AFE PCM controller for mt2701 + +Required properties: +- compatible = "mediatek,mt2701-audio"; +- reg: register location and size +- interrupts: Should contain AFE interrupt +- clock-names: should have these clock names: + "infra_sys_audio_clk", + "top_audio_mux1_sel", + "top_audio_mux2_sel", + "top_audio_mux1_div", + "top_audio_mux2_div", + "top_audio_48k_timing", + "top_audio_44k_timing", + "top_audpll_mux_sel", + "top_apll_sel", + "top_aud1_pll_98M", + "top_aud2_pll_90M", + "top_hadds2_pll_98M", + "top_hadds2_pll_294M", + "top_audpll", + "top_audpll_d4", + "top_audpll_d8", + "top_audpll_d16", + "top_audpll_d24", + "top_audintbus_sel", + "clk_26m", + "top_syspll1_d4", + "top_aud_k1_src_sel", + "top_aud_k2_src_sel", + "top_aud_k3_src_sel", + "top_aud_k4_src_sel", + "top_aud_k5_src_sel", + "top_aud_k6_src_sel", + "top_aud_k1_src_div", + "top_aud_k2_src_div", + "top_aud_k3_src_div", + "top_aud_k4_src_div", + "top_aud_k5_src_div", + "top_aud_k6_src_div", + "top_aud_i2s1_mclk", + "top_aud_i2s2_mclk", + "top_aud_i2s3_mclk", + "top_aud_i2s4_mclk", + "top_aud_i2s5_mclk", + "top_aud_i2s6_mclk", + "top_asm_m_sel", + "top_asm_h_sel", + "top_univpll2_d4", + "top_univpll2_d2", + "top_syspll_d5"; + +Example: + + afe: mt2701-afe-pcm@11220000 { + compatible = "mediatek,mt2701-audio"; + reg = <0 0x11220000 0 0x2000>, + <0 0x112A0000 0 0x20000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_AUDIO>, + <&topckgen CLK_TOP_AUD_MUX1_SEL>, + <&topckgen CLK_TOP_AUD_MUX2_SEL>, + <&topckgen CLK_TOP_AUD_MUX1_DIV>, + <&topckgen CLK_TOP_AUD_MUX2_DIV>, + <&topckgen CLK_TOP_AUD_48K_TIMING>, + <&topckgen CLK_TOP_AUD_44K_TIMING>, + <&topckgen CLK_TOP_AUDPLL_MUX_SEL>, + <&topckgen CLK_TOP_APLL_SEL>, + <&topckgen CLK_TOP_AUD1PLL_98M>, + <&topckgen CLK_TOP_AUD2PLL_90M>, + <&topckgen CLK_TOP_HADDS2PLL_98M>, + <&topckgen CLK_TOP_HADDS2PLL_294M>, + <&topckgen CLK_TOP_AUDPLL>, + <&topckgen CLK_TOP_AUDPLL_D4>, + <&topckgen CLK_TOP_AUDPLL_D8>, + <&topckgen CLK_TOP_AUDPLL_D16>, + <&topckgen CLK_TOP_AUDPLL_D24>, + <&topckgen CLK_TOP_AUDINTBUS_SEL>, + <&clk26m>, + <&topckgen CLK_TOP_SYSPLL1_D4>, + <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K5_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K6_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K5_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K6_SRC_DIV>, + <&topckgen CLK_TOP_AUD_I2S1_MCLK>, + <&topckgen CLK_TOP_AUD_I2S2_MCLK>, + <&topckgen CLK_TOP_AUD_I2S3_MCLK>, + <&topckgen CLK_TOP_AUD_I2S4_MCLK>, + <&topckgen CLK_TOP_AUD_I2S5_MCLK>, + <&topckgen CLK_TOP_AUD_I2S6_MCLK>, + <&topckgen CLK_TOP_ASM_M_SEL>, + <&topckgen CLK_TOP_ASM_H_SEL>, + <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_UNIVPLL2_D2>, + <&topckgen CLK_TOP_SYSPLL_D5>; + + clock-names = "infra_sys_audio_clk", + "top_audio_mux1_sel", + "top_audio_mux2_sel", + "top_audio_mux1_div", + "top_audio_mux2_div", + "top_audio_48k_timing", + "top_audio_44k_timing", + "top_audpll_mux_sel", + "top_apll_sel", + "top_aud1_pll_98M", + "top_aud2_pll_90M", + "top_hadds2_pll_98M", + "top_hadds2_pll_294M", + "top_audpll", + "top_audpll_d4", + "top_audpll_d8", + "top_audpll_d16", + "top_audpll_d24", + "top_audintbus_sel", + "clk_26m", + "top_syspll1_d4", + "top_aud_k1_src_sel", + "top_aud_k2_src_sel", + "top_aud_k3_src_sel", + "top_aud_k4_src_sel", + "top_aud_k5_src_sel", + "top_aud_k6_src_sel", + "top_aud_k1_src_div", + "top_aud_k2_src_div", + "top_aud_k3_src_div", + "top_aud_k4_src_div", + "top_aud_k5_src_div", + "top_aud_k6_src_div", + "top_aud_i2s1_mclk", + "top_aud_i2s2_mclk", + "top_aud_i2s3_mclk", + "top_aud_i2s4_mclk", + "top_aud_i2s5_mclk", + "top_aud_i2s6_mclk", + "top_asm_m_sel", + "top_asm_h_sel", + "top_univpll2_d4", + "top_univpll2_d2", + "top_syspll_d5"; + }; diff --git a/Documentation/devicetree/bindings/sound/mt2701-cs42448.txt b/Documentation/devicetree/bindings/sound/mt2701-cs42448.txt new file mode 100644 index 000000000000..05574446ceb6 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mt2701-cs42448.txt @@ -0,0 +1,43 @@ +MT2701 with CS42448 CODEC + +Required properties: +- compatible: "mediatek,mt2701-cs42448-machine" +- mediatek,platform: the phandle of MT2701 ASoC platform +- audio-routing: a list of the connections between audio +- mediatek,audio-codec: the phandles of cs42448 codec +- mediatek,audio-codec-bt-mrg the phandles of bt-sco dummy codec +- pinctrl-names: Should contain only one value - "default" +- pinctrl-0: Should specify pin control groups used for this controller. +- i2s1-in-sel-gpio1, i2s1-in-sel-gpio2: Should specify two gpio pins to + control I2S1-in mux. + +Example: + + sound:sound { + compatible = "mediatek,mt2701-cs42448-machine"; + mediatek,platform = <&afe>; + /* CS42448 Machine name */ + audio-routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "AMIC", + "AIN1R", "AMIC", + "AIN2L", "Tuner In", + "AIN2R", "Tuner In", + "AIN3L", "Satellite Tuner In", + "AIN3R", "Satellite Tuner In", + "AIN3L", "AUX In", + "AIN3R", "AUX In"; + mediatek,audio-codec = <&cs42448>; + mediatek,audio-codec-bt-mrg = <&bt_sco_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&aud_pins_default>; + i2s1-in-sel-gpio1 = <&pio 53 0>; + i2s1-in-sel-gpio2 = <&pio 54 0>; + }; diff --git a/Documentation/devicetree/bindings/sound/mt8173-rt5650.txt b/Documentation/devicetree/bindings/sound/mt8173-rt5650.txt index 5bfa6b60530b..29dce2ac8773 100644 --- a/Documentation/devicetree/bindings/sound/mt8173-rt5650.txt +++ b/Documentation/devicetree/bindings/sound/mt8173-rt5650.txt @@ -1,8 +1,9 @@ -MT8173 with RT5650 CODECS +MT8173 with RT5650 CODECS and HDMI via I2S Required properties: - compatible : "mediatek,mt8173-rt5650" - mediatek,audio-codec: the phandles of rt5650 codecs + and of the hdmi encoder node - mediatek,platform: the phandle of MT8173 ASoC platform Optional subnodes: @@ -12,12 +13,17 @@ Required codec-capture subnode properties: <&rt5650 0> : Default setting. Connect rt5650 I2S1 for capture. (dai_name = rt5645-aif1) <&rt5650 1> : Connect rt5650 I2S2 for capture. (dai_name = rt5645-aif2) +- mediatek,mclk: the MCLK source + 0 : external oscillator, MCLK = 12.288M + 1 : internal source from mt8173, MCLK = sampling rate*256 + Example: sound { compatible = "mediatek,mt8173-rt5650"; - mediatek,audio-codec = <&rt5650>; + mediatek,audio-codec = <&rt5650 &hdmi0>; mediatek,platform = <&afe>; + mediatek,mclk = <0>; codec-capture { sound-dai = <&rt5650 1>; }; diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index c7b29df4a963..15a7316e4c91 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt @@ -373,6 +373,8 @@ Optional properties: - #clock-cells : it must be 0 if your system has audio_clkout it must be 1 if your system has audio_clkout0/1/2/3 - clock-frequency : for all audio_clkout0/1/2/3 +- clkout-lr-asynchronous : boolean property. it indicates that audio_clkoutn + is asynchronizes with lr-clock. SSI subnode properties: - interrupts : Should contain SSI interrupt for PIO transfer diff --git a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt index 6e86d8aa29b4..4ea29aa9af59 100644 --- a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt +++ b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt @@ -23,6 +23,11 @@ Required properties: - rockchip,playback-channels: max playback channels, if not set, 8 channels default. - rockchip,capture-channels: max capture channels, if not set, 2 channels default. +Required properties for controller which support multi channels +playback/capture: + +- rockchip,grf: the phandle of the syscon node for GRF register. + Example for rk3288 I2S controller: i2s@ff890000 { |
