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-rw-r--r--Documentation/devicetree/bindings/display/fsl,dcu.txt11
-rw-r--r--drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c2
-rw-r--r--drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c16
-rw-r--r--drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h1
4 files changed, 24 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt
index ebf1be9ae393..2703cf29dd04 100644
--- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
+++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
@@ -6,8 +6,11 @@ Required properties:
* "fsl,vf610-dcu".
- reg: Address and length of the register set for dcu.
-- clocks: From common clock binding: handle to dcu clock.
-- clock-names: From common clock binding: Shall be "dcu".
+- clocks: Handle to "dcu" and "pix" clock (in the order below)
+ This can be the same clock (e.g. LS1021a)
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Should be "dcu" and "pix"
+ See ../clocks/clock-bindings.txt for details.
- big-endian Boolean property, LS1021A DCU registers are big-endian.
- fsl,panel: The phandle to panel node.
@@ -15,8 +18,8 @@ Examples:
dcu: dcu@2ce0000 {
compatible = "fsl,ls1021a-dcu";
reg = <0x0 0x2ce0000 0x0 0x10000>;
- clocks = <&platform_clk 0>;
- clock-names = "dcu";
+ clocks = <&platform_clk 0>, <&platform_clk 0>;
+ clock-names = "dcu", "pix";
big-endian;
fsl,panel = <&panel>;
};
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index 4ed7798533f9..87d85faaac6a 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -71,7 +71,7 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
unsigned long dcuclk;
index = drm_crtc_index(crtc);
- dcuclk = clk_get_rate(fsl_dev->clk);
+ dcuclk = clk_get_rate(fsl_dev->pix_clk);
div = dcuclk / mode->clock / 1000;
/* Configure timings: */
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index f2a9c1bb32c0..f80c116018b5 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -331,10 +331,21 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
return ret;
}
+ fsl_dev->pix_clk = devm_clk_get(dev, "pix");
+ if (IS_ERR(fsl_dev->pix_clk)) {
+ /* legancy binding, use dcu clock as pixel clock */
+ fsl_dev->pix_clk = fsl_dev->clk;
+ }
+ ret = clk_prepare_enable(fsl_dev->pix_clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable pix clk\n");
+ goto disable_clk;
+ }
+
drm = drm_dev_alloc(driver, dev);
if (!drm) {
ret = -ENOMEM;
- goto disable_clk;
+ goto disable_pix_clk;
}
fsl_dev->dev = dev;
@@ -355,6 +366,8 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
unref:
drm_dev_unref(drm);
+disable_pix_clk:
+ clk_disable_unprepare(fsl_dev->pix_clk);
disable_clk:
clk_disable_unprepare(fsl_dev->clk);
return ret;
@@ -365,6 +378,7 @@ static int fsl_dcu_drm_remove(struct platform_device *pdev)
struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
clk_disable_unprepare(fsl_dev->clk);
+ clk_disable_unprepare(fsl_dev->pix_clk);
drm_put_dev(fsl_dev->drm);
return 0;
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
index 6413ac9e4769..edb210277771 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
@@ -183,6 +183,7 @@ struct fsl_dcu_drm_device {
struct regmap *regmap;
int irq;
struct clk *clk;
+ struct clk *pix_clk;
/*protects hardware register*/
spinlock_t irq_lock;
struct drm_device *drm;
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