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-rw-r--r--arch/arm/boot/dts/omap5.dtsi60
-rw-r--r--arch/arm/mach-omap1/ocpi.c1
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c79
-rw-r--r--arch/arm/mach-omap2/usb-tusb6010.c1
4 files changed, 97 insertions, 44 deletions
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index a4ed54988866..8eee6fbef7ad 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -985,6 +985,66 @@
dma-names = "audio_tx";
};
};
+
+ abb_mpu: regulator-abb-mpu {
+ compatible = "ti,abb-v2";
+ regulator-name = "abb_mpu";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ clocks = <&sys_clkin>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
+ <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
+ reg-names = "base-address", "int-address",
+ "efuse-address", "ldo-address";
+ ti,tranxdone-status-mask = <0x80>;
+ /* LDOVBBMPU_MUX_CTRL */
+ ti,ldovbb-override-mask = <0x400>;
+ /* LDOVBBMPU_VSET_OUT */
+ ti,ldovbb-vset-mask = <0x1F>;
+
+ /*
+ * NOTE: only FBB mode used but actual vset will
+ * determine final biasing
+ */
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1060000 0 0x0 0 0x02000000 0x01F00000
+ 1250000 0 0x4 0 0x02000000 0x01F00000
+ >;
+ };
+
+ abb_mm: regulator-abb-mm {
+ compatible = "ti,abb-v2";
+ regulator-name = "abb_mm";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ clocks = <&sys_clkin>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
+ <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
+ reg-names = "base-address", "int-address",
+ "efuse-address", "ldo-address";
+ ti,tranxdone-status-mask = <0x80000000>;
+ /* LDOVBBMM_MUX_CTRL */
+ ti,ldovbb-override-mask = <0x400>;
+ /* LDOVBBMM_VSET_OUT */
+ ti,ldovbb-vset-mask = <0x1F>;
+
+ /*
+ * NOTE: only FBB mode used but actual vset will
+ * determine final biasing
+ */
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1025000 0 0x0 0 0x02000000 0x01F00000
+ 1120000 0 0x4 0 0x02000000 0x01F00000
+ >;
+ };
};
};
diff --git a/arch/arm/mach-omap1/ocpi.c b/arch/arm/mach-omap1/ocpi.c
index 238170cab5b7..44a3d19eb481 100644
--- a/arch/arm/mach-omap1/ocpi.c
+++ b/arch/arm/mach-omap1/ocpi.c
@@ -55,7 +55,6 @@ static struct clk *ocpi_ck;
/*
* Enables device access to OMAP buses via the OCPI bridge
- * FIXME: Add locking
*/
int ocpi_enable(void)
{
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 17cd39360afe..7ab486eeb769 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -24,25 +24,6 @@
/* minimum size for IO mapping */
#define NAND_IO_SIZE 4
-static struct resource gpmc_nand_resource[] = {
- {
- .flags = IORESOURCE_MEM,
- },
- {
- .flags = IORESOURCE_IRQ,
- },
- {
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device gpmc_nand_device = {
- .name = "omap2-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(gpmc_nand_resource),
- .resource = gpmc_nand_resource,
-};
-
static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
{
/* platforms which support all ECC schemes */
@@ -93,43 +74,41 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
{
int err = 0;
struct gpmc_settings s;
- struct device *dev = &gpmc_nand_device.dev;
-
- memset(&s, 0, sizeof(struct gpmc_settings));
+ struct platform_device *pdev;
+ struct resource gpmc_nand_res[] = {
+ { .flags = IORESOURCE_MEM, },
+ { .flags = IORESOURCE_IRQ, },
+ { .flags = IORESOURCE_IRQ, },
+ };
- gpmc_nand_device.dev.platform_data = gpmc_nand_data;
+ BUG_ON(gpmc_nand_data->cs >= GPMC_CS_NUM);
err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
- (unsigned long *)&gpmc_nand_resource[0].start);
+ (unsigned long *)&gpmc_nand_res[0].start);
if (err < 0) {
- dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
- gpmc_nand_data->cs, err);
+ pr_err("omap2-gpmc: Cannot request GPMC CS %d, error %d\n",
+ gpmc_nand_data->cs, err);
return err;
}
-
- gpmc_nand_resource[0].end = gpmc_nand_resource[0].start +
- NAND_IO_SIZE - 1;
-
- gpmc_nand_resource[1].start =
- gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
- gpmc_nand_resource[2].start =
- gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
+ gpmc_nand_res[0].end = gpmc_nand_res[0].start + NAND_IO_SIZE - 1;
+ gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
+ gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
if (gpmc_t) {
err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
if (err < 0) {
- dev_err(dev, "Unable to set gpmc timings: %d\n", err);
+ pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n", err);
return err;
}
}
+ memset(&s, 0, sizeof(struct gpmc_settings));
if (gpmc_nand_data->of_node)
gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
else
gpmc_set_legacy(gpmc_nand_data, &s);
s.device_nand = true;
-
err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
if (err < 0)
goto out_free_cs;
@@ -141,18 +120,34 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
- dev_err(dev, "Unsupported NAND ECC scheme selected\n");
- return -EINVAL;
+ pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n");
+ err = -EINVAL;
+ goto out_free_cs;
}
- err = platform_device_register(&gpmc_nand_device);
- if (err < 0) {
- dev_err(dev, "Unable to register NAND device\n");
- goto out_free_cs;
+
+ pdev = platform_device_alloc("omap2-nand", gpmc_nand_data->cs);
+ if (pdev) {
+ err = platform_device_add_resources(pdev, gpmc_nand_res,
+ ARRAY_SIZE(gpmc_nand_res));
+ if (!err)
+ pdev->dev.platform_data = gpmc_nand_data;
+ } else {
+ err = -ENOMEM;
+ }
+ if (err)
+ goto out_free_pdev;
+
+ err = platform_device_add(pdev);
+ if (err) {
+ dev_err(&pdev->dev, "Unable to register NAND device\n");
+ goto out_free_pdev;
}
return 0;
+out_free_pdev:
+ platform_device_put(pdev);
out_free_cs:
gpmc_cs_free(gpmc_nand_data->cs);
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index e832bc7b8e2d..8333400898fb 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -95,7 +95,6 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
dev_t.t_avdp_w = t_scsnh_advnh;
dev_t.cyc_aavdh_we = 3;
dev_t.cyc_wpl = 6;
- dev_t.t_ce_rdyz = 7000;
gpmc_calc_timings(&t, &tusb_sync, &dev_t);
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