diff options
| -rw-r--r-- | arch/powerpc/platforms/83xx/mpc834x_sys.c | 73 | ||||
| -rw-r--r-- | arch/powerpc/platforms/83xx/mpc83xx.h | 18 |
2 files changed, 91 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/83xx/mpc834x_sys.c b/arch/powerpc/platforms/83xx/mpc834x_sys.c index f30393f0b832..873ec543c361 100644 --- a/arch/powerpc/platforms/83xx/mpc834x_sys.c +++ b/arch/powerpc/platforms/83xx/mpc834x_sys.c @@ -43,6 +43,76 @@ unsigned long isa_io_base = 0; unsigned long isa_mem_base = 0; #endif +#define BCSR5_INT_USB 0x02 +/* Note: This is only for PB, not for PB+PIB + * On PB only port0 is connected using ULPI */ +static int mpc834x_usb_cfg(void) +{ + unsigned long sccr, sicrl; + void __iomem *immap; + void __iomem *bcsr_regs = NULL; + u8 bcsr5; + struct device_node *np = NULL; + int port0_is_dr = 0; + + if ((np = of_find_compatible_node(np, "usb", "fsl-usb2-dr")) != NULL) + port0_is_dr = 1; + if ((np = of_find_compatible_node(np, "usb", "fsl-usb2-mph")) != NULL){ + if (port0_is_dr) { + printk(KERN_WARNING + "There is only one USB port on PB board! \n"); + return -1; + } else if (!port0_is_dr) + /* No usb port enabled */ + return -1; + } + + immap = ioremap(get_immrbase(), 0x1000); + if (!immap) + return -1; + + /* Configure clock */ + sccr = in_be32(immap + MPC83XX_SCCR_OFFS); + if (port0_is_dr) + sccr |= MPC83XX_SCCR_USB_DRCM_11; /* 1:3 */ + else + sccr |= MPC83XX_SCCR_USB_MPHCM_11; /* 1:3 */ + out_be32(immap + MPC83XX_SCCR_OFFS, sccr); + + /* Configure Pin */ + sicrl = in_be32(immap + MPC83XX_SICRL_OFFS); + /* set port0 only */ + if (port0_is_dr) + sicrl |= MPC83XX_SICRL_USB0; + else + sicrl &= ~(MPC83XX_SICRL_USB0); + out_be32(immap + MPC83XX_SICRL_OFFS, sicrl); + + iounmap(immap); + + /* Map BCSR area */ + np = of_find_node_by_name(NULL, "bcsr"); + if (np != 0) { + struct resource res; + + of_address_to_resource(np, 0, &res); + bcsr_regs = ioremap(res.start, res.end - res.start + 1); + of_node_put(np); + } + if (!bcsr_regs) + return -1; + + /* + * if SYS board is plug into PIB board, + * force to use the PHY on SYS board + */ + bcsr5 = in_8(bcsr_regs + 5); + if (!(bcsr5 & BCSR5_INT_USB)) + out_8(bcsr_regs + 5, (bcsr5 | BCSR5_INT_USB)); + iounmap(bcsr_regs); + return 0; +} + /* ************************************************************************ * * Setup the architecture @@ -65,6 +135,7 @@ static void __init mpc834x_sys_setup_arch(void) loops_per_jiffy = 50000000 / HZ; of_node_put(np); } + #ifdef CONFIG_PCI for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) add_bridge(np); @@ -72,6 +143,8 @@ static void __init mpc834x_sys_setup_arch(void) ppc_md.pci_exclude_device = mpc83xx_exclude_device; #endif + mpc834x_usb_cfg(); + #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h index 01cae106912b..9cd03b59c8f4 100644 --- a/arch/powerpc/platforms/83xx/mpc83xx.h +++ b/arch/powerpc/platforms/83xx/mpc83xx.h @@ -4,6 +4,24 @@ #include <linux/init.h> #include <linux/device.h> +/* System Clock Control Register */ +#define MPC83XX_SCCR_OFFS 0xA08 +#define MPC83XX_SCCR_USB_MPHCM_11 0x00c00000 +#define MPC83XX_SCCR_USB_MPHCM_01 0x00400000 +#define MPC83XX_SCCR_USB_MPHCM_10 0x00800000 +#define MPC83XX_SCCR_USB_DRCM_11 0x00300000 +#define MPC83XX_SCCR_USB_DRCM_01 0x00100000 +#define MPC83XX_SCCR_USB_DRCM_10 0x00200000 + +/* system i/o configuration register low */ +#define MPC83XX_SICRL_OFFS 0x114 +#define MPC83XX_SICRL_USB0 0x40000000 +#define MPC83XX_SICRL_USB1 0x20000000 + +/* system i/o configuration register high */ +#define MPC83XX_SICRH_OFFS 0x118 +#define MPC83XX_SICRH_USB_UTMI 0x00020000 + /* * Declaration for the various functions exported by the * mpc83xx_* files. Mostly for use by mpc83xx_setup |
