diff options
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 26 | ||||
| -rw-r--r-- | arch/mips/kernel/traps.c | 4 |
2 files changed, 17 insertions, 13 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 7e4e6f8fab37..1ad3e34e18e6 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1142,17 +1142,21 @@ do { \ /* * Macros to access the floating point coprocessor control registers */ -#define read_32bit_cp1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - /* gas fails to assemble cfc1 for some archs (octeon).*/ \ - ".set\tmips1\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) +#define read_32bit_cp1_register(source) \ +({ \ + int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set reorder \n" \ + " # gas fails to assemble cfc1 for some archs, \n" \ + " # like Octeon. \n" \ + " .set mips1 \n" \ + " cfc1 %0,"STR(source)" \n" \ + " .set pop \n" \ + : "=r" (__res)); \ + __res; \ +}) #define rddsp(mask) \ ({ \ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index cf7ac5483f53..e3a5f3ddab1a 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -518,7 +518,7 @@ static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) offset >>= 16; vaddr = (unsigned long __user *) - ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); + ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); if ((unsigned long)vaddr & 3) return SIGBUS; @@ -558,7 +558,7 @@ static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) offset >>= 16; vaddr = (unsigned long __user *) - ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); + ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); reg = (opcode & RT) >> 16; if ((unsigned long)vaddr & 3) |
