diff options
680 files changed, 23466 insertions, 11027 deletions
diff --git a/Documentation/arm/memory.txt b/Documentation/arm/memory.txt index eb0fae18ffb1..771d48d3b335 100644 --- a/Documentation/arm/memory.txt +++ b/Documentation/arm/memory.txt @@ -33,7 +33,13 @@ ffff0000 ffff0fff CPU vector page. fffe0000 fffeffff XScale cache flush area. This is used in proc-xscale.S to flush the whole data - cache. Free for other usage on non-XScale. + cache. (XScale does not have TCM.) + +fffe8000 fffeffff DTCM mapping area for platforms with + DTCM mounted inside the CPU. + +fffe0000 fffe7fff ITCM mapping area for platforms with + ITCM mounted inside the CPU. fff00000 fffdffff Fixmap mapping region. Addresses provided by fix_to_virt() will be located here. diff --git a/Documentation/arm/tcm.txt b/Documentation/arm/tcm.txt index 77fd9376e6d7..7c15871c1885 100644 --- a/Documentation/arm/tcm.txt +++ b/Documentation/arm/tcm.txt @@ -19,8 +19,8 @@ defines a CPUID_TCM register that you can read out from the system control coprocessor. Documentation from ARM can be found at http://infocenter.arm.com, search for "TCM Status Register" to see documents for all CPUs. Reading this register you can -determine if ITCM (bit 0) and/or DTCM (bit 16) is present in the -machine. +determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present +in the machine. There is further a TCM region register (search for "TCM Region Registers" at the ARM site) that can report and modify the location @@ -35,7 +35,15 @@ The TCM memory can then be remapped to another address again using the MMU, but notice that the TCM if often used in situations where the MMU is turned off. To avoid confusion the current Linux implementation will map the TCM 1 to 1 from physical to virtual -memory in the location specified by the machine. +memory in the location specified by the kernel. Currently Linux +will map ITCM to 0xfffe0000 and on, and DTCM to 0xfffe8000 and +on, supporting a maximum of 32KiB of ITCM and 32KiB of DTCM. + +Newer versions of the region registers also support dividing these +TCMs in two separate banks, so for example an 8KiB ITCM is divided +into two 4KiB banks with its own control registers. The idea is to +be able to lock and hide one of the banks for use by the secure +world (TrustZone). TCM is used for a few things: @@ -65,18 +73,18 @@ in <asm/tcm.h>. Using this interface it is possible to: memory. Such a heap is great for things like saving device state when shutting off device power domains. -A machine that has TCM memory shall select HAVE_TCM in -arch/arm/Kconfig for itself, and then the -rest of the functionality will depend on the physical -location and size of ITCM and DTCM to be defined in -mach/memory.h for the machine. Code that needs to use -TCM shall #include <asm/tcm.h> If the TCM is not located -at the place given in memory.h it will be moved using -the TCM Region registers. +A machine that has TCM memory shall select HAVE_TCM from +arch/arm/Kconfig for itself. Code that needs to use TCM shall +#include <asm/tcm.h> Functions to go into itcm can be tagged like this: int __tcmfunc foo(int bar); +Since these are marked to become long_calls and you may want +to have functions called locally inside the TCM without +wasting space, there is also the __tcmlocalfunc prefix that +will make the call relative. + Variables to go into dtcm can be tagged like this: int __tcmdata foo; diff --git a/Documentation/credentials.txt b/Documentation/credentials.txt index a2db35287003..995baf379c07 100644 --- a/Documentation/credentials.txt +++ b/Documentation/credentials.txt @@ -417,6 +417,9 @@ reference on them using: This does all the RCU magic inside of it. The caller must call put_cred() on the credentials so obtained when they're finished with. + [*] Note: The result of __task_cred() should not be passed directly to + get_cred() as this may race with commit_cred(). + There are a couple of convenience functions to access bits of another task's credentials, hiding the RCU magic from the caller: diff --git a/Documentation/filesystems/xfs.txt b/Documentation/filesystems/xfs.txt index 9878f50d6ed6..7bff3e4f35df 100644 --- a/Documentation/filesystems/xfs.txt +++ b/Documentation/filesystems/xfs.txt @@ -131,17 +131,6 @@ When mounting an XFS filesystem, the following options are accepted. Don't check for double mounted file systems using the file system uuid. This is useful to mount LVM snapshot volumes. - osyncisosync - Make O_SYNC writes implement true O_SYNC. WITHOUT this option, - Linux XFS behaves as if an "osyncisdsync" option is used, - which will make writes to files opened with the O_SYNC flag set - behave as if the O_DSYNC flag had been used instead. - This can result in better performance without compromising - data safety. - However if this option is not in effect, timestamp updates from - O_SYNC writes can be lost if the system crashes. - If timestamp updates are critical, use the osyncisosync option. - uquota/usrquota/uqnoenforce/quota User disk quota accounting enabled, and limits (optionally) enforced. Refer to xfs_quota(8) for further details. diff --git a/MAINTAINERS b/MAINTAINERS index db3d0f5061f9..02f75fccac20 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6243,6 +6243,8 @@ F: drivers/mmc/host/wbsd.* WATCHDOG DEVICE DRIVERS M: Wim Van Sebroeck <wim@iguana.be> +L: linux-watchdog@vger.kernel.org +W: http://www.linux-watchdog.org/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog.git S: Maintained F: Documentation/watchdog/ @@ -1,7 +1,7 @@ VERSION = 2 PATCHLEVEL = 6 SUBLEVEL = 35 -EXTRAVERSION = -rc6 +EXTRAVERSION = NAME = Sheep on Meth # *DOCUMENTATION* diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 98922f7d2d12..e39caa8b0c93 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -10,6 +10,7 @@ config ARM default y select HAVE_AOUT select HAVE_IDE + select HAVE_MEMBLOCK select RTC_LIB select SYS_SUPPORTS_APM_EMULATION select GENERIC_ATOMIC64 if (!CPU_32v6K) @@ -24,6 +25,7 @@ config ARM select HAVE_KERNEL_LZMA select HAVE_PERF_EVENTS select PERF_USE_VMALLOC + select HAVE_REGS_AND_STACK_ACCESS_API help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and @@ -55,7 +57,7 @@ config GENERIC_CLOCKEVENTS config GENERIC_CLOCKEVENTS_BROADCAST bool depends on GENERIC_CLOCKEVENTS - default y if SMP && !LOCAL_TIMERS + default y if SMP config HAVE_TCM bool @@ -301,6 +303,7 @@ config ARCH_CNS3XXX select CPU_V6 select GENERIC_CLOCKEVENTS select ARM_GIC + select PCI_DOMAINS if PCI help Support for Cavium Networks CNS3XXX platform. @@ -439,21 +442,6 @@ config ARCH_IXP4XX help Support for Intel's IXP4XX (XScale) family of processors. -config ARCH_L7200 - bool "LinkUp-L7200" - select CPU_ARM720T - select FIQ - select ARCH_USES_GETTIMEOFFSET - help - Say Y here if you intend to run this kernel on a LinkUp Systems - L7200 Software Development Board which uses an ARM720T processor. - Information on this board can be obtained at: - - <http://www.linkupsys.com/> - - If you have any questions or comments about the Linux kernel port - to this board, send e-mail to <sjhill@cotw.com>. - config ARCH_DOVE bool "Marvell Dove" select PCI @@ -482,6 +470,19 @@ config ARCH_LOKI help Support for the Marvell Loki (88RC8480) SoC. +config ARCH_LPC32XX + bool "NXP LPC32XX" + select CPU_ARM926T + select ARCH_REQUIRE_GPIOLIB + select HAVE_IDE + select ARM_AMBA + select USB_ARCH_HAS_OHCI + select COMMON_CLKDEV + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + help + Support for the NXP LPC32XX family of processors + config ARCH_MV78XX0 bool "Marvell MV78xx0" select CPU_FEROCEON @@ -586,6 +587,7 @@ config ARCH_MSM bool "Qualcomm MSM" select HAVE_CLK select GENERIC_CLOCKEVENTS + select ARCH_REQUIRE_GPIOLIB help Support for Qualcomm MSM/QSD based systems. This runs on the apps processor of the MSM/QSD and depends on a shared memory @@ -719,7 +721,6 @@ config ARCH_SHARK config ARCH_LH7A40X bool "Sharp LH7A40X" select CPU_ARM922T - select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM select ARCH_USES_GETTIMEOFFSET help @@ -845,6 +846,8 @@ source "arch/arm/mach-lh7a40x/Kconfig" source "arch/arm/mach-loki/Kconfig" +source "arch/arm/mach-lpc32xx/Kconfig" + source "arch/arm/mach-msm/Kconfig" source "arch/arm/mach-mv78xx0/Kconfig" @@ -1031,11 +1034,6 @@ endmenu source "arch/arm/common/Kconfig" -config FORCE_MAX_ZONEORDER - int - depends on SA1111 - default "9" - menu "Bus support" config ARM_AMBA @@ -1060,7 +1058,7 @@ config ISA_DMA_API bool config PCI - bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE + bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX help Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside @@ -1172,9 +1170,10 @@ config HOTPLUG_CPU config LOCAL_TIMERS bool "Use local timer interrupts" depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \ - REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500) + REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ + ARCH_U8500 || ARCH_VEXPRESS_CA9X4) default y - select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500) + select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_VEXPRESS || ARCH_OMAP4 || ARCH_U8500) help Enable support for local timers on SMP platforms, rather then the legacy IPI broadcast method. Local timers allows the system @@ -1185,10 +1184,10 @@ source kernel/Kconfig.preempt config HZ int - default 128 if ARCH_L7200 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER default AT91_TIMER_HZ if ARCH_AT91 + default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE default 100 config THUMB2_KERNEL @@ -1241,10 +1240,6 @@ config OABI_COMPAT config ARCH_HAS_HOLES_MEMORYMODEL bool -# Discontigmem is deprecated -config ARCH_DISCONTIGMEM_ENABLE - bool - config ARCH_SPARSEMEM_ENABLE bool @@ -1252,13 +1247,7 @@ config ARCH_SPARSEMEM_DEFAULT def_bool ARCH_SPARSEMEM_ENABLE config ARCH_SELECT_MEMORY_MODEL - def_bool ARCH_DISCONTIGMEM_ENABLE && ARCH_SPARSEMEM_ENABLE - -config NODES_SHIFT - int - default "4" if ARCH_LH7A40X - default "2" - depends on NEED_MULTIPLE_NODES + def_bool ARCH_SPARSEMEM_ENABLE config HIGHMEM bool "High Memory Support (EXPERIMENTAL)" @@ -1290,8 +1279,33 @@ config HW_PERF_EVENTS Enable hardware performance counter support for perf events. If disabled, perf events will use software events only. +config SPARSE_IRQ + def_bool n + help + This enables support for sparse irqs. This is useful in general + as most CPUs have a fairly sparse array of IRQ vectors, which + the irq_desc then maps directly on to. Systems with a high + number of off-chip IRQs will want to treat this as + experimental until they have been independently verified. + source "mm/Kconfig" +config FORCE_MAX_ZONEORDER + int "Maximum zone order" if ARCH_SHMOBILE + range 11 64 if ARCH_SHMOBILE + default "9" if SA1111 + default "11" + help + The kernel memory allocator divides physically contiguous memory + blocks into "zones", where each zone is a power of two number of + pages. This option selects the largest power of two that the kernel + keeps in the memory allocator. If you need to allocate very large + blocks of physically contiguous memory, then you may need to + increase this value. + + This config option is actually maximum order plus one. For example, + a value of 11 means that the largest free memory block is 2^10 pages. + config LEDS bool "Timer and CPU usage LEDs" depends on ARCH_CDB89712 || ARCH_EBSA110 || \ @@ -1375,6 +1389,24 @@ config UACCESS_WITH_MEMCPY However, if the CPU data cache is using a write-allocate mode, this option is unlikely to provide any performance gain. +config CC_STACKPROTECTOR + bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" + help + This option turns on the -fstack-protector GCC feature. This + feature puts, at the beginning of functions, a canary value on + the stack just before the return address, and validates + the value just before actually returning. Stack based buffer + overflows (that need to overwrite this return address) now also + overwrite the canary, which gets detected and the attack is then + neutralized via a kernel panic. + This feature requires gcc version 4.2 or above. + +config DEPRECATED_PARAM_STRUCT + bool "Provide old way to pass kernel parameters" + help + This was deprecated in 2001 and announced to live on for 5 years. + Some old boot loaders still use this way. + endmenu menu "Boot options" @@ -1485,6 +1517,105 @@ config ATAGS_PROC Should the atags used to boot the kernel be exported in an "atags" file in procfs. Useful with kexec. +config AUTO_ZRELADDR + bool "Auto calculation of the decompressed kernel image address" + depends on !ZBOOT_ROM && !ARCH_U300 + help + ZRELADDR is the physical address where the decompressed kernel + image will be placed. If AUTO_ZRELADDR is selected, the address + will be determined at run-time by masking the current IP with + 0xf8000000. This assumes the zImage being placed in the first 128MB + from start of memory. + +config ZRELADDR + hex "Physical address of the decompressed kernel image" + depends on !AUTO_ZRELADDR + default 0x00008000 if ARCH_BCMRING ||\ + ARCH_CNS3XXX ||\ + ARCH_DOVE ||\ + ARCH_EBSA110 ||\ + ARCH_FOOTBRIDGE ||\ + ARCH_INTEGRATOR ||\ + ARCH_IOP13XX ||\ + ARCH_IOP33X ||\ + ARCH_IXP2000 ||\ + ARCH_IXP23XX ||\ + ARCH_IXP4XX ||\ + ARCH_KIRKWOOD ||\ + ARCH_KS8695 ||\ + ARCH_LOKI ||\ + ARCH_MMP ||\ + ARCH_MV78XX0 ||\ + ARCH_NOMADIK ||\ + ARCH_NUC93X ||\ + ARCH_NS9XXX ||\ + ARCH_ORION5X ||\ + ARCH_SPEAR3XX ||\ + ARCH_SPEAR6XX ||\ + ARCH_U8500 ||\ + ARCH_VERSATILE ||\ + ARCH_W90X900 + default 0x08008000 if ARCH_MX1 ||\ + ARCH_SHARK + default 0x10008000 if ARCH_MSM ||\ + ARCH_OMAP1 ||\ + ARCH_RPC + default 0x20008000 if ARCH_S5P6440 ||\ + ARCH_S5P6442 ||\ + ARCH_S5PC100 ||\ + ARCH_S5PV210 + default 0x30008000 if ARCH_S3C2410 ||\ + ARCH_S3C2400 ||\ + ARCH_S3C2412 ||\ + ARCH_S3C2416 ||\ + ARCH_S3C2440 ||\ + ARCH_S3C2443 + default 0x40008000 if ARCH_STMP378X ||\ + ARCH_STMP37XX ||\ + ARCH_SH7372 ||\ + ARCH_SH7377 + default 0x50008000 if ARCH_S3C64XX ||\ + ARCH_SH7367 + default 0x60008000 if ARCH_VEXPRESS + default 0x80008000 if ARCH_MX25 ||\ + ARCH_MX3 ||\ + ARCH_NETX ||\ + ARCH_OMAP2PLUS ||\ + ARCH_PNX4008 + default 0x90008000 if ARCH_MX5 ||\ + ARCH_MX91231 + default 0xa0008000 if ARCH_IOP32X ||\ + ARCH_PXA ||\ + MACH_MX27 + default 0xc0008000 if ARCH_LH7A40X ||\ + MACH_MX21 + default 0xf0008000 if ARCH_AAEC2000 ||\ + ARCH_L7200 + default 0xc0028000 if ARCH_CLPS711X + default 0x70008000 if ARCH_AT91 && (ARCH_AT91CAP9 || ARCH_AT91SAM9G45) + default 0x20008000 if ARCH_AT91 && !(ARCH_AT91CAP9 || ARCH_AT91SAM9G45) + default 0xc0008000 if ARCH_DAVINCI && ARCH_DAVINCI_DA8XX + default 0x80008000 if ARCH_DAVINCI && !ARCH_DAVINCI_DA8XX + default 0x00008000 if ARCH_EP93XX && EP93XX_SDCE3_SYNC_PHYS_OFFSET + default 0xc0008000 if ARCH_EP93XX && EP93XX_SDCE0_PHYS_OFFSET + default 0xd0008000 if ARCH_EP93XX && EP93XX_SDCE1_PHYS_OFFSET + default 0xe0008000 if ARCH_EP93XX && EP93XX_SDCE2_PHYS_OFFSET + default 0xf0008000 if ARCH_EP93XX && EP93XX_SDCE3_ASYNC_PHYS_OFFSET + default 0x00008000 if ARCH_GEMINI && GEMINI_MEM_SWAP + default 0x10008000 if ARCH_GEMINI && !GEMINI_MEM_SWAP + default 0x70008000 if ARCH_REALVIEW && REALVIEW_HIGH_PHYS_OFFSET + default 0x00008000 if ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET + default 0xc0208000 if ARCH_SA1100 && SA1111 + default 0xc0008000 if ARCH_SA1100 && !SA1111 + default 0x30108000 if ARCH_S3C2410 && PM_H1940 + default 0x28E08000 if ARCH_U300 && MACH_U300_SINGLE_RAM + default 0x48008000 if ARCH_U300 && !MACH_U300_SINGLE_RAM + help + ZRELADDR is the physical address where the decompressed kernel + image will be placed. ZRELADDR has to be specified when the + assumption of AUTO_ZRELADDR is not valid, or when ZBOOT_ROM is + selected. + endmenu menu "CPU Power Management" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 64ba313724d2..63d998e8c672 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -34,6 +34,10 @@ ifeq ($(CONFIG_FRAME_POINTER),y) KBUILD_CFLAGS +=-fno-omit-frame-pointer -mapcs -mno-sched-prolog endif +ifeq ($(CONFIG_CC_STACKPROTECTOR),y) +KBUILD_CFLAGS +=-fstack-protector +endif + ifeq ($(CONFIG_CPU_BIG_ENDIAN),y) KBUILD_CPPFLAGS += -mbig-endian AS += -EB @@ -139,14 +143,14 @@ machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood machine-$(CONFIG_ARCH_KS8695) := ks8695 -machine-$(CONFIG_ARCH_L7200) := l7200 machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x machine-$(CONFIG_ARCH_LOKI) := loki +machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx machine-$(CONFIG_ARCH_MMP) := mmp machine-$(CONFIG_ARCH_MSM) := msm machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 -machine-$(CONFIG_ARCH_MX1) := mx1 -machine-$(CONFIG_ARCH_MX2) := mx2 +machine-$(CONFIG_ARCH_MX1) := imx +machine-$(CONFIG_ARCH_MX2) := imx machine-$(CONFIG_ARCH_MX25) := mx25 machine-$(CONFIG_ARCH_MX3) := mx3 machine-$(CONFIG_ARCH_MX5) := mx5 diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile index 4a590f4113e2..f705213caa88 100644 --- a/arch/arm/boot/Makefile +++ b/arch/arm/boot/Makefile @@ -14,18 +14,16 @@ MKIMAGE := $(srctree)/scripts/mkuboot.sh ifneq ($(MACHINE),) -include $(srctree)/$(MACHINE)/Makefile.boot +-include $(srctree)/$(MACHINE)/Makefile.boot endif # Note: the following conditions must always be true: -# ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET) # PARAMS_PHYS must be within 4MB of ZRELADDR # INITRD_PHYS must be in RAM -ZRELADDR := $(zreladdr-y) PARAMS_PHYS := $(params_phys-y) INITRD_PHYS := $(initrd_phys-y) -export ZRELADDR INITRD_PHYS PARAMS_PHYS +export INITRD_PHYS PARAMS_PHYS targets := Image zImage xipImage bootpImage uImage @@ -67,7 +65,7 @@ quiet_cmd_uimage = UIMAGE $@ ifeq ($(CONFIG_ZBOOT_ROM),y) $(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT) else -$(obj)/uImage: LOADADDR=$(ZRELADDR) +$(obj)/uImage: LOADADDR=$(CONFIG_ZRELADDR) endif ifeq ($(CONFIG_THUMB2_KERNEL),y) diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 53faa9063a03..7636c9b3f9a7 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -4,6 +4,7 @@ # create a compressed vmlinuz image from the original vmlinux # +AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) HEAD = head.o OBJS = misc.o decompress.o FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c @@ -19,10 +20,6 @@ ifeq ($(CONFIG_ARCH_SHARK),y) OBJS += head-shark.o ofw-shark.o endif -ifeq ($(CONFIG_ARCH_L7200),y) -OBJS += head-l7200.o -endif - ifeq ($(CONFIG_ARCH_P720T),y) # Borrow this code from SA1100 OBJS += head-sa1100.o @@ -71,6 +68,9 @@ targets := vmlinux vmlinux.lds \ piggy.$(suffix_y) piggy.$(suffix_y).o \ font.o font.c head.o misc.o $(OBJS) +# Make sure files are removed during clean +extra-y += piggy.gzip piggy.lzo piggy.lzma lib1funcs.S + ifeq ($(CONFIG_FUNCTION_TRACER),y) ORIG_CFLAGS := $(KBUILD_CFLAGS) KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) @@ -79,19 +79,9 @@ endif EXTRA_CFLAGS := -fpic -fno-builtin EXTRA_AFLAGS := -Wa,-march=all -# Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via -# linker symbols. We only define initrd_phys and params_phys if the -# machine class defined the corresponding makefile variable. -LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR) ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) LDFLAGS_vmlinux += --be8 endif -ifneq ($(INITRD_PHYS),) -LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS) -endif -ifneq ($(PARAMS_PHYS),) -LDFLAGS_vmlinux += --defsym params_phys=$(PARAMS_PHYS) -endif # ? LDFLAGS_vmlinux += -p # Report unresolved symbol references diff --git a/arch/arm/boot/compressed/Makefile.debug b/arch/arm/boot/compressed/Makefile.debug deleted file mode 100644 index 491a037b2973..000000000000 --- a/arch/arm/boot/compressed/Makefile.debug +++ /dev/null @@ -1,23 +0,0 @@ -# -# linux/arch/arm/boot/compressed/Makefile -# -# create a compressed vmlinux image from the original vmlinux -# - -COMPRESSED_EXTRA=../../lib/ll_char_wr.o -OBJECTS=misc-debug.o ll_char_wr.aout.o - -CFLAGS=-D__KERNEL__ -O2 -DSTDC_HEADERS -DSTANDALONE_DEBUG -Wall -I../../../../include -c - -test-gzip: piggy.aout.o $(OBJECTS) - $(CC) -o $@ $(OBJECTS) piggy.aout.o - -misc-debug.o: misc.c - $(CC) $(CFLAGS) -o $@ misc.c - -piggy.aout.o: piggy.o - arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux piggy.o piggy.aout.o - -ll_char_wr.aout.o: $(COMPRESSED_EXTRA) - arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux $(COMPRESSED_EXTRA) ll_char_wr.aout.o - diff --git a/arch/arm/boot/compressed/head-l7200.S b/arch/arm/boot/compressed/head-l7200.S deleted file mode 100644 index d0e3b20856cd..000000000000 --- a/arch/arm/boot/compressed/head-l7200.S +++ /dev/null @@ -1,29 +0,0 @@ -/* - * linux/arch/arm/boot/compressed/head-l7200.S - * - * Copyright (C) 2000 Steve Hill <sjhill@cotw.com> - * - * Some code borrowed from Nicolas Pitre's 'head-sa1100.S' file. This - * is merged with head.S by the linker. - */ - -#include <asm/mach-types.h> - -#ifndef CONFIG_ARCH_L7200 -#error What am I doing here... -#endif - - .section ".start", "ax" - -__L7200_start: - mov r0, #0x00100000 @ FLASH address of initrd - mov r2, #0xf1000000 @ RAM address of initrd - add r3, r2, #0x00700000 @ Size of initrd -1: - ldmia r0!, {r4, r5, r6, r7} - stmia r2!, {r4, r5, r6, r7} - cmp r2, r3 - ble 1b - - mov r8, #0 @ Zero it out - mov r7, #MACH_TYPE_L7200 @ Set architecture ID diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index c5191b1532e8..abf4d65acf62 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -170,9 +170,16 @@ not_angel: .text adr r0, LC0 - ARM( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp}) - THUMB( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip} ) + ARM( ldmia r0, {r1, r2, r3, r5, r6, r11, ip, sp}) + THUMB( ldmia r0, {r1, r2, r3, r5, r6, r11, ip} ) THUMB( ldr sp, [r0, #32] ) +#ifdef CONFIG_AUTO_ZRELADDR + @ determine final kernel image address + and r4, pc, #0xf8000000 + add r4, r4, #TEXT_OFFSET +#else + ldr r4, =CONFIG_ZRELADDR +#endif subs r0, r0, r1 @ calculate the delta offset @ if delta is zero, we are @@ -310,18 +317,17 @@ wont_overwrite: mov r0, r4 LC0: .word LC0 @ r1 .word __bss_start @ r2 .word _end @ r3 - .word zreladdr @ r4 .word _start @ r5 .word _image_size @ r6 .word _got_start @ r11 .word _got_end @ ip - .word user_stack+4096 @ sp + .word user_stack_end @ sp LC1: .word reloc_end - reloc_start .size LC0, . - LC0 #ifdef CONFIG_ARCH_RPC .globl params -params: ldr r0, =params_phys +params: ldr r0, =0x10000100 @ params_phys for RPC mov pc, lr .ltorg .align @@ -339,9 +345,8 @@ params: ldr r0, =params_phys * r4 = kernel execution address * r7 = architecture number * r8 = atags pointer - * r9 = run-time address of "start" (???) * On exit, - * r1, r2, r3, r9, r10, r12 corrupted + * r0, r1, r2, r3, r9, r10, r12 corrupted * This routine must preserve: * r4, r5, r6, r7, r8 */ @@ -396,12 +401,18 @@ __armv3_mpu_cache_on: mov r0, #0 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 + /* + * ?? ARMv3 MMU does not allow reading the control register, + * does this really work on ARMv3 MPU? + */ mrc p15, 0, r0, c1, c0, 0 @ read control reg @ .... .... .... WC.M orr r0, r0, #0x000d @ .... .... .... 11.1 + /* ?? this overwrites the value constructed above? */ mov r0, #0 mcr p15, 0, r0, c1, c0, 0 @ write control reg + /* ?? invalidate for the second time? */ mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 mov pc, lr @@ -771,8 +782,10 @@ proc_types: * Turn off the Cache and MMU. ARMv3 does not support * reading the control register, but ARMv4 does. * - * On exit, r0, r1, r2, r3, r9, r12 corrupted - * This routine must preserve: r4, r6, r7 + * On exit, + * r0, r1, r2, r3, r9, r12 corrupted + * This routine must preserve: + * r4, r6, r7 */ .align 5 cache_off: mov r3, #12 @ cache_off function @@ -845,7 +858,7 @@ __armv3_mmu_cache_off: * Clean and flush the cache to maintain consistency. * * On exit, - * r1, r2, r3, r9, r11, r12 corrupted + * r1, r2, r3, r9, r10, r11, r12 corrupted * This routine must preserve: * r0, r4, r5, r6, r7 */ @@ -988,7 +1001,7 @@ no_cache_id: __armv3_mmu_cache_flush: __armv3_mpu_cache_flush: mov r1, #0 - mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 + mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3 mov pc, lr /* @@ -1001,6 +1014,7 @@ __armv3_mpu_cache_flush: phexbuf: .space 12 .size phexbuf, . - phexbuf +@ phex corrupts {r0, r1, r2, r3} phex: adr r3, phexbuf mov r2, #0 strb r2, [r3, r1] @@ -1015,6 +1029,7 @@ phex: adr r3, phexbuf strb r2, [r3, r1] b 1b +@ puts corrupts {r0, r1, r2, r3} puts: loadsp r3, r1 1: ldrb r2, [r0], #1 teq r2, #0 @@ -1029,12 +1044,14 @@ puts: loadsp r3, r1 teq r0, #0 bne 1b mov pc, lr +@ putc corrupts {r0, r1, r2, r3} putc: mov r2, r0 mov r0, #0 loadsp r3, r1 b 2b +@ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr} memdump: mov r12, r0 mov r10, lr mov r11, #0 @@ -1070,3 +1087,4 @@ reloc_end: .align .section ".stack", "w" user_stack: .space 4096 +user_stack_end: diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index d2b2ef41cd4f..e653a6d3c8d9 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c @@ -28,9 +28,6 @@ unsigned int __machine_arch_type; #include <asm/unaligned.h> -#ifdef STANDALONE_DEBUG -#define putstr printf -#else static void putstr(const char *ptr); extern void error(char *x); @@ -116,7 +113,6 @@ static void putstr(const char *ptr) flush(); } -#endif void *memcpy(void *__dest, __const void *__src, size_t __n) { @@ -186,7 +182,6 @@ asmlinkage void __div0(void) extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)); -#ifndef STANDALONE_DEBUG unsigned long decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, @@ -211,18 +206,3 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, putstr(" done, booting the kernel.\n"); return output_ptr; } -#else - -char output_buffer[1500*1024]; - -int main() -{ - output_data = output_buffer; - - putstr("Uncompressing Linux..."); - decompress(input_data, input_data_end - input_data, - NULL, NULL, output_data, NULL, error); - putstr("done.\n"); - return 0; -} -#endif diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 337741f734ac..7dfa9a85bc0c 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -108,6 +108,51 @@ static void gic_unmask_irq(unsigned int irq) spin_unlock(&irq_controller_lock); } +static int gic_set_type(unsigned int irq, unsigned int type) +{ + void __iomem *base = gic_dist_base(irq); + unsigned int gicirq = gic_irq(irq); + u32 enablemask = 1 << (gicirq % 32); + u32 enableoff = (gicirq / 32) * 4; + u32 confmask = 0x2 << ((gicirq % 16) * 2); + u32 confoff = (gicirq / 16) * 4; + bool enabled = false; + u32 val; + + /* Interrupt configuration for SGIs can't be changed */ + if (gicirq < 16) + return -EINVAL; + + if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) + return -EINVAL; + + spin_lock(&irq_controller_lock); + + val = readl(base + GIC_DIST_CONFIG + confoff); + if (type == IRQ_TYPE_LEVEL_HIGH) + val &= ~confmask; + else if (type == IRQ_TYPE_EDGE_RISING) + val |= confmask; + + /* + * As recommended by the spec, disable the interrupt before changing + * the configuration + */ + if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { + writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); + enabled = true; + } + + writel(val, base + GIC_DIST_CONFIG + confoff); + + if (enabled) + writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); + + spin_unlock(&irq_controller_lock); + + return 0; +} + #ifdef CONFIG_SMP static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) { @@ -161,6 +206,7 @@ static struct irq_chip gic_chip = { .ack = gic_ack_irq, .mask = gic_mask_irq, .unmask = gic_unmask_irq, + .set_type = gic_set_type, #ifdef CONFIG_SMP .set_affinity = gic_set_cpu, #endif diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 6f80665f477e..517d50ddbeb3 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -185,13 +185,10 @@ static struct sa1111_dev_info sa1111_devices[] = { }, }; -void __init sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes) +void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes) { unsigned int sz = SZ_1M >> PAGE_SHIFT; - if (node != 0) - sz = 0; - size[1] = size[0] - sz; size[0] = sz; } @@ -1028,13 +1025,12 @@ static int sa1111_remove(struct platform_device *pdev) struct sa1111 *sachip = platform_get_drvdata(pdev); if (sachip) { - __sa1111_remove(sachip); - platform_set_drvdata(pdev, NULL); - #ifdef CONFIG_PM kfree(sachip->saved_state); sachip->saved_state = NULL; #endif + __sa1111_remove(sachip); + platform_set_drvdata(pdev, NULL); } return 0; diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index f2e3a9088df6..ccc9c9959b82 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -13,11 +13,19 @@ CONFIG_MACH_RD88F6192_NAS=y CONFIG_MACH_RD88F6281=y CONFIG_MACH_MV88F6281GTW_GE=y CONFIG_MACH_SHEEVAPLUG=y +CONFIG_MACH_ESATA_SHEEVAPLUG=y +CONFIG_MACH_GURUPLUG=y CONFIG_MACH_TS219=y CONFIG_MACH_TS41X=y CONFIG_MACH_OPENRD_BASE=y CONFIG_MACH_OPENRD_CLIENT=y +CONFIG_MACH_OPENRD_ULTIMATE=y CONFIG_MACH_NETSPACE_V2=y +CONFIG_MACH_INETSPACE_V2=y +CONFIG_MACH_NETSPACE_MAX_V2=y +CONFIG_MACH_NET2BIG_V2=y +CONFIG_MACH_NET5BIG_V2=y +CONFIG_MACH_T5325=y # CONFIG_CPU_FEROCEON_OLD_ID is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y diff --git a/arch/arm/configs/lusl7200_defconfig b/arch/arm/configs/lusl7200_defconfig deleted file mode 100644 index 816fc42884c9..000000000000 --- a/arch/arm/configs/lusl7200_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_HOTPLUG is not set -CONFIG_MODULES=y -CONFIG_ARCH_L7200=y -# CONFIG_ARM_THUMB is not set -CONFIG_ZBOOT_ROM_TEXT=0x00010000 -CONFIG_ZBOOT_ROM_BSS=0xf03e0000 -CONFIG_ZBOOT_ROM=y -CONFIG_CMDLINE="console=tty0 console=ttyLU1,115200 root=/dev/ram initrd=0xf1000000,0x005dac7b mem=32M" -CONFIG_BINFMT_AOUT=y -CONFIG_BLK_DEV_RAM=y -# CONFIG_INPUT is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_VT is not set -CONFIG_SERIAL_NONSTANDARD=y -CONFIG_EXT2_FS=y -CONFIG_DEBUG_USER=y -# CONFIG_CRC32 is not set diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index 51662feb9f1d..6750b8e45a49 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -121,4 +121,8 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); extern void elf_set_personality(const struct elf32_hdr *); #define SET_PERSONALITY(ex) elf_set_personality(&(ex)) +struct mm_struct; +extern unsigned long arch_randomize_brk(struct mm_struct *mm); +#define arch_randomize_brk arch_randomize_brk + #endif diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h index f7bd52b1c365..c1062c317103 100644 --- a/arch/arm/include/asm/hwcap.h +++ b/arch/arm/include/asm/hwcap.h @@ -19,6 +19,7 @@ #define HWCAP_NEON 4096 #define HWCAP_VFPv3 8192 #define HWCAP_VFPv3D16 16384 +#define HWCAP_TLS 32768 #if defined(__KERNEL__) && !defined(__ASSEMBLY__) /* diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index c980156f3263..1261b1f928d9 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -26,6 +26,7 @@ #include <linux/types.h> #include <asm/byteorder.h> #include <asm/memory.h> +#include <asm/system.h> /* * ISA I/O bus memory addresses are 1:1 with the physical address. @@ -179,25 +180,38 @@ extern void _memset_io(volatile void __iomem *, int, size_t); * IO port primitives for more information. */ #ifdef __mem_pci -#define readb(c) ({ __u8 __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ __u16 __v = le16_to_cpu((__force __le16) \ +#define readb_relaxed(c) ({ u8 __v = __raw_readb(__mem_pci(c)); __v; }) +#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16) \ __raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ __u32 __v = le32_to_cpu((__force __le32) \ +#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32) \ __raw_readl(__mem_pci(c))); __v; }) -#define readb_relaxed(addr) readb(addr) -#define readw_relaxed(addr) readw(addr) -#define readl_relaxed(addr) readl(addr) + +#define writeb_relaxed(v,c) ((void)__raw_writeb(v,__mem_pci(c))) +#define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \ + cpu_to_le16(v),__mem_pci(c))) +#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \ + cpu_to_le32(v),__mem_pci(c))) + +#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE +#define __iormb() rmb() +#define __iowmb() wmb() +#else +#define __iormb() do { } while (0) +#define __iowmb() do { } while (0) +#endif + +#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) +#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) +#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) + +#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); }) +#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) +#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) #define readsb(p,d,l) __raw_readsb(__mem_pci(p),d,l) #define readsw(p,d,l) __raw_readsw(__mem_pci(p),d,l) #define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l) -#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) -#define writew(v,c) __raw_writew((__force __u16) \ - cpu_to_le16(v),__mem_pci(c)) -#define writel(v,c) __raw_writel((__force __u32) \ - cpu_to_le32(v),__mem_pci(c)) - #define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l) #define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l) #define writesl(p,d,l) __raw_writesl(__mem_pci(p),d,l) @@ -244,13 +258,13 @@ extern void _memset_io(volatile void __iomem *, int, size_t); * io{read,write}{8,16,32} macros */ #ifndef ioread8 -#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; }) -#define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __v; }) -#define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __v; }) +#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __iormb(); __v; }) +#define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; }) +#define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; }) -#define iowrite8(v,p) __raw_writeb(v, p) -#define iowrite16(v,p) __raw_writew((__force __u16)cpu_to_le16(v), p) -#define iowrite32(v,p) __raw_writel((__force __u32)cpu_to_le32(v), p) +#define iowrite8(v,p) ({ __iowmb(); (void)__raw_writeb(v, p); }) +#define iowrite16(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_le16(v), p); }) +#define iowrite32(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_le32(v), p); }) #define ioread8_rep(p,d,c) __raw_readsb(p,d,c) #define ioread16_rep(p,d,c) __raw_readsw(p,d,c) diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h index 237282f7c762..2721a5814cb9 100644 --- a/arch/arm/include/asm/irq.h +++ b/arch/arm/include/asm/irq.h @@ -7,6 +7,8 @@ #define irq_canonicalize(i) (i) #endif +#define NR_IRQS_LEGACY 16 + /* * Use this value to indicate lack of interrupt * capability diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h index df15a0dc228e..8ec9ef5c3c7b 100644 --- a/arch/arm/include/asm/kexec.h +++ b/arch/arm/include/asm/kexec.h @@ -19,10 +19,26 @@ #ifndef __ASSEMBLY__ -struct kimage; -/* Provide a dummy definition to avoid build failures. */ +/** + * crash_setup_regs() - save registers for the panic kernel + * @newregs: registers are saved here + * @oldregs: registers to be saved (may be %NULL) + * + * Function copies machine registers from @oldregs to @newregs. If @oldregs is + * %NULL then current registers are stored there. + */ static inline void crash_setup_regs(struct pt_regs *newregs, - struct pt_regs *oldregs) { } + struct pt_regs *oldregs) +{ + if (oldregs) { + memcpy(newregs, oldregs, sizeof(*newregs)); + } else { + __asm__ __volatile__ ("stmia %0, {r0 - r15}" + : : "r" (&newregs->ARM_r0)); + __asm__ __volatile__ ("mrs %0, cpsr" + : "=r" (newregs->ARM_cpsr)); + } +} #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h index c59842dc7cb8..8a0dd18ba642 100644 --- a/arch/arm/include/asm/mach/arch.h +++ b/arch/arm/include/asm/mach/arch.h @@ -20,6 +20,7 @@ struct machine_desc { * by assembler code in head.S, head-common.S */ unsigned int nr; /* architecture number */ + unsigned int nr_irqs; /* number of IRQs */ unsigned int phys_io; /* start of physical io */ unsigned int io_pg_offst; /* byte offset for io * page tabe entry */ @@ -37,6 +38,7 @@ struct machine_desc { void (*fixup)(struct machine_desc *, struct tag *, char **, struct meminfo *); + void (*reserve)(void);/* reserve mem blocks */ void (*map_io)(void);/* IO mapping function */ void (*init_irq)(void); struct sys_timer *timer; /* system tick timer */ diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h index 8920b2d6e3b8..ce3eee9fe26c 100644 --- a/arch/arm/include/asm/mach/irq.h +++ b/arch/arm/include/asm/mach/irq.h @@ -17,6 +17,7 @@ struct seq_file; /* * This is internal. Do not use it. */ +extern unsigned int arch_nr_irqs; extern void (*init_arch_irq)(void); extern void init_FIQ(void); extern int show_fiq_list(struct seq_file *, void *); diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h index 742c2aaeb020..d2fedb5aeb1f 100644 --- a/arch/arm/include/asm/mach/map.h +++ b/arch/arm/include/asm/mach/map.h @@ -27,6 +27,8 @@ struct map_desc { #define MT_MEMORY 9 #define MT_ROM 10 #define MT_MEMORY_NONCACHED 11 +#define MT_MEMORY_DTCM 12 +#define MT_MEMORY_ITCM 13 #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index 52f0da1e97df..16330bd0657c 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -46,6 +46,7 @@ struct pci_sys_data { /* IRQ mapping */ int (*map_irq)(struct pci_dev *, u8, u8); struct hw_pci *hw; + void *private_data; /* platform controller private data */ }; /* diff --git a/arch/arm/include/asm/memblock.h b/arch/arm/include/asm/memblock.h new file mode 100644 index 000000000000..fdbc43b2e6c0 --- /dev/null +++ b/arch/arm/include/asm/memblock.h @@ -0,0 +1,16 @@ +#ifndef _ASM_ARM_MEMBLOCK_H +#define _ASM_ARM_MEMBLOCK_H + +#ifdef CONFIG_MMU +extern phys_addr_t lowmem_end_addr; +#define MEMBLOCK_REAL_LIMIT lowmem_end_addr +#else +#define MEMBLOCK_REAL_LIMIT 0 +#endif + +struct meminfo; +struct machine_desc; + +extern void arm_memblock_init(struct meminfo *, struct machine_desc *); + +#endif diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 4312ee5e3d0b..23c2e8e5c0fa 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -124,6 +124,15 @@ #endif /* !CONFIG_MMU */ /* + * We fix the TCM memories max 32 KiB ITCM resp DTCM at these + * locations + */ +#ifdef CONFIG_HAVE_TCM +#define ITCM_OFFSET UL(0xfffe0000) +#define DTCM_OFFSET UL(0xfffe8000) +#endif + +/* * Physical vs virtual RAM address space conversion. These are * private definitions which should NOT be used outside memory.h * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. @@ -158,7 +167,7 @@ #endif #ifndef arch_adjust_zones -#define arch_adjust_zones(node,size,holes) do { } while (0) +#define arch_adjust_zones(size,holes) do { } while (0) #elif !defined(CONFIG_ZONE_DMA) #error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA" #endif @@ -234,76 +243,11 @@ static inline __deprecated void *bus_to_virt(unsigned long x) * virt_to_page(k) convert a _valid_ virtual address to struct page * * virt_addr_valid(k) indicates whether a virtual address is valid */ -#ifndef CONFIG_DISCONTIGMEM - #define ARCH_PFN_OFFSET PHYS_PFN_OFFSET #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) #define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory) -#define PHYS_TO_NID(addr) (0) - -#else /* CONFIG_DISCONTIGMEM */ - -/* - * This is more complex. We have a set of mem_map arrays spread - * around in memory. - */ -#include <linux/numa.h> - -#define arch_pfn_to_nid(pfn) PFN_TO_NID(pfn) -#define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT) - -#define virt_to_page(kaddr) \ - (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) - -#define virt_addr_valid(kaddr) (KVADDR_TO_NID(kaddr) < MAX_NUMNODES) - -/* - * Common discontigmem stuff. - * PHYS_TO_NID is used by the ARM kernel/setup.c - */ -#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) - -/* - * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory - * and returns the mem_map of that node. - */ -#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr)) - -/* - * Given a page frame number, find the owning node of the memory - * and returns the mem_map of that node. - */ -#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) - -#ifdef NODE_MEM_SIZE_BITS -#define NODE_MEM_SIZE_MASK ((1 << NODE_MEM_SIZE_BITS) - 1) - -/* - * Given a kernel address, find the home node of the underlying memory. - */ -#define KVADDR_TO_NID(addr) \ - (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS) - -/* - * Given a page frame number, convert it to a node id. - */ -#define PFN_TO_NID(pfn) \ - (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT)) - -/* - * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory - * and returns the index corresponding to the appropriate page in the - * node's mem_map. - */ -#define LOCAL_MAP_NR(addr) \ - (((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT) - -#endif /* NODE_MEM_SIZE_BITS */ - -#endif /* !CONFIG_DISCONTIGMEM */ - /* * Optional coherency support. Currently used only by selected * Intel XSC3-based systems. diff --git a/arch/arm/include/asm/mmzone.h b/arch/arm/include/asm/mmzone.h deleted file mode 100644 index ae63a4fd28c8..000000000000 --- a/arch/arm/include/asm/mmzone.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * arch/arm/include/asm/mmzone.h - * - * 1999-12-29 Nicolas Pitre Created - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_MMZONE_H -#define __ASM_MMZONE_H - -/* - * Currently defined in arch/arm/mm/discontig.c - */ -extern pg_data_t discontig_node_data[]; - -/* - * Return a pointer to the node data for node n. - */ -#define NODE_DATA(nid) (&discontig_node_data[nid]) - -/* - * NODE_MEM_MAP gives the kaddr for the mem_map of the node. - */ -#define NODE_MEM_MAP(nid) (NODE_DATA(nid)->node_mem_map) - -#include <mach/memory.h> - -#endif diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 9dcb11e59026..c974be8913a7 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -184,6 +184,42 @@ extern unsigned long profile_pc(struct pt_regs *regs); #define predicate(x) ((x) & 0xf0000000) #define PREDICATE_ALWAYS 0xe0000000 +/* + * kprobe-based event tracer support + */ +#include <linux/stddef.h> +#include <linux/types.h> +#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0)) + +extern int regs_query_register_offset(const char *name); +extern const char *regs_query_register_name(unsigned int offset); +extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr); +extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, + unsigned int n); + +/** + * regs_get_register() - get register value from its offset + * @regs: pt_regs from which register value is gotten + * @offset: offset number of the register. + * + * regs_get_register returns the value of a register whose offset from @regs. + * The @offset is the offset of the register in struct pt_regs. + * If @offset is bigger than MAX_REG_OFFSET, this returns 0. + */ +static inline unsigned long regs_get_register(struct pt_regs *regs, + unsigned int offset) +{ + if (unlikely(offset > MAX_REG_OFFSET)) + return 0; + return *(unsigned long *)((unsigned long)regs + offset); +} + +/* Valid only for Kernel mode traps. */ +static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) +{ + return regs->ARM_sp; +} + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index f392fb4437af..f1e5a9bca249 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -201,8 +201,7 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn } struct membank { unsigned long start; unsigned long size; - unsigned short node; - unsigned short highmem; + unsigned int highmem; }; struct meminfo { @@ -212,9 +211,8 @@ struct meminfo { extern struct meminfo meminfo; -#define for_each_nodebank(iter,mi,no) \ - for (iter = 0; iter < (mi)->nr_banks; iter++) \ - if ((mi)->bank[iter].node == no) +#define for_each_bank(iter,mi) \ + for (iter = 0; iter < (mi)->nr_banks; iter++) #define bank_pfn_start(bank) __phys_to_pfn((bank)->start) #define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size) diff --git a/arch/arm/include/asm/stackprotector.h b/arch/arm/include/asm/stackprotector.h new file mode 100644 index 000000000000..de003327be97 --- /dev/null +++ b/arch/arm/include/asm/stackprotector.h @@ -0,0 +1,38 @@ +/* + * GCC stack protector support. + * + * Stack protector works by putting predefined pattern at the start of + * the stack frame and verifying that it hasn't been overwritten when + * returning from the function. The pattern is called stack canary + * and gcc expects it to be defined by a global variable called + * "__stack_chk_guard" on ARM. This unfortunately means that on SMP + * we cannot have a different canary value per task. + */ + +#ifndef _ASM_STACKPROTECTOR_H +#define _ASM_STACKPROTECTOR_H 1 + +#include <linux/random.h> +#include <linux/version.h> + +extern unsigned long __stack_chk_guard; + +/* + * Initialize the stackprotector canary value. + * + * NOTE: this must only be called from functions that never return, + * and it must always be inlined. + */ +static __always_inline void boot_init_stack_canary(void) +{ + unsigned long canary; + + /* Try to get a semi random initial value. */ + get_random_bytes(&canary, sizeof(canary)); + canary ^= LINUX_VERSION_CODE; + + current->stack_canary = canary; + __stack_chk_guard = current->stack_canary; +} + +#endif /* _ASM_STACKPROTECTOR_H */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 5f4f48002734..8ba1ccf82a02 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -83,7 +83,7 @@ void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info, void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *), - int sig, const char *name); + int sig, int code, const char *name); #define xchg(ptr,x) \ ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h new file mode 100644 index 000000000000..e71d6ff8d104 --- /dev/null +++ b/arch/arm/include/asm/tls.h @@ -0,0 +1,46 @@ +#ifndef __ASMARM_TLS_H +#define __ASMARM_TLS_H + +#ifdef __ASSEMBLY__ + .macro set_tls_none, tp, tmp1, tmp2 + .endm + + .macro set_tls_v6k, tp, tmp1, tmp2 + mcr p15, 0, \tp, c13, c0, 3 @ set TLS register + .endm + + .macro set_tls_v6, tp, tmp1, tmp2 + ldr \tmp1, =elf_hwcap + ldr \tmp1, [\tmp1, #0] + mov \tmp2, #0xffff0fff + tst \tmp1, #HWCAP_TLS @ hardware TLS available? + mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register + streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0 + .endm + + .macro set_tls_software, tp, tmp1, tmp2 + mov \tmp1, #0xffff0fff + str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0 + .endm +#endif + +#ifdef CONFIG_TLS_REG_EMUL +#define tls_emu 1 +#define has_tls_reg 1 +#define set_tls set_tls_none +#elif __LINUX_ARM_ARCH__ >= 7 || \ + (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K)) +#define tls_emu 0 +#define has_tls_reg 1 +#define set_tls set_tls_v6k +#elif __LINUX_ARM_ARCH__ == 6 +#define tls_emu 0 +#define has_tls_reg (elf_hwcap & HWCAP_TLS) +#define set_tls set_tls_v6 +#else +#define tls_emu 0 +#define has_tls_reg 0 +#define set_tls set_tls_software +#endif + +#endif /* __ASMARM_TLS_H */ diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h index 422f3cc204a2..3d5fc41ae8d3 100644 --- a/arch/arm/include/asm/vfpmacros.h +++ b/arch/arm/include/asm/vfpmacros.h @@ -3,6 +3,8 @@ * * Assembler-only file containing VFP macros and register definitions. */ +#include <asm/hwcap.h> + #include "vfp.h" @ Macros to allow building with old toolkits (with no VFP support) @@ -22,12 +24,20 @@ LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15} #endif #ifdef CONFIG_VFPv3 +#if __LINUX_ARM_ARCH__ <= 6 + ldr \tmp, =elf_hwcap @ may not have MVFR regs + ldr \tmp, [\tmp, #0] + tst \tmp, #HWCAP_VFPv3D16 + ldceq p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} + addne \base, \base, #32*4 @ step over unused register space +#else VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field cmp \tmp, #2 @ 32 x 64bit registers? ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} addne \base, \base, #32*4 @ step over unused register space #endif +#endif .endm @ write all the working registers out of the VFP @@ -38,10 +48,18 @@ STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15} #endif #ifdef CONFIG_VFPv3 +#if __LINUX_ARM_ARCH__ <= 6 + ldr \tmp, =elf_hwcap @ may not have MVFR regs + ldr \tmp, [\tmp, #0] + tst \tmp, #HWCAP_VFPv3D16 + stceq p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} + addne \base, \base, #32*4 @ step over unused register space +#else VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field cmp \tmp, #2 @ 32 x 64bit registers? stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} addne \base, \base, #32*4 @ step over unused register space #endif +#endif .endm diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 26d302c28e13..980b78e31328 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -13,10 +13,12 @@ CFLAGS_REMOVE_return_address.o = -pg # Object file lists. -obj-y := compat.o elf.o entry-armv.o entry-common.o irq.o \ +obj-y := elf.o entry-armv.o entry-common.o irq.o \ process.o ptrace.o return_address.o setup.o signal.o \ sys_arm.o stacktrace.o time.o traps.o +obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o + obj-$(CONFIG_LEDS) += leds.o obj-$(CONFIG_OC_ETM) += etm.o @@ -39,6 +41,7 @@ obj-$(CONFIG_ARM_THUMBEE) += thumbee.o obj-$(CONFIG_KGDB) += kgdb.o obj-$(CONFIG_ARM_UNWIND) += unwind.o obj-$(CONFIG_HAVE_TCM) += tcm.o +obj-$(CONFIG_CRASH_DUMP) += crash_dump.o obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index 883511522fca..85f2a019f77b 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c @@ -40,6 +40,9 @@ int main(void) { DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm)); +#ifdef CONFIG_CC_STACKPROTECTOR + DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary)); +#endif BLANK(); DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); diff --git a/arch/arm/kernel/compat.c b/arch/arm/kernel/compat.c index 0a1385442f43..925652318b8b 100644 --- a/arch/arm/kernel/compat.c +++ b/arch/arm/kernel/compat.c @@ -217,10 +217,3 @@ void __init convert_to_tag_list(struct tag *tags) struct param_struct *params = (struct param_struct *)tags; build_tag_list(params, ¶ms->u2); } - -void __init squash_mem_tags(struct tag *tag) -{ - for (; tag->hdr.size; tag = tag_next(tag)) - if (tag->hdr.tag == ATAG_MEM) - tag->hdr.tag = ATAG_NONE; -} diff --git a/arch/arm/kernel/compat.h b/arch/arm/kernel/compat.h index 27e61a68bd1c..39264ab1b9c6 100644 --- a/arch/arm/kernel/compat.h +++ b/arch/arm/kernel/compat.h @@ -9,5 +9,3 @@ */ extern void convert_to_tag_list(struct tag *tags); - -extern void squash_mem_tags(struct tag *tag); diff --git a/arch/arm/kernel/crash_dump.c b/arch/arm/kernel/crash_dump.c new file mode 100644 index 000000000000..cd3b853a8a6d --- /dev/null +++ b/arch/arm/kernel/crash_dump.c @@ -0,0 +1,60 @@ +/* + * arch/arm/kernel/crash_dump.c + * + * Copyright (C) 2010 Nokia Corporation. + * Author: Mika Westerberg + * + * This code is taken from arch/x86/kernel/crash_dump_64.c + * Created by: Hariprasad Nellitheertha (hari@in.ibm.com) + * Copyright (C) IBM Corporation, 2004. All rights reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/errno.h> +#include <linux/crash_dump.h> +#include <linux/uaccess.h> +#include <linux/io.h> + +/* stores the physical address of elf header of crash image */ +unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX; + +/** + * copy_oldmem_page() - copy one page from old kernel memory + * @pfn: page frame number to be copied + * @buf: buffer where the copied page is placed + * @csize: number of bytes to copy + * @offset: offset in bytes into the page + * @userbuf: if set, @buf is int he user address space + * + * This function copies one page from old kernel memory into buffer pointed by + * @buf. If @buf is in userspace, set @userbuf to %1. Returns number of bytes + * copied or negative error in case of failure. + */ +ssize_t copy_oldmem_page(unsigned long pfn, char *buf, + size_t csize, unsigned long offset, + int userbuf) +{ + void *vaddr; + + if (!csize) + return 0; + + vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE); + if (!vaddr) + return -ENOMEM; + + if (userbuf) { + if (copy_to_user(buf, vaddr + offset, csize)) { + iounmap(vaddr); + return -EFAULT; + } + } else { + memcpy(buf, vaddr + offset, csize); + } + + iounmap(vaddr); + return csize; +} diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 3fd7861de4d1..bb8e93a76407 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -22,6 +22,7 @@ #include <asm/thread_notify.h> #include <asm/unwind.h> #include <asm/unistd.h> +#include <asm/tls.h> #include "entry-header.S" @@ -735,11 +736,11 @@ ENTRY(__switch_to) #ifdef CONFIG_MMU ldr r6, [r2, #TI_CPU_DOMAIN] #endif -#if defined(CONFIG_HAS_TLS_REG) - mcr p15, 0, r3, c13, c0, 3 @ set TLS register -#elif !defined(CONFIG_TLS_REG_EMUL) - mov r4, #0xffff0fff - str r3, [r4, #-15] @ TLS val at 0xffff0ff0 + set_tls r3, r4, r5 +#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) + ldr r7, [r2, #TI_TASK] + ldr r8, =__stack_chk_guard + ldr r7, [r7, #TSK_STACK_CANARY] #endif #ifdef CONFIG_MMU mcr p15, 0, r6, c3, c0, 0 @ Set domain register @@ -749,6 +750,9 @@ ENTRY(__switch_to) ldr r0, =thread_notify_head mov r1, #THREAD_NOTIFY_SWITCH bl atomic_notifier_call_chain +#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) + str r7, [r8] +#endif THUMB( mov ip, r4 ) mov r0, r5 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously @@ -1005,17 +1009,12 @@ kuser_cmpxchg_fixup: */ __kuser_get_tls: @ 0xffff0fe0 - -#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) - ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 -#else - mrc p15, 0, r0, c13, c0, 3 @ read TLS register -#endif + ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init usr_ret lr - - .rep 5 - .word 0 @ pad up to __kuser_helper_version - .endr + mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code + .rep 4 + .word 0 @ 0xffff0ff0 software TLS value, then + .endr @ pad up to __kuser_helper_version /* * Reference declaration: diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 3b3d2c80509c..c0d5c3b3a760 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -47,12 +47,14 @@ #define irq_finish(irq) do { } while (0) #endif +unsigned int arch_nr_irqs; void (*init_arch_irq)(void) __initdata = NULL; unsigned long irq_err_count; int show_interrupts(struct seq_file *p, void *v) { int i = *(loff_t *) v, cpu; + struct irq_desc *desc; struct irqaction * action; unsigned long flags; @@ -67,24 +69,25 @@ int show_interrupts(struct seq_file *p, void *v) seq_putc(p, '\n'); } - if (i < NR_IRQS) { - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; + if (i < nr_irqs) { + desc = irq_to_desc(i); + raw_spin_lock_irqsave(&desc->lock, flags); + action = desc->action; if (!action) goto unlock; seq_printf(p, "%3d: ", i); for_each_present_cpu(cpu) seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); - seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-"); + seq_printf(p, " %10s", desc->chip->name ? : "-"); seq_printf(p, " %s", action->name); for (action = action->next; action; action = action->next) seq_printf(p, ", %s", action->name); seq_putc(p, '\n'); unlock: - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); - } else if (i == NR_IRQS) { + raw_spin_unlock_irqrestore(&desc->lock, flags); + } else if (i == nr_irqs) { #ifdef CONFIG_FIQ show_fiq_list(p, v); #endif @@ -112,7 +115,7 @@ asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs) * Some hardware gives randomly wrong interrupts. Rather * than crashing, do something sensible. */ - if (unlikely(irq >= NR_IRQS)) { + if (unlikely(irq >= nr_irqs)) { if (printk_ratelimit()) printk(KERN_WARNING "Bad IRQ%u\n", irq); ack_bad_irq(irq); @@ -132,12 +135,12 @@ void set_irq_flags(unsigned int irq, unsigned int iflags) struct irq_desc *desc; unsigned long flags; - if (irq >= NR_IRQS) { + if (irq >= nr_irqs) { printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq); return; } - desc = irq_desc + irq; + desc = irq_to_desc(irq); raw_spin_lock_irqsave(&desc->lock, flags); desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; if (iflags & IRQF_VALID) @@ -151,14 +154,25 @@ void set_irq_flags(unsigned int irq, unsigned int iflags) void __init init_IRQ(void) { + struct irq_desc *desc; int irq; - for (irq = 0; irq < NR_IRQS; irq++) - irq_desc[irq].status |= IRQ_NOREQUEST | IRQ_NOPROBE; + for (irq = 0; irq < nr_irqs; irq++) { + desc = irq_to_desc_alloc_node(irq, 0); + desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; + } init_arch_irq(); } +#ifdef CONFIG_SPARSE_IRQ +int __init arch_probe_nr_irqs(void) +{ + nr_irqs = arch_nr_irqs ? arch_nr_irqs : NR_IRQS; + return 0; +} +#endif + #ifdef CONFIG_HOTPLUG_CPU static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu) @@ -178,10 +192,9 @@ static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu) void migrate_irqs(void) { unsigned int i, cpu = smp_processor_id(); + struct irq_desc *desc; - for (i = 0; i < NR_IRQS; i++) { - struct irq_desc *desc = irq_desc + i; - + for_each_irq_desc(i, desc) { if (desc->node == cpu) { unsigned int newcpu = cpumask_any_and(desc->affinity, cpu_online_mask); diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c index 598ca61e7bca..1fc74cbd1a19 100644 --- a/arch/arm/kernel/machine_kexec.c +++ b/arch/arm/kernel/machine_kexec.c @@ -37,12 +37,12 @@ void machine_kexec_cleanup(struct kimage *image) { } -void machine_shutdown(void) -{ -} - void machine_crash_shutdown(struct pt_regs *regs) { + local_irq_disable(); + crash_save_cpu(regs, smp_processor_id()); + + printk(KERN_INFO "Loading crashdump kernel...\n"); } void machine_kexec(struct kimage *image) @@ -74,7 +74,11 @@ void machine_kexec(struct kimage *image) (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE); printk(KERN_INFO "Bye!\n"); - cpu_proc_fin(); + local_irq_disable(); + local_fiq_disable(); setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/ + flush_cache_all(); + cpu_proc_fin(); + flush_cache_all(); cpu_reset(reboot_code_buffer_phys); } diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index a4a9cc88bec7..401e38be1f78 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -28,7 +28,9 @@ #include <linux/tick.h> #include <linux/utsname.h> #include <linux/uaccess.h> +#include <linux/random.h> +#include <asm/cacheflush.h> #include <asm/leds.h> #include <asm/processor.h> #include <asm/system.h> @@ -36,6 +38,12 @@ #include <asm/stacktrace.h> #include <asm/mach/time.h> +#ifdef CONFIG_CC_STACKPROTECTOR +#include <linux/stackprotector.h> +unsigned long __stack_chk_guard __read_mostly; +EXPORT_SYMBOL(__stack_chk_guard); +#endif + static const char *processor_modes[] = { "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" , "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26", @@ -84,10 +92,9 @@ __setup("hlt", hlt_setup); void arm_machine_restart(char mode, const char *cmd) { - /* - * Clean and disable cache, and turn off interrupts - */ - cpu_proc_fin(); + /* Disable interrupts first */ + local_irq_disable(); + local_fiq_disable(); /* * Tell the mm system that we are going to reboot - @@ -96,6 +103,15 @@ void arm_machine_restart(char mode, const char *cmd) */ setup_mm_for_reboot(mode); + /* Clean and invalidate caches */ + flush_cache_all(); + + /* Turn off caching */ + cpu_proc_fin(); + + /* Push out any further dirty data, and ensure cache is empty */ + flush_cache_all(); + /* * Now call the architecture specific reboot code. */ @@ -189,19 +205,29 @@ int __init reboot_setup(char *str) __setup("reboot=", reboot_setup); -void machine_halt(void) +void machine_shutdown(void) { +#ifdef CONFIG_SMP + smp_send_stop(); +#endif } +void machine_halt(void) +{ + machine_shutdown(); + while (1); +} void machine_power_off(void) { + machine_shutdown(); if (pm_power_off) pm_power_off(); } void machine_restart(char *cmd) { + machine_shutdown(); arm_pm_restart(reboot_mode, cmd); } @@ -426,3 +452,9 @@ unsigned long get_wchan(struct task_struct *p) } while (count ++ < 16); return 0; } + +unsigned long arch_randomize_brk(struct mm_struct *mm) +{ + unsigned long range_end = mm->brk + 0x02000000; + return randomize_range(mm->brk, range_end, 0) ? : mm->brk; +} diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 3f562a7c0a99..f99d489822d5 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -52,6 +52,102 @@ #define BREAKINST_THUMB 0xde01 #endif +struct pt_regs_offset { + const char *name; + int offset; +}; + +#define REG_OFFSET_NAME(r) \ + {.name = #r, .offset = offsetof(struct pt_regs, ARM_##r)} +#define REG_OFFSET_END {.name = NULL, .offset = 0} + +static const struct pt_regs_offset regoffset_table[] = { + REG_OFFSET_NAME(r0), + REG_OFFSET_NAME(r1), + REG_OFFSET_NAME(r2), + REG_OFFSET_NAME(r3), + REG_OFFSET_NAME(r4), + REG_OFFSET_NAME(r5), + REG_OFFSET_NAME(r6), + REG_OFFSET_NAME(r7), + REG_OFFSET_NAME(r8), + REG_OFFSET_NAME(r9), + REG_OFFSET_NAME(r10), + REG_OFFSET_NAME(fp), + REG_OFFSET_NAME(ip), + REG_OFFSET_NAME(sp), + REG_OFFSET_NAME(lr), + REG_OFFSET_NAME(pc), + REG_OFFSET_NAME(cpsr), + REG_OFFSET_NAME(ORIG_r0), + REG_OFFSET_END, +}; + +/** + * regs_query_register_offset() - query register offset from its name + * @name: the name of a register + * + * regs_query_register_offset() returns the offset of a register in struct + * pt_regs from its name. If the name is invalid, this returns -EINVAL; + */ +int regs_query_register_offset(const char *name) +{ + const struct pt_regs_offset *roff; + for (roff = regoffset_table; roff->name != NULL; roff++) + if (!strcmp(roff->name, name)) + return roff->offset; + return -EINVAL; +} + +/** + * regs_query_register_name() - query register name from its offset + * @offset: the offset of a register in struct pt_regs. + * + * regs_query_register_name() returns the name of a register from its + * offset in struct pt_regs. If the @offset is invalid, this returns NULL; + */ +const char *regs_query_register_name(unsigned int offset) +{ + const struct pt_regs_offset *roff; + for (roff = regoffset_table; roff->name != NULL; roff++) + if (roff->offset == offset) + return roff->name; + return NULL; +} + +/** + * regs_within_kernel_stack() - check the address in the stack + * @regs: pt_regs which contains kernel stack pointer. + * @addr: address which is checked. + * + * regs_within_kernel_stack() checks @addr is within the kernel stack page(s). + * If @addr is within the kernel stack, it returns true. If not, returns false. + */ +bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr) +{ + return ((addr & ~(THREAD_SIZE - 1)) == + (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))); +} + +/** + * regs_get_kernel_stack_nth() - get Nth entry of the stack + * @regs: pt_regs which contains kernel stack pointer. + * @n: stack entry number. + * + * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which + * is specified by @regs. If the @n th entry is NOT in the kernel stack, + * this returns 0. + */ +unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n) +{ + unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); + addr += n; + if (regs_within_kernel_stack(regs, (unsigned long)addr)) + return *addr; + else + return 0; +} + /* * this routine will get a word off of the processes privileged stack. * the offset is how far from the base addr as stored in the THREAD. diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S index 61930eb09029..fd26f8d65151 100644 --- a/arch/arm/kernel/relocate_kernel.S +++ b/arch/arm/kernel/relocate_kernel.S @@ -10,6 +10,12 @@ relocate_new_kernel: ldr r0,kexec_indirection_page ldr r1,kexec_start_address + /* + * If there is no indirection page (we are doing crashdumps) + * skip any relocation. + */ + cmp r0, #0 + beq 2f 0: /* top, read another word for the indirection page */ ldr r3, [r0],#4 diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 122d999bdc7c..d5231ae7355a 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -19,12 +19,15 @@ #include <linux/seq_file.h> #include <linux/screen_info.h> #include <linux/init.h> +#include <linux/kexec.h> +#include <linux/crash_dump.h> #include <linux/root_dev.h> #include <linux/cpu.h> #include <linux/interrupt.h> #include <linux/smp.h> #include <linux/fs.h> #include <linux/proc_fs.h> +#include <linux/memblock.h> #include <asm/unified.h> #include <asm/cpu.h> @@ -44,7 +47,9 @@ #include <asm/traps.h> #include <asm/unwind.h> +#if defined(CONFIG_DEPRECATED_PARAM_STRUCT) #include "compat.h" +#endif #include "atags.h" #include "tcm.h" @@ -269,6 +274,21 @@ static void __init cacheid_init(void) extern struct proc_info_list *lookup_processor_type(unsigned int); extern struct machine_desc *lookup_machine_type(unsigned int); +static void __init feat_v6_fixup(void) +{ + int id = read_cpuid_id(); + + if ((id & 0xff0f0000) != 0x41070000) + return; + + /* + * HWCAP_TLS is available only on 1136 r1p0 and later, + * see also kuser_get_tls_init. + */ + if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0)) + elf_hwcap &= ~HWCAP_TLS; +} + static void __init setup_processor(void) { struct proc_info_list *list; @@ -311,6 +331,8 @@ static void __init setup_processor(void) elf_hwcap &= ~HWCAP_THUMB; #endif + feat_v6_fixup(); + cacheid_init(); cpu_proc_init(); } @@ -402,13 +424,12 @@ static int __init arm_add_memory(unsigned long start, unsigned long size) size -= start & ~PAGE_MASK; bank->start = PAGE_ALIGN(start); bank->size = size & PAGE_MASK; - bank->node = PHYS_TO_NID(start); /* * Check whether this memory region has non-zero size or * invalid node number. */ - if (bank->size == 0 || bank->node >= MAX_NUMNODES) + if (bank->size == 0) return -EINVAL; meminfo.nr_banks++; @@ -663,6 +684,86 @@ static int __init customize_machine(void) } arch_initcall(customize_machine); +#ifdef CONFIG_KEXEC +static inline unsigned long long get_total_mem(void) +{ + unsigned long total; + + total = max_low_pfn - min_low_pfn; + return total << PAGE_SHIFT; +} + +/** + * reserve_crashkernel() - reserves memory are for crash kernel + * + * This function reserves memory area given in "crashkernel=" kernel command + * line parameter. The memory reserved is used by a dump capture kernel when + * primary kernel is crashing. + */ +static void __init reserve_crashkernel(void) +{ + unsigned long long crash_size, crash_base; + unsigned long long total_mem; + int ret; + + total_mem = get_total_mem(); + ret = parse_crashkernel(boot_command_line, total_mem, + &crash_size, &crash_base); + if (ret) + return; + + ret = reserve_bootmem(crash_base, crash_size, BOOTMEM_EXCLUSIVE); + if (ret < 0) { + printk(KERN_WARNING "crashkernel reservation failed - " + "memory is in use (0x%lx)\n", (unsigned long)crash_base); + return; + } + + printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " + "for crashkernel (System RAM: %ldMB)\n", + (unsigned long)(crash_size >> 20), + (unsigned long)(crash_base >> 20), + (unsigned long)(total_mem >> 20)); + + crashk_res.start = crash_base; + crashk_res.end = crash_base + crash_size - 1; + insert_resource(&iomem_resource, &crashk_res); +} +#else +static inline void reserve_crashkernel(void) {} +#endif /* CONFIG_KEXEC */ + +/* + * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by + * is_kdump_kernel() to determine if we are booting after a panic. Hence + * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE. + */ + +#ifdef CONFIG_CRASH_DUMP +/* + * elfcorehdr= specifies the location of elf core header stored by the crashed + * kernel. This option will be passed by kexec loader to the capture kernel. + */ +static int __init setup_elfcorehdr(char *arg) +{ + char *end; + + if (!arg) + return -EINVAL; + + elfcorehdr_addr = memparse(arg, &end); + return end > arg ? 0 : -EINVAL; +} +early_param("elfcorehdr", setup_elfcorehdr); +#endif /* CONFIG_CRASH_DUMP */ + +static void __init squash_mem_tags(struct tag *tag) +{ + for (; tag->hdr.size; tag = tag_next(tag)) + if (tag->hdr.tag == ATAG_MEM) + tag->hdr.tag = ATAG_NONE; +} + void __init setup_arch(char **cmdline_p) { struct tag *tags = (struct tag *)&init_tags; @@ -683,12 +784,14 @@ void __init setup_arch(char **cmdline_p) else if (mdesc->boot_params) tags = phys_to_virt(mdesc->boot_params); +#if defined(CONFIG_DEPRECATED_PARAM_STRUCT) /* * If we have the old style parameters, convert them to * a tag list. */ if (tags->hdr.tag != ATAG_CORE) convert_to_tag_list(tags); +#endif if (tags->hdr.tag != ATAG_CORE) tags = (struct tag *)&init_tags; @@ -716,12 +819,15 @@ void __init setup_arch(char **cmdline_p) parse_early_param(); + arm_memblock_init(&meminfo, mdesc); + paging_init(mdesc); request_standard_resources(&meminfo, mdesc); #ifdef CONFIG_SMP smp_init_cpus(); #endif + reserve_crashkernel(); cpu_init(); tcm_init(); @@ -729,6 +835,7 @@ void __init setup_arch(char **cmdline_p) /* * Set up various architecture-specific pointers */ + arch_nr_irqs = mdesc->nr_irqs; init_arch_irq = mdesc->init_irq; system_timer = mdesc->timer; init_machine = mdesc->init_machine; diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index b8c3d0f689d9..40dc74f2b27f 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -429,7 +429,11 @@ static void smp_timer_broadcast(const struct cpumask *mask) { send_ipi_message(mask, IPI_TIMER); } +#else +#define smp_timer_broadcast NULL +#endif +#ifndef CONFIG_LOCAL_TIMERS static void broadcast_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { @@ -444,7 +448,6 @@ static void local_timer_setup(struct clock_event_device *evt) evt->rating = 400; evt->mult = 1; evt->set_mode = broadcast_timer_set_mode; - evt->broadcast = smp_timer_broadcast; clockevents_register_device(evt); } @@ -456,6 +459,7 @@ void __cpuinit percpu_timer_setup(void) struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu); evt->cpumask = cpumask_of(cpu); + evt->broadcast = smp_timer_broadcast; local_timer_setup(evt); } @@ -467,10 +471,13 @@ static DEFINE_SPINLOCK(stop_lock); */ static void ipi_cpu_stop(unsigned int cpu) { - spin_lock(&stop_lock); - printk(KERN_CRIT "CPU%u: stopping\n", cpu); - dump_stack(); - spin_unlock(&stop_lock); + if (system_state == SYSTEM_BOOTING || + system_state == SYSTEM_RUNNING) { + spin_lock(&stop_lock); + printk(KERN_CRIT "CPU%u: stopping\n", cpu); + dump_stack(); + spin_unlock(&stop_lock); + } set_cpu_online(cpu, false); diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 7c5f0c024db7..35882fbf37f9 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -132,7 +132,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) twd_calibrate_rate(); clk->name = "local_timer"; - clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_C3STOP; clk->rating = 350; clk->set_mode = twd_set_mode; clk->set_next_event = twd_set_next_event; diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c index e50303868f1b..26685c2f7a49 100644 --- a/arch/arm/kernel/tcm.c +++ b/arch/arm/kernel/tcm.c @@ -13,38 +13,35 @@ #include <linux/ioport.h> #include <linux/genalloc.h> #include <linux/string.h> /* memcpy */ -#include <asm/page.h> /* PAGE_SHIFT */ #include <asm/cputype.h> #include <asm/mach/map.h> #include <mach/memory.h> #include "tcm.h" -/* Scream and warn about misuse */ -#if !defined(ITCM_OFFSET) || !defined(ITCM_END) || \ - !defined(DTCM_OFFSET) || !defined(DTCM_END) -#error "TCM support selected but offsets not defined!" -#endif - static struct gen_pool *tcm_pool; /* TCM section definitions from the linker */ extern char __itcm_start, __sitcm_text, __eitcm_text; extern char __dtcm_start, __sdtcm_data, __edtcm_data; +/* These will be increased as we run */ +u32 dtcm_end = DTCM_OFFSET; +u32 itcm_end = ITCM_OFFSET; + /* * TCM memory resources */ static struct resource dtcm_res = { .name = "DTCM RAM", .start = DTCM_OFFSET, - .end = DTCM_END, + .end = DTCM_OFFSET, .flags = IORESOURCE_MEM }; static struct resource itcm_res = { .name = "ITCM RAM", .start = ITCM_OFFSET, - .end = ITCM_END, + .end = ITCM_OFFSET, .flags = IORESOURCE_MEM }; @@ -52,8 +49,8 @@ static struct map_desc dtcm_iomap[] __initdata = { { .virtual = DTCM_OFFSET, .pfn = __phys_to_pfn(DTCM_OFFSET), - .length = (DTCM_END - DTCM_OFFSET + 1), - .type = MT_UNCACHED + .length = 0, + .type = MT_MEMORY_DTCM } }; @@ -61,8 +58,8 @@ static struct map_desc itcm_iomap[] __initdata = { { .virtual = ITCM_OFFSET, .pfn = __phys_to_pfn(ITCM_OFFSET), - .length = (ITCM_END - ITCM_OFFSET + 1), - .type = MT_UNCACHED + .length = 0, + .type = MT_MEMORY_ITCM } }; @@ -93,14 +90,24 @@ void tcm_free(void *addr, size_t len) } EXPORT_SYMBOL(tcm_free); - -static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size) +static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks, + u32 *offset) { const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128, 256, 512, 1024, -1, -1, -1, -1 }; u32 tcm_region; int tcm_size; + /* + * If there are more than one TCM bank of this type, + * select the TCM bank to operate on in the TCM selection + * register. + */ + if (banks > 1) + asm("mcr p15, 0, %0, c9, c2, 0" + : /* No output operands */ + : "r" (bank)); + /* Read the special TCM region register c9, 0 */ if (!type) asm("mrc p15, 0, %0, c9, c1, 0" @@ -111,26 +118,24 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size) tcm_size = tcm_sizes[(tcm_region >> 2) & 0x0f]; if (tcm_size < 0) { - pr_err("CPU: %sTCM of unknown size!\n", - type ? "I" : "D"); + pr_err("CPU: %sTCM%d of unknown size\n", + type ? "I" : "D", bank); + return -EINVAL; + } else if (tcm_size > 32) { + pr_err("CPU: %sTCM%d larger than 32k found\n", + type ? "I" : "D", bank); + return -EINVAL; } else { - pr_info("CPU: found %sTCM %dk @ %08x, %senabled\n", + pr_info("CPU: found %sTCM%d %dk @ %08x, %senabled\n", type ? "I" : "D", + bank, tcm_size, (tcm_region & 0xfffff000U), (tcm_region & 1) ? "" : "not "); } - if (tcm_size != expected_size) { - pr_crit("CPU: %sTCM was detected %dk but expected %dk!\n", - type ? "I" : "D", - tcm_size, - expected_size); - /* Adjust to the expected size? what can we do... */ - } - /* Force move the TCM bank to where we want it, enable */ - tcm_region = offset | (tcm_region & 0x00000ffeU) | 1; + tcm_region = *offset | (tcm_region & 0x00000ffeU) | 1; if (!type) asm("mcr p15, 0, %0, c9, c1, 0" @@ -141,10 +146,15 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size) : /* No output operands */ : "r" (tcm_region)); - pr_debug("CPU: moved %sTCM %dk to %08x, enabled\n", - type ? "I" : "D", - tcm_size, - (tcm_region & 0xfffff000U)); + /* Increase offset */ + *offset += (tcm_size << 10); + + pr_info("CPU: moved %sTCM%d %dk to %08x, enabled\n", + type ? "I" : "D", + bank, + tcm_size, + (tcm_region & 0xfffff000U)); + return 0; } /* @@ -153,34 +163,52 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size) void __init tcm_init(void) { u32 tcm_status = read_cpuid_tcmstatus(); + u8 dtcm_banks = (tcm_status >> 16) & 0x03; + u8 itcm_banks = (tcm_status & 0x03); char *start; char *end; char *ram; + int ret; + int i; /* Setup DTCM if present */ - if (tcm_status & (1 << 16)) { - setup_tcm_bank(0, DTCM_OFFSET, - (DTCM_END - DTCM_OFFSET + 1) >> 10); + if (dtcm_banks > 0) { + for (i = 0; i < dtcm_banks; i++) { + ret = setup_tcm_bank(0, i, dtcm_banks, &dtcm_end); + if (ret) + return; + } + dtcm_res.end = dtcm_end - 1; request_resource(&iomem_resource, &dtcm_res); + dtcm_iomap[0].length = dtcm_end - DTCM_OFFSET; iotable_init(dtcm_iomap, 1); /* Copy data from RAM to DTCM */ start = &__sdtcm_data; end = &__edtcm_data; ram = &__dtcm_start; + /* This means you compiled more code than fits into DTCM */ + BUG_ON((end - start) > (dtcm_end - DTCM_OFFSET)); memcpy(start, ram, (end-start)); pr_debug("CPU DTCM: copied data from %p - %p\n", start, end); } /* Setup ITCM if present */ - if (tcm_status & 1) { - setup_tcm_bank(1, ITCM_OFFSET, - (ITCM_END - ITCM_OFFSET + 1) >> 10); + if (itcm_banks > 0) { + for (i = 0; i < itcm_banks; i++) { + ret = setup_tcm_bank(1, i, itcm_banks, &itcm_end); + if (ret) + return; + } + itcm_res.end = itcm_end - 1; request_resource(&iomem_resource, &itcm_res); + itcm_iomap[0].length = itcm_end - ITCM_OFFSET; iotable_init(itcm_iomap, 1); /* Copy code from RAM to ITCM */ start = &__sitcm_text; end = &__eitcm_text; ram = &__itcm_start; + /* This means you compiled more code than fits into ITCM */ + BUG_ON((end - start) > (itcm_end - ITCM_OFFSET)); memcpy(start, ram, (end-start)); pr_debug("CPU ITCM: copied code from %p - %p\n", start, end); } @@ -208,10 +236,10 @@ static int __init setup_tcm_pool(void) pr_debug("Setting up TCM memory pool\n"); /* Add the rest of DTCM to the TCM pool */ - if (tcm_status & (1 << 16)) { - if (dtcm_pool_start < DTCM_END) { + if (tcm_status & (0x03 << 16)) { + if (dtcm_pool_start < dtcm_end) { ret = gen_pool_add(tcm_pool, dtcm_pool_start, - DTCM_END - dtcm_pool_start + 1, -1); + dtcm_end - dtcm_pool_start, -1); if (ret) { pr_err("CPU DTCM: could not add DTCM " \ "remainder to pool!\n"); @@ -219,16 +247,16 @@ static int __init setup_tcm_pool(void) } pr_debug("CPU DTCM: Added %08x bytes @ %08x to " \ "the TCM memory pool\n", - DTCM_END - dtcm_pool_start + 1, + dtcm_end - dtcm_pool_start, dtcm_pool_start); } } /* Add the rest of ITCM to the TCM pool */ - if (tcm_status & 1) { - if (itcm_pool_start < ITCM_END) { + if (tcm_status & 0x03) { + if (itcm_pool_start < itcm_end) { ret = gen_pool_add(tcm_pool, itcm_pool_start, - ITCM_END - itcm_pool_start + 1, -1); + itcm_end - itcm_pool_start, -1); if (ret) { pr_err("CPU ITCM: could not add ITCM " \ "remainder to pool!\n"); @@ -236,7 +264,7 @@ static int __init setup_tcm_pool(void) } pr_debug("CPU ITCM: Added %08x bytes @ %08x to " \ "the TCM memory pool\n", - ITCM_END - itcm_pool_start + 1, + itcm_end - itcm_pool_start, itcm_pool_start); } } diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 1621e5327b2a..cda78d59aa31 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -30,6 +30,7 @@ #include <asm/unistd.h> #include <asm/traps.h> #include <asm/unwind.h> +#include <asm/tls.h> #include "ptrace.h" #include "signal.h" @@ -518,17 +519,20 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs) case NR(set_tls): thread->tp_value = regs->ARM_r0; -#if defined(CONFIG_HAS_TLS_REG) - asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) ); -#elif !defined(CONFIG_TLS_REG_EMUL) - /* - * User space must never try to access this directly. - * Expect your app to break eventually if you do so. - * The user helper at 0xffff0fe0 must be used instead. - * (see entry-armv.S for details) - */ - *((unsigned int *)0xffff0ff0) = regs->ARM_r0; -#endif + if (tls_emu) + return 0; + if (has_tls_reg) { + asm ("mcr p15, 0, %0, c13, c0, 3" + : : "r" (regs->ARM_r0)); + } else { + /* + * User space must never try to access this directly. + * Expect your app to break eventually if you do so. + * The user helper at 0xffff0fe0 must be used instead. + * (see entry-armv.S for details) + */ + *((unsigned int *)0xffff0ff0) = regs->ARM_r0; + } return 0; #ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG @@ -743,6 +747,16 @@ void __init trap_init(void) return; } +static void __init kuser_get_tls_init(unsigned long vectors) +{ + /* + * vectors + 0xfe0 = __kuser_get_tls + * vectors + 0xfe8 = hardware TLS instruction at 0xffff0fe8 + */ + if (tls_emu || has_tls_reg) + memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4); +} + void __init early_trap_init(void) { unsigned long vectors = CONFIG_VECTORS_BASE; @@ -761,6 +775,11 @@ void __init early_trap_init(void) memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz); /* + * Do processor specific fixups for the kuser helpers + */ + kuser_get_tls_init(vectors); + + /* * Copy signal return handlers into the vector page, and * set sigreturn to be a pointer to these. */ diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 030ba7219f48..59ff42ddf0ae 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -41,7 +41,6 @@ else endif lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o -lib-$(CONFIG_ARCH_L7200) += io-acorn.o lib-$(CONFIG_ARCH_SHARK) += io-shark.o $(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S diff --git a/arch/arm/lib/csumpartialcopyuser.S b/arch/arm/lib/csumpartialcopyuser.S index 59ff6fdc1e63..7d08b43d2c0e 100644 --- a/arch/arm/lib/csumpartialcopyuser.S +++ b/arch/arm/lib/csumpartialcopyuser.S @@ -71,7 +71,7 @@ .pushsection .fixup,"ax" .align 4 9001: mov r4, #-EFAULT - ldr r5, [fp, #4] @ *err_ptr + ldr r5, [sp, #8*4] @ *err_ptr str r4, [r5] ldmia sp, {r1, r2} @ retrieve dst, len add r2, r2, r1 diff --git a/arch/arm/mach-aaec2000/include/mach/memory.h b/arch/arm/mach-aaec2000/include/mach/memory.h index c00822543d9f..4f93c567a35a 100644 --- a/arch/arm/mach-aaec2000/include/mach/memory.h +++ b/arch/arm/mach-aaec2000/include/mach/memory.h @@ -14,14 +14,4 @@ #define PHYS_OFFSET UL(0xf0000000) -/* - * The nodes are the followings: - * - * node 0: 0xf000.0000 - 0xf3ff.ffff - * node 1: 0xf400.0000 - 0xf7ff.ffff - * node 2: 0xf800.0000 - 0xfbff.ffff - * node 3: 0xfc00.0000 - 0xffff.ffff - */ -#define NODE_MEM_SIZE_BITS 26 - #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 841eaf8f27e2..939bccd70569 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -366,6 +366,17 @@ config MACH_STAMP9G20 endif +if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) +comment "AT91SAM9260/AT91SAM9G20 boards" + +config MACH_SNAPPER_9260 + bool "Bluewater Systems Snapper 9260/9G20 module" + help + Select this if you are using the Bluewater Systems Snapper 9260 or + Snapper 9G20 modules. + <http://www.bluewatersys.com/> +endif + # ---------------------------------------------------------- if ARCH_AT91SAM9G45 diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index c1f821e58222..ca2ac003f41f 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -66,6 +66,9 @@ obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o +# AT91SAM9260/AT91SAM9G20 board-specific support +obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o + # AT91SAM9G45 board-specific support obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 85166b7e69a1..753c0d31a3d3 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -20,6 +20,7 @@ #include <mach/at91_pmc.h> #include <mach/at91_rstc.h> #include <mach/at91_shdwc.h> +#include <mach/cpu.h> #include "generic.h" #include "clock.h" @@ -176,6 +177,13 @@ static struct clk mmc1_clk = { .type = CLK_TYPE_PERIPHERAL, }; +/* Video decoder clock - Only for sam9m10/sam9m11 */ +static struct clk vdec_clk = { + .name = "vdec_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_VDEC, + .type = CLK_TYPE_PERIPHERAL, +}; + /* One additional fake clock for ohci */ static struct clk ohci_clk = { .name = "ohci_clk", @@ -239,6 +247,9 @@ static void __init at91sam9g45_register_clocks(void) for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) clk_register(periph_clocks[i]); + if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11()) + clk_register(&vdec_clk); + clk_register(&pck0); clk_register(&pck1); } diff --git a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c index a4102d72cc9b..c49f5c003ee1 100644 --- a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c +++ b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c @@ -26,6 +26,9 @@ #include <linux/spi/spi.h> #include <linux/spi/at73c213.h> #include <linux/clk.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/consumer.h> #include <mach/hardware.h> #include <asm/setup.h> @@ -235,6 +238,46 @@ static struct gpio_led ek_leds[] = { } }; +#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) +static struct regulator_consumer_supply ek_audio_consumer_supplies[] = { + REGULATOR_SUPPLY("AVDD", "0-001b"), + REGULATOR_SUPPLY("HPVDD", "0-001b"), + REGULATOR_SUPPLY("DBVDD", "0-001b"), + REGULATOR_SUPPLY("DCVDD", "0-001b"), +}; + +static struct regulator_init_data ek_avdd_reg_init_data = { + .constraints = { + .name = "3V3", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .consumer_supplies = ek_audio_consumer_supplies, + .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies), +}; + +static struct fixed_voltage_config ek_vdd_pdata = { + .supply_name = "board-3V3", + .microvolts = 3300000, + .gpio = -EINVAL, + .enabled_at_boot = 0, + .init_data = &ek_avdd_reg_init_data, +}; +static struct platform_device ek_voltage_regulator = { + .name = "reg-fixed-voltage", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &ek_vdd_pdata, + }, +}; +static void __init ek_add_regulators(void) +{ + platform_device_register(&ek_voltage_regulator); +} +#else +static void __init ek_add_regulators(void) {} +#endif + static struct i2c_board_info __initdata ek_i2c_devices[] = { { I2C_BOARD_INFO("24c512", 0x50), @@ -256,6 +299,8 @@ static void __init ek_board_init(void) ek_add_device_nand(); /* Ethernet */ at91_add_device_eth(&ek_macb_data); + /* Regulators */ + ek_add_regulators(); /* MMC */ #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) at91_add_device_mci(0, &ek_mmc_data); diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c index c11fd47aec5d..6ea9808b8868 100644 --- a/arch/arm/mach-at91/board-sam9g20ek.c +++ b/arch/arm/mach-at91/board-sam9g20ek.c @@ -27,6 +27,9 @@ #include <linux/gpio_keys.h> #include <linux/input.h> #include <linux/clk.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/consumer.h> #include <mach/hardware.h> #include <asm/setup.h> @@ -269,6 +272,46 @@ static void __init ek_add_device_buttons(void) static void __init ek_add_device_buttons(void) {} #endif +#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) +static struct regulator_consumer_supply ek_audio_consumer_supplies[] = { + REGULATOR_SUPPLY("AVDD", "0-001b"), + REGULATOR_SUPPLY("HPVDD", "0-001b"), + REGULATOR_SUPPLY("DBVDD", "0-001b"), + REGULATOR_SUPPLY("DCVDD", "0-001b"), +}; + +static struct regulator_init_data ek_avdd_reg_init_data = { + .constraints = { + .name = "3V3", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .consumer_supplies = ek_audio_consumer_supplies, + .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies), +}; + +static struct fixed_voltage_config ek_vdd_pdata = { + .supply_name = "board-3V3", + .microvolts = 3300000, + .gpio = -EINVAL, + .enabled_at_boot = 0, + .init_data = &ek_avdd_reg_init_data, +}; +static struct platform_device ek_voltage_regulator = { + .name = "reg-fixed-voltage", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &ek_vdd_pdata, + }, +}; +static void __init ek_add_regulators(void) +{ + platform_device_register(&ek_voltage_regulator); +} +#else +static void __init ek_add_regulators(void) {} +#endif + static struct i2c_board_info __initdata ek_i2c_devices[] = { { @@ -294,6 +337,8 @@ static void __init ek_board_init(void) ek_add_device_nand(); /* Ethernet */ at91_add_device_eth(&ek_macb_data); + /* Regulators */ + ek_add_regulators(); /* MMC */ at91_add_device_mmc(0, &ek_mmc_data); /* I2C */ diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c new file mode 100644 index 000000000000..2c08ae4ad3a1 --- /dev/null +++ b/arch/arm/mach-at91/board-snapper9260.c @@ -0,0 +1,189 @@ +/* + * linux/arch/arm/mach-at91/board-snapper9260.c + * + * Copyright (C) 2010 Bluewater System Ltd + * + * Author: Andre Renaud <andre@bluewatersys.com> + * Author: Ryan Mallon <ryan@bluewatersys.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/platform_device.h> +#include <linux/spi/spi.h> +#include <linux/i2c/pca953x.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/hardware.h> +#include <mach/board.h> +#include <mach/at91sam9_smc.h> + +#include "sam9_smc.h" +#include "generic.h" + +#define SNAPPER9260_IO_EXP_GPIO(x) (NR_BUILTIN_GPIO + (x)) + +static void __init snapper9260_map_io(void) +{ + at91sam9260_initialize(18432000); + + /* Debug on ttyS0 */ + at91_register_uart(0, 0, 0); + at91_set_serial_console(0); + + at91_register_uart(AT91SAM9260_ID_US0, 1, + ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_register_uart(AT91SAM9260_ID_US1, 2, + ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_register_uart(AT91SAM9260_ID_US2, 3, 0); +} + +static void __init snapper9260_init_irq(void) +{ + at91sam9260_init_interrupts(NULL); +} + +static struct at91_usbh_data __initdata snapper9260_usbh_data = { + .ports = 2, +}; + +static struct at91_udc_data __initdata snapper9260_udc_data = { + .vbus_pin = SNAPPER9260_IO_EXP_GPIO(5), + .vbus_active_low = 1, + .vbus_polled = 1, +}; + +static struct at91_eth_data snapper9260_macb_data = { + .is_rmii = 1, +}; + +static struct mtd_partition __initdata snapper9260_nand_partitions[] = { + { + .name = "Preboot", + .offset = 0, + .size = SZ_128K, + }, + { + .name = "Bootloader", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + }, + { + .name = "Environment", + .offset = MTDPART_OFS_APPEND, + .size = SZ_128K, + }, + { + .name = "Kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + }, + { + .name = "Filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct mtd_partition * __init +snapper9260_nand_partition_info(int size, int *num_partitions) +{ + *num_partitions = ARRAY_SIZE(snapper9260_nand_partitions); + return snapper9260_nand_partitions; +} + +static struct atmel_nand_data __initdata snapper9260_nand_data = { + .ale = 21, + .cle = 22, + .rdy_pin = AT91_PIN_PC13, + .partition_info = snapper9260_nand_partition_info, + .bus_width_16 = 0, +}; + +static struct sam9_smc_config __initdata snapper9260_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 0, + .ncs_write_setup = 0, + .nwe_setup = 0, + + .ncs_read_pulse = 5, + .nrd_pulse = 2, + .ncs_write_pulse = 5, + .nwe_pulse = 2, + + .read_cycle = 7, + .write_cycle = 7, + + .mode = (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE), + .tdf_cycles = 1, +}; + +static struct pca953x_platform_data snapper9260_io_expander_data = { + .gpio_base = SNAPPER9260_IO_EXP_GPIO(0), +}; + +static struct i2c_board_info __initdata snapper9260_i2c_devices[] = { + { + /* IO expander */ + I2C_BOARD_INFO("max7312", 0x28), + .platform_data = &snapper9260_io_expander_data, + }, + { + /* Audio codec */ + I2C_BOARD_INFO("tlv320aic23", 0x1a), + }, + { + /* RTC */ + I2C_BOARD_INFO("isl1208", 0x6f), + }, +}; + +static void __init snapper9260_add_device_nand(void) +{ + at91_set_A_periph(AT91_PIN_PC14, 0); + sam9_smc_configure(3, &snapper9260_nand_smc_config); + at91_add_device_nand(&snapper9260_nand_data); +} + +static void __init snapper9260_board_init(void) +{ + at91_add_device_i2c(snapper9260_i2c_devices, + ARRAY_SIZE(snapper9260_i2c_devices)); + at91_add_device_serial(); + at91_add_device_usbh(&snapper9260_usbh_data); + at91_add_device_udc(&snapper9260_udc_data); + at91_add_device_eth(&snapper9260_macb_data); + at91_add_device_ssc(AT91SAM9260_ID_SSC, (ATMEL_SSC_TF | ATMEL_SSC_TK | + ATMEL_SSC_TD | ATMEL_SSC_RD)); + snapper9260_add_device_nand(); +} + +MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module") + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91sam926x_timer, + .map_io = snapper9260_map_io, + .init_irq = snapper9260_init_irq, + .init_machine = snapper9260_board_init, +MACHINE_END + + diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h index d8c1ededaa75..9c6af9737485 100644 --- a/arch/arm/mach-at91/include/mach/at91cap9.h +++ b/arch/arm/mach-at91/include/mach/at91cap9.h @@ -84,7 +84,7 @@ */ #define AT91_ECC (0xffffe200 - AT91_BASE_SYS) #define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) -#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS) +#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) #define AT91_SMC (0xffffe800 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) #define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h index 1499b1cbffdd..976f4a6c3353 100644 --- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h +++ b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h @@ -15,7 +15,7 @@ #ifndef AT91CAP9_DDRSDR_H #define AT91CAP9_DDRSDR_H -#define AT91_DDRSDRC_MR (AT91_DDRSDRC + 0x00) /* Mode Register */ +#define AT91_DDRSDRC_MR 0x00 /* Mode Register */ #define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ #define AT91_DDRSDRC_MODE_NORMAL 0 #define AT91_DDRSDRC_MODE_NOP 1 @@ -25,10 +25,10 @@ #define AT91_DDRSDRC_MODE_EXT_LMR 5 #define AT91_DDRSDRC_MODE_DEEP 6 -#define AT91_DDRSDRC_RTR (AT91_DDRSDRC + 0x04) /* Refresh Timer Register */ +#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */ #define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ -#define AT91_DDRSDRC_CR (AT91_DDRSDRC + 0x08) /* Configuration Register */ +#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */ #define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ #define AT91_DDRSDRC_NC_SDR8 (0 << 0) #define AT91_DDRSDRC_NC_SDR9 (1 << 0) @@ -49,7 +49,7 @@ #define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */ #define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ -#define AT91_DDRSDRC_T0PR (AT91_DDRSDRC + 0x0C) /* Timing 0 Register */ +#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ @@ -59,13 +59,13 @@ #define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ -#define AT91_DDRSDRC_T1PR (AT91_DDRSDRC + 0x10) /* Timing 1 Register */ +#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ #define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ -#define AT91_DDRSDRC_LPR (AT91_DDRSDRC + 0x18) /* Low Power Register */ +#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */ #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ #define AT91_DDRSDRC_LPCB_DISABLE 0 #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 @@ -80,14 +80,14 @@ #define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) #define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) -#define AT91_DDRSDRC_MDR (AT91_DDRSDRC + 0x1C) /* Memory Device Register */ +#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */ #define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ #define AT91_DDRSDRC_MD_SDR 0 #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 #define AT91_DDRSDRC_MD_DDR 2 #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 -#define AT91_DDRSDRC_DLLR (AT91_DDRSDRC + 0x20) /* DLL Information Register */ +#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */ #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ @@ -98,5 +98,11 @@ #define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ #define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ +/* Register access macros */ +#define at91_ramc_read(num, reg) \ + at91_sys_read(AT91_DDRSDRC##num + reg) +#define at91_ramc_write(num, reg, value) \ + at91_sys_write(AT91_DDRSDRC##num + reg, value) + #endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index 43c396b9b4cb..4e79036d3b80 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -84,7 +84,7 @@ * System Peripherals (offset from AT91_BASE_SYS) */ #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index 87de8be17484..2b5618518129 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h @@ -68,7 +68,7 @@ /* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h new file mode 100644 index 000000000000..d27b15ba8ebf --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h @@ -0,0 +1,130 @@ +/* + * Header file for the Atmel DDR/SDR SDRAM Controller + * + * Copyright (C) 2010 Atmel Corporation + * Nicolas Ferre <nicolas.ferre@atmel.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef AT91SAM9_DDRSDR_H +#define AT91SAM9_DDRSDR_H + +#define AT91_DDRSDRC_MR 0x00 /* Mode Register */ +#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */ +#define AT91_DDRSDRC_MODE_NORMAL 0 +#define AT91_DDRSDRC_MODE_NOP 1 +#define AT91_DDRSDRC_MODE_PRECHARGE 2 +#define AT91_DDRSDRC_MODE_LMR 3 +#define AT91_DDRSDRC_MODE_REFRESH 4 +#define AT91_DDRSDRC_MODE_EXT_LMR 5 +#define AT91_DDRSDRC_MODE_DEEP 6 + +#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */ +#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ + +#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */ +#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ +#define AT91_DDRSDRC_NC_SDR8 (0 << 0) +#define AT91_DDRSDRC_NC_SDR9 (1 << 0) +#define AT91_DDRSDRC_NC_SDR10 (2 << 0) +#define AT91_DDRSDRC_NC_SDR11 (3 << 0) +#define AT91_DDRSDRC_NC_DDR9 (0 << 0) +#define AT91_DDRSDRC_NC_DDR10 (1 << 0) +#define AT91_DDRSDRC_NC_DDR11 (2 << 0) +#define AT91_DDRSDRC_NC_DDR12 (3 << 0) +#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */ +#define AT91_DDRSDRC_NR_11 (0 << 2) +#define AT91_DDRSDRC_NR_12 (1 << 2) +#define AT91_DDRSDRC_NR_13 (2 << 2) +#define AT91_DDRSDRC_NR_14 (3 << 2) +#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ +#define AT91_DDRSDRC_CAS_2 (2 << 4) +#define AT91_DDRSDRC_CAS_3 (3 << 4) +#define AT91_DDRSDRC_CAS_25 (6 << 4) +#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */ +#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ +#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */ +#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */ +#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */ +#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */ + +#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ +#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ +#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ +#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ +#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ +#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ +#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ +#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ +#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */ +#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ + +#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ +#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ +#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ +#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ +#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ + +#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */ +#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */ +#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */ +#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */ +#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ + +#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ +#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ +#define AT91_DDRSDRC_LPCB_DISABLE 0 +#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 +#define AT91_DDRSDRC_LPCB_POWER_DOWN 2 +#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 +#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ +#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ +#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ +#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ +#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ +#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12) +#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) +#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) +#define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */ +#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ + +#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ +#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ +#define AT91_DDRSDRC_MD_SDR 0 +#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 +#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 +#define AT91_DDRSDRC_MD_DDR2 6 +#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ +#define AT91_DDRSDRC_DBW_32BITS (0 << 4) +#define AT91_DDRSDRC_DBW_16BITS (1 << 4) + +#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ +#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ +#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ +#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ +#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ + +#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */ +#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ + +#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */ + +#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */ +#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */ +#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */ +#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */ + +#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */ +#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ +#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ + +/* Register access macros */ +#define at91_ramc_read(num, reg) \ + at91_sys_read(AT91_DDRSDRC##num + reg) +#define at91_ramc_write(num, reg, value) \ + at91_sys_write(AT91_DDRSDRC##num + reg, value) + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h index b7260389f7ca..100f5a592926 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h @@ -17,7 +17,7 @@ #define AT91SAM9_SDRAMC_H /* SDRAM Controller (SDRAMC) registers */ -#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ +#define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */ #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ #define AT91_SDRAMC_MODE_NORMAL 0 #define AT91_SDRAMC_MODE_NOP 1 @@ -27,10 +27,10 @@ #define AT91_SDRAMC_MODE_EXT_LMR 5 #define AT91_SDRAMC_MODE_DEEP 6 -#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ +#define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */ #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ -#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ +#define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */ #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ #define AT91_SDRAMC_NC_8 (0 << 0) #define AT91_SDRAMC_NC_9 (1 << 0) @@ -57,7 +57,7 @@ #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ -#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ +#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */ #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ #define AT91_SDRAMC_LPCB_DISABLE 0 #define AT91_SDRAMC_LPCB_SELF_REFRESH 1 @@ -71,16 +71,21 @@ #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) -#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ -#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ -#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ -#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ +#define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */ +#define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */ +#define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */ +#define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */ #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ -#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ +#define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */ #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ #define AT91_SDRAMC_MD_SDRAM 0 #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 +/* Register access macros */ +#define at91_ramc_read(num, reg) \ + at91_sys_read(AT91_SDRAMC##num + reg) +#define at91_ramc_write(num, reg, value) \ + at91_sys_write(AT91_SDRAMC##num + reg, value) #endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index fc2de6c09c86..87ba8517ad98 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h @@ -74,7 +74,7 @@ */ #define AT91_DMA (0xffffe600 - AT91_BASE_SYS) #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index df2ed848c9f8..58528aa9c8a8 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h @@ -44,6 +44,8 @@ /* USB Device */ struct at91_udc_data { u8 vbus_pin; /* high == host powering us */ + u8 vbus_active_low; /* vbus polarity */ + u8 vbus_polled; /* Use polling, not interrupt */ u8 pullup_pin; /* active == D+ pulled up */ u8 pullup_active_low; /* true == pullup_pin is active low */ }; diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index 833659d1200a..3bef931d0b1c 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -52,6 +52,7 @@ static inline unsigned long at91_cpu_fully_identify(void) #define ARCH_EXID_AT91SAM9M11 0x00000001 #define ARCH_EXID_AT91SAM9M10 0x00000002 +#define ARCH_EXID_AT91SAM9G46 0x00000003 #define ARCH_EXID_AT91SAM9G45 0x00000004 static inline unsigned long at91_exid_identify(void) @@ -128,9 +129,18 @@ static inline unsigned long at91cap9_rev_identify(void) #ifdef CONFIG_ARCH_AT91SAM9G45 #define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45) #define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES) +#define cpu_is_at91sam9m10() (cpu_is_at91sam9g45() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9M10)) +#define cpu_is_at91sam9m46() (cpu_is_at91sam9g45() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9G46)) +#define cpu_is_at91sam9m11() (cpu_is_at91sam9g45() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9M11)) #else #define cpu_is_at91sam9g45() (0) #define cpu_is_at91sam9g45es() (0) +#define cpu_is_at91sam9m10() (0) +#define cpu_is_at91sam9g46() (0) +#define cpu_is_at91sam9m11() (0) #endif #ifdef CONFIG_ARCH_AT91CAP9 diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index 04c91e31c9c5..bfdd8ab26dc8 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -19,6 +19,7 @@ #define PIN_BASE NR_AIC_IRQS #define MAX_GPIO_BANKS 5 +#define NR_BUILTIN_GPIO (PIN_BASE + (MAX_GPIO_BANKS * 32)) /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 08322c44df1a..8c87d0c1b8f8 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -30,14 +30,50 @@ static inline u32 sdram_selfrefresh_enable(void) { u32 saved_lpr, lpr; - saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR); + saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR); lpr = saved_lpr & ~AT91_DDRSDRC_LPCB; - at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); + at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); return saved_lpr; } -#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr) +#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr) + +#elif defined(CONFIG_ARCH_AT91SAM9G45) +#include <mach/at91sam9_ddrsdr.h> + +/* We manage both DDRAM/SDRAM controllers, we need more than one value to + * remember. + */ +static u32 saved_lpr1; + +static inline u32 sdram_selfrefresh_enable(void) +{ + /* Those tow values allow us to delay self-refresh activation + * to the maximum. */ + u32 lpr0, lpr1; + u32 saved_lpr0; + + saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); + lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; + lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; + + saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); + lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; + lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; + + /* self-refresh mode now */ + at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); + at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); + + return saved_lpr0; +} + +#define sdram_selfrefresh_disable(saved_lpr0) \ + do { \ + at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \ + at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \ + } while (0) #else #include <mach/at91sam9_sdramc.h> @@ -47,7 +83,6 @@ static inline u32 sdram_selfrefresh_enable(void) * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; * handle those cases both here and in the Suspend-To-RAM support. */ -#define AT91_SDRAMC AT91_SDRAMC0 #warning Assuming EB1 SDRAM controller is *NOT* used #endif @@ -55,13 +90,13 @@ static inline u32 sdram_selfrefresh_enable(void) { u32 saved_lpr, lpr; - saved_lpr = at91_sys_read(AT91_SDRAMC_LPR); + saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR); lpr = saved_lpr & ~AT91_SDRAMC_LPCB; - at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH); + at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH); return saved_lpr; } -#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) +#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr) #endif diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S index 9c5b48e68a71..b6b00a1f6125 100644 --- a/arch/arm/mach-at91/pm_slowclock.S +++ b/arch/arm/mach-at91/pm_slowclock.S @@ -16,10 +16,12 @@ #include <mach/hardware.h> #include <mach/at91_pmc.h> -#ifdef CONFIG_ARCH_AT91RM9200 +#if defined(CONFIG_ARCH_AT91RM9200) #include <mach/at91rm9200_mc.h> #elif defined(CONFIG_ARCH_AT91CAP9) #include <mach/at91cap9_ddrsdr.h> +#elif defined(CONFIG_ARCH_AT91SAM9G45) +#include <mach/at91sam9_ddrsdr.h> #else #include <mach/at91sam9_sdramc.h> #endif @@ -30,7 +32,6 @@ * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; * handle those cases both here and in the Suspend-To-RAM support. */ -#define AT91_SDRAMC AT91_SDRAMC0 #warning Assuming EB1 SDRAM controller is *NOT* used #endif @@ -113,12 +114,14 @@ ENTRY(at91_slow_clock) /* * Register usage: * R1 = Base address of AT91_PMC - * R2 = Base address of AT91_SDRAMC (or AT91_SYS on AT91RM9200) + * R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS) * R3 = temporary register * R4 = temporary register + * R5 = Base address of second RAM Controller or 0 if not present */ ldr r1, .at91_va_base_pmc ldr r2, .at91_va_base_sdramc + ldr r5, .at91_va_base_ramc1 /* Drain write buffer */ mcr p15, 0, r0, c7, c10, 4 @@ -127,20 +130,33 @@ ENTRY(at91_slow_clock) /* Put SDRAM in self-refresh mode */ mov r3, #1 str r3, [r2, #AT91_SDRAMC_SRR] -#elif defined(CONFIG_ARCH_AT91CAP9) - /* Enable SDRAM self-refresh mode */ - ldr r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC] - str r3, .saved_sam9_lpr +#elif defined(CONFIG_ARCH_AT91CAP9) \ + || defined(CONFIG_ARCH_AT91SAM9G45) - mov r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH - str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC] + /* prepare for DDRAM self-refresh mode */ + ldr r3, [r2, #AT91_DDRSDRC_LPR] + str r3, .saved_sam9_lpr + bic r3, #AT91_DDRSDRC_LPCB + orr r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH + + /* figure out if we use the second ram controller */ + cmp r5, #0 + ldrne r4, [r5, #AT91_DDRSDRC_LPR] + strne r4, .saved_sam9_lpr1 + bicne r4, #AT91_DDRSDRC_LPCB + orrne r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH + + /* Enable DDRAM self-refresh mode */ + str r3, [r2, #AT91_DDRSDRC_LPR] + strne r4, [r5, #AT91_DDRSDRC_LPR] #else /* Enable SDRAM self-refresh mode */ - ldr r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC] + ldr r3, [r2, #AT91_SDRAMC_LPR] str r3, .saved_sam9_lpr - mov r3, #AT91_SDRAMC_LPCB_SELF_REFRESH - str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC] + bic r3, #AT91_SDRAMC_LPCB + orr r3, #AT91_SDRAMC_LPCB_SELF_REFRESH + str r3, [r2, #AT91_SDRAMC_LPR] #endif /* Save Master clock setting */ @@ -247,14 +263,21 @@ ENTRY(at91_slow_clock) #ifdef CONFIG_ARCH_AT91RM9200 /* Do nothing - self-refresh is automatically disabled. */ -#elif defined(CONFIG_ARCH_AT91CAP9) - /* Restore LPR on AT91CAP9 */ +#elif defined(CONFIG_ARCH_AT91CAP9) \ + || defined(CONFIG_ARCH_AT91SAM9G45) + /* Restore LPR on AT91 with DDRAM */ ldr r3, .saved_sam9_lpr - str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC] + str r3, [r2, #AT91_DDRSDRC_LPR] + + /* if we use the second ram controller */ + cmp r5, #0 + ldrne r4, .saved_sam9_lpr1 + strne r4, [r5, #AT91_DDRSDRC_LPR] + #else - /* Restore LPR on AT91SAM9 */ + /* Restore LPR on AT91 with SDRAM */ ldr r3, .saved_sam9_lpr - str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC] + str r3, [r2, #AT91_SDRAMC_LPR] #endif /* Restore registers, and return */ @@ -273,18 +296,29 @@ ENTRY(at91_slow_clock) .saved_sam9_lpr: .word 0 +.saved_sam9_lpr1: + .word 0 + .at91_va_base_pmc: .word AT91_VA_BASE_SYS + AT91_PMC #ifdef CONFIG_ARCH_AT91RM9200 .at91_va_base_sdramc: .word AT91_VA_BASE_SYS -#elif defined(CONFIG_ARCH_AT91CAP9) +#elif defined(CONFIG_ARCH_AT91CAP9) \ + || defined(CONFIG_ARCH_AT91SAM9G45) .at91_va_base_sdramc: - .word AT91_VA_BASE_SYS + AT91_DDRSDRC + .word AT91_VA_BASE_SYS + AT91_DDRSDRC0 #else .at91_va_base_sdramc: - .word AT91_VA_BASE_SYS + AT91_SDRAMC + .word AT91_VA_BASE_SYS + AT91_SDRAMC0 +#endif + +.at91_va_base_ramc1: +#if defined(CONFIG_ARCH_AT91SAM9G45) + .word AT91_VA_BASE_SYS + AT91_DDRSDRC1 +#else + .word 0 #endif ENTRY(at91_slow_clock_sz) diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c index 72e405df0fb0..d3f959e92b2d 100644 --- a/arch/arm/mach-bcmring/core.c +++ b/arch/arm/mach-bcmring/core.c @@ -91,14 +91,23 @@ static struct clk uart_clk = { .parent = &pll1_clk, }; +static struct clk dummy_apb_pclk = { + .name = "BUSCLK", + .type = CLK_TYPE_PRIMARY, + .mode = CLK_MODE_XTAL, +}; + static struct clk_lookup lookups[] = { - { /* UART0 */ - .dev_id = "uarta", - .clk = &uart_clk, - }, { /* UART1 */ - .dev_id = "uartb", - .clk = &uart_clk, - } + { /* Bus clock */ + .con_id = "apb_pclk", + .clk = &dummy_apb_pclk, + }, { /* UART0 */ + .dev_id = "uarta", + .clk = &uart_clk, + }, { /* UART1 */ + .dev_id = "uartb", + .clk = &uart_clk, + } }; static struct amba_device *amba_devs[] __initdata = { diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index dbaae5f746a1..eb34bd1251d4 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig @@ -30,7 +30,6 @@ config ARCH_CLEP7312 config ARCH_EDB7211 bool "EDB7211" select ISA - select ARCH_DISCONTIGMEM_ENABLE select ARCH_SPARSEMEM_ENABLE select ARCH_SELECT_MEMORY_MODEL help diff --git a/arch/arm/mach-clps711x/clep7312.c b/arch/arm/mach-clps711x/clep7312.c index 09fb57e45213..3c3bf45039ff 100644 --- a/arch/arm/mach-clps711x/clep7312.c +++ b/arch/arm/mach-clps711x/clep7312.c @@ -32,7 +32,6 @@ fixup_clep7312(struct machine_desc *desc, struct tag *tags, mi->nr_banks=1; mi->bank[0].start = 0xc0000000; mi->bank[0].size = 0x01000000; - mi->bank[0].node = 0; } diff --git a/arch/arm/mach-clps711x/edb7211-arch.c b/arch/arm/mach-clps711x/edb7211-arch.c index dc81cc68595d..4a7a2322979a 100644 --- a/arch/arm/mach-clps711x/edb7211-arch.c +++ b/arch/arm/mach-clps711x/edb7211-arch.c @@ -18,6 +18,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/init.h> +#include <linux/memblock.h> #include <linux/types.h> #include <linux/string.h> @@ -29,6 +30,12 @@ extern void edb7211_map_io(void); +/* Reserve screen memory region at the start of main system memory. */ +static void __init edb7211_reserve(void) +{ + memblock_reserve(PHYS_OFFSET, 0x00020000); +} + static void __init fixup_edb7211(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi) @@ -43,10 +50,8 @@ fixup_edb7211(struct machine_desc *desc, struct tag *tags, */ mi->bank[0].start = 0xc0000000; mi->bank[0].size = 8*1024*1024; - mi->bank[0].node = 0; mi->bank[1].start = 0xc1000000; mi->bank[1].size = 8*1024*1024; - mi->bank[1].node = 1; mi->nr_banks = 2; } @@ -57,6 +62,7 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)") .boot_params = 0xc0020100, /* 0xc0000000 - 0xc001ffff can be video RAM */ .fixup = fixup_edb7211, .map_io = edb7211_map_io, + .reserve = edb7211_reserve, .init_irq = clps711x_init_irq, .timer = &clps711x_timer, MACHINE_END diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c index 7430e4049d87..a696099aa4f8 100644 --- a/arch/arm/mach-clps711x/fortunet.c +++ b/arch/arm/mach-clps711x/fortunet.c @@ -39,7 +39,6 @@ struct meminfo memmap = { { .start = 0xC0000000, .size = 0x01000000, - .node = 0 }, }, }; diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h index f70d52be48a2..f45c8e892cb5 100644 --- a/arch/arm/mach-clps711x/include/mach/memory.h +++ b/arch/arm/mach-clps711x/include/mach/memory.h @@ -20,7 +20,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H - /* * Physical DRAM offset. */ @@ -72,7 +71,6 @@ * node 2: 0xd0000000 - 0xd7ffffff * node 3: 0xd8000000 - 0xdfffffff */ -#define NODE_MEM_SIZE_BITS 24 #define SECTION_SIZE_BITS 24 #define MAX_PHYSMEM_BITS 32 diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile index 427507a2d696..11033f1c2e23 100644 --- a/arch/arm/mach-cns3xxx/Makefile +++ b/arch/arm/mach-cns3xxx/Makefile @@ -1,2 +1,3 @@ -obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o +obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o +obj-$(CONFIG_PCI) += pcie.o obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index 2e30c8288740..9df8391fd78a 100644 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/arch/arm/mach-cns3xxx/cns3420vb.c @@ -32,6 +32,7 @@ #include <mach/cns3xxx.h> #include <mach/irqs.h> #include "core.h" +#include "devices.h" /* * NOR Flash @@ -117,6 +118,9 @@ static void __init cns3420_init(void) { platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); + cns3xxx_ahci_init(); + cns3xxx_sdhci_init(); + pm_power_off = cns3xxx_power_off; } diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c new file mode 100644 index 000000000000..50b4d31c27c0 --- /dev/null +++ b/arch/arm/mach-cns3xxx/devices.c @@ -0,0 +1,111 @@ +/* + * CNS3xxx common devices + * + * Copyright 2008 Cavium Networks + * Scott Shu + * Copyright 2010 MontaVista Software, LLC. + * Anton Vorontsov <avorontsov@mvista.com> + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/io.h> +#include <linux/init.h> +#include <linux/compiler.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <mach/cns3xxx.h> +#include <mach/irqs.h> +#include "core.h" +#include "devices.h" + +/* + * AHCI + */ +static struct resource cns3xxx_ahci_resource[] = { + [0] = { + .start = CNS3XXX_SATA2_BASE, + .end = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_CNS3XXX_SATA, + .end = IRQ_CNS3XXX_SATA, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32); + +static struct platform_device cns3xxx_ahci_pdev = { + .name = "ahci", + .id = 0, + .resource = cns3xxx_ahci_resource, + .num_resources = ARRAY_SIZE(cns3xxx_ahci_resource), + .dev = { + .dma_mask = &cns3xxx_ahci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init cns3xxx_ahci_init(void) +{ + u32 tmp; + + tmp = __raw_readl(MISC_SATA_POWER_MODE); + tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */ + tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */ + __raw_writel(tmp, MISC_SATA_POWER_MODE); + + /* Enable SATA PHY */ + cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0); + cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1); + + /* Enable SATA Clock */ + cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA); + + /* De-Asscer SATA Reset */ + cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA)); + + platform_device_register(&cns3xxx_ahci_pdev); +} + +/* + * SDHCI + */ +static struct resource cns3xxx_sdhci_resources[] = { + [0] = { + .start = CNS3XXX_SDIO_BASE, + .end = CNS3XXX_SDIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_CNS3XXX_SDIO, + .end = IRQ_CNS3XXX_SDIO, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cns3xxx_sdhci_pdev = { + .name = "sdhci-cns3xxx", + .id = 0, + .num_resources = ARRAY_SIZE(cns3xxx_sdhci_resources), + .resource = cns3xxx_sdhci_resources, +}; + +void __init cns3xxx_sdhci_init(void) +{ + u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014); + u32 gpioa_pins = __raw_readl(gpioa); + + /* MMC/SD pins share with GPIOA */ + gpioa_pins |= 0x1fff0004; + __raw_writel(gpioa_pins, gpioa); + + cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); + cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO)); + + platform_device_register(&cns3xxx_sdhci_pdev); +} diff --git a/arch/arm/mach-cns3xxx/devices.h b/arch/arm/mach-cns3xxx/devices.h new file mode 100644 index 000000000000..27e15a10aa85 --- /dev/null +++ b/arch/arm/mach-cns3xxx/devices.h @@ -0,0 +1,20 @@ +/* + * CNS3xxx common devices + * + * Copyright 2008 Cavium Networks + * Scott Shu + * Copyright 2010 MontaVista Software, LLC. + * Anton Vorontsov <avorontsov@mvista.com> + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#ifndef __CNS3XXX_DEVICES_H_ +#define __CNS3XXX_DEVICES_H_ + +void __init cns3xxx_ahci_init(void); +void __init cns3xxx_sdhci_init(void); + +#endif /* __CNS3XXX_DEVICES_H_ */ diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h index 8a2f5a21d4ee..6dbce13771ca 100644 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h @@ -247,37 +247,36 @@ * Misc block */ #define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) -#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset)))) - -#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00) -#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04) -#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08) -#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C) -#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP_VALUE(0x10) -#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x14) -#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x18) -#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP_VALUE(0x1C) -#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP_VALUE(0x20) -#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x24) -#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x28) -#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x2C) -#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x30) -#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x34) -#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP_VALUE(0x40) -#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP_VALUE(0x44) -#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP_VALUE(0x48) -#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP_VALUE(0x4C) -#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x50) -#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x54) - -#define MISC_SATA_POWER_MODE MISC_MEM_MAP_VALUE(0x310) - -#define MISC_USB_CFG_REG MISC_MEM_MAP_VALUE(0x800) -#define MISC_USB_STS_REG MISC_MEM_MAP_VALUE(0x804) -#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP_VALUE(0x808) -#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP_VALUE(0x80c) -#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP_VALUE(0x810) -#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP_VALUE(0x814) + +#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00) +#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04) +#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08) +#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C) +#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10) +#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14) +#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18) +#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C) +#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20) +#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24) +#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28) +#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C) +#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30) +#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34) +#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40) +#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44) +#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48) +#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C) +#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50) +#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54) + +#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310) + +#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800) +#define MISC_USB_STS_REG MISC_MEM_MAP(0x804) +#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808) +#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c) +#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810) +#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814) #define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) #define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) @@ -300,21 +299,21 @@ /* * Power management and clock control */ -#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset)))) - -#define PM_CLK_GATE_REG PMU_REG_VALUE(0x000) -#define PM_SOFT_RST_REG PMU_REG_VALUE(0x004) -#define PM_HS_CFG_REG PMU_REG_VALUE(0x008) -#define PM_CACTIVE_STA_REG PMU_REG_VALUE(0x00C) -#define PM_PWR_STA_REG PMU_REG_VALUE(0x010) -#define PM_CLK_CTRL_REG PMU_REG_VALUE(0x014) -#define PM_PLL_LCD_I2S_CTRL_REG PMU_REG_VALUE(0x018) -#define PM_PLL_HM_PD_CTRL_REG PMU_REG_VALUE(0x01C) -#define PM_REGULAT_CTRL_REG PMU_REG_VALUE(0x020) -#define PM_WDT_CTRL_REG PMU_REG_VALUE(0x024) -#define PM_WU_CTRL0_REG PMU_REG_VALUE(0x028) -#define PM_WU_CTRL1_REG PMU_REG_VALUE(0x02C) -#define PM_CSR_REG PMU_REG_VALUE(0x030) +#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs)) + +#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000) +#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004) +#define PM_HS_CFG_REG PMU_MEM_MAP(0x008) +#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C) +#define PM_PWR_STA_REG PMU_MEM_MAP(0x010) +#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014) +#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018) +#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C) +#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020) +#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024) +#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028) +#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C) +#define PM_CSR_REG PMU_MEM_MAP(0x030) /* PM_CLK_GATE_REG */ #define PM_CLK_GATE_REG_OFFSET_SDIO (25) diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c new file mode 100644 index 000000000000..38088c36936c --- /dev/null +++ b/arch/arm/mach-cns3xxx/pcie.c @@ -0,0 +1,389 @@ +/* + * PCI-E support for CNS3xxx + * + * Copyright 2008 Cavium Networks + * Richard Liu <richard.liu@caviumnetworks.com> + * Copyright 2010 MontaVista Software, LLC. + * Anton Vorontsov <avorontsov@mvista.com> + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/bug.h> +#include <linux/pci.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/interrupt.h> +#include <linux/ptrace.h> +#include <asm/mach/map.h> +#include <mach/cns3xxx.h> +#include "core.h" + +enum cns3xxx_access_type { + CNS3XXX_HOST_TYPE = 0, + CNS3XXX_CFG0_TYPE, + CNS3XXX_CFG1_TYPE, + CNS3XXX_NUM_ACCESS_TYPES, +}; + +struct cns3xxx_pcie { + struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES]; + unsigned int irqs[2]; + struct resource res_io; + struct resource res_mem; + struct hw_pci hw_pci; + + bool linked; +}; + +static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */ + +static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata) +{ + struct pci_sys_data *root = sysdata; + + return &cns3xxx_pcie[root->domain]; +} + +static struct cns3xxx_pcie *pdev_to_cnspci(struct pci_dev *dev) +{ + return sysdata_to_cnspci(dev->sysdata); +} + +static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus) +{ + return sysdata_to_cnspci(bus->sysdata); +} + +static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus, + unsigned int devfn, int where) +{ + struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus); + int busno = bus->number; + int slot = PCI_SLOT(devfn); + int offset; + enum cns3xxx_access_type type; + void __iomem *base; + + /* If there is no link, just show the CNS PCI bridge. */ + if (!cnspci->linked && (busno > 0 || slot > 0)) + return NULL; + + /* + * The CNS PCI bridge doesn't fit into the PCI hierarchy, though + * we still want to access it. For this to work, we must place + * the first device on the same bus as the CNS PCI bridge. + */ + if (busno == 0) { + if (slot > 1) + return NULL; + type = slot; + } else { + type = CNS3XXX_CFG1_TYPE; + } + + base = (void __iomem *)cnspci->cfg_bases[type].virtual; + offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc); + + return base + offset; +} + +static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + u32 v; + void __iomem *base; + u32 mask = (0x1ull << (size * 8)) - 1; + int shift = (where % 4) * 8; + + base = cns3xxx_pci_cfg_base(bus, devfn, where); + if (!base) { + *val = 0xffffffff; + return PCIBIOS_SUCCESSFUL; + } + + v = __raw_readl(base); + + if (bus->number == 0 && devfn == 0 && + (where & 0xffc) == PCI_CLASS_REVISION) { + /* + * RC's class is 0xb, but Linux PCI driver needs 0x604 + * for a PCIe bridge. So we must fixup the class code + * to 0x604 here. + */ + v &= 0xff; + v |= 0x604 << 16; + } + + *val = (v >> shift) & mask; + + return PCIBIOS_SUCCESSFUL; +} + +static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 v; + void __iomem *base; + u32 mask = (0x1ull << (size * 8)) - 1; + int shift = (where % 4) * 8; + + base = cns3xxx_pci_cfg_base(bus, devfn, where); + if (!base) + return PCIBIOS_SUCCESSFUL; + + v = __raw_readl(base); + + v &= ~(mask << shift); + v |= (val & mask) << shift; + + __raw_writel(v, base); + + return PCIBIOS_SUCCESSFUL; +} + +static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys) +{ + struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys); + struct resource *res_io = &cnspci->res_io; + struct resource *res_mem = &cnspci->res_mem; + struct resource **sysres = sys->resource; + + BUG_ON(request_resource(&iomem_resource, res_io) || + request_resource(&iomem_resource, res_mem)); + + sysres[0] = res_io; + sysres[1] = res_mem; + + return 1; +} + +static struct pci_ops cns3xxx_pcie_ops = { + .read = cns3xxx_pci_read_config, + .write = cns3xxx_pci_write_config, +}; + +static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys) +{ + return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys); +} + +static int cns3xxx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev); + int irq = cnspci->irqs[slot]; + + pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n", + pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn), slot, pin, irq); + + return irq; +} + +static struct cns3xxx_pcie cns3xxx_pcie[] = { + [0] = { + .cfg_bases = { + [CNS3XXX_HOST_TYPE] = { + .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE), + .length = SZ_16M, + .type = MT_DEVICE, + }, + [CNS3XXX_CFG0_TYPE] = { + .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE), + .length = SZ_16M, + .type = MT_DEVICE, + }, + [CNS3XXX_CFG1_TYPE] = { + .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE), + .length = SZ_16M, + .type = MT_DEVICE, + }, + }, + .res_io = { + .name = "PCIe0 I/O space", + .start = CNS3XXX_PCIE0_IO_BASE, + .end = CNS3XXX_PCIE0_IO_BASE + SZ_16M - 1, + .flags = IORESOURCE_IO, + }, + .res_mem = { + .name = "PCIe0 non-prefetchable", + .start = CNS3XXX_PCIE0_MEM_BASE, + .end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, + }, + .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, }, + .hw_pci = { + .domain = 0, + .swizzle = pci_std_swizzle, + .nr_controllers = 1, + .setup = cns3xxx_pci_setup, + .scan = cns3xxx_pci_scan_bus, + .map_irq = cns3xxx_pcie_map_irq, + }, + }, + [1] = { + .cfg_bases = { + [CNS3XXX_HOST_TYPE] = { + .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE), + .length = SZ_16M, + .type = MT_DEVICE, + }, + [CNS3XXX_CFG0_TYPE] = { + .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE), + .length = SZ_16M, + .type = MT_DEVICE, + }, + [CNS3XXX_CFG1_TYPE] = { + .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE), + .length = SZ_16M, + .type = MT_DEVICE, + }, + }, + .res_io = { + .name = "PCIe1 I/O space", + .start = CNS3XXX_PCIE1_IO_BASE, + .end = CNS3XXX_PCIE1_IO_BASE + SZ_16M - 1, + .flags = IORESOURCE_IO, + }, + .res_mem = { + .name = "PCIe1 non-prefetchable", + .start = CNS3XXX_PCIE1_MEM_BASE, + .end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, + }, + .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, }, + .hw_pci = { + .domain = 1, + .swizzle = pci_std_swizzle, + .nr_controllers = 1, + .setup = cns3xxx_pci_setup, + .scan = cns3xxx_pci_scan_bus, + .map_irq = cns3xxx_pcie_map_irq, + }, + }, +}; + +static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci) +{ + int port = cnspci->hw_pci.domain; + u32 reg; + unsigned long time; + + reg = __raw_readl(MISC_PCIE_CTRL(port)); + /* + * Enable Application Request to 1, it will exit L1 automatically, + * but when chip back, it will use another clock, still can use 0x1. + */ + reg |= 0x3; + __raw_writel(reg, MISC_PCIE_CTRL(port)); + + pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port); + pr_info("PCIe: Port[%d] Check data link layer...", port); + + time = jiffies; + while (1) { + reg = __raw_readl(MISC_PCIE_PM_DEBUG(port)); + if (reg & 0x1) { + pr_info("Link up.\n"); + cnspci->linked = 1; + break; + } else if (time_after(jiffies, time + 50)) { + pr_info("Device not found.\n"); + break; + } + } +} + +static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci) +{ + int port = cnspci->hw_pci.domain; + struct pci_sys_data sd = { + .domain = port, + }; + struct pci_bus bus = { + .number = 0, + .ops = &cns3xxx_pcie_ops, + .sysdata = &sd, + }; + u32 io_base = cnspci->res_io.start >> 16; + u32 mem_base = cnspci->res_mem.start >> 16; + u32 host_base = cnspci->cfg_bases[CNS3XXX_HOST_TYPE].pfn; + u32 cfg0_base = cnspci->cfg_bases[CNS3XXX_CFG0_TYPE].pfn; + u32 devfn = 0; + u8 tmp8; + u16 pos; + u16 dc; + + host_base = (__pfn_to_phys(host_base) - 1) >> 16; + cfg0_base = (__pfn_to_phys(cfg0_base) - 1) >> 16; + + pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0); + pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1); + pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1); + + pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8); + pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8); + pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8); + + pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base); + pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, host_base); + pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base); + pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, cfg0_base); + + if (!cnspci->linked) + return; + + /* Set Device Max_Read_Request_Size to 128 byte */ + devfn = PCI_DEVFN(1, 0); + pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP); + pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc); + dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */ + pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc); + pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc); + if (!(dc & (0x3 << 12))) + pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n"); + + /* Disable PCIe0 Interrupt Mask INTA to INTD */ + __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port)); +} + +static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) +{ + if (fsr & (1 << 10)) + regs->ARM_pc += 4; + return 0; +} + +static int __init cns3xxx_pcie_init(void) +{ + int i; + + hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, + "imprecise external abort"); + + for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { + iotable_init(cns3xxx_pcie[i].cfg_bases, + ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases)); + cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i)); + cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i)); + cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); + cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); + pci_common_init(&cns3xxx_pcie[i].hw_pci); + } + + pci_assign_unassigned_resources(); + + return 0; +} +device_initcall(cns3xxx_pcie_init); diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c index 725e1a4fc231..38e44706feab 100644 --- a/arch/arm/mach-cns3xxx/pm.c +++ b/arch/arm/mach-cns3xxx/pm.c @@ -6,18 +6,25 @@ * published by the Free Software Foundation. */ +#include <linux/io.h> #include <linux/delay.h> #include <mach/system.h> #include <mach/cns3xxx.h> void cns3xxx_pwr_clk_en(unsigned int block) { - PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK); + u32 reg = __raw_readl(PM_CLK_GATE_REG); + + reg |= (block & PM_CLK_GATE_REG_MASK); + __raw_writel(reg, PM_CLK_GATE_REG); } void cns3xxx_pwr_power_up(unsigned int block) { - PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL); + u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); + + reg &= ~(block & CNS3XXX_PWR_PLL_ALL); + __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); /* Wait for 300us for the PLL output clock locked. */ udelay(300); @@ -25,22 +32,29 @@ void cns3xxx_pwr_power_up(unsigned int block) void cns3xxx_pwr_power_down(unsigned int block) { + u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); + /* write '1' to power down */ - PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL); + reg |= (block & CNS3XXX_PWR_PLL_ALL); + __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); }; static void cns3xxx_pwr_soft_rst_force(unsigned int block) { + u32 reg = __raw_readl(PM_SOFT_RST_REG); + /* * bit 0, 28, 29 => program low to reset, * the other else program low and then high */ if (block & 0x30000001) { - PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK); + reg &= ~(block & PM_SOFT_RST_REG_MASK); } else { - PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK); - PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK); + reg &= ~(block & PM_SOFT_RST_REG_MASK); + reg |= (block & PM_SOFT_RST_REG_MASK); } + + __raw_writel(reg, PM_SOFT_RST_REG); } void cns3xxx_pwr_soft_rst(unsigned int block) @@ -73,12 +87,13 @@ void arch_reset(char mode, const char *cmd) */ int cns3xxx_cpu_clock(void) { + u32 reg = __raw_readl(PM_CLK_CTRL_REG); int cpu; int cpu_sel; int div_sel; - cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf; - div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3; + cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf; + div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3; cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel; diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h index a91edfb8beea..22eb97c1c30b 100644 --- a/arch/arm/mach-davinci/include/mach/memory.h +++ b/arch/arm/mach-davinci/include/mach/memory.h @@ -48,19 +48,16 @@ * below 128M */ static inline void -__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes) +__arch_adjust_zones(unsigned long *size, unsigned long *holes) { unsigned int sz = (128<<20) >> PAGE_SHIFT; - if (node != 0) - sz = 0; - size[1] = size[0] - sz; size[0] = sz; } -#define arch_adjust_zones(node, zone_size, holes) \ - if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes) +#define arch_adjust_zones(zone_size, holes) \ + if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes) #define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) #define MAX_DMA_ADDRESS (PAGE_OFFSET + (128<<20)) diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 5da2cf402c81..f7a12586a1f5 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -752,6 +752,67 @@ void __init dove_xor1_init(void) platform_device_register(&dove_xor11_channel); } +/***************************************************************************** + * SDIO + ****************************************************************************/ +static u64 sdio_dmamask = DMA_BIT_MASK(32); + +static struct resource dove_sdio0_resources[] = { + { + .start = DOVE_SDIO0_PHYS_BASE, + .end = DOVE_SDIO0_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_SDIO0, + .end = IRQ_DOVE_SDIO0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_sdio0 = { + .name = "sdhci-mv", + .id = 0, + .dev = { + .dma_mask = &sdio_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = dove_sdio0_resources, + .num_resources = ARRAY_SIZE(dove_sdio0_resources), +}; + +void __init dove_sdio0_init(void) +{ + platform_device_register(&dove_sdio0); +} + +static struct resource dove_sdio1_resources[] = { + { + .start = DOVE_SDIO1_PHYS_BASE, + .end = DOVE_SDIO1_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_SDIO1, + .end = IRQ_DOVE_SDIO1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_sdio1 = { + .name = "sdhci-mv", + .id = 1, + .dev = { + .dma_mask = &sdio_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = dove_sdio1_resources, + .num_resources = ARRAY_SIZE(dove_sdio1_resources), +}; + +void __init dove_sdio1_init(void) +{ + platform_device_register(&dove_sdio1); +} + void __init dove_init(void) { int tclk; diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h index b29e8937de4f..a51517c3fe76 100644 --- a/arch/arm/mach-dove/common.h +++ b/arch/arm/mach-dove/common.h @@ -36,5 +36,7 @@ void dove_uart3_init(void); void dove_spi0_init(void); void dove_spi1_init(void); void dove_i2c_init(void); +void dove_sdio0_init(void); +void dove_sdio1_init(void); #endif diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c index f2971b745224..bef70460fbc6 100644 --- a/arch/arm/mach-dove/dove-db-setup.c +++ b/arch/arm/mach-dove/dove-db-setup.c @@ -82,6 +82,8 @@ static void __init dove_db_init(void) dove_ehci0_init(); dove_ehci1_init(); dove_sata_init(&dove_db_sata_data); + dove_sdio0_init(); + dove_sdio1_init(); dove_spi0_init(); dove_spi1_init(); dove_uart0_init(); diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c index 3a1a855bfdca..f744f676783f 100644 --- a/arch/arm/mach-ep93xx/adssphere.c +++ b/arch/arm/mach-ep93xx/adssphere.c @@ -13,7 +13,6 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/mtd/physmap.h> #include <mach/hardware.h> @@ -21,26 +20,6 @@ #include <asm/mach/arch.h> -static struct physmap_flash_data adssphere_flash_data = { - .width = 4, -}; - -static struct resource adssphere_flash_resource = { - .start = EP93XX_CS6_PHYS_BASE, - .end = EP93XX_CS6_PHYS_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device adssphere_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &adssphere_flash_data, - }, - .num_resources = 1, - .resource = &adssphere_flash_resource, -}; - static struct ep93xx_eth_data __initdata adssphere_eth_data = { .phy_id = 1, }; @@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata adssphere_eth_data = { static void __init adssphere_init_machine(void) { ep93xx_init_devices(); - platform_device_register(&adssphere_flash); - + ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M); ep93xx_register_eth(&adssphere_eth_data, 1); } diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c index e29bdef9b2e2..7f3039761d91 100644 --- a/arch/arm/mach-ep93xx/clock.c +++ b/arch/arm/mach-ep93xx/clock.c @@ -185,7 +185,7 @@ static struct clk_lookup clocks[] = { INIT_CK(NULL, "pll1", &clk_pll1), INIT_CK(NULL, "fclk", &clk_f), INIT_CK(NULL, "hclk", &clk_h), - INIT_CK(NULL, "pclk", &clk_p), + INIT_CK(NULL, "apb_pclk", &clk_p), INIT_CK(NULL, "pll2", &clk_pll2), INIT_CK("ep93xx-ohci", NULL, &clk_usb_host), INIT_CK("ep93xx-keypad", NULL, &clk_keypad), diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 9092677f63eb..8e37a045188c 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -29,6 +29,7 @@ #include <linux/termios.h> #include <linux/amba/bus.h> #include <linux/amba/serial.h> +#include <linux/mtd/physmap.h> #include <linux/i2c.h> #include <linux/i2c-gpio.h> #include <linux/spi/spi.h> @@ -215,8 +216,8 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits) spin_lock_irqsave(&syscon_swlock, flags); val = __raw_readl(EP93XX_SYSCON_DEVCFG); - val |= set_bits; val &= ~clear_bits; + val |= set_bits; __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); __raw_writel(val, EP93XX_SYSCON_DEVCFG); @@ -348,6 +349,43 @@ static struct platform_device ep93xx_ohci_device = { /************************************************************************* + * EP93xx physmap'ed flash + *************************************************************************/ +static struct physmap_flash_data ep93xx_flash_data; + +static struct resource ep93xx_flash_resource = { + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ep93xx_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &ep93xx_flash_data, + }, + .num_resources = 1, + .resource = &ep93xx_flash_resource, +}; + +/** + * ep93xx_register_flash() - Register the external flash device. + * @width: bank width in octets + * @start: resource start address + * @size: resource size + */ +void __init ep93xx_register_flash(unsigned int width, + resource_size_t start, resource_size_t size) +{ + ep93xx_flash_data.width = width; + + ep93xx_flash_resource.start = start; + ep93xx_flash_resource.end = start + size - 1; + + platform_device_register(&ep93xx_flash); +} + + +/************************************************************************* * EP93xx ethernet peripheral handling *************************************************************************/ static struct ep93xx_eth_data ep93xx_eth_data; @@ -620,6 +658,11 @@ static struct platform_device ep93xx_fb_device = { .resource = ep93xx_fb_resource, }; +static struct platform_device ep93xx_bl_device = { + .name = "ep93xx-bl", + .id = -1, +}; + /** * ep93xx_register_fb - Register the framebuffer platform device. * @data: platform specific framebuffer configuration (__initdata) @@ -628,6 +671,7 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data) { ep93xxfb_data = *data; platform_device_register(&ep93xx_fb_device); + platform_device_register(&ep93xx_bl_device); } diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index 3884182cd362..c2ce9034ba87 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c @@ -27,7 +27,6 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/mtd/physmap.h> #include <linux/gpio.h> #include <linux/i2c.h> #include <linux/i2c-gpio.h> @@ -38,39 +37,13 @@ #include <asm/mach/arch.h> -static struct physmap_flash_data edb93xx_flash_data; - -static struct resource edb93xx_flash_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device edb93xx_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &edb93xx_flash_data, - }, - .num_resources = 1, - .resource = &edb93xx_flash_resource, -}; - -static void __init __edb93xx_register_flash(unsigned int width, - resource_size_t start, resource_size_t size) -{ - edb93xx_flash_data.width = width; - edb93xx_flash_resource.start = start; - edb93xx_flash_resource.end = start + size - 1; - - platform_device_register(&edb93xx_flash); -} - static void __init edb93xx_register_flash(void) { if (machine_is_edb9307() || machine_is_edb9312() || machine_is_edb9315()) { - __edb93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M); + ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M); } else { - __edb93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M); + ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M); } } diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c index a809618e9f05..d97168c0ba33 100644 --- a/arch/arm/mach-ep93xx/gesbc9312.c +++ b/arch/arm/mach-ep93xx/gesbc9312.c @@ -13,7 +13,6 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/mtd/physmap.h> #include <mach/hardware.h> @@ -21,26 +20,6 @@ #include <asm/mach/arch.h> -static struct physmap_flash_data gesbc9312_flash_data = { - .width = 4, -}; - -static struct resource gesbc9312_flash_resource = { - .start = EP93XX_CS6_PHYS_BASE, - .end = EP93XX_CS6_PHYS_BASE + SZ_8M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device gesbc9312_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &gesbc9312_flash_data, - }, - .num_resources = 1, - .resource = &gesbc9312_flash_resource, -}; - static struct ep93xx_eth_data __initdata gesbc9312_eth_data = { .phy_id = 1, }; @@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata gesbc9312_eth_data = { static void __init gesbc9312_init_machine(void) { ep93xx_init_devices(); - platform_device_register(&gesbc9312_flash); - + ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_8M); ep93xx_register_eth(&gesbc9312_eth_data, 0); } diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h index 9a4413dd44bb..a6c09176334c 100644 --- a/arch/arm/mach-ep93xx/include/mach/platform.h +++ b/arch/arm/mach-ep93xx/include/mach/platform.h @@ -43,6 +43,9 @@ static inline void ep93xx_devcfg_clear_bits(unsigned int bits) unsigned int ep93xx_chip_revision(void); +void ep93xx_register_flash(unsigned int width, + resource_size_t start, resource_size_t size); + void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr); void ep93xx_register_i2c(struct i2c_gpio_platform_data *data, struct i2c_board_info *devices, int num); diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c index 1cc911b4efa6..2ba776320a82 100644 --- a/arch/arm/mach-ep93xx/micro9.c +++ b/arch/arm/mach-ep93xx/micro9.c @@ -14,7 +14,6 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/mtd/physmap.h> #include <linux/io.h> #include <mach/hardware.h> @@ -31,31 +30,6 @@ * Micro9-Lite uses a separate MTD map driver for flash support * Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1 *************************************************************************/ -static struct physmap_flash_data micro9_flash_data; - -static struct resource micro9_flash_resource = { - .start = EP93XX_CS1_PHYS_BASE, - .end = EP93XX_CS1_PHYS_BASE + SZ_64M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device micro9_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = µ9_flash_data, - }, - .num_resources = 1, - .resource = µ9_flash_resource, -}; - -static void __init __micro9_register_flash(unsigned int width) -{ - micro9_flash_data.width = width; - - platform_device_register(µ9_flash); -} - static unsigned int __init micro9_detect_bootwidth(void) { u32 v; @@ -70,10 +44,17 @@ static unsigned int __init micro9_detect_bootwidth(void) static void __init micro9_register_flash(void) { + unsigned int width; + if (machine_is_micro9()) - __micro9_register_flash(4); + width = 4; else if (machine_is_micro9m() || machine_is_micro9s()) - __micro9_register_flash(micro9_detect_bootwidth()); + width = micro9_detect_bootwidth(); + else + width = 0; + + if (width) + ep93xx_register_flash(width, EP93XX_CS1_PHYS_BASE, SZ_64M); } diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c index 388aec95f60e..5dded5884133 100644 --- a/arch/arm/mach-ep93xx/simone.c +++ b/arch/arm/mach-ep93xx/simone.c @@ -18,7 +18,6 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/mtd/physmap.h> #include <linux/gpio.h> #include <linux/i2c.h> #include <linux/i2c-gpio.h> @@ -29,26 +28,6 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> -static struct physmap_flash_data simone_flash_data = { - .width = 2, -}; - -static struct resource simone_flash_resource = { - .start = EP93XX_CS6_PHYS_BASE, - .end = EP93XX_CS6_PHYS_BASE + SZ_8M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device simone_flash = { - .name = "physmap-flash", - .id = 0, - .num_resources = 1, - .resource = &simone_flash_resource, - .dev = { - .platform_data = &simone_flash_data, - }, -}; - static struct ep93xx_eth_data __initdata simone_eth_data = { .phy_id = 1, }; @@ -77,8 +56,7 @@ static struct i2c_board_info __initdata simone_i2c_board_info[] = { static void __init simone_init_machine(void) { ep93xx_init_devices(); - - platform_device_register(&simone_flash); + ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_8M); ep93xx_register_eth(&simone_eth_data, 1); ep93xx_register_fb(&simone_fb_info); ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info, diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index ae7319e588c7..93aeab8af705 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -17,7 +17,6 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/m48t86.h> -#include <linux/mtd/physmap.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> @@ -173,31 +172,13 @@ static struct platform_device ts72xx_nand_flash = { }; -/************************************************************************* - * NOR flash (TS-7200 only) - *************************************************************************/ -static struct physmap_flash_data ts72xx_nor_data = { - .width = 2, -}; - -static struct resource ts72xx_nor_resource = { - .start = EP93XX_CS6_PHYS_BASE, - .end = EP93XX_CS6_PHYS_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ts72xx_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev.platform_data = &ts72xx_nor_data, - .resource = &ts72xx_nor_resource, - .num_resources = 1, -}; - static void __init ts72xx_register_flash(void) { + /* + * TS7200 has NOR flash all other TS72xx board have NAND flash. + */ if (board_is_ts7200()) { - platform_device_register(&ts72xx_nor_flash); + ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M); } else { resource_size_t start; diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-imx/Kconfig index 742fd4e6dcb9..c5c0369bb481 100644 --- a/arch/arm/mach-mx2/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -1,42 +1,103 @@ +config IMX_HAVE_DMA_V1 + bool + +if ARCH_MX1 + +config SOC_IMX1 + select CPU_ARM920T + select IMX_HAVE_DMA_V1 + select IMX_HAVE_IOMUX_V1 + bool + +comment "MX1 platforms:" +config MACH_MXLADS + bool + +config ARCH_MX1ADS + bool "MX1ADS platform" + select MACH_MXLADS + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + help + Say Y here if you are using Motorola MX1ADS/MXLADS boards + +config MACH_SCB9328 + bool "Synertronixx scb9328" + select IMX_HAVE_PLATFORM_IMX_UART + help + Say Y here if you are using a Synertronixx scb9328 board + +endif + if ARCH_MX2 +config SOC_IMX21 + select CPU_ARM926T + select ARCH_MXC_AUDMUX_V1 + select IMX_HAVE_DMA_V1 + select IMX_HAVE_IOMUX_V1 + bool + +config SOC_IMX27 + select CPU_ARM926T + select ARCH_MXC_AUDMUX_V1 + select IMX_HAVE_DMA_V1 + select IMX_HAVE_IOMUX_V1 + bool + choice prompt "CPUs:" default MACH_MX21 config MACH_MX21 bool "i.MX21 support" - select ARCH_MXC_AUDMUX_V1 + select SOC_IMX21 help This enables support for Freescale's MX2 based i.MX21 processor. config MACH_MX27 bool "i.MX27 support" - select ARCH_MXC_AUDMUX_V1 + select SOC_IMX27 help This enables support for Freescale's MX2 based i.MX27 processor. endchoice -comment "MX2 platforms:" +endif + +if MACH_MX21 + +comment "MX21 platforms:" config MACH_MX21ADS bool "MX21ADS platform" - depends on MACH_MX21 + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND help Include support for MX21ADS platform. This includes specific configurations for the board and its peripherals. +endif + +if MACH_MX27 + +comment "MX27 platforms:" + config MACH_MX27ADS bool "MX27ADS platform" - depends on MACH_MX27 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND help Include support for MX27ADS platform. This includes specific configurations for the board and its peripherals. config MACH_PCM038 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" - depends on MACH_MX27 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help Include support for phyCORE-i.MX27 (aka pcm038) platform. This @@ -58,7 +119,9 @@ endchoice config MACH_CPUIMX27 bool "Eukrea CPUIMX27 module" - depends on MACH_MX27 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND help Include support for Eukrea CPUIMX27 platform. This includes specific configurations for the module and its peripherals. @@ -67,9 +130,16 @@ config MACH_EUKREA_CPUIMX27_USESDHC2 bool "CPUIMX27 integrates SDHC2 module" depends on MACH_CPUIMX27 help - This adds support for the internal SDHC2 used on CPUIMX27 used + This adds support for the internal SDHC2 used on CPUIMX27 for wifi or eMMC. +config MACH_EUKREA_CPUIMX27_USEUART4 + bool "CPUIMX27 integrates UART4 module" + depends on MACH_CPUIMX27 + help + This adds support for the internal UART4 used on CPUIMX27 + for bluetooth. + choice prompt "Baseboard" depends on MACH_CPUIMX27 @@ -78,6 +148,8 @@ choice config MACH_EUKREA_MBIMX27_BASEBOARD prompt "Eukrea MBIMX27 development board" bool + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_SPI_IMX help This adds board specific devices that can be found on Eukrea's MBIMX27 evaluation board. @@ -86,21 +158,24 @@ endchoice config MACH_MX27_3DS bool "MX27PDK platform" - depends on MACH_MX27 + select IMX_HAVE_PLATFORM_IMX_UART help Include support for MX27PDK platform. This includes specific configurations for the board and its peripherals. config MACH_IMX27LITE bool "LogicPD MX27 LITEKIT platform" - depends on MACH_MX27 + select IMX_HAVE_PLATFORM_IMX_UART help Include support for MX27 LITEKIT platform. This includes specific configurations for the board and its peripherals. config MACH_PCA100 bool "Phytec phyCARD-s (pca100)" - depends on MACH_MX27 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help Include support for phyCARD-s (aka pca100) platform. This @@ -108,7 +183,9 @@ config MACH_PCA100 config MACH_MXT_TD60 bool "Maxtrack i-MXT TD60" - depends on MACH_MX27 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND help Include support for i-MXT (aka td60) platform. This includes specific configurations for the module and its peripherals. diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-imx/Makefile index e3254faac828..46a9fdfbbd15 100644 --- a/arch/arm/mach-mx2/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -4,14 +4,24 @@ # Object file lists. -obj-y := devices.o serial.o +obj-y := devices.o -obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o +obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o -obj-$(CONFIG_MACH_MX27) += cpu_imx27.o -obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o +obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o +obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o + +obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o +obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o + +# Support for CMOS sensor interface +obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o + +obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o +obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o + obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o diff --git a/arch/arm/mach-mx2/Makefile.boot b/arch/arm/mach-imx/Makefile.boot index e867398a8fdb..7988a85cf07d 100644 --- a/arch/arm/mach-mx2/Makefile.boot +++ b/arch/arm/mach-imx/Makefile.boot @@ -1,3 +1,7 @@ +zreladdr-$(CONFIG_ARCH_MX1) := 0x08008000 +params_phys-$(CONFIG_ARCH_MX1) := 0x08000100 +initrd_phys-$(CONFIG_ARCH_MX1) := 0x08800000 + zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000 params_phys-$(CONFIG_MACH_MX21) := 0xC0000100 initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000 diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-imx/clock-imx1.c index 6cf2d4a7511d..c05096c38301 100644 --- a/arch/arm/mach-mx1/clock.c +++ b/arch/arm/mach-imx/clock-imx1.c @@ -2,18 +2,17 @@ * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix * * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. */ #include <linux/kernel.h> @@ -29,7 +28,41 @@ #include <mach/clock.h> #include <mach/hardware.h> #include <mach/common.h> -#include "crm_regs.h" + +#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off))) + +/* CCM register addresses */ +#define CCM_CSCR IO_ADDR_CCM(0x0) +#define CCM_MPCTL0 IO_ADDR_CCM(0x4) +#define CCM_SPCTL0 IO_ADDR_CCM(0xc) +#define CCM_PCDR IO_ADDR_CCM(0x20) + +#define CCM_CSCR_CLKO_OFFSET 29 +#define CCM_CSCR_CLKO_MASK (0x7 << 29) +#define CCM_CSCR_USB_OFFSET 26 +#define CCM_CSCR_USB_MASK (0x7 << 26) +#define CCM_CSCR_OSC_EN_SHIFT 17 +#define CCM_CSCR_SYSTEM_SEL (1 << 16) +#define CCM_CSCR_BCLK_OFFSET 10 +#define CCM_CSCR_BCLK_MASK (0xf << 10) +#define CCM_CSCR_PRESC (1 << 15) + +#define CCM_PCDR_PCLK3_OFFSET 16 +#define CCM_PCDR_PCLK3_MASK (0x7f << 16) +#define CCM_PCDR_PCLK2_OFFSET 4 +#define CCM_PCDR_PCLK2_MASK (0xf << 4) +#define CCM_PCDR_PCLK1_OFFSET 0 +#define CCM_PCDR_PCLK1_MASK 0xf + +#define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off))) + +/* SCM register addresses */ +#define SCM_GCCR IO_ADDR_SCM(0xc) + +#define SCM_GCCR_DMA_CLK_EN_OFFSET 3 +#define SCM_GCCR_CSI_CLK_EN_OFFSET 2 +#define SCM_GCCR_MMA_CLK_EN_OFFSET 1 +#define SCM_GCCR_USBD_CLK_EN_OFFSET 0 static int _clk_enable(struct clk *clk) { @@ -596,7 +629,8 @@ int __init mx1_clocks_init(unsigned long fref) clk_enable(&hclk); clk_enable(&fclk); - mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT); + mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), + MX1_TIM1_INT); return 0; } diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-imx/clock-imx21.c index bb419ef4d133..bb419ef4d133 100644 --- a/arch/arm/mach-mx2/clock_imx21.c +++ b/arch/arm/mach-imx/clock-imx21.c diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-imx/clock-imx27.c index 0f0823c8b170..5a1aa15c8a16 100644 --- a/arch/arm/mach-mx2/clock_imx27.c +++ b/arch/arm/mach-imx/clock-imx27.c @@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) - _REGISTER_CLOCK(NULL, "csi", csi_clk) + _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1) _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk) diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-imx/cpu-imx27.c index d8d3b2d84dc5..d8d3b2d84dc5 100644 --- a/arch/arm/mach-mx2/cpu_imx27.c +++ b/arch/arm/mach-imx/cpu-imx27.c diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h new file mode 100644 index 000000000000..a8d94f078196 --- /dev/null +++ b/arch/arm/mach-imx/devices-imx1.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx1.h> +#include <mach/devices-common.h> + +#define imx1_add_i2c_imx(pdata) \ + imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata) + +#define imx1_add_imx_uart0(pdata) \ + imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata) +#define imx1_add_imx_uart1(pdata) \ + imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata) diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h new file mode 100644 index 000000000000..42788e99d127 --- /dev/null +++ b/arch/arm/mach-imx/devices-imx21.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx21.h> +#include <mach/devices-common.h> + +#define imx21_add_i2c_imx(pdata) \ + imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata) + +#define imx21_add_imx_uart0(pdata) \ + imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata) +#define imx21_add_imx_uart1(pdata) \ + imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata) +#define imx21_add_imx_uart2(pdata) \ + imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata) +#define imx21_add_imx_uart3(pdata) \ + imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata) + +#define imx21_add_mxc_nand(pdata) \ + imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata) + +#define imx21_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata) +#define imx21_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata) diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h new file mode 100644 index 000000000000..65e7bb7ec2e8 --- /dev/null +++ b/arch/arm/mach-imx/devices-imx27.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx27.h> +#include <mach/devices-common.h> + +#define imx27_add_i2c_imx0(pdata) \ + imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata) +#define imx27_add_i2c_imx1(pdata) \ + imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata) + +#define imx27_add_imx_uart0(pdata) \ + imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata) +#define imx27_add_imx_uart1(pdata) \ + imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata) +#define imx27_add_imx_uart2(pdata) \ + imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata) +#define imx27_add_imx_uart3(pdata) \ + imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata) +#define imx27_add_imx_uart4(pdata) \ + imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata) +#define imx27_add_imx_uart5(pdata) \ + imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata) + +#define imx27_add_mxc_nand(pdata) \ + imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata) + +#define imx27_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata) +#define imx27_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata) +#define imx27_add_spi_imx2(pdata) \ + imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata) diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-imx/devices.c index a0aeb8a4adc1..9c271a752b84 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-imx/devices.c @@ -11,6 +11,9 @@ * * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * Copyright 2008 Sascha Hauer, kernel@pengutronix.de + * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> + * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -32,6 +35,7 @@ #include <linux/platform_device.h> #include <linux/gpio.h> #include <linux/dma-mapping.h> +#include <linux/serial.h> #include <mach/irqs.h> #include <mach/hardware.h> @@ -40,38 +44,179 @@ #include "devices.h" -/* - * SPI master controller - * - * - i.MX1: 2 channel (slighly different register setting) - * - i.MX21: 2 channel - * - i.MX27: 3 channel - */ -#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \ - static struct resource mxc_spi_resources ## n[] = { \ - { \ - .start = baseaddr, \ - .end = baseaddr + SZ_4K - 1, \ - .flags = IORESOURCE_MEM, \ - }, { \ - .start = irq, \ - .end = irq, \ - .flags = IORESOURCE_IRQ, \ - }, \ - }; \ - \ - struct platform_device mxc_spi_device ## n = { \ - .name = "spi_imx", \ - .id = n, \ - .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \ - .resource = mxc_spi_resources ## n, \ +#if defined(CONFIG_ARCH_MX1) +static struct resource imx1_camera_resources[] = { + { + .start = 0x00224000, + .end = 0x00224010, + .flags = IORESOURCE_MEM, + }, { + .start = MX1_CSI_INT, + .end = MX1_CSI_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 imx1_camera_dmamask = DMA_BIT_MASK(32); + +struct platform_device imx1_camera_device = { + .name = "mx1-camera", + .id = 0, /* This is used to put cameras on this interface */ + .dev = { + .dma_mask = &imx1_camera_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = imx1_camera_resources, + .num_resources = ARRAY_SIZE(imx1_camera_resources), +}; + +static struct resource imx_rtc_resources[] = { + { + .start = 0x00204000, + .end = 0x00204024, + .flags = IORESOURCE_MEM, + }, { + .start = MX1_RTC_INT, + .end = MX1_RTC_INT, + .flags = IORESOURCE_IRQ, + }, { + .start = MX1_RTC_SAMINT, + .end = MX1_RTC_SAMINT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_rtc_device = { + .name = "rtc-imx", + .id = 0, + .resource = imx_rtc_resources, + .num_resources = ARRAY_SIZE(imx_rtc_resources), +}; + +static struct resource imx_wdt_resources[] = { + { + .start = 0x00201000, + .end = 0x00201008, + .flags = IORESOURCE_MEM, + }, { + .start = MX1_WDT_INT, + .end = MX1_WDT_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_wdt_device = { + .name = "imx-wdt", + .id = 0, + .resource = imx_wdt_resources, + .num_resources = ARRAY_SIZE(imx_wdt_resources), +}; + +static struct resource imx_usb_resources[] = { + { + .start = 0x00212000, + .end = 0x00212148, + .flags = IORESOURCE_MEM, + }, { + .start = MX1_USBD_INT0, + .end = MX1_USBD_INT0, + .flags = IORESOURCE_IRQ, + }, { + .start = MX1_USBD_INT1, + .end = MX1_USBD_INT1, + .flags = IORESOURCE_IRQ, + }, { + .start = MX1_USBD_INT2, + .end = MX1_USBD_INT2, + .flags = IORESOURCE_IRQ, + }, { + .start = MX1_USBD_INT3, + .end = MX1_USBD_INT3, + .flags = IORESOURCE_IRQ, + }, { + .start = MX1_USBD_INT4, + .end = MX1_USBD_INT4, + .flags = IORESOURCE_IRQ, + }, { + .start = MX1_USBD_INT5, + .end = MX1_USBD_INT5, + .flags = IORESOURCE_IRQ, + }, { + .start = MX1_USBD_INT6, + .end = MX1_USBD_INT6, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_usb_device = { + .name = "imx_udc", + .id = 0, + .num_resources = ARRAY_SIZE(imx_usb_resources), + .resource = imx_usb_resources, +}; + +/* GPIO port description */ +static struct mxc_gpio_port imx_gpio_ports[] = { + { + .chip.label = "gpio-0", + .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR), + .irq = MX1_GPIO_INT_PORTA, + .virtual_irq_start = MXC_GPIO_IRQ_START, + }, { + .chip.label = "gpio-1", + .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100), + .irq = MX1_GPIO_INT_PORTB, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32, + }, { + .chip.label = "gpio-2", + .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200), + .irq = MX1_GPIO_INT_PORTC, + .virtual_irq_start = MXC_GPIO_IRQ_START + 64, + }, { + .chip.label = "gpio-3", + .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300), + .irq = MX1_GPIO_INT_PORTD, + .virtual_irq_start = MXC_GPIO_IRQ_START + 96, } +}; + +int __init imx1_register_gpios(void) +{ + return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); +} +#endif -DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1); -DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2); +#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27) #ifdef CONFIG_MACH_MX27 -DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3); +static struct resource mx27_camera_resources[] = { + { + .start = MX27_CSI_BASE_ADDR, + .end = MX27_CSI_BASE_ADDR + 0x1f, + .flags = IORESOURCE_MEM, + }, { + .start = MX27_EMMA_PRP_BASE_ADDR, + .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f, + .flags = IORESOURCE_MEM, + }, { + .start = MX27_INT_CSI, + .end = MX27_INT_CSI, + .flags = IORESOURCE_IRQ, + },{ + .start = MX27_INT_EMMAPRP, + .end = MX27_INT_EMMAPRP, + .flags = IORESOURCE_IRQ, + }, +}; +struct platform_device mx27_camera_device = { + .name = "mx2-camera", + .id = 0, + .num_resources = ARRAY_SIZE(mx27_camera_resources), + .resource = mx27_camera_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; #endif /* @@ -140,34 +285,6 @@ struct platform_device mxc_w1_master_device = { .resource = mxc_w1_master_resources, }; -#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \ - static struct resource pfx ## _nand_resources[] = { \ - { \ - .start = baseaddr, \ - .end = baseaddr + SZ_4K - 1, \ - .flags = IORESOURCE_MEM, \ - }, { \ - .start = irq, \ - .end = irq, \ - .flags = IORESOURCE_IRQ, \ - }, \ - }; \ - \ - struct platform_device pfx ## _nand_device = { \ - .name = "mxc_nand", \ - .id = 0, \ - .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \ - .resource = pfx ## _nand_resources, \ - } - -#ifdef CONFIG_MACH_MX21 -DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC); -#endif - -#ifdef CONFIG_MACH_MX27 -DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC); -#endif - /* * lcdc: * - i.MX1: the basic controller @@ -218,32 +335,6 @@ struct platform_device mxc_fec_device = { }; #endif -#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \ - static struct resource mxc_i2c_resources ## n[] = { \ - { \ - .start = baseaddr, \ - .end = baseaddr + SZ_4K - 1, \ - .flags = IORESOURCE_MEM, \ - }, { \ - .start = irq, \ - .end = irq, \ - .flags = IORESOURCE_IRQ, \ - } \ - }; \ - \ - struct platform_device mxc_i2c_device ## n = { \ - .name = "imx-i2c", \ - .id = n, \ - .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \ - .resource = mxc_i2c_resources ## n, \ - } - -DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C); - -#ifdef CONFIG_MACH_MX27 -DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2); -#endif - static struct resource mxc_pwm_resources[] = { { .start = MX2x_PWM_BASE_ADDR, @@ -454,26 +545,21 @@ DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); #ifdef CONFIG_MACH_MX21 DEFINE_MXC_GPIO_PORTS(MX21, imx21); + +int __init imx21_register_gpios(void) +{ + return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); +} #endif #ifdef CONFIG_MACH_MX27 DEFINE_MXC_GPIO_PORTS(MX27, imx27); -#endif -int __init mxc_register_gpios(void) +int __init imx27_register_gpios(void) { -#ifdef CONFIG_MACH_MX21 - if (cpu_is_mx21()) - return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); - else -#endif -#ifdef CONFIG_MACH_MX27 - if (cpu_is_mx27()) - return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); - else -#endif - return 0; + return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); } +#endif #ifdef CONFIG_MACH_MX21 static struct resource mx21_usbhc_resources[] = { @@ -501,3 +587,23 @@ struct platform_device mx21_usbhc_device = { }; #endif +static struct resource imx_kpp_resources[] = { + { + .start = MX2x_KPP_BASE_ADDR, + .end = MX2x_KPP_BASE_ADDR + 0xf, + .flags = IORESOURCE_MEM + }, { + .start = MX2x_INT_KPP, + .end = MX2x_INT_KPP, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_kpp_device = { + .name = "imx-keypad", + .id = -1, + .num_resources = ARRAY_SIZE(imx_kpp_resources), + .resource = imx_kpp_resources, +}; + +#endif diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-imx/devices.h index 84ed51380174..efd4527506a5 100644 --- a/arch/arm/mach-mx2/devices.h +++ b/arch/arm/mach-imx/devices.h @@ -1,3 +1,11 @@ +#ifdef CONFIG_ARCH_MX1 +extern struct platform_device imx1_camera_device; +extern struct platform_device imx_rtc_device; +extern struct platform_device imx_wdt_device; +extern struct platform_device imx_usb_device; +#endif + +#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27) extern struct platform_device mxc_gpt1; extern struct platform_device mxc_gpt2; #ifdef CONFIG_MACH_MX27 @@ -6,37 +14,19 @@ extern struct platform_device mxc_gpt4; extern struct platform_device mxc_gpt5; #endif extern struct platform_device mxc_wdt; -extern struct platform_device mxc_uart_device0; -extern struct platform_device mxc_uart_device1; -extern struct platform_device mxc_uart_device2; -extern struct platform_device mxc_uart_device3; -extern struct platform_device mxc_uart_device4; -extern struct platform_device mxc_uart_device5; extern struct platform_device mxc_w1_master_device; -#ifdef CONFIG_MACH_MX21 -extern struct platform_device imx21_nand_device; -#endif -#ifdef CONFIG_MACH_MX27 -extern struct platform_device imx27_nand_device; -#endif extern struct platform_device mxc_fb_device; extern struct platform_device mxc_fec_device; extern struct platform_device mxc_pwm_device; -extern struct platform_device mxc_i2c_device0; -#ifdef CONFIG_MACH_MX27 -extern struct platform_device mxc_i2c_device1; -#endif extern struct platform_device mxc_sdhc_device0; extern struct platform_device mxc_sdhc_device1; extern struct platform_device mxc_otg_udc_device; +extern struct platform_device mx27_camera_device; extern struct platform_device mxc_otg_host; extern struct platform_device mxc_usbh1; extern struct platform_device mxc_usbh2; -extern struct platform_device mxc_spi_device0; -extern struct platform_device mxc_spi_device1; -#ifdef CONFIG_MACH_MX27 -extern struct platform_device mxc_spi_device2; -#endif extern struct platform_device mx21_usbhc_device; extern struct platform_device imx_ssi_device0; extern struct platform_device imx_ssi_device1; +extern struct platform_device imx_kpp_device; +#endif diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/mach-imx/dma-v1.c index e16014b0d13c..fd1d9197d06e 100644 --- a/arch/arm/plat-mxc/dma-mx1-mx2.c +++ b/arch/arm/mach-imx/dma-v1.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/plat-mxc/dma-mx1-mx2.c + * linux/arch/arm/plat-mxc/dma-v1.c * * i.MX DMA registration and IRQ dispatching * @@ -34,7 +34,7 @@ #include <asm/system.h> #include <asm/irq.h> #include <mach/hardware.h> -#include <mach/dma-mx1-mx2.h> +#include <mach/dma-v1.h> #define DMA_DCR 0x00 /* Control Register */ #define DMA_DISR 0x04 /* Interrupt status Register */ diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index f3b169d5245f..4edc5f439201 100644 --- a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Eric Benard - eric@eukrea.com + * Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com * * Based on pcm970-baseboard.c which is : * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) @@ -24,6 +24,9 @@ #include <linux/platform_device.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> +#include <linux/backlight.h> +#include <video/platform_lcd.h> +#include <linux/input/matrix_keypad.h> #include <asm/mach/arch.h> @@ -32,8 +35,11 @@ #include <mach/imxfb.h> #include <mach/hardware.h> #include <mach/mmc.h> -#include <mach/imx-uart.h> +#include <mach/spi.h> +#include <mach/ssi.h> +#include <mach/audmux.h> +#include "devices-imx27.h" #include "devices.h" static int eukrea_mbimx27_pins[] = { @@ -48,10 +54,12 @@ static int eukrea_mbimx27_pins[] = { PE10_PF_UART3_CTS, PE11_PF_UART3_RTS, /* UART4 */ +#if !defined(MACH_EUKREA_CPUIMX27_USEUART4) PB26_AF_UART4_RTS, PB28_AF_UART4_TXD, PB29_AF_UART4_CTS, PB31_AF_UART4_RXD, +#endif /* SDHC1*/ PE18_PF_SD1_D0, PE19_PF_SD1_D1, @@ -84,10 +92,29 @@ static int eukrea_mbimx27_pins[] = { PA30_PF_CONTRAST, PA31_PF_OE_ACD, /* SPI1 */ - PD28_PF_CSPI1_SS0, PD29_PF_CSPI1_SCLK, PD30_PF_CSPI1_MISO, PD31_PF_CSPI1_MOSI, + /* SSI4 */ +#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \ + || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE) + PC16_PF_SSI4_FS, + PC17_PF_SSI4_RXD | GPIO_PUEN, + PC18_PF_SSI4_TXD | GPIO_PUEN, + PC19_PF_SSI4_CLK, +#endif +}; + +static const uint32_t eukrea_mbimx27_keymap[] = { + KEY(0, 0, KEY_UP), + KEY(0, 1, KEY_DOWN), + KEY(1, 0, KEY_RIGHT), + KEY(1, 1, KEY_LEFT), +}; + +static struct matrix_keymap_data eukrea_mbimx27_keymap_data = { + .keymap = eukrea_mbimx27_keymap, + .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap), }; static struct gpio_led gpio_leds[] = { @@ -103,12 +130,6 @@ static struct gpio_led gpio_leds[] = { .active_low = 1, .gpio = GPIO_PORTF | 19, }, - { - .name = "backlight", - .default_trigger = "backlight", - .active_low = 0, - .gpio = GPIO_PORTE | 5, - }, }; static struct gpio_led_platform_data gpio_led_info = { @@ -127,7 +148,7 @@ static struct platform_device leds_gpio = { static struct imx_fb_videomode eukrea_mbimx27_modes[] = { { .mode = { - .name = "CMO-QGVA", + .name = "CMO-QVGA", .refresh = 60, .xres = 320, .yres = 240, @@ -141,6 +162,38 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = { }, .pcr = 0xFAD08B80, .bpp = 16, + }, { + .mode = { + .name = "DVI-VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 32000, + .hsync_len = 1, + .left_margin = 35, + .right_margin = 0, + .vsync_len = 1, + .upper_margin = 7, + .lower_margin = 0, + }, + .pcr = 0xFA208B80, + .bpp = 16, + }, { + .mode = { + .name = "DVI-SVGA", + .refresh = 60, + .xres = 800, + .yres = 600, + .pixclock = 25000, + .hsync_len = 1, + .left_margin = 35, + .right_margin = 0, + .vsync_len = 1, + .upper_margin = 7, + .lower_margin = 0, + }, + .pcr = 0xFA208B80, + .bpp = 16, }, }; @@ -153,16 +206,52 @@ static struct imx_fb_platform_data eukrea_mbimx27_fb_data = { .dmacr = 0x00040060, }; -static struct imxuart_platform_data uart_pdata[] = { - { - .flags = IMXUART_HAVE_RTSCTS, - }, - { - .flags = IMXUART_HAVE_RTSCTS, +static void eukrea_mbimx27_bl_set_intensity(int intensity) +{ + if (intensity) + gpio_direction_output(GPIO_PORTE | 5, 1); + else + gpio_direction_output(GPIO_PORTE | 5, 0); +} + +static struct generic_bl_info eukrea_mbimx27_bl_info = { + .name = "eukrea_mbimx27-bl", + .max_intensity = 0xff, + .default_intensity = 0xff, + .set_bl_intensity = eukrea_mbimx27_bl_set_intensity, +}; + +static struct platform_device eukrea_mbimx27_bl_dev = { + .name = "generic-bl", + .id = 1, + .dev = { + .platform_data = &eukrea_mbimx27_bl_info, }, }; -#if defined(CONFIG_TOUCHSCREEN_ADS7846) +static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd, + unsigned int power) +{ + if (power) + gpio_direction_output(GPIO_PORTA | 25, 1); + else + gpio_direction_output(GPIO_PORTA | 25, 0); +} + +static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = { + .set_power = eukrea_mbimx27_lcd_power_set, +}; + +static struct platform_device eukrea_mbimx27_lcd_powerdev = { + .name = "platform-lcd", + .dev.platform_data = &eukrea_mbimx27_lcd_power_data, +}; + +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +#if defined(CONFIG_TOUCHSCREEN_ADS7846) \ || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) #define ADS7846_PENDOWN (GPIO_PORTD | 25) @@ -173,7 +262,6 @@ static void ads7846_dev_init(void) printk(KERN_ERR "can't get ads746 pen down GPIO\n"); return; } - gpio_direction_input(ADS7846_PENDOWN); } @@ -186,7 +274,9 @@ static struct ads7846_platform_data ads7846_config __initdata = { .get_pendown_state = ads7846_get_pendown_state, .keep_vref_on = 1, }; +#endif +#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = { [0] = { .modalias = "ads7846", @@ -201,16 +291,30 @@ static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = { static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28}; -static struct spi_imx_master eukrea_mbimx27_spi_0_data = { +static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = { .chipselect = eukrea_mbimx27_spi_cs, .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs), }; #endif +static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = { + { + I2C_BOARD_INFO("tlv320aic23", 0x1a), + }, +}; + static struct platform_device *platform_devices[] __initdata = { &leds_gpio, }; +static struct imxmmc_platform_data sdhc_pdata = { + .dat3_card_detect = 1, +}; + +struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata = { + .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE, +}; + /* * system init for baseboard usage. Will be called by cpuimx27 init. * @@ -222,21 +326,52 @@ void __init eukrea_mbimx27_baseboard_init(void) mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins, ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27"); - mxc_register_device(&mxc_uart_device1, &uart_pdata[0]); - mxc_register_device(&mxc_uart_device2, &uart_pdata[1]); +#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \ + || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE) + /* SSI unit master I2S codec connected to SSI_PINS_4*/ + mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0, + MXC_AUDMUX_V1_PCR_SYN | + MXC_AUDMUX_V1_PCR_TFSDIR | + MXC_AUDMUX_V1_PCR_TCLKDIR | + MXC_AUDMUX_V1_PCR_RFSDIR | + MXC_AUDMUX_V1_PCR_RCLKDIR | + MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) | + MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) | + MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) + ); + mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4, + MXC_AUDMUX_V1_PCR_SYN | + MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0) + ); +#endif + + imx27_add_imx_uart1(&uart_pdata); + imx27_add_imx_uart2(&uart_pdata); +#if !defined(MACH_EUKREA_CPUIMX27_USEUART4) + imx27_add_imx_uart3(&uart_pdata); +#endif mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data); - mxc_register_device(&mxc_sdhc_device0, NULL); + mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata); -#if defined(CONFIG_TOUCHSCREEN_ADS7846) + i2c_register_board_info(0, eukrea_mbimx27_i2c_devices, + ARRAY_SIZE(eukrea_mbimx27_i2c_devices)); + + mxc_register_device(&imx_ssi_device0, &eukrea_mbimx27_ssi_pdata); + +#if defined(CONFIG_TOUCHSCREEN_ADS7846) \ || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) - /* SPI and ADS7846 Touchscreen controler init */ - mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT); + /* ADS7846 Touchscreen controller init */ mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN); - mxc_register_device(&mxc_spi_device0, &eukrea_mbimx27_spi_0_data); + ads7846_dev_init(); +#endif + +#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) + /* SPI_CS0 init */ + mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT); + imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data); spi_register_board_info(eukrea_mbimx27_spi_board_info, ARRAY_SIZE(eukrea_mbimx27_spi_board_info)); - ads7846_dev_init(); #endif /* Leds configuration */ @@ -244,6 +379,14 @@ void __init eukrea_mbimx27_baseboard_init(void) mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT); /* Backlight */ mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT); + gpio_request(GPIO_PORTE | 5, "backlight"); + platform_device_register(&eukrea_mbimx27_bl_dev); + /* LCD Reset */ + mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT); + gpio_request(GPIO_PORTA | 25, "lcd_enable"); + platform_device_register(&eukrea_mbimx27_lcd_powerdev); + + mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h new file mode 100644 index 000000000000..df5f522da6b3 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h @@ -0,0 +1,10 @@ +#ifndef __MACH_DMA_MX1_MX2_H__ +#define __MACH_DMA_MX1_MX2_H__ +/* + * Don't use this header in new code, it will go away when all users are + * converted to mach/dma-v1.h + */ + +#include <mach/dma-v1.h> + +#endif /* ifndef __MACH_DMA_MX1_MX2_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/mach-imx/include/mach/dma-v1.h index 7c4870bd5a21..287431cc13e5 100644 --- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h +++ b/arch/arm/mach-imx/include/mach/dma-v1.h @@ -1,5 +1,5 @@ /* - * linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h + * linux/arch/arm/mach-imx/include/mach/dma-v1.h * * i.MX DMA registration and IRQ dispatching * @@ -22,8 +22,10 @@ * MA 02110-1301, USA. */ -#ifndef __ASM_ARCH_MXC_DMA_H -#define __ASM_ARCH_MXC_DMA_H +#ifndef __MACH_DMA_V1_H__ +#define __MACH_DMA_V1_H__ + +#define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) #define IMX_DMA_CHANNELS 16 @@ -102,4 +104,4 @@ enum imx_dma_prio { int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio); -#endif /* _ASM_ARCH_MXC_DMA_H */ +#endif /* __MACH_DMA_V1_H__ */ diff --git a/arch/arm/mach-mx2/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index 1f616dcaabc9..575ff1ae85a7 100644 --- a/arch/arm/mach-mx2/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c @@ -26,20 +26,24 @@ #include <linux/mtd/physmap.h> #include <linux/platform_device.h> #include <linux/serial_8250.h> +#include <linux/usb/otg.h> +#include <linux/usb/ulpi.h> +#include <linux/fsl_devices.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/mach/map.h> -#include <mach/board-eukrea_cpuimx27.h> +#include <mach/eukrea-baseboards.h> #include <mach/common.h> #include <mach/hardware.h> -#include <mach/i2c.h> #include <mach/iomux-mx27.h> -#include <mach/imx-uart.h> #include <mach/mxc_nand.h> +#include <mach/mxc_ehci.h> +#include <mach/ulpi.h> +#include "devices-imx27.h" #include "devices.h" static int eukrea_cpuimx27_pins[] = { @@ -49,10 +53,12 @@ static int eukrea_cpuimx27_pins[] = { PE14_PF_UART1_CTS, PE15_PF_UART1_RTS, /* UART4 */ +#if defined(MACH_EUKREA_CPUIMX27_USEUART4) PB26_AF_UART4_RTS, PB28_AF_UART4_TXD, PB29_AF_UART4_CTS, PB31_AF_UART4_RXD, +#endif /* FEC */ PD0_AIN_FEC_TXD0, PD1_AIN_FEC_TXD1, @@ -76,19 +82,47 @@ static int eukrea_cpuimx27_pins[] = { PD17_PF_I2C_DATA, PD18_PF_I2C_CLK, /* SDHC2 */ +#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) PB4_PF_SD2_D0, PB5_PF_SD2_D1, PB6_PF_SD2_D2, PB7_PF_SD2_D3, PB8_PF_SD2_CMD, PB9_PF_SD2_CLK, +#endif #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) /* Quad UART's IRQ */ - GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN, - GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN, - GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN, - GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN, + GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN, + GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN, + GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN, + GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN, #endif + /* OTG */ + PC7_PF_USBOTG_DATA5, + PC8_PF_USBOTG_DATA6, + PC9_PF_USBOTG_DATA0, + PC10_PF_USBOTG_DATA2, + PC11_PF_USBOTG_DATA1, + PC12_PF_USBOTG_DATA4, + PC13_PF_USBOTG_DATA3, + PE0_PF_USBOTG_NXT, + PE1_PF_USBOTG_STP, + PE2_PF_USBOTG_DIR, + PE24_PF_USBOTG_CLK, + PE25_PF_USBOTG_DATA7, + /* USBH2 */ + PA0_PF_USBH2_CLK, + PA1_PF_USBH2_DIR, + PA2_PF_USBH2_DATA7, + PA3_PF_USBH2_NXT, + PA4_PF_USBH2_STP, + PD19_AF_USBH2_DATA4, + PD20_AF_USBH2_DATA3, + PD21_AF_USBH2_DATA6, + PD22_AF_USBH2_DATA0, + PD23_AF_USBH2_DATA2, + PD24_AF_USBH2_DATA1, + PD26_AF_USBH2_DATA5, }; static struct physmap_flash_data eukrea_cpuimx27_flash_data = { @@ -111,15 +145,12 @@ static struct platform_device eukrea_cpuimx27_nor_mtd_device = { .resource = &eukrea_cpuimx27_flash_resource, }; -static struct imxuart_platform_data uart_pdata[] = { - { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, }; -static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = { +static const struct mxc_nand_platform_data +cpuimx27_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; @@ -127,9 +158,11 @@ static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = { static struct platform_device *platform_devices[] __initdata = { &eukrea_cpuimx27_nor_mtd_device, &mxc_fec_device, + &mxc_wdt, + &mxc_w1_master_device, }; -static struct imxi2c_platform_data eukrea_cpuimx27_i2c_1_data = { +static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = { .bitrate = 100000, }; @@ -182,34 +215,83 @@ static struct platform_device serial_device = { }; #endif +#if defined(CONFIG_USB_ULPI) +static struct mxc_usbh_platform_data otg_pdata = { + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static struct mxc_usbh_platform_data usbh2_pdata = { + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; +#endif + +static struct fsl_usb2_platform_data otg_device_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_ULPI, +}; + +static int otg_mode_host; + +static int __init eukrea_cpuimx27_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", eukrea_cpuimx27_otg_mode); + static void __init eukrea_cpuimx27_init(void) { mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins, ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27"); - mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); + imx27_add_imx_uart0(&uart_pdata); - mxc_register_device(&imx27_nand_device, - &eukrea_cpuimx27_nand_board_info); + imx27_add_mxc_nand(&cpuimx27_nand_board_info); i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices, ARRAY_SIZE(eukrea_cpuimx27_i2c_devices)); - mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx27_i2c_1_data); + imx27_add_i2c_imx1(&cpuimx27_i2c1_data); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) /* SDHC2 can be used for Wifi */ mxc_register_device(&mxc_sdhc_device1, NULL); +#endif +#if defined(MACH_EUKREA_CPUIMX27_USEUART4) /* in which case UART4 is also used for Bluetooth */ - mxc_register_device(&mxc_uart_device3, &uart_pdata[1]); + imx27_add_imx_uart3(&uart_pdata); #endif #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) platform_device_register(&serial_device); #endif +#if defined(CONFIG_USB_ULPI) + if (otg_mode_host) { + otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_otg_host, &otg_pdata); + } + + usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_usbh2, &usbh2_pdata); +#endif + if (!otg_mode_host) + mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + #ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD eukrea_mbimx27_baseboard_init(); #endif diff --git a/arch/arm/mach-mx2/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c index b5710bf18b96..22a2b5d91213 100644 --- a/arch/arm/mach-mx2/mach-imx27lite.c +++ b/arch/arm/mach-imx/mach-imx27lite.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/platform_device.h> @@ -26,10 +22,9 @@ #include <asm/mach/map.h> #include <mach/hardware.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx27.h> -#include <mach/board-mx27lite.h> +#include "devices-imx27.h" #include "devices.h" static unsigned int mx27lite_pins[] = { @@ -59,7 +54,7 @@ static unsigned int mx27lite_pins[] = { PF23_AIN_FEC_TX_EN, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -71,7 +66,7 @@ static void __init mx27lite_init(void) { mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins), "imx27lite"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx27_add_imx_uart0(&uart_pdata); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c index 51f3cfd83db2..77a760cfadc0 100644 --- a/arch/arm/mach-mx1/mach-mx1ads.c +++ b/arch/arm/mach-imx/mach-mx1ads.c @@ -26,10 +26,10 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/i2c.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx1.h> #include <mach/irqs.h> +#include "devices-imx1.h" #include "devices.h" static int mx1ads_pins[] = { @@ -58,12 +58,12 @@ static int mx1ads_pins[] = { * UARTs platform data */ -static struct imxuart_platform_data uart_pdata[] = { - { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, +static const struct imxuart_platform_data uart0_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static const struct imxuart_platform_data uart1_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, }; /* @@ -75,8 +75,8 @@ static struct physmap_flash_data mx1ads_flash_data = { }; static struct resource flash_resource = { - .start = IMX_CS0_PHYS, - .end = IMX_CS0_PHYS + SZ_32M - 1, + .start = MX1_CS0_PHYS, + .end = MX1_CS0_PHYS + SZ_32M - 1, .flags = IORESOURCE_MEM, }; @@ -98,7 +98,7 @@ static struct pcf857x_platform_data pcf857x_data[] = { } }; -static struct imxi2c_platform_data mx1ads_i2c_data = { +static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = { .bitrate = 100000, }; @@ -121,8 +121,8 @@ static void __init mx1ads_init(void) ARRAY_SIZE(mx1ads_pins), "mx1ads"); /* UART */ - mxc_register_device(&imx_uart1_device, &uart_pdata[0]); - mxc_register_device(&imx_uart2_device, &uart_pdata[1]); + imx1_add_imx_uart0(&uart0_pdata); + imx1_add_imx_uart1(&uart1_pdata); /* Physmap flash */ mxc_register_device(&flash_device, &mx1ads_flash_data); @@ -131,7 +131,7 @@ static void __init mx1ads_init(void) i2c_register_board_info(0, mx1ads_i2c_devices, ARRAY_SIZE(mx1ads_i2c_devices)); - mxc_register_device(&imx_i2c_device, &mx1ads_i2c_data); + imx1_add_i2c_imx(&mx1ads_i2c_data); } static void __init mx1ads_timer_init(void) @@ -145,8 +145,8 @@ struct sys_timer mx1ads_timer = { MACHINE_START(MX1ADS, "Freescale MX1ADS") /* Maintainer: Sascha Hauer, Pengutronix */ - .phys_io = IMX_IO_PHYS, - .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, + .phys_io = MX1_IO_BASE_ADDR, + .io_pg_offst = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc, .boot_params = MX1_PHYS_OFFSET + 0x100, .map_io = mx1_map_io, .init_irq = mx1_init_irq, @@ -155,8 +155,8 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS") MACHINE_END MACHINE_START(MXLADS, "Freescale MXLADS") - .phys_io = IMX_IO_PHYS, - .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, + .phys_io = MX1_IO_BASE_ADDR, + .io_pg_offst = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc, .boot_params = MX1_PHYS_OFFSET + 0x100, .map_io = mx1_map_io, .init_irq = mx1_init_irq, diff --git a/arch/arm/mach-mx2/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index 113e58d7cb40..96d7f8189f32 100644 --- a/arch/arm/mach-mx2/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/platform_device.h> @@ -28,15 +24,49 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/mach/map.h> -#include <mach/imx-uart.h> #include <mach/imxfb.h> #include <mach/iomux-mx21.h> #include <mach/mxc_nand.h> #include <mach/mmc.h> -#include <mach/board-mx21ads.h> +#include "devices-imx21.h" #include "devices.h" +/* + * Memory-mapped I/O on MX21ADS base board + */ +#define MX21ADS_MMIO_BASE_ADDR 0xf5000000 +#define MX21ADS_MMIO_SIZE SZ_16M + +#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \ + (MX21ADS_MMIO_BASE_ADDR + (offset)) + +#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11) +#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000) +#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000) +#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000) +#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000) + +/* MX21ADS_IO_REG bit definitions */ +#define MX21ADS_IO_SD_WP 0x0001 /* read */ +#define MX21ADS_IO_TP6 0x0001 /* write */ +#define MX21ADS_IO_SW_SEL 0x0002 /* read */ +#define MX21ADS_IO_TP7 0x0002 /* write */ +#define MX21ADS_IO_RESET_E_UART 0x0004 +#define MX21ADS_IO_RESET_BASE 0x0008 +#define MX21ADS_IO_CSI_CTL2 0x0010 +#define MX21ADS_IO_CSI_CTL1 0x0020 +#define MX21ADS_IO_CSI_CTL0 0x0040 +#define MX21ADS_IO_UART1_EN 0x0080 +#define MX21ADS_IO_UART4_EN 0x0100 +#define MX21ADS_IO_LCDON 0x0200 +#define MX21ADS_IO_IRDA_EN 0x0400 +#define MX21ADS_IO_IRDA_FIR_SEL 0x0800 +#define MX21ADS_IO_IRDA_MD0_B 0x1000 +#define MX21ADS_IO_IRDA_MD1 0x2000 +#define MX21ADS_IO_LED4_ON 0x4000 +#define MX21ADS_IO_LED3_ON 0x8000 + static unsigned int mx21ads_pins[] = { /* CS8900A */ @@ -133,14 +163,13 @@ static struct platform_device mx21ads_nor_mtd_device = { .resource = &mx21ads_flash_resource, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata_rts __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -static struct imxuart_platform_data uart_norts_pdata = { +static const struct imxuart_platform_data uart_pdata_norts __initconst = { }; - static int mx21ads_fb_init(struct platform_device *pdev) { u16 tmp; @@ -227,7 +256,8 @@ static struct imxmmc_platform_data mx21ads_sdhc_pdata = { .exit = mx21ads_sdhc_exit, }; -static struct mxc_nand_platform_data mx21ads_nand_board_info = { +static const struct mxc_nand_platform_data +mx21ads_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; @@ -263,12 +293,12 @@ static void __init mx21ads_board_init(void) mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins), "mx21ads"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device2, &uart_norts_pdata); - mxc_register_device(&mxc_uart_device3, &uart_pdata); + imx21_add_imx_uart0(&uart_pdata_rts); + imx21_add_imx_uart2(&uart_pdata_norts); + imx21_add_imx_uart3(&uart_pdata_rts); mxc_register_device(&mxc_fb_device, &mx21ads_fb_data); mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata); - mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info); + imx21_add_mxc_nand(&mx21ads_nand_board_info); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/arch/arm/mach-mx2/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index b2f4e0db3fb3..e66ffaa1c26c 100644 --- a/arch/arm/mach-mx2/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -12,23 +12,25 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * This machine is known as: + * - i.MX27 3-Stack Development System + * - i.MX27 Platform Development Kit (i.MX27 PDK) */ #include <linux/platform_device.h> #include <linux/gpio.h> +#include <linux/input/matrix_keypad.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <mach/hardware.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx27.h> -#include <mach/board-mx27pdk.h> +#include "devices-imx27.h" #include "devices.h" static unsigned int mx27pdk_pins[] = { @@ -58,7 +60,7 @@ static unsigned int mx27pdk_pins[] = { PF23_AIN_FEC_TX_EN, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -66,12 +68,34 @@ static struct platform_device *platform_devices[] __initdata = { &mxc_fec_device, }; +/* + * Matrix keyboard + */ + +static const uint32_t mx27_3ds_keymap[] = { + KEY(0, 0, KEY_UP), + KEY(0, 1, KEY_DOWN), + KEY(1, 0, KEY_RIGHT), + KEY(1, 1, KEY_LEFT), + KEY(1, 2, KEY_ENTER), + KEY(2, 0, KEY_F6), + KEY(2, 1, KEY_F8), + KEY(2, 2, KEY_F9), + KEY(2, 3, KEY_F10), +}; + +static struct matrix_keymap_data mx27_3ds_keymap_data = { + .keymap = mx27_3ds_keymap, + .keymap_size = ARRAY_SIZE(mx27_3ds_keymap), +}; + static void __init mx27pdk_init(void) { mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), "mx27pdk"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx27_add_imx_uart0(&uart_pdata); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data); } static void __init mx27pdk_timer_init(void) diff --git a/arch/arm/mach-mx2/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c index 6ce323669e58..9c77da98a10e 100644 --- a/arch/arm/mach-mx2/mach-mx27ads.c +++ b/arch/arm/mach-imx/mach-mx27ads.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/platform_device.h> @@ -32,16 +28,44 @@ #include <asm/mach/time.h> #include <asm/mach/map.h> #include <mach/gpio.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx27.h> -#include <mach/board-mx27ads.h> #include <mach/mxc_nand.h> -#include <mach/i2c.h> #include <mach/imxfb.h> #include <mach/mmc.h> +#include "devices-imx27.h" #include "devices.h" +/* + * Base address of PBC controller, CS4 + */ +#define PBC_BASE_ADDRESS 0xf4300000 +#define PBC_REG_ADDR(offset) (void __force __iomem *) \ + (PBC_BASE_ADDRESS + (offset)) + +/* When the PBC address connection is fixed in h/w, defined as 1 */ +#define PBC_ADDR_SH 0 + +/* Offsets for the PBC Controller register */ +/* + * PBC Board version register offset + */ +#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH) +/* + * PBC Board control register 1 set address. + */ +#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH) +/* + * PBC Board control register 1 clear address. + */ +#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH) + +/* PBC Board Control Register 1 bit definitions */ +#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */ + +/* to determine the correct external crystal reference */ +#define CKIH_27MHZ_BIT_SET (1 << 3) + static unsigned int mx27ads_pins[] = { /* UART0 */ PE12_PF_UART1_TXD, @@ -141,7 +165,8 @@ static unsigned int mx27ads_pins[] = { PB9_PF_SD2_CLK, }; -static struct mxc_nand_platform_data mx27ads_nand_board_info = { +static const struct mxc_nand_platform_data +mx27ads_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; @@ -168,7 +193,7 @@ static struct platform_device mx27ads_nor_mtd_device = { .resource = &mx27ads_flash_resource, }; -static struct imxi2c_platform_data mx27ads_i2c_data = { +static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = { .bitrate = 100000, }; @@ -263,20 +288,8 @@ static struct platform_device *platform_devices[] __initdata = { &mxc_w1_master_device, }; -static struct imxuart_platform_data uart_pdata[] = { - { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, }; static void __init mx27ads_board_init(void) @@ -284,18 +297,18 @@ static void __init mx27ads_board_init(void) mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins), "mx27ads"); - mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); - mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); - mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); - mxc_register_device(&mxc_uart_device3, &uart_pdata[3]); - mxc_register_device(&mxc_uart_device4, &uart_pdata[4]); - mxc_register_device(&mxc_uart_device5, &uart_pdata[5]); - mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info); + imx27_add_imx_uart0(&uart_pdata); + imx27_add_imx_uart1(&uart_pdata); + imx27_add_imx_uart2(&uart_pdata); + imx27_add_imx_uart3(&uart_pdata); + imx27_add_imx_uart4(&uart_pdata); + imx27_add_imx_uart5(&uart_pdata); + imx27_add_mxc_nand(&mx27ads_nand_board_info); /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, mx27ads_i2c_devices, ARRAY_SIZE(mx27ads_i2c_devices)); - mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data); + imx27_add_i2c_imx1(&mx27ads_i2c1_data); mxc_register_device(&mxc_fb_device, &mx27ads_fb_data); mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata); @@ -342,4 +355,3 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS") .init_machine = mx27ads_board_init, .timer = &mx27ads_timer, MACHINE_END - diff --git a/arch/arm/mach-mx2/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c index bc3855992677..a3a1e452d4c5 100644 --- a/arch/arm/mach-mx2/mach-mxt_td60.c +++ b/arch/arm/mach-imx/mach-mxt_td60.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/platform_device.h> @@ -32,14 +28,13 @@ #include <asm/mach/time.h> #include <asm/mach/map.h> #include <linux/gpio.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx27.h> #include <mach/mxc_nand.h> -#include <mach/i2c.h> #include <linux/i2c/pca953x.h> #include <mach/imxfb.h> #include <mach/mmc.h> +#include "devices-imx27.h" #include "devices.h" static unsigned int mxt_td60_pins[] __initdata = { @@ -128,12 +123,13 @@ static unsigned int mxt_td60_pins[] __initdata = { PB9_PF_SD2_CLK, }; -static struct mxc_nand_platform_data mxt_td60_nand_board_info = { +static const struct mxc_nand_platform_data +mxt_td60_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; -static struct imxi2c_platform_data mxt_td60_i2c_data = { +static const struct imxi2c_platform_data mxt_td60_i2c0_data __initconst = { .bitrate = 100000, }; @@ -173,7 +169,7 @@ static struct i2c_board_info mxt_td60_i2c_devices[] = { }, }; -static struct imxi2c_platform_data mxt_td60_i2c2_data = { +static const struct imxi2c_platform_data mxt_td60_i2c1_data __initconst = { .bitrate = 100000, }; @@ -239,14 +235,8 @@ static struct platform_device *platform_devices[] __initdata = { &mxc_fec_device, }; -static struct imxuart_platform_data uart_pdata[] = { - { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, }; static void __init mxt_td60_board_init(void) @@ -254,10 +244,10 @@ static void __init mxt_td60_board_init(void) mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins), "MXT_TD60"); - mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); - mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); - mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); - mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info); + imx27_add_imx_uart0(&uart_pdata); + imx27_add_imx_uart1(&uart_pdata); + imx27_add_imx_uart2(&uart_pdata); + imx27_add_mxc_nand(&mxt_td60_nand_board_info); i2c_register_board_info(0, mxt_td60_i2c_devices, ARRAY_SIZE(mxt_td60_i2c_devices)); @@ -265,8 +255,8 @@ static void __init mxt_td60_board_init(void) i2c_register_board_info(1, mxt_td60_i2c2_devices, ARRAY_SIZE(mxt_td60_i2c2_devices)); - mxc_register_device(&mxc_i2c_device0, &mxt_td60_i2c_data); - mxc_register_device(&mxc_i2c_device1, &mxt_td60_i2c2_data); + imx27_add_i2c_imx0(&mxt_td60_i2c0_data); + imx27_add_i2c_imx1(&mxt_td60_i2c1_data); mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data); mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index a87422ed4ff5..6c92deaf468f 100644 --- a/arch/arm/mach-mx2/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -36,12 +36,7 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-mx27.h> -#include <mach/i2c.h> #include <asm/mach/time.h> -#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) -#include <mach/spi.h> -#endif -#include <mach/imx-uart.h> #include <mach/audmux.h> #include <mach/ssi.h> #include <mach/mxc_nand.h> @@ -49,11 +44,16 @@ #include <mach/mmc.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> +#include <mach/imxfb.h> +#include "devices-imx27.h" #include "devices.h" #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23) #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24) +#define SPI1_SS0 (GPIO_PORTD + 28) +#define SPI1_SS1 (GPIO_PORTD + 27) +#define SD2_CD (GPIO_PORTC + 29) static int pca100_pins[] = { /* UART1 */ @@ -68,6 +68,7 @@ static int pca100_pins[] = { PB7_PF_SD2_D3, PB8_PF_SD2_CMD, PB9_PF_SD2_CLK, + SD2_CD | GPIO_GPIO | GPIO_IN, /* FEC */ PD0_AIN_FEC_TXD0, PD1_AIN_FEC_TXD1, @@ -131,13 +132,42 @@ static int pca100_pins[] = { PD23_AF_USBH2_DATA2, PD24_AF_USBH2_DATA1, PD26_AF_USBH2_DATA5, + /* display */ + PA5_PF_LSCLK, + PA6_PF_LD0, + PA7_PF_LD1, + PA8_PF_LD2, + PA9_PF_LD3, + PA10_PF_LD4, + PA11_PF_LD5, + PA12_PF_LD6, + PA13_PF_LD7, + PA14_PF_LD8, + PA15_PF_LD9, + PA16_PF_LD10, + PA17_PF_LD11, + PA18_PF_LD12, + PA19_PF_LD13, + PA20_PF_LD14, + PA21_PF_LD15, + PA22_PF_LD16, + PA23_PF_LD17, + PA26_PF_PS, + PA28_PF_HSYNC, + PA29_PF_VSYNC, + PA31_PF_OE_ACD, + /* free GPIO */ + GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */ + GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */ + GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */ }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -static struct mxc_nand_platform_data pca100_nand_board_info = { +static const struct mxc_nand_platform_data +pca100_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; @@ -148,7 +178,7 @@ static struct platform_device *platform_devices[] __initdata = { &mxc_wdt, }; -static struct imxi2c_platform_data pca100_i2c_1_data = { +static const struct imxi2c_platform_data pca100_i2c1_data __initconst = { .bitrate = 100000, }; @@ -189,9 +219,9 @@ static struct spi_board_info pca100_spi_board_info[] __initdata = { }, }; -static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27}; +static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1}; -static struct spi_imx_master pca100_spi_0_data = { +static const struct spi_imx_master pca100_spi0_data __initconst = { .chipselect = pca100_spi_cs, .num_chipselect = ARRAY_SIZE(pca100_spi_cs), }; @@ -253,6 +283,7 @@ static struct imxmmc_platform_data sdhc_pdata = { .exit = pca100_sdhc2_exit, }; +#if defined(CONFIG_USB_ULPI) static int otg_phy_init(struct platform_device *pdev) { gpio_set_value(OTG_PHY_CS_GPIO, 0); @@ -276,6 +307,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; +#endif static struct fsl_usb2_platform_data otg_device_pdata = { .operating_mode = FSL_USB2_DR_DEVICE, @@ -297,6 +329,45 @@ static int __init pca100_otg_mode(char *options) } __setup("otg_mode=", pca100_otg_mode); +/* framebuffer info */ +static struct imx_fb_videomode pca100_fb_modes[] = { + { + .mode = { + .name = "EMERGING-ETV570G0DHU", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 39722, /* in ps (25.175 MHz) */ + .hsync_len = 30, + .left_margin = 114, + .right_margin = 16, + .vsync_len = 3, + .upper_margin = 32, + .lower_margin = 0, + }, + /* + * TFT + * Pixel pol active high + * HSYNC active low + * VSYNC active low + * use HSYNC for ACD count + * line clock disable while idle + * always enable line clock even if no data + */ + .pcr = 0xf0c08080, + .bpp = 16, + }, +}; + +static struct imx_fb_platform_data pca100_fb_data = { + .mode = pca100_fb_modes, + .num_modes = ARRAY_SIZE(pca100_fb_modes), + + .pwmr = 0x00A903FF, + .lscr1 = 0x00120300, + .dmacr = 0x00020010, +}; + static void __init pca100_init(void) { int ret; @@ -320,33 +391,24 @@ static void __init pca100_init(void) mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx27_add_imx_uart0(&uart_pdata); - mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN); mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); - mxc_register_device(&imx27_nand_device, &pca100_nand_board_info); + imx27_add_mxc_nand(&pca100_nand_board_info); /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, pca100_i2c_devices, ARRAY_SIZE(pca100_i2c_devices)); - mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data); - - mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT); - mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT); - - /* GPIO0_IRQ */ - mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN); - /* GPIO1_IRQ */ - mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN); - /* GPIO2_IRQ */ - mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN); + imx27_add_i2c_imx1(&pca100_i2c1_data); #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) + mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN); + mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN); spi_register_board_info(pca100_spi_board_info, ARRAY_SIZE(pca100_spi_board_info)); - mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data); + imx27_add_spi_imx0(&pca100_spi_0_data); #endif gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs"); @@ -372,6 +434,8 @@ static void __init pca100_init(void) mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); } + mxc_register_device(&mxc_fb_device, &pca100_fb_data); + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 36c89431679a..9212e8f37001 100644 --- a/arch/arm/mach-mx2/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -35,14 +35,12 @@ #include <mach/board-pcm038.h> #include <mach/common.h> #include <mach/hardware.h> -#include <mach/i2c.h> #include <mach/iomux-mx27.h> -#include <mach/imx-uart.h> #include <mach/mxc_nand.h> -#include <mach/spi.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> +#include "devices-imx27.h" #include "devices.h" static int pcm038_pins[] = { @@ -162,17 +160,12 @@ static struct platform_device pcm038_nor_mtd_device = { .resource = &pcm038_flash_resource, }; -static struct imxuart_platform_data uart_pdata[] = { - { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, }; -static struct mxc_nand_platform_data pcm038_nand_board_info = { +static const struct mxc_nand_platform_data +pcm038_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; @@ -192,7 +185,7 @@ static void __init pcm038_init_sram(void) mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00); } -static struct imxi2c_platform_data pcm038_i2c_1_data = { +static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = { .bitrate = 100000, }; @@ -215,7 +208,7 @@ static struct i2c_board_info pcm038_i2c_devices[] = { static int pcm038_spi_cs[] = {GPIO_PORTD + 28}; -static struct spi_imx_master pcm038_spi_0_data = { +static const struct spi_imx_master pcm038_spi0_data __initconst = { .chipselect = pcm038_spi_cs, .num_chipselect = ARRAY_SIZE(pcm038_spi_cs), }; @@ -305,18 +298,18 @@ static void __init pcm038_init(void) pcm038_init_sram(); - mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); - mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); - mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); + imx27_add_imx_uart0(&uart_pdata); + imx27_add_imx_uart1(&uart_pdata); + imx27_add_imx_uart2(&uart_pdata); mxc_gpio_mode(PE16_AF_OWIRE); - mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info); + imx27_add_mxc_nand(&pcm038_nand_board_info); /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, pcm038_i2c_devices, ARRAY_SIZE(pcm038_i2c_devices)); - mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data); + imx27_add_i2c_imx1(&pcm038_i2c1_data); /* PE18 for user-LED D40 */ mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT); @@ -326,7 +319,7 @@ static void __init pcm038_init(void) /* MC13783 IRQ */ mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN); - mxc_register_device(&mxc_spi_device0, &pcm038_spi_0_data); + imx27_add_spi_imx0(&pcm038_spi0_data); spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); diff --git a/arch/arm/mach-mx1/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c index 7587a7a12460..88bf0d1e26e6 100644 --- a/arch/arm/mach-mx1/mach-scb9328.c +++ b/arch/arm/mach-imx/mach-scb9328.c @@ -22,17 +22,17 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/irqs.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx1.h> +#include "devices-imx1.h" #include "devices.h" /* * This scb9328 has a 32MiB flash */ static struct resource flash_resource = { - .start = IMX_CS0_PHYS, - .end = IMX_CS0_PHYS + (32 * 1024 * 1024) - 1, + .start = MX1_CS0_PHYS, + .end = MX1_CS0_PHYS + (32 * 1024 * 1024) - 1, .flags = IORESOURCE_MEM, }; @@ -70,13 +70,13 @@ static struct dm9000_plat_data dm9000_platdata = { static struct resource dm9000x_resources[] = { { .name = "address area", - .start = IMX_CS5_PHYS, - .end = IMX_CS5_PHYS + 1, + .start = MX1_CS5_PHYS, + .end = MX1_CS5_PHYS + 1, .flags = IORESOURCE_MEM, /* address access */ }, { .name = "data area", - .start = IMX_CS5_PHYS + 4, - .end = IMX_CS5_PHYS + 5, + .start = MX1_CS5_PHYS + 4, + .end = MX1_CS5_PHYS + 5, .flags = IORESOURCE_MEM, /* data access */ }, { .start = IRQ_GPIOC(3), @@ -108,14 +108,13 @@ static int uart1_mxc_init(struct platform_device *pdev) ARRAY_SIZE(mxc_uart1_pins), "UART1"); } -static int uart1_mxc_exit(struct platform_device *pdev) +static void uart1_mxc_exit(struct platform_device *pdev) { mxc_gpio_release_multiple_pins(mxc_uart1_pins, ARRAY_SIZE(mxc_uart1_pins)); - return 0; } -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .init = uart1_mxc_init, .exit = uart1_mxc_exit, .flags = IMXUART_HAVE_RTSCTS, @@ -131,7 +130,7 @@ static struct platform_device *devices[] __initdata = { */ static void __init scb9328_init(void) { - mxc_register_device(&imx_uart1_device, &uart_pdata); + imx1_add_imx_uart0(&uart_pdata); printk(KERN_INFO"Scb9328: Adding devices\n"); platform_add_devices(devices, ARRAY_SIZE(devices)); diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-imx/mm-imx1.c index 7f9fc1034c08..9be92b96dc89 100644 --- a/arch/arm/mach-mx1/generic.c +++ b/arch/arm/mach-imx/mm-imx1.c @@ -3,7 +3,7 @@ * Created: april 20th, 2004 * Copyright: Synertronixx GmbH * - * Common code for i.MX machines + * Common code for i.MX1 machines * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,11 +14,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * */ #include <linux/kernel.h> #include <linux/init.h> @@ -31,23 +26,25 @@ static struct map_desc imx_io_desc[] __initdata = { { - .virtual = IMX_IO_BASE, - .pfn = __phys_to_pfn(IMX_IO_PHYS), - .length = IMX_IO_SIZE, - .type = MT_DEVICE + .virtual = MX1_IO_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX1_IO_BASE_ADDR), + .length = MX1_IO_SIZE, + .type = MT_DEVICE } }; void __init mx1_map_io(void) { mxc_set_cpu_type(MXC_CPU_MX1); - mxc_arch_reset_init(IO_ADDRESS(WDT_BASE_ADDR)); + mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR)); iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); } +int imx1_register_gpios(void); + void __init mx1_init_irq(void) { - mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); + mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR)); + imx1_register_gpios(); } - diff --git a/arch/arm/mach-mx2/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c index 64134314d012..12faeeaa0a97 100644 --- a/arch/arm/mach-mx2/mm-imx21.c +++ b/arch/arm/mach-imx/mm-imx21.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-mx2/mm-imx21.c + * arch/arm/mach-imx/mm-imx21.c * * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) * @@ -77,7 +77,10 @@ void __init mx21_map_io(void) iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc)); } +int imx21_register_gpios(void); + void __init mx21_init_irq(void) { mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR)); + imx21_register_gpios(); } diff --git a/arch/arm/mach-mx2/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c index 3366ed44cfd5..a24622957ff2 100644 --- a/arch/arm/mach-mx2/mm-imx27.c +++ b/arch/arm/mach-imx/mm-imx27.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-mx2/mm-imx27.c + * arch/arm/mach-imx/mm-imx27.c * * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) * @@ -77,7 +77,10 @@ void __init mx27_map_io(void) iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc)); } +int imx27_register_gpios(void); + void __init mx27_init_irq(void) { mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); + imx27_register_gpios(); } diff --git a/arch/arm/mach-mx1/ksym_mx1.c b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c index b09ee12a4ff0..b09ee12a4ff0 100644 --- a/arch/arm/mach-mx1/ksym_mx1.c +++ b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c diff --git a/arch/arm/mach-mx1/mx1_camera_fiq.S b/arch/arm/mach-imx/mx1-camera-fiq.S index 9c69aa65bf17..9c69aa65bf17 100644 --- a/arch/arm/mach-mx1/mx1_camera_fiq.S +++ b/arch/arm/mach-imx/mx1-camera-fiq.S diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c index f490a406d57e..f490a406d57e 100644 --- a/arch/arm/mach-mx2/pcm970-baseboard.c +++ b/arch/arm/mach-imx/pcm970-baseboard.c diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c new file mode 100644 index 000000000000..afc17ce0bb54 --- /dev/null +++ b/arch/arm/mach-imx/pm-imx27.c @@ -0,0 +1,46 @@ +/* + * i.MX27 Power Management Routines + * + * Based on Freescale's BSP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License. + */ + +#include <linux/kernel.h> +#include <linux/suspend.h> +#include <linux/io.h> +#include <mach/system.h> +#include <mach/mx27.h> + +static int mx27_suspend_enter(suspend_state_t state) +{ + u32 cscr; + switch (state) { + case PM_SUSPEND_MEM: + /* Clear MPEN and SPEN to disable MPLL/SPLL */ + cscr = __raw_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); + cscr &= 0xFFFFFFFC; + __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); + /* Executes WFI */ + arch_idle(); + break; + + default: + return -EINVAL; + } + return 0; +} + +static struct platform_suspend_ops mx27_suspend_ops = { + .enter = mx27_suspend_enter, + .valid = suspend_valid_only_mem, +}; + +static int __init mx27_pm_init(void) +{ + suspend_set_ops(&mx27_suspend_ops); + return 0; +} + +device_initcall(mx27_pm_init); diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h new file mode 100644 index 000000000000..5f96e1518aa9 --- /dev/null +++ b/arch/arm/mach-integrator/common.h @@ -0,0 +1 @@ +void integrator_reserve(void); diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index b02cfc06e0ae..8f4fb6d638f7 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c @@ -14,6 +14,7 @@ #include <linux/spinlock.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <linux/memblock.h> #include <linux/sched.h> #include <linux/smp.h> #include <linux/termios.h> @@ -30,6 +31,7 @@ #include <asm/system.h> #include <asm/leds.h> #include <asm/mach/time.h> +#include <asm/pgtable.h> static struct amba_pl010_data integrator_uart_data; @@ -119,8 +121,13 @@ static struct clk uartclk = { .rate = 14745600, }; +static struct clk dummy_apb_pclk; + static struct clk_lookup lookups[] = { - { /* UART0 */ + { /* Bus clock */ + .con_id = "apb_pclk", + .clk = &dummy_apb_pclk, + }, { /* UART0 */ .dev_id = "mb:16", .clk = &uartclk, }, { /* UART1 */ @@ -215,3 +222,13 @@ void cm_control(u32 mask, u32 set) } EXPORT_SYMBOL(cm_control); + +/* + * We need to stop things allocating the low memory; ideally we need a + * better implementation of GFP_DMA which does not assume that DMA-able + * memory starts at zero. + */ +void __init integrator_reserve(void) +{ + memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); +} diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 227cf4d05088..6ab5a03ab9d8 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -48,6 +48,8 @@ #include <asm/mach/map.h> #include <asm/mach/time.h> +#include "common.h" + /* * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx * is the (PA >> 12). @@ -502,6 +504,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator") .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc, .boot_params = 0x00000100, .map_io = ap_map_io, + .reserve = integrator_reserve, .init_irq = ap_init_irq, .timer = &ap_timer, .init_machine = ap_init, diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index cde57b2b83b5..05db40e3c4f7 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -43,6 +43,8 @@ #include <plat/timer-sp.h> +#include "common.h" + #define INTCP_PA_FLASH_BASE 0x24000000 #define INTCP_FLASH_SIZE SZ_32M @@ -601,6 +603,7 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc, .boot_params = 0x00000100, .map_io = intcp_map_io, + .reserve = integrator_reserve, .init_irq = intcp_init_irq, .timer = &cp_timer, .init_machine = intcp_init, diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index 9cef0590d5aa..6467d99fa2ee 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -505,10 +505,10 @@ void __init pci_v3_preinit(void) /* * Hook in our fault handler for PCI errors */ - hook_fault_code(4, v3_pci_fault, SIGBUS, "external abort on linefetch"); - hook_fault_code(6, v3_pci_fault, SIGBUS, "external abort on linefetch"); - hook_fault_code(8, v3_pci_fault, SIGBUS, "external abort on non-linefetch"); - hook_fault_code(10, v3_pci_fault, SIGBUS, "external abort on non-linefetch"); + hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch"); + hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch"); + hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); + hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); spin_lock_irqsave(&v3_lock, flags); diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h index 25b1da9a5035..7415e4338651 100644 --- a/arch/arm/mach-iop13xx/include/mach/memory.h +++ b/arch/arm/mach-iop13xx/include/mach/memory.h @@ -69,6 +69,4 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x) #endif /* CONFIG_ARCH_IOP13XX */ #endif /* !ASSEMBLY */ -#define PFN_TO_NID(addr) (0) - #endif diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 6d5a90813d31..773ea0c95b9f 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -987,7 +987,7 @@ void __init iop13xx_pci_init(void) iop13xx_atux_setup(); } - hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, + hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0, "imprecise external abort"); } diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c index 90771cad06f8..f797c5f538b0 100644 --- a/arch/arm/mach-ixp2000/pci.c +++ b/arch/arm/mach-ixp2000/pci.c @@ -209,7 +209,7 @@ ixp2000_pci_preinit(void) "the needed workaround has not been configured in"); #endif - hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, + hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, 0, "PCI config cycle to non-existent device"); } diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c index 4b0e598a91c9..563819a83292 100644 --- a/arch/arm/mach-ixp23xx/pci.c +++ b/arch/arm/mach-ixp23xx/pci.c @@ -229,7 +229,7 @@ void __init ixp23xx_pci_preinit(void) { ixp23xx_pci_common_init(); - hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, + hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0, "PCI config cycle to non-existent device"); *IXP23XX_PCI_ADDR_EXT = 0x0000e000; diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index e3181534c7f9..61cd4d64b985 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c @@ -348,7 +348,7 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) * This is really ugly and we need a better way of specifying * DMA-capable regions of memory. */ -void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size, +void __init ixp4xx_adjust_zones(unsigned long *zone_size, unsigned long *zhole_size) { unsigned int sz = SZ_64M >> PAGE_SHIFT; @@ -356,7 +356,7 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size, /* * Only adjust if > 64M on current system */ - if (node || (zone_size[0] <= sz)) + if (zone_size[0] <= sz) return; zone_size[1] = zone_size[0] - sz; @@ -382,7 +382,8 @@ void __init ixp4xx_pci_preinit(void) /* hook in our fault handler for PCI errors */ - hook_fault_code(16+6, abort_handler, SIGBUS, "imprecise external abort"); + hook_fault_code(16+6, abort_handler, SIGBUS, 0, + "imprecise external abort"); pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h index 98f5e5e20980..0136eaa29224 100644 --- a/arch/arm/mach-ixp4xx/include/mach/memory.h +++ b/arch/arm/mach-ixp4xx/include/mach/memory.h @@ -16,10 +16,10 @@ #if !defined(__ASSEMBLY__) && defined(CONFIG_PCI) -void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes); +void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes); -#define arch_adjust_zones(node, size, holes) \ - ixp4xx_adjust_zones(node, size, holes) +#define arch_adjust_zones(size, holes) \ + ixp4xx_adjust_zones(size, holes) #define ISA_DMA_THRESHOLD (SZ_64M - 1) #define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 29b2163b1fe3..cc25501b57fa 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -75,6 +75,13 @@ config MACH_OPENRD_CLIENT Say 'Y' here if you want your kernel to support the Marvell OpenRD Client Board. +config MACH_OPENRD_ULTIMATE + bool "Marvell OpenRD Ultimate Board" + select MACH_OPENRD + help + Say 'Y' here if you want your kernel to support the + Marvell OpenRD Ultimate Board. + config MACH_NETSPACE_V2 bool "LaCie Network Space v2 NAS Board" help @@ -87,6 +94,12 @@ config MACH_INETSPACE_V2 Say 'Y' here if you want your kernel to support the LaCie Internet Space v2 NAS. +config MACH_NETSPACE_MAX_V2 + bool "LaCie Network Space Max v2 NAS Board" + help + Say 'Y' here if you want your kernel to support the + LaCie Network Space Max v2 NAS. + config MACH_NET2BIG_V2 bool "LaCie 2Big Network v2 NAS Board" help @@ -99,6 +112,12 @@ config MACH_NET5BIG_V2 Say 'Y' here if you want your kernel to support the LaCie 5Big Network v2 NAS. +config MACH_T5325 + bool "HP t5325 Thin Client" + help + Say 'Y' here if you want your kernel to support the + HP t5325 Thin Client. + endmenu endif diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index c0cd5d362002..295d7baa6ae1 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -12,7 +12,9 @@ obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o +obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o +obj-$(CONFIG_MACH_T5325) += t5325-setup.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c index 2e69168fc699..8d03bcef5182 100644 --- a/arch/arm/mach-kirkwood/addr-map.c +++ b/arch/arm/mach-kirkwood/addr-map.c @@ -31,6 +31,8 @@ #define ATTR_DEV_CS0 0x3e #define ATTR_PCIE_IO 0xe0 #define ATTR_PCIE_MEM 0xe8 +#define ATTR_PCIE1_IO 0xd0 +#define ATTR_PCIE1_MEM 0xd8 #define ATTR_SRAM 0x01 /* @@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void) TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE); + setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE, + TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE); + setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE); /* * Setup window for NAND controller. */ - setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, + setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, TARGET_DEV_BUS, ATTR_DEV_NAND, -1); /* * Setup window for SRAM. */ - setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, + setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); /* diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 6072eaa5e66a..9dd67c7b4459 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -44,6 +44,11 @@ static struct map_desc kirkwood_io_desc[] __initdata = { .length = KIRKWOOD_PCIE_IO_SIZE, .type = MT_DEVICE, }, { + .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE, + .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE), + .length = KIRKWOOD_PCIE1_IO_SIZE, + .type = MT_DEVICE, + }, { .virtual = KIRKWOOD_REGS_VIRT_BASE, .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), .length = KIRKWOOD_REGS_SIZE, @@ -402,7 +407,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data) u32 dev, rev; kirkwood_pcie_id(&dev, &rev); - if (rev == 0) /* catch all Kirkwood Z0's */ + if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */ mvsdio_data->clock = 100000000; else mvsdio_data->clock = 200000000; @@ -847,8 +852,10 @@ int __init kirkwood_find_tclk(void) u32 dev, rev; kirkwood_pcie_id(&dev, &rev); - if (dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 || - rev == MV88F6281_REV_A1)) + + if ((dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 || + rev == MV88F6281_REV_A1)) || + (dev == MV88F6282_DEV_ID)) return 200000000; return 166666667; @@ -891,13 +898,22 @@ static char * __init kirkwood_id(void) return "MV88F6192-Z0"; else if (rev == MV88F6192_REV_A0) return "MV88F6192-A0"; + else if (rev == MV88F6192_REV_A1) + return "MV88F6192-A1"; else return "MV88F6192-Rev-Unsupported"; } else if (dev == MV88F6180_DEV_ID) { if (rev == MV88F6180_REV_A0) return "MV88F6180-Rev-A0"; + else if (rev == MV88F6180_REV_A1) + return "MV88F6180-Rev-A1"; else return "MV88F6180-Rev-Unsupported"; + } else if (dev == MV88F6282_DEV_ID) { + if (rev == MV88F6282_REV_A0) + return "MV88F6282-Rev-A0"; + else + return "MV88F6282-Rev-Unsupported"; } else { return "Device-Unknown"; } @@ -949,12 +965,14 @@ void __init kirkwood_init(void) static int __init kirkwood_clock_gate(void) { unsigned int curr = readl(CLOCK_GATING_CTRL); + u32 dev, rev; + kirkwood_pcie_id(&dev, &rev); printk(KERN_DEBUG "Gating clock of unused units\n"); printk(KERN_DEBUG "before: 0x%08x\n", curr); /* Make sure those units are accessible */ - writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL); + writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL); /* For SATA: first shutdown the phy */ if (!(kirkwood_clk_ctrl & CGC_SATA0)) { @@ -979,6 +997,18 @@ static int __init kirkwood_clock_gate(void) writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL); } + /* For PCIe 1: first shutdown the phy */ + if (dev == MV88F6282_DEV_ID) { + if (!(kirkwood_clk_ctrl & CGC_PEX1)) { + writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL); + while (1) + if (readl(PCIE1_STATUS) & 0x1) + break; + writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL); + } + } else /* keep this bit set for devices that don't have PCIe1 */ + kirkwood_clk_ctrl |= CGC_PEX1; + /* Now gate clock the required units */ writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL); printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL)); diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 05e8a8a5692e..5b2c1c18d641 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -18,6 +18,9 @@ struct mvsdio_platform_data; struct mtd_partition; struct mtd_info; +#define KW_PCIE0 (1 << 0) +#define KW_PCIE1 (1 << 1) + /* * Basic Kirkwood init functions used early by machine-setup. */ @@ -34,7 +37,7 @@ void kirkwood_ehci_init(void); void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data); void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data); void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq); -void kirkwood_pcie_init(void); +void kirkwood_pcie_init(unsigned int portmask); void kirkwood_sata_init(struct mv_sata_platform_data *sata_data); void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data); void kirkwood_spi_init(void); diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c index 39bdf4bcace9..16f6691e7c68 100644 --- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c +++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c @@ -51,6 +51,14 @@ static struct mvsdio_platform_data db88f6281_mvsdio_data = { }; static unsigned int db88f6281_mpp_config[] __initdata = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP18_NF_IO0, + MPP19_NF_IO1, MPP37_GPIO, MPP38_GPIO, 0 @@ -74,9 +82,15 @@ static void __init db88f6281_init(void) static int __init db88f6281_pci_init(void) { - if (machine_is_db88f6281_bp()) - kirkwood_pcie_init(); + if (machine_is_db88f6281_bp()) { + u32 dev, rev; + kirkwood_pcie_id(&dev, &rev); + if (dev == MV88F6282_DEV_ID) + kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0); + else + kirkwood_pcie_init(KW_PCIE0); + } return 0; } subsys_initcall(db88f6281_pci_init); diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index 418f5017c50e..aff0e1327e38 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h @@ -59,8 +59,9 @@ #define CGC_SATA1 (1 << 15) #define CGC_XOR1 (1 << 16) #define CGC_CRYPTO (1 << 17) +#define CGC_PEX1 (1 << 18) #define CGC_GE1 (1 << 19) #define CGC_TDM (1 << 20) -#define CGC_RESERVED ((1 << 18) | (0x6 << 21)) +#define CGC_RESERVED (0x6 << 21) #endif diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h index f00a0a45a67e..9da2eb59180b 100644 --- a/arch/arm/mach-kirkwood/include/mach/irqs.h +++ b/arch/arm/mach-kirkwood/include/mach/irqs.h @@ -23,6 +23,7 @@ #define IRQ_KIRKWOOD_XOR_10 7 #define IRQ_KIRKWOOD_XOR_11 8 #define IRQ_KIRKWOOD_PCIE 9 +#define IRQ_KIRKWOOD_PCIE1 10 #define IRQ_KIRKWOOD_GE00_SUM 11 #define IRQ_KIRKWOOD_GE01_SUM 15 #define IRQ_KIRKWOOD_USB 19 diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index a15cf0ee22bd..d141af4c2744 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -16,36 +16,48 @@ * Marvell Kirkwood address maps. * * phys - * e0000000 PCIe Memory space + * e0000000 PCIe #0 Memory space + * e8000000 PCIe #1 Memory space * f1000000 on-chip peripheral registers - * f2000000 PCIe I/O space - * f3000000 NAND controller address window - * f4000000 Security Accelerator SRAM + * f2000000 PCIe #0 I/O space + * f3000000 PCIe #1 I/O space + * f4000000 NAND controller address window + * f5000000 Security Accelerator SRAM * * virt phys size - * fee00000 f1000000 1M on-chip peripheral registers - * fef00000 f2000000 1M PCIe I/O space + * fed00000 f1000000 1M on-chip peripheral registers + * fee00000 f2000000 1M PCIe #0 I/O space + * fef00000 f3000000 1M PCIe #1 I/O space */ -#define KIRKWOOD_SRAM_PHYS_BASE 0xf4000000 +#define KIRKWOOD_SRAM_PHYS_BASE 0xf5000000 #define KIRKWOOD_SRAM_SIZE SZ_2K -#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000 +#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf4000000 #define KIRKWOOD_NAND_MEM_SIZE SZ_1K +#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000 +#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000 +#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00000000 +#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M + #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 -#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000 +#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000 #define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 #define KIRKWOOD_PCIE_IO_SIZE SZ_1M #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 -#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000 +#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000 #define KIRKWOOD_REGS_SIZE SZ_1M #define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 #define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000 #define KIRKWOOD_PCIE_MEM_SIZE SZ_128M +#define KIRKWOOD_PCIE1_MEM_PHYS_BASE 0xe8000000 +#define KIRKWOOD_PCIE1_MEM_BUS_BASE 0xe8000000 +#define KIRKWOOD_PCIE1_MEM_SIZE SZ_128M + /* * Register Map */ @@ -72,6 +84,9 @@ #define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) #define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70) #define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04) +#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000) +#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70) +#define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04) #define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) @@ -107,8 +122,12 @@ #define MV88F6192_DEV_ID 0x6192 #define MV88F6192_REV_Z0 0 #define MV88F6192_REV_A0 2 +#define MV88F6192_REV_A1 3 #define MV88F6180_DEV_ID 0x6180 #define MV88F6180_REV_A0 2 +#define MV88F6180_REV_A1 3 +#define MV88F6282_DEV_ID 0x6282 +#define MV88F6282_REV_A0 0 #endif diff --git a/arch/arm/mach-kirkwood/include/mach/leds-ns2.h b/arch/arm/mach-kirkwood/include/mach/leds-ns2.h new file mode 100644 index 000000000000..e21272e5f668 --- /dev/null +++ b/arch/arm/mach-kirkwood/include/mach/leds-ns2.h @@ -0,0 +1,26 @@ +/* + * arch/arm/mach-kirkwood/include/mach/leds-ns2.h + * + * Platform data structure for Network Space v2 LED driver + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_LEDS_NS2_H +#define __MACH_LEDS_NS2_H + +struct ns2_led { + const char *name; + const char *default_trigger; + unsigned cmd; + unsigned slow; +}; + +struct ns2_led_platform_data { + int num_leds; + struct ns2_led *leds; +}; + +#endif /* __MACH_LEDS_NS2_H */ diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index a5900f64e38c..065187d177c6 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -23,7 +23,8 @@ static unsigned int __init kirkwood_variant(void) kirkwood_pcie_id(&dev, &rev); - if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) + if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) || + (dev == MV88F6282_DEV_ID)) return MPP_F6281_MASK; if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0) return MPP_F6192_MASK; diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h index bc74278ed311..9b0a94d85c3e 100644 --- a/arch/arm/mach-kirkwood/mpp.h +++ b/arch/arm/mach-kirkwood/mpp.h @@ -11,7 +11,7 @@ #ifndef __KIRKWOOD_MPP_H #define __KIRKWOOD_MPP_H -#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ +#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281, _F6282) ( \ /* MPP number */ ((_num) & 0xff) | \ /* MPP select value */ (((_sel) & 0xf) << 8) | \ /* may be input signal */ ((!!(_in)) << 12) | \ @@ -19,282 +19,332 @@ /* available on F6180 */ ((!!(_F6180)) << 14) | \ /* available on F6190 */ ((!!(_F6190)) << 15) | \ /* available on F6192 */ ((!!(_F6192)) << 16) | \ - /* available on F6281 */ ((!!(_F6281)) << 17)) + /* available on F6281 */ ((!!(_F6281)) << 17) | \ + /* available on F6282 */ ((!!(_F6282)) << 18)) #define MPP_NUM(x) ((x) & 0xff) #define MPP_SEL(x) (((x) >> 8) & 0xf) - /* num sel i o 6180 6190 6192 6281 */ - -#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) -#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) - -#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) -#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) -#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) -#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) - -#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) - -#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) - -#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) - -#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) - -#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) -#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) -#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) -#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) - -#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) -#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) - -#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) -#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) -#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) -#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) -#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) -#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) -#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) -#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) -#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) - -#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) -#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) -#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) -#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) - -#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) - -#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) -#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) - -#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) - -#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) - -#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) - -#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) -#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) - -#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) - -#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) -#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) - -#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) - -#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) -#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) - -#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) - -#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) -#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) - -#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) -#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) -#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) -#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) -#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) -#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) - -#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) - -#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) -#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) -#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) - -#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) -#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) - -#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) - -#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) - -#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) - -#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 ) - -#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) + /* num sel i o 6180 6190 6192 6281 6282 */ + +#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0, 0 ) +#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0, 0 ) + +#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 ) +#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 ) +#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 ) +#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1, 0 ) +#define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 ) + +#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 ) + +#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 ) + +#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 ) + +#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 ) + +#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 ) +#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 ) + +#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 ) +#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 ) +#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 ) + +#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 ) +#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 ) +#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 ) + +#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 ) +#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 ) + +#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 ) + +#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 ) +#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 ) +#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 ) +#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) + +#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 ) + +#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 ) + +#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 ) +#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 ) +#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 ) + +#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 ) + +#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 ) +#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 ) + +#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 ) + +#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 ) + +#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 ) + +#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 ) + +#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 ) +#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 ) + +#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 ) + +#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 ) +#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 ) +#define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 ) +#define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 ) +#define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 ) +#define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 ) +#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 ) +#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP_MAX 49 diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c index 5e6f711b1c67..c6b92b42eb4e 100644 --- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c +++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c @@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void) static int __init mv88f6281gtw_ge_pci_init(void) { if (machine_is_mv88f6281gtw_ge()) - kirkwood_pcie_init(); + kirkwood_pcie_init(KW_PCIE0); return 0; } diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c index 3ae158d72681..d26bf324738b 100644 --- a/arch/arm/mach-kirkwood/netspace_v2-setup.c +++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c @@ -39,6 +39,7 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <mach/kirkwood.h> +#include <mach/leds-ns2.h> #include <plat/time.h> #include "common.h" #include "mpp.h" @@ -126,6 +127,18 @@ static void __init netspace_v2_sata_power_init(void) } if (err) pr_err("netspace_v2: failed to setup SATA0 power\n"); + + if (machine_is_netspace_max_v2()) { + err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power"); + if (err == 0) { + err = gpio_direction_output( + NETSPACE_V2_GPIO_SATA1_POWER, 1); + if (err) + gpio_free(NETSPACE_V2_GPIO_SATA1_POWER); + } + if (err) + pr_err("netspace_v2: failed to setup SATA1 power\n"); + } } /***************************************************************************** @@ -160,36 +173,12 @@ static struct platform_device netspace_v2_gpio_buttons = { * GPIO LEDs ****************************************************************************/ -/* - * The blue front LED is wired to a CPLD and can blink in relation with the - * SATA activity. - * - * The following array detail the different LED registers and the combination - * of their possible values: - * - * cmd_led | slow_led | /SATA active | LED state - * | | | - * 1 | 0 | x | off - * - | 1 | x | on - * 0 | 0 | 1 | on - * 0 | 0 | 0 | blink (rate 300ms) - */ - #define NETSPACE_V2_GPIO_RED_LED 12 -#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29 -#define NETSPACE_V2_GPIO_BLUE_LED_CMD 30 - static struct gpio_led netspace_v2_gpio_led_pins[] = { { - .name = "ns_v2:blue:sata", - .default_trigger = "default-on", - .gpio = NETSPACE_V2_GPIO_BLUE_LED_CMD, - .active_low = 1, - }, - { - .name = "ns_v2:red:fail", - .gpio = NETSPACE_V2_GPIO_RED_LED, + .name = "ns_v2:red:fail", + .gpio = NETSPACE_V2_GPIO_RED_LED, }, }; @@ -206,22 +195,33 @@ static struct platform_device netspace_v2_gpio_leds = { }, }; -static void __init netspace_v2_gpio_leds_init(void) -{ - int err; +/***************************************************************************** + * Dual-GPIO CPLD LEDs + ****************************************************************************/ - /* Configure register slow_led to allow SATA activity LED blinking */ - err = gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW, "blue LED slow"); - if (err == 0) { - err = gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0); - if (err) - gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW); - } - if (err) - pr_err("netspace_v2: failed to configure blue LED slow GPIO\n"); +#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29 +#define NETSPACE_V2_GPIO_BLUE_LED_CMD 30 - platform_device_register(&netspace_v2_gpio_leds); -} +static struct ns2_led netspace_v2_led_pins[] = { + { + .name = "ns_v2:blue:sata", + .cmd = NETSPACE_V2_GPIO_BLUE_LED_CMD, + .slow = NETSPACE_V2_GPIO_BLUE_LED_SLOW, + }, +}; + +static struct ns2_led_platform_data netspace_v2_leds_data = { + .num_leds = ARRAY_SIZE(netspace_v2_led_pins), + .leds = netspace_v2_led_pins, +}; + +static struct platform_device netspace_v2_leds = { + .name = "leds-ns2", + .id = -1, + .dev = { + .platform_data = &netspace_v2_leds_data, + }, +}; /***************************************************************************** * Timer @@ -249,17 +249,21 @@ static unsigned int netspace_v2_mpp_config[] __initdata = { MPP4_NF_IO6, MPP5_NF_IO7, MPP6_SYSRST_OUTn, - MPP8_TW_SDA, - MPP9_TW_SCK, + MPP7_GPO, /* Fan speed (bit 1) */ + MPP8_TW0_SDA, + MPP9_TW0_SCK, MPP10_UART0_TXD, MPP11_UART0_RXD, MPP12_GPO, /* Red led */ MPP14_GPIO, /* USB fuse */ MPP16_GPIO, /* SATA 0 power */ + MPP17_GPIO, /* SATA 1 power */ MPP18_NF_IO0, MPP19_NF_IO1, MPP20_SATA1_ACTn, MPP21_SATA0_ACTn, + MPP22_GPIO, /* Fan speed (bit 0) */ + MPP23_GPIO, /* Fan power */ MPP24_GPIO, /* USB mode select */ MPP25_GPIO, /* Fan rotation fail */ MPP26_GPIO, /* USB device vbus */ @@ -268,6 +272,7 @@ static unsigned int netspace_v2_mpp_config[] __initdata = { MPP30_GPIO, /* Blue led (command register) */ MPP31_GPIO, /* Board power off */ MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */ + MPP33_GPO, /* Fan speed (bit 2) */ 0 }; @@ -299,7 +304,8 @@ static void __init netspace_v2_init(void) i2c_register_board_info(0, netspace_v2_i2c_info, ARRAY_SIZE(netspace_v2_i2c_info)); - netspace_v2_gpio_leds_init(); + platform_device_register(&netspace_v2_leds); + platform_device_register(&netspace_v2_gpio_leds); platform_device_register(&netspace_v2_gpio_buttons); if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 && @@ -332,3 +338,15 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2") .timer = &netspace_v2_timer, MACHINE_END #endif + +#ifdef CONFIG_MACH_NETSPACE_MAX_V2 +MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2") + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = netspace_v2_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &netspace_v2_timer, +MACHINE_END +#endif diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c index 8a2bb0228e4f..2bd14c5079de 100644 --- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c +++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c @@ -270,8 +270,8 @@ static unsigned int net2big_v2_mpp_config[] __initdata = { MPP3_SPI_MISO, MPP6_SYSRST_OUTn, MPP7_GPO, /* Request power-off */ - MPP8_TW_SDA, - MPP9_TW_SCK, + MPP8_TW0_SDA, + MPP9_TW0_SCK, MPP10_UART0_TXD, MPP11_UART0_RXD, MPP13_GPIO, /* Rear power switch (on|auto) */ @@ -306,8 +306,8 @@ static unsigned int net5big_v2_mpp_config[] __initdata = { MPP3_SPI_MISO, MPP6_SYSRST_OUTn, MPP7_GPO, /* Request power-off */ - MPP8_TW_SDA, - MPP9_TW_SCK, + MPP8_TW0_SDA, + MPP9_TW0_SCK, MPP10_UART0_TXD, MPP11_UART0_RXD, MPP13_GPIO, /* Rear power switch (on|auto) */ @@ -315,20 +315,20 @@ static unsigned int net5big_v2_mpp_config[] __initdata = { MPP15_GPIO, /* Rear power switch (auto|off) */ MPP16_GPIO, /* SATA HDD1 power */ MPP17_GPIO, /* SATA HDD2 power */ - MPP20_GE1_0, - MPP21_GE1_1, - MPP22_GE1_2, - MPP23_GE1_3, - MPP24_GE1_4, - MPP25_GE1_5, - MPP26_GE1_6, - MPP27_GE1_7, + MPP20_GE1_TXD0, + MPP21_GE1_TXD1, + MPP22_GE1_TXD2, + MPP23_GE1_TXD3, + MPP24_GE1_RXD0, + MPP25_GE1_RXD1, + MPP26_GE1_RXD2, + MPP27_GE1_RXD3, MPP28_GPIO, /* USB enable host vbus */ MPP29_GPIO, /* CPLD extension ALE */ - MPP30_GE1_10, - MPP31_GE1_11, - MPP32_GE1_12, - MPP33_GE1_13, + MPP30_GE1_RXCTL, + MPP31_GE1_RXCLK, + MPP32_GE1_TCLKOUT, + MPP33_GE1_TXCTL, MPP34_GPIO, /* Rear Push button */ MPP35_GPIO, /* Inhibit switch power-off */ MPP36_GPIO, /* SATA HDD1 presence */ diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c index ad3f1ec33796..fd64cd2b4e0a 100644 --- a/arch/arm/mach-kirkwood/openrd-setup.c +++ b/arch/arm/mach-kirkwood/openrd-setup.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-kirkwood/openrd-setup.c * - * Marvell OpenRD (Base|Client) Board Setup + * Marvell OpenRD (Base|Client|Ultimate) Board Setup * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -73,9 +73,15 @@ static void __init openrd_init(void) kirkwood_ehci_init(); + if (machine_is_openrd_ultimate()) { + openrd_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); + openrd_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1); + } + kirkwood_ge00_init(&openrd_ge00_data); - if (machine_is_openrd_client()) + if (!machine_is_openrd_base()) kirkwood_ge01_init(&openrd_ge01_data); + kirkwood_sata_init(&openrd_sata_data); kirkwood_sdio_init(&openrd_mvsdio_data); @@ -84,8 +90,10 @@ static void __init openrd_init(void) static int __init openrd_pci_init(void) { - if (machine_is_openrd_base() || machine_is_openrd_client()) - kirkwood_pcie_init(); + if (machine_is_openrd_base() || + machine_is_openrd_client() || + machine_is_openrd_ultimate()) + kirkwood_pcie_init(KW_PCIE0); return 0; } @@ -116,3 +124,16 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board") .timer = &kirkwood_timer, MACHINE_END #endif + +#ifdef CONFIG_MACH_OPENRD_ULTIMATE +MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board") + /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */ + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = openrd_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END +#endif diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index dee1eff50d39..55e7f00836b7 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -18,29 +18,43 @@ #include <mach/bridge-regs.h> #include "common.h" +void __init kirkwood_pcie_id(u32 *dev, u32 *rev) +{ + *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE); + *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE); +} -#define PCIE_BASE ((void __iomem *)PCIE_VIRT_BASE) +struct pcie_port { + u8 root_bus_nr; + void __iomem *base; + spinlock_t conf_lock; + int irq; + struct resource res[2]; +}; -void __init kirkwood_pcie_id(u32 *dev, u32 *rev) +static int pcie_port_map[2]; +static int num_pcie_ports; + +static inline struct pcie_port *bus_to_port(struct pci_bus *bus) { - *dev = orion_pcie_dev_id(PCIE_BASE); - *rev = orion_pcie_rev(PCIE_BASE); + struct pci_sys_data *sys = bus->sysdata; + return sys->private_data; } -static int pcie_valid_config(int bus, int dev) +static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) { /* * Don't go out when trying to access -- * 1. nonexisting device on local bus * 2. where there's no device connected (no link) */ - if (bus == 0 && dev == 0) + if (bus == pp->root_bus_nr && dev == 0) return 1; - if (!orion_pcie_link_up(PCIE_BASE)) + if (!orion_pcie_link_up(pp->base)) return 0; - if (bus == 0 && dev != 1) + if (bus == pp->root_bus_nr && dev != 1) return 0; return 1; @@ -52,22 +66,22 @@ static int pcie_valid_config(int bus, int dev) * and then reading the PCIE_CONF_DATA register. Need to make sure these * transactions are atomic. */ -static DEFINE_SPINLOCK(kirkwood_pcie_lock); static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { + struct pcie_port *pp = bus_to_port(bus); unsigned long flags; int ret; - if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { + if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) { *val = 0xffffffff; return PCIBIOS_DEVICE_NOT_FOUND; } - spin_lock_irqsave(&kirkwood_pcie_lock, flags); - ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); - spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); + spin_lock_irqsave(&pp->conf_lock, flags); + ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); + spin_unlock_irqrestore(&pp->conf_lock, flags); return ret; } @@ -75,15 +89,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { + struct pcie_port *pp = bus_to_port(bus); unsigned long flags; int ret; - if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) + if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) return PCIBIOS_DEVICE_NOT_FOUND; - spin_lock_irqsave(&kirkwood_pcie_lock, flags); - ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); - spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); + spin_lock_irqsave(&pp->conf_lock, flags); + ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); + spin_unlock_irqrestore(&pp->conf_lock, flags); return ret; } @@ -93,50 +108,98 @@ static struct pci_ops pcie_ops = { .write = pcie_wr_conf, }; - -static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) +static void __init pcie0_ioresources_init(struct pcie_port *pp) { - struct resource *res; - extern unsigned int kirkwood_clk_ctrl; + pp->base = (void __iomem *)PCIE_VIRT_BASE; + pp->irq = IRQ_KIRKWOOD_PCIE; /* - * Generic PCIe unit setup. + * IORESOURCE_IO */ - orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info); + pp->res[0].name = "PCIe 0 I/O Space"; + pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE; + pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; + pp->res[0].flags = IORESOURCE_IO; /* - * Request resources. + * IORESOURCE_MEM */ - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); - if (!res) - panic("pcie_setup unable to alloc resources"); + pp->res[1].name = "PCIe 0 MEM"; + pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE; + pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; + pp->res[1].flags = IORESOURCE_MEM; +} + +static void __init pcie1_ioresources_init(struct pcie_port *pp) +{ + pp->base = (void __iomem *)PCIE1_VIRT_BASE; + pp->irq = IRQ_KIRKWOOD_PCIE1; /* * IORESOURCE_IO */ - res[0].name = "PCIe I/O Space"; - res[0].flags = IORESOURCE_IO; - res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE; - res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; - if (request_resource(&ioport_resource, &res[0])) - panic("Request PCIe IO resource failed\n"); - sys->resource[0] = &res[0]; + pp->res[0].name = "PCIe 1 I/O Space"; + pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE; + pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1; + pp->res[0].flags = IORESOURCE_IO; /* * IORESOURCE_MEM */ - res[1].name = "PCIe Memory Space"; - res[1].flags = IORESOURCE_MEM; - res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE; - res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; - if (request_resource(&iomem_resource, &res[1])) - panic("Request PCIe Memory resource failed\n"); - sys->resource[1] = &res[1]; + pp->res[1].name = "PCIe 1 MEM"; + pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE; + pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1; + pp->res[1].flags = IORESOURCE_MEM; +} + +static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) +{ + extern unsigned int kirkwood_clk_ctrl; + struct pcie_port *pp; + int index; + if (nr >= num_pcie_ports) + return 0; + + index = pcie_port_map[nr]; + printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index); + + pp = kzalloc(sizeof(*pp), GFP_KERNEL); + if (!pp) + panic("PCIe: failed to allocate pcie_port data"); + sys->private_data = pp; + pp->root_bus_nr = sys->busnr; + spin_lock_init(&pp->conf_lock); + + switch (index) { + case 0: + kirkwood_clk_ctrl |= CGC_PEX0; + pcie0_ioresources_init(pp); + break; + case 1: + kirkwood_clk_ctrl |= CGC_PEX1; + pcie1_ioresources_init(pp); + break; + default: + panic("PCIe setup: invalid controller %d", index); + } + + if (request_resource(&ioport_resource, &pp->res[0])) + panic("Request PCIe%d IO resource failed\n", index); + if (request_resource(&iomem_resource, &pp->res[1])) + panic("Request PCIe%d Memory resource failed\n", index); + + sys->resource[0] = &pp->res[0]; + sys->resource[1] = &pp->res[1]; sys->resource[2] = NULL; sys->io_offset = 0; - kirkwood_clk_ctrl |= CGC_PEX0; + /* + * Generic PCIe unit setup. + */ + orion_pcie_set_local_bus_nr(pp->base, sys->busnr); + + orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info); return 1; } @@ -163,7 +226,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys) { struct pci_bus *bus; - if (nr == 0) { + if (nr < num_pcie_ports) { bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); } else { bus = NULL; @@ -175,18 +238,37 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys) static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - return IRQ_KIRKWOOD_PCIE; + struct pcie_port *pp = bus_to_port(dev->bus); + + return pp->irq; } static struct hw_pci kirkwood_pci __initdata = { - .nr_controllers = 1, .swizzle = pci_std_swizzle, .setup = kirkwood_pcie_setup, .scan = kirkwood_pcie_scan_bus, .map_irq = kirkwood_pcie_map_irq, }; -void __init kirkwood_pcie_init(void) +static void __init add_pcie_port(int index, unsigned long base) { + printk(KERN_INFO "Kirkwood PCIe port %d: ", index); + + if (orion_pcie_link_up((void __iomem *)base)) { + printk(KERN_INFO "link up\n"); + pcie_port_map[num_pcie_ports++] = index; + } else + printk(KERN_INFO "link down, ignoring\n"); +} + +void __init kirkwood_pcie_init(unsigned int portmask) +{ + if (portmask & KW_PCIE0) + add_pcie_port(0, PCIE_VIRT_BASE); + + if (portmask & KW_PCIE1) + add_pcie_port(1, PCIE1_VIRT_BASE); + + kirkwood_pci.nr_controllers = num_pcie_ports; pci_common_init(&kirkwood_pci); } diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c index 3bf6304158f6..c34718c2cfe5 100644 --- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c @@ -71,7 +71,7 @@ static void __init rd88f6192_init(void) static int __init rd88f6192_pci_init(void) { if (machine_is_rd88f6192_nas()) - kirkwood_pcie_init(); + kirkwood_pcie_init(KW_PCIE0); return 0; } diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c index 31708ddbc83e..3d1477135e12 100644 --- a/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c @@ -107,7 +107,7 @@ static void __init rd88f6281_init(void) static int __init rd88f6281_pci_init(void) { if (machine_is_rd88f6281()) - kirkwood_pcie_init(); + kirkwood_pcie_init(KW_PCIE0); return 0; } diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c new file mode 100644 index 000000000000..d01bf89cedbe --- /dev/null +++ b/arch/arm/mach-kirkwood/t5325-setup.c @@ -0,0 +1,194 @@ +/* + * + * HP t5325 Thin Client setup + * + * Copyright (C) 2010 Martin Michlmayr <tbm@cyrius.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/spi/flash.h> +#include <linux/spi/spi.h> +#include <linux/spi/orion_spi.h> +#include <linux/i2c.h> +#include <linux/mv643xx_eth.h> +#include <linux/ata_platform.h> +#include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/kirkwood.h> +#include "common.h" +#include "mpp.h" + +struct mtd_partition hp_t5325_partitions[] = { + { + .name = "u-boot env", + .size = SZ_64K, + .offset = SZ_512K + SZ_256K, + }, + { + .name = "permanent u-boot env", + .size = SZ_64K, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "HP env", + .size = SZ_64K, + .offset = MTDPART_OFS_APPEND, + }, + { + .name = "u-boot", + .size = SZ_512K, + .offset = 0, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "SSD firmware", + .size = SZ_256K, + .offset = SZ_512K, + }, +}; + +const struct flash_platform_data hp_t5325_flash = { + .type = "mx25l8005", + .name = "spi_flash", + .parts = hp_t5325_partitions, + .nr_parts = ARRAY_SIZE(hp_t5325_partitions), +}; + +struct spi_board_info __initdata hp_t5325_spi_slave_info[] = { + { + .modalias = "m25p80", + .platform_data = &hp_t5325_flash, + .irq = -1, + }, +}; + +static struct mv643xx_eth_platform_data hp_t5325_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(8), +}; + +static struct mv_sata_platform_data hp_t5325_sata_data = { + .n_ports = 2, +}; + +static struct gpio_keys_button hp_t5325_buttons[] = { + { + .code = KEY_POWER, + .gpio = 45, + .desc = "Power", + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data hp_t5325_button_data = { + .buttons = hp_t5325_buttons, + .nbuttons = ARRAY_SIZE(hp_t5325_buttons), +}; + +static struct platform_device hp_t5325_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &hp_t5325_button_data, + } +}; + +static unsigned int hp_t5325_mpp_config[] __initdata = { + MPP0_NF_IO2, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_SPI_SCn, + MPP8_TW0_SDA, + MPP9_TW0_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_GPIO, + MPP14_GPIO, + MPP15_GPIO, + MPP16_GPIO, + MPP17_GPIO, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GPIO, + MPP21_GPIO, + MPP22_GPIO, + MPP23_GPIO, + MPP32_GPIO, + MPP33_GE1_TXCTL, + MPP39_AU_I2SBCLK, + MPP40_AU_I2SDO, + MPP41_AU_I2SLRCLK, + MPP42_AU_I2SMCLK, + MPP45_GPIO, /* Power button */ + MPP48_GPIO, /* Board power off */ + 0 +}; + +#define HP_T5325_GPIO_POWER_OFF 48 + +static void hp_t5325_power_off(void) +{ + gpio_set_value(HP_T5325_GPIO_POWER_OFF, 1); +} + +static void __init hp_t5325_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_init(); + kirkwood_mpp_conf(hp_t5325_mpp_config); + + kirkwood_uart0_init(); + spi_register_board_info(hp_t5325_spi_slave_info, + ARRAY_SIZE(hp_t5325_spi_slave_info)); + kirkwood_spi_init(); + kirkwood_i2c_init(); + kirkwood_ge00_init(&hp_t5325_ge00_data); + kirkwood_sata_init(&hp_t5325_sata_data); + kirkwood_ehci_init(); + platform_device_register(&hp_t5325_button_device); + + if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 && + gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0) + pm_power_off = hp_t5325_power_off; + else + pr_err("t5325: failed to configure power-off GPIO\n"); +} + +static int __init hp_t5325_pci_init(void) +{ + if (machine_is_t5325()) + kirkwood_pcie_init(KW_PCIE0); + + return 0; +} +subsys_initcall(hp_t5325_pci_init); + +MACHINE_START(T5325, "HP t5325 Thin Client") + /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */ + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = hp_t5325_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c index 2830f0fe80e0..a5bd7fde04a9 100644 --- a/arch/arm/mach-kirkwood/ts219-setup.c +++ b/arch/arm/mach-kirkwood/ts219-setup.c @@ -74,8 +74,8 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = { MPP3_SPI_MISO, MPP4_SATA1_ACTn, MPP5_SATA0_ACTn, - MPP8_TW_SDA, - MPP9_TW_SCK, + MPP8_TW0_SDA, + MPP9_TW0_SCK, MPP10_UART0_TXD, MPP11_UART0_RXD, MPP13_UART1_TXD, /* PIC controller */ @@ -83,6 +83,7 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = { MPP15_GPIO, /* USB Copy button */ MPP16_GPIO, /* Reset button */ MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ + MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */ 0 }; @@ -110,10 +111,10 @@ static void __init qnap_ts219_init(void) static int __init ts219_pci_init(void) { - if (machine_is_ts219()) - kirkwood_pcie_init(); + if (machine_is_ts219()) + kirkwood_pcie_init(KW_PCIE0); - return 0; + return 0; } subsys_initcall(ts219_pci_init); diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c index de49c2d9e74b..2e14afef07a2 100644 --- a/arch/arm/mach-kirkwood/ts41x-setup.c +++ b/arch/arm/mach-kirkwood/ts41x-setup.c @@ -2,7 +2,7 @@ * * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup * - * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com> + * Copyright (C) 2009-2010 Martin Michlmayr <tbm@cyrius.com> * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com> * * This program is free software; you can redistribute it and/or @@ -17,6 +17,7 @@ #include <linux/i2c.h> #include <linux/mv643xx_eth.h> #include <linux/ata_platform.h> +#include <linux/gpio.h> #include <linux/gpio_keys.h> #include <linux/input.h> #include <asm/mach-types.h> @@ -26,6 +27,8 @@ #include "mpp.h" #include "tsx1x-common.h" +#define QNAP_TS41X_JUMPER_JP1 45 + static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = { I2C_BOARD_INFO("s35390a", 0x30), }; @@ -78,31 +81,31 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = { MPP3_SPI_MISO, MPP6_SYSRST_OUTn, MPP7_PEX_RST_OUTn, - MPP8_TW_SDA, - MPP9_TW_SCK, + MPP8_TW0_SDA, + MPP9_TW0_SCK, MPP10_UART0_TXD, MPP11_UART0_RXD, MPP13_UART1_TXD, /* PIC controller */ MPP14_UART1_RXD, /* PIC controller */ MPP15_SATA0_ACTn, MPP16_SATA1_ACTn, - MPP20_GE1_0, - MPP21_GE1_1, - MPP22_GE1_2, - MPP23_GE1_3, - MPP24_GE1_4, - MPP25_GE1_5, - MPP26_GE1_6, - MPP27_GE1_7, - MPP30_GE1_10, - MPP31_GE1_11, - MPP32_GE1_12, - MPP33_GE1_13, + MPP20_GE1_TXD0, + MPP21_GE1_TXD1, + MPP22_GE1_TXD2, + MPP23_GE1_TXD3, + MPP24_GE1_RXD0, + MPP25_GE1_RXD1, + MPP26_GE1_RXD2, + MPP27_GE1_RXD3, + MPP30_GE1_RXCTL, + MPP31_GE1_RXCLK, + MPP32_GE1_TCLKOUT, + MPP33_GE1_TXCTL, MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ MPP37_GPIO, /* Reset button */ MPP43_GPIO, /* USB Copy button */ MPP44_GPIO, /* Board ID: 0: TS-419U, 1: TS-419 */ - MPP45_GPIO, /* JP1: 0: console, 1: LCD */ + MPP45_GPIO, /* JP1: 0: LCD, 1: serial console */ MPP46_GPIO, /* External SATA HDD1 error indicator */ MPP47_GPIO, /* External SATA HDD2 error indicator */ MPP48_GPIO, /* External SATA HDD3 error indicator */ @@ -131,12 +134,14 @@ static void __init qnap_ts41x_init(void) pm_power_off = qnap_tsx1x_power_off; + if (gpio_request(QNAP_TS41X_JUMPER_JP1, "JP1") == 0) + gpio_export(QNAP_TS41X_JUMPER_JP1, 0); } static int __init ts41x_pci_init(void) { if (machine_is_ts41x()) - kirkwood_pcie_init(); + kirkwood_pcie_init(KW_PCIE0); return 0; } diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c index 78499667eb7b..5fcd082a17f9 100644 --- a/arch/arm/mach-ks8695/pci.c +++ b/arch/arm/mach-ks8695/pci.c @@ -268,8 +268,8 @@ static void __init ks8695_pci_preinit(void) __raw_writel(0, KS8695_PCI_VA + KS8695_PIOBAC); /* hook in fault handlers */ - hook_fault_code(8, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch"); - hook_fault_code(10, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch"); + hook_fault_code(8, ks8695_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); + hook_fault_code(10, ks8695_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); } static void ks8695_show_pciregs(void) diff --git a/arch/arm/mach-l7200/Makefile b/arch/arm/mach-l7200/Makefile deleted file mode 100644 index 4bd8ebd70e7b..000000000000 --- a/arch/arm/mach-l7200/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# Object file lists. - -obj-y := core.o -obj-m := -obj-n := -obj- := - diff --git a/arch/arm/mach-l7200/Makefile.boot b/arch/arm/mach-l7200/Makefile.boot deleted file mode 100644 index 6c72ecbe6b64..000000000000 --- a/arch/arm/mach-l7200/Makefile.boot +++ /dev/null @@ -1,2 +0,0 @@ - zreladdr-y := 0xf0008000 - diff --git a/arch/arm/mach-l7200/core.c b/arch/arm/mach-l7200/core.c deleted file mode 100644 index 50d23246d4f0..000000000000 --- a/arch/arm/mach-l7200/core.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * linux/arch/arm/mm/mm-lusl7200.c - * - * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) - * - * Extra MM routines for L7200 architecture - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/irq.h> -#include <linux/device.h> - -#include <asm/types.h> -#include <asm/irq.h> -#include <asm/mach-types.h> -#include <mach/hardware.h> -#include <asm/page.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -/* - * IRQ base register - */ -#define IRQ_BASE (IO_BASE_2 + 0x1000) - -/* - * Normal IRQ registers - */ -#define IRQ_STATUS (*(volatile unsigned long *) (IRQ_BASE + 0x000)) -#define IRQ_RAWSTATUS (*(volatile unsigned long *) (IRQ_BASE + 0x004)) -#define IRQ_ENABLE (*(volatile unsigned long *) (IRQ_BASE + 0x008)) -#define IRQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x00c)) -#define IRQ_SOFT (*(volatile unsigned long *) (IRQ_BASE + 0x010)) -#define IRQ_SOURCESEL (*(volatile unsigned long *) (IRQ_BASE + 0x018)) - -/* - * Fast IRQ registers - */ -#define FIQ_STATUS (*(volatile unsigned long *) (IRQ_BASE + 0x100)) -#define FIQ_RAWSTATUS (*(volatile unsigned long *) (IRQ_BASE + 0x104)) -#define FIQ_ENABLE (*(volatile unsigned long *) (IRQ_BASE + 0x108)) -#define FIQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x10c)) -#define FIQ_SOFT (*(volatile unsigned long *) (IRQ_BASE + 0x110)) -#define FIQ_SOURCESEL (*(volatile unsigned long *) (IRQ_BASE + 0x118)) - -static void l7200_mask_irq(unsigned int irq) -{ - IRQ_ENABLECLEAR = 1 << irq; -} - -static void l7200_unmask_irq(unsigned int irq) -{ - IRQ_ENABLE = 1 << irq; -} - -static struct irq_chip l7200_irq_chip = { - .ack = l7200_mask_irq, - .mask = l7200_mask_irq, - .unmask = l7200_unmask_irq -}; - -static void __init l7200_init_irq(void) -{ - int irq; - - IRQ_ENABLECLEAR = 0xffffffff; /* clear all interrupt enables */ - FIQ_ENABLECLEAR = 0xffffffff; /* clear all fast interrupt enables */ - - for (irq = 0; irq < NR_IRQS; irq++) { - set_irq_chip(irq, &l7200_irq_chip); - set_irq_flags(irq, IRQF_VALID); - set_irq_handler(irq, handle_level_irq); - } - - init_FIQ(); -} - -static struct map_desc l7200_io_desc[] __initdata = { - { IO_BASE, IO_START, IO_SIZE, MT_DEVICE }, - { IO_BASE_2, IO_START_2, IO_SIZE_2, MT_DEVICE }, - { AUX_BASE, AUX_START, AUX_SIZE, MT_DEVICE }, - { FLASH1_BASE, FLASH1_START, FLASH1_SIZE, MT_DEVICE }, - { FLASH2_BASE, FLASH2_START, FLASH2_SIZE, MT_DEVICE } -}; - -static void __init l7200_map_io(void) -{ - iotable_init(l7200_io_desc, ARRAY_SIZE(l7200_io_desc)); -} - -MACHINE_START(L7200, "LinkUp Systems L7200") - /* Maintainer: Steve Hill / Scott McConnell */ - .phys_io = 0x80040000, - .io_pg_offst = ((0xd0000000) >> 18) & 0xfffc, - .map_io = l7200_map_io, - .init_irq = l7200_init_irq, -MACHINE_END - diff --git a/arch/arm/mach-l7200/include/mach/aux_reg.h b/arch/arm/mach-l7200/include/mach/aux_reg.h deleted file mode 100644 index 4671558cdd51..000000000000 --- a/arch/arm/mach-l7200/include/mach/aux_reg.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * arch/arm/mach-l7200/include/mach/aux_reg.h - * - * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) - * - * Changelog: - * 08-02-2000 SJH Created file - */ -#ifndef _ASM_ARCH_AUXREG_H -#define _ASM_ARCH_AUXREG_H - -#include <mach/hardware.h> - -#define l7200aux_reg *((volatile unsigned int *) (AUX_BASE)) - -/* - * Auxillary register values - */ -#define AUX_CLEAR 0x00000000 -#define AUX_DIAG_LED_ON 0x00000002 -#define AUX_RTS_UART1 0x00000004 -#define AUX_DTR_UART1 0x00000008 -#define AUX_KBD_COLUMN_12_HIGH 0x00000010 -#define AUX_KBD_COLUMN_12_OFF 0x00000020 -#define AUX_KBD_COLUMN_13_HIGH 0x00000040 -#define AUX_KBD_COLUMN_13_OFF 0x00000080 - -#endif diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S deleted file mode 100644 index b69ed344c7c9..000000000000 --- a/arch/arm/mach-l7200/include/mach/debug-macro.S +++ /dev/null @@ -1,40 +0,0 @@ -/* arch/arm/mach-l7200/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - .equ io_virt, IO_BASE - .equ io_phys, IO_START - - .macro addruart, rx, tmp - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ MMU enabled? - moveq \rx, #io_phys @ physical base address - movne \rx, #io_virt @ virtual address - add \rx, \rx, #0x00044000 @ UART1 -@ add \rx, \rx, #0x00045000 @ UART2 - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #0x0] @ UARTDR - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #0x18] @ UARTFLG - tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full - bne 1001b - .endm - - .macro busyuart,rd,rx -1001: ldr \rd, [\rx, #0x18] @ UARTFLG - tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy - bne 1001b - .endm diff --git a/arch/arm/mach-l7200/include/mach/entry-macro.S b/arch/arm/mach-l7200/include/mach/entry-macro.S deleted file mode 100644 index 1726d91fc1d3..000000000000 --- a/arch/arm/mach-l7200/include/mach/entry-macro.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/mach-l7200/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for L7200-based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <mach/hardware.h> - - .equ irq_base_addr, IO_BASE_2 - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov \irqstat, #irq_base_addr @ Virt addr IRQ regs - add \irqstat, \irqstat, #0x00001000 @ Status reg - ldr \irqstat, [\irqstat, #0] @ get interrupts - mov \irqnr, #0 -1001: tst \irqstat, #1 - addeq \irqnr, \irqnr, #1 - moveq \irqstat, \irqstat, lsr #1 - tsteq \irqnr, #32 - beq 1001b - teq \irqnr, #32 - .endm - diff --git a/arch/arm/mach-l7200/include/mach/gp_timers.h b/arch/arm/mach-l7200/include/mach/gp_timers.h deleted file mode 100644 index 2b7086a26b81..000000000000 --- a/arch/arm/mach-l7200/include/mach/gp_timers.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * arch/arm/mach-l7200/include/mach/gp_timers.h - * - * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) - * - * Changelog: - * 07-28-2000 SJH Created file - * 08-02-2000 SJH Used structure for registers - */ -#ifndef _ASM_ARCH_GPTIMERS_H -#define _ASM_ARCH_GPTIMERS_H - -#include <mach/hardware.h> - -/* - * Layout of L7200 general purpose timer registers - */ -struct GPT_Regs { - unsigned int TIMERLOAD; - unsigned int TIMERVALUE; - unsigned int TIMERCONTROL; - unsigned int TIMERCLEAR; -}; - -#define GPT_BASE (IO_BASE_2 + 0x3000) -#define l7200_timer1_regs ((volatile struct GPT_Regs *) (GPT_BASE)) -#define l7200_timer2_regs ((volatile struct GPT_Regs *) (GPT_BASE + 0x20)) - -/* - * General register values - */ -#define GPT_PRESCALE_1 0x00000000 -#define GPT_PRESCALE_16 0x00000004 -#define GPT_PRESCALE_256 0x00000008 -#define GPT_MODE_FREERUN 0x00000000 -#define GPT_MODE_PERIODIC 0x00000040 -#define GPT_ENABLE 0x00000080 -#define GPT_BZTOG 0x00000100 -#define GPT_BZMOD 0x00000200 -#define GPT_LOAD_MASK 0x0000ffff - -#endif diff --git a/arch/arm/mach-l7200/include/mach/gpio.h b/arch/arm/mach-l7200/include/mach/gpio.h deleted file mode 100644 index c7b0a5d7b8bb..000000000000 --- a/arch/arm/mach-l7200/include/mach/gpio.h +++ /dev/null @@ -1,105 +0,0 @@ -/****************************************************************************/ -/* - * arch/arm/mach-l7200/include/mach/gpio.h - * - * Registers and helper functions for the L7200 Link-Up Systems - * GPIO. - * - * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -/****************************************************************************/ - -#define GPIO_OFF 0x00005000 /* Offset from IO_START to the GPIO reg's. */ - -/* IO_START and IO_BASE are defined in hardware.h */ - -#define GPIO_START (IO_START_2 + GPIO_OFF) /* Physical addr of the GPIO reg. */ -#define GPIO_BASE (IO_BASE_2 + GPIO_OFF) /* Virtual addr of the GPIO reg. */ - -/* Offsets from the start of the GPIO for all the registers. */ -#define PADR_OFF 0x000 -#define PADDR_OFF 0x004 -#define PASBSR_OFF 0x008 -#define PAEENR_OFF 0x00c -#define PAESNR_OFF 0x010 -#define PAESTR_OFF 0x014 -#define PAIMR_OFF 0x018 -#define PAINT_OFF 0x01c - -#define PBDR_OFF 0x020 -#define PBDDR_OFF 0x024 -#define PBSBSR_OFF 0x028 -#define PBIMR_OFF 0x038 -#define PBINT_OFF 0x03c - -#define PCDR_OFF 0x040 -#define PCDDR_OFF 0x044 -#define PCSBSR_OFF 0x048 -#define PCIMR_OFF 0x058 -#define PCINT_OFF 0x05c - -#define PDDR_OFF 0x060 -#define PDDDR_OFF 0x064 -#define PDSBSR_OFF 0x068 -#define PDEENR_OFF 0x06c -#define PDESNR_OFF 0x070 -#define PDESTR_OFF 0x074 -#define PDIMR_OFF 0x078 -#define PDINT_OFF 0x07c - -#define PEDR_OFF 0x080 -#define PEDDR_OFF 0x084 -#define PESBSR_OFF 0x088 -#define PEEENR_OFF 0x08c -#define PEESNR_OFF 0x090 -#define PEESTR_OFF 0x094 -#define PEIMR_OFF 0x098 -#define PEINT_OFF 0x09c - -/* Define the GPIO registers for use by device drivers and the kernel. */ -#define PADR (*(volatile unsigned long *)(GPIO_BASE+PADR_OFF)) -#define PADDR (*(volatile unsigned long *)(GPIO_BASE+PADDR_OFF)) -#define PASBSR (*(volatile unsigned long *)(GPIO_BASE+PASBSR_OFF)) -#define PAEENR (*(volatile unsigned long *)(GPIO_BASE+PAEENR_OFF)) -#define PAESNR (*(volatile unsigned long *)(GPIO_BASE+PAESNR_OFF)) -#define PAESTR (*(volatile unsigned long *)(GPIO_BASE+PAESTR_OFF)) -#define PAIMR (*(volatile unsigned long *)(GPIO_BASE+PAIMR_OFF)) -#define PAINT (*(volatile unsigned long *)(GPIO_BASE+PAINT_OFF)) - -#define PBDR (*(volatile unsigned long *)(GPIO_BASE+PBDR_OFF)) -#define PBDDR (*(volatile unsigned long *)(GPIO_BASE+PBDDR_OFF)) -#define PBSBSR (*(volatile unsigned long *)(GPIO_BASE+PBSBSR_OFF)) -#define PBIMR (*(volatile unsigned long *)(GPIO_BASE+PBIMR_OFF)) -#define PBINT (*(volatile unsigned long *)(GPIO_BASE+PBINT_OFF)) - -#define PCDR (*(volatile unsigned long *)(GPIO_BASE+PCDR_OFF)) -#define PCDDR (*(volatile unsigned long *)(GPIO_BASE+PCDDR_OFF)) -#define PCSBSR (*(volatile unsigned long *)(GPIO_BASE+PCSBSR_OFF)) -#define PCIMR (*(volatile unsigned long *)(GPIO_BASE+PCIMR_OFF)) -#define PCINT (*(volatile unsigned long *)(GPIO_BASE+PCINT_OFF)) - -#define PDDR (*(volatile unsigned long *)(GPIO_BASE+PDDR_OFF)) -#define PDDDR (*(volatile unsigned long *)(GPIO_BASE+PDDDR_OFF)) -#define PDSBSR (*(volatile unsigned long *)(GPIO_BASE+PDSBSR_OFF)) -#define PDEENR (*(volatile unsigned long *)(GPIO_BASE+PDEENR_OFF)) -#define PDESNR (*(volatile unsigned long *)(GPIO_BASE+PDESNR_OFF)) -#define PDESTR (*(volatile unsigned long *)(GPIO_BASE+PDESTR_OFF)) -#define PDIMR (*(volatile unsigned long *)(GPIO_BASE+PDIMR_OFF)) -#define PDINT (*(volatile unsigned long *)(GPIO_BASE+PDINT_OFF)) - -#define PEDR (*(volatile unsigned long *)(GPIO_BASE+PEDR_OFF)) -#define PEDDR (*(volatile unsigned long *)(GPIO_BASE+PEDDR_OFF)) -#define PESBSR (*(volatile unsigned long *)(GPIO_BASE+PESBSR_OFF)) -#define PEEENR (*(volatile unsigned long *)(GPIO_BASE+PEEENR_OFF)) -#define PEESNR (*(volatile unsigned long *)(GPIO_BASE+PEESNR_OFF)) -#define PEESTR (*(volatile unsigned long *)(GPIO_BASE+PEESTR_OFF)) -#define PEIMR (*(volatile unsigned long *)(GPIO_BASE+PEIMR_OFF)) -#define PEINT (*(volatile unsigned long *)(GPIO_BASE+PEINT_OFF)) - -#define VEE_EN 0x02 -#define BACKLIGHT_EN 0x04 diff --git a/arch/arm/mach-l7200/include/mach/hardware.h b/arch/arm/mach-l7200/include/mach/hardware.h deleted file mode 100644 index c31909cfc254..000000000000 --- a/arch/arm/mach-l7200/include/mach/hardware.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * arch/arm/mach-l7200/include/mach/hardware.h - * - * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net) - * Steve Hill (sjhill@cotw.com) - * - * This file contains the hardware definitions for the - * LinkUp Systems L7200 SOC development board. - * - * Changelog: - * 02-01-2000 RS Created L7200 version, derived from rpc code - * 03-21-2000 SJH Cleaned up file - * 04-21-2000 RS Changed mapping of I/O in virtual space - * 04-25-2000 SJH Removed unused symbols and such - * 05-05-2000 SJH Complete rewrite - * 07-31-2000 SJH Added undocumented debug auxillary port to - * get at last two columns for keyboard driver - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* Hardware addresses of major areas. - * *_START is the physical address - * *_SIZE is the size of the region - * *_BASE is the virtual address - */ -#define RAM_START 0xf0000000 -#define RAM_SIZE 0x02000000 -#define RAM_BASE 0xc0000000 - -#define IO_START 0x80000000 /* I/O */ -#define IO_SIZE 0x01000000 -#define IO_BASE 0xd0000000 - -#define IO_START_2 0x90000000 /* I/O */ -#define IO_SIZE_2 0x01000000 -#define IO_BASE_2 0xd1000000 - -#define AUX_START 0x1a000000 /* AUX PORT */ -#define AUX_SIZE 0x01000000 -#define AUX_BASE 0xd2000000 - -#define FLASH1_START 0x00000000 /* FLASH BANK 1 */ -#define FLASH1_SIZE 0x01000000 -#define FLASH1_BASE 0xd3000000 - -#define FLASH2_START 0x10000000 /* FLASH BANK 2 */ -#define FLASH2_SIZE 0x01000000 -#define FLASH2_BASE 0xd4000000 - -#define ISA_START 0x20000000 /* ISA */ -#define ISA_SIZE 0x20000000 -#define ISA_BASE 0xe0000000 - -#define PCIO_BASE IO_BASE - -#endif diff --git a/arch/arm/mach-l7200/include/mach/io.h b/arch/arm/mach-l7200/include/mach/io.h deleted file mode 100644 index a770a89fb708..000000000000 --- a/arch/arm/mach-l7200/include/mach/io.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-l7200/include/mach/io.h - * - * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) - * - * Changelog: - * 03-21-2000 SJH Created from arch/arm/mach-nexuspci/include/mach/io.h - * 08-31-2000 SJH Added in IO functions necessary for new drivers - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * There are not real ISA nor PCI buses, so we fake it. - */ -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) - -#endif diff --git a/arch/arm/mach-l7200/include/mach/irqs.h b/arch/arm/mach-l7200/include/mach/irqs.h deleted file mode 100644 index 7edffd713c5b..000000000000 --- a/arch/arm/mach-l7200/include/mach/irqs.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * arch/arm/mach-l7200/include/mach/irqs.h - * - * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net) - * Steve Hill (sjhill@cotw.com) - * - * Changelog: - * 01-02-2000 RS Create l7200 version - * 03-28-2000 SJH Removed unused interrupt - * 07-28-2000 SJH Added pseudo-keyboard interrupt - */ - -/* - * NOTE: The second timer (Timer 2) is used as the keyboard - * interrupt when the keyboard driver is enabled. - */ - -#define NR_IRQS 32 - -#define IRQ_STWDOG 0 /* Watchdog timer */ -#define IRQ_PROG 1 /* Programmable interrupt */ -#define IRQ_DEBUG_RX 2 /* Comm Rx debug */ -#define IRQ_DEBUG_TX 3 /* Comm Tx debug */ -#define IRQ_GCTC1 4 /* Timer 1 */ -#define IRQ_GCTC2 5 /* Timer 2 / Keyboard */ -#define IRQ_DMA 6 /* DMA controller */ -#define IRQ_CLCD 7 /* Color LCD controller */ -#define IRQ_SM_RX 8 /* Smart card */ -#define IRQ_SM_TX 9 /* Smart cart */ -#define IRQ_SM_RST 10 /* Smart card */ -#define IRQ_SIB 11 /* Serial Interface Bus */ -#define IRQ_MMC 12 /* MultiMediaCard */ -#define IRQ_SSP1 13 /* Synchronous Serial Port 1 */ -#define IRQ_SSP2 14 /* Synchronous Serial Port 1 */ -#define IRQ_SPI 15 /* SPI slave */ -#define IRQ_UART_1 16 /* UART 1 */ -#define IRQ_UART_2 17 /* UART 2 */ -#define IRQ_IRDA 18 /* IRDA */ -#define IRQ_RTC_TICK 19 /* Real Time Clock tick */ -#define IRQ_RTC_ALARM 20 /* Real Time Clock alarm */ -#define IRQ_GPIO 21 /* General Purpose IO */ -#define IRQ_GPIO_DMA 22 /* General Purpose IO, DMA */ -#define IRQ_M2M 23 /* Memory to memory DMA */ -#define IRQ_RESERVED 24 /* RESERVED, don't use */ -#define IRQ_INTF 25 /* External active low interrupt */ -#define IRQ_INT0 26 /* External active low interrupt */ -#define IRQ_INT1 27 /* External active low interrupt */ -#define IRQ_INT2 28 /* External active low interrupt */ -#define IRQ_UCB1200 29 /* Interrupt generated by UCB1200*/ -#define IRQ_BAT_LO 30 /* Low batery or external power */ -#define IRQ_MEDIA_CHG 31 /* Media change interrupt */ - -/* - * This is the offset of the FIQ "IRQ" numbers - */ -#define FIQ_START 64 diff --git a/arch/arm/mach-l7200/include/mach/memory.h b/arch/arm/mach-l7200/include/mach/memory.h deleted file mode 100644 index 9fb40ed2f03b..000000000000 --- a/arch/arm/mach-l7200/include/mach/memory.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * arch/arm/mach-l7200/include/mach/memory.h - * - * Copyright (c) 2000 Steve Hill (sjhill@cotw.com) - * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net) - * - * Changelog: - * 03-13-2000 SJH Created - * 04-13-2000 RS Changed bus macros for new addr - * 05-03-2000 SJH Removed bus macros and fixed virt_to_phys macro - */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Physical DRAM offset on the L7200 SDB. - */ -#define PHYS_OFFSET UL(0xf0000000) - -/* - * Cache flushing area - ROM - */ -#define FLUSH_BASE_PHYS 0x40000000 -#define FLUSH_BASE 0xdf000000 - -#endif diff --git a/arch/arm/mach-l7200/include/mach/pmpcon.h b/arch/arm/mach-l7200/include/mach/pmpcon.h deleted file mode 100644 index 3959871e8361..000000000000 --- a/arch/arm/mach-l7200/include/mach/pmpcon.h +++ /dev/null @@ -1,46 +0,0 @@ -/****************************************************************************/ -/* - * arch/arm/mach-l7200/include/mach/pmpcon.h - * - * Registers and helper functions for the L7200 Link-Up Systems - * DC/DC converter register. - * - * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -/****************************************************************************/ - -#define PMPCON_OFF 0x00006000 /* Offset from IO_START_2. */ - -/* IO_START_2 and IO_BASE_2 are defined in hardware.h */ - -#define PMPCON_START (IO_START_2 + PMPCON_OFF) /* Physical address of reg. */ -#define PMPCON_BASE (IO_BASE_2 + PMPCON_OFF) /* Virtual address of reg. */ - - -#define PMPCON (*(volatile unsigned int *)(PMPCON_BASE)) - -#define PWM2_50CYCLE 0x800 -#define CONTRAST 0x9 - -#define PWM1H (CONTRAST) -#define PWM1L (CONTRAST << 4) - -#define PMPCON_VALUE (PWM2_50CYCLE | PWM1L | PWM1H) - -/* PMPCON = 0x811; // too light and fuzzy - * PMPCON = 0x844; - * PMPCON = 0x866; // better color poor depth - * PMPCON = 0x888; // Darker but better depth - * PMPCON = 0x899; // Darker even better depth - * PMPCON = 0x8aa; // too dark even better depth - * PMPCON = 0X8cc; // Way too dark - */ - -/* As CONTRAST value increases the greater the depth perception and - * the darker the colors. - */ diff --git a/arch/arm/mach-l7200/include/mach/pmu.h b/arch/arm/mach-l7200/include/mach/pmu.h deleted file mode 100644 index a2da7aedf208..000000000000 --- a/arch/arm/mach-l7200/include/mach/pmu.h +++ /dev/null @@ -1,125 +0,0 @@ -/****************************************************************************/ -/* - * arch/arm/mach-l7200/include/mach/pmu.h - * - * Registers and helper functions for the L7200 Link-Up Systems - * Power Management Unit (PMU). - * - * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -/****************************************************************************/ - -#define PMU_OFF 0x00050000 /* Offset from IO_START to the PMU registers. */ - -/* IO_START and IO_BASE are defined in hardware.h */ - -#define PMU_START (IO_START + PMU_OFF) /* Physical addr. of the PMU reg. */ -#define PMU_BASE (IO_BASE + PMU_OFF) /* Virtual addr. of the PMU reg. */ - - -/* Define the PMU registers for use by device drivers and the kernel. */ - -typedef struct { - unsigned int CURRENT; /* Current configuration register */ - unsigned int NEXT; /* Next configuration register */ - unsigned int reserved; - unsigned int RUN; /* Run configuration register */ - unsigned int COMM; /* Configuration command register */ - unsigned int SDRAM; /* SDRAM configuration bypass register */ -} pmu_interface; - -#define PMU ((volatile pmu_interface *)(PMU_BASE)) - - -/* Macro's for reading the common register fields. */ - -#define GET_TRANSOP(reg) ((reg >> 25) & 0x03) /* Bits 26-25 */ -#define GET_OSCEN(reg) ((reg >> 16) & 0x01) -#define GET_OSCMUX(reg) ((reg >> 15) & 0x01) -#define GET_PLLMUL(reg) ((reg >> 9) & 0x3f) /* Bits 14-9 */ -#define GET_PLLEN(reg) ((reg >> 8) & 0x01) -#define GET_PLLMUX(reg) ((reg >> 7) & 0x01) -#define GET_BCLK_DIV(reg) ((reg >> 3) & 0x03) /* Bits 4-3 */ -#define GET_SDRB_SEL(reg) ((reg >> 2) & 0x01) -#define GET_SDRF_SEL(reg) ((reg >> 1) & 0x01) -#define GET_FASTBUS(reg) (reg & 0x1) - -/* CFG_NEXT register */ - -#define CFG_NEXT_CLOCKRECOVERY ((PMU->NEXT >> 18) & 0x7f) /* Bits 24-18 */ -#define CFG_NEXT_INTRET ((PMU->NEXT >> 17) & 0x01) -#define CFG_NEXT_SDR_STOP ((PMU->NEXT >> 6) & 0x01) -#define CFG_NEXT_SYSCLKEN ((PMU->NEXT >> 5) & 0x01) - -/* Useful field values that can be used to construct the - * CFG_NEXT and CFG_RUN registers. - */ - -#define TRANSOP_NOP 0<<25 /* NOCHANGE_NOSTALL */ -#define NOCHANGE_STALL 1<<25 -#define CHANGE_NOSTALL 2<<25 -#define CHANGE_STALL 3<<25 - -#define INTRET 1<<17 -#define OSCEN 1<<16 -#define OSCMUX 1<<15 - -/* PLL frequencies */ - -#define PLLMUL_0 0<<9 /* 3.6864 MHz */ -#define PLLMUL_1 1<<9 /* ?????? MHz */ -#define PLLMUL_5 5<<9 /* 18.432 MHz */ -#define PLLMUL_10 10<<9 /* 36.864 MHz */ -#define PLLMUL_18 18<<9 /* ?????? MHz */ -#define PLLMUL_20 20<<9 /* 73.728 MHz */ -#define PLLMUL_32 32<<9 /* ?????? MHz */ -#define PLLMUL_35 35<<9 /* 129.024 MHz */ -#define PLLMUL_36 36<<9 /* ?????? MHz */ -#define PLLMUL_39 39<<9 /* ?????? MHz */ -#define PLLMUL_40 40<<9 /* 147.456 MHz */ - -/* Clock recovery times */ - -#define CRCLOCK_1 1<<18 -#define CRCLOCK_2 2<<18 -#define CRCLOCK_4 4<<18 -#define CRCLOCK_8 8<<18 -#define CRCLOCK_16 16<<18 -#define CRCLOCK_32 32<<18 -#define CRCLOCK_63 63<<18 -#define CRCLOCK_127 127<<18 - -#define PLLEN 1<<8 -#define PLLMUX 1<<7 -#define SDR_STOP 1<<6 -#define SYSCLKEN 1<<5 - -#define BCLK_DIV_4 2<<3 -#define BCLK_DIV_2 1<<3 -#define BCLK_DIV_1 0<<3 - -#define SDRB_SEL 1<<2 -#define SDRF_SEL 1<<1 -#define FASTBUS 1<<0 - - -/* CFG_SDRAM */ - -#define SDRREFFQ 1<<0 /* Only if SDRSTOPRQ is not set. */ -#define SDRREFACK 1<<1 /* Read-only */ -#define SDRSTOPRQ 1<<2 /* Only if SDRREFFQ is not set. */ -#define SDRSTOPACK 1<<3 /* Read-only */ -#define PICEN 1<<4 /* Enable Co-procesor */ -#define PICTEST 1<<5 - -#define GET_SDRREFFQ ((PMU->SDRAM >> 0) & 0x01) -#define GET_SDRREFACK ((PMU->SDRAM >> 1) & 0x01) /* Read-only */ -#define GET_SDRSTOPRQ ((PMU->SDRAM >> 2) & 0x01) -#define GET_SDRSTOPACK ((PMU->SDRAM >> 3) & 0x01) /* Read-only */ -#define GET_PICEN ((PMU->SDRAM >> 4) & 0x01) -#define GET_PICTEST ((PMU->SDRAM >> 5) & 0x01) diff --git a/arch/arm/mach-l7200/include/mach/serial.h b/arch/arm/mach-l7200/include/mach/serial.h deleted file mode 100644 index adc05e5f8378..000000000000 --- a/arch/arm/mach-l7200/include/mach/serial.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * arch/arm/mach-l7200/include/mach/serial.h - * - * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net) - * Steve Hill (sjhill@cotw.com) - * - * Changelog: - * 03-20-2000 SJH Created - * 03-26-2000 SJH Added flags for serial ports - * 03-27-2000 SJH Corrected BASE_BAUD value - * 04-14-2000 RS Made register addr dependent on IO_BASE - * 05-03-2000 SJH Complete rewrite - * 05-09-2000 SJH Stripped out architecture specific serial stuff - * and placed it in a separate file - * 07-28-2000 SJH Moved base baud rate variable - */ -#ifndef __ASM_ARCH_SERIAL_H -#define __ASM_ARCH_SERIAL_H - -/* - * This assumes you have a 3.6864 MHz clock for your UART. - */ -#define BASE_BAUD 3686400 - -/* - * Standard COM flags - */ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) - -#define STD_SERIAL_PORT_DEFNS \ - /* MAGIC UART CLK PORT IRQ FLAGS */ \ - { 0, BASE_BAUD, UART1_BASE, IRQ_UART_1, STD_COM_FLAGS }, /* ttyLU0 */ \ - { 0, BASE_BAUD, UART2_BASE, IRQ_UART_2, STD_COM_FLAGS }, /* ttyLU1 */ \ - -#define EXTRA_SERIAL_PORT_DEFNS - -#endif diff --git a/arch/arm/mach-l7200/include/mach/serial_l7200.h b/arch/arm/mach-l7200/include/mach/serial_l7200.h deleted file mode 100644 index 645f1c5e568d..000000000000 --- a/arch/arm/mach-l7200/include/mach/serial_l7200.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * arch/arm/mach-l7200/include/mach/serial_l7200.h - * - * Copyright (c) 2000 Steven Hill (sjhill@cotw.com) - * - * Changelog: - * 05-09-2000 SJH Created - */ -#ifndef __ASM_ARCH_SERIAL_L7200_H -#define __ASM_ARCH_SERIAL_L7200_H - -#include <mach/memory.h> - -/* - * This assumes you have a 3.6864 MHz clock for your UART. - */ -#define BASE_BAUD 3686400 - -/* - * UART base register addresses - */ -#define UART1_BASE (IO_BASE + 0x00044000) -#define UART2_BASE (IO_BASE + 0x00045000) - -/* - * UART register offsets - */ -#define UARTDR 0x00 /* Tx/Rx data */ -#define RXSTAT 0x04 /* Rx status */ -#define H_UBRLCR 0x08 /* mode register high */ -#define M_UBRLCR 0x0C /* mode reg mid (MSB of baud)*/ -#define L_UBRLCR 0x10 /* mode reg low (LSB of baud)*/ -#define UARTCON 0x14 /* control register */ -#define UARTFLG 0x18 /* flag register */ -#define UARTINTSTAT 0x1C /* FIFO IRQ status register */ -#define UARTINTMASK 0x20 /* FIFO IRQ mask register */ - -/* - * UART baud rate register values - */ -#define BR_110 0x827 -#define BR_1200 0x06e -#define BR_2400 0x05f -#define BR_4800 0x02f -#define BR_9600 0x017 -#define BR_14400 0x00f -#define BR_19200 0x00b -#define BR_38400 0x005 -#define BR_57600 0x003 -#define BR_76800 0x002 -#define BR_115200 0x001 - -/* - * Receiver status register (RXSTAT) mask values - */ -#define RXSTAT_NO_ERR 0x00 /* No error */ -#define RXSTAT_FRM_ERR 0x01 /* Framing error */ -#define RXSTAT_PAR_ERR 0x02 /* Parity error */ -#define RXSTAT_OVR_ERR 0x04 /* Overrun error */ - -/* - * High byte of UART bit rate and line control register (H_UBRLCR) values - */ -#define UBRLCR_BRK 0x01 /* generate break on tx */ -#define UBRLCR_PEN 0x02 /* enable parity */ -#define UBRLCR_PDIS 0x00 /* disable parity */ -#define UBRLCR_EVEN 0x04 /* 1= even parity,0 = odd parity */ -#define UBRLCR_STP2 0x08 /* transmit 2 stop bits */ -#define UBRLCR_FIFO 0x10 /* enable FIFO */ -#define UBRLCR_LEN5 0x60 /* word length5 */ -#define UBRLCR_LEN6 0x40 /* word length6 */ -#define UBRLCR_LEN7 0x20 /* word length7 */ -#define UBRLCR_LEN8 0x00 /* word length8 */ - -/* - * UART control register (UARTCON) values - */ -#define UARTCON_UARTEN 0x01 /* Enable UART */ -#define UARTCON_DMAONERR 0x08 /* Mask RxDmaRq when errors occur */ - -/* - * UART flag register (UARTFLG) mask values - */ -#define UARTFLG_UTXFF 0x20 /* Transmit FIFO full */ -#define UARTFLG_URXFE 0x10 /* Receiver FIFO empty */ -#define UARTFLG_UBUSY 0x08 /* Transmitter busy */ -#define UARTFLG_DCD 0x04 /* Data carrier detect */ -#define UARTFLG_DSR 0x02 /* Data set ready */ -#define UARTFLG_CTS 0x01 /* Clear to send */ - -/* - * UART interrupt status/clear registers (UARTINTSTAT/CLR) values - */ -#define UART_TXINT 0x01 /* TX interrupt */ -#define UART_RXINT 0x02 /* RX interrupt */ -#define UART_RXERRINT 0x04 /* RX error interrupt */ -#define UART_MSINT 0x08 /* Modem Status interrupt */ -#define UART_UDINT 0x10 /* UART Disabled interrupt */ -#define UART_ALLIRQS 0x1f /* All interrupts */ - -#endif diff --git a/arch/arm/mach-l7200/include/mach/sib.h b/arch/arm/mach-l7200/include/mach/sib.h deleted file mode 100644 index 965728712cf3..000000000000 --- a/arch/arm/mach-l7200/include/mach/sib.h +++ /dev/null @@ -1,119 +0,0 @@ -/****************************************************************************/ -/* - * arch/arm/mach-l7200/include/mach/sib.h - * - * Registers and helper functions for the Serial Interface Bus. - * - * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -/****************************************************************************/ - -#define SIB_OFF 0x00040000 /* Offset from IO_START to the SIB reg's. */ - -/* IO_START and IO_BASE are defined in hardware.h */ - -#define SIB_START (IO_START + SIB_OFF) /* Physical addr of the SIB reg. */ -#define SIB_BASE (IO_BASE + SIB_OFF) /* Virtual addr of the SIB reg. */ - -/* Offsets from the start of the SIB for all the registers. */ - -/* Define the SIB registers for use by device drivers and the kernel. */ - -typedef struct -{ - unsigned int MCCR; /* SIB Control Register Offset: 0x00 */ - unsigned int RES1; /* Reserved Offset: 0x04 */ - unsigned int MCDR0; /* SIB Data Register 0 Offset: 0x08 */ - unsigned int MCDR1; /* SIB Data Register 1 Offset: 0x0c */ - unsigned int MCDR2; /* SIB Data Register 2 (UCB1x00) Offset: 0x10 */ - unsigned int RES2; /* Reserved Offset: 0x14 */ - unsigned int MCSR; /* SIB Status Register Offset: 0x18 */ -} SIB_Interface; - -#define SIB ((volatile SIB_Interface *) (SIB_BASE)) - -/* MCCR */ - -#define INTERNAL_FREQ 9216000 /* Hertz */ -#define AUDIO_FREQ 5000 /* Hertz */ -#define TELECOM_FREQ 5000 /* Hertz */ - -#define AUDIO_DIVIDE (INTERNAL_FREQ / (32 * AUDIO_FREQ)) -#define TELECOM_DIVIDE (INTERNAL_FREQ / (32 * TELECOM_FREQ)) - -#define MCCR_ASD57 AUDIO_DIVIDE -#define MCCR_TSD57 (TELECOM_DIVIDE << 8) -#define MCCR_MCE (1 << 16) /* SIB enable */ -#define MCCR_ECS (1 << 17) /* External Clock Select */ -#define MCCR_ADM (1 << 18) /* A/D Data Sampling */ -#define MCCR_PMC (1 << 26) /* PIN Multiplexer Control */ - - -#define GET_ASD ((SIB->MCCR >> 0) & 0x3f) /* Audio Sample Rate Div. */ -#define GET_TSD ((SIB->MCCR >> 8) & 0x3f) /* Telcom Sample Rate Div. */ -#define GET_MCE ((SIB->MCCR >> 16) & 0x01) /* SIB Enable */ -#define GET_ECS ((SIB->MCCR >> 17) & 0x01) /* External Clock Select */ -#define GET_ADM ((SIB->MCCR >> 18) & 0x01) /* A/D Data Sampling Mode */ -#define GET_TTM ((SIB->MCCR >> 19) & 0x01) /* Telco Trans. FIFO I mask */ -#define GET_TRM ((SIB->MCCR >> 20) & 0x01) /* Telco Recv. FIFO I mask */ -#define GET_ATM ((SIB->MCCR >> 21) & 0x01) /* Audio Trans. FIFO I mask */ -#define GET_ARM ((SIB->MCCR >> 22) & 0x01) /* Audio Recv. FIFO I mask */ -#define GET_LBM ((SIB->MCCR >> 23) & 0x01) /* Loop Back Mode */ -#define GET_ECP ((SIB->MCCR >> 24) & 0x03) /* Extern. Clck Prescale sel */ -#define GET_PMC ((SIB->MCCR >> 26) & 0x01) /* PIN Multiplexer Control */ -#define GET_ERI ((SIB->MCCR >> 27) & 0x01) /* External Read Interrupt */ -#define GET_EWI ((SIB->MCCR >> 28) & 0x01) /* External Write Interrupt */ - -/* MCDR0 */ - -#define AUDIO_RECV ((SIB->MCDR0 >> 4) & 0xfff) -#define AUDIO_WRITE(v) ((SIB->MCDR0 = (v & 0xfff) << 4)) - -/* MCDR1 */ - -#define TELECOM_RECV ((SIB->MCDR1 >> 2) & 032fff) -#define TELECOM_WRITE(v) ((SIB->MCDR1 = (v & 0x3fff) << 2)) - - -/* MCSR */ - -#define MCSR_ATU (1 << 4) /* Audio Transmit FIFO Underrun */ -#define MCSR_ARO (1 << 5) /* Audio Receive FIFO Underrun */ -#define MCSR_TTU (1 << 6) /* TELECOM Transmit FIFO Underrun */ -#define MCSR_TRO (1 << 7) /* TELECOM Receive FIFO Underrun */ - -#define MCSR_CLEAR_UNDERUN_BITS (MCSR_ATU | MCSR_ARO | MCSR_TTU | MCSR_TRO) - - -#define GET_ATS ((SIB->MCSR >> 0) & 0x01) /* Audio Transmit FIFO Service Req*/ -#define GET_ARS ((SIB->MCSR >> 1) & 0x01) /* Audio Recv FIFO Service Request*/ -#define GET_TTS ((SIB->MCSR >> 2) & 0x01) /* TELECOM Transmit FIFO Flag */ -#define GET_TRS ((SIB->MCSR >> 3) & 0x01) /* TELECOM Recv FIFO Service Req. */ -#define GET_ATU ((SIB->MCSR >> 4) & 0x01) /* Audio Transmit FIFO Underrun */ -#define GET_ARO ((SIB->MCSR >> 5) & 0x01) /* Audio Receive FIFO Underrun */ -#define GET_TTU ((SIB->MCSR >> 6) & 0x01) /* TELECOM Transmit FIFO Underrun */ -#define GET_TRO ((SIB->MCSR >> 7) & 0x01) /* TELECOM Receive FIFO Underrun */ -#define GET_ANF ((SIB->MCSR >> 8) & 0x01) /* Audio Transmit FIFO not full */ -#define GET_ANE ((SIB->MCSR >> 9) & 0x01) /* Audio Receive FIFO not empty */ -#define GET_TNF ((SIB->MCSR >> 10) & 0x01) /* Telecom Transmit FIFO not full */ -#define GET_TNE ((SIB->MCSR >> 11) & 0x01) /* Telecom Receive FIFO not empty */ -#define GET_CWC ((SIB->MCSR >> 12) & 0x01) /* Codec Write Complete */ -#define GET_CRC ((SIB->MCSR >> 13) & 0x01) /* Codec Read Complete */ -#define GET_ACE ((SIB->MCSR >> 14) & 0x01) /* Audio Codec Enabled */ -#define GET_TCE ((SIB->MCSR >> 15) & 0x01) /* Telecom Codec Enabled */ - -/* MCDR2 */ - -#define MCDR2_rW (1 << 16) - -#define WRITE_MCDR2(reg, data) (SIB->MCDR2 =((reg<<17)|MCDR2_rW|(data&0xffff))) -#define MCDR2_WRITE_COMPLETE GET_CWC - -#define INITIATE_MCDR2_READ(reg) (SIB->MCDR2 = (reg << 17)) -#define MCDR2_READ_COMPLETE GET_CRC -#define MCDR2_READ (SIB->MCDR2 & 0xffff) diff --git a/arch/arm/mach-l7200/include/mach/sys-clock.h b/arch/arm/mach-l7200/include/mach/sys-clock.h deleted file mode 100644 index e9729a35751d..000000000000 --- a/arch/arm/mach-l7200/include/mach/sys-clock.h +++ /dev/null @@ -1,67 +0,0 @@ -/****************************************************************************/ -/* - * arch/arm/mach-l7200/include/mach/sys-clock.h - * - * Registers and helper functions for the L7200 Link-Up Systems - * System clocks. - * - * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -/****************************************************************************/ - -#define SYS_CLOCK_OFF 0x00050030 /* Offset from IO_START. */ - -/* IO_START and IO_BASE are defined in hardware.h */ - -#define SYS_CLOCK_START (IO_START + SYS_CLOCK_OFF) /* Physical address */ -#define SYS_CLOCK_BASE (IO_BASE + SYS_CLOCK_OFF) /* Virtual address */ - -/* Define the interface to the SYS_CLOCK */ - -typedef struct -{ - unsigned int ENABLE; - unsigned int ESYNC; - unsigned int SELECT; -} sys_clock_interface; - -#define SYS_CLOCK ((volatile sys_clock_interface *)(SYS_CLOCK_BASE)) - -//#define CLOCK_EN (*(volatile unsigned long *)(PMU_BASE+CLOCK_EN_OFF)) -//#define CLOCK_ESYNC (*(volatile unsigned long *)(PMU_BASE+CLOCK_ESYNC_OFF)) -//#define CLOCK_SEL (*(volatile unsigned long *)(PMU_BASE+CLOCK_SEL_OFF)) - -/* SYS_CLOCK -> ENABLE */ - -#define SYN_EN 1<<0 -#define B18M_EN 1<<1 -#define CLK3M6_EN 1<<2 -#define BUART_EN 1<<3 -#define CLK18MU_EN 1<<4 -#define FIR_EN 1<<5 -#define MIRN_EN 1<<6 -#define UARTM_EN 1<<7 -#define SIBADC_EN 1<<8 -#define ALTD_EN 1<<9 -#define CLCLK_EN 1<<10 - -/* SYS_CLOCK -> SELECT */ - -#define CLK18M_DIV 1<<0 -#define MIR_SEL 1<<1 -#define SSP_SEL 1<<4 -#define MM_DIV 1<<5 -#define MM_SEL 1<<6 -#define ADC_SEL_2 0<<7 -#define ADC_SEL_4 1<<7 -#define ADC_SEL_8 3<<7 -#define ADC_SEL_16 7<<7 -#define ADC_SEL_32 0x0f<<7 -#define ADC_SEL_64 0x1f<<7 -#define ADC_SEL_128 0x3f<<7 -#define ALTD_SEL 1<<13 diff --git a/arch/arm/mach-l7200/include/mach/system.h b/arch/arm/mach-l7200/include/mach/system.h deleted file mode 100644 index e0dd3b6ae4aa..000000000000 --- a/arch/arm/mach-l7200/include/mach/system.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * arch/arm/mach-l7200/include/mach/system.h - * - * Copyright (c) 2000 Steve Hill (sjhill@cotw.com) - * - * Changelog - * 03-21-2000 SJH Created - * 04-26-2000 SJH Fixed functions - * 05-03-2000 SJH Removed usage of obsolete 'iomd.h' - * 05-31-2000 SJH Properly implemented 'arch_idle' - */ -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -#include <mach/hardware.h> - -static inline void arch_idle(void) -{ - *(unsigned long *)(IO_BASE + 0x50004) = 1; /* idle mode */ -} - -static inline void arch_reset(char mode, const char *cmd) -{ - if (mode == 's') { - cpu_reset(0); - } -} - -#endif diff --git a/arch/arm/mach-l7200/include/mach/time.h b/arch/arm/mach-l7200/include/mach/time.h deleted file mode 100644 index 061771c2c2bd..000000000000 --- a/arch/arm/mach-l7200/include/mach/time.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * arch/arm/mach-l7200/include/mach/time.h - * - * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net) - * Steve Hill (sjhill@cotw.com) - * - * Changelog: - * 01-02-2000 RS Created l7200 version, derived from rpc code - * 05-03-2000 SJH Complete rewrite - */ -#ifndef _ASM_ARCH_TIME_H -#define _ASM_ARCH_TIME_H - -#include <mach/irqs.h> - -/* - * RTC base register address - */ -#define RTC_BASE (IO_BASE_2 + 0x2000) - -/* - * RTC registers - */ -#define RTC_RTCDR (*(volatile unsigned char *) (RTC_BASE + 0x000)) -#define RTC_RTCMR (*(volatile unsigned char *) (RTC_BASE + 0x004)) -#define RTC_RTCS (*(volatile unsigned char *) (RTC_BASE + 0x008)) -#define RTC_RTCC (*(volatile unsigned char *) (RTC_BASE + 0x008)) -#define RTC_RTCDV (*(volatile unsigned char *) (RTC_BASE + 0x00c)) -#define RTC_RTCCR (*(volatile unsigned char *) (RTC_BASE + 0x010)) - -/* - * RTCCR register values - */ -#define RTC_RATE_32 0x00 /* 32 Hz tick */ -#define RTC_RATE_64 0x10 /* 64 Hz tick */ -#define RTC_RATE_128 0x20 /* 128 Hz tick */ -#define RTC_RATE_256 0x30 /* 256 Hz tick */ -#define RTC_EN_ALARM 0x01 /* Enable alarm */ -#define RTC_EN_TIC 0x04 /* Enable counter */ -#define RTC_EN_STWDOG 0x08 /* Enable watchdog */ - -/* - * Handler for RTC timer interrupt - */ -static irqreturn_t -timer_interrupt(int irq, void *dev_id) -{ - struct pt_regs *regs = get_irq_regs(); - do_timer(1); -#ifndef CONFIG_SMP - update_process_times(user_mode(regs)); -#endif - do_profile(regs); - RTC_RTCC = 0; /* Clear interrupt */ - - return IRQ_HANDLED; -} - -/* - * Set up RTC timer interrupt, and return the current time in seconds. - */ -void __init time_init(void) -{ - RTC_RTCC = 0; /* Clear interrupt */ - - timer_irq.handler = timer_interrupt; - - setup_irq(IRQ_RTC_TICK, &timer_irq); - - RTC_RTCCR = RTC_RATE_128 | RTC_EN_TIC; /* Set rate and enable timer */ -} - -#endif diff --git a/arch/arm/mach-l7200/include/mach/timex.h b/arch/arm/mach-l7200/include/mach/timex.h deleted file mode 100644 index ffc96a63b5a2..000000000000 --- a/arch/arm/mach-l7200/include/mach/timex.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * arch/arm/mach-l7200/include/mach/timex.h - * - * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net) - * Steve Hill (sjhill@cotw.com) - * - * 04-21-2000 RS Created file - * 05-03-2000 SJH Tick rate was wrong - * - */ - -/* - * On the ARM720T, clock ticks are set to 128 Hz. - * - * NOTE: The actual RTC value is set in 'time.h' which - * must be changed when choosing a different tick - * rate. The value of HZ in 'param.h' must also - * be changed to match below. - */ -#define CLOCK_TICK_RATE 128 diff --git a/arch/arm/mach-l7200/include/mach/uncompress.h b/arch/arm/mach-l7200/include/mach/uncompress.h deleted file mode 100644 index 591c962bb315..000000000000 --- a/arch/arm/mach-l7200/include/mach/uncompress.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * arch/arm/mach-l7200/include/mach/uncompress.h - * - * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) - * - * Changelog: - * 05-01-2000 SJH Created - * 05-13-2000 SJH Filled in function bodies - * 07-26-2000 SJH Removed hard coded baud rate - */ - -#include <mach/hardware.h> - -#define IO_UART IO_START + 0x00044000 - -#define __raw_writeb(v,p) (*(volatile unsigned char *)(p) = (v)) -#define __raw_readb(p) (*(volatile unsigned char *)(p)) - -static inline void putc(int c) -{ - while(__raw_readb(IO_UART + 0x18) & 0x20 || - __raw_readb(IO_UART + 0x18) & 0x08) - barrier(); - - __raw_writeb(c, IO_UART + 0x00); -} - -static inline void flush(void) -{ -} - -static __inline__ void arch_decomp_setup(void) -{ - __raw_writeb(0x00, IO_UART + 0x08); /* Set HSB */ - __raw_writeb(0x00, IO_UART + 0x20); /* Disable IRQs */ - __raw_writeb(0x01, IO_UART + 0x14); /* Enable UART */ -} - -#define arch_decomp_wdog() diff --git a/arch/arm/mach-l7200/include/mach/vmalloc.h b/arch/arm/mach-l7200/include/mach/vmalloc.h deleted file mode 100644 index 85f0abbf15f1..000000000000 --- a/arch/arm/mach-l7200/include/mach/vmalloc.h +++ /dev/null @@ -1,4 +0,0 @@ -/* - * arch/arm/mach-l7200/include/mach/vmalloc.h - */ -#define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/arch/arm/mach-lh7a40x/include/mach/memory.h b/arch/arm/mach-lh7a40x/include/mach/memory.h index 189d20e543e7..edb8f5faf5d5 100644 --- a/arch/arm/mach-lh7a40x/include/mach/memory.h +++ b/arch/arm/mach-lh7a40x/include/mach/memory.h @@ -19,50 +19,6 @@ */ #define PHYS_OFFSET UL(0xc0000000) -#ifdef CONFIG_DISCONTIGMEM - -/* - * Given a kernel address, find the home node of the underlying memory. - */ - -# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE -# define KVADDR_TO_NID(addr) \ - ( ((((unsigned long) (addr) - PAGE_OFFSET) >> 24) & 1)\ - | ((((unsigned long) (addr) - PAGE_OFFSET) >> 25) & ~1)) -# else /* 2 banks per node */ -# define KVADDR_TO_NID(addr) \ - (((unsigned long) (addr) - PAGE_OFFSET) >> 26) -# endif - -/* - * Given a page frame number, convert it to a node id. - */ - -# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE -# define PFN_TO_NID(pfn) \ - (((((pfn) - PHYS_PFN_OFFSET) >> (24 - PAGE_SHIFT)) & 1)\ - | ((((pfn) - PHYS_PFN_OFFSET) >> (25 - PAGE_SHIFT)) & ~1)) -# else /* 2 banks per node */ -# define PFN_TO_NID(pfn) \ - (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT)) -#endif - -/* - * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory - * and returns the index corresponding to the appropriate page in the - * node's mem_map. - */ - -# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE -# define LOCAL_MAP_NR(addr) \ - (((unsigned long)(addr) & 0x003fffff) >> PAGE_SHIFT) -# else /* 2 banks per node */ -# define LOCAL_MAP_NR(addr) \ - (((unsigned long)(addr) & 0x01ffffff) >> PAGE_SHIFT) -# endif - -#endif - /* * Sparsemem version of the above */ diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig new file mode 100644 index 000000000000..fde663508696 --- /dev/null +++ b/arch/arm/mach-lpc32xx/Kconfig @@ -0,0 +1,33 @@ +if ARCH_LPC32XX + +menu "Individual UART enable selections" + +config ARCH_LPC32XX_UART3_SELECT + bool "Add support for standard UART3" + help + Adds support for standard UART 3 when the 8250 serial support + is enabled. + +config ARCH_LPC32XX_UART4_SELECT + bool "Add support for standard UART4" + help + Adds support for standard UART 4 when the 8250 serial support + is enabled. + +config ARCH_LPC32XX_UART5_SELECT + bool "Add support for standard UART5" + default y + help + Adds support for standard UART 5 when the 8250 serial support + is enabled. + +config ARCH_LPC32XX_UART6_SELECT + bool "Add support for standard UART6" + help + Adds support for standard UART 6 when the 8250 serial support + is enabled. + +endmenu + +endif + diff --git a/arch/arm/mach-lpc32xx/Makefile b/arch/arm/mach-lpc32xx/Makefile new file mode 100644 index 000000000000..a5fc5d0eeaeb --- /dev/null +++ b/arch/arm/mach-lpc32xx/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the linux kernel. +# + +obj-y := timer.o irq.o common.o serial.o clock.o +obj-y += gpiolib.o pm.o suspend.o +obj-y += phy3250.o + diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot new file mode 100644 index 000000000000..b796b41ebf8f --- /dev/null +++ b/arch/arm/mach-lpc32xx/Makefile.boot @@ -0,0 +1,4 @@ + zreladdr-y := 0x80008000 +params_phys-y := 0x80000100 +initrd_phys-y := 0x82000000 + diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c new file mode 100644 index 000000000000..32d63796430a --- /dev/null +++ b/arch/arm/mach-lpc32xx/clock.c @@ -0,0 +1,1137 @@ +/* + * arch/arm/mach-lpc32xx/clock.c + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * LPC32xx clock management driver overview + * + * The LPC32XX contains a number of high level system clocks that can be + * generated from different sources. These system clocks are used to + * generate the CPU and bus rates and the individual peripheral clocks in + * the system. When Linux is started by the boot loader, the system + * clocks are already running. Stopping a system clock during normal + * Linux operation should never be attempted, as peripherals that require + * those clocks will quit working (ie, DRAM). + * + * The LPC32xx high level clock tree looks as follows. Clocks marked with + * an asterisk are always on and cannot be disabled. Clocks marked with + * an ampersand can only be disabled in CPU suspend mode. Clocks marked + * with a caret are always on if it is the selected clock for the SYSCLK + * source. The clock that isn't used for SYSCLK can be enabled and + * disabled normally. + * 32KHz oscillator* + * / | \ + * RTC* PLL397^ TOUCH + * / + * Main oscillator^ / + * | \ / + * | SYSCLK& + * | \ + * | \ + * USB_PLL HCLK_PLL& + * | | | + * USB host/device PCLK& | + * | | + * Peripherals + * + * The CPU and chip bus rates are derived from the HCLK PLL, which can + * generate various clock rates up to 266MHz and beyond. The internal bus + * rates (PCLK and HCLK) are generated from dividers based on the HCLK + * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate, + * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high + * level clocks are based on either HCLK or PCLK, but have their own + * dividers as part of the IP itself. Because of this, the system clock + * rates should not be changed. + * + * The HCLK PLL is clocked from SYSCLK, which can be derived from the + * main oscillator or PLL397. PLL397 generates a rate that is 397 times + * the 32KHz oscillator rate. The main oscillator runs at the selected + * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate + * is normally 13MHz, but depends on the selection of external crystals + * or oscillators. If USB operation is required, the main oscillator must + * be used in the system. + * + * Switching SYSCLK between sources during normal Linux operation is not + * supported. SYSCLK is preset in the bootloader. Because of the + * complexities of clock management during clock frequency changes, + * there are some limitations to the clock driver explained below: + * - The PLL397 and main oscillator can be enabled and disabled by the + * clk_enable() and clk_disable() functions unless SYSCLK is based + * on that clock. This allows the other oscillator that isn't driving + * the HCLK PLL to be used as another system clock that can be routed + * to an external pin. + * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with + * this driver. + * - HCLK and PCLK rates cannot be changed as part of this driver. + * - Most peripherals have their own dividers are part of the peripheral + * block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates + * will also impact the individual peripheral rates. + */ + +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/amba/bus.h> +#include <linux/amba/clcd.h> + +#include <mach/hardware.h> +#include <asm/clkdev.h> +#include <mach/clkdev.h> +#include <mach/platform.h> +#include "clock.h" +#include "common.h" + +static struct clk clk_armpll; +static struct clk clk_usbpll; +static DEFINE_MUTEX(clkm_lock); + +/* + * Post divider values for PLLs based on selected register value + */ +static const u32 pll_postdivs[4] = {1, 2, 4, 8}; + +static unsigned long local_return_parent_rate(struct clk *clk) +{ + /* + * If a clock has a rate of 0, then it inherits it's parent + * clock rate + */ + while (clk->rate == 0) + clk = clk->parent; + + return clk->rate; +} + +/* 32KHz clock has a fixed rate and is not stoppable */ +static struct clk osc_32KHz = { + .rate = LPC32XX_CLOCK_OSC_FREQ, + .get_rate = local_return_parent_rate, +}; + +static int local_pll397_enable(struct clk *clk, int enable) +{ + u32 reg; + unsigned long timeout = 1 + msecs_to_jiffies(10); + + reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL); + + if (enable == 0) { + reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS; + __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL); + } else { + /* Enable PLL397 */ + reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS; + __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL); + + /* Wait for PLL397 lock */ + while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) & + LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) && + (timeout > jiffies)) + cpu_relax(); + + if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) & + LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) + return -ENODEV; + } + + return 0; +} + +static int local_oscmain_enable(struct clk *clk, int enable) +{ + u32 reg; + unsigned long timeout = 1 + msecs_to_jiffies(10); + + reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL); + + if (enable == 0) { + reg |= LPC32XX_CLKPWR_MOSC_DISABLE; + __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL); + } else { + /* Enable main oscillator */ + reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE; + __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL); + + /* Wait for main oscillator to start */ + while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) & + LPC32XX_CLKPWR_MOSC_DISABLE) != 0) && + (timeout > jiffies)) + cpu_relax(); + + if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) & + LPC32XX_CLKPWR_MOSC_DISABLE) != 0) + return -ENODEV; + } + + return 0; +} + +static struct clk osc_pll397 = { + .parent = &osc_32KHz, + .enable = local_pll397_enable, + .rate = LPC32XX_CLOCK_OSC_FREQ * 397, + .get_rate = local_return_parent_rate, +}; + +static struct clk osc_main = { + .enable = local_oscmain_enable, + .rate = LPC32XX_MAIN_OSC_FREQ, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_sys; + +/* + * Convert a PLL register value to a PLL output frequency + */ +u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval) +{ + struct clk_pll_setup pllcfg; + + pllcfg.cco_bypass_b15 = 0; + pllcfg.direct_output_b14 = 0; + pllcfg.fdbk_div_ctrl_b13 = 0; + if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0) + pllcfg.cco_bypass_b15 = 1; + if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0) + pllcfg.direct_output_b14 = 1; + if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0) + pllcfg.fdbk_div_ctrl_b13 = 1; + pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF); + pllcfg.pll_n = 1 + ((regval >> 9) & 0x3); + pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)]; + + return clk_check_pll_setup(inputclk, &pllcfg); +} + +/* + * Setup the HCLK PLL with a PLL structure + */ +static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup) +{ + u32 tv, tmp = 0; + + if (PllSetup->analog_on != 0) + tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP; + if (PllSetup->cco_bypass_b15 != 0) + tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS; + if (PllSetup->direct_output_b14 != 0) + tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS; + if (PllSetup->fdbk_div_ctrl_b13 != 0) + tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK; + + tv = ffs(PllSetup->pll_p) - 1; + if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3)) + return 0; + + tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv); + tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1); + tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1); + + return tmp; +} + +/* + * Update the ARM core PLL frequency rate variable from the actual PLL setting + */ +static void local_update_armpll_rate(void) +{ + u32 clkin, pllreg; + + clkin = clk_armpll.parent->rate; + pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF; + + clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg); +} + +/* + * Find a PLL configuration for the selected input frequency + */ +static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq, + struct clk_pll_setup *pllsetup) +{ + u32 ifreq, freqtol, m, n, p, fclkout; + + /* Determine frequency tolerance limits */ + freqtol = target_freq / 250; + ifreq = pllin_freq; + + /* Is direct bypass mode possible? */ + if (abs(pllin_freq - target_freq) <= freqtol) { + pllsetup->analog_on = 0; + pllsetup->cco_bypass_b15 = 1; + pllsetup->direct_output_b14 = 1; + pllsetup->fdbk_div_ctrl_b13 = 1; + pllsetup->pll_p = pll_postdivs[0]; + pllsetup->pll_n = 1; + pllsetup->pll_m = 1; + return clk_check_pll_setup(ifreq, pllsetup); + } else if (target_freq <= ifreq) { + pllsetup->analog_on = 0; + pllsetup->cco_bypass_b15 = 1; + pllsetup->direct_output_b14 = 0; + pllsetup->fdbk_div_ctrl_b13 = 1; + pllsetup->pll_n = 1; + pllsetup->pll_m = 1; + for (p = 0; p <= 3; p++) { + pllsetup->pll_p = pll_postdivs[p]; + fclkout = clk_check_pll_setup(ifreq, pllsetup); + if (abs(target_freq - fclkout) <= freqtol) + return fclkout; + } + } + + /* Is direct mode possible? */ + pllsetup->analog_on = 1; + pllsetup->cco_bypass_b15 = 0; + pllsetup->direct_output_b14 = 1; + pllsetup->fdbk_div_ctrl_b13 = 0; + pllsetup->pll_p = pll_postdivs[0]; + for (m = 1; m <= 256; m++) { + for (n = 1; n <= 4; n++) { + /* Compute output frequency for this value */ + pllsetup->pll_n = n; + pllsetup->pll_m = m; + fclkout = clk_check_pll_setup(ifreq, + pllsetup); + if (abs(target_freq - fclkout) <= + freqtol) + return fclkout; + } + } + + /* Is integer mode possible? */ + pllsetup->analog_on = 1; + pllsetup->cco_bypass_b15 = 0; + pllsetup->direct_output_b14 = 0; + pllsetup->fdbk_div_ctrl_b13 = 1; + for (m = 1; m <= 256; m++) { + for (n = 1; n <= 4; n++) { + for (p = 0; p < 4; p++) { + /* Compute output frequency */ + pllsetup->pll_p = pll_postdivs[p]; + pllsetup->pll_n = n; + pllsetup->pll_m = m; + fclkout = clk_check_pll_setup( + ifreq, pllsetup); + if (abs(target_freq - fclkout) <= freqtol) + return fclkout; + } + } + } + + /* Try non-integer mode */ + pllsetup->analog_on = 1; + pllsetup->cco_bypass_b15 = 0; + pllsetup->direct_output_b14 = 0; + pllsetup->fdbk_div_ctrl_b13 = 0; + for (m = 1; m <= 256; m++) { + for (n = 1; n <= 4; n++) { + for (p = 0; p < 4; p++) { + /* Compute output frequency */ + pllsetup->pll_p = pll_postdivs[p]; + pllsetup->pll_n = n; + pllsetup->pll_m = m; + fclkout = clk_check_pll_setup( + ifreq, pllsetup); + if (abs(target_freq - fclkout) <= freqtol) + return fclkout; + } + } + } + + return 0; +} + +static struct clk clk_armpll = { + .parent = &clk_sys, + .get_rate = local_return_parent_rate, +}; + +/* + * Setup the USB PLL with a PLL structure + */ +static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup) +{ + u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup); + + reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF; + reg |= tmp; + __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); + + return clk_check_pll_setup(clk_usbpll.parent->rate, + pHCLKPllSetup); +} + +static int local_usbpll_enable(struct clk *clk, int enable) +{ + u32 reg; + int ret = -ENODEV; + unsigned long timeout = 1 + msecs_to_jiffies(10); + + reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); + + if (enable == 0) { + reg &= ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 | + LPC32XX_CLKPWR_USBCTRL_CLK_EN2); + __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); + } else if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) { + reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1; + __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); + + /* Wait for PLL lock */ + while ((timeout > jiffies) & (ret == -ENODEV)) { + reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); + if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS) + ret = 0; + } + + if (ret == 0) { + reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2; + __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); + } + } + + return ret; +} + +static unsigned long local_usbpll_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 clkin, usbdiv; + struct clk_pll_setup pllsetup; + + /* + * Unlike other clocks, this clock has a KHz input rate, so bump + * it up to work with the PLL function + */ + rate = rate * 1000; + + clkin = clk->parent->rate; + usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) & + LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1; + clkin = clkin / usbdiv; + + /* Try to find a good rate setup */ + if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0) + return 0; + + return clk_check_pll_setup(clkin, &pllsetup); +} + +static int local_usbpll_set_rate(struct clk *clk, unsigned long rate) +{ + u32 clkin, reg, usbdiv; + struct clk_pll_setup pllsetup; + + /* + * Unlike other clocks, this clock has a KHz input rate, so bump + * it up to work with the PLL function + */ + rate = rate * 1000; + + clkin = clk->get_rate(clk); + usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) & + LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1; + clkin = clkin / usbdiv; + + /* Try to find a good rate setup */ + if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0) + return -EINVAL; + + local_usbpll_enable(clk, 0); + + reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); + reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1; + __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); + + pllsetup.analog_on = 1; + local_clk_usbpll_setup(&pllsetup); + + clk->rate = clk_check_pll_setup(clkin, &pllsetup); + + reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); + reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2; + __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); + + return 0; +} + +static struct clk clk_usbpll = { + .parent = &osc_main, + .set_rate = local_usbpll_set_rate, + .enable = local_usbpll_enable, + .rate = 48000, /* In KHz */ + .get_rate = local_return_parent_rate, + .round_rate = local_usbpll_round_rate, +}; + +static u32 clk_get_hclk_div(void) +{ + static const u32 hclkdivs[4] = {1, 2, 4, 4}; + return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW( + __raw_readl(LPC32XX_CLKPWR_HCLK_DIV))]; +} + +static struct clk clk_hclk = { + .parent = &clk_armpll, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_pclk = { + .parent = &clk_armpll, + .get_rate = local_return_parent_rate, +}; + +static int local_onoff_enable(struct clk *clk, int enable) +{ + u32 tmp; + + tmp = __raw_readl(clk->enable_reg); + + if (enable == 0) + tmp &= ~clk->enable_mask; + else + tmp |= clk->enable_mask; + + __raw_writel(tmp, clk->enable_reg); + + return 0; +} + +/* Peripheral clock sources */ +static struct clk clk_timer0 = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1, + .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN, + .get_rate = local_return_parent_rate, +}; +static struct clk clk_timer1 = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1, + .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN, + .get_rate = local_return_parent_rate, +}; +static struct clk clk_timer2 = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1, + .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN, + .get_rate = local_return_parent_rate, +}; +static struct clk clk_timer3 = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1, + .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN, + .get_rate = local_return_parent_rate, +}; +static struct clk clk_wdt = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_TIMER_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_PWMCLK_WDOG_EN, + .get_rate = local_return_parent_rate, +}; +static struct clk clk_vfp9 = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_DEBUG_CTRL, + .enable_mask = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT, + .get_rate = local_return_parent_rate, +}; +static struct clk clk_dma = { + .parent = &clk_hclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_DMA_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_uart3 = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_uart4 = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_uart5 = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_uart6 = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_i2c0 = { + .parent = &clk_hclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_i2c1 = { + .parent = &clk_hclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_i2c2 = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = io_p2v(LPC32XX_USB_BASE + 0xFF4), + .enable_mask = 0x4, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_ssp0 = { + .parent = &clk_hclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_ssp1 = { + .parent = &clk_hclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_kscan = { + .parent = &osc_32KHz, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_KEY_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_nand = { + .parent = &clk_hclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_i2s0 = { + .parent = &clk_hclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_i2s1 = { + .parent = &clk_hclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_net = { + .parent = &clk_hclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_MACCLK_CTRL, + .enable_mask = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN | + LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN | + LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN), + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_rtc = { + .parent = &osc_32KHz, + .rate = 1, /* 1 Hz */ + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_usbd = { + .parent = &clk_usbpll, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_USB_CTRL, + .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN, + .get_rate = local_return_parent_rate, +}; + +static int tsc_onoff_enable(struct clk *clk, int enable) +{ + u32 tmp; + + /* Make sure 32KHz clock is the selected clock */ + tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1); + tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL; + __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1); + + if (enable == 0) + __raw_writel(0, clk->enable_reg); + else + __raw_writel(clk->enable_mask, clk->enable_reg); + + return 0; +} + +static struct clk clk_tsc = { + .parent = &osc_32KHz, + .enable = tsc_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN, + .get_rate = local_return_parent_rate, +}; + +static int mmc_onoff_enable(struct clk *clk, int enable) +{ + u32 tmp; + + tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & + ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN; + + /* If rate is 0, disable clock */ + if (enable != 0) + tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN; + + __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); + + return 0; +} + +static unsigned long mmc_get_rate(struct clk *clk) +{ + u32 div, rate, oldclk; + + /* The MMC clock must be on when accessing an MMC register */ + oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); + __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN, + LPC32XX_CLKPWR_MS_CTRL); + div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); + __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL); + + /* Get the parent clock rate */ + rate = clk->parent->get_rate(clk->parent); + + /* Get the MMC controller clock divider value */ + div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf); + + if (!div) + div = 1; + + return rate / div; +} + +static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long div, prate; + + /* Get the parent clock rate */ + prate = clk->parent->get_rate(clk->parent); + + if (rate >= prate) + return prate; + + div = prate / rate; + if (div > 0xf) + div = 0xf; + + return prate / div; +} + +static int mmc_set_rate(struct clk *clk, unsigned long rate) +{ + u32 oldclk, tmp; + unsigned long prate, div, crate = mmc_round_rate(clk, rate); + + prate = clk->parent->get_rate(clk->parent); + + div = prate / crate; + + /* The MMC clock must be on when accessing an MMC register */ + oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); + __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN, + LPC32XX_CLKPWR_MS_CTRL); + tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & + ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf); + tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div); + __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); + + __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL); + + return 0; +} + +static struct clk clk_mmc = { + .parent = &clk_armpll, + .set_rate = mmc_set_rate, + .get_rate = mmc_get_rate, + .round_rate = mmc_round_rate, + .enable = mmc_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_MS_CTRL, + .enable_mask = LPC32XX_CLKPWR_MSCARD_SDCARD_EN, +}; + +static unsigned long clcd_get_rate(struct clk *clk) +{ + u32 tmp, div, rate, oldclk; + + /* The LCD clock must be on when accessing an LCD register */ + oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); + __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN, + LPC32XX_CLKPWR_LCDCLK_CTRL); + tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)); + __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL); + + rate = clk->parent->get_rate(clk->parent); + + /* Only supports internal clocking */ + if (tmp & TIM2_BCD) + return rate; + + div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22); + tmp = rate / (2 + div); + + return tmp; +} + +static int clcd_set_rate(struct clk *clk, unsigned long rate) +{ + u32 tmp, prate, div, oldclk; + + /* The LCD clock must be on when accessing an LCD register */ + oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); + __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN, + LPC32XX_CLKPWR_LCDCLK_CTRL); + + tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD; + prate = clk->parent->get_rate(clk->parent); + + if (rate < prate) { + /* Find closest divider */ + div = prate / rate; + if (div >= 2) { + div -= 2; + tmp &= ~TIM2_BCD; + } + + tmp &= ~(0xF800001F); + tmp |= (div & 0x1F); + tmp |= (((div >> 5) & 0x1F) << 27); + } + + __raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)); + __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL); + + return 0; +} + +static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate) +{ + u32 prate, div; + + prate = clk->parent->get_rate(clk->parent); + + if (rate >= prate) + rate = prate; + else { + div = prate / rate; + if (div > 0x3ff) + div = 0x3ff; + + rate = prate / div; + } + + return rate; +} + +static struct clk clk_lcd = { + .parent = &clk_hclk, + .set_rate = clcd_set_rate, + .get_rate = clcd_get_rate, + .round_rate = clcd_round_rate, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_LCDCLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_LCDCTRL_CLK_EN, +}; + +static inline void clk_lock(void) +{ + mutex_lock(&clkm_lock); +} + +static inline void clk_unlock(void) +{ + mutex_unlock(&clkm_lock); +} + +static void local_clk_disable(struct clk *clk) +{ + WARN_ON(clk->usecount == 0); + + /* Don't attempt to disable clock if it has no users */ + if (clk->usecount > 0) { + clk->usecount--; + + /* Only disable clock when it has no more users */ + if ((clk->usecount == 0) && (clk->enable)) + clk->enable(clk, 0); + + /* Check parent clocks, they may need to be disabled too */ + if (clk->parent) + local_clk_disable(clk->parent); + } +} + +static int local_clk_enable(struct clk *clk) +{ + int ret = 0; + + /* Enable parent clocks first and update use counts */ + if (clk->parent) + ret = local_clk_enable(clk->parent); + + if (!ret) { + /* Only enable clock if it's currently disabled */ + if ((clk->usecount == 0) && (clk->enable)) + ret = clk->enable(clk, 1); + + if (!ret) + clk->usecount++; + else if (clk->parent) + local_clk_disable(clk->parent); + } + + return ret; +} + +/* + * clk_enable - inform the system when the clock source should be running. + */ +int clk_enable(struct clk *clk) +{ + int ret; + + clk_lock(); + ret = local_clk_enable(clk); + clk_unlock(); + + return ret; +} +EXPORT_SYMBOL(clk_enable); + +/* + * clk_disable - inform the system when the clock source is no longer required + */ +void clk_disable(struct clk *clk) +{ + clk_lock(); + local_clk_disable(clk); + clk_unlock(); +} +EXPORT_SYMBOL(clk_disable); + +/* + * clk_get_rate - obtain the current clock rate (in Hz) for a clock source + */ +unsigned long clk_get_rate(struct clk *clk) +{ + unsigned long rate; + + clk_lock(); + rate = clk->get_rate(clk); + clk_unlock(); + + return rate; +} +EXPORT_SYMBOL(clk_get_rate); + +/* + * clk_set_rate - set the clock rate for a clock source + */ +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = -EINVAL; + + /* + * Most system clocks can only be enabled or disabled, with + * the actual rate set as part of the peripheral dividers + * instead of high level clock control + */ + if (clk->set_rate) { + clk_lock(); + ret = clk->set_rate(clk, rate); + clk_unlock(); + } + + return ret; +} +EXPORT_SYMBOL(clk_set_rate); + +/* + * clk_round_rate - adjust a rate to the exact rate a clock can provide + */ +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + clk_lock(); + + if (clk->round_rate) + rate = clk->round_rate(clk, rate); + else + rate = clk->get_rate(clk); + + clk_unlock(); + + return rate; +} +EXPORT_SYMBOL(clk_round_rate); + +/* + * clk_set_parent - set the parent clock source for this clock + */ +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + /* Clock re-parenting is not supported */ + return -EINVAL; +} +EXPORT_SYMBOL(clk_set_parent); + +/* + * clk_get_parent - get the parent clock source for this clock + */ +struct clk *clk_get_parent(struct clk *clk) +{ + return clk->parent; +} +EXPORT_SYMBOL(clk_get_parent); + +#define _REGISTER_CLOCK(d, n, c) \ + { \ + .dev_id = (d), \ + .con_id = (n), \ + .clk = &(c), \ + }, + +static struct clk_lookup lookups[] = { + _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz) + _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397) + _REGISTER_CLOCK(NULL, "osc_main", osc_main) + _REGISTER_CLOCK(NULL, "sys_ck", clk_sys) + _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll) + _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll) + _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk) + _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk) + _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0) + _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1) + _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2) + _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3) + _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9) + _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma) + _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt) + _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3) + _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4) + _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5) + _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6) + _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0) + _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1) + _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2) + _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0) + _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1) + _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan) + _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand) + _REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0) + _REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1) + _REGISTER_CLOCK("lpc32xx-ts", NULL, clk_tsc) + _REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc) + _REGISTER_CLOCK("lpc-net.0", NULL, clk_net) + _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd) + _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd) + _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc) +}; + +static int __init clk_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); + + /* + * Setup muxed SYSCLK for HCLK PLL base -this selects the + * parent clock used for the ARM PLL and is used to derive + * the many system clock rates in the device. + */ + if (clk_is_sysclk_mainosc() != 0) + clk_sys.parent = &osc_main; + else + clk_sys.parent = &osc_pll397; + + clk_sys.rate = clk_sys.parent->rate; + + /* Compute the current ARM PLL and USB PLL frequencies */ + local_update_armpll_rate(); + + /* Compute HCLK and PCLK bus rates */ + clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div(); + clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div(); + + /* + * Enable system clocks - this step is somewhat formal, as the + * clocks are already running, but it does get the clock data + * inline with the actual system state. Never disable these + * clocks as they will only stop if the system is going to sleep. + * In that case, the chip/system power management functions will + * handle clock gating. + */ + if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk)) + printk(KERN_ERR "Error enabling system HCLK and PCLK\n"); + + /* + * Timers 0 and 1 were enabled and are being used by the high + * resolution tick function prior to this driver being initialized. + * Tag them now as used. + */ + if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1)) + printk(KERN_ERR "Error enabling timer tick clocks\n"); + + return 0; +} +core_initcall(clk_init); + diff --git a/arch/arm/mach-lpc32xx/clock.h b/arch/arm/mach-lpc32xx/clock.h new file mode 100644 index 000000000000..c0a8434307f7 --- /dev/null +++ b/arch/arm/mach-lpc32xx/clock.h @@ -0,0 +1,38 @@ +/* + * arch/arm/mach-lpc32xx/clock.h + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LPC32XX_CLOCK_H +#define __LPC32XX_CLOCK_H + +struct clk { + struct list_head node; + struct clk *parent; + u32 rate; + u32 usecount; + + int (*set_rate) (struct clk *, unsigned long); + unsigned long (*round_rate) (struct clk *, unsigned long); + unsigned long (*get_rate) (struct clk *clk); + int (*enable) (struct clk *, int); + + /* Register address and bit mask for simple clocks */ + void __iomem *enable_reg; + u32 enable_mask; +}; + +#endif diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c new file mode 100644 index 000000000000..ee24dc28e93e --- /dev/null +++ b/arch/arm/mach-lpc32xx/common.c @@ -0,0 +1,271 @@ +/* + * arch/arm/mach-lpc32xx/common.c + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/err.h> +#include <linux/i2c.h> +#include <linux/i2c-pnx.h> +#include <linux/io.h> + +#include <asm/mach/map.h> + +#include <mach/i2c.h> +#include <mach/hardware.h> +#include <mach/platform.h> +#include "common.h" + +/* + * Watchdog timer + */ +static struct resource watchdog_resources[] = { + [0] = { + .start = LPC32XX_WDTIM_BASE, + .end = LPC32XX_WDTIM_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device lpc32xx_watchdog_device = { + .name = "pnx4008-watchdog", + .id = -1, + .num_resources = ARRAY_SIZE(watchdog_resources), + .resource = watchdog_resources, +}; + +/* + * I2C busses + */ +static struct i2c_pnx_data i2c0_data = { + .name = I2C_CHIP_NAME "1", + .base = LPC32XX_I2C1_BASE, + .irq = IRQ_LPC32XX_I2C_1, +}; + +static struct i2c_pnx_data i2c1_data = { + .name = I2C_CHIP_NAME "2", + .base = LPC32XX_I2C2_BASE, + .irq = IRQ_LPC32XX_I2C_2, +}; + +static struct i2c_pnx_data i2c2_data = { + .name = "USB-I2C", + .base = LPC32XX_OTG_I2C_BASE, + .irq = IRQ_LPC32XX_USB_I2C, +}; + +struct platform_device lpc32xx_i2c0_device = { + .name = "pnx-i2c", + .id = 0, + .dev = { + .platform_data = &i2c0_data, + }, +}; + +struct platform_device lpc32xx_i2c1_device = { + .name = "pnx-i2c", + .id = 1, + .dev = { + .platform_data = &i2c1_data, + }, +}; + +struct platform_device lpc32xx_i2c2_device = { + .name = "pnx-i2c", + .id = 2, + .dev = { + .platform_data = &i2c2_data, + }, +}; + +/* + * Returns the unique ID for the device + */ +void lpc32xx_get_uid(u32 devid[4]) +{ + int i; + + for (i = 0; i < 4; i++) + devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2)); +} + +/* + * Returns SYSCLK source + * 0 = PLL397, 1 = main oscillator + */ +int clk_is_sysclk_mainosc(void) +{ + if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) & + LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0) + return 1; + + return 0; +} + +/* + * System reset via the watchdog timer + */ +void lpc32xx_watchdog_reset(void) +{ + /* Make sure WDT clocks are enabled */ + __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN, + LPC32XX_CLKPWR_TIMER_CLK_CTRL); + + /* Instant assert of RESETOUT_N with pulse length 1mS */ + __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18)); + __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC)); +} + +/* + * Detects and returns IRAM size for the device variation + */ +#define LPC32XX_IRAM_BANK_SIZE SZ_128K +static u32 iram_size; +u32 lpc32xx_return_iram_size(void) +{ + if (iram_size == 0) { + u32 savedval1, savedval2; + void __iomem *iramptr1, *iramptr2; + + iramptr1 = io_p2v(LPC32XX_IRAM_BASE); + iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE); + savedval1 = __raw_readl(iramptr1); + savedval2 = __raw_readl(iramptr2); + + if (savedval1 == savedval2) { + __raw_writel(savedval2 + 1, iramptr2); + if (__raw_readl(iramptr1) == savedval2 + 1) + iram_size = LPC32XX_IRAM_BANK_SIZE; + else + iram_size = LPC32XX_IRAM_BANK_SIZE * 2; + __raw_writel(savedval2, iramptr2); + } else + iram_size = LPC32XX_IRAM_BANK_SIZE * 2; + } + + return iram_size; +} + +/* + * Computes PLL rate from PLL register and input clock + */ +u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup) +{ + u32 ilfreq, p, m, n, fcco, fref, cfreq; + int mode; + + /* + * PLL requirements + * ifreq must be >= 1MHz and <= 20MHz + * FCCO must be >= 156MHz and <= 320MHz + * FREF must be >= 1MHz and <= 27MHz + * Assume the passed input data is not valid + */ + + ilfreq = ifreq; + m = pllsetup->pll_m; + n = pllsetup->pll_n; + p = pllsetup->pll_p; + + mode = (pllsetup->cco_bypass_b15 << 2) | + (pllsetup->direct_output_b14 << 1) | + pllsetup->fdbk_div_ctrl_b13; + + switch (mode) { + case 0x0: /* Non-integer mode */ + cfreq = (m * ilfreq) / (2 * p * n); + fcco = (m * ilfreq) / n; + fref = ilfreq / n; + break; + + case 0x1: /* integer mode */ + cfreq = (m * ilfreq) / n; + fcco = (m * ilfreq) / (n * 2 * p); + fref = ilfreq / n; + break; + + case 0x2: + case 0x3: /* Direct mode */ + cfreq = (m * ilfreq) / n; + fcco = cfreq; + fref = ilfreq / n; + break; + + case 0x4: + case 0x5: /* Bypass mode */ + cfreq = ilfreq / (2 * p); + fcco = 156000000; + fref = 1000000; + break; + + case 0x6: + case 0x7: /* Direct bypass mode */ + default: + cfreq = ilfreq; + fcco = 156000000; + fref = 1000000; + break; + } + + if (fcco < 156000000 || fcco > 320000000) + cfreq = 0; + + if (fref < 1000000 || fref > 27000000) + cfreq = 0; + + return (u32) cfreq; +} + +u32 clk_get_pclk_div(void) +{ + return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F); +} + +static struct map_desc lpc32xx_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(LPC32XX_AHB0_START), + .pfn = __phys_to_pfn(LPC32XX_AHB0_START), + .length = LPC32XX_AHB0_SIZE, + .type = MT_DEVICE + }, + { + .virtual = IO_ADDRESS(LPC32XX_AHB1_START), + .pfn = __phys_to_pfn(LPC32XX_AHB1_START), + .length = LPC32XX_AHB1_SIZE, + .type = MT_DEVICE + }, + { + .virtual = IO_ADDRESS(LPC32XX_FABAPB_START), + .pfn = __phys_to_pfn(LPC32XX_FABAPB_START), + .length = LPC32XX_FABAPB_SIZE, + .type = MT_DEVICE + }, + { + .virtual = IO_ADDRESS(LPC32XX_IRAM_BASE), + .pfn = __phys_to_pfn(LPC32XX_IRAM_BASE), + .length = (LPC32XX_IRAM_BANK_SIZE * 2), + .type = MT_DEVICE + }, +}; + +void __init lpc32xx_map_io(void) +{ + iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc)); +} diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h new file mode 100644 index 000000000000..f82211fd80c1 --- /dev/null +++ b/arch/arm/mach-lpc32xx/common.h @@ -0,0 +1,73 @@ +/* + * arch/arm/mach-lpc32xx/common.h + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2009-2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LPC32XX_COMMON_H +#define __LPC32XX_COMMON_H + +#include <linux/platform_device.h> + +/* + * Arch specific platform device structures + */ +extern struct platform_device lpc32xx_watchdog_device; +extern struct platform_device lpc32xx_i2c0_device; +extern struct platform_device lpc32xx_i2c1_device; +extern struct platform_device lpc32xx_i2c2_device; + +/* + * Other arch specific structures and functions + */ +extern struct sys_timer lpc32xx_timer; +extern void __init lpc32xx_init_irq(void); +extern void __init lpc32xx_map_io(void); +extern void __init lpc32xx_serial_init(void); +extern void __init lpc32xx_gpio_init(void); + +/* + * Structure used for setting up and querying the PLLS + */ +struct clk_pll_setup { + int analog_on; + int cco_bypass_b15; + int direct_output_b14; + int fdbk_div_ctrl_b13; + int pll_p; + int pll_n; + u32 pll_m; +}; + +extern int clk_is_sysclk_mainosc(void); +extern u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup); +extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval); +extern u32 clk_get_pclk_div(void); + +/* + * Returns the LPC32xx unique 128-bit chip ID + */ +extern void lpc32xx_get_uid(u32 devid[4]); + +extern void lpc32xx_watchdog_reset(void); +extern u32 lpc32xx_return_iram_size(void); + +/* + * Pointers used for sizing and copying suspend function data + */ +extern int lpc32xx_sys_suspend(void); +extern int lpc32xx_sys_suspend_sz; + +#endif diff --git a/arch/arm/mach-lpc32xx/gpiolib.c b/arch/arm/mach-lpc32xx/gpiolib.c new file mode 100644 index 000000000000..69061ea8997a --- /dev/null +++ b/arch/arm/mach-lpc32xx/gpiolib.c @@ -0,0 +1,446 @@ +/* + * arch/arm/mach-lpc32xx/gpiolib.c + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/errno.h> +#include <linux/gpio.h> + +#include <mach/hardware.h> +#include <mach/platform.h> +#include "common.h" + +#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000) +#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004) +#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008) +#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C) +#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010) +#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014) +#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018) +#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C) +#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020) +#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024) +#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) +#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) +#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) +#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040) +#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044) +#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048) +#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C) +#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050) +#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054) +#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058) +#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060) +#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064) +#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068) +#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C) +#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070) +#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074) +#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078) + +#define GPIO012_PIN_TO_BIT(x) (1 << (x)) +#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25)) +#define GPO3_PIN_TO_BIT(x) (1 << (x)) +#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) +#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x)) +#define GPIO3_PIN_IN_SEL(x, y) ((x) >> GPIO3_PIN_IN_SHIFT(y)) +#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1) +#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) + +struct gpio_regs { + void __iomem *inp_state; + void __iomem *outp_set; + void __iomem *outp_clr; + void __iomem *dir_set; + void __iomem *dir_clr; +}; + +/* + * GPIO names + */ +static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = { + "p0.0", "p0.1", "p0.2", "p0.3", + "p0.4", "p0.5", "p0.6", "p0.7" +}; + +static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = { + "p1.0", "p1.1", "p1.2", "p1.3", + "p1.4", "p1.5", "p1.6", "p1.7", + "p1.8", "p1.9", "p1.10", "p1.11", + "p1.12", "p1.13", "p1.14", "p1.15", + "p1.16", "p1.17", "p1.18", "p1.19", + "p1.20", "p1.21", "p1.22", "p1.23", +}; + +static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = { + "p2.0", "p2.1", "p2.2", "p2.3", + "p2.4", "p2.5", "p2.6", "p2.7", + "p2.8", "p2.9", "p2.10", "p2.11", + "p2.12" +}; + +static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = { + "gpi000", "gpio01", "gpio02", "gpio03", + "gpio04", "gpio05" +}; + +static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = { + "gpi00", "gpi01", "gpi02", "gpi03", + "gpi04", "gpi05", "gpi06", "gpi07", + "gpi08", "gpi09", NULL, NULL, + NULL, NULL, NULL, "gpi15", + "gpi16", "gpi17", "gpi18", "gpi19", + "gpi20", "gpi21", "gpi22", "gpi23", + "gpi24", "gpi25", "gpi26", "gpi27" +}; + +static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = { + "gpo00", "gpo01", "gpo02", "gpo03", + "gpo04", "gpo05", "gpo06", "gpo07", + "gpo08", "gpo09", "gpo10", "gpo11", + "gpo12", "gpo13", "gpo14", "gpo15", + "gpo16", "gpo17", "gpo18", "gpo19", + "gpo20", "gpo21", "gpo22", "gpo23" +}; + +static struct gpio_regs gpio_grp_regs_p0 = { + .inp_state = LPC32XX_GPIO_P0_INP_STATE, + .outp_set = LPC32XX_GPIO_P0_OUTP_SET, + .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR, + .dir_set = LPC32XX_GPIO_P0_DIR_SET, + .dir_clr = LPC32XX_GPIO_P0_DIR_CLR, +}; + +static struct gpio_regs gpio_grp_regs_p1 = { + .inp_state = LPC32XX_GPIO_P1_INP_STATE, + .outp_set = LPC32XX_GPIO_P1_OUTP_SET, + .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR, + .dir_set = LPC32XX_GPIO_P1_DIR_SET, + .dir_clr = LPC32XX_GPIO_P1_DIR_CLR, +}; + +static struct gpio_regs gpio_grp_regs_p2 = { + .inp_state = LPC32XX_GPIO_P2_INP_STATE, + .outp_set = LPC32XX_GPIO_P2_OUTP_SET, + .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR, + .dir_set = LPC32XX_GPIO_P2_DIR_SET, + .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, +}; + +static struct gpio_regs gpio_grp_regs_p3 = { + .inp_state = LPC32XX_GPIO_P3_INP_STATE, + .outp_set = LPC32XX_GPIO_P3_OUTP_SET, + .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR, + .dir_set = LPC32XX_GPIO_P2_DIR_SET, + .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, +}; + +struct lpc32xx_gpio_chip { + struct gpio_chip chip; + struct gpio_regs *gpio_grp; +}; + +static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio( + struct gpio_chip *gpc) +{ + return container_of(gpc, struct lpc32xx_gpio_chip, chip); +} + +static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, + unsigned pin, int input) +{ + if (input) + __raw_writel(GPIO012_PIN_TO_BIT(pin), + group->gpio_grp->dir_clr); + else + __raw_writel(GPIO012_PIN_TO_BIT(pin), + group->gpio_grp->dir_set); +} + +static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group, + unsigned pin, int input) +{ + u32 u = GPIO3_PIN_TO_BIT(pin); + + if (input) + __raw_writel(u, group->gpio_grp->dir_clr); + else + __raw_writel(u, group->gpio_grp->dir_set); +} + +static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group, + unsigned pin, int high) +{ + if (high) + __raw_writel(GPIO012_PIN_TO_BIT(pin), + group->gpio_grp->outp_set); + else + __raw_writel(GPIO012_PIN_TO_BIT(pin), + group->gpio_grp->outp_clr); +} + +static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group, + unsigned pin, int high) +{ + u32 u = GPIO3_PIN_TO_BIT(pin); + + if (high) + __raw_writel(u, group->gpio_grp->outp_set); + else + __raw_writel(u, group->gpio_grp->outp_clr); +} + +static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group, + unsigned pin, int high) +{ + if (high) + __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); + else + __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); +} + +static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group, + unsigned pin) +{ + return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), + pin); +} + +static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, + unsigned pin) +{ + int state = __raw_readl(group->gpio_grp->inp_state); + + /* + * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped + * to bits 10..14, while GPIOP3-5 is mapped to bit 24. + */ + return GPIO3_PIN_IN_SEL(state, pin); +} + +static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group, + unsigned pin) +{ + return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin); +} + +/* + * GENERIC_GPIO primitives. + */ +static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip, + unsigned pin) +{ + struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); + + __set_gpio_dir_p012(group, pin, 1); + + return 0; +} + +static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip, + unsigned pin) +{ + struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); + + __set_gpio_dir_p3(group, pin, 1); + + return 0; +} + +static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip, + unsigned pin) +{ + return 0; +} + +static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin) +{ + struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); + + return __get_gpio_state_p012(group, pin); +} + +static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin) +{ + struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); + + return __get_gpio_state_p3(group, pin); +} + +static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin) +{ + struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); + + return __get_gpi_state_p3(group, pin); +} + +static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin, + int value) +{ + struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); + + __set_gpio_dir_p012(group, pin, 0); + + return 0; +} + +static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin, + int value) +{ + struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); + + __set_gpio_dir_p3(group, pin, 0); + + return 0; +} + +static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin, + int value) +{ + return 0; +} + +static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin, + int value) +{ + struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); + + __set_gpio_level_p012(group, pin, value); +} + +static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin, + int value) +{ + struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); + + __set_gpio_level_p3(group, pin, value); +} + +static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin, + int value) +{ + struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); + + __set_gpo_level_p3(group, pin, value); +} + +static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin) +{ + if (pin < chip->ngpio) + return 0; + + return -EINVAL; +} + +static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = { + { + .chip = { + .label = "gpio_p0", + .direction_input = lpc32xx_gpio_dir_input_p012, + .get = lpc32xx_gpio_get_value_p012, + .direction_output = lpc32xx_gpio_dir_output_p012, + .set = lpc32xx_gpio_set_value_p012, + .request = lpc32xx_gpio_request, + .base = LPC32XX_GPIO_P0_GRP, + .ngpio = LPC32XX_GPIO_P0_MAX, + .names = gpio_p0_names, + .can_sleep = 0, + }, + .gpio_grp = &gpio_grp_regs_p0, + }, + { + .chip = { + .label = "gpio_p1", + .direction_input = lpc32xx_gpio_dir_input_p012, + .get = lpc32xx_gpio_get_value_p012, + .direction_output = lpc32xx_gpio_dir_output_p012, + .set = lpc32xx_gpio_set_value_p012, + .request = lpc32xx_gpio_request, + .base = LPC32XX_GPIO_P1_GRP, + .ngpio = LPC32XX_GPIO_P1_MAX, + .names = gpio_p1_names, + .can_sleep = 0, + }, + .gpio_grp = &gpio_grp_regs_p1, + }, + { + .chip = { + .label = "gpio_p2", + .direction_input = lpc32xx_gpio_dir_input_p012, + .get = lpc32xx_gpio_get_value_p012, + .direction_output = lpc32xx_gpio_dir_output_p012, + .set = lpc32xx_gpio_set_value_p012, + .request = lpc32xx_gpio_request, + .base = LPC32XX_GPIO_P2_GRP, + .ngpio = LPC32XX_GPIO_P2_MAX, + .names = gpio_p2_names, + .can_sleep = 0, + }, + .gpio_grp = &gpio_grp_regs_p2, + }, + { + .chip = { + .label = "gpio_p3", + .direction_input = lpc32xx_gpio_dir_input_p3, + .get = lpc32xx_gpio_get_value_p3, + .direction_output = lpc32xx_gpio_dir_output_p3, + .set = lpc32xx_gpio_set_value_p3, + .request = lpc32xx_gpio_request, + .base = LPC32XX_GPIO_P3_GRP, + .ngpio = LPC32XX_GPIO_P3_MAX, + .names = gpio_p3_names, + .can_sleep = 0, + }, + .gpio_grp = &gpio_grp_regs_p3, + }, + { + .chip = { + .label = "gpi_p3", + .direction_input = lpc32xx_gpio_dir_in_always, + .get = lpc32xx_gpi_get_value, + .request = lpc32xx_gpio_request, + .base = LPC32XX_GPI_P3_GRP, + .ngpio = LPC32XX_GPI_P3_MAX, + .names = gpi_p3_names, + .can_sleep = 0, + }, + .gpio_grp = &gpio_grp_regs_p3, + }, + { + .chip = { + .label = "gpo_p3", + .direction_output = lpc32xx_gpio_dir_out_always, + .set = lpc32xx_gpo_set_value, + .request = lpc32xx_gpio_request, + .base = LPC32XX_GPO_P3_GRP, + .ngpio = LPC32XX_GPO_P3_MAX, + .names = gpo_p3_names, + .can_sleep = 0, + }, + .gpio_grp = &gpio_grp_regs_p3, + }, +}; + +void __init lpc32xx_gpio_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) + gpiochip_add(&lpc32xx_gpiochip[i].chip); +} diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/mach-lpc32xx/include/mach/clkdev.h index 1ac4e1682e5c..9bf0637e29ce 100644 --- a/arch/arm/plat-mxc/include/mach/board-pcm043.h +++ b/arch/arm/mach-lpc32xx/include/mach/clkdev.h @@ -1,5 +1,9 @@ /* - * Copyright (C) 2008 Sascha Hauer, Pengutronix + * arch/arm/mach-lpc32xx/include/mach/clkdev.h + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -10,13 +14,12 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__ -#define __ASM_ARCH_MXC_BOARD_PCM043_H__ +#ifndef __ASM_ARCH_CLKDEV_H +#define __ASM_ARCH_CLKDEV_H + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) -#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */ +#endif diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S index 383f1c04df06..621744d6b152 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h +++ b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S @@ -1,5 +1,9 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved + * arch/arm/mach-lpc32xx/include/mach/debug-macro.S + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -10,13 +14,18 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__ -#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__ +/* + * Debug output is hardcoded to standard UART 5 +*/ + + .macro addruart,rx, tmp + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =0x40090000 + ldrne \rx, =0xF4090000 + .endm -#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */ +#define UART_SHIFT 2 +#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S new file mode 100644 index 000000000000..870227c96602 --- /dev/null +++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S @@ -0,0 +1,47 @@ +/* + * arch/arm/mach-lpc32xx/include/mach/entry-macro.S + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mach/hardware.h> +#include <mach/platform.h> + +#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8 + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE) + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + +/* + * Return IRQ number in irqnr. Also return processor Z flag status in CPSR + * as set if an interrupt is pending. + */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS] + clz \irqnr, \irqstat + rsb \irqnr, \irqnr, #31 + teq \irqstat, #0 + .endm + + .macro irq_prio_table + .endm + diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h new file mode 100644 index 000000000000..67d03da1eee9 --- /dev/null +++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h @@ -0,0 +1,74 @@ +/* + * arch/arm/mach-lpc32xx/include/mach/gpio.h + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#include <asm-generic/gpio.h> + +/* + * Note! + * Muxed GP pins need to be setup to the GP state in the board level + * code prior to using this driver. + * GPI pins : 28xP3 group + * GPO pins : 24xP3 group + * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group + */ + +#define LPC32XX_GPIO_P0_MAX 8 +#define LPC32XX_GPIO_P1_MAX 24 +#define LPC32XX_GPIO_P2_MAX 13 +#define LPC32XX_GPIO_P3_MAX 6 +#define LPC32XX_GPI_P3_MAX 28 +#define LPC32XX_GPO_P3_MAX 24 + +#define LPC32XX_GPIO_P0_GRP 0 +#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX) +#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX) +#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX) +#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX) +#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX) + +/* + * A specific GPIO can be selected with this macro + * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) + * See the LPC32x0 User's guide for GPIO group numbers + */ +#define LPC32XX_GPIO(x, y) ((x) + (y)) + +static inline int gpio_get_value(unsigned gpio) +{ + return __gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + __gpio_set_value(gpio, value); +} + +static inline int gpio_cansleep(unsigned gpio) +{ + return __gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(unsigned gpio) +{ + return __gpio_to_irq(gpio); +} + +#endif diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h new file mode 100644 index 000000000000..33e1dde37bd9 --- /dev/null +++ b/arch/arm/mach-lpc32xx/include/mach/hardware.h @@ -0,0 +1,34 @@ +/* + * arch/arm/mach-lpc32xx/include/mach/hardware.h + * + * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* + * Start of virtual addresses for IO devices + */ +#define IO_BASE 0xF0000000 + +/* + * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 + */ +#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ + IO_BASE) + +#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x)) +#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff)) + +#endif diff --git a/arch/arm/mach-lpc32xx/include/mach/i2c.h b/arch/arm/mach-lpc32xx/include/mach/i2c.h new file mode 100644 index 000000000000..034dc9286bcc --- /dev/null +++ b/arch/arm/mach-lpc32xx/include/mach/i2c.h @@ -0,0 +1,63 @@ +/* + * PNX4008-specific tweaks for I2C IP3204 block + * + * Author: Vitaly Wool <vwool@ru.mvista.com> + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef __ASM_ARCH_I2C_H +#define __ASM_ARCH_I2C_H + +enum { + mstatus_tdi = 0x00000001, + mstatus_afi = 0x00000002, + mstatus_nai = 0x00000004, + mstatus_drmi = 0x00000008, + mstatus_active = 0x00000020, + mstatus_scl = 0x00000040, + mstatus_sda = 0x00000080, + mstatus_rff = 0x00000100, + mstatus_rfe = 0x00000200, + mstatus_tff = 0x00000400, + mstatus_tfe = 0x00000800, +}; + +enum { + mcntrl_tdie = 0x00000001, + mcntrl_afie = 0x00000002, + mcntrl_naie = 0x00000004, + mcntrl_drmie = 0x00000008, + mcntrl_daie = 0x00000020, + mcntrl_rffie = 0x00000040, + mcntrl_tffie = 0x00000080, + mcntrl_reset = 0x00000100, + mcntrl_cdbmode = 0x00000400, +}; + +enum { + rw_bit = 1 << 0, + start_bit = 1 << 8, + stop_bit = 1 << 9, +}; + +#define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */ +#define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */ +#define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */ +#define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */ +#define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */ +#define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */ +#define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */ +#define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */ +#define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */ +#define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */ +#define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */ +#define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */ +#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */ + +#define I2C_CHIP_NAME "PNX4008-I2C" + +#endif /* __ASM_ARCH_I2C_H */ diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/mach-lpc32xx/include/mach/io.h index 13411709b13a..9b59ab5cef89 100644 --- a/arch/arm/plat-mxc/include/mach/board-pcm037.h +++ b/arch/arm/mach-lpc32xx/include/mach/io.h @@ -1,5 +1,9 @@ /* - * Copyright (C) 2008 Sascha Hauer, Pengutronix + * arch/arm/mach-lpc32xx/include/mach/io.h + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -10,13 +14,14 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__ -#define __ASM_ARCH_MXC_BOARD_PCM037_H__ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) -#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */ +#endif diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h new file mode 100644 index 000000000000..2667f52e3b04 --- /dev/null +++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h @@ -0,0 +1,117 @@ +/* + * arch/arm/mach-lpc32xx/include/mach/irqs.h + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARM_ARCH_IRQS_H +#define __ASM_ARM_ARCH_IRQS_H + +#define LPC32XX_SIC1_IRQ(n) (32 + (n)) +#define LPC32XX_SIC2_IRQ(n) (64 + (n)) + +/* + * MIC interrupts + */ +#define IRQ_LPC32XX_SUB1IRQ 0 +#define IRQ_LPC32XX_SUB2IRQ 1 +#define IRQ_LPC32XX_PWM3 3 +#define IRQ_LPC32XX_PWM4 4 +#define IRQ_LPC32XX_HSTIMER 5 +#define IRQ_LPC32XX_WATCH 6 +#define IRQ_LPC32XX_UART_IIR3 7 +#define IRQ_LPC32XX_UART_IIR4 8 +#define IRQ_LPC32XX_UART_IIR5 9 +#define IRQ_LPC32XX_UART_IIR6 10 +#define IRQ_LPC32XX_FLASH 11 +#define IRQ_LPC32XX_SD1 13 +#define IRQ_LPC32XX_LCD 14 +#define IRQ_LPC32XX_SD0 15 +#define IRQ_LPC32XX_TIMER0 16 +#define IRQ_LPC32XX_TIMER1 17 +#define IRQ_LPC32XX_TIMER2 18 +#define IRQ_LPC32XX_TIMER3 19 +#define IRQ_LPC32XX_SSP0 20 +#define IRQ_LPC32XX_SSP1 21 +#define IRQ_LPC32XX_I2S0 22 +#define IRQ_LPC32XX_I2S1 23 +#define IRQ_LPC32XX_UART_IIR7 24 +#define IRQ_LPC32XX_UART_IIR2 25 +#define IRQ_LPC32XX_UART_IIR1 26 +#define IRQ_LPC32XX_MSTIMER 27 +#define IRQ_LPC32XX_DMA 28 +#define IRQ_LPC32XX_ETHERNET 29 +#define IRQ_LPC32XX_SUB1FIQ 30 +#define IRQ_LPC32XX_SUB2FIQ 31 + +/* + * SIC1 interrupts start at offset 32 + */ +#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1) +#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2) +#define IRQ_LPC32XX_GPI_11 LPC32XX_SIC1_IRQ(4) +#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6) +#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7) +#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8) +#define IRQ_LPC32XX_SPI2 LPC32XX_SIC1_IRQ(12) +#define IRQ_LPC32XX_PLLUSB LPC32XX_SIC1_IRQ(13) +#define IRQ_LPC32XX_PLLHCLK LPC32XX_SIC1_IRQ(14) +#define IRQ_LPC32XX_PLL397 LPC32XX_SIC1_IRQ(17) +#define IRQ_LPC32XX_I2C_2 LPC32XX_SIC1_IRQ(18) +#define IRQ_LPC32XX_I2C_1 LPC32XX_SIC1_IRQ(19) +#define IRQ_LPC32XX_RTC LPC32XX_SIC1_IRQ(20) +#define IRQ_LPC32XX_KEY LPC32XX_SIC1_IRQ(22) +#define IRQ_LPC32XX_SPI1 LPC32XX_SIC1_IRQ(23) +#define IRQ_LPC32XX_SW LPC32XX_SIC1_IRQ(24) +#define IRQ_LPC32XX_USB_OTG_TIMER LPC32XX_SIC1_IRQ(25) +#define IRQ_LPC32XX_USB_OTG_ATX LPC32XX_SIC1_IRQ(26) +#define IRQ_LPC32XX_USB_HOST LPC32XX_SIC1_IRQ(27) +#define IRQ_LPC32XX_USB_DEV_DMA LPC32XX_SIC1_IRQ(28) +#define IRQ_LPC32XX_USB_DEV_LP LPC32XX_SIC1_IRQ(29) +#define IRQ_LPC32XX_USB_DEV_HP LPC32XX_SIC1_IRQ(30) +#define IRQ_LPC32XX_USB_I2C LPC32XX_SIC1_IRQ(31) + +/* + * SIC2 interrupts start at offset 64 + */ +#define IRQ_LPC32XX_GPIO_00 LPC32XX_SIC2_IRQ(0) +#define IRQ_LPC32XX_GPIO_01 LPC32XX_SIC2_IRQ(1) +#define IRQ_LPC32XX_GPIO_02 LPC32XX_SIC2_IRQ(2) +#define IRQ_LPC32XX_GPIO_03 LPC32XX_SIC2_IRQ(3) +#define IRQ_LPC32XX_GPIO_04 LPC32XX_SIC2_IRQ(4) +#define IRQ_LPC32XX_GPIO_05 LPC32XX_SIC2_IRQ(5) +#define IRQ_LPC32XX_SPI2_DATAIN LPC32XX_SIC2_IRQ(6) +#define IRQ_LPC32XX_U2_HCTS LPC32XX_SIC2_IRQ(7) +#define IRQ_LPC32XX_P0_P1_IRQ LPC32XX_SIC2_IRQ(8) +#define IRQ_LPC32XX_GPI_08 LPC32XX_SIC2_IRQ(9) +#define IRQ_LPC32XX_GPI_09 LPC32XX_SIC2_IRQ(10) +#define IRQ_LPC32XX_GPI_19 LPC32XX_SIC2_IRQ(11) +#define IRQ_LPC32XX_U7_HCTS LPC32XX_SIC2_IRQ(12) +#define IRQ_LPC32XX_GPI_07 LPC32XX_SIC2_IRQ(15) +#define IRQ_LPC32XX_SDIO LPC32XX_SIC2_IRQ(18) +#define IRQ_LPC32XX_U5_RX LPC32XX_SIC2_IRQ(19) +#define IRQ_LPC32XX_SPI1_DATAIN LPC32XX_SIC2_IRQ(20) +#define IRQ_LPC32XX_GPI_00 LPC32XX_SIC2_IRQ(22) +#define IRQ_LPC32XX_GPI_01 LPC32XX_SIC2_IRQ(23) +#define IRQ_LPC32XX_GPI_02 LPC32XX_SIC2_IRQ(24) +#define IRQ_LPC32XX_GPI_03 LPC32XX_SIC2_IRQ(25) +#define IRQ_LPC32XX_GPI_04 LPC32XX_SIC2_IRQ(26) +#define IRQ_LPC32XX_GPI_05 LPC32XX_SIC2_IRQ(27) +#define IRQ_LPC32XX_GPI_06 LPC32XX_SIC2_IRQ(28) +#define IRQ_LPC32XX_SYSCLK LPC32XX_SIC2_IRQ(31) + +#define NR_IRQS 96 + +#endif diff --git a/arch/arm/mach-lpc32xx/include/mach/memory.h b/arch/arm/mach-lpc32xx/include/mach/memory.h new file mode 100644 index 000000000000..044e1acecbe6 --- /dev/null +++ b/arch/arm/mach-lpc32xx/include/mach/memory.h @@ -0,0 +1,27 @@ +/* + * arch/arm/mach-lpc32xx/include/mach/memory.h + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* + * Physical DRAM offset of bank 0 + */ +#define PHYS_OFFSET UL(0x80000000) + +#endif diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h new file mode 100644 index 000000000000..14ea8d1aadb5 --- /dev/null +++ b/arch/arm/mach-lpc32xx/include/mach/platform.h @@ -0,0 +1,694 @@ +/* + * arch/arm/mach-lpc32xx/include/mach/platform.h + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_PLATFORM_H +#define __ASM_ARCH_PLATFORM_H + +#define _SBF(f, v) ((v) << (f)) +#define _BIT(n) _SBF(n, 1) + +/* + * AHB 0 physical base addresses + */ +#define LPC32XX_SLC_BASE 0x20020000 +#define LPC32XX_SSP0_BASE 0x20084000 +#define LPC32XX_SPI1_BASE 0x20088000 +#define LPC32XX_SSP1_BASE 0x2008C000 +#define LPC32XX_SPI2_BASE 0x20090000 +#define LPC32XX_I2S0_BASE 0x20094000 +#define LPC32XX_SD_BASE 0x20098000 +#define LPC32XX_I2S1_BASE 0x2009C000 +#define LPC32XX_MLC_BASE 0x200A8000 +#define LPC32XX_AHB0_START LPC32XX_SLC_BASE +#define LPC32XX_AHB0_SIZE 0x00089000 + +/* + * AHB 1 physical base addresses + */ +#define LPC32XX_DMA_BASE 0x31000000 +#define LPC32XX_USB_BASE 0x31020000 +#define LPC32XX_USBH_BASE 0x31020000 +#define LPC32XX_USB_OTG_BASE 0x31020000 +#define LPC32XX_OTG_I2C_BASE 0x31020300 +#define LPC32XX_LCD_BASE 0x31040000 +#define LPC32XX_ETHERNET_BASE 0x31060000 +#define LPC32XX_EMC_BASE 0x31080000 +#define LPC32XX_ETB_CFG_BASE 0x310C0000 +#define LPC32XX_ETB_DATA_BASE 0x310E0000 +#define LPC32XX_AHB1_START LPC32XX_DMA_BASE +#define LPC32XX_AHB1_SIZE 0x000E1000 + +/* + * FAB physical base addresses + */ +#define LPC32XX_CLK_PM_BASE 0x40004000 +#define LPC32XX_MIC_BASE 0x40008000 +#define LPC32XX_SIC1_BASE 0x4000C000 +#define LPC32XX_SIC2_BASE 0x40010000 +#define LPC32XX_HS_UART1_BASE 0x40014000 +#define LPC32XX_HS_UART2_BASE 0x40018000 +#define LPC32XX_HS_UART7_BASE 0x4001C000 +#define LPC32XX_RTC_BASE 0x40024000 +#define LPC32XX_RTC_RAM_BASE 0x40024080 +#define LPC32XX_GPIO_BASE 0x40028000 +#define LPC32XX_PWM3_BASE 0x4002C000 +#define LPC32XX_PWM4_BASE 0x40030000 +#define LPC32XX_MSTIM_BASE 0x40034000 +#define LPC32XX_HSTIM_BASE 0x40038000 +#define LPC32XX_WDTIM_BASE 0x4003C000 +#define LPC32XX_DEBUG_CTRL_BASE 0x40040000 +#define LPC32XX_TIMER0_BASE 0x40044000 +#define LPC32XX_ADC_BASE 0x40048000 +#define LPC32XX_TIMER1_BASE 0x4004C000 +#define LPC32XX_KSCAN_BASE 0x40050000 +#define LPC32XX_UART_CTRL_BASE 0x40054000 +#define LPC32XX_TIMER2_BASE 0x40058000 +#define LPC32XX_PWM1_BASE 0x4005C000 +#define LPC32XX_PWM2_BASE 0x4005C004 +#define LPC32XX_TIMER3_BASE 0x40060000 + +/* + * APB physical base addresses + */ +#define LPC32XX_UART3_BASE 0x40080000 +#define LPC32XX_UART4_BASE 0x40088000 +#define LPC32XX_UART5_BASE 0x40090000 +#define LPC32XX_UART6_BASE 0x40098000 +#define LPC32XX_I2C1_BASE 0x400A0000 +#define LPC32XX_I2C2_BASE 0x400A8000 + +/* + * FAB and APB base and sizing + */ +#define LPC32XX_FABAPB_START LPC32XX_CLK_PM_BASE +#define LPC32XX_FABAPB_SIZE 0x000A5000 + +/* + * Internal memory bases and sizes + */ +#define LPC32XX_IRAM_BASE 0x08000000 +#define LPC32XX_IROM_BASE 0x0C000000 + +/* + * External Static Memory Bank Address Space Bases + */ +#define LPC32XX_EMC_CS0_BASE 0xE0000000 +#define LPC32XX_EMC_CS1_BASE 0xE1000000 +#define LPC32XX_EMC_CS2_BASE 0xE2000000 +#define LPC32XX_EMC_CS3_BASE 0xE3000000 + +/* + * External SDRAM Memory Bank Address Space Bases + */ +#define LPC32XX_EMC_DYCS0_BASE 0x80000000 +#define LPC32XX_EMC_DYCS1_BASE 0xA0000000 + +/* + * Clock and crystal information + */ +#define LPC32XX_MAIN_OSC_FREQ 13000000 +#define LPC32XX_CLOCK_OSC_FREQ 32768 + +/* + * Clock and Power control register offsets + */ +#define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\ + (x)) +#define LPC32XX_CLKPWR_DEBUG_CTRL _PMREG(0x000) +#define LPC32XX_CLKPWR_BOOTMAP _PMREG(0x014) +#define LPC32XX_CLKPWR_P01_ER _PMREG(0x018) +#define LPC32XX_CLKPWR_USBCLK_PDIV _PMREG(0x01C) +#define LPC32XX_CLKPWR_INT_ER _PMREG(0x020) +#define LPC32XX_CLKPWR_INT_RS _PMREG(0x024) +#define LPC32XX_CLKPWR_INT_SR _PMREG(0x028) +#define LPC32XX_CLKPWR_INT_AP _PMREG(0x02C) +#define LPC32XX_CLKPWR_PIN_ER _PMREG(0x030) +#define LPC32XX_CLKPWR_PIN_RS _PMREG(0x034) +#define LPC32XX_CLKPWR_PIN_SR _PMREG(0x038) +#define LPC32XX_CLKPWR_PIN_AP _PMREG(0x03C) +#define LPC32XX_CLKPWR_HCLK_DIV _PMREG(0x040) +#define LPC32XX_CLKPWR_PWR_CTRL _PMREG(0x044) +#define LPC32XX_CLKPWR_PLL397_CTRL _PMREG(0x048) +#define LPC32XX_CLKPWR_MAIN_OSC_CTRL _PMREG(0x04C) +#define LPC32XX_CLKPWR_SYSCLK_CTRL _PMREG(0x050) +#define LPC32XX_CLKPWR_LCDCLK_CTRL _PMREG(0x054) +#define LPC32XX_CLKPWR_HCLKPLL_CTRL _PMREG(0x058) +#define LPC32XX_CLKPWR_ADC_CLK_CTRL_1 _PMREG(0x060) +#define LPC32XX_CLKPWR_USB_CTRL _PMREG(0x064) +#define LPC32XX_CLKPWR_SDRAMCLK_CTRL _PMREG(0x068) +#define LPC32XX_CLKPWR_DDR_LAP_NOM _PMREG(0x06C) +#define LPC32XX_CLKPWR_DDR_LAP_COUNT _PMREG(0x070) +#define LPC32XX_CLKPWR_DDR_LAP_DELAY _PMREG(0x074) +#define LPC32XX_CLKPWR_SSP_CLK_CTRL _PMREG(0x078) +#define LPC32XX_CLKPWR_I2S_CLK_CTRL _PMREG(0x07C) +#define LPC32XX_CLKPWR_MS_CTRL _PMREG(0x080) +#define LPC32XX_CLKPWR_MACCLK_CTRL _PMREG(0x090) +#define LPC32XX_CLKPWR_TEST_CLK_SEL _PMREG(0x0A4) +#define LPC32XX_CLKPWR_SFW_INT _PMREG(0x0A8) +#define LPC32XX_CLKPWR_I2C_CLK_CTRL _PMREG(0x0AC) +#define LPC32XX_CLKPWR_KEY_CLK_CTRL _PMREG(0x0B0) +#define LPC32XX_CLKPWR_ADC_CLK_CTRL _PMREG(0x0B4) +#define LPC32XX_CLKPWR_PWM_CLK_CTRL _PMREG(0x0B8) +#define LPC32XX_CLKPWR_TIMER_CLK_CTRL _PMREG(0x0BC) +#define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1 _PMREG(0x0C0) +#define LPC32XX_CLKPWR_SPI_CLK_CTRL _PMREG(0x0C4) +#define LPC32XX_CLKPWR_NAND_CLK_CTRL _PMREG(0x0C8) +#define LPC32XX_CLKPWR_UART3_CLK_CTRL _PMREG(0x0D0) +#define LPC32XX_CLKPWR_UART4_CLK_CTRL _PMREG(0x0D4) +#define LPC32XX_CLKPWR_UART5_CLK_CTRL _PMREG(0x0D8) +#define LPC32XX_CLKPWR_UART6_CLK_CTRL _PMREG(0x0DC) +#define LPC32XX_CLKPWR_IRDA_CLK_CTRL _PMREG(0x0E0) +#define LPC32XX_CLKPWR_UART_CLK_CTRL _PMREG(0x0E4) +#define LPC32XX_CLKPWR_DMA_CLK_CTRL _PMREG(0x0E8) +#define LPC32XX_CLKPWR_AUTOCLOCK _PMREG(0x0EC) +#define LPC32XX_CLKPWR_DEVID(x) _PMREG(0x130 + (x)) + +/* + * clkpwr_debug_ctrl register definitions +*/ +#define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT _BIT(4) + +/* + * clkpwr_bootmap register definitions + */ +#define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT _BIT(1) + +/* + * clkpwr_start_gpio register bit definitions + */ +#define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT _BIT(31) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT _BIT(30) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT _BIT(29) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT _BIT(28) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT _BIT(27) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT _BIT(26) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT _BIT(25) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT _BIT(24) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT _BIT(23) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT _BIT(22) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT _BIT(21) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT _BIT(20) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT _BIT(19) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT _BIT(18) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT _BIT(17) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT _BIT(16) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT _BIT(15) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT _BIT(14) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT _BIT(13) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT _BIT(12) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT _BIT(11) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT _BIT(10) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT _BIT(9) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT _BIT(8) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT _BIT(7) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT _BIT(6) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT _BIT(5) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT _BIT(4) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT _BIT(3) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT _BIT(2) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT _BIT(1) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT _BIT(0) + +/* + * clkpwr_usbclk_pdiv register definitions + */ +#define LPC32XX_CLKPWR_USBPDIV_PLL_MASK 0xF + +/* + * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int, + * clkpwr_start_pol_int, register bit definitions + */ +#define LPC32XX_CLKPWR_INTSRC_ADC_BIT _BIT(31) +#define LPC32XX_CLKPWR_INTSRC_TS_P_BIT _BIT(30) +#define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT _BIT(29) +#define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT _BIT(26) +#define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT _BIT(25) +#define LPC32XX_CLKPWR_INTSRC_RTC_BIT _BIT(24) +#define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT _BIT(23) +#define LPC32XX_CLKPWR_INTSRC_USB_BIT _BIT(22) +#define LPC32XX_CLKPWR_INTSRC_I2C_BIT _BIT(21) +#define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT _BIT(20) +#define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT _BIT(19) +#define LPC32XX_CLKPWR_INTSRC_KEY_BIT _BIT(16) +#define LPC32XX_CLKPWR_INTSRC_MAC_BIT _BIT(7) +#define LPC32XX_CLKPWR_INTSRC_P0P1_BIT _BIT(6) +#define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT _BIT(5) +#define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT _BIT(4) +#define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT _BIT(3) +#define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT _BIT(2) +#define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT _BIT(1) +#define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT _BIT(0) + +/* + * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin, + * clkpwr_start_pol_pin register bit definitions + */ +#define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT _BIT(31) +#define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT _BIT(30) +#define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT _BIT(28) +#define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT _BIT(26) +#define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT _BIT(25) +#define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT _BIT(24) +#define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT _BIT(23) +#define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT _BIT(22) +#define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT _BIT(21) +#define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT _BIT(18) +#define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT _BIT(17) +#define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT _BIT(16) +#define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT _BIT(15) +#define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT _BIT(14) +#define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT _BIT(13) +#define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT _BIT(12) +#define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT _BIT(11) +#define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT _BIT(10) +#define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT _BIT(9) +#define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT _BIT(8) +#define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT _BIT(7) +#define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT _BIT(6) +#define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT _BIT(5) +#define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT _BIT(4) +#define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT _BIT(3) + +/* + * clkpwr_hclk_div register definitions + */ +#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP (0x0 << 7) +#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM (0x1 << 7) +#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF (0x2 << 7) +#define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n) (((n) & 0x1F) << 2) +#define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n) ((n) & 0x3) + +/* + * clkpwr_pwr_ctrl register definitions + */ +#define LPC32XX_CLKPWR_CTRL_FORCE_PCLK _BIT(10) +#define LPC32XX_CLKPWR_SDRAM_SELF_RFSH _BIT(9) +#define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH _BIT(8) +#define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH _BIT(7) +#define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT _BIT(5) +#define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT _BIT(4) +#define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN _BIT(3) +#define LPC32XX_CLKPWR_SELECT_RUN_MODE _BIT(2) +#define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN _BIT(1) +#define LPC32XX_CLKPWR_STOP_MODE_CTRL _BIT(0) + +/* + * clkpwr_pll397_ctrl register definitions + */ +#define LPC32XX_CLKPWR_PLL397_MSLOCK_STS _BIT(10) +#define LPC32XX_CLKPWR_PLL397_BYPASS _BIT(9) +#define LPC32XX_CLKPWR_PLL397_BIAS_NORM 0x000 +#define LPC32XX_CLKPWR_PLL397_BIAS_N12_5 0x040 +#define LPC32XX_CLKPWR_PLL397_BIAS_N25 0x080 +#define LPC32XX_CLKPWR_PLL397_BIAS_N37_5 0x0C0 +#define LPC32XX_CLKPWR_PLL397_BIAS_P12_5 0x100 +#define LPC32XX_CLKPWR_PLL397_BIAS_P25 0x140 +#define LPC32XX_CLKPWR_PLL397_BIAS_P37_5 0x180 +#define LPC32XX_CLKPWR_PLL397_BIAS_P50 0x1C0 +#define LPC32XX_CLKPWR_PLL397_BIAS_MASK 0x1C0 +#define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS _BIT(1) +#define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS _BIT(0) + +/* + * clkpwr_main_osc_ctrl register definitions + */ +#define LPC32XX_CLKPWR_MOSC_ADD_CAP(n) (((n) & 0x7F) << 2) +#define LPC32XX_CLKPWR_MOSC_CAP_MASK (0x7F << 2) +#define LPC32XX_CLKPWR_TEST_MODE _BIT(1) +#define LPC32XX_CLKPWR_MOSC_DISABLE _BIT(0) + +/* + * clkpwr_sysclk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n) (((n) & 0x3FF) << 2) +#define LPC32XX_CLKPWR_SYSCTRL_BP_MASK (0x3FF << 2) +#define LPC32XX_CLKPWR_SYSCTRL_USEPLL397 _BIT(1) +#define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX _BIT(0) + +/* + * clkpwr_lcdclk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12 0x000 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16 0x040 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15 0x080 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24 0x0C0 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M 0x100 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C 0x140 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M 0x180 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C 0x1C0 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK 0x01C0 +#define LPC32XX_CLKPWR_LCDCTRL_CLK_EN 0x020 +#define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n) ((n - 1) & 0x1F) +#define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK 0x001F + +/* + * clkpwr_hclkpll_ctrl register definitions + */ +#define LPC32XX_CLKPWR_HCLKPLL_POWER_UP _BIT(16) +#define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS _BIT(15) +#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS _BIT(14) +#define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK _BIT(13) +#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n) (((n) & 0x3) << 11) +#define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n) (((n) & 0x3) << 9) +#define LPC32XX_CLKPWR_HCLKPLL_PLLM(n) (((n) & 0xFF) << 1) +#define LPC32XX_CLKPWR_HCLKPLL_PLL_STS _BIT(0) + +/* + * clkpwr_adc_clk_ctrl_1 register definitions + */ +#define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n) (((n) & 0xFF) << 0) +#define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL _BIT(8) + +/* + * clkpwr_usb_ctrl register definitions + */ +#define LPC32XX_CLKPWR_USBCTRL_HCLK_EN _BIT(24) +#define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN _BIT(23) +#define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN _BIT(22) +#define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN _BIT(21) +#define LPC32XX_CLKPWR_USBCTRL_PU_ADD (0x0 << 19) +#define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER (0x1 << 19) +#define LPC32XX_CLKPWR_USBCTRL_PD_ADD (0x3 << 19) +#define LPC32XX_CLKPWR_USBCTRL_CLK_EN2 _BIT(18) +#define LPC32XX_CLKPWR_USBCTRL_CLK_EN1 _BIT(17) +#define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP _BIT(16) +#define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS _BIT(15) +#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS _BIT(14) +#define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK _BIT(13) +#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11) +#define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n) (((n) & 0x3) << 9) +#define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1) +#define LPC32XX_CLKPWR_USBCTRL_PLL_STS _BIT(0) + +/* + * clkpwr_sdramclk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK _BIT(22) +#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW _BIT(21) +#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT _BIT(20) +#define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET _BIT(19) +#define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n) (((n) & 0x1F) << 14) +#define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS _BIT(13) +#define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n) (((n) & 0x7) << 10) +#define LPC32XX_CLKPWR_SDRCLK_USE_CAL _BIT(9) +#define LPC32XX_CLKPWR_SDRCLK_DO_CAL _BIT(8) +#define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC _BIT(7) +#define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n) (((n) & 0x1F) << 2) +#define LPC32XX_CLKPWR_SDRCLK_USE_DDR _BIT(1) +#define LPC32XX_CLKPWR_SDRCLK_CLK_DIS _BIT(0) + +/* + * clkpwr_ssp_blk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX _BIT(5) +#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX _BIT(4) +#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX _BIT(3) +#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX _BIT(2) +#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN _BIT(1) +#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN _BIT(0) + +/* + * clkpwr_i2s_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX _BIT(6) +#define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX _BIT(5) +#define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA _BIT(4) +#define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX _BIT(3) +#define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX _BIT(2) +#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN _BIT(1) +#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN _BIT(0) + +/* + * clkpwr_ms_ctrl register definitions + */ +#define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS _BIT(10) +#define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN _BIT(9) +#define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS _BIT(8) +#define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS _BIT(7) +#define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS _BIT(6) +#define LPC32XX_CLKPWR_MSCARD_SDCARD_EN _BIT(5) +#define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n) ((n) & 0xF) + +/* + * clkpwr_macclk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS 0x00 +#define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS 0x08 +#define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS 0x18 +#define LPC32XX_CLKPWR_MACCTRL_PINS_MSK 0x18 +#define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN _BIT(2) +#define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN _BIT(1) +#define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN _BIT(0) + +/* + * clkpwr_test_clk_sel register definitions + */ +#define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK (0x0 << 5) +#define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC (0x1 << 5) +#define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC (0x2 << 5) +#define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK (0x3 << 5) +#define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN _BIT(4) +#define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK (0x0 << 1) +#define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK (0x1 << 1) +#define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK (0x2 << 1) +#define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC (0x5 << 1) +#define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397 (0x7 << 1) +#define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK (0x7 << 1) +#define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN _BIT(0) + +/* + * clkpwr_sw_int register definitions + */ +#define LPC32XX_CLKPWR_SW_INT(n) (_BIT(0) | (((n) & 0x7F) << 1)) +#define LPC32XX_CLKPWR_SW_GET_ARG(n) (((n) & 0xFE) >> 1) + +/* + * clkpwr_i2c_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE _BIT(4) +#define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE _BIT(3) +#define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE _BIT(2) +#define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN _BIT(1) +#define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN _BIT(0) + +/* + * clkpwr_key_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN 0x1 + +/* + * clkpwr_adc_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN 0x1 + +/* + * clkpwr_pwm_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n) (((n) & 0xF) << 8) +#define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n) (((n) & 0xF) << 4) +#define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK 0x8 +#define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN 0x4 +#define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK 0x2 +#define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN 0x1 + +/* + * clkpwr_timer_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN 0x2 +#define LPC32XX_CLKPWR_PWMCLK_WDOG_EN 0x1 + +/* + * clkpwr_timers_pwms_clk_ctrl_1 register definitions + */ +#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20 +#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10 +#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08 +#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN 0x04 +#define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN 0x02 +#define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN 0x01 + +/* + * clkpwr_spi_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO 0x80 +#define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK 0x40 +#define LPC32XX_CLKPWR_SPICLK_USE_SPI2 0x20 +#define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN 0x10 +#define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO 0x08 +#define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK 0x04 +#define LPC32XX_CLKPWR_SPICLK_USE_SPI1 0x02 +#define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN 0x01 + +/* + * clkpwr_nand_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC 0x20 +#define LPC32XX_CLKPWR_NANDCLK_DMA_RNB 0x10 +#define LPC32XX_CLKPWR_NANDCLK_DMA_INT 0x08 +#define LPC32XX_CLKPWR_NANDCLK_SEL_SLC 0x04 +#define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN 0x02 +#define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN 0x01 + +/* + * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl + * and clkpwr_uart6_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_UART_Y_DIV(y) ((y) & 0xFF) +#define LPC32XX_CLKPWR_UART_X_DIV(x) (((x) & 0xFF) << 8) +#define LPC32XX_CLKPWR_UART_USE_HCLK _BIT(16) + +/* + * clkpwr_irda_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_IRDA_Y_DIV(y) ((y) & 0xFF) +#define LPC32XX_CLKPWR_IRDA_X_DIV(x) (((x) & 0xFF) << 8) + +/* + * clkpwr_uart_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN _BIT(3) +#define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN _BIT(2) +#define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN _BIT(1) +#define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN _BIT(0) + +/* + * clkpwr_dmaclk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN 0x1 + +/* + * clkpwr_autoclock register definitions + */ +#define LPC32XX_CLKPWR_AUTOCLK_USB_EN 0x40 +#define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN 0x02 +#define LPC32XX_CLKPWR_AUTOCLK_IROM_EN 0x01 + +/* + * Interrupt controller register offsets + */ +#define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00) +#define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04) +#define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08) +#define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C) +#define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10) +#define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14) + +/* + * Timer/counter register offsets + */ +#define LCP32XX_TIMER_IR(x) io_p2v((x) + 0x00) +#define LCP32XX_TIMER_TCR(x) io_p2v((x) + 0x04) +#define LCP32XX_TIMER_TC(x) io_p2v((x) + 0x08) +#define LCP32XX_TIMER_PR(x) io_p2v((x) + 0x0C) +#define LCP32XX_TIMER_PC(x) io_p2v((x) + 0x10) +#define LCP32XX_TIMER_MCR(x) io_p2v((x) + 0x14) +#define LCP32XX_TIMER_MR0(x) io_p2v((x) + 0x18) +#define LCP32XX_TIMER_MR1(x) io_p2v((x) + 0x1C) +#define LCP32XX_TIMER_MR2(x) io_p2v((x) + 0x20) +#define LCP32XX_TIMER_MR3(x) io_p2v((x) + 0x24) +#define LCP32XX_TIMER_CCR(x) io_p2v((x) + 0x28) +#define LCP32XX_TIMER_CR0(x) io_p2v((x) + 0x2C) +#define LCP32XX_TIMER_CR1(x) io_p2v((x) + 0x30) +#define LCP32XX_TIMER_CR2(x) io_p2v((x) + 0x34) +#define LCP32XX_TIMER_CR3(x) io_p2v((x) + 0x38) +#define LCP32XX_TIMER_EMR(x) io_p2v((x) + 0x3C) +#define LCP32XX_TIMER_CTCR(x) io_p2v((x) + 0x70) + +/* + * ir register definitions + */ +#define LCP32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3)) +#define LCP32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3))) + +/* + * tcr register definitions + */ +#define LCP32XX_TIMER_CNTR_TCR_EN 0x1 +#define LCP32XX_TIMER_CNTR_TCR_RESET 0x2 + +/* + * mcr register definitions + */ +#define LCP32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3)) +#define LCP32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1)) +#define LCP32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2)) + +/* + * Standard UART register offsets + */ +#define LPC32XX_UART_DLL_FIFO(x) io_p2v((x) + 0x00) +#define LPC32XX_UART_DLM_IER(x) io_p2v((x) + 0x04) +#define LPC32XX_UART_IIR_FCR(x) io_p2v((x) + 0x08) +#define LPC32XX_UART_LCR(x) io_p2v((x) + 0x0C) +#define LPC32XX_UART_MODEM_CTRL(x) io_p2v((x) + 0x10) +#define LPC32XX_UART_LSR(x) io_p2v((x) + 0x14) +#define LPC32XX_UART_MODEM_STATUS(x) io_p2v((x) + 0x18) +#define LPC32XX_UART_RXLEV(x) io_p2v((x) + 0x1C) + +/* + * UART control structure offsets + */ +#define _UCREG(x) io_p2v(\ + LPC32XX_UART_CTRL_BASE + (x)) +#define LPC32XX_UARTCTL_CTRL _UCREG(0x00) +#define LPC32XX_UARTCTL_CLKMODE _UCREG(0x04) +#define LPC32XX_UARTCTL_CLOOP _UCREG(0x08) + +/* + * ctrl register definitions + */ +#define LPC32XX_UART_U3_MD_CTRL_EN _BIT(11) +#define LPC32XX_UART_IRRX6_INV_EN _BIT(10) +#define LPC32XX_UART_HDPX_EN _BIT(9) +#define LPC32XX_UART_UART6_IRDAMOD_BYPASS _BIT(5) +#define LPC32XX_RT_IRTX6_INV_EN _BIT(4) +#define LPC32XX_RT_IRTX6_INV_MIR_EN _BIT(3) +#define LPC32XX_RT_RX_IRPULSE_3_16_115K _BIT(2) +#define LPC32XX_RT_TX_IRPULSE_3_16_115K _BIT(1) +#define LPC32XX_UART_U5_ROUTE_TO_USB _BIT(0) + +/* + * clkmode register definitions + */ +#define LPC32XX_UART_ENABLED_CLOCKS(n) (((n) >> 16) & 0x7F) +#define LPC32XX_UART_ENABLED_CLOCK(n, u) (((n) >> (16 + (u))) & 0x1) +#define LPC32XX_UART_ENABLED_CLKS_ANY _BIT(14) +#define LPC32XX_UART_CLKMODE_OFF 0x0 +#define LPC32XX_UART_CLKMODE_ON 0x1 +#define LPC32XX_UART_CLKMODE_AUTO 0x2 +#define LPC32XX_UART_CLKMODE_MASK(u) (0x3 << ((((u) - 3) * 2) + 4)) +#define LPC32XX_UART_CLKMODE_LOAD(m, u) ((m) << ((((u) - 3) * 2) + 4)) + +/* + * GPIO Module Register offsets + */ +#define _GPREG(x) io_p2v(LPC32XX_GPIO_BASE + (x)) +#define LPC32XX_GPIO_P_MUX_SET _GPREG(0x100) +#define LPC32XX_GPIO_P_MUX_CLR _GPREG(0x104) +#define LPC32XX_GPIO_P_MUX_STATE _GPREG(0x108) +#define LPC32XX_GPIO_P3_MUX_SET _GPREG(0x110) +#define LPC32XX_GPIO_P3_MUX_CLR _GPREG(0x114) +#define LPC32XX_GPIO_P3_MUX_STATE _GPREG(0x118) +#define LPC32XX_GPIO_P0_MUX_SET _GPREG(0x120) +#define LPC32XX_GPIO_P0_MUX_CLR _GPREG(0x124) +#define LPC32XX_GPIO_P0_MUX_STATE _GPREG(0x128) +#define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130) +#define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134) +#define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138) + +#endif diff --git a/arch/arm/mach-lpc32xx/include/mach/system.h b/arch/arm/mach-lpc32xx/include/mach/system.h new file mode 100644 index 000000000000..df3b0dea4d7b --- /dev/null +++ b/arch/arm/mach-lpc32xx/include/mach/system.h @@ -0,0 +1,52 @@ +/* + * arch/arm/mach-lpc32xx/include/mach/system.h + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +static void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + extern void lpc32xx_watchdog_reset(void); + + switch (mode) { + case 's': + case 'h': + printk(KERN_CRIT "RESET: Rebooting system\n"); + + /* Disable interrupts */ + local_irq_disable(); + + lpc32xx_watchdog_reset(); + break; + + default: + /* Do nothing */ + break; + } + + /* Wait for watchdog to reset system */ + while (1) + ; +} + +#endif diff --git a/arch/arm/mach-lpc32xx/include/mach/timex.h b/arch/arm/mach-lpc32xx/include/mach/timex.h new file mode 100644 index 000000000000..8d4066b16b3f --- /dev/null +++ b/arch/arm/mach-lpc32xx/include/mach/timex.h @@ -0,0 +1,28 @@ +/* + * arch/arm/mach-lpc32xx/include/mach/timex.h + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* + * Rate in Hz of the main system oscillator. This value should match + * the value 'MAIN_OSC_FREQ' in platform.h + */ +#define CLOCK_TICK_RATE 13000000 + +#endif diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h new file mode 100644 index 000000000000..c142487d299a --- /dev/null +++ b/arch/arm/mach-lpc32xx/include/mach/uncompress.h @@ -0,0 +1,60 @@ +/* + * arch/arm/mach-lpc32xx/include/mach/uncompress.h + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARM_ARCH_UNCOMPRESS_H +#define __ASM_ARM_ARCH_UNCOMPRESS_H + +#include <linux/io.h> + +#include <mach/hardware.h> +#include <mach/platform.h> + +/* + * Uncompress output is hardcoded to standard UART 5 + */ + +#define UART_FIFO_CTL_TX_RESET (1 << 2) +#define UART_STATUS_TX_MT (1 << 6) + +#define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x)) + +#define LPC32XX_UART_DLLFIFO_O 0x00 +#define LPC32XX_UART_IIRFCR_O 0x08 +#define LPC32XX_UART_LSR_O 0x14 + +static inline void putc(int ch) +{ + /* Wait for transmit FIFO to empty */ + while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) & + UART_STATUS_TX_MT) == 0) + ; + + __raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O)); +} + +static inline void flush(void) +{ + __raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) | + UART_FIFO_CTL_TX_RESET, _UARTREG(LPC32XX_UART_IIRFCR_O)); +} + +/* NULL functions; we don't presently need them */ +#define arch_decomp_setup() +#define arch_decomp_wdog() + +#endif diff --git a/arch/arm/mach-lpc32xx/include/mach/vmalloc.h b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h new file mode 100644 index 000000000000..d1d936c7236d --- /dev/null +++ b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h @@ -0,0 +1,24 @@ +/* + * arch/arm/mach-lpc32xx/include/mach/vmalloc.h + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H + +#define VMALLOC_END 0xF0000000 + +#endif diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c new file mode 100644 index 000000000000..bd0df26c415b --- /dev/null +++ b/arch/arm/mach-lpc32xx/irq.c @@ -0,0 +1,432 @@ +/* + * arch/arm/mach-lpc32xx/irq.c + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/err.h> +#include <linux/io.h> + +#include <mach/irqs.h> +#include <mach/hardware.h> +#include <mach/platform.h> +#include "common.h" + +/* + * Default value representing the Activation polarity of all internal + * interrupt sources + */ +#define MIC_APR_DEFAULT 0x3FF0EFE0 +#define SIC1_APR_DEFAULT 0xFBD27186 +#define SIC2_APR_DEFAULT 0x801810C0 + +/* + * Default value representing the Activation Type of all internal + * interrupt sources. All are level sensitive. + */ +#define MIC_ATR_DEFAULT 0x00000000 +#define SIC1_ATR_DEFAULT 0x00026000 +#define SIC2_ATR_DEFAULT 0x00000000 + +struct lpc32xx_event_group_regs { + void __iomem *enab_reg; + void __iomem *edge_reg; + void __iomem *maskstat_reg; + void __iomem *rawstat_reg; +}; + +static const struct lpc32xx_event_group_regs lpc32xx_event_int_regs = { + .enab_reg = LPC32XX_CLKPWR_INT_ER, + .edge_reg = LPC32XX_CLKPWR_INT_AP, + .maskstat_reg = LPC32XX_CLKPWR_INT_SR, + .rawstat_reg = LPC32XX_CLKPWR_INT_RS, +}; + +static const struct lpc32xx_event_group_regs lpc32xx_event_pin_regs = { + .enab_reg = LPC32XX_CLKPWR_PIN_ER, + .edge_reg = LPC32XX_CLKPWR_PIN_AP, + .maskstat_reg = LPC32XX_CLKPWR_PIN_SR, + .rawstat_reg = LPC32XX_CLKPWR_PIN_RS, +}; + +struct lpc32xx_event_info { + const struct lpc32xx_event_group_regs *event_group; + u32 mask; +}; + +/* + * Maps an IRQ number to and event mask and register + */ +static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = { + [IRQ_LPC32XX_GPI_08] = { + .event_group = &lpc32xx_event_pin_regs, + .mask = LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT, + }, + [IRQ_LPC32XX_GPI_09] = { + .event_group = &lpc32xx_event_pin_regs, + .mask = LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT, + }, + [IRQ_LPC32XX_GPI_19] = { + .event_group = &lpc32xx_event_pin_regs, + .mask = LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT, + }, + [IRQ_LPC32XX_GPI_07] = { + .event_group = &lpc32xx_event_pin_regs, + .mask = LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT, + }, + [IRQ_LPC32XX_GPI_00] = { + .event_group = &lpc32xx_event_pin_regs, + .mask = LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT, + }, + [IRQ_LPC32XX_GPI_01] = { + .event_group = &lpc32xx_event_pin_regs, + .mask = LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT, + }, + [IRQ_LPC32XX_GPI_02] = { + .event_group = &lpc32xx_event_pin_regs, + .mask = LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT, + }, + [IRQ_LPC32XX_GPI_03] = { + .event_group = &lpc32xx_event_pin_regs, + .mask = LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT, + }, + [IRQ_LPC32XX_GPI_04] = { + .event_group = &lpc32xx_event_pin_regs, + .mask = LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT, + }, + [IRQ_LPC32XX_GPI_05] = { + .event_group = &lpc32xx_event_pin_regs, + .mask = LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT, + }, + [IRQ_LPC32XX_GPI_06] = { + .event_group = &lpc32xx_event_pin_regs, + .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT, + }, + [IRQ_LPC32XX_GPIO_00] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT, + }, + [IRQ_LPC32XX_GPIO_01] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT, + }, + [IRQ_LPC32XX_GPIO_02] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT, + }, + [IRQ_LPC32XX_GPIO_03] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT, + }, + [IRQ_LPC32XX_GPIO_04] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT, + }, + [IRQ_LPC32XX_GPIO_05] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT, + }, + [IRQ_LPC32XX_KEY] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT, + }, + [IRQ_LPC32XX_USB_OTG_ATX] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT, + }, + [IRQ_LPC32XX_USB_HOST] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_USB_BIT, + }, + [IRQ_LPC32XX_RTC] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT, + }, + [IRQ_LPC32XX_MSTIMER] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT, + }, + [IRQ_LPC32XX_TS_AUX] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT, + }, + [IRQ_LPC32XX_TS_P] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT, + }, + [IRQ_LPC32XX_TS_IRQ] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT, + }, +}; + +static void get_controller(unsigned int irq, unsigned int *base, + unsigned int *irqbit) +{ + if (irq < 32) { + *base = LPC32XX_MIC_BASE; + *irqbit = 1 << irq; + } else if (irq < 64) { + *base = LPC32XX_SIC1_BASE; + *irqbit = 1 << (irq - 32); + } else { + *base = LPC32XX_SIC2_BASE; + *irqbit = 1 << (irq - 64); + } +} + +static void lpc32xx_mask_irq(unsigned int irq) +{ + unsigned int reg, ctrl, mask; + + get_controller(irq, &ctrl, &mask); + + reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask; + __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); +} + +static void lpc32xx_unmask_irq(unsigned int irq) +{ + unsigned int reg, ctrl, mask; + + get_controller(irq, &ctrl, &mask); + + reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask; + __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); +} + +static void lpc32xx_ack_irq(unsigned int irq) +{ + unsigned int ctrl, mask; + + get_controller(irq, &ctrl, &mask); + + __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl)); + + /* Also need to clear pending wake event */ + if (lpc32xx_events[irq].mask != 0) + __raw_writel(lpc32xx_events[irq].mask, + lpc32xx_events[irq].event_group->rawstat_reg); +} + +static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level, + int use_edge) +{ + unsigned int reg, ctrl, mask; + + get_controller(irq, &ctrl, &mask); + + /* Activation level, high or low */ + reg = __raw_readl(LPC32XX_INTC_POLAR(ctrl)); + if (use_high_level) + reg |= mask; + else + reg &= ~mask; + __raw_writel(reg, LPC32XX_INTC_POLAR(ctrl)); + + /* Activation type, edge or level */ + reg = __raw_readl(LPC32XX_INTC_ACT_TYPE(ctrl)); + if (use_edge) + reg |= mask; + else + reg &= ~mask; + __raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl)); + + /* Use same polarity for the wake events */ + if (lpc32xx_events[irq].mask != 0) { + reg = __raw_readl(lpc32xx_events[irq].event_group->edge_reg); + + if (use_high_level) + reg |= lpc32xx_events[irq].mask; + else + reg &= ~lpc32xx_events[irq].mask; + + __raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg); + } +} + +static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type) +{ + switch (type) { + case IRQ_TYPE_EDGE_RISING: + /* Rising edge sensitive */ + __lpc32xx_set_irq_type(irq, 1, 1); + break; + + case IRQ_TYPE_EDGE_FALLING: + /* Falling edge sensitive */ + __lpc32xx_set_irq_type(irq, 0, 1); + break; + + case IRQ_TYPE_LEVEL_LOW: + /* Low level sensitive */ + __lpc32xx_set_irq_type(irq, 0, 0); + break; + + case IRQ_TYPE_LEVEL_HIGH: + /* High level sensitive */ + __lpc32xx_set_irq_type(irq, 1, 0); + break; + + /* Other modes are not supported */ + default: + return -EINVAL; + } + + /* Ok to use the level handler for all types */ + set_irq_handler(irq, handle_level_irq); + + return 0; +} + +static int lpc32xx_irq_wake(unsigned int irqno, unsigned int state) +{ + unsigned long eventreg; + + if (lpc32xx_events[irqno].mask != 0) { + eventreg = __raw_readl(lpc32xx_events[irqno]. + event_group->enab_reg); + + if (state) + eventreg |= lpc32xx_events[irqno].mask; + else + eventreg &= ~lpc32xx_events[irqno].mask; + + __raw_writel(eventreg, + lpc32xx_events[irqno].event_group->enab_reg); + + return 0; + } + + /* Clear event */ + __raw_writel(lpc32xx_events[irqno].mask, + lpc32xx_events[irqno].event_group->rawstat_reg); + + return -ENODEV; +} + +static void __init lpc32xx_set_default_mappings(unsigned int apr, + unsigned int atr, unsigned int offset) +{ + unsigned int i; + + /* Set activation levels for each interrupt */ + i = 0; + while (i < 32) { + __lpc32xx_set_irq_type(offset + i, ((apr >> i) & 0x1), + ((atr >> i) & 0x1)); + i++; + } +} + +static struct irq_chip lpc32xx_irq_chip = { + .ack = lpc32xx_ack_irq, + .mask = lpc32xx_mask_irq, + .unmask = lpc32xx_unmask_irq, + .set_type = lpc32xx_set_irq_type, + .set_wake = lpc32xx_irq_wake +}; + +static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc) +{ + unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE)); + + while (ints != 0) { + int irqno = fls(ints) - 1; + + ints &= ~(1 << irqno); + + generic_handle_irq(LPC32XX_SIC1_IRQ(irqno)); + } +} + +static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc) +{ + unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE)); + + while (ints != 0) { + int irqno = fls(ints) - 1; + + ints &= ~(1 << irqno); + + generic_handle_irq(LPC32XX_SIC2_IRQ(irqno)); + } +} + +void __init lpc32xx_init_irq(void) +{ + unsigned int i; + + /* Setup MIC */ + __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE)); + __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_MIC_BASE)); + __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_MIC_BASE)); + + /* Setup SIC1 */ + __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); + __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); + __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); + + /* Setup SIC2 */ + __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); + __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); + __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); + + /* Configure supported IRQ's */ + for (i = 0; i < NR_IRQS; i++) { + set_irq_chip(i, &lpc32xx_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + + /* Set default mappings */ + lpc32xx_set_default_mappings(MIC_APR_DEFAULT, MIC_ATR_DEFAULT, 0); + lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32); + lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64); + + /* mask all interrupts except SUBIRQ */ + __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE)); + __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); + __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); + + /* MIC SUBIRQx interrupts will route handling to the chain handlers */ + set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); + set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); + + /* Initially disable all wake events */ + __raw_writel(0, LPC32XX_CLKPWR_P01_ER); + __raw_writel(0, LPC32XX_CLKPWR_INT_ER); + __raw_writel(0, LPC32XX_CLKPWR_PIN_ER); + + /* + * Default wake activation polarities, all pin sources are low edge + * triggered + */ + __raw_writel(LPC32XX_CLKPWR_INTSRC_TS_P_BIT | + LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT | + LPC32XX_CLKPWR_INTSRC_RTC_BIT, + LPC32XX_CLKPWR_INT_AP); + __raw_writel(0, LPC32XX_CLKPWR_PIN_AP); + + /* Clear latched wake event states */ + __raw_writel(__raw_readl(LPC32XX_CLKPWR_PIN_RS), + LPC32XX_CLKPWR_PIN_RS); + __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS), + LPC32XX_CLKPWR_INT_RS); +} diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c new file mode 100644 index 000000000000..bc9a42da2145 --- /dev/null +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -0,0 +1,397 @@ +/* + * arch/arm/mach-lpc32xx/phy3250.c + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/sysdev.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/dma-mapping.h> +#include <linux/device.h> +#include <linux/spi/spi.h> +#include <linux/spi/eeprom.h> +#include <linux/leds.h> +#include <linux/gpio.h> +#include <linux/amba/bus.h> +#include <linux/amba/clcd.h> +#include <linux/amba/pl022.h> + +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/hardware.h> +#include <mach/platform.h> +#include "common.h" + +/* + * Mapped GPIOLIB GPIOs + */ +#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) +#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) +#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) +#define LED_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1) + +/* + * AMBA LCD controller + */ +static struct clcd_panel conn_lcd_panel = { + .mode = { + .name = "QVGA portrait", + .refresh = 60, + .xres = 240, + .yres = 320, + .pixclock = 191828, + .left_margin = 22, + .right_margin = 11, + .upper_margin = 2, + .lower_margin = 1, + .hsync_len = 5, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, + .width = -1, + .height = -1, + .tim2 = (TIM2_IVS | TIM2_IHS), + .cntl = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) | + CNTL_LCDBPP16_565), + .bpp = 16, +}; +#define PANEL_SIZE (3 * SZ_64K) + +static int lpc32xx_clcd_setup(struct clcd_fb *fb) +{ + dma_addr_t dma; + + fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, + PANEL_SIZE, &dma, GFP_KERNEL); + if (!fb->fb.screen_base) { + printk(KERN_ERR "CLCD: unable to map framebuffer\n"); + return -ENOMEM; + } + + fb->fb.fix.smem_start = dma; + fb->fb.fix.smem_len = PANEL_SIZE; + fb->panel = &conn_lcd_panel; + + if (gpio_request(LCD_POWER_GPIO, "LCD power")) + printk(KERN_ERR "Error requesting gpio %u", + LCD_POWER_GPIO); + else if (gpio_direction_output(LCD_POWER_GPIO, 1)) + printk(KERN_ERR "Error setting gpio %u to output", + LCD_POWER_GPIO); + + if (gpio_request(BKL_POWER_GPIO, "LCD backlight power")) + printk(KERN_ERR "Error requesting gpio %u", + BKL_POWER_GPIO); + else if (gpio_direction_output(BKL_POWER_GPIO, 1)) + printk(KERN_ERR "Error setting gpio %u to output", + BKL_POWER_GPIO); + + return 0; +} + +static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) +{ + return dma_mmap_writecombine(&fb->dev->dev, vma, + fb->fb.screen_base, fb->fb.fix.smem_start, + fb->fb.fix.smem_len); +} + +static void lpc32xx_clcd_remove(struct clcd_fb *fb) +{ + dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, + fb->fb.screen_base, fb->fb.fix.smem_start); +} + +/* + * On some early LCD modules (1307.0), the backlight logic is inverted. + * For those board variants, swap the disable and enable states for + * BKL_POWER_GPIO. +*/ +static void clcd_disable(struct clcd_fb *fb) +{ + gpio_set_value(BKL_POWER_GPIO, 0); + gpio_set_value(LCD_POWER_GPIO, 0); +} + +static void clcd_enable(struct clcd_fb *fb) +{ + gpio_set_value(BKL_POWER_GPIO, 1); + gpio_set_value(LCD_POWER_GPIO, 1); +} + +static struct clcd_board lpc32xx_clcd_data = { + .name = "Phytec LCD", + .check = clcdfb_check, + .decode = clcdfb_decode, + .disable = clcd_disable, + .enable = clcd_enable, + .setup = lpc32xx_clcd_setup, + .mmap = lpc32xx_clcd_mmap, + .remove = lpc32xx_clcd_remove, +}; + +static struct amba_device lpc32xx_clcd_device = { + .dev = { + .coherent_dma_mask = ~0, + .init_name = "dev:clcd", + .platform_data = &lpc32xx_clcd_data, + }, + .res = { + .start = LPC32XX_LCD_BASE, + .end = (LPC32XX_LCD_BASE + SZ_4K - 1), + .flags = IORESOURCE_MEM, + }, + .dma_mask = ~0, + .irq = {IRQ_LPC32XX_LCD, NO_IRQ}, +}; + +/* + * AMBA SSP (SPI) + */ +static void phy3250_spi_cs_set(u32 control) +{ + gpio_set_value(SPI0_CS_GPIO, (int) control); +} + +static struct pl022_config_chip spi0_chip_info = { + .lbm = LOOPBACK_DISABLED, + .com_mode = INTERRUPT_TRANSFER, + .iface = SSP_INTERFACE_MOTOROLA_SPI, + .hierarchy = SSP_MASTER, + .slave_tx_disable = 0, + .endian_tx = SSP_TX_LSB, + .endian_rx = SSP_RX_LSB, + .data_size = SSP_DATA_BITS_8, + .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, + .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, + .clk_phase = SSP_CLK_FIRST_EDGE, + .clk_pol = SSP_CLK_POL_IDLE_LOW, + .ctrl_len = SSP_BITS_8, + .wait_state = SSP_MWIRE_WAIT_ZERO, + .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, + .cs_control = phy3250_spi_cs_set, +}; + +static struct pl022_ssp_controller lpc32xx_ssp0_data = { + .bus_id = 0, + .num_chipselect = 1, + .enable_dma = 0, +}; + +static struct amba_device lpc32xx_ssp0_device = { + .dev = { + .coherent_dma_mask = ~0, + .init_name = "dev:ssp0", + .platform_data = &lpc32xx_ssp0_data, + }, + .res = { + .start = LPC32XX_SSP0_BASE, + .end = (LPC32XX_SSP0_BASE + SZ_4K - 1), + .flags = IORESOURCE_MEM, + }, + .dma_mask = ~0, + .irq = {IRQ_LPC32XX_SSP0, NO_IRQ}, +}; + +/* AT25 driver registration */ +static int __init phy3250_spi_board_register(void) +{ +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) + static struct spi_board_info info[] = { + { + .modalias = "spidev", + .max_speed_hz = 5000000, + .bus_num = 0, + .chip_select = 0, + .controller_data = &spi0_chip_info, + }, + }; + +#else + static struct spi_eeprom eeprom = { + .name = "at25256a", + .byte_len = 0x8000, + .page_size = 64, + .flags = EE_ADDR2, + }; + + static struct spi_board_info info[] = { + { + .modalias = "at25", + .max_speed_hz = 5000000, + .bus_num = 0, + .chip_select = 0, + .platform_data = &eeprom, + .controller_data = &spi0_chip_info, + }, + }; +#endif + return spi_register_board_info(info, ARRAY_SIZE(info)); +} +arch_initcall(phy3250_spi_board_register); + +static struct i2c_board_info __initdata phy3250_i2c_board_info[] = { + { + I2C_BOARD_INFO("pcf8563", 0x51), + }, +}; + +static struct gpio_led phy_leds[] = { + { + .name = "led0", + .gpio = LED_GPIO, + .active_low = 1, + .default_trigger = "heartbeat", + }, +}; + +static struct gpio_led_platform_data led_data = { + .leds = phy_leds, + .num_leds = ARRAY_SIZE(phy_leds), +}; + +static struct platform_device lpc32xx_gpio_led_device = { + .name = "leds-gpio", + .id = -1, + .dev.platform_data = &led_data, +}; + +static struct platform_device *phy3250_devs[] __initdata = { + &lpc32xx_i2c0_device, + &lpc32xx_i2c1_device, + &lpc32xx_i2c2_device, + &lpc32xx_watchdog_device, + &lpc32xx_gpio_led_device, +}; + +static struct amba_device *amba_devs[] __initdata = { + &lpc32xx_clcd_device, + &lpc32xx_ssp0_device, +}; + +/* + * Board specific functions + */ +static void __init phy3250_board_init(void) +{ + u32 tmp; + int i; + + lpc32xx_gpio_init(); + + /* Register GPIOs used on this board */ + if (gpio_request(SPI0_CS_GPIO, "spi0 cs")) + printk(KERN_ERR "Error requesting gpio %u", + SPI0_CS_GPIO); + else if (gpio_direction_output(SPI0_CS_GPIO, 1)) + printk(KERN_ERR "Error setting gpio %u to output", + SPI0_CS_GPIO); + + /* Setup network interface for RMII mode */ + tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); + tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK; + tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS; + __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL); + + /* Setup SLC NAND controller muxing */ + __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC, + LPC32XX_CLKPWR_NAND_CLK_CTRL); + + /* Setup LCD muxing to RGB565 */ + tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) & + ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK | + LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK); + tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16; + __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL); + + /* Set up I2C pull levels */ + tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); + tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE | + LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE; + __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL); + + /* Disable IrDA pulsing support on UART6 */ + tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); + tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS; + __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); + + /* Enable DMA for I2S1 channel */ + tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL); + tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA; + __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL); + + lpc32xx_serial_init(); + + /* + * AMBA peripheral clocks need to be enabled prior to AMBA device + * detection or a data fault will occur, so enable the clocks + * here. However, we don't want to enable them if the peripheral + * isn't included in the image + */ +#ifdef CONFIG_FB_ARMCLCD + tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); + __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN), + LPC32XX_CLKPWR_LCDCLK_CTRL); +#endif +#ifdef CONFIG_SPI_PL022 + tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL); + __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN), + LPC32XX_CLKPWR_SSP_CLK_CTRL); +#endif + + platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs)); + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; + amba_device_register(d, &iomem_resource); + } + + /* Test clock needed for UDA1380 initial init */ + __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | + LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, + LPC32XX_CLKPWR_TEST_CLK_SEL); + + i2c_register_board_info(0, phy3250_i2c_board_info, + ARRAY_SIZE(phy3250_i2c_board_info)); +} + +static int __init lpc32xx_display_uid(void) +{ + u32 uid[4]; + + lpc32xx_get_uid(uid); + + printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n", + uid[3], uid[2], uid[1], uid[0]); + + return 1; +} +arch_initcall(lpc32xx_display_uid); + +MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller") + /* Maintainer: Kevin Wells, NXP Semiconductors */ + .phys_io = LPC32XX_UART5_BASE, + .io_pg_offst = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = lpc32xx_map_io, + .init_irq = lpc32xx_init_irq, + .timer = &lpc32xx_timer, + .init_machine = phy3250_board_init, +MACHINE_END diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c new file mode 100644 index 000000000000..a6e2aed9a49f --- /dev/null +++ b/arch/arm/mach-lpc32xx/pm.c @@ -0,0 +1,146 @@ +/* + * arch/arm/mach-lpc32xx/pm.c + * + * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com> + * Modified by Kevin Wells <kevin.wells@nxp.com> + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +/* + * LPC32XX CPU and system power management + * + * The LCP32XX has three CPU modes for controlling system power: run, + * direct-run, and halt modes. When switching between halt and run modes, + * the CPU transistions through direct-run mode. For Linux, direct-run + * mode is not used in normal operation. Halt mode is used when the + * system is fully suspended. + * + * Run mode: + * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are + * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from + * the HCLK_PLL rate. Linux runs in this mode. + * + * Direct-run mode: + * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from + * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK + * source or the frequency of the main oscillator. In this mode, the + * HCLK_PLL can be safely enabled, changed, or disabled. + * + * Halt mode: + * SYSCLK is gated off and the CPU and system clocks are halted. + * Peripherals based on the 32KHz oscillator clock (ie, RTC, touch, + * key scanner, etc.) still operate if enabled. In this state, an enabled + * system event (ie, GPIO state change, RTC match, key press, etc.) will + * wake the system up back into direct-run mode. + * + * DRAM refresh + * DRAM clocking and refresh are slightly different for systems with DDR + * DRAM or regular SDRAM devices. If SDRAM is used in the system, the + * SDRAM will still be accessible in direct-run mode. In DDR based systems, + * a transistion to direct-run mode will stop all DDR accesses (no clocks). + * Because of this, the code to switch power modes and the code to enter + * and exit DRAM self-refresh modes must not be executed in DRAM. A small + * section of IRAM is used instead for this. + * + * Suspend is handled with the following logic: + * Backup a small area of IRAM used for the suspend code + * Copy suspend code to IRAM + * Transfer control to code in IRAM + * Places DRAMs in self-refresh mode + * Enter direct-run mode + * Save state of HCLK_PLL PLL + * Disable HCLK_PLL PLL + * Enter halt mode - CPU and buses will stop + * System enters direct-run mode when an enabled event occurs + * HCLK PLL state is restored + * Run mode is entered + * DRAMS are placed back into normal mode + * Code execution returns from IRAM + * IRAM code are used for suspend is restored + * Suspend mode is exited + */ + +#include <linux/suspend.h> +#include <linux/io.h> +#include <linux/slab.h> + +#include <asm/cacheflush.h> + +#include <mach/hardware.h> +#include <mach/platform.h> +#include "common.h" +#include "clock.h" + +#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE) + +/* + * Both STANDBY and MEM suspend states are handled the same with no + * loss of CPU or memory state + */ +static int lpc32xx_pm_enter(suspend_state_t state) +{ + int (*lpc32xx_suspend_ptr) (void); + void *iram_swap_area; + + /* Allocate some space for temporary IRAM storage */ + iram_swap_area = kmalloc(lpc32xx_sys_suspend_sz, GFP_KERNEL); + if (!iram_swap_area) { + printk(KERN_ERR + "PM Suspend: cannot allocate memory to save portion " + "of SRAM\n"); + return -ENOMEM; + } + + /* Backup a small area of IRAM used for the suspend code */ + memcpy(iram_swap_area, (void *) TEMP_IRAM_AREA, + lpc32xx_sys_suspend_sz); + + /* + * Copy code to suspend system into IRAM. The suspend code + * needs to run from IRAM as DRAM may no longer be available + * when the PLL is stopped. + */ + memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend, + lpc32xx_sys_suspend_sz); + flush_icache_range((unsigned long)TEMP_IRAM_AREA, + (unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz); + + /* Transfer to suspend code in IRAM */ + lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA; + flush_cache_all(); + (void) lpc32xx_suspend_ptr(); + + /* Restore original IRAM contents */ + memcpy((void *) TEMP_IRAM_AREA, iram_swap_area, + lpc32xx_sys_suspend_sz); + + kfree(iram_swap_area); + + return 0; +} + +static struct platform_suspend_ops lpc32xx_pm_ops = { + .valid = suspend_valid_only_mem, + .enter = lpc32xx_pm_enter, +}; + +#define EMC_DYN_MEM_CTRL_OFS 0x20 +#define EMC_SRMMC (1 << 3) +#define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS) +static int __init lpc32xx_pm_init(void) +{ + /* + * Setup SDRAM self-refresh clock to automatically disable o + * start of self-refresh. This only needs to be done once. + */ + __raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG); + + suspend_set_ops(&lpc32xx_pm_ops); + + return 0; +} +arch_initcall(lpc32xx_pm_init); diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c new file mode 100644 index 000000000000..429cfdbb2b3d --- /dev/null +++ b/arch/arm/mach-lpc32xx/serial.c @@ -0,0 +1,190 @@ +/* + * arch/arm/mach-lpc32xx/serial.c + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/serial.h> +#include <linux/serial_core.h> +#include <linux/serial_reg.h> +#include <linux/serial_8250.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <mach/hardware.h> +#include <mach/platform.h> +#include "common.h" + +#define LPC32XX_SUART_FIFO_SIZE 64 + +/* Standard 8250/16550 compatible serial ports */ +static struct plat_serial8250_port serial_std_platform_data[] = { +#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT + { + .membase = io_p2v(LPC32XX_UART5_BASE), + .mapbase = LPC32XX_UART5_BASE, + .irq = IRQ_LPC32XX_UART_IIR5, + .uartclk = LPC32XX_MAIN_OSC_FREQ, + .regshift = 2, + .iotype = UPIO_MEM32, + .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | + UPF_SKIP_TEST, + }, +#endif +#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT + { + .membase = io_p2v(LPC32XX_UART3_BASE), + .mapbase = LPC32XX_UART3_BASE, + .irq = IRQ_LPC32XX_UART_IIR3, + .uartclk = LPC32XX_MAIN_OSC_FREQ, + .regshift = 2, + .iotype = UPIO_MEM32, + .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | + UPF_SKIP_TEST, + }, +#endif +#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT + { + .membase = io_p2v(LPC32XX_UART4_BASE), + .mapbase = LPC32XX_UART4_BASE, + .irq = IRQ_LPC32XX_UART_IIR4, + .uartclk = LPC32XX_MAIN_OSC_FREQ, + .regshift = 2, + .iotype = UPIO_MEM32, + .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | + UPF_SKIP_TEST, + }, +#endif +#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT + { + .membase = io_p2v(LPC32XX_UART6_BASE), + .mapbase = LPC32XX_UART6_BASE, + .irq = IRQ_LPC32XX_UART_IIR6, + .uartclk = LPC32XX_MAIN_OSC_FREQ, + .regshift = 2, + .iotype = UPIO_MEM32, + .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | + UPF_SKIP_TEST, + }, +#endif + { }, +}; + +struct uartinit { + char *uart_ck_name; + u32 ck_mode_mask; + void __iomem *pdiv_clk_reg; +}; + +static struct uartinit uartinit_data[] __initdata = { +#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT + { + .uart_ck_name = "uart5_ck", + .ck_mode_mask = + LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5), + .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, + }, +#endif +#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT + { + .uart_ck_name = "uart3_ck", + .ck_mode_mask = + LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3), + .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, + }, +#endif +#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT + { + .uart_ck_name = "uart4_ck", + .ck_mode_mask = + LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4), + .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, + }, +#endif +#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT + { + .uart_ck_name = "uart6_ck", + .ck_mode_mask = + LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6), + .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, + }, +#endif +}; + +static struct platform_device serial_std_platform_device = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = serial_std_platform_data, + }, +}; + +static struct platform_device *lpc32xx_serial_devs[] __initdata = { + &serial_std_platform_device, +}; + +void __init lpc32xx_serial_init(void) +{ + u32 tmp, clkmodes = 0; + struct clk *clk; + unsigned int puart; + int i, j; + + /* UART clocks are off, let clock driver manage them */ + __raw_writel(0, LPC32XX_CLKPWR_UART_CLK_CTRL); + + for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) { + clk = clk_get(NULL, uartinit_data[i].uart_ck_name); + if (!IS_ERR(clk)) { + clk_enable(clk); + serial_std_platform_data[i].uartclk = + clk_get_rate(clk); + } + + /* Fall back on main osc rate if clock rate return fails */ + if (serial_std_platform_data[i].uartclk == 0) + serial_std_platform_data[i].uartclk = + LPC32XX_MAIN_OSC_FREQ; + + /* Setup UART clock modes for all UARTs, disable autoclock */ + clkmodes |= uartinit_data[i].ck_mode_mask; + + /* pre-UART clock divider set to 1 */ + __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg); + } + + /* This needs to be done after all UART clocks are setup */ + __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); + for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) { + /* Force a flush of the RX FIFOs to work around a HW bug */ + puart = serial_std_platform_data[i].mapbase; + __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); + __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); + j = LPC32XX_SUART_FIFO_SIZE; + while (j--) + tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart)); + __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); + } + + /* Disable UART5->USB transparent mode or USB won't work */ + tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); + tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB; + __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); + + platform_add_devices(lpc32xx_serial_devs, + ARRAY_SIZE(lpc32xx_serial_devs)); +} diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S new file mode 100644 index 000000000000..374f9f07fe48 --- /dev/null +++ b/arch/arm/mach-lpc32xx/suspend.S @@ -0,0 +1,151 @@ +/* + * arch/arm/mach-lpc32xx/suspend.S + * + * Original authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com> + * Modified by Kevin Wells <kevin.wells@nxp.com> + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <mach/platform.h> +#include <mach/hardware.h> + +/* Using named register defines makes the code easier to follow */ +#define WORK1_REG r0 +#define WORK2_REG r1 +#define SAVED_HCLK_DIV_REG r2 +#define SAVED_HCLK_PLL_REG r3 +#define SAVED_DRAM_CLKCTRL_REG r4 +#define SAVED_PWR_CTRL_REG r5 +#define CLKPWRBASE_REG r6 +#define EMCBASE_REG r7 + +#define LPC32XX_EMC_STATUS_OFFS 0x04 +#define LPC32XX_EMC_STATUS_BUSY 0x1 +#define LPC32XX_EMC_STATUS_SELF_RFSH 0x4 + +#define LPC32XX_CLKPWR_PWR_CTRL_OFFS 0x44 +#define LPC32XX_CLKPWR_HCLK_DIV_OFFS 0x40 +#define LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS 0x58 + +#define CLKPWR_PCLK_DIV_MASK 0xFFFFFE7F + + .text + +ENTRY(lpc32xx_sys_suspend) + @ Save a copy of the used registers in IRAM, r0 is corrupted + adr r0, tmp_stack_end + stmfd r0!, {r3 - r7, sp, lr} + + @ Load a few common register addresses + adr WORK1_REG, reg_bases + ldr CLKPWRBASE_REG, [WORK1_REG, #0] + ldr EMCBASE_REG, [WORK1_REG, #4] + + ldr SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\ + #LPC32XX_CLKPWR_PWR_CTRL_OFFS] + orr WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH + + @ Wait for SDRAM busy status to go busy and then idle + @ This guarantees a small windows where DRAM isn't busy +1: + ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS] + and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY + cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY + bne 1b @ Branch while idle +2: + ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS] + and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY + cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY + beq 2b @ Branch until idle + + @ Setup self-refresh with support for manual exit of + @ self-refresh mode + str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS] + orr WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH + str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS] + str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS] + + @ Wait for self-refresh acknowledge, clocks to the DRAM device + @ will automatically stop on start of self-refresh +3: + ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS] + and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH + cmp WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH + bne 3b @ Branch until self-refresh mode starts + + @ Enter direct-run mode from run mode + bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE + str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS] + + @ Safe disable of DRAM clock in EMC block, prevents DDR sync + @ issues on restart + ldr SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\ + #LPC32XX_CLKPWR_HCLK_DIV_OFFS] + and WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK + str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS] + + @ Save HCLK PLL state and disable HCLK PLL + ldr SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\ + #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS] + bic WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP + str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS] + + @ Enter stop mode until an enabled event occurs + orr WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL + str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS] + .rept 9 + nop + .endr + + @ Clear stop status + bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL + + @ Restore original HCLK PLL value and wait for PLL lock + str SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\ + #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS] +4: + ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS] + and WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS + bne 4b + + @ Re-enter run mode with self-refresh flag cleared, but no DRAM + @ update yet. DRAM is still in self-refresh + str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\ + #LPC32XX_CLKPWR_PWR_CTRL_OFFS] + + @ Restore original DRAM clock mode to restore DRAM clocks + str SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\ + #LPC32XX_CLKPWR_HCLK_DIV_OFFS] + + @ Clear self-refresh mode + orr WORK1_REG, SAVED_PWR_CTRL_REG,\ + #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH + str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS] + str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\ + #LPC32XX_CLKPWR_PWR_CTRL_OFFS] + + @ Wait for EMC to clear self-refresh mode +5: + ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS] + and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH + bne 5b @ Branch until self-refresh has exited + + @ restore regs and return + adr r0, tmp_stack + ldmfd r0!, {r3 - r7, sp, pc} + +reg_bases: + .long IO_ADDRESS(LPC32XX_CLK_PM_BASE) + .long IO_ADDRESS(LPC32XX_EMC_BASE) + +tmp_stack: + .long 0, 0, 0, 0, 0, 0, 0 +tmp_stack_end: + +ENTRY(lpc32xx_sys_suspend_sz) + .word . - lpc32xx_sys_suspend diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c new file mode 100644 index 000000000000..630dd4a74b26 --- /dev/null +++ b/arch/arm/mach-lpc32xx/timer.c @@ -0,0 +1,182 @@ +/* + * arch/arm/mach-lpc32xx/timer.c + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2009 - 2010 NXP Semiconductors + * Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven + * Ed Schouten <e.schouten@fontys.nl> + * Laurens Timmermans <l.timmermans@fontys.nl> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/time.h> +#include <linux/err.h> +#include <linux/clockchips.h> + +#include <asm/mach/time.h> + +#include <mach/hardware.h> +#include <mach/platform.h> +#include "common.h" + +static cycle_t lpc32xx_clksrc_read(struct clocksource *cs) +{ + return (cycle_t)__raw_readl(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE)); +} + +static struct clocksource lpc32xx_clksrc = { + .name = "lpc32xx_clksrc", + .shift = 24, + .rating = 300, + .read = lpc32xx_clksrc_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int lpc32xx_clkevt_next_event(unsigned long delta, + struct clock_event_device *dev) +{ + __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET, + LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); + __raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE)); + __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN, + LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); + + return 0; +} + +static void lpc32xx_clkevt_mode(enum clock_event_mode mode, + struct clock_event_device *dev) +{ + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + WARN_ON(1); + break; + + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_SHUTDOWN: + /* + * Disable the timer. When using oneshot, we must also + * disable the timer to wait for the first call to + * set_next_event(). + */ + __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); + break; + + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + break; + } +} + +static struct clock_event_device lpc32xx_clkevt = { + .name = "lpc32xx_clkevt", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .rating = 300, + .set_next_event = lpc32xx_clkevt_next_event, + .set_mode = lpc32xx_clkevt_mode, +}; + +static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &lpc32xx_clkevt; + + /* Clear match */ + __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0), + LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE)); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction lpc32xx_timer_irq = { + .name = "LPC32XX Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = lpc32xx_timer_interrupt, +}; + +/* + * The clock management driver isn't initialized at this point, so the + * clocks need to be enabled here manually and then tagged as used in + * the clock driver initialization + */ +static void __init lpc32xx_timer_init(void) +{ + u32 clkrate, pllreg; + + /* Enable timer clock */ + __raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN | + LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN, + LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1); + + /* + * The clock driver isn't initialized at this point. So determine if + * the SYSCLK is driven from the PLL397 or main oscillator and then use + * it to compute the PLL frequency and the PCLK divider to get the base + * timer rates. This rate is needed to compute the tick rate. + */ + if (clk_is_sysclk_mainosc() != 0) + clkrate = LPC32XX_MAIN_OSC_FREQ; + else + clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ; + + /* Get ARM HCLKPLL register and convert it into a frequency */ + pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF; + clkrate = clk_get_pllrate_from_reg(clkrate, pllreg); + + /* Get PCLK divider and divide ARM PLL clock by it to get timer rate */ + clkrate = clkrate / clk_get_pclk_div(); + + /* Initial timer setup */ + __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); + __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0), + LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE)); + __raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE)); + __raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) | + LCP32XX_TIMER_CNTR_MCR_STOP(0) | + LCP32XX_TIMER_CNTR_MCR_RESET(0), + LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE)); + + /* Setup tick interrupt */ + setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq); + + /* Setup the clockevent structure. */ + lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC, + lpc32xx_clkevt.shift); + lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1, + &lpc32xx_clkevt); + lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1, + &lpc32xx_clkevt) + 1; + lpc32xx_clkevt.cpumask = cpumask_of(0); + clockevents_register_device(&lpc32xx_clkevt); + + /* Use timer1 as clock source. */ + __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET, + LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE)); + __raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE)); + __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE)); + __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN, + LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE)); + lpc32xx_clksrc.mult = clocksource_hz2mult(clkrate, + lpc32xx_clksrc.shift); + clocksource_register(&lpc32xx_clksrc); +} + +struct sys_timer lpc32xx_timer = { + .init = &lpc32xx_timer_init, +}; + diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 66677f0acaed..7ff8020d4d24 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_QSD8X50) += sirc.o obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o obj-$(CONFIG_MSM_SMD) += last_radio_log.o -obj-$(CONFIG_MACH_TROUT) += board-trout.o devices-msm7x00.o +obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o devices-msm7x00.o obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c new file mode 100644 index 000000000000..523d213bf79e --- /dev/null +++ b/arch/arm/mach-msm/board-trout-gpio.c @@ -0,0 +1,112 @@ +/* + * linux/arch/arm/mach-msm/gpio.c + * + * Copyright (C) 2005 HP Labs + * Copyright (C) 2008 Google, Inc. + * Copyright (C) 2009 Pavel Machek <pavel@ucw.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/gpio.h> + +#include "board-trout.h" + +struct msm_gpio_chip { + struct gpio_chip chip; + void __iomem *reg; /* Base of register bank */ + u8 shadow; +}; + +#define to_msm_gpio_chip(c) container_of(c, struct msm_gpio_chip, chip) + +static int msm_gpiolib_get(struct gpio_chip *chip, unsigned offset) +{ + struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip); + unsigned mask = 1 << offset; + + return !!(readb(msm_gpio->reg) & mask); +} + +static void msm_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val) +{ + struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip); + unsigned mask = 1 << offset; + + if (val) + msm_gpio->shadow |= mask; + else + msm_gpio->shadow &= ~mask; + + writeb(msm_gpio->shadow, msm_gpio->reg); +} + +static int msm_gpiolib_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + msm_gpiolib_set(chip, offset, 0); + return 0; +} + +static int msm_gpiolib_direction_output(struct gpio_chip *chip, + unsigned offset, int val) +{ + msm_gpiolib_set(chip, offset, val); + return 0; +} + +#define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val) \ + { \ + .chip = { \ + .label = name, \ + .direction_input = msm_gpiolib_direction_input,\ + .direction_output = msm_gpiolib_direction_output, \ + .get = msm_gpiolib_get, \ + .set = msm_gpiolib_set, \ + .base = base_gpio, \ + .ngpio = 8, \ + }, \ + .reg = (void *) reg_num + TROUT_CPLD_BASE, \ + .shadow = shadow_val, \ + } + +static struct msm_gpio_chip msm_gpio_banks[] = { +#if defined(CONFIG_MSM_DEBUG_UART1) + /* H2W pins <-> UART1 */ + TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x40), +#else + /* H2W pins <-> UART3, Bluetooth <-> UART1 */ + TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x80), +#endif + /* I2C pull */ + TROUT_GPIO_BANK("MISC3", 0x02, TROUT_GPIO_MISC3_BASE, 0x04), + TROUT_GPIO_BANK("MISC4", 0x04, TROUT_GPIO_MISC4_BASE, 0), + /* mmdi 32k en */ + TROUT_GPIO_BANK("MISC5", 0x06, TROUT_GPIO_MISC5_BASE, 0x04), + TROUT_GPIO_BANK("INT2", 0x08, TROUT_GPIO_INT2_BASE, 0), + TROUT_GPIO_BANK("MISC1", 0x0a, TROUT_GPIO_MISC1_BASE, 0), + TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0), +}; + +/* + * Called from the processor-specific init to enable GPIO pin support. + */ +int __init trout_init_gpio(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++) + gpiochip_add(&msm_gpio_banks[i].chip); + + return 0; +} + +postcore_initcall(trout_init_gpio); + diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index dca5a5f062dc..e69a1502e4e8 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c @@ -50,7 +50,6 @@ static void __init trout_fixup(struct machine_desc *desc, struct tag *tags, { mi->nr_banks = 1; mi->bank[0].start = PHYS_OFFSET; - mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET); mi->bank[0].size = (101*1024*1024); } diff --git a/arch/arm/mach-msm/board-trout.h b/arch/arm/mach-msm/board-trout.h index 4f345a5a0a61..651851c3e1dd 100644 --- a/arch/arm/mach-msm/board-trout.h +++ b/arch/arm/mach-msm/board-trout.h @@ -1,5 +1,162 @@ +/* linux/arch/arm/mach-msm/board-trout.h +** Author: Brian Swetland <swetland@google.com> +*/ +#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H +#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H + +#include <mach/board.h> + +#define MSM_SMI_BASE 0x00000000 +#define MSM_SMI_SIZE 0x00800000 + +#define MSM_EBI_BASE 0x10000000 +#define MSM_EBI_SIZE 0x06e00000 + +#define MSM_PMEM_GPU0_BASE 0x00000000 +#define MSM_PMEM_GPU0_SIZE 0x00700000 + +#define MSM_PMEM_MDP_BASE 0x02000000 +#define MSM_PMEM_MDP_SIZE 0x00800000 + +#define MSM_PMEM_ADSP_BASE 0x02800000 +#define MSM_PMEM_ADSP_SIZE 0x00800000 + +#define MSM_PMEM_CAMERA_BASE 0x03000000 +#define MSM_PMEM_CAMERA_SIZE 0x00800000 + +#define MSM_FB_BASE 0x03800000 +#define MSM_FB_SIZE 0x00100000 + +#define MSM_LINUX_BASE MSM_EBI_BASE +#define MSM_LINUX_SIZE 0x06500000 + +#define MSM_PMEM_GPU1_SIZE 0x800000 +#define MSM_PMEM_GPU1_BASE (MSM_RAM_CONSOLE_BASE - MSM_PMEM_GPU1_SIZE) + +#define MSM_RAM_CONSOLE_BASE (MSM_EBI_BASE + 0x6d00000) +#define MSM_RAM_CONSOLE_SIZE (128 * SZ_1K) + +#if (MSM_FB_BASE + MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE) +#error invalid memory map +#endif + +#define DECLARE_MSM_IOMAP +#include <mach/msm_iomap.h> + +#define TROUT_4_BALL_UP_0 1 +#define TROUT_4_BALL_LEFT_0 18 +#define TROUT_4_BALL_DOWN_0 57 +#define TROUT_4_BALL_RIGHT_0 91 + +#define TROUT_5_BALL_UP_0 94 +#define TROUT_5_BALL_LEFT_0 18 +#define TROUT_5_BALL_DOWN_0 90 +#define TROUT_5_BALL_RIGHT_0 19 + +#define TROUT_POWER_KEY 20 + +#define TROUT_4_TP_LS_EN 19 +#define TROUT_5_TP_LS_EN 1 #define TROUT_CPLD_BASE 0xE8100000 #define TROUT_CPLD_START 0x98000000 #define TROUT_CPLD_SIZE SZ_4K +#define TROUT_GPIO_CABLE_IN1 (83) +#define TROUT_GPIO_CABLE_IN2 (49) + +#define TROUT_GPIO_START (128) + +#define TROUT_GPIO_INT_MASK0_REG (0x0c) +#define TROUT_GPIO_INT_STAT0_REG (0x0e) +#define TROUT_GPIO_INT_MASK1_REG (0x14) +#define TROUT_GPIO_INT_STAT1_REG (0x10) + +#define TROUT_GPIO_HAPTIC_PWM (28) +#define TROUT_GPIO_PS_HOLD (25) + +#define TROUT_GPIO_MISC2_BASE (TROUT_GPIO_START + 0x00) +#define TROUT_GPIO_MISC3_BASE (TROUT_GPIO_START + 0x08) +#define TROUT_GPIO_MISC4_BASE (TROUT_GPIO_START + 0x10) +#define TROUT_GPIO_MISC5_BASE (TROUT_GPIO_START + 0x18) +#define TROUT_GPIO_INT2_BASE (TROUT_GPIO_START + 0x20) +#define TROUT_GPIO_MISC1_BASE (TROUT_GPIO_START + 0x28) +#define TROUT_GPIO_VIRTUAL_BASE (TROUT_GPIO_START + 0x30) +#define TROUT_GPIO_INT5_BASE (TROUT_GPIO_START + 0x48) + +#define TROUT_GPIO_CHARGER_EN (TROUT_GPIO_MISC2_BASE + 0) +#define TROUT_GPIO_ISET (TROUT_GPIO_MISC2_BASE + 1) +#define TROUT_GPIO_H2W_DAT_DIR (TROUT_GPIO_MISC2_BASE + 2) +#define TROUT_GPIO_H2W_CLK_DIR (TROUT_GPIO_MISC2_BASE + 3) +#define TROUT_GPIO_H2W_DAT_GPO (TROUT_GPIO_MISC2_BASE + 4) +#define TROUT_GPIO_H2W_CLK_GPO (TROUT_GPIO_MISC2_BASE + 5) +#define TROUT_GPIO_H2W_SEL0 (TROUT_GPIO_MISC2_BASE + 6) +#define TROUT_GPIO_H2W_SEL1 (TROUT_GPIO_MISC2_BASE + 7) + +#define TROUT_GPIO_SPOTLIGHT_EN (TROUT_GPIO_MISC3_BASE + 0) +#define TROUT_GPIO_FLASH_EN (TROUT_GPIO_MISC3_BASE + 1) +#define TROUT_GPIO_I2C_PULL (TROUT_GPIO_MISC3_BASE + 2) +#define TROUT_GPIO_TP_I2C_PULL (TROUT_GPIO_MISC3_BASE + 3) +#define TROUT_GPIO_TP_EN (TROUT_GPIO_MISC3_BASE + 4) +#define TROUT_GPIO_JOG_EN (TROUT_GPIO_MISC3_BASE + 5) +#define TROUT_GPIO_UI_LED_EN (TROUT_GPIO_MISC3_BASE + 6) +#define TROUT_GPIO_QTKEY_LED_EN (TROUT_GPIO_MISC3_BASE + 7) + +#define TROUT_GPIO_VCM_PWDN (TROUT_GPIO_MISC4_BASE + 0) +#define TROUT_GPIO_USB_H2W_SW (TROUT_GPIO_MISC4_BASE + 1) +#define TROUT_GPIO_COMPASS_RST_N (TROUT_GPIO_MISC4_BASE + 2) +#define TROUT_GPIO_HAPTIC_EN_UP (TROUT_GPIO_MISC4_BASE + 3) +#define TROUT_GPIO_HAPTIC_EN_MAIN (TROUT_GPIO_MISC4_BASE + 4) +#define TROUT_GPIO_USB_PHY_RST_N (TROUT_GPIO_MISC4_BASE + 5) +#define TROUT_GPIO_WIFI_PA_RESETX (TROUT_GPIO_MISC4_BASE + 6) +#define TROUT_GPIO_WIFI_EN (TROUT_GPIO_MISC4_BASE + 7) + +#define TROUT_GPIO_BT_32K_EN (TROUT_GPIO_MISC5_BASE + 0) +#define TROUT_GPIO_MAC_32K_EN (TROUT_GPIO_MISC5_BASE + 1) +#define TROUT_GPIO_MDDI_32K_EN (TROUT_GPIO_MISC5_BASE + 2) +#define TROUT_GPIO_COMPASS_32K_EN (TROUT_GPIO_MISC5_BASE + 3) + +#define TROUT_GPIO_NAVI_ACT_N (TROUT_GPIO_INT2_BASE + 0) +#define TROUT_GPIO_COMPASS_IRQ (TROUT_GPIO_INT2_BASE + 1) +#define TROUT_GPIO_SLIDING_DET (TROUT_GPIO_INT2_BASE + 2) +#define TROUT_GPIO_AUD_HSMIC_DET_N (TROUT_GPIO_INT2_BASE + 3) +#define TROUT_GPIO_SD_DOOR_N (TROUT_GPIO_INT2_BASE + 4) +#define TROUT_GPIO_CAM_BTN_STEP1_N (TROUT_GPIO_INT2_BASE + 5) +#define TROUT_GPIO_CAM_BTN_STEP2_N (TROUT_GPIO_INT2_BASE + 6) +#define TROUT_GPIO_TP_ATT_N (TROUT_GPIO_INT2_BASE + 7) +#define TROUT_GPIO_BANK0_FIRST_INT_SOURCE (TROUT_GPIO_NAVI_ACT_N) +#define TROUT_GPIO_BANK0_LAST_INT_SOURCE (TROUT_GPIO_TP_ATT_N) + +#define TROUT_GPIO_H2W_DAT_GPI (TROUT_GPIO_MISC1_BASE + 0) +#define TROUT_GPIO_H2W_CLK_GPI (TROUT_GPIO_MISC1_BASE + 1) +#define TROUT_GPIO_CPLD128_VER_0 (TROUT_GPIO_MISC1_BASE + 4) +#define TROUT_GPIO_CPLD128_VER_1 (TROUT_GPIO_MISC1_BASE + 5) +#define TROUT_GPIO_CPLD128_VER_2 (TROUT_GPIO_MISC1_BASE + 6) +#define TROUT_GPIO_CPLD128_VER_3 (TROUT_GPIO_MISC1_BASE + 7) + +#define TROUT_GPIO_SDMC_CD_N (TROUT_GPIO_VIRTUAL_BASE + 0) +#define TROUT_GPIO_END (TROUT_GPIO_SDMC_CD_N) +#define TROUT_GPIO_BANK1_FIRST_INT_SOURCE (TROUT_GPIO_SDMC_CD_N) +#define TROUT_GPIO_BANK1_LAST_INT_SOURCE (TROUT_GPIO_SDMC_CD_N) + +#define TROUT_GPIO_VIRTUAL_TO_REAL_OFFSET \ + (TROUT_GPIO_INT5_BASE - TROUT_GPIO_VIRTUAL_BASE) + +#define TROUT_INT_START (NR_MSM_IRQS + NR_GPIO_IRQS) +#define TROUT_INT_BANK0_COUNT (8) +#define TROUT_INT_BANK1_START (TROUT_INT_START + TROUT_INT_BANK0_COUNT) +#define TROUT_INT_BANK1_COUNT (1) +#define TROUT_INT_END (TROUT_INT_START + TROUT_INT_BANK0_COUNT + \ + TROUT_INT_BANK1_COUNT - 1) +#define TROUT_GPIO_TO_INT(n) (((n) <= TROUT_GPIO_BANK0_LAST_INT_SOURCE) ? \ + (TROUT_INT_START - TROUT_GPIO_BANK0_FIRST_INT_SOURCE + (n)) : \ + (TROUT_INT_BANK1_START - TROUT_GPIO_BANK1_FIRST_INT_SOURCE + (n))) + +#define TROUT_INT_TO_BANK(n) ((n - TROUT_INT_START) / TROUT_INT_BANK0_COUNT) +#define TROUT_INT_TO_MASK(n) (1U << ((n - TROUT_INT_START) & 7)) +#define TROUT_BANK_TO_MASK_REG(bank) \ + (bank ? TROUT_GPIO_INT_MASK1_REG : TROUT_GPIO_INT_MASK0_REG) +#define TROUT_BANK_TO_STAT_REG(bank) \ + (bank ? TROUT_GPIO_INT_STAT1_REG : TROUT_GPIO_INT_STAT0_REG) + +#endif /* GUARD */ diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h index 262b441b4374..83e47c0d5c2e 100644 --- a/arch/arm/mach-msm/include/mach/gpio.h +++ b/arch/arm/mach-msm/include/mach/gpio.h @@ -16,6 +16,13 @@ #ifndef __ASM_ARCH_MSM_GPIO_H #define __ASM_ARCH_MSM_GPIO_H +#include <asm-generic/gpio.h> + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq + /** * struct msm_gpio - GPIO pin description * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config() diff --git a/arch/arm/mach-mx1/Kconfig b/arch/arm/mach-mx1/Kconfig deleted file mode 100644 index eb7660f5d4b7..000000000000 --- a/arch/arm/mach-mx1/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -if ARCH_MX1 - -comment "MX1 platforms:" - -config MACH_MXLADS - bool - -config ARCH_MX1ADS - bool "MX1ADS platform" - select MACH_MXLADS - help - Say Y here if you are using Motorola MX1ADS/MXLADS boards - -config MACH_SCB9328 - bool "Synertronixx scb9328" - help - Say Y here if you are using a Synertronixx scb9328 board - -endif diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile deleted file mode 100644 index fc2ddf82441b..000000000000 --- a/arch/arm/mach-mx1/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# Object file lists. - -EXTRA_CFLAGS += -DIMX_NEEDS_DEPRECATED_SYMBOLS -obj-y += generic.o clock.o devices.o - -# Support for CMOS sensor interface -obj-$(CONFIG_MX1_VIDEO) += ksym_mx1.o mx1_camera_fiq.o - -# Specific board support -obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o -obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o diff --git a/arch/arm/mach-mx1/Makefile.boot b/arch/arm/mach-mx1/Makefile.boot deleted file mode 100644 index 8ed1492288a2..000000000000 --- a/arch/arm/mach-mx1/Makefile.boot +++ /dev/null @@ -1,4 +0,0 @@ - zreladdr-y := 0x08008000 -params_phys-y := 0x08000100 -initrd_phys-y := 0x08800000 - diff --git a/arch/arm/mach-mx1/crm_regs.h b/arch/arm/mach-mx1/crm_regs.h deleted file mode 100644 index 22e866ff0c09..000000000000 --- a/arch/arm/mach-mx1/crm_regs.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> - * - * This file may be distributed under the terms of the GNU General - * Public License, version 2. - */ - -#ifndef __ARCH_ARM_MACH_MX1_CRM_REGS_H__ -#define __ARCH_ARM_MACH_MX1_CRM_REGS_H__ - -#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) -#define SCM_BASE IO_ADDRESS(SCM_BASE_ADDR) - -/* CCM register addresses */ -#define CCM_CSCR (CCM_BASE + 0x0) -#define CCM_MPCTL0 (CCM_BASE + 0x4) -#define CCM_MPCTL1 (CCM_BASE + 0x8) -#define CCM_SPCTL0 (CCM_BASE + 0xC) -#define CCM_SPCTL1 (CCM_BASE + 0x10) -#define CCM_PCDR (CCM_BASE + 0x20) - -#define CCM_CSCR_CLKO_OFFSET 29 -#define CCM_CSCR_CLKO_MASK (0x7 << 29) -#define CCM_CSCR_USB_OFFSET 26 -#define CCM_CSCR_USB_MASK (0x7 << 26) -#define CCM_CSCR_SPLL_RESTART (1 << 22) -#define CCM_CSCR_MPLL_RESTART (1 << 21) -#define CCM_CSCR_OSC_EN_SHIFT 17 -#define CCM_CSCR_SYSTEM_SEL (1 << 16) -#define CCM_CSCR_BCLK_OFFSET 10 -#define CCM_CSCR_BCLK_MASK (0xF << 10) -#define CCM_CSCR_PRESC (1 << 15) -#define CCM_CSCR_SPEN (1 << 1) -#define CCM_CSCR_MPEN (1 << 0) - -#define CCM_PCDR_PCLK3_OFFSET 16 -#define CCM_PCDR_PCLK3_MASK (0x7F << 16) -#define CCM_PCDR_PCLK2_OFFSET 4 -#define CCM_PCDR_PCLK2_MASK (0xF << 4) -#define CCM_PCDR_PCLK1_OFFSET 0 -#define CCM_PCDR_PCLK1_MASK 0xF - -/* SCM register addresses */ -#define SCM_SIDR (SCM_BASE + 0x0) -#define SCM_FMCR (SCM_BASE + 0x4) -#define SCM_GPCR (SCM_BASE + 0x8) -#define SCM_GCCR (SCM_BASE + 0xC) - -#define SCM_GCCR_DMA_CLK_EN_OFFSET 3 -#define SCM_GCCR_CSI_CLK_EN_OFFSET 2 -#define SCM_GCCR_MMA_CLK_EN_OFFSET 1 -#define SCM_GCCR_USBD_CLK_EN_OFFSET 0 - -#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */ diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c deleted file mode 100644 index b6be29d1cb08..000000000000 --- a/arch/arm/mach-mx1/devices.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Sascha Hauer, kernel@pengutronix.de - * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> - * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <mach/irqs.h> -#include <mach/hardware.h> - -#include "devices.h" - -static struct resource imx_csi_resources[] = { - { - .start = 0x00224000, - .end = 0x00224010, - .flags = IORESOURCE_MEM, - }, { - .start = CSI_INT, - .end = CSI_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 imx_csi_dmamask = 0xffffffffUL; - -struct platform_device imx_csi_device = { - .name = "mx1-camera", - .id = 0, /* This is used to put cameras on this interface */ - .dev = { - .dma_mask = &imx_csi_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .resource = imx_csi_resources, - .num_resources = ARRAY_SIZE(imx_csi_resources), -}; - -static struct resource imx_i2c_resources[] = { - { - .start = 0x00217000, - .end = 0x00217010, - .flags = IORESOURCE_MEM, - }, { - .start = I2C_INT, - .end = I2C_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_i2c_device = { - .name = "imx-i2c", - .id = 0, - .resource = imx_i2c_resources, - .num_resources = ARRAY_SIZE(imx_i2c_resources), -}; - -static struct resource imx_uart1_resources[] = { - { - .start = UART1_BASE_ADDR, - .end = UART1_BASE_ADDR + 0xD0, - .flags = IORESOURCE_MEM, - }, { - .start = UART1_MINT_RX, - .end = UART1_MINT_RX, - .flags = IORESOURCE_IRQ, - }, { - .start = UART1_MINT_TX, - .end = UART1_MINT_TX, - .flags = IORESOURCE_IRQ, - }, { - .start = UART1_MINT_RTS, - .end = UART1_MINT_RTS, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_uart1_device = { - .name = "imx-uart", - .id = 0, - .num_resources = ARRAY_SIZE(imx_uart1_resources), - .resource = imx_uart1_resources, -}; - -static struct resource imx_uart2_resources[] = { - { - .start = UART2_BASE_ADDR, - .end = UART2_BASE_ADDR + 0xD0, - .flags = IORESOURCE_MEM, - }, { - .start = UART2_MINT_RX, - .end = UART2_MINT_RX, - .flags = IORESOURCE_IRQ, - }, { - .start = UART2_MINT_TX, - .end = UART2_MINT_TX, - .flags = IORESOURCE_IRQ, - }, { - .start = UART2_MINT_RTS, - .end = UART2_MINT_RTS, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_uart2_device = { - .name = "imx-uart", - .id = 1, - .num_resources = ARRAY_SIZE(imx_uart2_resources), - .resource = imx_uart2_resources, -}; - -static struct resource imx_rtc_resources[] = { - { - .start = 0x00204000, - .end = 0x00204024, - .flags = IORESOURCE_MEM, - }, { - .start = RTC_INT, - .end = RTC_INT, - .flags = IORESOURCE_IRQ, - }, { - .start = RTC_SAMINT, - .end = RTC_SAMINT, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_rtc_device = { - .name = "rtc-imx", - .id = 0, - .resource = imx_rtc_resources, - .num_resources = ARRAY_SIZE(imx_rtc_resources), -}; - -static struct resource imx_wdt_resources[] = { - { - .start = 0x00201000, - .end = 0x00201008, - .flags = IORESOURCE_MEM, - }, { - .start = WDT_INT, - .end = WDT_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_wdt_device = { - .name = "imx-wdt", - .id = 0, - .resource = imx_wdt_resources, - .num_resources = ARRAY_SIZE(imx_wdt_resources), -}; - -static struct resource imx_usb_resources[] = { - { - .start = 0x00212000, - .end = 0x00212148, - .flags = IORESOURCE_MEM, - }, { - .start = USBD_INT0, - .end = USBD_INT0, - .flags = IORESOURCE_IRQ, - }, { - .start = USBD_INT1, - .end = USBD_INT1, - .flags = IORESOURCE_IRQ, - }, { - .start = USBD_INT2, - .end = USBD_INT2, - .flags = IORESOURCE_IRQ, - }, { - .start = USBD_INT3, - .end = USBD_INT3, - .flags = IORESOURCE_IRQ, - }, { - .start = USBD_INT4, - .end = USBD_INT4, - .flags = IORESOURCE_IRQ, - }, { - .start = USBD_INT5, - .end = USBD_INT5, - .flags = IORESOURCE_IRQ, - }, { - .start = USBD_INT6, - .end = USBD_INT6, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_usb_device = { - .name = "imx_udc", - .id = 0, - .num_resources = ARRAY_SIZE(imx_usb_resources), - .resource = imx_usb_resources, -}; - -/* GPIO port description */ -static struct mxc_gpio_port imx_gpio_ports[] = { - { - .chip.label = "gpio-0", - .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR), - .irq = GPIO_INT_PORTA, - .virtual_irq_start = MXC_GPIO_IRQ_START, - }, { - .chip.label = "gpio-1", - .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100), - .irq = GPIO_INT_PORTB, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32, - }, { - .chip.label = "gpio-2", - .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200), - .irq = GPIO_INT_PORTC, - .virtual_irq_start = MXC_GPIO_IRQ_START + 64, - }, { - .chip.label = "gpio-3", - .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300), - .irq = GPIO_INT_PORTD, - .virtual_irq_start = MXC_GPIO_IRQ_START + 96, - } -}; - -int __init mxc_register_gpios(void) -{ - return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); -} diff --git a/arch/arm/mach-mx1/devices.h b/arch/arm/mach-mx1/devices.h deleted file mode 100644 index 0da5d7cce3a2..000000000000 --- a/arch/arm/mach-mx1/devices.h +++ /dev/null @@ -1,7 +0,0 @@ -extern struct platform_device imx_csi_device; -extern struct platform_device imx_i2c_device; -extern struct platform_device imx_uart1_device; -extern struct platform_device imx_uart2_device; -extern struct platform_device imx_rtc_device; -extern struct platform_device imx_wdt_device; -extern struct platform_device imx_usb_device; diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c deleted file mode 100644 index 1c0c835b2252..000000000000 --- a/arch/arm/mach-mx2/serial.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/serial.h> -#include <mach/hardware.h> -#include <mach/imx-uart.h> -#include "devices.h" - -static struct resource uart0[] = { - { - .start = MX2x_UART1_BASE_ADDR, - .end = MX2x_UART1_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MX2x_INT_UART1, - .end = MX2x_INT_UART1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device0 = { - .name = "imx-uart", - .id = 0, - .resource = uart0, - .num_resources = ARRAY_SIZE(uart0), -}; - -static struct resource uart1[] = { - { - .start = MX2x_UART2_BASE_ADDR, - .end = MX2x_UART2_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MX2x_INT_UART2, - .end = MX2x_INT_UART2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device1 = { - .name = "imx-uart", - .id = 1, - .resource = uart1, - .num_resources = ARRAY_SIZE(uart1), -}; - -static struct resource uart2[] = { - { - .start = MX2x_UART3_BASE_ADDR, - .end = MX2x_UART3_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MX2x_INT_UART3, - .end = MX2x_INT_UART3, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device2 = { - .name = "imx-uart", - .id = 2, - .resource = uart2, - .num_resources = ARRAY_SIZE(uart2), -}; - -static struct resource uart3[] = { - { - .start = MX2x_UART4_BASE_ADDR, - .end = MX2x_UART4_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MX2x_INT_UART4, - .end = MX2x_INT_UART4, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device3 = { - .name = "imx-uart", - .id = 3, - .resource = uart3, - .num_resources = ARRAY_SIZE(uart3), -}; - -#ifdef CONFIG_MACH_MX27 -static struct resource uart4[] = { - { - .start = MX27_UART5_BASE_ADDR, - .end = MX27_UART5_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_INT_UART5, - .end = MX27_INT_UART5, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device4 = { - .name = "imx-uart", - .id = 4, - .resource = uart4, - .num_resources = ARRAY_SIZE(uart4), -}; - -static struct resource uart5[] = { - { - .start = MX27_UART6_BASE_ADDR, - .end = MX27_UART6_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_INT_UART6, - .end = MX27_INT_UART6, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device5 = { - .name = "imx-uart", - .id = 5, - .resource = uart5, - .num_resources = ARRAY_SIZE(uart5), -}; -#endif diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig index 54d217314ee9..c71a7bc19284 100644 --- a/arch/arm/mach-mx25/Kconfig +++ b/arch/arm/mach-mx25/Kconfig @@ -4,5 +4,28 @@ comment "MX25 platforms:" config MACH_MX25_3DS bool "Support MX25PDK (3DS) Platform" + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND + +config MACH_EUKREA_CPUIMX25 + bool "Support Eukrea CPUIMX25 Platform" + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND + select MXC_ULPI if USB_ULPI + +choice + prompt "Baseboard" + depends on MACH_EUKREA_CPUIMX25 + default MACH_EUKREA_MBIMXSD25_BASEBOARD + +config MACH_EUKREA_MBIMXSD25_BASEBOARD + prompt "Eukrea MBIMXSD development board" + bool + help + This adds board specific devices that can be found on Eukrea's + MBIMXSD evaluation board. + +endchoice endif diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile index 10cebc5ced8c..d9e46ce00a4e 100644 --- a/arch/arm/mach-mx25/Makefile +++ b/arch/arm/mach-mx25/Makefile @@ -1,3 +1,5 @@ obj-y := mm.o devices.o obj-$(CONFIG_ARCH_MX25) += clock.o -obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25pdk.o +obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o +obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-cpuimx25.o +obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd-baseboard.o diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index 155014993b13..40c7cc41cee3 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c @@ -109,6 +109,16 @@ static unsigned long get_rate_uart(struct clk *clk) return get_rate_per(15); } +static unsigned long get_rate_ssi2(struct clk *clk) +{ + return get_rate_per(14); +} + +static unsigned long get_rate_ssi1(struct clk *clk) +{ + return get_rate_per(13); +} + static unsigned long get_rate_i2c(struct clk *clk) { return get_rate_per(6); @@ -129,9 +139,17 @@ static unsigned long get_rate_lcdc(struct clk *clk) return get_rate_per(7); } +static unsigned long get_rate_csi(struct clk *clk) +{ + return get_rate_per(0); +} + static unsigned long get_rate_otg(struct clk *clk) { - return 48000000; /* FIXME */ + unsigned long cctl = readl(CRM_BASE + CCM_CCTL); + unsigned long rate = get_rate_upll(); + + return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1); } static int clk_cgcr_enable(struct clk *clk) @@ -166,14 +184,40 @@ static void clk_cgcr_disable(struct clk *clk) .secondary = s, \ } +/* + * Note: the following IPG clock gating bits are wrongly marked "Reserved" in + * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is + * taken from the Freescale released BSP. + * + * bit reg offset clock + * + * 0 CGCR1 0 AUDMUX + * 12 CGCR1 12 ESAI + * 16 CGCR1 16 GPIO1 + * 17 CGCR1 17 GPIO2 + * 18 CGCR1 18 GPIO3 + * 23 CGCR1 23 I2C1 + * 24 CGCR1 24 I2C2 + * 25 CGCR1 25 I2C3 + * 27 CGCR1 27 IOMUXC + * 28 CGCR1 28 KPP + * 30 CGCR1 30 OWIRE + * 36 CGCR2 4 RTIC + * 51 CGCR2 19 WDOG + */ + DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL); DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL); +DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL); +DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); +DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL); +DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk); DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk); @@ -191,6 +235,13 @@ DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL); DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk); DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk); +DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL); +DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); +DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); +DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); +DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); +DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL); +DEFINE_CLOCK(can2_clk, 0, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL); #define _REGISTER_CLOCK(d, n, c) \ { \ @@ -217,7 +268,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk) _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk) _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk) - _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk) + _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk) _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk) _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk) @@ -225,6 +276,13 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("fec.0", NULL, fec_clk) _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) + _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk) + _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) + _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) + _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) + _REGISTER_CLOCK(NULL, "audmux", audmux_clk) + _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) + _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) }; int __init mx25_clocks_init(void) @@ -238,9 +296,13 @@ int __init mx25_clocks_init(void) __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0); __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); +#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) + clk_enable(&uart1_clk); +#endif - /* Clock source for lcdc is upll */ - __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64); + /* Clock source for lcdc and csi is upll */ + __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0), + CRM_BASE + 0x64); mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h new file mode 100644 index 000000000000..d86a7c3ca8b0 --- /dev/null +++ b/arch/arm/mach-mx25/devices-imx25.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx25.h> +#include <mach/devices-common.h> + +#define imx25_add_flexcan0(pdata) \ + imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata) +#define imx25_add_flexcan1(pdata) \ + imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata) + +#define imx25_add_imx_i2c0(pdata) \ + imx_add_imx_i2c(0, MX25_I2C1_BASE_ADDR, SZ_16K, MX25_INT_I2C1, pdata) +#define imx25_add_imx_i2c1(pdata) \ + imx_add_imx_i2c(1, MX25_I2C2_BASE_ADDR, SZ_16K, MX25_INT_I2C2, pdata) +#define imx25_add_imx_i2c2(pdata) \ + imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata) + +#define imx25_add_imx_uart0(pdata) \ + imx_add_imx_uart_1irq(0, MX25_UART1_BASE_ADDR, SZ_16K, MX25_INT_UART1, pdata) +#define imx25_add_imx_uart1(pdata) \ + imx_add_imx_uart_1irq(1, MX25_UART2_BASE_ADDR, SZ_16K, MX25_INT_UART2, pdata) +#define imx25_add_imx_uart2(pdata) \ + imx_add_imx_uart_1irq(2, MX25_UART3_BASE_ADDR, SZ_16K, MX25_INT_UART3, pdata) +#define imx25_add_imx_uart3(pdata) \ + imx_add_imx_uart_1irq(3, MX25_UART4_BASE_ADDR, SZ_16K, MX25_INT_UART4, pdata) +#define imx25_add_imx_uart4(pdata) \ + imx_add_imx_uart_1irq(4, MX25_UART5_BASE_ADDR, SZ_16K, MX25_INT_UART5, pdata) + +#define imx25_add_mxc_nand(pdata) \ + imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata) + +#define imx25_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX25_CSPI1_BASE_ADDR, SZ_16K, MX25_INT_CSPI1, pdata) +#define imx25_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX25_CSPI2_BASE_ADDR, SZ_16K, MX25_INT_CSPI2, pdata) +#define imx25_add_spi_imx2(pdata) \ + imx_add_spi_imx(2, MX25_CSPI3_BASE_ADDR, SZ_16K, MX25_INT_CSPI3, pdata) diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c index 3a405fa400eb..3468eb15b236 100644 --- a/arch/arm/mach-mx25/devices.c +++ b/arch/arm/mach-mx25/devices.c @@ -22,103 +22,6 @@ #include <mach/mx25.h> #include <mach/irqs.h> -static struct resource uart0[] = { - { - .start = 0x43f90000, - .end = 0x43f93fff, - .flags = IORESOURCE_MEM, - }, { - .start = 45, - .end = 45, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device0 = { - .name = "imx-uart", - .id = 0, - .resource = uart0, - .num_resources = ARRAY_SIZE(uart0), -}; - -static struct resource uart1[] = { - { - .start = 0x43f94000, - .end = 0x43f97fff, - .flags = IORESOURCE_MEM, - }, { - .start = 32, - .end = 32, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device1 = { - .name = "imx-uart", - .id = 1, - .resource = uart1, - .num_resources = ARRAY_SIZE(uart1), -}; - -static struct resource uart2[] = { - { - .start = 0x5000c000, - .end = 0x5000ffff, - .flags = IORESOURCE_MEM, - }, { - .start = 18, - .end = 18, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device2 = { - .name = "imx-uart", - .id = 2, - .resource = uart2, - .num_resources = ARRAY_SIZE(uart2), -}; - -static struct resource uart3[] = { - { - .start = 0x50008000, - .end = 0x5000bfff, - .flags = IORESOURCE_MEM, - }, { - .start = 5, - .end = 5, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device3 = { - .name = "imx-uart", - .id = 3, - .resource = uart3, - .num_resources = ARRAY_SIZE(uart3), -}; - -static struct resource uart4[] = { - { - .start = 0x5002c000, - .end = 0x5002ffff, - .flags = IORESOURCE_MEM, - }, { - .start = 40, - .end = 40, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device4 = { - .name = "imx-uart", - .id = 4, - .resource = uart4, - .num_resources = ARRAY_SIZE(uart4), -}; - -#define MX25_OTG_BASE_ADDR 0x53FF4000 - static u64 otg_dmamask = DMA_BIT_MASK(32); static struct resource mxc_otg_resources[] = { @@ -181,63 +84,6 @@ struct platform_device mxc_usbh2 = { .num_resources = ARRAY_SIZE(mxc_usbh2_resources), }; -static struct resource mxc_spi_resources0[] = { - { - .start = 0x43fa4000, - .end = 0x43fa7fff, - .flags = IORESOURCE_MEM, - }, { - .start = 14, - .end = 14, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_spi_device0 = { - .name = "spi_imx", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_spi_resources0), - .resource = mxc_spi_resources0, -}; - -static struct resource mxc_spi_resources1[] = { - { - .start = 0x50010000, - .end = 0x50013fff, - .flags = IORESOURCE_MEM, - }, { - .start = 13, - .end = 13, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_spi_device1 = { - .name = "spi_imx", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_spi_resources1), - .resource = mxc_spi_resources1, -}; - -static struct resource mxc_spi_resources2[] = { - { - .start = 0x50004000, - .end = 0x50007fff, - .flags = IORESOURCE_MEM, - }, { - .start = 0, - .end = 0, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_spi_device2 = { - .name = "spi_imx", - .id = 2, - .num_resources = ARRAY_SIZE(mxc_spi_resources2), - .resource = mxc_spi_resources2, -}; - static struct resource mxc_pwm_resources0[] = { { .start = 0x53fe0000, @@ -333,63 +179,6 @@ struct platform_device mxc_pwm_device3 = { .resource = mxc_pwm_resources3, }; -static struct resource mxc_i2c_1_resources[] = { - { - .start = 0x43f80000, - .end = 0x43f83fff, - .flags = IORESOURCE_MEM, - }, { - .start = 3, - .end = 3, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_i2c_device0 = { - .name = "imx-i2c", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_i2c_1_resources), - .resource = mxc_i2c_1_resources, -}; - -static struct resource mxc_i2c_2_resources[] = { - { - .start = 0x43f98000, - .end = 0x43f9bfff, - .flags = IORESOURCE_MEM, - }, { - .start = 4, - .end = 4, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_i2c_device1 = { - .name = "imx-i2c", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_i2c_2_resources), - .resource = mxc_i2c_2_resources, -}; - -static struct resource mxc_i2c_3_resources[] = { - { - .start = 0x43f84000, - .end = 0x43f87fff, - .flags = IORESOURCE_MEM, - }, { - .start = 10, - .end = 10, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_i2c_device2 = { - .name = "imx-i2c", - .id = 2, - .num_resources = ARRAY_SIZE(mxc_i2c_3_resources), - .resource = mxc_i2c_3_resources, -}; - static struct mxc_gpio_port imx_gpio_ports[] = { { .chip.label = "gpio-0", @@ -414,7 +203,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = { } }; -int __init mxc_register_gpios(void) +int __init imx25_register_gpios(void) { return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); } @@ -439,26 +228,6 @@ struct platform_device mx25_fec_device = { .resource = mx25_fec_resources, }; -static struct resource mxc_nand_resources[] = { - { - .start = MX25_NFC_BASE_ADDR, - .end = MX25_NFC_BASE_ADDR + 0x1fff, - .flags = IORESOURCE_MEM, - }, - { - .start = MX25_INT_NANDFC, - .end = MX25_INT_NANDFC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_nand_device = { - .name = "mxc_nand", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_nand_resources), - .resource = mxc_nand_resources, -}; - static struct resource mx25_rtc_resources[] = { { .start = MX25_DRYICE_BASE_ADDR, @@ -515,3 +284,83 @@ struct platform_device mxc_wdt = { .num_resources = ARRAY_SIZE(mxc_wdt_resources), .resource = mxc_wdt_resources, }; + +static struct resource mx25_kpp_resources[] = { + { + .start = MX25_KPP_BASE_ADDR, + .end = MX25_KPP_BASE_ADDR + 0xf, + .flags = IORESOURCE_MEM, + }, + { + .start = MX25_INT_KPP, + .end = MX25_INT_KPP, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mx25_kpp_device = { + .name = "imx-keypad", + .id = -1, + .num_resources = ARRAY_SIZE(mx25_kpp_resources), + .resource = mx25_kpp_resources, +}; + +static struct resource imx_ssi_resources0[] = { + { + .start = MX25_SSI1_BASE_ADDR, + .end = MX25_SSI1_BASE_ADDR + 0x3fff, + .flags = IORESOURCE_MEM, + }, { + .start = MX25_INT_SSI1, + .end = MX25_INT_SSI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource imx_ssi_resources1[] = { + { + .start = MX25_SSI2_BASE_ADDR, + .end = MX25_SSI2_BASE_ADDR + 0x3fff, + .flags = IORESOURCE_MEM + }, { + .start = MX25_INT_SSI2, + .end = MX25_INT_SSI2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_ssi_device0 = { + .name = "imx-ssi", + .id = 0, + .num_resources = ARRAY_SIZE(imx_ssi_resources0), + .resource = imx_ssi_resources0, +}; + +struct platform_device imx_ssi_device1 = { + .name = "imx-ssi", + .id = 1, + .num_resources = ARRAY_SIZE(imx_ssi_resources1), + .resource = imx_ssi_resources1, +}; + +static struct resource mx25_csi_resources[] = { + { + .start = MX25_CSI_BASE_ADDR, + .end = MX25_CSI_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + { + .start = MX25_INT_CSI, + .flags = IORESOURCE_IRQ + }, +}; + +struct platform_device mx25_csi_device = { + .name = "mx2-camera", + .id = 0, + .num_resources = ARRAY_SIZE(mx25_csi_resources), + .resource = mx25_csi_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h index cee12c0a0be6..4aceb68e35a7 100644 --- a/arch/arm/mach-mx25/devices.h +++ b/arch/arm/mach-mx25/devices.h @@ -1,24 +1,16 @@ -extern struct platform_device mxc_uart_device0; -extern struct platform_device mxc_uart_device1; -extern struct platform_device mxc_uart_device2; -extern struct platform_device mxc_uart_device3; -extern struct platform_device mxc_uart_device4; extern struct platform_device mxc_otg; extern struct platform_device otg_udc_device; extern struct platform_device mxc_usbh2; -extern struct platform_device mxc_spi_device0; -extern struct platform_device mxc_spi_device1; -extern struct platform_device mxc_spi_device2; extern struct platform_device mxc_pwm_device0; extern struct platform_device mxc_pwm_device1; extern struct platform_device mxc_pwm_device2; extern struct platform_device mxc_pwm_device3; extern struct platform_device mxc_keypad_device; -extern struct platform_device mxc_i2c_device0; -extern struct platform_device mxc_i2c_device1; -extern struct platform_device mxc_i2c_device2; extern struct platform_device mx25_fec_device; -extern struct platform_device mxc_nand_device; extern struct platform_device mx25_rtc_device; extern struct platform_device mx25_fb_device; extern struct platform_device mxc_wdt; +extern struct platform_device mx25_kpp_device; +extern struct platform_device imx_ssi_device0; +extern struct platform_device imx_ssi_device1; +extern struct platform_device mx25_csi_device; diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c new file mode 100644 index 000000000000..91931dcb0689 --- /dev/null +++ b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c @@ -0,0 +1,260 @@ +/* + * Copyright (C) 2010 Eric Benard - eric@eukrea.com + * + * Based on pcm970-baseboard.c which is : + * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/gpio.h> +#include <linux/leds.h> +#include <linux/platform_device.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <video/platform_lcd.h> + +#include <mach/hardware.h> +#include <mach/iomux-mx25.h> +#include <mach/common.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/mx25.h> +#include <mach/imx-uart.h> +#include <mach/imxfb.h> +#include <mach/ssi.h> +#include <mach/audmux.h> + +#include "devices-imx25.h" +#include "devices.h" + +static struct pad_desc eukrea_mbimxsd_pads[] = { + /* LCD */ + MX25_PAD_LD0__LD0, + MX25_PAD_LD1__LD1, + MX25_PAD_LD2__LD2, + MX25_PAD_LD3__LD3, + MX25_PAD_LD4__LD4, + MX25_PAD_LD5__LD5, + MX25_PAD_LD6__LD6, + MX25_PAD_LD7__LD7, + MX25_PAD_LD8__LD8, + MX25_PAD_LD9__LD9, + MX25_PAD_LD10__LD10, + MX25_PAD_LD11__LD11, + MX25_PAD_LD12__LD12, + MX25_PAD_LD13__LD13, + MX25_PAD_LD14__LD14, + MX25_PAD_LD15__LD15, + MX25_PAD_GPIO_E__LD16, + MX25_PAD_GPIO_F__LD17, + MX25_PAD_HSYNC__HSYNC, + MX25_PAD_VSYNC__VSYNC, + MX25_PAD_LSCLK__LSCLK, + MX25_PAD_OE_ACD__OE_ACD, + MX25_PAD_CONTRAST__CONTRAST, + /* LCD_PWR */ + MX25_PAD_PWM__GPIO_1_26, + /* LED */ + MX25_PAD_POWER_FAIL__GPIO_3_19, + /* SWITCH */ + MX25_PAD_VSTBY_ACK__GPIO_3_18, + /* UART2 */ + MX25_PAD_UART2_RTS__UART2_RTS, + MX25_PAD_UART2_CTS__UART2_CTS, + MX25_PAD_UART2_TXD__UART2_TXD, + MX25_PAD_UART2_RXD__UART2_RXD, + /* SD1 */ + MX25_PAD_SD1_CMD__SD1_CMD, + MX25_PAD_SD1_CLK__SD1_CLK, + MX25_PAD_SD1_DATA0__SD1_DATA0, + MX25_PAD_SD1_DATA1__SD1_DATA1, + MX25_PAD_SD1_DATA2__SD1_DATA2, + MX25_PAD_SD1_DATA3__SD1_DATA3, + /* SD1 CD */ + MX25_PAD_DE_B__GPIO_2_20, + /* I2S */ + MX25_PAD_KPP_COL3__AUD5_TXFS, + MX25_PAD_KPP_COL2__AUD5_TXC, + MX25_PAD_KPP_COL1__AUD5_RXD, + MX25_PAD_KPP_COL0__AUD5_TXD, +}; + +#define GPIO_LED1 83 +#define GPIO_SWITCH1 82 +#define GPIO_SD1CD 52 +#define GPIO_LCDPWR 26 + +static struct imx_fb_videomode eukrea_mximxsd_modes[] = { + { + .mode = { + .name = "CMO-QVGA", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6500), + .left_margin = 30, + .right_margin = 38, + .upper_margin = 20, + .lower_margin = 3, + .hsync_len = 15, + .vsync_len = 4, + }, + .bpp = 16, + .pcr = 0xCAD08B80, + }, +}; + +static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = { + .mode = eukrea_mximxsd_modes, + .num_modes = ARRAY_SIZE(eukrea_mximxsd_modes), + .pwmr = 0x00A903FF, + .lscr1 = 0x00120300, + .dmacr = 0x00040060, +}; + +static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, + unsigned int power) +{ + if (power) + gpio_direction_output(GPIO_LCDPWR, 1); + else + gpio_direction_output(GPIO_LCDPWR, 0); +} + +static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = { + .set_power = eukrea_mbimxsd_lcd_power_set, +}; + +static struct platform_device eukrea_mbimxsd_lcd_powerdev = { + .name = "platform-lcd", + .dev.platform_data = &eukrea_mbimxsd_lcd_power_data, +}; + +static struct gpio_led eukrea_mbimxsd_leds[] = { + { + .name = "led1", + .default_trigger = "heartbeat", + .active_low = 1, + .gpio = GPIO_LED1, + }, +}; + +static struct gpio_led_platform_data eukrea_mbimxsd_led_info = { + .leds = eukrea_mbimxsd_leds, + .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds), +}; + +static struct platform_device eukrea_mbimxsd_leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &eukrea_mbimxsd_led_info, + }, +}; + +static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { + { + .gpio = GPIO_SWITCH1, + .code = BTN_0, + .desc = "BP1", + .active_low = 1, + .wakeup = 1, + }, +}; + +static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = { + .buttons = eukrea_mbimxsd_gpio_buttons, + .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), +}; + +static struct platform_device eukrea_mbimxsd_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &eukrea_mbimxsd_button_data, + } +}; + +static struct platform_device *platform_devices[] __initdata = { + &eukrea_mbimxsd_leds_gpio, + &eukrea_mbimxsd_button_device, + &eukrea_mbimxsd_lcd_powerdev, +}; + +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = { + { + I2C_BOARD_INFO("tlv320aic23", 0x1a), + }, +}; + +struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = { + .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, +}; + +/* + * system init for baseboard usage. Will be called by cpuimx25 init. + * + * Add platform devices present on this baseboard and init + * them from CPU side as far as required to use them later on + */ +void __init eukrea_mbimxsd_baseboard_init(void) +{ + if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads, + ARRAY_SIZE(eukrea_mbimxsd_pads))) + printk(KERN_ERR "error setting mbimxsd pads !\n"); + +#if defined(CONFIG_SND_SOC_EUKREA_TLV320) + /* SSI unit master I2S codec connected to SSI_AUD5*/ + mxc_audmux_v2_configure_port(0, + MXC_AUDMUX_V2_PTCR_SYN | + MXC_AUDMUX_V2_PTCR_TFSDIR | + MXC_AUDMUX_V2_PTCR_TFSEL(4) | + MXC_AUDMUX_V2_PTCR_TCLKDIR | + MXC_AUDMUX_V2_PTCR_TCSEL(4), + MXC_AUDMUX_V2_PDCR_RXDSEL(4) + ); + mxc_audmux_v2_configure_port(4, + MXC_AUDMUX_V2_PTCR_SYN, + MXC_AUDMUX_V2_PDCR_RXDSEL(0) + ); +#endif + + imx25_add_imx_uart1(&uart_pdata); + mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata); + mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata); + + gpio_request(GPIO_LED1, "LED1"); + gpio_direction_output(GPIO_LED1, 1); + gpio_free(GPIO_LED1); + + gpio_request(GPIO_SWITCH1, "SWITCH1"); + gpio_direction_input(GPIO_SWITCH1); + gpio_free(GPIO_SWITCH1); + + gpio_request(GPIO_LCDPWR, "LCDPWR"); + gpio_direction_output(GPIO_LCDPWR, 1); + gpio_free(GPIO_SWITCH1); + + i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, + ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); + + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); +} diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c new file mode 100644 index 000000000000..56b2e26d23b4 --- /dev/null +++ b/arch/arm/mach-mx25/mach-cpuimx25.c @@ -0,0 +1,173 @@ +/* + * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de> + * Copyright 2010 Eric Bénard - Eukréa Electromatique, <eric@eukrea.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + */ + +#include <linux/types.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <linux/fec.h> +#include <linux/platform_device.h> +#include <linux/usb/otg.h> +#include <linux/usb/ulpi.h> +#include <linux/fsl_devices.h> + +#include <mach/eukrea-baseboards.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/memory.h> +#include <asm/mach/map.h> +#include <mach/common.h> +#include <mach/mx25.h> +#include <mach/mxc_nand.h> +#include <mach/imxfb.h> +#include <mach/mxc_ehci.h> +#include <mach/ulpi.h> +#include <mach/iomux-mx25.h> + +#include "devices-imx25.h" +#include "devices.h" + +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct pad_desc eukrea_cpuimx25_pads[] = { + /* FEC - RMII */ + MX25_PAD_FEC_MDC__FEC_MDC, + MX25_PAD_FEC_MDIO__FEC_MDIO, + MX25_PAD_FEC_TDATA0__FEC_TDATA0, + MX25_PAD_FEC_TDATA1__FEC_TDATA1, + MX25_PAD_FEC_TX_EN__FEC_TX_EN, + MX25_PAD_FEC_RDATA0__FEC_RDATA0, + MX25_PAD_FEC_RDATA1__FEC_RDATA1, + MX25_PAD_FEC_RX_DV__FEC_RX_DV, + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, + /* I2C1 */ + MX25_PAD_I2C1_CLK__I2C1_CLK, + MX25_PAD_I2C1_DAT__I2C1_DAT, +}; + +static struct fec_platform_data mx25_fec_pdata = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +static const struct mxc_nand_platform_data +eukrea_cpuimx25_nand_board_info __initconst = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static const struct imxi2c_platform_data +eukrea_cpuimx25_i2c0_data __initconst = { + .bitrate = 100000, +}; + +static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = { + { + I2C_BOARD_INFO("pcf8563", 0x51), + }, +}; + +static struct mxc_usbh_platform_data otg_pdata = { + .portsc = MXC_EHCI_MODE_UTMI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static struct mxc_usbh_platform_data usbh2_pdata = { + .portsc = MXC_EHCI_MODE_SERIAL, + .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | + MXC_EHCI_IPPUE_DOWN, +}; + +static struct fsl_usb2_platform_data otg_device_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI, +}; + +static int otg_mode_host; + +static int __init eukrea_cpuimx25_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", eukrea_cpuimx25_otg_mode); + +static void __init eukrea_cpuimx25_init(void) +{ + if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads, + ARRAY_SIZE(eukrea_cpuimx25_pads))) + printk(KERN_ERR "error setting cpuimx25 pads !\n"); + + imx25_add_imx_uart0(&uart_pdata); + imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info); + mxc_register_device(&mx25_rtc_device, NULL); + mxc_register_device(&mx25_fec_device, &mx25_fec_pdata); + + i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices, + ARRAY_SIZE(eukrea_cpuimx25_i2c_devices)); + imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data); + +#if defined(CONFIG_USB_ULPI) + if (otg_mode_host) { + otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_otg, &otg_pdata); + } + mxc_register_device(&mxc_usbh2, &usbh2_pdata); +#endif + if (!otg_mode_host) + mxc_register_device(&otg_udc_device, &otg_device_pdata); + +#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD + eukrea_mbimxsd_baseboard_init(); +#endif +} + +static void __init eukrea_cpuimx25_timer_init(void) +{ + mx25_clocks_init(); +} + +static struct sys_timer eukrea_cpuimx25_timer = { + .init = eukrea_cpuimx25_timer_init, +}; + +MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25") + /* Maintainer: Eukrea Electromatique */ + .phys_io = MX25_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX25_PHYS_OFFSET + 0x100, + .map_io = mx25_map_io, + .init_irq = mx25_init_irq, + .init_machine = eukrea_cpuimx25_init, + .timer = &eukrea_cpuimx25_timer, +MACHINE_END diff --git a/arch/arm/mach-mx25/mach-mx25pdk.c b/arch/arm/mach-mx25/mach-mx25_3ds.c index 83d74109e7d8..62bc21f11a71 100644 --- a/arch/arm/mach-mx25/mach-mx25pdk.c +++ b/arch/arm/mach-mx25/mach-mx25_3ds.c @@ -16,6 +16,12 @@ * Boston, MA 02110-1301, USA. */ +/* + * This machine is known as: + * - i.MX25 3-Stack Development System + * - i.MX25 Platform Development Kit (i.MX25 PDK) + */ + #include <linux/types.h> #include <linux/init.h> #include <linux/delay.h> @@ -24,6 +30,7 @@ #include <linux/gpio.h> #include <linux/fec.h> #include <linux/platform_device.h> +#include <linux/input/matrix_keypad.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -32,14 +39,14 @@ #include <asm/memory.h> #include <asm/mach/map.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/mx25.h> -#include <mach/mxc_nand.h> #include <mach/imxfb.h> -#include "devices.h" #include <mach/iomux-mx25.h> -static struct imxuart_platform_data uart_pdata = { +#include "devices-imx25.h" +#include "devices.h" + +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -80,6 +87,16 @@ static struct pad_desc mx25pdk_pads[] = { MX25_PAD_LSCLK__LSCLK, MX25_PAD_OE_ACD__OE_ACD, MX25_PAD_CONTRAST__CONTRAST, + + /* Keypad */ + MX25_PAD_KPP_ROW0__KPP_ROW0, + MX25_PAD_KPP_ROW1__KPP_ROW1, + MX25_PAD_KPP_ROW2__KPP_ROW2, + MX25_PAD_KPP_ROW3__KPP_ROW3, + MX25_PAD_KPP_COL0__KPP_COL0, + MX25_PAD_KPP_COL1__KPP_COL1, + MX25_PAD_KPP_COL2__KPP_COL2, + MX25_PAD_KPP_COL3__KPP_COL3, }; static struct fec_platform_data mx25_fec_pdata = { @@ -103,7 +120,8 @@ static void __init mx25pdk_fec_reset(void) gpio_set_value(FEC_RESET_B_GPIO, 1); } -static struct mxc_nand_platform_data mx25pdk_nand_board_info = { +static const struct mxc_nand_platform_data +mx25pdk_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, .flash_bbt = 1, @@ -137,19 +155,45 @@ static struct imx_fb_platform_data mx25pdk_fb_pdata = { .dmacr = 0x00020010, }; +static const uint32_t mx25pdk_keymap[] = { + KEY(0, 0, KEY_UP), + KEY(0, 1, KEY_DOWN), + KEY(0, 2, KEY_VOLUMEDOWN), + KEY(0, 3, KEY_HOME), + KEY(1, 0, KEY_RIGHT), + KEY(1, 1, KEY_LEFT), + KEY(1, 2, KEY_ENTER), + KEY(1, 3, KEY_VOLUMEUP), + KEY(2, 0, KEY_F6), + KEY(2, 1, KEY_F8), + KEY(2, 2, KEY_F9), + KEY(2, 3, KEY_F10), + KEY(3, 0, KEY_F1), + KEY(3, 1, KEY_F2), + KEY(3, 2, KEY_F3), + KEY(3, 3, KEY_POWER), +}; + +static struct matrix_keymap_data mx25pdk_keymap_data = { + .keymap = mx25pdk_keymap, + .keymap_size = ARRAY_SIZE(mx25pdk_keymap), +}; + static void __init mx25pdk_init(void) { mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, ARRAY_SIZE(mx25pdk_pads)); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx25_add_imx_uart0(&uart_pdata); mxc_register_device(&mxc_usbh2, NULL); - mxc_register_device(&mxc_nand_device, &mx25pdk_nand_board_info); + imx25_add_mxc_nand(&mx25pdk_nand_board_info); mxc_register_device(&mx25_rtc_device, NULL); mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata); + mxc_register_device(&mxc_wdt, NULL); mx25pdk_fec_reset(); mxc_register_device(&mx25_fec_device, &mx25_fec_pdata); + mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data); } static void __init mx25pdk_timer_init(void) diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-mx25/mm.c index a7e587ff3e9e..bb677111fb0f 100644 --- a/arch/arm/mach-mx25/mm.c +++ b/arch/arm/mach-mx25/mm.c @@ -14,10 +14,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/mm.h> @@ -69,8 +65,11 @@ void __init mx25_map_io(void) iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); } +int imx25_register_gpios(void); + void __init mx25_init_irq(void) { mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT); + imx25_register_gpios(); } diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 344753fdf25e..85beece802aa 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -15,6 +15,8 @@ comment "MX3 platforms:" config MACH_MX31ADS bool "Support MX31ADS platforms" select ARCH_MX31 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART default y help Include support for MX31ADS platform. This includes specific @@ -34,6 +36,9 @@ config MACH_MX31ADS_WM1133_EV1 config MACH_PCM037 bool "Support Phytec pcm037 (i.MX31) platforms" select ARCH_MX31 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND select MXC_ULPI if USB_ULPI help Include support for Phytec pcm037 platform. This includes @@ -42,6 +47,7 @@ config MACH_PCM037 config MACH_PCM037_EET bool "Support pcm037 EET board extensions" depends on MACH_PCM037 + select IMX_HAVE_PLATFORM_SPI_IMX help Add support for PCM037 EET baseboard extensions. If you are using the OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel @@ -51,6 +57,9 @@ config MACH_MX31LITE bool "Support MX31 LITEKIT (LogicPD)" select ARCH_MX31 select MXC_ULPI if USB_ULPI + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SPI_IMX help Include support for MX31 LITEKIT platform. This includes specific configurations for the board and its peripherals. @@ -58,6 +67,10 @@ config MACH_MX31LITE config MACH_MX31_3DS bool "Support MX31PDK (3DS)" select ARCH_MX31 + select MXC_DEBUG_BOARD + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SPI_IMX help Include support for MX31PDK (3DS) platform. This includes specific configurations for the board and its peripherals. @@ -74,6 +87,9 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT config MACH_MX31MOBOARD bool "Support mx31moboard platforms (EPFL Mobots group)" select ARCH_MX31 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help Include support for mx31moboard platform. This includes specific @@ -82,6 +98,8 @@ config MACH_MX31MOBOARD config MACH_MX31LILLY bool "Support MX31 LILLY-1131 platforms (INCO startec)" select ARCH_MX31 + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help Include support for mx31 based LILLY1131 modules. This includes @@ -90,6 +108,7 @@ config MACH_MX31LILLY config MACH_QONG bool "Support Dave/DENX QongEVB-LITE platform" select ARCH_MX31 + select IMX_HAVE_PLATFORM_IMX_UART help Include support for Dave/DENX QongEVB-LITE platform. This includes specific configurations for the board and its peripherals. @@ -97,6 +116,10 @@ config MACH_QONG config MACH_PCM043 bool "Support Phytec pcm043 (i.MX35) platforms" select ARCH_MX35 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_FLEXCAN select MXC_ULPI if USB_ULPI help Include support for Phytec pcm043 platform. This includes @@ -105,6 +128,9 @@ config MACH_PCM043 config MACH_ARMADILLO5X0 bool "Support Atmark Armadillo-500 Development Base Board" select ARCH_MX31 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND select MXC_ULPI if USB_ULPI help Include support for Atmark Armadillo-500 platform. This includes @@ -113,6 +139,7 @@ config MACH_ARMADILLO5X0 config MACH_MX35_3DS bool "Support MX35PDK platform" select ARCH_MX35 + select IMX_HAVE_PLATFORM_IMX_UART default n help Include support for MX35PDK platform. This includes specific @@ -121,8 +148,34 @@ config MACH_MX35_3DS config MACH_KZM_ARM11_01 bool "Support KZM-ARM11-01(Kyoto Microcomputer)" select ARCH_MX31 + select IMX_HAVE_PLATFORM_IMX_UART help Include support for KZM-ARM11-01. This includes specific configurations for the board and its peripherals. +config MACH_EUKREA_CPUIMX35 + bool "Support Eukrea CPUIMX35 Platform" + select ARCH_MX35 + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_MXC_NAND + select MXC_ULPI if USB_ULPI + help + Include support for Eukrea CPUIMX35 platform. This includes + specific configurations for the board and its peripherals. + +choice + prompt "Baseboard" + depends on MACH_EUKREA_CPUIMX35 + default MACH_EUKREA_MBIMXSD35_BASEBOARD + +config MACH_EUKREA_MBIMXSD35_BASEBOARD + prompt "Eukrea MBIMXSD development board" + bool + help + This adds board specific devices that can be found on Eukrea's + MBIMXSD evaluation board. + +endchoice + endif diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 5d650fda5d5d..2bd7beceb991 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -22,5 +22,7 @@ obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ obj-$(CONFIG_MACH_QONG) += mach-qong.o obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o -obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35pdk.o +obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o +obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o +obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd-baseboard.o diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index 9f3e943e2232..d3af0fdf8475 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -359,7 +359,7 @@ DEFINE_CLOCK(i2c1_clk, 0, CCM_CGR1, 10, get_rate_ipg_per, NULL); DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL); DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL); DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL); -DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, NULL, NULL); +DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, get_rate_ahb, NULL); DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL); DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL); DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL); @@ -428,8 +428,8 @@ static struct clk nfc_clk = { static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "asrc", asrc_clk) _REGISTER_CLOCK(NULL, "ata", ata_clk) - _REGISTER_CLOCK(NULL, "can", can1_clk) - _REGISTER_CLOCK(NULL, "can", can2_clk) + _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) + _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) _REGISTER_CLOCK(NULL, "ect", ect_clk) diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h new file mode 100644 index 000000000000..3b1a44a20585 --- /dev/null +++ b/arch/arm/mach-mx3/devices-imx31.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx31.h> +#include <mach/devices-common.h> + +#define imx31_add_imx_i2c0(pdata) \ + imx_add_imx_i2c(0, MX31_I2C1_BASE_ADDR, SZ_4K, MX31_INT_I2C1, pdata) +#define imx31_add_imx_i2c1(pdata) \ + imx_add_imx_i2c(1, MX31_I2C2_BASE_ADDR, SZ_4K, MX31_INT_I2C2, pdata) +#define imx31_add_imx_i2c2(pdata) \ + imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata) + +#define imx31_add_imx_uart0(pdata) \ + imx_add_imx_uart_1irq(0, MX31_UART1_BASE_ADDR, SZ_16K, MX31_INT_UART1, pdata) +#define imx31_add_imx_uart1(pdata) \ + imx_add_imx_uart_1irq(1, MX31_UART2_BASE_ADDR, SZ_16K, MX31_INT_UART2, pdata) +#define imx31_add_imx_uart2(pdata) \ + imx_add_imx_uart_1irq(2, MX31_UART3_BASE_ADDR, SZ_16K, MX31_INT_UART3, pdata) +#define imx31_add_imx_uart3(pdata) \ + imx_add_imx_uart_1irq(3, MX31_UART4_BASE_ADDR, SZ_16K, MX31_INT_UART4, pdata) +#define imx31_add_imx_uart4(pdata) \ + imx_add_imx_uart_1irq(4, MX31_UART5_BASE_ADDR, SZ_16K, MX31_INT_UART5, pdata) + +#define imx31_add_mxc_nand(pdata) \ + imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata) + +#define imx31_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata) +#define imx31_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2, pdata) +#define imx31_add_spi_imx2(pdata) \ + imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3, pdata) diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h new file mode 100644 index 000000000000..f6a431a4c3d2 --- /dev/null +++ b/arch/arm/mach-mx3/devices-imx35.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx35.h> +#include <mach/devices-common.h> + +#define imx35_add_flexcan0(pdata) \ + imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata) +#define imx35_add_flexcan1(pdata) \ + imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata) + +#define imx35_add_imx_i2c0(pdata) \ + imx_add_imx_i2c(0, MX35_I2C1_BASE_ADDR, SZ_4K, MX35_INT_I2C1, pdata) +#define imx35_add_imx_i2c1(pdata) \ + imx_add_imx_i2c(1, MX35_I2C2_BASE_ADDR, SZ_4K, MX35_INT_I2C2, pdata) +#define imx35_add_imx_i2c2(pdata) \ + imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata) + +#define imx35_add_imx_uart0(pdata) \ + imx_add_imx_uart_1irq(0, MX35_UART1_BASE_ADDR, SZ_16K, MX35_INT_UART1, pdata) +#define imx35_add_imx_uart1(pdata) \ + imx_add_imx_uart_1irq(1, MX35_UART2_BASE_ADDR, SZ_16K, MX35_INT_UART2, pdata) +#define imx35_add_imx_uart2(pdata) \ + imx_add_imx_uart_1irq(2, MX35_UART3_BASE_ADDR, SZ_16K, MX35_INT_UART3, pdata) + +#define imx35_add_mxc_nand(pdata) \ + imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata) + +#define imx35_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata) +#define imx35_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata) diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index db7acd6e9101..a4fd1a26fc91 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c @@ -25,108 +25,10 @@ #include <mach/hardware.h> #include <mach/irqs.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/mx3_camera.h> #include "devices.h" -static struct resource uart0[] = { - { - .start = UART1_BASE_ADDR, - .end = UART1_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_UART1, - .end = MXC_INT_UART1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device0 = { - .name = "imx-uart", - .id = 0, - .resource = uart0, - .num_resources = ARRAY_SIZE(uart0), -}; - -static struct resource uart1[] = { - { - .start = UART2_BASE_ADDR, - .end = UART2_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_UART2, - .end = MXC_INT_UART2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device1 = { - .name = "imx-uart", - .id = 1, - .resource = uart1, - .num_resources = ARRAY_SIZE(uart1), -}; - -static struct resource uart2[] = { - { - .start = UART3_BASE_ADDR, - .end = UART3_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_UART3, - .end = MXC_INT_UART3, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device2 = { - .name = "imx-uart", - .id = 2, - .resource = uart2, - .num_resources = ARRAY_SIZE(uart2), -}; - -#ifdef CONFIG_ARCH_MX31 -static struct resource uart3[] = { - { - .start = UART4_BASE_ADDR, - .end = UART4_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_UART4, - .end = MXC_INT_UART4, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device3 = { - .name = "imx-uart", - .id = 3, - .resource = uart3, - .num_resources = ARRAY_SIZE(uart3), -}; - -static struct resource uart4[] = { - { - .start = UART5_BASE_ADDR, - .end = UART5_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_UART5, - .end = MXC_INT_UART5, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device4 = { - .name = "imx-uart", - .id = 4, - .resource = uart4, - .num_resources = ARRAY_SIZE(uart4), -}; -#endif /* CONFIG_ARCH_MX31 */ - /* GPIO port description */ static struct mxc_gpio_port imx_gpio_ports[] = { { @@ -147,7 +49,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = { } }; -int __init mxc_register_gpios(void) +int __init imx3x_register_gpios(void) { return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); } @@ -167,82 +69,6 @@ struct platform_device mxc_w1_master_device = { .resource = mxc_w1_master_resources, }; -static struct resource mxc_nand_resources[] = { - { - .start = 0, /* runtime dependent */ - .end = 0, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_NANDFC, - .end = MXC_INT_NANDFC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_nand_device = { - .name = "mxc_nand", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_nand_resources), - .resource = mxc_nand_resources, -}; - -static struct resource mxc_i2c0_resources[] = { - { - .start = I2C_BASE_ADDR, - .end = I2C_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_I2C, - .end = MXC_INT_I2C, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_i2c_device0 = { - .name = "imx-i2c", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_i2c0_resources), - .resource = mxc_i2c0_resources, -}; - -static struct resource mxc_i2c1_resources[] = { - { - .start = I2C2_BASE_ADDR, - .end = I2C2_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_I2C2, - .end = MXC_INT_I2C2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_i2c_device1 = { - .name = "imx-i2c", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_i2c1_resources), - .resource = mxc_i2c1_resources, -}; - -static struct resource mxc_i2c2_resources[] = { - { - .start = I2C3_BASE_ADDR, - .end = I2C3_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_I2C3, - .end = MXC_INT_I2C3, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_i2c_device2 = { - .name = "imx-i2c", - .id = 2, - .num_resources = ARRAY_SIZE(mxc_i2c2_resources), - .resource = mxc_i2c2_resources, -}; - #ifdef CONFIG_ARCH_MX31 static struct resource mxcsdhc0_resources[] = { { @@ -455,68 +281,7 @@ struct platform_device mxc_usbh2 = { .num_resources = ARRAY_SIZE(mxc_usbh2_resources), }; -/* - * SPI master controller - * 3 channels - */ -static struct resource mxc_spi_0_resources[] = { - { - .start = CSPI1_BASE_ADDR, - .end = CSPI1_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI1, - .end = MXC_INT_CSPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource mxc_spi_1_resources[] = { - { - .start = CSPI2_BASE_ADDR, - .end = CSPI2_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI2, - .end = MXC_INT_CSPI2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource mxc_spi_2_resources[] = { - { - .start = CSPI3_BASE_ADDR, - .end = CSPI3_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI3, - .end = MXC_INT_CSPI3, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_spi_device0 = { - .name = "spi_imx", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_spi_0_resources), - .resource = mxc_spi_0_resources, -}; - -struct platform_device mxc_spi_device1 = { - .name = "spi_imx", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_spi_1_resources), - .resource = mxc_spi_1_resources, -}; - -struct platform_device mxc_spi_device2 = { - .name = "spi_imx", - .id = 2, - .num_resources = ARRAY_SIZE(mxc_spi_2_resources), - .resource = mxc_spi_2_resources, -}; - -#ifdef CONFIG_ARCH_MX35 +#if defined(CONFIG_ARCH_MX35) static struct resource mxc_fec_resources[] = { { .start = MXC_FEC_BASE_ADDR, @@ -628,16 +393,15 @@ struct platform_device imx_kpp_device = { static int __init mx3_devices_init(void) { +#if defined(CONFIG_ARCH_MX31) if (cpu_is_mx31()) { - mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR; - mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff; imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR; imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff; mxc_register_device(&mxc_rnga_device, NULL); } +#endif +#if defined(CONFIG_ARCH_MX35) if (cpu_is_mx35()) { - mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR; - mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff; otg_resources[0].start = MX35_OTG_BASE_ADDR; otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; otg_resources[1].start = MXC_INT_USBOTG; @@ -653,6 +417,7 @@ static int __init mx3_devices_init(void) imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; } +#endif return 0; } diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h index 2c3c8646a29e..e5535234839f 100644 --- a/arch/arm/mach-mx3/devices.h +++ b/arch/arm/mach-mx3/devices.h @@ -1,14 +1,4 @@ - -extern struct platform_device mxc_uart_device0; -extern struct platform_device mxc_uart_device1; -extern struct platform_device mxc_uart_device2; -extern struct platform_device mxc_uart_device3; -extern struct platform_device mxc_uart_device4; extern struct platform_device mxc_w1_master_device; -extern struct platform_device mxc_nand_device; -extern struct platform_device mxc_i2c_device0; -extern struct platform_device mxc_i2c_device1; -extern struct platform_device mxc_i2c_device2; extern struct platform_device mx3_ipu; extern struct platform_device mx3_fb; extern struct platform_device mx3_camera; @@ -20,9 +10,6 @@ extern struct platform_device mxc_otg_host; extern struct platform_device mxc_usbh1; extern struct platform_device mxc_usbh2; extern struct platform_device mxc_rnga_device; -extern struct platform_device mxc_spi_device0; -extern struct platform_device mxc_spi_device1; -extern struct platform_device mxc_spi_device2; extern struct platform_device imx_ssi_device0; extern struct platform_device imx_ssi_device1; extern struct platform_device imx_ssi_device1; diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c new file mode 100644 index 000000000000..1dc5004df866 --- /dev/null +++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c @@ -0,0 +1,263 @@ +/* + * Copyright (C) 2010 Eric Benard - eric@eukrea.com + * + * Based on pcm970-baseboard.c which is : + * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/types.h> +#include <linux/init.h> + +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/leds.h> +#include <linux/platform_device.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <video/platform_lcd.h> +#include <linux/i2c.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/imx-uart.h> +#include <mach/iomux-mx35.h> +#include <mach/ipu.h> +#include <mach/mx3fb.h> +#include <mach/audmux.h> +#include <mach/ssi.h> + +#include "devices-imx35.h" +#include "devices.h" + +static const struct fb_videomode fb_modedb[] = { + { + .name = "CMO_QVGA", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6500), + .left_margin = 68, + .right_margin = 20, + .upper_margin = 15, + .lower_margin = 4, + .hsync_len = 30, + .vsync_len = 3, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, +}; + +static struct ipu_platform_data mx3_ipu_data = { + .irq_base = MXC_IPU_IRQ_START, +}; + +static struct mx3fb_platform_data mx3fb_pdata = { + .dma_dev = &mx3_ipu.dev, + .name = "CMO_QVGA", + .mode = fb_modedb, + .num_modes = ARRAY_SIZE(fb_modedb), +}; + +static struct pad_desc eukrea_mbimxsd_pads[] = { + /* LCD */ + MX35_PAD_LD0__IPU_DISPB_DAT_0, + MX35_PAD_LD1__IPU_DISPB_DAT_1, + MX35_PAD_LD2__IPU_DISPB_DAT_2, + MX35_PAD_LD3__IPU_DISPB_DAT_3, + MX35_PAD_LD4__IPU_DISPB_DAT_4, + MX35_PAD_LD5__IPU_DISPB_DAT_5, + MX35_PAD_LD6__IPU_DISPB_DAT_6, + MX35_PAD_LD7__IPU_DISPB_DAT_7, + MX35_PAD_LD8__IPU_DISPB_DAT_8, + MX35_PAD_LD9__IPU_DISPB_DAT_9, + MX35_PAD_LD10__IPU_DISPB_DAT_10, + MX35_PAD_LD11__IPU_DISPB_DAT_11, + MX35_PAD_LD12__IPU_DISPB_DAT_12, + MX35_PAD_LD13__IPU_DISPB_DAT_13, + MX35_PAD_LD14__IPU_DISPB_DAT_14, + MX35_PAD_LD15__IPU_DISPB_DAT_15, + MX35_PAD_LD16__IPU_DISPB_DAT_16, + MX35_PAD_LD17__IPU_DISPB_DAT_17, + MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, + MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, + MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, + MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, + /* Backlight */ + MX35_PAD_CONTRAST__IPU_DISPB_CONTR, + /* LCD_PWR */ + MX35_PAD_D3_CLS__GPIO1_4, + /* LED */ + MX35_PAD_LD23__GPIO3_29, + /* SWITCH */ + MX35_PAD_LD19__GPIO3_25, + /* UART2 */ + MX35_PAD_CTS2__UART2_CTS, + MX35_PAD_RTS2__UART2_RTS, + MX35_PAD_TXD2__UART2_TXD_MUX, + MX35_PAD_RXD2__UART2_RXD_MUX, + /* I2S */ + MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, + MX35_PAD_STXD4__AUDMUX_AUD4_TXD, + MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, + MX35_PAD_SCK4__AUDMUX_AUD4_TXC, +}; + +#define GPIO_LED1 (2 * 32 + 29) +#define GPIO_SWITCH1 (2 * 32 + 25) +#define GPIO_LCDPWR (4) + +static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, + unsigned int power) +{ + if (power) + gpio_direction_output(GPIO_LCDPWR, 1); + else + gpio_direction_output(GPIO_LCDPWR, 0); +} + +static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = { + .set_power = eukrea_mbimxsd_lcd_power_set, +}; + +static struct platform_device eukrea_mbimxsd_lcd_powerdev = { + .name = "platform-lcd", + .dev.platform_data = &eukrea_mbimxsd_lcd_power_data, +}; + +static struct gpio_led eukrea_mbimxsd_leds[] = { + { + .name = "led1", + .default_trigger = "heartbeat", + .active_low = 1, + .gpio = GPIO_LED1, + }, +}; + +static struct gpio_led_platform_data eukrea_mbimxsd_led_info = { + .leds = eukrea_mbimxsd_leds, + .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds), +}; + +static struct platform_device eukrea_mbimxsd_leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &eukrea_mbimxsd_led_info, + }, +}; + +static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { + { + .gpio = GPIO_SWITCH1, + .code = BTN_0, + .desc = "BP1", + .active_low = 1, + .wakeup = 1, + }, +}; + +static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = { + .buttons = eukrea_mbimxsd_gpio_buttons, + .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), +}; + +static struct platform_device eukrea_mbimxsd_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &eukrea_mbimxsd_button_data, + } +}; + +static struct platform_device *platform_devices[] __initdata = { + &eukrea_mbimxsd_leds_gpio, + &eukrea_mbimxsd_button_device, + &eukrea_mbimxsd_lcd_powerdev, +}; + +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = { + { + I2C_BOARD_INFO("tlv320aic23", 0x1a), + }, +}; + +struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = { + .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, +}; + +/* + * system init for baseboard usage. Will be called by cpuimx35 init. + * + * Add platform devices present on this baseboard and init + * them from CPU side as far as required to use them later on + */ +void __init eukrea_mbimxsd_baseboard_init(void) +{ + if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads, + ARRAY_SIZE(eukrea_mbimxsd_pads))) + printk(KERN_ERR "error setting mbimxsd pads !\n"); + +#if defined(CONFIG_SND_SOC_EUKREA_TLV320) + /* SSI unit master I2S codec connected to SSI_AUD4 */ + mxc_audmux_v2_configure_port(0, + MXC_AUDMUX_V2_PTCR_SYN | + MXC_AUDMUX_V2_PTCR_TFSDIR | + MXC_AUDMUX_V2_PTCR_TFSEL(3) | + MXC_AUDMUX_V2_PTCR_TCLKDIR | + MXC_AUDMUX_V2_PTCR_TCSEL(3), + MXC_AUDMUX_V2_PDCR_RXDSEL(3) + ); + mxc_audmux_v2_configure_port(3, + MXC_AUDMUX_V2_PTCR_SYN, + MXC_AUDMUX_V2_PDCR_RXDSEL(0) + ); +#endif + + imx35_add_imx_uart1(&uart_pdata); + mxc_register_device(&mx3_ipu, &mx3_ipu_data); + mxc_register_device(&mx3_fb, &mx3fb_pdata); + + mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata); + + gpio_request(GPIO_LED1, "LED1"); + gpio_direction_output(GPIO_LED1, 1); + gpio_free(GPIO_LED1); + + gpio_request(GPIO_SWITCH1, "SWITCH1"); + gpio_direction_input(GPIO_SWITCH1); + gpio_free(GPIO_SWITCH1); + + gpio_request(GPIO_LCDPWR, "LCDPWR"); + gpio_direction_output(GPIO_LCDPWR, 1); + gpio_free(GPIO_SWITCH1); + + i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, + ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); + + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); +} diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c index 5f72ec91af2d..96aadcadb4ff 100644 --- a/arch/arm/mach-mx3/mach-armadillo5x0.c +++ b/arch/arm/mach-mx3/mach-armadillo5x0.c @@ -48,16 +48,14 @@ #include <asm/mach/map.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> -#include <mach/board-armadillo5x0.h> #include <mach/mmc.h> #include <mach/ipu.h> #include <mach/mx3fb.h> -#include <mach/mxc_nand.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> +#include "devices-imx31.h" #include "devices.h" #include "crm_regs.h" @@ -301,7 +299,8 @@ static struct platform_device armadillo5x0_button_device = { /* * NAND Flash */ -static struct mxc_nand_platform_data armadillo5x0_nand_flash_pdata = { +static const struct mxc_nand_platform_data +armadillo5x0_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; @@ -493,13 +492,12 @@ static struct platform_device armadillo5x0_smc911x_device = { }; /* UART device data */ -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; static struct platform_device *devices[] __initdata = { &armadillo5x0_smc911x_device, - &mxc_i2c_device1, &armadillo5x0_button_device, }; @@ -512,10 +510,11 @@ static void __init armadillo5x0_init(void) ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0"); platform_add_devices(devices, ARRAY_SIZE(devices)); + imx31_add_imx_i2c1(NULL); /* Register UART */ - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device1, &uart_pdata); + imx31_add_imx_uart0(&uart_pdata); + imx31_add_imx_uart1(&uart_pdata); /* SMSC9118 IRQ pin */ gpio_direction_input(MX31_PIN_GPIO1_0); @@ -532,7 +531,7 @@ static void __init armadillo5x0_init(void) &armadillo5x0_nor_flash_pdata); /* Register NAND Flash */ - mxc_register_device(&mxc_nand_device, &armadillo5x0_nand_flash_pdata); + imx31_add_mxc_nand(&armadillo5x0_nand_board_info); /* set NAND page size to 2k if not configured via boot mode pins */ __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR); diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c new file mode 100644 index 000000000000..63f970f340a2 --- /dev/null +++ b/arch/arm/mach-mx3/mach-cpuimx35.c @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2010 Eric Benard - eric@eukrea.com + * Copyright (C) 2009 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/types.h> +#include <linux/init.h> + +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/memory.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/i2c/tsc2007.h> +#include <linux/usb/otg.h> +#include <linux/usb/ulpi.h> +#include <linux/fsl_devices.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/mach/map.h> + +#include <mach/eukrea-baseboards.h> +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/iomux-mx35.h> +#include <mach/mxc_nand.h> +#include <mach/mxc_ehci.h> +#include <mach/ulpi.h> + +#include "devices-imx35.h" +#include "devices.h" + +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static const struct imxi2c_platform_data +eukrea_cpuimx35_i2c0_data __initconst = { + .bitrate = 50000, +}; + +#define TSC2007_IRQGPIO (2 * 32 + 2) +static int ts_get_pendown_state(void) +{ + int val = 0; + gpio_free(TSC2007_IRQGPIO); + gpio_request(TSC2007_IRQGPIO, NULL); + gpio_direction_input(TSC2007_IRQGPIO); + + val = gpio_get_value(TSC2007_IRQGPIO); + + gpio_free(TSC2007_IRQGPIO); + gpio_request(TSC2007_IRQGPIO, NULL); + + return val ? 0 : 1; +} + +static int ts_init(void) +{ + gpio_request(TSC2007_IRQGPIO, NULL); + return 0; +} + +static struct tsc2007_platform_data tsc2007_info = { + .model = 2007, + .x_plate_ohms = 180, + .get_pendown_state = ts_get_pendown_state, + .init_platform_hw = ts_init, +}; + +static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { + { + I2C_BOARD_INFO("pcf8563", 0x51), + }, { + I2C_BOARD_INFO("tsc2007", 0x48), + .type = "tsc2007", + .platform_data = &tsc2007_info, + .irq = gpio_to_irq(TSC2007_IRQGPIO), + }, +}; + +static struct platform_device *devices[] __initdata = { + &mxc_fec_device, + &imx_wdt_device0, +}; + +static struct pad_desc eukrea_cpuimx35_pads[] = { + /* UART1 */ + MX35_PAD_CTS1__UART1_CTS, + MX35_PAD_RTS1__UART1_RTS, + MX35_PAD_TXD1__UART1_TXD_MUX, + MX35_PAD_RXD1__UART1_RXD_MUX, + /* FEC */ + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, + MX35_PAD_FEC_RX_DV__FEC_RX_DV, + MX35_PAD_FEC_COL__FEC_COL, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_TX_EN__FEC_TX_EN, + MX35_PAD_FEC_MDC__FEC_MDC, + MX35_PAD_FEC_MDIO__FEC_MDIO, + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, + MX35_PAD_FEC_CRS__FEC_CRS, + MX35_PAD_FEC_RDATA1__FEC_RDATA_1, + MX35_PAD_FEC_TDATA1__FEC_TDATA_1, + MX35_PAD_FEC_RDATA2__FEC_RDATA_2, + MX35_PAD_FEC_TDATA2__FEC_TDATA_2, + MX35_PAD_FEC_RDATA3__FEC_RDATA_3, + MX35_PAD_FEC_TDATA3__FEC_TDATA_3, + /* I2C1 */ + MX35_PAD_I2C1_CLK__I2C1_SCL, + MX35_PAD_I2C1_DAT__I2C1_SDA, + /* TSC2007 IRQ */ + MX35_PAD_ATA_DA2__GPIO3_2, +}; + +static const struct mxc_nand_platform_data +eukrea_cpuimx35_nand_board_info __initconst = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static struct mxc_usbh_platform_data otg_pdata = { + .portsc = MXC_EHCI_MODE_UTMI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static struct mxc_usbh_platform_data usbh1_pdata = { + .portsc = MXC_EHCI_MODE_SERIAL, + .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | + MXC_EHCI_IPPUE_DOWN, +}; + +static struct fsl_usb2_platform_data otg_device_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI, +}; + +static int otg_mode_host; + +static int __init eukrea_cpuimx35_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", eukrea_cpuimx35_otg_mode); + +/* + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads, + ARRAY_SIZE(eukrea_cpuimx35_pads)); + + platform_add_devices(devices, ARRAY_SIZE(devices)); + + imx35_add_imx_uart0(&uart_pdata); + imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info); + + i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices, + ARRAY_SIZE(eukrea_cpuimx35_i2c_devices)); + imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data); + +#if defined(CONFIG_USB_ULPI) + if (otg_mode_host) { + otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_otg_host, &otg_pdata); + } + mxc_register_device(&mxc_usbh1, &usbh1_pdata); +#endif + if (!otg_mode_host) + mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + +#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD + eukrea_mbimxsd_baseboard_init(); +#endif +} + +static void __init eukrea_cpuimx35_timer_init(void) +{ + mx35_clocks_init(); +} + +struct sys_timer eukrea_cpuimx35_timer = { + .init = eukrea_cpuimx35_timer_init, +}; + +MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35") + /* Maintainer: Eukrea Electromatique */ + .phys_io = MX35_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX3x_PHYS_OFFSET + 0x100, + .map_io = mx35_map_io, + .init_irq = mx35_init_irq, + .init_machine = mxc_board_init, + .timer = &eukrea_cpuimx35_timer, +MACHINE_END diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c index f085d5d1a6de..5b23e416d6c7 100644 --- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c +++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c @@ -16,10 +16,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/gpio.h> @@ -37,13 +33,12 @@ #include <asm/mach/map.h> #include <asm/mach/time.h> -#include <mach/board-kzmarm11.h> #include <mach/clock.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/memory.h> +#include "devices-imx31.h" #include "devices.h" #define KZM_ARM11_IO_ADDRESS(x) ( \ @@ -51,6 +46,23 @@ IMX_IO_ADDRESS(x, MX31_CS5) ?: \ MX31_IO_ADDRESS(x)) +/* + * KZM-ARM11-01 Board Control Registers on FPGA + */ +#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000) +#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001) +#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002) +#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004) +#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008) +#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010) +#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020) +#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003) + +/* + * External UART for touch panel on FPGA + */ +#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050) + #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) /* * KZM-ARM11-01 has an external UART on FPGA @@ -173,15 +185,14 @@ static inline int kzm_init_smsc9118(void) #endif #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; static void __init kzm_init_imx_uart(void) { - mxc_register_device(&mxc_uart_device0, &uart_pdata); - - mxc_register_device(&mxc_uart_device1, &uart_pdata); + imx31_add_imx_uart0(&uart_pdata); + imx31_add_imx_uart1(&uart_pdata); } #else static inline void kzm_init_imx_uart(void) diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 58e57291b79d..6fe69e124d30 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/delay.h> @@ -22,7 +18,6 @@ #include <linux/clk.h> #include <linux/irq.h> #include <linux/gpio.h> -#include <linux/smsc911x.h> #include <linux/platform_device.h> #include <linux/mfd/mc13783.h> #include <linux/spi/spi.h> @@ -37,19 +32,47 @@ #include <asm/memory.h> #include <asm/mach/map.h> #include <mach/common.h> -#include <mach/board-mx31_3ds.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> -#include <mach/mxc_nand.h> -#include <mach/spi.h> +#include <mach/3ds_debugboard.h> + +#include "devices-imx31.h" #include "devices.h" -/*! - * @file mx31_3ds.c - * - * @brief This file contains the board-specific initialization routines. - * - * @ingroup System +/* Definitions for components on the Debug board */ + +/* Base address of CPLD controller on the Debug board */ +#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR) + +/* LAN9217 ethernet base address */ +#define LAN9217_BASE_ADDR MX3x_CS5_BASE_ADDR + +/* CPLD config and interrupt base address */ +#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000) + +/* status, interrupt */ +#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10) +#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38) +#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20) +/* magic word for debug CPLD */ +#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40) +#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48) +/* CPLD code version */ +#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50) +/* magic word for debug CPLD */ +#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58) + +/* CPLD IRQ line for external uart, external ethernet etc */ +#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) + +#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) +#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) + +#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0) + +#define MXC_MAX_EXP_IO_LINES 16 + +/* + * This file contains the board-specific initialization routines. */ static int mx31_3ds_pins[] = { @@ -145,7 +168,7 @@ static int spi1_internal_chipselect[] = { MXC_SPI_CS(2), }; -static struct spi_imx_master spi1_pdata = { +static const struct spi_imx_master spi1_pdata __initconst = { .chipselect = spi1_internal_chipselect, .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect), }; @@ -165,7 +188,8 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = { /* * NAND Flash */ -static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = { +static const struct mxc_nand_platform_data +mx31_3ds_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, #ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT @@ -182,8 +206,10 @@ static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = { #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) -static void mx31_3ds_usbotg_init(void) +static int mx31_3ds_usbotg_init(void) { + int err; + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); @@ -197,10 +223,25 @@ static void mx31_3ds_usbotg_init(void) mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); - gpio_request(USBOTG_RST_B, "otgusb-reset"); - gpio_direction_output(USBOTG_RST_B, 0); + err = gpio_request(USBOTG_RST_B, "otgusb-reset"); + if (err) { + pr_err("Failed to request the USB OTG reset gpio\n"); + return err; + } + + err = gpio_direction_output(USBOTG_RST_B, 0); + if (err) { + pr_err("Failed to drive the USB OTG reset gpio\n"); + goto usbotg_free_reset; + } + mdelay(1); gpio_set_value(USBOTG_RST_B, 1); + return 0; + +usbotg_free_reset: + gpio_free(USBOTG_RST_B); + return err; } static struct fsl_usb2_platform_data usbotg_pdata = { @@ -208,178 +249,16 @@ static struct fsl_usb2_platform_data usbotg_pdata = { .phy_mode = FSL_USB2_PHY_ULPI, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; /* - * Support for the SMSC9217 on the Debug board. - */ - -static struct smsc911x_platform_config smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct resource smsc911x_resources[] = { - { - .start = LAN9217_BASE_ADDR, - .end = LAN9217_BASE_ADDR + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = EXPIO_INT_ENET, - .end = EXPIO_INT_ENET, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; - -/* - * Routines for the CPLD on the debug board. It contains a CPLD handling - * LEDs, switches, interrupts for Ethernet. - */ - -static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc) -{ - uint32_t imr_val; - uint32_t int_valid; - uint32_t expio_irq; - - imr_val = __raw_readw(CPLD_INT_MASK_REG); - int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val; - - expio_irq = MXC_EXP_IO_BASE; - for (; int_valid != 0; int_valid >>= 1, expio_irq++) { - if ((int_valid & 1) == 0) - continue; - generic_handle_irq(expio_irq); - } -} - -/* - * Disable an expio pin's interrupt by setting the bit in the imr. - * @param irq an expio virtual irq number - */ -static void expio_mask_irq(uint32_t irq) -{ - uint16_t reg; - uint32_t expio = MXC_IRQ_TO_EXPIO(irq); - - /* mask the interrupt */ - reg = __raw_readw(CPLD_INT_MASK_REG); - reg |= 1 << expio; - __raw_writew(reg, CPLD_INT_MASK_REG); -} - -/* - * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. - * @param irq an expanded io virtual irq number - */ -static void expio_ack_irq(uint32_t irq) -{ - uint32_t expio = MXC_IRQ_TO_EXPIO(irq); - - /* clear the interrupt status */ - __raw_writew(1 << expio, CPLD_INT_RESET_REG); - __raw_writew(0, CPLD_INT_RESET_REG); - /* mask the interrupt */ - expio_mask_irq(irq); -} - -/* - * Enable a expio pin's interrupt by clearing the bit in the imr. - * @param irq a expio virtual irq number - */ -static void expio_unmask_irq(uint32_t irq) -{ - uint16_t reg; - uint32_t expio = MXC_IRQ_TO_EXPIO(irq); - - /* unmask the interrupt */ - reg = __raw_readw(CPLD_INT_MASK_REG); - reg &= ~(1 << expio); - __raw_writew(reg, CPLD_INT_MASK_REG); -} - -static struct irq_chip expio_irq_chip = { - .ack = expio_ack_irq, - .mask = expio_mask_irq, - .unmask = expio_unmask_irq, -}; - -static int __init mx31_3ds_init_expio(void) -{ - int i; - int ret; - - /* Check if there's a debug board connected */ - if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) || - (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) || - (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) { - /* No Debug board found */ - return -ENODEV; - } - - pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n", - __raw_readw(CPLD_CODE_VER_REG)); - - /* - * Configure INT line as GPIO input - */ - ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq"); - if (ret) - pr_warning("could not get LAN irq gpio\n"); - else - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); - - /* Disable the interrupts and clear the status */ - __raw_writew(0, CPLD_INT_MASK_REG); - __raw_writew(0xFFFF, CPLD_INT_RESET_REG); - __raw_writew(0, CPLD_INT_RESET_REG); - __raw_writew(0x1F, CPLD_INT_MASK_REG); - for (i = MXC_EXP_IO_BASE; - i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); - i++) { - set_irq_chip(i, &expio_irq_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } - set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW); - set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler); - - return 0; -} - -/* - * This structure defines the MX31 memory map. - */ -static struct map_desc mx31_3ds_io_desc[] __initdata = { - { - .virtual = MX31_CS5_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR), - .length = MX31_CS5_SIZE, - .type = MT_DEVICE, - }, -}; - -/* * Set up static virtual mappings. */ static void __init mx31_3ds_map_io(void) { mx31_map_io(); - iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc)); } /*! @@ -390,10 +269,10 @@ static void __init mxc_board_init(void) mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), "mx31_3ds"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata); + imx31_add_imx_uart0(&uart_pdata); + imx31_add_mxc_nand(&mx31_3ds_nand_board_info); - mxc_register_device(&mxc_spi_device1, &spi1_pdata); + imx31_add_spi_imx0(&spi1_pdata); spi_register_board_info(mx31_3ds_spi_devs, ARRAY_SIZE(mx31_3ds_spi_devs)); @@ -402,8 +281,9 @@ static void __init mxc_board_init(void) mx31_3ds_usbotg_init(); mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata); - if (!mx31_3ds_init_expio()) - platform_device_register(&smsc911x_device); + if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT)) + printk(KERN_WARNING "Init of the debugboard failed, all " + "devices on the board are unusable.\n"); } static void __init mx31_3ds_timer_init(void) diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index b3d1a1895c20..94b3e7c42404 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/types.h> @@ -33,8 +29,6 @@ #include <asm/memory.h> #include <asm/mach/map.h> #include <mach/common.h> -#include <mach/board-mx31ads.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 @@ -43,14 +37,45 @@ #include <linux/mfd/wm8350/pmic.h> #endif +#include "devices-imx31.h" #include "devices.h" -/*! - * @file mx31ads.c - * - * @brief This file contains the board-specific initialization routines. - * - * @ingroup System +/* Base address of PBC controller */ +#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT +/* Offsets for the PBC Controller register */ + +/* PBC Board interrupt status register */ +#define PBC_INTSTATUS 0x000016 + +/* PBC Board interrupt current status register */ +#define PBC_INTCURR_STATUS 0x000018 + +/* PBC Interrupt mask register set address */ +#define PBC_INTMASK_SET 0x00001A + +/* PBC Interrupt mask register clear address */ +#define PBC_INTMASK_CLEAR 0x00001C + +/* External UART A */ +#define PBC_SC16C652_UARTA 0x010000 + +/* External UART B */ +#define PBC_SC16C652_UARTB 0x010010 + +#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) +#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS) +#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) +#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) + +#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) +#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) + +#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) +#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11) + +#define MXC_MAX_EXP_IO_LINES 16 +/* + * This file contains the board-specific initialization routines. */ #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) @@ -98,7 +123,7 @@ static inline int mxc_init_extuart(void) #endif #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -112,7 +137,7 @@ static unsigned int uart_pins[] = { static inline void mxc_init_imx_uart(void) { mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx31_add_imx_uart0(&uart_pdata); } #else /* !SERIAL_IMX */ static inline void mxc_init_imx_uart(void) @@ -475,7 +500,7 @@ static void mxc_init_i2c(void) mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)); mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)); - mxc_register_device(&mxc_i2c_device1, NULL); + imx31_add_imx_i2c1(NULL); } #else static void mxc_init_i2c(void) diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index b2c7f512070f..8f66f65e80e2 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -18,10 +18,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/types.h> @@ -46,10 +42,10 @@ #include <mach/common.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31lilly.h> -#include <mach/spi.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> +#include "devices-imx31.h" #include "devices.h" /* @@ -269,12 +265,12 @@ static int spi_internal_chipselect[] = { MXC_SPI_CS(2), }; -static struct spi_imx_master spi0_pdata = { +static const struct spi_imx_master spi0_pdata __initconst = { .chipselect = spi_internal_chipselect, .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), }; -static struct spi_imx_master spi1_pdata = { +static const struct spi_imx_master spi1_pdata __initconst = { .chipselect = spi_internal_chipselect, .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), }; @@ -289,6 +285,7 @@ static struct spi_board_info mc13783_dev __initdata = { .bus_num = 1, .chip_select = 0, .platform_data = &mc13783_pdata, + .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), }; static struct platform_device *devices[] __initdata = { @@ -331,8 +328,8 @@ static void __init mx31lilly_board_init(void) mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1"); mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2"); - mxc_register_device(&mxc_spi_device0, &spi0_pdata); - mxc_register_device(&mxc_spi_device1, &spi1_pdata); + imx31_add_spi_imx0(&spi0_pdata); + imx31_add_spi_imx1(&spi1_pdata); spi_register_board_info(&mc13783_dev, 1); platform_add_devices(devices, ARRAY_SIZE(devices)); diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c index 2b6d11400877..da236c497d2a 100644 --- a/arch/arm/mach-mx3/mach-mx31lite.c +++ b/arch/arm/mach-mx3/mach-mx31lite.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/types.h> @@ -42,14 +38,12 @@ #include <mach/hardware.h> #include <mach/common.h> #include <mach/board-mx31lite.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/irqs.h> -#include <mach/mxc_nand.h> -#include <mach/spi.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> +#include "devices-imx31.h" #include "devices.h" /* @@ -69,7 +63,8 @@ static unsigned int mx31lite_pins[] = { MX31_PIN_CSPI2_SS2__SS2, }; -static struct mxc_nand_platform_data mx31lite_nand_board_info = { +static const struct mxc_nand_platform_data +mx31lite_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; @@ -112,7 +107,7 @@ static int spi_internal_chipselect[] = { MXC_SPI_CS(0), }; -static struct spi_imx_master spi1_pdata = { +static const struct spi_imx_master spi1_pdata __initconst = { .chipselect = spi_internal_chipselect, .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), }; @@ -253,9 +248,9 @@ static void __init mxc_board_init(void) /* NOR and NAND flash */ platform_device_register(&physmap_flash_device); - mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info); + imx31_add_mxc_nand(&mx31lite_nand_board_info); - mxc_register_device(&mxc_spi_device1, &spi1_pdata); + imx31_add_spi_imx1(&spi1_pdata); spi_register_board_info(&mc13783_spi_dev, 1); #if defined(CONFIG_USB_ULPI) diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index 62b5e40165df..67776bc61c33 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/delay.h> @@ -42,16 +38,15 @@ #include <mach/board-mx31moboard.h> #include <mach/common.h> #include <mach/hardware.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/ipu.h> -#include <mach/i2c.h> #include <mach/mmc.h> #include <mach/mxc_ehci.h> #include <mach/mx3_camera.h> #include <mach/spi.h> #include <mach/ulpi.h> +#include "devices-imx31.h" #include "devices.h" static unsigned int moboard_pins[] = { @@ -130,24 +125,36 @@ static struct platform_device mx31moboard_flash = { static int moboard_uart0_init(struct platform_device *pdev) { - gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack"); - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0); - return 0; + int ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack"); + if (ret) + return ret; + + ret = gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0); + if (ret) + gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1)); + + return ret; +} + +static void moboard_uart0_exit(struct platform_device *pdev) +{ + gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1)); } -static struct imxuart_platform_data uart0_pdata = { +static const struct imxuart_platform_data uart0_pdata __initconst = { .init = moboard_uart0_init, + .exit = moboard_uart0_exit, }; -static struct imxuart_platform_data uart4_pdata = { +static const struct imxuart_platform_data uart4_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -static struct imxi2c_platform_data moboard_i2c0_pdata = { +static const struct imxi2c_platform_data moboard_i2c0_data __initconst = { .bitrate = 400000, }; -static struct imxi2c_platform_data moboard_i2c1_pdata = { +static const struct imxi2c_platform_data moboard_i2c1_data __initconst = { .bitrate = 100000, }; @@ -156,7 +163,7 @@ static int moboard_spi1_cs[] = { MXC_SPI_CS(2), }; -static struct spi_imx_master moboard_spi1_master = { +static const struct spi_imx_master moboard_spi1_pdata __initconst = { .chipselect = moboard_spi1_cs, .num_chipselect = ARRAY_SIZE(moboard_spi1_cs), }; @@ -286,7 +293,7 @@ static int moboard_spi2_cs[] = { MXC_SPI_CS(1), }; -static struct spi_imx_master moboard_spi2_master = { +static const struct spi_imx_master moboard_spi2_pdata __initconst = { .chipselect = moboard_spi2_cs, .num_chipselect = ARRAY_SIZE(moboard_spi2_cs), }; @@ -499,15 +506,14 @@ static void __init mxc_board_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); - mxc_register_device(&mxc_uart_device0, &uart0_pdata); - - mxc_register_device(&mxc_uart_device4, &uart4_pdata); + imx31_add_imx_uart0(&uart0_pdata); + imx31_add_imx_uart4(&uart4_pdata); - mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata); - mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata); + imx31_add_imx_i2c0(&moboard_i2c0_data); + imx31_add_imx_i2c1(&moboard_i2c1_data); - mxc_register_device(&mxc_spi_device1, &moboard_spi1_master); - mxc_register_device(&mxc_spi_device2, &moboard_spi2_master); + imx31_add_spi_imx1(&moboard_spi1_pdata); + imx31_add_spi_imx2(&moboard_spi2_pdata); gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq"); gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); diff --git a/arch/arm/mach-mx3/mach-mx35pdk.c b/arch/arm/mach-mx3/mach-mx35_3ds.c index bcac84d4dca4..1c30d7212f17 100644 --- a/arch/arm/mach-mx3/mach-mx35pdk.c +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -12,10 +12,12 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * This machine is known as: + * - i.MX35 3-Stack Development System + * - i.MX35 Platform Development Kit (i.MX35 PDK) */ #include <linux/types.h> @@ -32,12 +34,12 @@ #include <mach/hardware.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx35.h> +#include "devices-imx35.h" #include "devices.h" -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -90,7 +92,7 @@ static void __init mxc_board_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx35_add_imx_uart0(&uart_pdata); mxc_register_device(&mxc_otg_udc_device, &usb_pdata); } diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index cce410662383..8a292dd1a714 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/types.h> @@ -43,20 +39,17 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/mach/map.h> -#include <mach/board-pcm037.h> #include <mach/common.h> #include <mach/hardware.h> -#include <mach/i2c.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/ipu.h> #include <mach/mmc.h> #include <mach/mx3_camera.h> #include <mach/mx3fb.h> -#include <mach/mxc_nand.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> +#include "devices-imx31.h" #include "devices.h" #include "pcm037.h" @@ -225,7 +218,7 @@ static struct platform_device pcm037_flash = { .num_resources = 1, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -279,16 +272,17 @@ static struct platform_device pcm037_sram_device = { .resource = &pcm038_sram_resource, }; -static struct mxc_nand_platform_data pcm037_nand_board_info = { +static const struct mxc_nand_platform_data +pcm037_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; -static struct imxi2c_platform_data pcm037_i2c_1_data = { +static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = { .bitrate = 100000, }; -static struct imxi2c_platform_data pcm037_i2c_2_data = { +static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = { .bitrate = 20000, }; @@ -545,6 +539,7 @@ static struct platform_device pcm970_sja1000 = { .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), }; +#if defined(CONFIG_USB_ULPI) static struct mxc_usbh_platform_data otg_pdata = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, @@ -554,6 +549,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; +#endif static struct fsl_usb2_platform_data otg_device_pdata = { .operating_mode = FSL_USB2_DR_DEVICE, @@ -581,7 +577,6 @@ __setup("otg_mode=", pcm037_otg_mode); static void __init mxc_board_init(void) { int ret; - u32 tmp; mxc_iomux_set_gpr(MUX_PGP_UH2, 1); @@ -614,9 +609,10 @@ static void __init mxc_board_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device1, &uart_pdata); - mxc_register_device(&mxc_uart_device2, &uart_pdata); + imx31_add_imx_uart0(&uart_pdata); + /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */ + imx31_add_imx_uart1(&uart_pdata); + imx31_add_imx_uart2(&uart_pdata); mxc_register_device(&mxc_w1_master_device, NULL); @@ -634,10 +630,10 @@ static void __init mxc_board_init(void) i2c_register_board_info(1, pcm037_i2c_devices, ARRAY_SIZE(pcm037_i2c_devices)); - mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data); - mxc_register_device(&mxc_i2c_device2, &pcm037_i2c_2_data); + imx31_add_imx_i2c1(&pcm037_i2c1_data); + imx31_add_imx_i2c2(&pcm037_i2c2_data); - mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); + imx31_add_mxc_nand(&pcm037_nand_board_info); mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_fb, &mx3fb_pdata); diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c index 8d386000fc40..c8b98218efee 100644 --- a/arch/arm/mach-mx3/mach-pcm037_eet.c +++ b/arch/arm/mach-mx3/mach-pcm037_eet.c @@ -13,9 +13,6 @@ #include <linux/spi/spi.h> #include <mach/common.h> -#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) -#include <mach/spi.h> -#endif #include <mach/iomux-mx3.h> #include <asm/mach-types.h> @@ -64,7 +61,7 @@ static struct spi_board_info pcm037_spi_dev[] = { #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)}; -struct spi_imx_master pcm037_spi1_master = { +static const struct spi_imx_master pcm037_spi1_pdata __initconst = { .chipselect = pcm037_spi1_cs, .num_chipselect = ARRAY_SIZE(pcm037_spi1_cs), }; @@ -184,7 +181,7 @@ static int eet_init_devices(void) /* SPI */ spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev)); #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) - mxc_register_device(&mxc_spi_device0, &pcm037_spi1_master); + imx35_add_spi_imx0(&pcm037_spi1_pdata); #endif platform_device_register(&pcm037_gpio_keys_device); diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index 78d9185a9d4b..47f5311b301a 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/types.h> @@ -40,19 +36,15 @@ #include <mach/hardware.h> #include <mach/common.h> -#include <mach/imx-uart.h> -#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE -#include <mach/i2c.h> -#endif #include <mach/iomux-mx35.h> #include <mach/ipu.h> #include <mach/mx3fb.h> -#include <mach/mxc_nand.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include <mach/audmux.h> #include <mach/ssi.h> +#include "devices-imx35.h" #include "devices.h" static const struct fb_videomode fb_modedb[] = { @@ -122,12 +114,12 @@ static struct platform_device pcm043_flash = { .num_resources = 1, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE -static struct imxi2c_platform_data pcm043_i2c_1_data = { +static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = { .bitrate = 50000, }; @@ -222,6 +214,9 @@ static struct pad_desc pcm043_pads[] = { MX35_PAD_STXD4__AUDMUX_AUD4_TXD, MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, MX35_PAD_SCK4__AUDMUX_AUD4_TXC, + /* CAN2 */ + MX35_PAD_TX5_RX0__CAN2_TXCAN, + MX35_PAD_TX4_RX1__CAN2_RXCAN, }; #define AC97_GPIO_TXFS (1 * 32 + 31) @@ -304,11 +299,13 @@ static struct imx_ssi_platform_data pcm043_ssi_pdata = { .flags = IMX_SSI_USE_AC97, }; -static struct mxc_nand_platform_data pcm037_nand_board_info = { +static const struct mxc_nand_platform_data +pcm037_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; +#if defined(CONFIG_USB_ULPI) static struct mxc_usbh_platform_data otg_pdata = { .portsc = MXC_EHCI_MODE_UTMI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, @@ -319,6 +316,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = { .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN, }; +#endif static struct fsl_usb2_platform_data otg_device_pdata = { .operating_mode = FSL_USB2_DR_DEVICE, @@ -361,17 +359,17 @@ static void __init mxc_board_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); + imx35_add_imx_uart0(&uart_pdata); + imx35_add_mxc_nand(&pcm037_nand_board_info); mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata); - mxc_register_device(&mxc_uart_device1, &uart_pdata); + imx35_add_imx_uart1(&uart_pdata); #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE i2c_register_board_info(0, pcm043_i2c_devices, ARRAY_SIZE(pcm043_i2c_devices)); - mxc_register_device(&mxc_i2c_device0, &pcm043_i2c_1_data); + imx35_add_imx_i2c0(&pcm043_i2c0_data); #endif mxc_register_device(&mx3_ipu, &mx3_ipu_data); @@ -390,6 +388,7 @@ static void __init mxc_board_init(void) if (!otg_mode_host) mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + imx35_add_flexcan1(NULL); } static void __init pcm043_timer_init(void) diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c index e5b5b8323a17..d44ac70222a5 100644 --- a/arch/arm/mach-mx3/mach-qong.c +++ b/arch/arm/mach-mx3/mach-qong.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/types.h> @@ -34,9 +30,9 @@ #include <mach/common.h> #include <asm/page.h> #include <asm/setup.h> -#include <mach/board-qong.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> + +#include "devices-imx31.h" #include "devices.h" /* FPGA defines */ @@ -62,7 +58,7 @@ * This file contains the board-specific initialization routines. */ -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -73,11 +69,11 @@ static int uart_pins[] = { MX31_PIN_RXD1__RXD1 }; -static inline void mxc_init_imx_uart(void) +static inline void __init mxc_init_imx_uart(void) { mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx31_add_imx_uart0(&uart_pdata); } static struct resource dnet_resources[] = { @@ -116,7 +112,7 @@ static struct physmap_flash_data qong_flash_data = { static struct resource qong_flash_resource = { .start = MX31_CS0_BASE_ADDR, - .end = MX31_CS0_BASE_ADDR + QONG_NOR_SIZE - 1, + .end = MX31_CS0_BASE_ADDR + SZ_128M - 1, .flags = IORESOURCE_MEM, }; diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c index 6858a4f9806c..20e48c0195c4 100644 --- a/arch/arm/mach-mx3/mm.c +++ b/arch/arm/mach-mx3/mm.c @@ -14,10 +14,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/mm.h> @@ -97,9 +93,12 @@ void __init mx35_map_io(void) } #endif +int imx3x_register_gpios(void); + void __init mx31_init_irq(void) { mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); + imx3x_register_gpios(); } void __init mx35_init_irq(void) diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c index 7aebd74a12e8..827fd3c80201 100644 --- a/arch/arm/mach-mx3/mx31lilly-db.c +++ b/arch/arm/mach-mx3/mx31lilly-db.c @@ -18,10 +18,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/kernel.h> @@ -36,13 +32,13 @@ #include <mach/hardware.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31lilly.h> #include <mach/mmc.h> #include <mach/mx3fb.h> #include <mach/ipu.h> +#include "devices-imx31.h" #include "devices.h" /* @@ -96,7 +92,7 @@ static unsigned int lilly_db_board_pins[] __initdata = { }; /* UART */ -static struct imxuart_platform_data uart_pdata __initdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -217,9 +213,9 @@ void __init mx31lilly_db_init(void) mxc_iomux_setup_multiple_pins(lilly_db_board_pins, ARRAY_SIZE(lilly_db_board_pins), "development board pins"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device1, &uart_pdata); - mxc_register_device(&mxc_uart_device2, &uart_pdata); + imx31_add_imx_uart0(&uart_pdata); + imx31_add_imx_uart1(&uart_pdata); + imx31_add_imx_uart2(&uart_pdata); mxc_register_device(&mxcsdhc_device0, &mmc_pdata); mx31lilly_init_fb(); } diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c index 5f05bfbec380..7b0e74e275ba 100644 --- a/arch/arm/mach-mx3/mx31lite-db.c +++ b/arch/arm/mach-mx3/mx31lite-db.c @@ -18,10 +18,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/kernel.h> @@ -37,12 +33,11 @@ #include <mach/hardware.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31lite.h> #include <mach/mmc.h> -#include <mach/spi.h> +#include "devices-imx31.h" #include "devices.h" /* @@ -76,7 +71,7 @@ static unsigned int litekit_db_board_pins[] __initdata = { }; /* UART */ -static struct imxuart_platform_data uart_pdata __initdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -161,7 +156,7 @@ static int spi_internal_chipselect[] = { MXC_SPI_CS(2), }; -static struct spi_imx_master spi0_pdata = { +static const struct spi_imx_master spi0_pdata __initconst = { .chipselect = spi_internal_chipselect, .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), }; @@ -201,9 +196,9 @@ void __init mx31lite_db_init(void) mxc_iomux_setup_multiple_pins(litekit_db_board_pins, ARRAY_SIZE(litekit_db_board_pins), "development board pins"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx31_add_imx_uart0(&uart_pdata); mxc_register_device(&mxcsdhc_device0, &mmc_pdata); - mxc_register_device(&mxc_spi_device0, &spi0_pdata); + imx31_add_spi_imx0(&spi0_pdata); platform_device_register(&litekit_led_device); mxc_register_device(&imx_wdt_device0, NULL); mxc_register_device(&imx_rtc_device0, NULL); diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c index 582299cb2c08..fc395a7a8599 100644 --- a/arch/arm/mach-mx3/mx31moboard-devboard.c +++ b/arch/arm/mach-mx3/mx31moboard-devboard.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/gpio.h> @@ -27,13 +23,13 @@ #include <linux/usb/otg.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/hardware.h> #include <mach/mmc.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> +#include "devices-imx31.h" #include "devices.h" static unsigned int devboard_pins[] = { @@ -56,7 +52,7 @@ static unsigned int devboard_pins[] = { MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -230,7 +226,7 @@ void __init mx31moboard_devboard_init(void) mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins), "devboard"); - mxc_register_device(&mxc_uart_device1, &uart_pdata); + imx31_add_imx_uart1(&uart_pdata); mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index 4930f8c27e66..0551eb39d97e 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/delay.h> diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c index 293eea6d9d97..40c3e7564cb6 100644 --- a/arch/arm/mach-mx3/mx31moboard-smartbot.c +++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/delay.h> @@ -30,7 +26,6 @@ #include <mach/common.h> #include <mach/hardware.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31moboard.h> #include <mach/mxc_ehci.h> @@ -38,6 +33,7 @@ #include <media/soc_camera.h> +#include "devices-imx31.h" #include "devices.h" static unsigned int smartbot_pins[] = { @@ -59,7 +55,7 @@ static unsigned int smartbot_pins[] = { MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -183,8 +179,7 @@ void __init mx31moboard_smartbot_init(int board) mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins), "smartbot"); - mxc_register_device(&mxc_uart_device1, &uart_pdata); - + imx31_add_imx_uart1(&uart_pdata); switch (board) { case MX31SMARTBOT: diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 1576d51e676c..0848db5dd364 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -15,4 +15,31 @@ config MACH_MX51_BABBAGE u-boot. This includes specific configurations for the board and its peripherals. +config MACH_MX51_3DS + bool "Support MX51PDK (3DS)" + select MXC_DEBUG_BOARD + help + Include support for MX51PDK (3DS) platform. This includes specific + configurations for the board and its peripherals. + +config MACH_EUKREA_CPUIMX51 + bool "Support Eukrea CPUIMX51 module" + help + Include support for Eukrea CPUIMX51 platform. This includes + specific configurations for the module and its peripherals. + +choice + prompt "Baseboard" + depends on MACH_EUKREA_CPUIMX51 + default MACH_EUKREA_MBIMX51_BASEBOARD + +config MACH_EUKREA_MBIMX51_BASEBOARD + prompt "Eukrea MBIMX51 development board" + bool + help + This adds board specific devices that can be found on Eukrea's + MBIMX51 evaluation board. + +endchoice + endif diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index bf23f869ef51..86c66e7f52f3 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -6,4 +6,6 @@ obj-y := cpu.o mm.o clock-mx51.o devices.o obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o - +obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o +obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o +obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c new file mode 100644 index 000000000000..623607a20f57 --- /dev/null +++ b/arch/arm/mach-mx5/board-cpuimx51.c @@ -0,0 +1,293 @@ +/* + * + * Copyright (C) 2010 Eric Bénard <eric@eukrea.com> + * + * based on board-mx51_babbage.c which is + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/fsl_devices.h> + +#include <mach/eukrea-baseboards.h> +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/imx-uart.h> +#include <mach/iomux-mx51.h> +#include <mach/i2c.h> +#include <mach/mxc_ehci.h> + +#include <asm/irq.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include "devices.h" + +#define CPUIMX51_USBH1_STP (0*32 + 27) +#define CPUIMX51_QUARTA_GPIO (2*32 + 28) +#define CPUIMX51_QUARTB_GPIO (2*32 + 25) +#define CPUIMX51_QUARTC_GPIO (2*32 + 26) +#define CPUIMX51_QUARTD_GPIO (2*32 + 27) +#define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO) +#define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO) +#define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO) +#define CPUIMX51_QUARTD_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO) +#define CPUIMX51_QUART_XTAL 14745600 +#define CPUIMX51_QUART_REGSHIFT 17 + +/* USB_CTRL_1 */ +#define MX51_USB_CTRL_1_OFFSET 0x10 +#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) + +#define MX51_USB_PLLDIV_12_MHZ 0x00 +#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 +#define MX51_USB_PLL_DIV_24_MHZ 0x02 + +#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) +static struct plat_serial8250_port serial_platform_data[] = { + { + .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000), + .irq = CPUIMX51_QUARTA_IRQ, + .irqflags = IRQF_TRIGGER_HIGH, + .uartclk = CPUIMX51_QUART_XTAL, + .regshift = CPUIMX51_QUART_REGSHIFT, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, + }, { + .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000), + .irq = CPUIMX51_QUARTB_IRQ, + .irqflags = IRQF_TRIGGER_HIGH, + .uartclk = CPUIMX51_QUART_XTAL, + .regshift = CPUIMX51_QUART_REGSHIFT, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, + }, { + .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000), + .irq = CPUIMX51_QUARTC_IRQ, + .irqflags = IRQF_TRIGGER_HIGH, + .uartclk = CPUIMX51_QUART_XTAL, + .regshift = CPUIMX51_QUART_REGSHIFT, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, + }, { + .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000), + .irq = CPUIMX51_QUARTD_IRQ, + .irqflags = IRQF_TRIGGER_HIGH, + .uartclk = CPUIMX51_QUART_XTAL, + .regshift = CPUIMX51_QUART_REGSHIFT, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, + }, { + } +}; + +static struct platform_device serial_device = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = serial_platform_data, + }, +}; +#endif + +static struct platform_device *devices[] __initdata = { + &mxc_fec_device, +#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) + &serial_device, +#endif +}; + +static struct pad_desc eukrea_cpuimx51_pads[] = { + /* UART1 */ + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, + + /* I2C2 */ + MX51_PAD_GPIO_1_2__I2C2_SCL, + MX51_PAD_GPIO_1_3__I2C2_SDA, + MX51_PAD_NANDF_D10__GPIO_3_30, + + /* QUART IRQ */ + MX51_PAD_NANDF_D15__GPIO_3_25, + MX51_PAD_NANDF_D14__GPIO_3_26, + MX51_PAD_NANDF_D13__GPIO_3_27, + MX51_PAD_NANDF_D12__GPIO_3_28, + + /* USB HOST1 */ + MX51_PAD_USBH1_CLK__USBH1_CLK, + MX51_PAD_USBH1_DIR__USBH1_DIR, + MX51_PAD_USBH1_NXT__USBH1_NXT, + MX51_PAD_USBH1_DATA0__USBH1_DATA0, + MX51_PAD_USBH1_DATA1__USBH1_DATA1, + MX51_PAD_USBH1_DATA2__USBH1_DATA2, + MX51_PAD_USBH1_DATA3__USBH1_DATA3, + MX51_PAD_USBH1_DATA4__USBH1_DATA4, + MX51_PAD_USBH1_DATA5__USBH1_DATA5, + MX51_PAD_USBH1_DATA6__USBH1_DATA6, + MX51_PAD_USBH1_DATA7__USBH1_DATA7, + MX51_PAD_USBH1_STP__USBH1_STP, +}; + +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct imxi2c_platform_data eukrea_cpuimx51_i2c_data = { + .bitrate = 100000, +}; + +static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = { + { + I2C_BOARD_INFO("pcf8563", 0x51), + }, +}; + +/* This function is board specific as the bit mask for the plldiv will also +be different for other Freescale SoCs, thus a common bitmask is not +possible and cannot get place in /plat-mxc/ehci.c.*/ +static int initialize_otg_port(struct platform_device *pdev) +{ + u32 v; + void __iomem *usb_base; + void __iomem *usbother_base; + + usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; + + /* Set the PHY clock to 19.2MHz */ + v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); + v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; + v |= MX51_USB_PLL_DIV_19_2_MHZ; + __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); + iounmap(usb_base); + return 0; +} + +static int initialize_usbh1_port(struct platform_device *pdev) +{ + u32 v; + void __iomem *usb_base; + void __iomem *usbother_base; + + usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; + + /* The clock for the USBH1 ULPI port will come externally from the PHY. */ + v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); + __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); + iounmap(usb_base); + return 0; +} + +static struct mxc_usbh_platform_data dr_utmi_config = { + .init = initialize_otg_port, + .portsc = MXC_EHCI_UTMI_16BIT, + .flags = MXC_EHCI_INTERNAL_PHY, +}; + +static struct fsl_usb2_platform_data usb_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, +}; + +static struct mxc_usbh_platform_data usbh1_config = { + .init = initialize_usbh1_port, + .portsc = MXC_EHCI_MODE_ULPI, + .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD), +}; + +static int otg_mode_host; + +static int __init eukrea_cpuimx51_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", eukrea_cpuimx51_otg_mode); + +/* + * Board specific initialization. + */ +static void __init eukrea_cpuimx51_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, + ARRAY_SIZE(eukrea_cpuimx51_pads)); + + mxc_register_device(&mxc_uart_device0, &uart_pdata); + gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq"); + gpio_direction_input(CPUIMX51_QUARTA_GPIO); + gpio_free(CPUIMX51_QUARTA_GPIO); + gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq"); + gpio_direction_input(CPUIMX51_QUARTB_GPIO); + gpio_free(CPUIMX51_QUARTB_GPIO); + gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq"); + gpio_direction_input(CPUIMX51_QUARTC_GPIO); + gpio_free(CPUIMX51_QUARTC_GPIO); + gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq"); + gpio_direction_input(CPUIMX51_QUARTD_GPIO); + gpio_free(CPUIMX51_QUARTD_GPIO); + + platform_add_devices(devices, ARRAY_SIZE(devices)); + + mxc_register_device(&mxc_i2c_device1, &eukrea_cpuimx51_i2c_data); + i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices, + ARRAY_SIZE(eukrea_cpuimx51_i2c_devices)); + + if (otg_mode_host) + mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); + else { + initialize_otg_port(NULL); + mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata); + } + mxc_register_device(&mxc_usbh1_device, &usbh1_config); + +#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD + eukrea_mbimx51_baseboard_init(); +#endif +} + +static void __init eukrea_cpuimx51_timer_init(void) +{ + mx51_clocks_init(32768, 24000000, 22579200, 0); +} + +static struct sys_timer mxc_timer = { + .init = eukrea_cpuimx51_timer_init, +}; + +MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module") + /* Maintainer: Eric Bénard <eric@eukrea.com> */ + .phys_io = MX51_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = mx51_map_io, + .init_irq = mx51_init_irq, + .init_machine = eukrea_cpuimx51_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c new file mode 100644 index 000000000000..f95c2fd94667 --- /dev/null +++ b/arch/arm/mach-mx5/board-mx51_3ds.c @@ -0,0 +1,164 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/input/matrix_keypad.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/iomux-mx51.h> +#include <mach/imx-uart.h> +#include <mach/3ds_debugboard.h> + +#include "devices.h" + +#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6) + +static struct pad_desc mx51_3ds_pads[] = { + /* UART1 */ + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, + + /* UART2 */ + MX51_PAD_UART2_RXD__UART2_RXD, + MX51_PAD_UART2_TXD__UART2_TXD, + MX51_PAD_EIM_D25__UART2_CTS, + MX51_PAD_EIM_D26__UART2_RTS, + + /* UART3 */ + MX51_PAD_UART3_RXD__UART3_RXD, + MX51_PAD_UART3_TXD__UART3_TXD, + MX51_PAD_EIM_D24__UART3_CTS, + MX51_PAD_EIM_D27__UART3_RTS, + + /* CPLD PARENT IRQ PIN */ + MX51_PAD_GPIO_1_6__GPIO_1_6, + + /* KPP */ + MX51_PAD_KEY_ROW0__KEY_ROW0, + MX51_PAD_KEY_ROW1__KEY_ROW1, + MX51_PAD_KEY_ROW2__KEY_ROW2, + MX51_PAD_KEY_ROW3__KEY_ROW3, + MX51_PAD_KEY_COL0__KEY_COL0, + MX51_PAD_KEY_COL1__KEY_COL1, + MX51_PAD_KEY_COL2__KEY_COL2, + MX51_PAD_KEY_COL3__KEY_COL3, + MX51_PAD_KEY_COL4__KEY_COL4, + MX51_PAD_KEY_COL5__KEY_COL5, +}; + +/* Serial ports */ +#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static inline void mxc_init_imx_uart(void) +{ + mxc_register_device(&mxc_uart_device0, &uart_pdata); + mxc_register_device(&mxc_uart_device1, &uart_pdata); + mxc_register_device(&mxc_uart_device2, &uart_pdata); +} +#else /* !SERIAL_IMX */ +static inline void mxc_init_imx_uart(void) +{ +} +#endif /* SERIAL_IMX */ + +#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE) +static int mx51_3ds_board_keymap[] = { + KEY(0, 0, KEY_1), + KEY(0, 1, KEY_2), + KEY(0, 2, KEY_3), + KEY(0, 3, KEY_F1), + KEY(0, 4, KEY_UP), + KEY(0, 5, KEY_F2), + + KEY(1, 0, KEY_4), + KEY(1, 1, KEY_5), + KEY(1, 2, KEY_6), + KEY(1, 3, KEY_LEFT), + KEY(1, 4, KEY_SELECT), + KEY(1, 5, KEY_RIGHT), + + KEY(2, 0, KEY_7), + KEY(2, 1, KEY_8), + KEY(2, 2, KEY_9), + KEY(2, 3, KEY_F3), + KEY(2, 4, KEY_DOWN), + KEY(2, 5, KEY_F4), + + KEY(3, 0, KEY_0), + KEY(3, 1, KEY_OK), + KEY(3, 2, KEY_ESC), + KEY(3, 3, KEY_ENTER), + KEY(3, 4, KEY_MENU), + KEY(3, 5, KEY_BACK) +}; + +static struct matrix_keymap_data mx51_3ds_map_data = { + .keymap = mx51_3ds_board_keymap, + .keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap), +}; + +static void mxc_init_keypad(void) +{ + mxc_register_device(&mxc_keypad_device, &mx51_3ds_map_data); +} +#else +static inline void mxc_init_keypad(void) +{ +} +#endif + +/* + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads, + ARRAY_SIZE(mx51_3ds_pads)); + mxc_init_imx_uart(); + + if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT)) + printk(KERN_WARNING "Init of the debugboard failed, all " + "devices on the board are unusable.\n"); + + mxc_init_keypad(); +} + +static void __init mx51_3ds_timer_init(void) +{ + mx51_clocks_init(32768, 24000000, 22579200, 0); +} + +static struct sys_timer mxc_timer = { + .init = mx51_3ds_timer_init, +}; + +MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .phys_io = MX51_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = mx51_map_io, + .init_irq = mx51_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index ed885f9d7b73..6e384d92e625 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -12,6 +12,7 @@ #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/i2c.h> #include <linux/gpio.h> #include <linux/delay.h> #include <linux/io.h> @@ -21,6 +22,7 @@ #include <mach/hardware.h> #include <mach/imx-uart.h> #include <mach/iomux-mx51.h> +#include <mach/i2c.h> #include <mach/mxc_ehci.h> #include <asm/irq.h> @@ -64,6 +66,18 @@ static struct pad_desc mx51babbage_pads[] = { MX51_PAD_EIM_D27__UART3_RTS, MX51_PAD_EIM_D24__UART3_CTS, + /* I2C1 */ + MX51_PAD_EIM_D16__I2C1_SDA, + MX51_PAD_EIM_D19__I2C1_SCL, + + /* I2C2 */ + MX51_PAD_KEY_COL4__I2C2_SCL, + MX51_PAD_KEY_COL5__I2C2_SDA, + + /* HSI2C */ + MX51_PAD_I2C1_CLK__HSI2C_CLK, + MX51_PAD_I2C1_DAT__HSI2C_DAT, + /* USB HOST1 */ MX51_PAD_USBH1_CLK__USBH1_CLK, MX51_PAD_USBH1_DIR__USBH1_DIR, @@ -78,7 +92,7 @@ static struct pad_desc mx51babbage_pads[] = { MX51_PAD_USBH1_DATA7__USBH1_DATA7, /* USB HUB reset line*/ - MX51_PAD_GPIO_1_7__GPIO1_7, + MX51_PAD_GPIO_1_7__GPIO_1_7, }; /* Serial ports */ @@ -99,6 +113,14 @@ static inline void mxc_init_imx_uart(void) } #endif /* SERIAL_IMX */ +static struct imxi2c_platform_data babbage_i2c_data = { + .bitrate = 100000, +}; + +static struct imxi2c_platform_data babbage_hsi2c_data = { + .bitrate = 400000, +}; + static int gpio_usbh1_active(void) { struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27; @@ -230,6 +252,10 @@ static void __init mxc_board_init(void) mxc_init_imx_uart(); platform_add_devices(devices, ARRAY_SIZE(devices)); + mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data); + mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data); + mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data); + if (otg_mode_host) mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); else { diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c index d9f612d3370e..6af69def357f 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51.c @@ -758,6 +758,10 @@ static struct clk gpt_32k_clk = { .parent = &ckil_clk, }; +static struct clk kpp_clk = { + .id = 0, +}; + #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ static struct clk name = { \ .id = i, \ @@ -798,6 +802,14 @@ DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, NULL, NULL, &ipg_clk, NULL); +/* I2C */ +DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET, + NULL, NULL, &ipg_clk, NULL); +DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET, + NULL, NULL, &ipg_clk, NULL); +DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET, + NULL, NULL, &ipg_clk, NULL); + /* FEC */ DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, NULL, NULL, &ipg_clk, NULL); @@ -815,12 +827,16 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) _REGISTER_CLOCK(NULL, "gpt", gpt_clk) _REGISTER_CLOCK("fec.0", NULL, fec_clk) + _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) + _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) + _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk) _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk) _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) + _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) }; static void clk_tree_init(void) diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index 7130449aacdc..1920ff4963b2 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -93,6 +93,64 @@ struct platform_device mxc_fec_device = { .resource = mxc_fec_resources, }; +static struct resource mxc_i2c0_resources[] = { + { + .start = MX51_I2C1_BASE_ADDR, + .end = MX51_I2C1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_I2C1, + .end = MX51_MXC_INT_I2C1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_i2c_device0 = { + .name = "imx-i2c", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_i2c0_resources), + .resource = mxc_i2c0_resources, +}; + +static struct resource mxc_i2c1_resources[] = { + { + .start = MX51_I2C2_BASE_ADDR, + .end = MX51_I2C2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_I2C2, + .end = MX51_MXC_INT_I2C2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_i2c_device1 = { + .name = "imx-i2c", + .id = 1, + .num_resources = ARRAY_SIZE(mxc_i2c1_resources), + .resource = mxc_i2c1_resources, +}; + +static struct resource mxc_hsi2c_resources[] = { + { + .start = MX51_HSI2C_DMA_BASE_ADDR, + .end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MX51_MXC_INT_HS_I2C, + .end = MX51_MXC_INT_HS_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_hsi2c_device = { + .name = "imx-i2c", + .id = 2, + .num_resources = ARRAY_SIZE(mxc_hsi2c_resources), + .resource = mxc_hsi2c_resources +}; + static u64 usb_dma_mask = DMA_BIT_MASK(32); static struct resource usbotg_resources[] = { @@ -168,34 +226,57 @@ struct platform_device mxc_wdt = { .resource = mxc_wdt_resources, }; +static struct resource mxc_kpp_resources[] = { + { + .start = MX51_MXC_INT_KPP, + .end = MX51_MXC_INT_KPP, + .flags = IORESOURCE_IRQ, + } , { + .start = MX51_KPP_BASE_ADDR, + .end = MX51_KPP_BASE_ADDR + 0x8 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mxc_keypad_device = { + .name = "imx-keypad", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_kpp_resources), + .resource = mxc_kpp_resources, +}; + static struct mxc_gpio_port mxc_gpio_ports[] = { { .chip.label = "gpio-0", .base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR), .irq = MX51_MXC_INT_GPIO1_LOW, + .irq_high = MX51_MXC_INT_GPIO1_HIGH, .virtual_irq_start = MXC_GPIO_IRQ_START }, { .chip.label = "gpio-1", .base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR), .irq = MX51_MXC_INT_GPIO2_LOW, + .irq_high = MX51_MXC_INT_GPIO2_HIGH, .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1 }, { .chip.label = "gpio-2", .base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR), .irq = MX51_MXC_INT_GPIO3_LOW, + .irq_high = MX51_MXC_INT_GPIO3_HIGH, .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2 }, { .chip.label = "gpio-3", .base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR), .irq = MX51_MXC_INT_GPIO4_LOW, + .irq_high = MX51_MXC_INT_GPIO4_HIGH, .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 }, }; -int __init mxc_register_gpios(void) +int __init imx51_register_gpios(void) { return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); } diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h index c879ae71cd5b..e509cfaad1d4 100644 --- a/arch/arm/mach-mx5/devices.h +++ b/arch/arm/mach-mx5/devices.h @@ -6,3 +6,7 @@ extern struct platform_device mxc_usbdr_host_device; extern struct platform_device mxc_usbh1_device; extern struct platform_device mxc_usbdr_udc_device; extern struct platform_device mxc_wdt; +extern struct platform_device mxc_i2c_device0; +extern struct platform_device mxc_i2c_device1; +extern struct platform_device mxc_hsi2c_device; +extern struct platform_device mxc_keypad_device; diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c new file mode 100644 index 000000000000..ffa93d1d6ef8 --- /dev/null +++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c @@ -0,0 +1,200 @@ +/* + * + * Copyright (C) 2010 Eric Bénard <eric@eukrea.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/io.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/fsl_devices.h> +#include <linux/i2c/tsc2007.h> +#include <linux/leds.h> +#include <linux/input/matrix_keypad.h> + +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/imx-uart.h> +#include <mach/iomux-mx51.h> + +#include <asm/mach/arch.h> + +#include "devices.h" + +#define MBIMX51_TSC2007_GPIO (2*32 + 30) +#define MBIMX51_TSC2007_IRQ (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO) +#define MBIMX51_LED0 (2*32 + 5) +#define MBIMX51_LED1 (2*32 + 6) +#define MBIMX51_LED2 (2*32 + 7) +#define MBIMX51_LED3 (2*32 + 8) + +static struct gpio_led mbimx51_leds[] = { + { + .name = "led0", + .default_trigger = "heartbeat", + .active_low = 1, + .gpio = MBIMX51_LED0, + }, + { + .name = "led1", + .default_trigger = "nand-disk", + .active_low = 1, + .gpio = MBIMX51_LED1, + }, + { + .name = "led2", + .default_trigger = "mmc0", + .active_low = 1, + .gpio = MBIMX51_LED2, + }, + { + .name = "led3", + .default_trigger = "default-on", + .active_low = 1, + .gpio = MBIMX51_LED3, + }, +}; + +static struct gpio_led_platform_data mbimx51_leds_info = { + .leds = mbimx51_leds, + .num_leds = ARRAY_SIZE(mbimx51_leds), +}; + +static struct platform_device mbimx51_leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &mbimx51_leds_info, + }, +}; + +static struct platform_device *devices[] __initdata = { + &mbimx51_leds_gpio, +}; + +static struct pad_desc mbimx51_pads[] = { + /* UART2 */ + MX51_PAD_UART2_RXD__UART2_RXD, + MX51_PAD_UART2_TXD__UART2_TXD, + + /* UART3 */ + MX51_PAD_UART3_RXD__UART3_RXD, + MX51_PAD_UART3_TXD__UART3_TXD, + MX51_PAD_KEY_COL4__UART3_RTS, + MX51_PAD_KEY_COL5__UART3_CTS, + + /* TSC2007 IRQ */ + MX51_PAD_NANDF_D10__GPIO_3_30, + + /* LEDS */ + MX51_PAD_DISPB2_SER_DIN__GPIO_3_5, + MX51_PAD_DISPB2_SER_DIO__GPIO_3_6, + MX51_PAD_DISPB2_SER_CLK__GPIO_3_7, + MX51_PAD_DISPB2_SER_RS__GPIO_3_8, + + /* KPP */ + MX51_PAD_KEY_ROW0__KEY_ROW0, + MX51_PAD_KEY_ROW1__KEY_ROW1, + MX51_PAD_KEY_ROW2__KEY_ROW2, + MX51_PAD_KEY_ROW3__KEY_ROW3, + MX51_PAD_KEY_COL0__KEY_COL0, + MX51_PAD_KEY_COL1__KEY_COL1, + MX51_PAD_KEY_COL2__KEY_COL2, + MX51_PAD_KEY_COL3__KEY_COL3, +}; + +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static int mbimx51_keymap[] = { + KEY(0, 0, KEY_1), + KEY(0, 1, KEY_2), + KEY(0, 2, KEY_3), + KEY(0, 3, KEY_UP), + + KEY(1, 0, KEY_4), + KEY(1, 1, KEY_5), + KEY(1, 2, KEY_6), + KEY(1, 3, KEY_LEFT), + + KEY(2, 0, KEY_7), + KEY(2, 1, KEY_8), + KEY(2, 2, KEY_9), + KEY(2, 3, KEY_RIGHT), + + KEY(3, 0, KEY_0), + KEY(3, 1, KEY_DOWN), + KEY(3, 2, KEY_ESC), + KEY(3, 3, KEY_ENTER), +}; + +static struct matrix_keymap_data mbimx51_map_data = { + .keymap = mbimx51_keymap, + .keymap_size = ARRAY_SIZE(mbimx51_keymap), +}; + +static int tsc2007_get_pendown_state(void) +{ + return !gpio_get_value(MBIMX51_TSC2007_GPIO); +} + +struct tsc2007_platform_data tsc2007_data = { + .model = 2007, + .x_plate_ohms = 180, + .get_pendown_state = tsc2007_get_pendown_state, +}; + +static struct i2c_board_info mbimx51_i2c_devices[] = { + { + I2C_BOARD_INFO("tsc2007", 0x48), + .irq = MBIMX51_TSC2007_IRQ, + .platform_data = &tsc2007_data, + }, +}; + +/* + * baseboard initialization. + */ +void __init eukrea_mbimx51_baseboard_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mbimx51_pads, + ARRAY_SIZE(mbimx51_pads)); + + mxc_register_device(&mxc_uart_device1, NULL); + mxc_register_device(&mxc_uart_device2, &uart_pdata); + + gpio_request(MBIMX51_LED0, "LED0"); + gpio_direction_output(MBIMX51_LED0, 1); + gpio_free(MBIMX51_LED0); + gpio_request(MBIMX51_LED1, "LED1"); + gpio_direction_output(MBIMX51_LED1, 1); + gpio_free(MBIMX51_LED1); + gpio_request(MBIMX51_LED2, "LED2"); + gpio_direction_output(MBIMX51_LED2, 1); + gpio_free(MBIMX51_LED2); + gpio_request(MBIMX51_LED3, "LED3"); + gpio_direction_output(MBIMX51_LED3, 1); + gpio_free(MBIMX51_LED3); + + platform_add_devices(devices, ARRAY_SIZE(devices)); + + mxc_register_device(&mxc_keypad_device, &mbimx51_map_data); + + gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq"); + gpio_direction_input(MBIMX51_TSC2007_GPIO); + set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); + i2c_register_board_info(1, mbimx51_i2c_devices, + ARRAY_SIZE(mbimx51_i2c_devices)); +} diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index b7677ef80cc4..bc3f30db8d9a 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -65,6 +65,8 @@ void __init mx51_map_io(void) iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); } +int imx51_register_gpios(void); + void __init mx51_init_irq(void) { unsigned long tzic_addr; @@ -80,4 +82,5 @@ void __init mx51_init_irq(void) panic("unable to map TZIC interrupt controller\n"); tzic_init_irq(tzic_virt); + imx51_register_gpios(); } diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h index ce4f59058189..b989baccd675 100644 --- a/arch/arm/mach-mxc91231/crm_regs.h +++ b/arch/arm/mach-mxc91231/crm_regs.h @@ -11,11 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * */ #ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c index 353bd977b393..027af4f0d18a 100644 --- a/arch/arm/mach-mxc91231/devices.c +++ b/arch/arm/mach-mxc91231/devices.c @@ -135,7 +135,7 @@ static struct mxc_gpio_port mxc_gpio_ports[] = { }, }; -int __init mxc_register_gpios(void) +int __init mxc91231_register_gpios(void) { return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); } diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c index 6becda3ff331..aeccfd755fee 100644 --- a/arch/arm/mach-mxc91231/mm.c +++ b/arch/arm/mach-mxc91231/mm.c @@ -15,11 +15,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * */ #include <linux/mm.h> @@ -88,7 +83,10 @@ void __init mxc91231_map_io(void) iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); } +int mxc91231_register_gpios(void); + void __init mxc91231_init_irq(void) { + mxc91231_register_gpios(); mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR)); } diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c index f035f4185274..89f793adf776 100644 --- a/arch/arm/mach-nomadik/clock.c +++ b/arch/arm/mach-nomadik/clock.c @@ -53,6 +53,10 @@ static struct clk clk_default; } static struct clk_lookup lookups[] = { + { + .con_id = "apb_pclk", + .clk = &clk_default, + }, CLK(&clk_24, "mtu0"), CLK(&clk_24, "mtu1"), CLK(&clk_48, "uart0"), diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index fdd1dd53fa9c..0a9d61d2d229 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -301,6 +301,7 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)") .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, .map_io = ams_delta_map_io, + .reserve = omap_reserve, .init_irq = ams_delta_init_irq, .init_machine = ams_delta_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 096f2ed102cb..059bac60b35a 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@ -378,6 +378,7 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample") .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, .map_io = omap_fsample_map_io, + .reserve = omap_reserve, .init_irq = omap_fsample_init_irq, .init_machine = omap_fsample_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index e1195a3467b8..7a65684d2a15 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c @@ -98,6 +98,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710") .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, .map_io = omap_generic_map_io, + .reserve = omap_reserve, .init_irq = omap_generic_init_irq, .init_machine = omap_generic_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index d1100e4f65ac..68b2beda8b99 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -467,6 +467,7 @@ MACHINE_START(OMAP_H2, "TI-H2") .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, .map_io = h2_map_io, + .reserve = omap_reserve, .init_irq = h2_init_irq, .init_machine = h2_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index a53ab8297d25..0b0825fe6751 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -437,6 +437,7 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board") .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, .map_io = h3_map_io, + .reserve = omap_reserve, .init_irq = h3_init_irq, .init_machine = h3_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 8e313b4b99a9..d70a4f0923f5 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -304,6 +304,7 @@ MACHINE_START(HERALD, "HTC Herald") .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, .map_io = htcherald_map_io, + .reserve = omap_reserve, .init_irq = htcherald_init_irq, .init_machine = htcherald_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 5d12fd35681b..91064b37859a 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -463,6 +463,7 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator") .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, .map_io = innovator_map_io, + .reserve = omap_reserve, .init_irq = innovator_init_irq, .init_machine = innovator_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 71e1a3fad0ea..8c28b10f3dae 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -400,6 +400,7 @@ MACHINE_START(NOKIA770, "Nokia 770") .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, .map_io = omap_nokia770_map_io, + .reserve = omap_reserve, .init_irq = omap_nokia770_init_irq, .init_machine = omap_nokia770_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 80d862001def..e2a72af30890 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -584,6 +584,7 @@ MACHINE_START(OMAP_OSK, "TI-OSK") .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, .map_io = osk_map_io, + .reserve = omap_reserve, .init_irq = osk_init_irq, .init_machine = osk_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 569b4c9085cd..61a2321b9732 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -373,6 +373,7 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E") .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, .map_io = omap_palmte_map_io, + .reserve = omap_reserve, .init_irq = omap_palmte_init_irq, .init_machine = omap_palmte_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 6ad49a2cc1a0..21c01c6afcc1 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -321,6 +321,7 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T") .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, .map_io = omap_palmtt_map_io, + .reserve = omap_reserve, .init_irq = omap_palmtt_init_irq, .init_machine = omap_palmtt_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index 6641de9257ef..f32492451533 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -338,10 +338,12 @@ omap_palmz71_map_io(void) } MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71") - .phys_io = 0xfff00000, - .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, - .boot_params = 0x10000100,.map_io = omap_palmz71_map_io, - .init_irq = omap_palmz71_init_irq, - .init_machine = omap_palmz71_init, - .timer = &omap_timer, + .phys_io = 0xfff00000, + .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, + .boot_params = 0x10000100, + .map_io = omap_palmz71_map_io, + .reserve = omap_reserve, + .init_irq = omap_palmz71_init_irq, + .init_machine = omap_palmz71_init, + .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index e854d5741c88..8b5ab1fcc405 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -339,6 +339,7 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2") .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, .map_io = omap_perseus2_map_io, + .reserve = omap_reserve, .init_irq = omap_perseus2_init_irq, .init_machine = omap_perseus2_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 2fb1e5f8e2ec..995566b862bb 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -423,7 +423,8 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1") .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, .map_io = omap_sx1_map_io, - .init_irq = omap_sx1_init_irq, + .reserve = omap_reserve, + .init_irq = omap_sx1_init_irq, .init_machine = omap_sx1_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 87b9436fe7c0..4c483dc1de5c 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -287,6 +287,7 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910") .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, .map_io = voiceblue_map_io, + .reserve = omap_reserve, .init_irq = voiceblue_init_irq, .init_machine = voiceblue_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index d9b8d82530ae..0ce3fec2d257 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c @@ -22,7 +22,6 @@ extern void omap_check_revision(void); extern void omap_sram_init(void); -extern void omapfb_reserve_sdram(void); /* * The machine specific code may provide the extra mapping besides the @@ -122,7 +121,6 @@ void __init omap1_map_common_io(void) #endif omap_sram_init(); - omapfb_reserve_sdram(); } /* diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index a11a575745e4..42f49f785c93 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -248,6 +248,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap_2430sdp_map_io, + .reserve = omap_reserve, .init_irq = omap_2430sdp_init_irq, .init_machine = omap_2430sdp_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index f474a80b8867..dd9c03171a19 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -815,6 +815,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap_3430sdp_map_io, + .reserve = omap_reserve, .init_irq = omap_3430sdp_init_irq, .init_machine = omap_3430sdp_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 504d2bd222fe..57290fb3fcd7 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -108,6 +108,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap_sdp_map_io, + .reserve = omap_reserve, .init_irq = omap_sdp_init_irq, .init_machine = omap_sdp_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index e4a5d66b83b8..4bb2c5d151ec 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -402,6 +402,7 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap_4430sdp_map_io, + .reserve = omap_reserve, .init_irq = omap_4430sdp_init_irq, .init_machine = omap_4430sdp_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index af383a876943..7da92defcde0 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -472,6 +472,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = am3517_evm_map_io, + .reserve = omap_reserve, .init_irq = am3517_evm_init_irq, .init_machine = am3517_evm_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index aa69fb999748..bd75642aee65 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -346,6 +346,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap_apollon_map_io, + .reserve = omap_reserve, .init_irq = omap_apollon_init_irq, .init_machine = omap_apollon_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index e679a2cc86c3..bc4c3f807068 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -837,6 +837,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35") .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = cm_t35_map_io, + .reserve = omap_reserve, .init_irq = cm_t35_init_irq, .init_machine = cm_t35_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 77022b588816..922b7464807f 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -825,6 +825,7 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = devkit8000_map_io, + .reserve = omap_reserve, .init_irq = devkit8000_init_irq, .init_machine = devkit8000_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 16cc06860670..9242902d3a43 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -59,6 +59,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap_generic_map_io, + .reserve = omap_reserve, .init_irq = omap_generic_init_irq, .init_machine = omap_generic_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 0665f2c8dc8e..16703fdb3515 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -378,6 +378,7 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap_h4_map_io, + .reserve = omap_reserve, .init_irq = omap_h4_init_irq, .init_machine = omap_h4_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index d55c57b761a9..759e39d1a702 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -543,6 +543,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = igep2_map_io, + .reserve = omap_reserve, .init_irq = igep2_init_irq, .init_machine = igep2_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index fefd7e6e9779..9cd2669113e4 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -417,6 +417,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap_ldp_map_io, + .reserve = omap_reserve, .init_irq = omap_ldp_init_irq, .init_machine = omap_ldp_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 3ccc34ebdcc7..2565ff08a221 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -667,6 +667,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = n8x0_map_io, + .reserve = omap_reserve, .init_irq = n8x0_init_irq, .init_machine = n8x0_init_machine, .timer = &omap_timer, @@ -677,6 +678,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = n8x0_map_io, + .reserve = omap_reserve, .init_irq = n8x0_init_irq, .init_machine = n8x0_init_machine, .timer = &omap_timer, @@ -687,6 +689,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = n8x0_map_io, + .reserve = omap_reserve, .init_irq = n8x0_init_irq, .init_machine = n8x0_init_machine, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 69b154cdc75d..0ab0c26db4dd 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -519,6 +519,7 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap3_beagle_map_io, + .reserve = omap_reserve, .init_irq = omap3_beagle_init_irq, .init_machine = omap3_beagle_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index b95261013812..a3d2e285e116 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -727,6 +727,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap3_evm_map_io, + .reserve = omap_reserve, .init_irq = omap3_evm_init_irq, .init_machine = omap3_evm_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index db06dc910ba7..c0f4f12eba54 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -601,6 +601,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap3pandora_map_io, + .reserve = omap_reserve, .init_irq = omap3pandora_init_irq, .init_machine = omap3pandora_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 2f5f8233dd5b..f05b867c5851 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -571,6 +571,7 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap3_touchbook_map_io, + .reserve = omap_reserve, .init_irq = omap3_touchbook_init_irq, .init_machine = omap3_touchbook_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 79ac41400c21..87acb2f198ec 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -495,6 +495,7 @@ MACHINE_START(OVERO, "Gumstix Overo") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = overo_map_io, + .reserve = omap_reserve, .init_irq = overo_init_irq, .init_machine = overo_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 1b86b5bb87a2..3bd956f9e19f 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -154,6 +154,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = rx51_map_io, + .reserve = omap_reserve, .init_irq = rx51_init_irq, .init_machine = rx51_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index 803ef14cbf2d..ffe188cb18e9 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c @@ -95,6 +95,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap_zoom2_map_io, + .reserve = omap_reserve, .init_irq = omap_zoom2_init_irq, .init_machine = omap_zoom2_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c index 33147042485f..5b605eba3e7b 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom3.c @@ -77,6 +77,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc, .boot_params = 0x80000100, .map_io = omap_zoom_map_io, + .reserve = omap_reserve, .init_irq = omap_zoom_init_irq, .init_machine = omap_zoom_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 41b155acfca7..d33744117ce2 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3166,6 +3166,10 @@ static struct clk uart4_ick_am35xx = { .recalc = &followparent_recalc, }; +static struct clk dummy_apb_pclk = { + .name = "apb_pclk", + .ops = &clkops_null, +}; /* * clkdev @@ -3173,6 +3177,7 @@ static struct clk uart4_ick_am35xx = { /* XXX At some point we should rename this file to clock3xxx_data.c */ static struct omap_clk omap3xxx_clks[] = { + CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX), CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 3cfb425ea67e..4e1f53d0b880 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -33,7 +33,6 @@ #include <plat/sdrc.h> #include <plat/gpmc.h> #include <plat/serial.h> -#include <plat/vram.h> #include "clock2xxx.h" #include "clock3xxx.h" @@ -241,8 +240,6 @@ static void __init _omap2_map_common_io(void) omap2_check_revision(); omap_sram_init(); - omapfb_reserve_sdram(); - omap_vram_reserve_sdram(); } #ifdef CONFIG_ARCH_OMAP2420 diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 905719a677ae..c897e03e413d 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -26,6 +26,7 @@ config MACH_KUROBOX_PRO config MACH_DNS323 bool "D-Link DNS-323" select I2C_BOARDINFO + select PHYLIB help Say 'Y' here if you want your kernel to support the D-Link DNS-323 platform. diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index fe0de1698edc..a47100d46a4e 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -3,6 +3,10 @@ * * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> * + * Support for HW Rev C1: + * + * Copyright (C) 2010 Benjamin Herrenschmidt <benh@kernel.crashing.org> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as * published by the Free Software Foundation; either version 2 of the @@ -23,6 +27,8 @@ #include <linux/input.h> #include <linux/i2c.h> #include <linux/ata_platform.h> +#include <linux/phy.h> +#include <linux/marvell_phy.h> #include <asm/mach-types.h> #include <asm/gpio.h> #include <asm/mach/arch.h> @@ -31,6 +37,7 @@ #include "common.h" #include "mpp.h" +/* Rev A1 and B1 */ #define DNS323_GPIO_LED_RIGHT_AMBER 1 #define DNS323_GPIO_LED_LEFT_AMBER 2 #define DNS323_GPIO_SYSTEM_UP 3 @@ -42,6 +49,23 @@ #define DNS323_GPIO_KEY_POWER 9 #define DNS323_GPIO_KEY_RESET 10 +/* Rev C1 */ +#define DNS323C_GPIO_KEY_POWER 1 +#define DNS323C_GPIO_POWER_OFF 2 +#define DNS323C_GPIO_LED_RIGHT_AMBER 8 +#define DNS323C_GPIO_LED_LEFT_AMBER 9 +#define DNS323C_GPIO_LED_POWER 17 +#define DNS323C_GPIO_FAN_BIT1 18 +#define DNS323C_GPIO_FAN_BIT0 19 + +/* Exposed to userspace, do not change */ +enum { + DNS323_REV_A1, /* 0 */ + DNS323_REV_B1, /* 1 */ + DNS323_REV_C1, /* 2 */ +}; + + /**************************************************************************** * PCI setup */ @@ -68,21 +92,12 @@ static struct hw_pci dns323_pci __initdata = { .map_irq = dns323_pci_map_irq, }; -static int __init dns323_dev_id(void) -{ - u32 dev, rev; - - orion5x_pcie_id(&dev, &rev); - - return dev; -} - static int __init dns323_pci_init(void) { - /* The 5182 doesn't really use its PCI bus, and initialising PCI + /* Rev B1 and C1 doesn't really use its PCI bus, and initialising PCI * gets in the way of initialising the SATA controller. */ - if (machine_is_dns323() && dns323_dev_id() != MV88F5182_DEV_ID) + if (machine_is_dns323() && system_rev == DNS323_REV_A1) pci_common_init(&dns323_pci); return 0; @@ -221,7 +236,7 @@ static int __init dns323_read_mac_addr(void) } iounmap(mac_page); - printk("DNS323: Found ethernet MAC address: "); + printk("DNS-323: Found ethernet MAC address: "); for (i = 0; i < 6; i++) printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n"); @@ -259,12 +274,11 @@ static int dns323_gpio_blink_set(unsigned gpio, int state, return 0; } -static struct gpio_led dns323_leds[] = { +static struct gpio_led dns323ab_leds[] = { { .name = "power:blue", .gpio = DNS323_GPIO_LED_POWER2, - .default_trigger = "timer", - .active_low = 1, + .default_trigger = "default-on", }, { .name = "right:amber", .gpio = DNS323_GPIO_LED_RIGHT_AMBER, @@ -276,9 +290,34 @@ static struct gpio_led dns323_leds[] = { }, }; -static struct gpio_led_platform_data dns323_led_data = { - .num_leds = ARRAY_SIZE(dns323_leds), - .leds = dns323_leds, + +static struct gpio_led dns323c_leds[] = { + { + .name = "power:blue", + .gpio = DNS323C_GPIO_LED_POWER, + .default_trigger = "timer", + .active_low = 1, + }, { + .name = "right:amber", + .gpio = DNS323C_GPIO_LED_RIGHT_AMBER, + .active_low = 1, + }, { + .name = "left:amber", + .gpio = DNS323C_GPIO_LED_LEFT_AMBER, + .active_low = 1, + }, +}; + + +static struct gpio_led_platform_data dns323ab_led_data = { + .num_leds = ARRAY_SIZE(dns323ab_leds), + .leds = dns323ab_leds, + .gpio_blink_set = dns323_gpio_blink_set, +}; + +static struct gpio_led_platform_data dns323c_led_data = { + .num_leds = ARRAY_SIZE(dns323c_leds), + .leds = dns323c_leds, .gpio_blink_set = dns323_gpio_blink_set, }; @@ -286,7 +325,7 @@ static struct platform_device dns323_gpio_leds = { .name = "leds-gpio", .id = -1, .dev = { - .platform_data = &dns323_led_data, + .platform_data = &dns323ab_led_data, }, }; @@ -294,7 +333,7 @@ static struct platform_device dns323_gpio_leds = { * GPIO Attached Keys */ -static struct gpio_keys_button dns323_buttons[] = { +static struct gpio_keys_button dns323ab_buttons[] = { { .code = KEY_RESTART, .gpio = DNS323_GPIO_KEY_RESET, @@ -308,9 +347,23 @@ static struct gpio_keys_button dns323_buttons[] = { }, }; -static struct gpio_keys_platform_data dns323_button_data = { - .buttons = dns323_buttons, - .nbuttons = ARRAY_SIZE(dns323_buttons), +static struct gpio_keys_platform_data dns323ab_button_data = { + .buttons = dns323ab_buttons, + .nbuttons = ARRAY_SIZE(dns323ab_buttons), +}; + +static struct gpio_keys_button dns323c_buttons[] = { + { + .code = KEY_POWER, + .gpio = DNS323C_GPIO_KEY_POWER, + .desc = "Power Button", + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data dns323c_button_data = { + .buttons = dns323c_buttons, + .nbuttons = ARRAY_SIZE(dns323c_buttons), }; static struct platform_device dns323_button_device = { @@ -318,7 +371,7 @@ static struct platform_device dns323_button_device = { .id = -1, .num_resources = 0, .dev = { - .platform_data = &dns323_button_data, + .platform_data = &dns323ab_button_data, }, }; @@ -332,7 +385,7 @@ static struct mv_sata_platform_data dns323_sata_data = { /**************************************************************************** * General Setup */ -static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = { +static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = { { 0, MPP_PCIE_RST_OUTn }, { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ @@ -356,7 +409,7 @@ static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = { { -1 }, }; -static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = { +static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = { { 0, MPP_UNUSED }, { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ @@ -380,15 +433,57 @@ static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = { { -1 }, }; +static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = { + { 0, MPP_GPIO }, /* ? input */ + { 1, MPP_GPIO }, /* input power switch (0 = pressed) */ + { 2, MPP_GPIO }, /* output power off */ + { 3, MPP_UNUSED }, /* ? output */ + { 4, MPP_UNUSED }, /* ? output */ + { 5, MPP_UNUSED }, /* ? output */ + { 6, MPP_UNUSED }, /* ? output */ + { 7, MPP_UNUSED }, /* ? output */ + { 8, MPP_GPIO }, /* i/o right amber LED */ + { 9, MPP_GPIO }, /* i/o left amber LED */ + { 10, MPP_GPIO }, /* input */ + { 11, MPP_UNUSED }, + { 12, MPP_SATA_LED }, + { 13, MPP_SATA_LED }, + { 14, MPP_SATA_LED }, + { 15, MPP_SATA_LED }, + { 16, MPP_UNUSED }, + { 17, MPP_GPIO }, /* power button LED */ + { 18, MPP_GPIO }, /* fan speed bit 0 */ + { 19, MPP_GPIO }, /* fan speed bit 1 */ + { -1 }, +}; + +/* Rev C1 Fan speed notes: + * + * The fan is controlled by 2 GPIOs on this board. The settings + * of the bits is as follow: + * + * GPIO 18 GPIO 19 Fan + * + * 0 0 stopped + * 0 1 low speed + * 1 0 high speed + * 1 1 don't do that (*) + * + * (*) I think the two bits control two feed-in resistors into a fixed + * PWN circuit, setting both bits will basically go a 'bit' faster + * than high speed, but d-link doesn't do it and you may get out of + * HW spec so don't do it. + */ + /* - * On the DNS-323 the following devices are attached via I2C: + * On the DNS-323 A1 and B1 the following devices are attached via I2C: * * i2c addr | chip | description * 0x3e | GMT G760Af | fan speed PWM controller * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible) * 0x68 | ST M41T80 | RTC w/ alarm */ -static struct i2c_board_info __initdata dns323_i2c_devices[] = { +static struct i2c_board_info __initdata dns323ab_i2c_devices[] = { { I2C_BOARD_INFO("g760a", 0x3e), }, { @@ -398,36 +493,140 @@ static struct i2c_board_info __initdata dns323_i2c_devices[] = { }, }; +/* + * On the DNS-323 C1 the following devices are attached via I2C: + * + * i2c addr | chip | description + * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible) + * 0x68 | ST M41T80 | RTC w/ alarm + */ +static struct i2c_board_info __initdata dns323c_i2c_devices[] = { + { + I2C_BOARD_INFO("lm75", 0x48), + }, { + I2C_BOARD_INFO("m41t80", 0x68), + }, +}; + /* DNS-323 rev. A specific power off method */ static void dns323a_power_off(void) { - pr_info("%s: triggering power-off...\n", __func__); + pr_info("DNS-323: Triggering power-off...\n"); gpio_set_value(DNS323_GPIO_POWER_OFF, 1); } /* DNS-323 rev B specific power off method */ static void dns323b_power_off(void) { - pr_info("%s: triggering power-off...\n", __func__); + pr_info("DNS-323: Triggering power-off...\n"); /* Pin has to be changed to 1 and back to 0 to do actual power off. */ gpio_set_value(DNS323_GPIO_POWER_OFF, 1); mdelay(100); gpio_set_value(DNS323_GPIO_POWER_OFF, 0); } +/* DNS-323 rev. C specific power off method */ +static void dns323c_power_off(void) +{ + pr_info("DNS-323: Triggering power-off...\n"); + gpio_set_value(DNS323C_GPIO_POWER_OFF, 1); +} + +static int dns323c_phy_fixup(struct phy_device *phy) +{ + phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS; + + return 0; +} + +static int __init dns323_identify_rev(void) +{ + u32 dev, rev, i, reg; + + pr_debug("DNS-323: Identifying board ... \n"); + + /* Rev A1 has a 5181 */ + orion5x_pcie_id(&dev, &rev); + if (dev == MV88F5181_DEV_ID) { + pr_debug("DNS-323: 5181 found, board is A1\n"); + return DNS323_REV_A1; + } + pr_debug("DNS-323: 5182 found, board is B1 or C1, checking PHY...\n"); + + /* Rev B1 and C1 both have 5182, let's poke at the eth PHY. This is + * a bit gross but we want to do that without links into the eth + * driver so let's poke at it directly. We default to rev B1 in + * case the accesses fail + */ + +#define ETH_SMI_REG (ORION5X_ETH_VIRT_BASE + 0x2000 + 0x004) +#define SMI_BUSY 0x10000000 +#define SMI_READ_VALID 0x08000000 +#define SMI_OPCODE_READ 0x04000000 +#define SMI_OPCODE_WRITE 0x00000000 + + for (i = 0; i < 1000; i++) { + reg = readl(ETH_SMI_REG); + if (!(reg & SMI_BUSY)) + break; + } + if (i >= 1000) { + pr_warning("DNS-323: Timeout accessing PHY, assuming rev B1\n"); + return DNS323_REV_B1; + } + writel((3 << 21) /* phy ID reg */ | + (8 << 16) /* phy addr */ | + SMI_OPCODE_READ, ETH_SMI_REG); + for (i = 0; i < 1000; i++) { + reg = readl(ETH_SMI_REG); + if (reg & SMI_READ_VALID) + break; + } + if (i >= 1000) { + pr_warning("DNS-323: Timeout reading PHY, assuming rev B1\n"); + return DNS323_REV_B1; + } + pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff); + + /* Note: the Marvell tools mask the ID with 0x3f0 before comparison + * but I don't see that making a difference here, at least with + * any known Marvell PHY ID + */ + switch(reg & 0xfff0) { + case 0x0cc0: /* MV88E1111 */ + return DNS323_REV_B1; + case 0x0e10: /* MV88E1118 */ + return DNS323_REV_C1; + default: + pr_warning("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n", + reg & 0xffff); + } + return DNS323_REV_B1; +} + static void __init dns323_init(void) { /* Setup basic Orion functions. Need to be called early. */ orion5x_init(); + /* Identify revision */ + system_rev = dns323_identify_rev(); + pr_info("DNS-323: Identified HW revision %c1\n", 'A' + system_rev); + /* Just to be tricky, the 5182 has a completely different * set of MPP modes to the 5181. */ - if (dns323_dev_id() == MV88F5182_DEV_ID) - orion5x_mpp_conf(dns323_mv88f5182_mpp_modes); - else { - orion5x_mpp_conf(dns323_mv88f5181_mpp_modes); + switch(system_rev) { + case DNS323_REV_A1: + orion5x_mpp_conf(dns323a_mpp_modes); writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ + break; + case DNS323_REV_B1: + orion5x_mpp_conf(dns323b_mpp_modes); + break; + case DNS323_REV_C1: + orion5x_mpp_conf(dns323c_mpp_modes); + break; } /* setup flash mapping @@ -436,53 +635,96 @@ static void __init dns323_init(void) orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); platform_device_register(&dns323_nor_flash); - /* The 5181 power LED is active low and requires - * DNS323_GPIO_LED_POWER1 to also be low. - */ - if (dns323_dev_id() == MV88F5181_DEV_ID) { - dns323_leds[0].active_low = 1; - gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable"); - gpio_direction_output(DNS323_GPIO_LED_POWER1, 0); + /* Sort out LEDs, Buttons and i2c devices */ + switch(system_rev) { + case DNS323_REV_A1: + /* The 5181 power LED is active low and requires + * DNS323_GPIO_LED_POWER1 to also be low. + */ + dns323ab_leds[0].active_low = 1; + gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable"); + gpio_direction_output(DNS323_GPIO_LED_POWER1, 0); + /* Fall through */ + case DNS323_REV_B1: + i2c_register_board_info(0, dns323ab_i2c_devices, + ARRAY_SIZE(dns323ab_i2c_devices)); + break; + case DNS323_REV_C1: + /* Hookup LEDs & Buttons */ + dns323_gpio_leds.dev.platform_data = &dns323c_led_data; + dns323_button_device.dev.platform_data = &dns323c_button_data; + + /* Hookup i2c devices and fan driver */ + i2c_register_board_info(0, dns323c_i2c_devices, + ARRAY_SIZE(dns323c_i2c_devices)); + platform_device_register_simple("dns323c-fan", 0, NULL, 0); + + /* Register fixup for the PHY LEDs */ + phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118, + MARVELL_PHY_ID_MASK, + dns323c_phy_fixup); } platform_device_register(&dns323_gpio_leds); - platform_device_register(&dns323_button_device); - i2c_register_board_info(0, dns323_i2c_devices, - ARRAY_SIZE(dns323_i2c_devices)); - /* * Configure peripherals. */ if (dns323_read_mac_addr() < 0) - printk("DNS323: Failed to read MAC address\n"); - + printk("DNS-323: Failed to read MAC address\n"); orion5x_ehci0_init(); orion5x_eth_init(&dns323_eth_data); orion5x_i2c_init(); orion5x_uart0_init(); - /* The 5182 has its SATA controller on-chip, and needs its own little - * init routine. - */ - if (dns323_dev_id() == MV88F5182_DEV_ID) + /* Remaining GPIOs */ + switch(system_rev) { + case DNS323_REV_A1: + /* Poweroff GPIO */ + if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 || + gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0) + pr_err("DNS-323: failed to setup power-off GPIO\n"); + pm_power_off = dns323a_power_off; + break; + case DNS323_REV_B1: + /* 5182 built-in SATA init */ orion5x_sata_init(&dns323_sata_data); - /* The 5182 has flag to indicate the system is up. Without this flag - * set, power LED will flash and cannot be controlled via leds-gpio. - */ - if (dns323_dev_id() == MV88F5182_DEV_ID) - gpio_set_value(DNS323_GPIO_SYSTEM_UP, 1); - - /* Register dns323 specific power-off method */ - if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 || - gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0) - pr_err("DNS323: failed to setup power-off GPIO\n"); - if (dns323_dev_id() == MV88F5182_DEV_ID) + /* The DNS323 rev B1 has flag to indicate the system is up. + * Without this flag set, power LED will flash and cannot be + * controlled via leds-gpio. + */ + if (gpio_request(DNS323_GPIO_SYSTEM_UP, "SYS_READY") == 0) + gpio_direction_output(DNS323_GPIO_SYSTEM_UP, 1); + + /* Poweroff GPIO */ + if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 || + gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0) + pr_err("DNS-323: failed to setup power-off GPIO\n"); pm_power_off = dns323b_power_off; - else - pm_power_off = dns323a_power_off; + break; + case DNS323_REV_C1: + /* 5182 built-in SATA init */ + orion5x_sata_init(&dns323_sata_data); + + /* Poweroff GPIO */ + if (gpio_request(DNS323C_GPIO_POWER_OFF, "POWEROFF") != 0 || + gpio_direction_output(DNS323C_GPIO_POWER_OFF, 0) != 0) + pr_err("DNS-323: failed to setup power-off GPIO\n"); + pm_power_off = dns323c_power_off; + + /* Now, -this- should theorically be done by the sata_mv driver + * once I figure out what's going on there. Maybe the behaviour + * of the LEDs should be somewhat passed via the platform_data. + * for now, just whack the register and make the LEDs happy + * + * Note: AFAIK, rev B1 needs the same treatement but I'll let + * somebody else test it. + */ + writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c); + break; + } } /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h index 60e734c10458..a1d6e46ab035 100644 --- a/arch/arm/mach-orion5x/include/mach/system.h +++ b/arch/arm/mach-orion5x/include/mach/system.h @@ -25,6 +25,8 @@ static inline void arch_reset(char mode, const char *cmd) */ orion5x_setbits(RSTOUTn_MASK, (1 << 2)); orion5x_setbits(CPU_SOFT_RESET, 1); + mdelay(200); + orion5x_clrbits(CPU_SOFT_RESET, 1); } diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index 161fc2d61207..0f3130599770 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c @@ -35,7 +35,7 @@ static int cmx2xx_it8152_irq_gpio; * This is really ugly and we need a better way of specifying * DMA-capable regions of memory. */ -void __init cmx2xx_pci_adjust_zones(int node, unsigned long *zone_size, +void __init cmx2xx_pci_adjust_zones(unsigned long *zone_size, unsigned long *zhole_size) { unsigned int sz = SZ_64M >> PAGE_SHIFT; @@ -46,7 +46,7 @@ void __init cmx2xx_pci_adjust_zones(int node, unsigned long *zone_size, /* * Only adjust if > 64M on current system */ - if (node || (zone_size[0] <= sz)) + if (zone_size[0] <= sz) return; zone_size[1] = zone_size[0] - sz; diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 51ffa6afb675..461ba4080155 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -715,7 +715,6 @@ static void __init fixup_corgi(struct machine_desc *desc, sharpsl_save_param(); mi->nr_banks=1; mi->bank[0].start = 0xa0000000; - mi->bank[0].node = 0; if (machine_is_corgi()) mi->bank[0].size = (32*1024*1024); else diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index 96ed13081639..a0ab3082a000 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c @@ -34,7 +34,6 @@ void __init eseries_fixup(struct machine_desc *desc, { mi->nr_banks=1; mi->bank[0].start = 0xa0000000; - mi->bank[0].node = 0; if (machine_is_e800()) mi->bank[0].size = (128*1024*1024); else diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 890fb90a672f..c6305c5b8a72 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -26,8 +26,7 @@ extern unsigned int get_clk_frequency_khz(int info); #define SET_BANK(__nr,__start,__size) \ mi->bank[__nr].start = (__start), \ - mi->bank[__nr].size = (__size), \ - mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27) + mi->bank[__nr].size = (__size) #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h index f626730ee42e..92361a66b223 100644 --- a/arch/arm/mach-pxa/include/mach/memory.h +++ b/arch/arm/mach-pxa/include/mach/memory.h @@ -17,24 +17,11 @@ */ #define PHYS_OFFSET UL(0xa0000000) -/* - * The nodes are matched with the physical SDRAM banks as follows: - * - * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff - * node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff - * node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff - * node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff - * - * This needs a node mem size of 26 bits. - */ -#define NODE_MEM_SIZE_BITS 26 - #if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) -void cmx2xx_pci_adjust_zones(int node, unsigned long *size, - unsigned long *holes); +void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes); -#define arch_adjust_zones(node, size, holes) \ - cmx2xx_pci_adjust_zones(node, size, holes) +#define arch_adjust_zones(size, holes) \ + cmx2xx_pci_adjust_zones(size, holes) #define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) #define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c index 5305a3993e69..5e92d84fe50d 100644 --- a/arch/arm/mach-pxa/palmt5.c +++ b/arch/arm/mach-pxa/palmt5.c @@ -21,6 +21,7 @@ #include <linux/irq.h> #include <linux/gpio_keys.h> #include <linux/input.h> +#include <linux/memblock.h> #include <linux/pda_power.h> #include <linux/pwm_backlight.h> #include <linux/gpio.h> @@ -396,6 +397,11 @@ static void __init palmt5_udc_init(void) } } +static void __init palmt5_reserve(void) +{ + memblock_reserve(0xa0200000, 0x1000); +} + static void __init palmt5_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmt5_pin_config)); @@ -421,6 +427,7 @@ MACHINE_START(PALMT5, "Palm Tungsten|T5") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = pxa_map_io, + .reserve = palmt5_reserve, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = palmt5_init diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c index d8b4469607a1..3d0c9cc2a406 100644 --- a/arch/arm/mach-pxa/palmtreo.c +++ b/arch/arm/mach-pxa/palmtreo.c @@ -20,6 +20,7 @@ #include <linux/irq.h> #include <linux/gpio_keys.h> #include <linux/input.h> +#include <linux/memblock.h> #include <linux/pda_power.h> #include <linux/pwm_backlight.h> #include <linux/gpio.h> @@ -633,6 +634,12 @@ static void __init treo_lcd_power_init(void) treo_lcd_screen.pxafb_lcd_power = treo_lcd_power; } +static void __init treo_reserve(void) +{ + memblock_reserve(0xa0000000, 0x1000); + memblock_reserve(0xa2000000, 0x1000); +} + static void __init treo_init(void) { pxa_set_ffuart_info(NULL); @@ -668,6 +675,7 @@ MACHINE_START(TREO680, "Palm Treo 680") .io_pg_offst = io_p2v(0x40000000), .boot_params = 0xa0000100, .map_io = pxa_map_io, + .reserve = treo_reserve, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = treo680_init, @@ -691,6 +699,7 @@ MACHINE_START(CENTRO, "Palm Centro 685") .io_pg_offst = io_p2v(0x40000000), .boot_params = 0xa0000100, .map_io = pxa_map_io, + .reserve = treo_reserve, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = centro_init, diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index f4abdaafdac4..bc2758b54446 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -463,7 +463,6 @@ static void __init fixup_poodle(struct machine_desc *desc, sharpsl_save_param(); mi->nr_banks=1; mi->bank[0].start = 0xa0000000; - mi->bank[0].node = 0; mi->bank[0].size = (32*1024*1024); } diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index c1048a35f187..51756c723557 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -847,7 +847,6 @@ static void __init fixup_spitz(struct machine_desc *desc, sharpsl_save_param(); mi->nr_banks = 1; mi->bank[0].start = 0xa0000000; - mi->bank[0].node = 0; mi->bank[0].size = (64*1024*1024); } diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 7512b822c6ca..83cc3a18c2e9 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -948,7 +948,6 @@ static void __init fixup_tosa(struct machine_desc *desc, sharpsl_save_param(); mi->nr_banks=1; mi->bank[0].start = 0xa0000000; - mi->bank[0].node = 0; mi->bank[0].size = (64*1024*1024); } diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 595be19f8ad5..2fa38df28414 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -61,12 +61,11 @@ void __iomem *gic_cpu_base_addr; /* * Adjust the zones if there are restrictions for DMA access. */ -void __init realview_adjust_zones(int node, unsigned long *size, - unsigned long *hole) +void __init realview_adjust_zones(unsigned long *size, unsigned long *hole) { unsigned long dma_size = SZ_256M >> PAGE_SHIFT; - if (!machine_is_realview_pbx() || node || (size[0] <= dma_size)) + if (!machine_is_realview_pbx() || size[0] <= dma_size) return; size[ZONE_NORMAL] = size[0] - dma_size; @@ -232,12 +231,27 @@ static unsigned int realview_mmc_status(struct device *dev) struct amba_device *adev = container_of(dev, struct amba_device, dev); u32 mask; + if (machine_is_realview_pb1176()) { + static bool inserted = false; + + /* + * The PB1176 does not have the status register, + * assume it is inserted at startup, then invert + * for each call so card insertion/removal will + * be detected anyway. This will not be called if + * GPIO on PL061 is active, which is the proper + * way to do this on the PB1176. + */ + inserted = !inserted; + return inserted ? 0 : 1; + } + if (adev->res.start == REALVIEW_MMCI0_BASE) mask = 1; else mask = 2; - return !(readl(REALVIEW_SYSMCI) & mask); + return readl(REALVIEW_SYSMCI) & mask; } struct mmci_platform_data realview_mmc0_plat_data = { @@ -300,8 +314,13 @@ static struct clk ref24_clk = { .rate = 24000000, }; +static struct clk dummy_apb_pclk; + static struct clk_lookup lookups[] = { - { /* UART0 */ + { /* Bus clock */ + .con_id = "apb_pclk", + .clk = &dummy_apb_pclk, + }, { /* UART0 */ .dev_id = "dev:uart0", .clk = &ref24_clk, }, { /* UART1 */ @@ -313,6 +332,12 @@ static struct clk_lookup lookups[] = { }, { /* UART3 */ .dev_id = "fpga:uart3", .clk = &ref24_clk, + }, { /* UART3 is on the dev chip in PB1176 */ + .dev_id = "dev:uart3", + .clk = &ref24_clk, + }, { /* UART4 only exists in PB1176 */ + .dev_id = "fpga:uart4", + .clk = &ref24_clk, }, { /* KMI0 */ .dev_id = "fpga:kmi0", .clk = &ref24_clk, @@ -322,12 +347,15 @@ static struct clk_lookup lookups[] = { }, { /* MMC0 */ .dev_id = "fpga:mmc0", .clk = &ref24_clk, - }, { /* EB:CLCD */ + }, { /* CLCD is in the PB1176 and EB DevChip */ .dev_id = "dev:clcd", .clk = &oscvco_clk, }, { /* PB:CLCD */ .dev_id = "issp:clcd", .clk = &oscvco_clk, + }, { /* SSP */ + .dev_id = "dev:ssp0", + .clk = &ref24_clk, } }; @@ -342,7 +370,7 @@ static int __init clk_init(void) return 0; } -arch_initcall(clk_init); +core_initcall(clk_init); /* * CLCD support. diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h index 2f5ccb298858..002ab5d8c11c 100644 --- a/arch/arm/mach-realview/include/mach/board-pb1176.h +++ b/arch/arm/mach-realview/include/mach/board-pb1176.h @@ -26,6 +26,7 @@ /* * Peripheral addresses */ +#define REALVIEW_PB1176_UART4_BASE 0x10009000 /* UART 4 */ #define REALVIEW_PB1176_SCTL_BASE 0x10100000 /* System controller */ #define REALVIEW_PB1176_SMC_BASE 0x10111000 /* SMC */ #define REALVIEW_PB1176_DMC_BASE 0x10109000 /* DMC configuration */ diff --git a/arch/arm/mach-realview/include/mach/irqs-pb1176.h b/arch/arm/mach-realview/include/mach/irqs-pb1176.h index 830055bb8628..5c3c625e3e04 100644 --- a/arch/arm/mach-realview/include/mach/irqs-pb1176.h +++ b/arch/arm/mach-realview/include/mach/irqs-pb1176.h @@ -40,6 +40,7 @@ #define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13) #define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14) #define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */ +#define IRQ_DC1176_SSP (IRQ_DC1176_GIC_START + 17) /* SSP port */ #define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */ #define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */ #define IRQ_DC1176_UART2 (IRQ_DC1176_GIC_START + 20) /* UART 2 on development chip */ @@ -73,7 +74,6 @@ #define IRQ_PB1176_RTC (IRQ_PB1176_GIC_START + 25) /* Real Time Clock */ #define IRQ_PB1176_GPIO0 -1 -#define IRQ_PB1176_SSP -1 #define IRQ_PB1176_SCTL -1 #define NR_GIC_PB1176 2 diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h index 2417bbcf97fd..5dafc157b276 100644 --- a/arch/arm/mach-realview/include/mach/memory.h +++ b/arch/arm/mach-realview/include/mach/memory.h @@ -30,10 +30,9 @@ #endif #if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA) -extern void realview_adjust_zones(int node, unsigned long *size, - unsigned long *hole); -#define arch_adjust_zones(node, size, hole) \ - realview_adjust_zones(node, size, hole) +extern void realview_adjust_zones(unsigned long *size, unsigned long *hole); +#define arch_adjust_zones(size, hole) \ + realview_adjust_zones(size, hole) #define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) #define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M) diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 4425018fab82..991c1f8390e2 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -25,6 +25,7 @@ #include <linux/amba/bus.h> #include <linux/amba/pl061.h> #include <linux/amba/mmci.h> +#include <linux/amba/pl022.h> #include <linux/io.h> #include <mach/hardware.h> @@ -129,6 +130,12 @@ static struct pl061_platform_data gpio2_plat_data = { .irq_base = -1, }; +static struct pl022_ssp_controller ssp0_plat_data = { + .bus_id = 0, + .enable_dma = 0, + .num_chipselect = 1, +}; + /* * RealView EB AMBA devices */ @@ -213,7 +220,7 @@ AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL); AMBA_DEVICE(uart0, "dev:uart0", EB_UART0, NULL); AMBA_DEVICE(uart1, "dev:uart1", EB_UART1, NULL); AMBA_DEVICE(uart2, "dev:uart2", EB_UART2, NULL); -AMBA_DEVICE(ssp0, "dev:ssp0", EB_SSP, NULL); +AMBA_DEVICE(ssp0, "dev:ssp0", EB_SSP, &ssp0_plat_data); static struct amba_device *amba_devs[] __initdata = { &dmac_device, @@ -324,6 +331,26 @@ static struct platform_device pmu_device = { .resource = pmu_resources, }; +static struct resource char_lcd_resources[] = { + { + .start = REALVIEW_CHAR_LCD_BASE, + .end = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1), + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_EB_CHARLCD, + .end = IRQ_EB_CHARLCD, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device char_lcd_device = { + .name = "arm-charlcd", + .id = -1, + .num_resources = ARRAY_SIZE(char_lcd_resources), + .resource = char_lcd_resources, +}; + static void __init gic_init_irq(void) { if (core_tile_eb11mp() || core_tile_a9mp()) { @@ -442,6 +469,7 @@ static void __init realview_eb_init(void) realview_flash_register(&realview_eb_flash_resource, 1); platform_device_register(&realview_i2c_device); + platform_device_register(&char_lcd_device); eth_device_register(); realview_usb_register(realview_eb_isp1761_resources); diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index 099a1f125cf8..d2be12eb829e 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c @@ -25,6 +25,7 @@ #include <linux/amba/bus.h> #include <linux/amba/pl061.h> #include <linux/amba/mmci.h> +#include <linux/amba/pl022.h> #include <linux/io.h> #include <mach/hardware.h> @@ -123,6 +124,12 @@ static struct pl061_platform_data gpio2_plat_data = { .irq_base = -1, }; +static struct pl022_ssp_controller ssp0_plat_data = { + .bus_id = 0, + .enable_dma = 0, + .num_chipselect = 1, +}; + /* * RealView PB1176 AMBA devices */ @@ -144,8 +151,6 @@ static struct pl061_platform_data gpio2_plat_data = { #define MPMC_DMA { 0, 0 } #define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ } #define PB1176_CLCD_DMA { 0, 0 } -#define DMAC_IRQ { IRQ_PB1176_DMAC, NO_IRQ } -#define DMAC_DMA { 0, 0 } #define SCTL_IRQ { NO_IRQ, NO_IRQ } #define SCTL_DMA { 0, 0 } #define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG, NO_IRQ } @@ -166,7 +171,9 @@ static struct pl061_platform_data gpio2_plat_data = { #define PB1176_UART2_DMA { 11, 10 } #define PB1176_UART3_IRQ { IRQ_DC1176_UART3, NO_IRQ } #define PB1176_UART3_DMA { 0x86, 0x87 } -#define PB1176_SSP_IRQ { IRQ_PB1176_SSP, NO_IRQ } +#define PB1176_UART4_IRQ { IRQ_PB1176_UART4, NO_IRQ } +#define PB1176_UART4_DMA { 0, 0 } +#define PB1176_SSP_IRQ { IRQ_DC1176_SSP, NO_IRQ } #define PB1176_SSP_DMA { 9, 8 } /* FPGA Primecells */ @@ -174,7 +181,7 @@ AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); AMBA_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data); AMBA_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL); AMBA_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL); -AMBA_DEVICE(uart3, "fpga:uart3", PB1176_UART3, NULL); +AMBA_DEVICE(uart4, "fpga:uart4", PB1176_UART4, NULL); /* DevChip Primecells */ AMBA_DEVICE(smc, "dev:smc", PB1176_SMC, NULL); @@ -188,18 +195,16 @@ AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL); AMBA_DEVICE(uart0, "dev:uart0", PB1176_UART0, NULL); AMBA_DEVICE(uart1, "dev:uart1", PB1176_UART1, NULL); AMBA_DEVICE(uart2, "dev:uart2", PB1176_UART2, NULL); -AMBA_DEVICE(ssp0, "dev:ssp0", PB1176_SSP, NULL); - -/* Primecells on the NEC ISSP chip */ -AMBA_DEVICE(clcd, "issp:clcd", PB1176_CLCD, &clcd_plat_data); -//AMBA_DEVICE(dmac, "issp:dmac", PB1176_DMAC, NULL); +AMBA_DEVICE(uart3, "dev:uart3", PB1176_UART3, NULL); +AMBA_DEVICE(ssp0, "dev:ssp0", PB1176_SSP, &ssp0_plat_data); +AMBA_DEVICE(clcd, "dev:clcd", PB1176_CLCD, &clcd_plat_data); static struct amba_device *amba_devs[] __initdata = { -// &dmac_device, &uart0_device, &uart1_device, &uart2_device, &uart3_device, + &uart4_device, &smc_device, &clcd_device, &sctl_device, @@ -276,6 +281,26 @@ static struct platform_device pmu_device = { .resource = &pmu_resource, }; +static struct resource char_lcd_resources[] = { + { + .start = REALVIEW_CHAR_LCD_BASE, + .end = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1), + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_PB1176_CHARLCD, + .end = IRQ_PB1176_CHARLCD, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device char_lcd_device = { + .name = "arm-charlcd", + .id = -1, + .num_resources = ARRAY_SIZE(char_lcd_resources), + .resource = char_lcd_resources, +}; + static void __init gic_init_irq(void) { /* ARM1176 DevChip GIC, primary */ @@ -338,6 +363,7 @@ static void __init realview_pb1176_init(void) platform_device_register(&realview_i2c_device); realview_usb_register(realview_pb1176_isp1761_resources); platform_device_register(&pmu_device); + platform_device_register(&char_lcd_device); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index 0e07a5ccb75f..d591bc00b86e 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c @@ -25,6 +25,7 @@ #include <linux/amba/bus.h> #include <linux/amba/pl061.h> #include <linux/amba/mmci.h> +#include <linux/amba/pl022.h> #include <linux/io.h> #include <mach/hardware.h> @@ -124,6 +125,12 @@ static struct pl061_platform_data gpio2_plat_data = { .irq_base = -1, }; +static struct pl022_ssp_controller ssp0_plat_data = { + .bus_id = 0, + .enable_dma = 0, + .num_chipselect = 1, +}; + /* * RealView PB11MPCore AMBA devices */ @@ -190,7 +197,7 @@ AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL); AMBA_DEVICE(uart0, "dev:uart0", PB11MP_UART0, NULL); AMBA_DEVICE(uart1, "dev:uart1", PB11MP_UART1, NULL); AMBA_DEVICE(uart2, "dev:uart2", PB11MP_UART2, NULL); -AMBA_DEVICE(ssp0, "dev:ssp0", PB11MP_SSP, NULL); +AMBA_DEVICE(ssp0, "dev:ssp0", PB11MP_SSP, &ssp0_plat_data); /* Primecells on the NEC ISSP chip */ AMBA_DEVICE(clcd, "issp:clcd", PB11MP_CLCD, &clcd_plat_data); diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index ac2f06f1ca50..6c37621217bc 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c @@ -25,6 +25,7 @@ #include <linux/amba/bus.h> #include <linux/amba/pl061.h> #include <linux/amba/mmci.h> +#include <linux/amba/pl022.h> #include <linux/io.h> #include <asm/irq.h> @@ -114,6 +115,12 @@ static struct pl061_platform_data gpio2_plat_data = { .irq_base = -1, }; +static struct pl022_ssp_controller ssp0_plat_data = { + .bus_id = 0, + .enable_dma = 0, + .num_chipselect = 1, +}; + /* * RealView PBA8Core AMBA devices */ @@ -180,7 +187,7 @@ AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL); AMBA_DEVICE(uart0, "dev:uart0", PBA8_UART0, NULL); AMBA_DEVICE(uart1, "dev:uart1", PBA8_UART1, NULL); AMBA_DEVICE(uart2, "dev:uart2", PBA8_UART2, NULL); -AMBA_DEVICE(ssp0, "dev:ssp0", PBA8_SSP, NULL); +AMBA_DEVICE(ssp0, "dev:ssp0", PBA8_SSP, &ssp0_plat_data); /* Primecells on the NEC ISSP chip */ AMBA_DEVICE(clcd, "issp:clcd", PBA8_CLCD, &clcd_plat_data); diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index 08fd683adc4c..9428eff0b116 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@ -24,6 +24,7 @@ #include <linux/amba/bus.h> #include <linux/amba/pl061.h> #include <linux/amba/mmci.h> +#include <linux/amba/pl022.h> #include <linux/io.h> #include <asm/irq.h> @@ -136,6 +137,12 @@ static struct pl061_platform_data gpio2_plat_data = { .irq_base = -1, }; +static struct pl022_ssp_controller ssp0_plat_data = { + .bus_id = 0, + .enable_dma = 0, + .num_chipselect = 1, +}; + /* * RealView PBXCore AMBA devices */ @@ -202,7 +209,7 @@ AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL); AMBA_DEVICE(uart0, "dev:uart0", PBX_UART0, NULL); AMBA_DEVICE(uart1, "dev:uart1", PBX_UART1, NULL); AMBA_DEVICE(uart2, "dev:uart2", PBX_UART2, NULL); -AMBA_DEVICE(ssp0, "dev:ssp0", PBX_SSP, NULL); +AMBA_DEVICE(ssp0, "dev:ssp0", PBX_SSP, &ssp0_plat_data); /* Primecells on the NEC ISSP chip */ AMBA_DEVICE(clcd, "issp:clcd", PBX_CLCD, &clcd_plat_data); diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 779b45b3f80f..3ba3bab139d0 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -15,6 +15,7 @@ #include <linux/types.h> #include <linux/interrupt.h> #include <linux/list.h> +#include <linux/memblock.h> #include <linux/timer.h> #include <linux/init.h> #include <linux/sysdev.h> @@ -304,6 +305,13 @@ static void __init h1940_map_io(void) s3c_pm_init(); } +/* H1940 and RX3715 need to reserve this for suspend */ +static void __init h1940_reserve(void) +{ + memblock_reserve(0x30003000, 0x1000); + memblock_reserve(0x30081000, 0x1000); +} + static void __init h1940_init_irq(void) { s3c24xx_init_irq(); @@ -346,6 +354,7 @@ MACHINE_START(H1940, "IPAQ-H1940") .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .boot_params = S3C2410_SDRAM_PA + 0x100, .map_io = h1940_map_io, + .reserve = h1940_reserve, .init_irq = h1940_init_irq, .init_machine = h1940_init, .timer = &s3c24xx_timer, diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c index ba93a356a839..054c9f92232a 100644 --- a/arch/arm/mach-s3c2412/mach-smdk2413.c +++ b/arch/arm/mach-s3c2412/mach-smdk2413.c @@ -119,7 +119,6 @@ static void __init smdk2413_fixup(struct machine_desc *desc, mi->nr_banks=1; mi->bank[0].start = 0x30000000; mi->bank[0].size = SZ_64M; - mi->bank[0].node = 0; } } diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c index 3ca9265b6997..f291ac25d312 100644 --- a/arch/arm/mach-s3c2412/mach-vstms.c +++ b/arch/arm/mach-s3c2412/mach-vstms.c @@ -137,7 +137,6 @@ static void __init vstms_fixup(struct machine_desc *desc, mi->nr_banks=1; mi->bank[0].start = 0x30000000; mi->bank[0].size = SZ_64M; - mi->bank[0].node = 0; } } diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c index 8603b577a24b..142d1f921176 100644 --- a/arch/arm/mach-s3c2440/mach-rx1950.c +++ b/arch/arm/mach-s3c2440/mach-rx1950.c @@ -15,6 +15,7 @@ #include <linux/types.h> #include <linux/interrupt.h> #include <linux/list.h> +#include <linux/memblock.h> #include <linux/delay.h> #include <linux/timer.h> #include <linux/init.h> @@ -570,12 +571,20 @@ static void __init rx1950_init_machine(void) platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices)); } +/* H1940 and RX3715 need to reserve this for suspend */ +static void __init rx1950_reserve(void) +{ + memblock_reserve(0x30003000, 0x1000); + memblock_reserve(0x30081000, 0x1000); +} + MACHINE_START(RX1950, "HP iPAQ RX1950") /* Maintainers: Vasily Khoruzhick */ .phys_io = S3C2410_PA_UART, .io_pg_offst = (((u32) S3C24XX_VA_UART) >> 18) & 0xfffc, .boot_params = S3C2410_SDRAM_PA + 0x100, .map_io = rx1950_map_io, + .reserve = rx1950_reserve, .init_irq = s3c24xx_init_irq, .init_machine = rx1950_init_machine, .timer = &s3c24xx_timer, diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index d2946de3f365..6bb44f75a9ce 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c @@ -15,6 +15,7 @@ #include <linux/types.h> #include <linux/interrupt.h> #include <linux/list.h> +#include <linux/memblock.h> #include <linux/timer.h> #include <linux/init.h> #include <linux/tty.h> @@ -191,6 +192,13 @@ static void __init rx3715_map_io(void) s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); } +/* H1940 and RX3715 need to reserve this for suspend */ +static void __init rx3715_reserve(void) +{ + memblock_reserve(0x30003000, 0x1000); + memblock_reserve(0x30081000, 0x1000); +} + static void __init rx3715_init_irq(void) { s3c24xx_init_irq(); @@ -214,6 +222,7 @@ MACHINE_START(RX3715, "IPAQ-RX3715") .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .boot_params = S3C2410_SDRAM_PA + 0x100, .map_io = rx3715_map_io, + .reserve = rx3715_reserve, .init_irq = rx3715_init_irq, .init_machine = rx3715_init_machine, .timer = &s3c24xx_timer, diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h index ec03f187c52b..b7a9a601c2d1 100644 --- a/arch/arm/mach-sa1100/generic.h +++ b/arch/arm/mach-sa1100/generic.h @@ -13,8 +13,7 @@ extern void __init sa1100_init_gpio(void); #define SET_BANK(__nr,__start,__size) \ mi->bank[__nr].start = (__start), \ - mi->bank[__nr].size = (__size), \ - mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27) + mi->bank[__nr].size = (__size) extern void (*sa1100fb_backlight_power)(int on); extern void (*sa1100fb_lcd_power)(int on); diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h index d5277f9bee77..128a1dfa96b9 100644 --- a/arch/arm/mach-sa1100/include/mach/memory.h +++ b/arch/arm/mach-sa1100/include/mach/memory.h @@ -17,10 +17,10 @@ #ifndef __ASSEMBLY__ #ifdef CONFIG_SA1111 -void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes); +void sa1111_adjust_zones(unsigned long *size, unsigned long *holes); -#define arch_adjust_zones(node, size, holes) \ - sa1111_adjust_zones(node, size, holes) +#define arch_adjust_zones(size, holes) \ + sa1111_adjust_zones(size, holes) #define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1) #define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_1M) diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h index 3053e5b7f168..d9c4812f1c31 100644 --- a/arch/arm/mach-shark/include/mach/memory.h +++ b/arch/arm/mach-shark/include/mach/memory.h @@ -19,9 +19,8 @@ #ifndef __ASSEMBLY__ -static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsigned long *zhole_size) +static inline void __arch_adjust_zones(unsigned long *zone_size, unsigned long *zhole_size) { - if (node != 0) return; /* Only the first 4 MB (=1024 Pages) are usable for DMA */ /* See dev / -> .properties in OpenFirmware. */ zone_size[1] = zone_size[0] - 1024; @@ -30,8 +29,8 @@ static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsig zhole_size[0] = 0; } -#define arch_adjust_zones(node, size, holes) \ - __arch_adjust_zones(node, size, holes) +#define arch_adjust_zones(size, holes) \ + __arch_adjust_zones(size, holes) #define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_4M - 1) #define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_4M) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index f2b88c5fe142..4c704b4e8b34 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -70,6 +70,18 @@ endmenu menu "Timer and clock configuration" +config SHMOBILE_TIMER_HZ + int "Kernel HZ (jiffies per second)" + range 32 1024 + default "128" + help + Allows the configuration of the timer frequency. It is customary + to have the timer interrupt run at 1000 Hz or 100 Hz, but in the + case of low timer frequencies other values may be more suitable. + SH-Mobile systems using a 32768 Hz RCLK for clock events may want + to select a HZ value such as 128 that can evenly divide RCLK. + A HZ value that does not divide evenly may cause timer drift. + config SH_TIMER_CMT bool "CMT timer driver" default y diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h index 5179b72e1ee3..132256bb8c81 100644 --- a/arch/arm/mach-shmobile/include/mach/irqs.h +++ b/arch/arm/mach-shmobile/include/mach/irqs.h @@ -2,7 +2,6 @@ #define __ASM_MACH_IRQS_H #define NR_IRQS 512 -#define NR_IRQS_LEGACY 8 #define evt2irq(evt) (((evt) >> 5) - 16) #define irq2evt(irq) (((irq) + 16) << 5) diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c index 39f6ccf22294..18febf92f20a 100644 --- a/arch/arm/mach-spear3xx/clock.c +++ b/arch/arm/mach-spear3xx/clock.c @@ -341,8 +341,11 @@ static struct clk gpio_clk = { .recalc = &follow_parent, }; +static struct clk dummy_apb_pclk; + /* array of all spear 3xx clock lookups */ static struct clk_lookup spear_clk_lookups[] = { + { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, /* root clks */ { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, { .con_id = "osc_24m_clk", .clk = &osc_24m_clk}, diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c index 13e27c769685..36ff056b7321 100644 --- a/arch/arm/mach-spear6xx/clock.c +++ b/arch/arm/mach-spear6xx/clock.c @@ -428,8 +428,11 @@ static struct clk gpio2_clk = { .recalc = &follow_parent, }; +static struct clk dummy_apb_pclk; + /* array of all spear 6xx clock lookups */ static struct clk_lookup spear_clk_lookups[] = { + { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, /* root clks */ { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, { .con_id = "osc_30m_clk", .clk = &osc_30m_clk}, diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c index 5af71d5ba665..5d12d547789e 100644 --- a/arch/arm/mach-u300/clock.c +++ b/arch/arm/mach-u300/clock.c @@ -1212,6 +1212,8 @@ static struct clk ppm_clk = { }; #endif +static struct clk dummy_apb_pclk; + #define DEF_LOOKUP(devid, clkref) \ { \ .dev_id = devid, \ @@ -1223,6 +1225,10 @@ static struct clk ppm_clk = { * look up through clockdevice. */ static struct clk_lookup lookups[] = { + { + .con_id = "apb_pclk", + .clk = &dummy_apb_pclk, + }, /* Connected directly to the AMBA bus */ DEF_LOOKUP("amba", &amba_clk), DEF_LOOKUP("cpu", &cpu_clk), diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h index ab000df7fc03..bf134bcc129d 100644 --- a/arch/arm/mach-u300/include/mach/memory.h +++ b/arch/arm/mach-u300/include/mach/memory.h @@ -35,14 +35,6 @@ #endif /* - * TCM memory whereabouts - */ -#define ITCM_OFFSET 0xffff2000 -#define ITCM_END 0xffff3fff -#define DTCM_OFFSET 0xffff4000 -#define DTCM_END 0xffff5fff - -/* * We enable a real big DMA buffer if need be. */ #define CONSISTENT_DMA_SIZE SZ_4M diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c index d2a0b8847a18..bfcda9820888 100644 --- a/arch/arm/mach-u300/u300.c +++ b/arch/arm/mach-u300/u300.c @@ -14,6 +14,7 @@ #include <linux/sched.h> #include <linux/interrupt.h> #include <linux/ioport.h> +#include <linux/memblock.h> #include <linux/platform_device.h> #include <linux/io.h> #include <mach/hardware.h> @@ -22,6 +23,21 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> +static void __init u300_reserve(void) +{ + /* + * U300 - This platform family can share physical memory + * between two ARM cpus, one running Linux and the other + * running another OS. + */ +#ifdef CONFIG_MACH_U300_SINGLE_RAM +#if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) && \ + CONFIG_MACH_U300_2MB_ALIGNMENT_FIX + memblock_reserve(PHYS_OFFSET, 0x00100000); +#endif +#endif +} + static void __init u300_init_machine(void) { u300_init_devices(); @@ -49,6 +65,7 @@ MACHINE_START(U300, MACH_U300_STRING) .io_pg_offst = ((U300_AHB_PER_VIRT_BASE) >> 18) & 0xfffc, .boot_params = BOOT_PARAMS_OFFSET, .map_io = u300_map_io, + .reserve = u300_reserve, .init_irq = u300_init_irq, .timer = &u300_timer, .init_machine = u300_init_machine, diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index bb8d7b771817..0e8fd135a57d 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -13,19 +13,42 @@ #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/gpio.h> #include <linux/amba/bus.h> #include <linux/amba/pl022.h> #include <linux/spi/spi.h> +#include <linux/mfd/ab8500.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> +#include <plat/pincfg.h> #include <plat/i2c.h> #include <mach/hardware.h> #include <mach/setup.h> #include <mach/devices.h> +#include "pins-db8500.h" + +static pin_cfg_t mop500_pins[] = { + /* SSP0 */ + GPIO143_SSP0_CLK, + GPIO144_SSP0_FRM, + GPIO145_SSP0_RXD, + GPIO146_SSP0_TXD, + + /* I2C */ + GPIO147_I2C0_SCL, + GPIO148_I2C0_SDA, + GPIO16_I2C1_SCL, + GPIO17_I2C1_SDA, + GPIO10_I2C2_SDA, + GPIO11_I2C2_SCL, + GPIO229_I2C3_SDA, + GPIO230_I2C3_SCL, +}; + static void ab4500_spi_cs_control(u32 command) { /* set the FRM signal, which is CS - TODO */ @@ -48,15 +71,20 @@ struct pl022_config_chip ab4500_chip_info = { .cs_control = ab4500_spi_cs_control, }; +static struct ab8500_platform_data ab8500_platdata = { + .irq_base = MOP500_AB8500_IRQ_BASE, +}; + static struct spi_board_info u8500_spi_devices[] = { { .modalias = "ab8500", .controller_data = &ab4500_chip_info, + .platform_data = &ab8500_platdata, .max_speed_hz = 12000000, .bus_num = 0, .chip_select = 0, .mode = SPI_MODE_0, - .irq = IRQ_AB4500, + .irq = IRQ_DB8500_AB8500, }, }; @@ -118,6 +146,10 @@ static void __init u8500_init_machine(void) { int i; + u8500_init_devices(); + + nmk_config_pins(mop500_pins, ARRAY_SIZE(mop500_pins)); + u8500_i2c0_device.dev.platform_data = &u8500_i2c0_data; ux500_i2c1_device.dev.platform_data = &u8500_i2c1_data; ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data; @@ -133,8 +165,6 @@ static void __init u8500_init_machine(void) spi_register_board_info(u8500_spi_devices, ARRAY_SIZE(u8500_spi_devices)); - - u8500_init_devices(); } MACHINE_START(U8500, "ST-Ericsson MOP500 platform") diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index 0a1318fc8e2b..d8ab7f184fe4 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@ -453,7 +453,11 @@ static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0); static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); +static struct clk clk_dummy_apb_pclk; + static struct clk_lookup u8500_common_clks[] = { + CLK(dummy_apb_pclk, NULL, "apb_pclk"), + /* Peripheral Cluster #1 */ CLK(gpio0, "gpio.0", NULL), CLK(gpio0, "gpio.1", NULL), diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 822903421943..654fca944e65 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -65,7 +65,7 @@ struct amba_device u8500_ssp0_device = { .end = U8500_SSP0_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, - .irq = {IRQ_SSP0, NO_IRQ }, + .irq = {IRQ_DB8500_SSP0, NO_IRQ }, /* ST-Ericsson modified id */ .periphid = SSP_PER_ID, }; @@ -77,8 +77,8 @@ static struct resource u8500_i2c0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_I2C0, - .end = IRQ_I2C0, + .start = IRQ_DB8500_I2C0, + .end = IRQ_DB8500_I2C0, .flags = IORESOURCE_IRQ, } }; @@ -97,8 +97,8 @@ static struct resource u8500_i2c4_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_I2C4, - .end = IRQ_I2C4, + .start = IRQ_DB8500_I2C4, + .end = IRQ_DB8500_I2C4, .flags = IORESOURCE_IRQ, } }; @@ -130,8 +130,8 @@ static struct resource dma40_resources[] = { .name = "lcla", }, [3] = { - .start = IRQ_DMA, - .end = IRQ_DMA, + .start = IRQ_DB8500_DMA, + .end = IRQ_DB8500_DMA, .flags = IORESOURCE_IRQ} }; diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h new file mode 100644 index 000000000000..cca4f705601e --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __MACH_IRQS_BOARD_MOP500_H +#define __MACH_IRQS_BOARD_MOP500_H + +#define AB8500_NR_IRQS 104 + +#define MOP500_AB8500_IRQ_BASE IRQ_BOARD_START +#define MOP500_AB8500_IRQ_END (MOP500_AB8500_IRQ_BASE \ + + AB8500_NR_IRQS) +#define MOP500_IRQ_END MOP500_AB8500_IRQ_END + +#if MOP500_IRQ_END > IRQ_BOARD_END +#undef IRQ_BOARD_END +#define IRQ_BOARD_END MOP500_IRQ_END +#endif + +#endif diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h new file mode 100644 index 000000000000..6fbfe5e2065a --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h @@ -0,0 +1,85 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __MACH_IRQS_DB5500_H +#define __MACH_IRQS_DB5500_H + +#define IRQ_DB5500_MTU0 (IRQ_SHPI_START + 4) +#define IRQ_DB5500_SPI2 (IRQ_SHPI_START + 6) +#define IRQ_DB5500_PMU0 (IRQ_SHPI_START + 7) +#define IRQ_DB5500_SPI0 (IRQ_SHPI_START + 8) +#define IRQ_DB5500_RTT (IRQ_SHPI_START + 9) +#define IRQ_DB5500_PKA (IRQ_SHPI_START + 10) +#define IRQ_DB5500_UART0 (IRQ_SHPI_START + 11) +#define IRQ_DB5500_I2C3 (IRQ_SHPI_START + 12) +#define IRQ_DB5500_L2CC (IRQ_SHPI_START + 13) +#define IRQ_DB5500_MSP0 (IRQ_SHPI_START + 14) +#define IRQ_DB5500_CRYP1 (IRQ_SHPI_START + 15) +#define IRQ_DB5500_PMU1 (IRQ_SHPI_START + 16) +#define IRQ_DB5500_MTU1 (IRQ_SHPI_START + 17) +#define IRQ_DB5500_RTC (IRQ_SHPI_START + 18) +#define IRQ_DB5500_UART1 (IRQ_SHPI_START + 19) +#define IRQ_DB5500_USB_WAKEUP (IRQ_SHPI_START + 20) +#define IRQ_DB5500_I2C0 (IRQ_SHPI_START + 21) +#define IRQ_DB5500_I2C1 (IRQ_SHPI_START + 22) +#define IRQ_DB5500_USBOTG (IRQ_SHPI_START + 23) +#define IRQ_DB5500_DMA_SECURE (IRQ_SHPI_START + 24) +#define IRQ_DB5500_DMA (IRQ_SHPI_START + 25) +#define IRQ_DB5500_UART2 (IRQ_SHPI_START + 26) +#define IRQ_DB5500_ICN_PMU1 (IRQ_SHPI_START + 27) +#define IRQ_DB5500_ICN_PMU2 (IRQ_SHPI_START + 28) +#define IRQ_DB5500_UART3 (IRQ_SHPI_START + 29) +#define IRQ_DB5500_SPI3 (IRQ_SHPI_START + 30) +#define IRQ_DB5500_SDMMC4 (IRQ_SHPI_START + 31) +#define IRQ_DB5500_IRRC (IRQ_SHPI_START + 33) +#define IRQ_DB5500_IRDA_FT (IRQ_SHPI_START + 34) +#define IRQ_DB5500_IRDA_SD (IRQ_SHPI_START + 35) +#define IRQ_DB5500_IRDA_FI (IRQ_SHPI_START + 36) +#define IRQ_DB5500_IRDA_FD (IRQ_SHPI_START + 37) +#define IRQ_DB5500_FSMC_CODEREADY (IRQ_SHPI_START + 38) +#define IRQ_DB5500_FSMC_NANDWAIT (IRQ_SHPI_START + 39) +#define IRQ_DB5500_AB5500 (IRQ_SHPI_START + 40) +#define IRQ_DB5500_SDMMC2 (IRQ_SHPI_START + 41) +#define IRQ_DB5500_SIA (IRQ_SHPI_START + 42) +#define IRQ_DB5500_SIA2 (IRQ_SHPI_START + 43) +#define IRQ_DB5500_HVA (IRQ_SHPI_START + 44) +#define IRQ_DB5500_HVA2 (IRQ_SHPI_START + 45) +#define IRQ_DB5500_PRCMU0 (IRQ_SHPI_START + 46) +#define IRQ_DB5500_PRCMU1 (IRQ_SHPI_START + 47) +#define IRQ_DB5500_DISP (IRQ_SHPI_START + 48) +#define IRQ_DB5500_SDMMC1 (IRQ_SHPI_START + 50) +#define IRQ_DB5500_MSP1 (IRQ_SHPI_START + 52) +#define IRQ_DB5500_KBD (IRQ_SHPI_START + 53) +#define IRQ_DB5500_I2C2 (IRQ_SHPI_START + 55) +#define IRQ_DB5500_B2R2 (IRQ_SHPI_START + 56) +#define IRQ_DB5500_CRYP0 (IRQ_SHPI_START + 57) +#define IRQ_DB5500_SDMMC3 (IRQ_SHPI_START + 59) +#define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60) +#define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61) +#define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63) +#define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96) +#define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98) +#define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101) +#define IRQ_DB5500_CTI0 (IRQ_SHPI_START + 108) +#define IRQ_DB5500_CTI1 (IRQ_SHPI_START + 109) +#define IRQ_DB5500_ICN_ERR (IRQ_SHPI_START + 110) +#define IRQ_DB5500_MALI_PPMMU (IRQ_SHPI_START + 112) +#define IRQ_DB5500_MALI_PP (IRQ_SHPI_START + 113) +#define IRQ_DB5500_MALI_GPMMU (IRQ_SHPI_START + 114) +#define IRQ_DB5500_MALI_GP (IRQ_SHPI_START + 115) +#define IRQ_DB5500_MALI (IRQ_SHPI_START + 116) +#define IRQ_DB5500_PRCMU_SEM (IRQ_SHPI_START + 118) +#define IRQ_DB5500_GPIO0 (IRQ_SHPI_START + 119) +#define IRQ_DB5500_GPIO1 (IRQ_SHPI_START + 120) +#define IRQ_DB5500_GPIO2 (IRQ_SHPI_START + 121) +#define IRQ_DB5500_GPIO3 (IRQ_SHPI_START + 122) +#define IRQ_DB5500_GPIO4 (IRQ_SHPI_START + 123) +#define IRQ_DB5500_GPIO5 (IRQ_SHPI_START + 124) +#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125) +#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126) + +#endif diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/include/mach/irqs-db8500.h new file mode 100644 index 000000000000..8b5d9f0a1633 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/irqs-db8500.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __MACH_IRQS_DB8500_H +#define __MACH_IRQS_DB8500_H + +#define IRQ_DB8500_MTU0 (IRQ_SHPI_START + 4) +#define IRQ_DB8500_SPI2 (IRQ_SHPI_START + 6) +#define IRQ_DB8500_PMU (IRQ_SHPI_START + 7) +#define IRQ_DB8500_SPI0 (IRQ_SHPI_START + 8) +#define IRQ_DB8500_RTT (IRQ_SHPI_START + 9) +#define IRQ_DB8500_PKA (IRQ_SHPI_START + 10) +#define IRQ_DB8500_UART0 (IRQ_SHPI_START + 11) +#define IRQ_DB8500_I2C3 (IRQ_SHPI_START + 12) +#define IRQ_DB8500_L2CC (IRQ_SHPI_START + 13) +#define IRQ_DB8500_SSP0 (IRQ_SHPI_START + 14) +#define IRQ_DB8500_CRYP1 (IRQ_SHPI_START + 15) +#define IRQ_DB8500_MSP1_RX (IRQ_SHPI_START + 16) +#define IRQ_DB8500_MTU1 (IRQ_SHPI_START + 17) +#define IRQ_DB8500_RTC (IRQ_SHPI_START + 18) +#define IRQ_DB8500_UART1 (IRQ_SHPI_START + 19) +#define IRQ_DB8500_USB_WAKEUP (IRQ_SHPI_START + 20) +#define IRQ_DB8500_I2C0 (IRQ_SHPI_START + 21) +#define IRQ_DB8500_I2C1 (IRQ_SHPI_START + 22) +#define IRQ_DB8500_USBOTG (IRQ_SHPI_START + 23) +#define IRQ_DB8500_DMA_SECURE (IRQ_SHPI_START + 24) +#define IRQ_DB8500_DMA (IRQ_SHPI_START + 25) +#define IRQ_DB8500_UART2 (IRQ_SHPI_START + 26) +#define IRQ_DB8500_ICN_PMU1 (IRQ_SHPI_START + 27) +#define IRQ_DB8500_ICN_PMU2 (IRQ_SHPI_START + 28) +#define IRQ_DB8500_HSIR_EXCEP (IRQ_SHPI_START + 29) +#define IRQ_DB8500_MSP0 (IRQ_SHPI_START + 31) +#define IRQ_DB8500_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32) +#define IRQ_DB8500_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33) +#define IRQ_DB8500_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34) +#define IRQ_DB8500_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35) +#define IRQ_DB8500_HSIR_CH4_OVRRUN (IRQ_SHPI_START + 36) +#define IRQ_DB8500_HSIR_CH5_OVRRUN (IRQ_SHPI_START + 37) +#define IRQ_DB8500_HSIR_CH6_OVRRUN (IRQ_SHPI_START + 38) +#define IRQ_DB8500_HSIR_CH7_OVRRUN (IRQ_SHPI_START + 39) +#define IRQ_DB8500_AB8500 (IRQ_SHPI_START + 40) +#define IRQ_DB8500_SDMMC2 (IRQ_SHPI_START + 41) +#define IRQ_DB8500_SIA (IRQ_SHPI_START + 42) +#define IRQ_DB8500_SIA2 (IRQ_SHPI_START + 43) +#define IRQ_DB8500_SVA (IRQ_SHPI_START + 44) +#define IRQ_DB8500_SVA2 (IRQ_SHPI_START + 45) +#define IRQ_DB8500_PRCMU0 (IRQ_SHPI_START + 46) +#define IRQ_DB8500_PRCMU1 (IRQ_SHPI_START + 47) +#define IRQ_DB8500_DISP (IRQ_SHPI_START + 48) +#define IRQ_DB8500_SPI3 (IRQ_SHPI_START + 49) +#define IRQ_DB8500_SDMMC1 (IRQ_SHPI_START + 50) +#define IRQ_DB8500_I2C4 (IRQ_SHPI_START + 51) +#define IRQ_DB8500_SSP1 (IRQ_SHPI_START + 52) +#define IRQ_DB8500_SKE (IRQ_SHPI_START + 53) +#define IRQ_DB8500_KB (IRQ_SHPI_START + 54) +#define IRQ_DB8500_I2C2 (IRQ_SHPI_START + 55) +#define IRQ_DB8500_B2R2 (IRQ_SHPI_START + 56) +#define IRQ_DB8500_CRYP0 (IRQ_SHPI_START + 57) +#define IRQ_DB8500_SDMMC3 (IRQ_SHPI_START + 59) +#define IRQ_DB8500_SDMMC0 (IRQ_SHPI_START + 60) +#define IRQ_DB8500_HSEM (IRQ_SHPI_START + 61) +#define IRQ_DB8500_MSP1 (IRQ_SHPI_START + 62) +#define IRQ_DB8500_SBAG (IRQ_SHPI_START + 63) +#define IRQ_DB8500_SPI1 (IRQ_SHPI_START + 96) +#define IRQ_DB8500_SRPTIMER (IRQ_SHPI_START + 97) +#define IRQ_DB8500_MSP2 (IRQ_SHPI_START + 98) +#define IRQ_DB8500_SDMMC4 (IRQ_SHPI_START + 99) +#define IRQ_DB8500_SDMMC5 (IRQ_SHPI_START + 100) +#define IRQ_DB8500_HSIRD0 (IRQ_SHPI_START + 104) +#define IRQ_DB8500_HSIRD1 (IRQ_SHPI_START + 105) +#define IRQ_DB8500_HSITD0 (IRQ_SHPI_START + 106) +#define IRQ_DB8500_HSITD1 (IRQ_SHPI_START + 107) +#define IRQ_DB8500_CTI0 (IRQ_SHPI_START + 108) +#define IRQ_DB8500_CTI1 (IRQ_SHPI_START + 109) +#define IRQ_DB8500_ICN_ERR (IRQ_SHPI_START + 110) +#define IRQ_DB8500_MALI_PPMMU (IRQ_SHPI_START + 112) +#define IRQ_DB8500_MALI_PP (IRQ_SHPI_START + 113) +#define IRQ_DB8500_MALI_GPMMU (IRQ_SHPI_START + 114) +#define IRQ_DB8500_MALI_GP (IRQ_SHPI_START + 115) +#define IRQ_DB8500_MALI (IRQ_SHPI_START + 116) +#define IRQ_DB8500_PRCMU_SEM (IRQ_SHPI_START + 118) +#define IRQ_DB8500_GPIO0 (IRQ_SHPI_START + 119) +#define IRQ_DB8500_GPIO1 (IRQ_SHPI_START + 120) +#define IRQ_DB8500_GPIO2 (IRQ_SHPI_START + 121) +#define IRQ_DB8500_GPIO3 (IRQ_SHPI_START + 122) +#define IRQ_DB8500_GPIO4 (IRQ_SHPI_START + 123) +#define IRQ_DB8500_GPIO5 (IRQ_SHPI_START + 124) +#define IRQ_DB8500_GPIO6 (IRQ_SHPI_START + 125) +#define IRQ_DB8500_GPIO7 (IRQ_SHPI_START + 126) +#define IRQ_DB8500_GPIO8 (IRQ_SHPI_START + 127) + +#endif diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h index 7970684b1d09..10385bdc2b77 100644 --- a/arch/arm/mach-ux500/include/mach/irqs.h +++ b/arch/arm/mach-ux500/include/mach/irqs.h @@ -10,7 +10,8 @@ #ifndef ASM_ARCH_IRQS_H #define ASM_ARCH_IRQS_H -#include <mach/hardware.h> +#include <mach/irqs-db5500.h> +#include <mach/irqs-db8500.h> #define IRQ_LOCALTIMER 29 #define IRQ_LOCALWDOG 30 @@ -67,12 +68,21 @@ /* There are 128 shared peripheral interrupts assigned to * INTID[160:32]. The first 32 interrupts are reserved. */ -#define U8500_SOC_NR_IRQS 161 +#define DBX500_NR_INTERNAL_IRQS 161 /* After chip-specific IRQ numbers we have the GPIO ones */ #define NOMADIK_NR_GPIO 288 -#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + U8500_SOC_NR_IRQS) -#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - U8500_SOC_NR_IRQS) -#define NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) +#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + DBX500_NR_INTERNAL_IRQS) +#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - DBX500_NR_INTERNAL_IRQS) +#define IRQ_BOARD_START NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) -#endif /*ASM_ARCH_IRQS_H*/ +/* This will be overridden by board-specific irq headers */ +#define IRQ_BOARD_END IRQ_BOARD_START + +#ifdef CONFIG_MACH_U8500_MOP +#include <mach/irqs-board-mop500.h> +#endif + +#define NR_IRQS IRQ_BOARD_END + +#endif /* ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h index 8552eb188b50..0271ca0a83df 100644 --- a/arch/arm/mach-ux500/include/mach/uncompress.h +++ b/arch/arm/mach-ux500/include/mach/uncompress.h @@ -30,22 +30,22 @@ static void putc(const char c) { /* Do nothing if the UART is not enabled. */ - if (!(readb(U8500_UART_CR) & 0x1)) + if (!(__raw_readb(U8500_UART_CR) & 0x1)) return; if (c == '\n') putc('\r'); - while (readb(U8500_UART_FR) & (1 << 5)) + while (__raw_readb(U8500_UART_FR) & (1 << 5)) barrier(); - writeb(c, U8500_UART_DR); + __raw_writeb(c, U8500_UART_DR); } static void flush(void) { - if (!(readb(U8500_UART_CR) & 0x1)) + if (!(__raw_readb(U8500_UART_CR) & 0x1)) return; - while (readb(U8500_UART_FR) & (1 << 3)) + while (__raw_readb(U8500_UART_FR) & (1 << 3)) barrier(); } diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h new file mode 100644 index 000000000000..9055d5d3233c --- /dev/null +++ b/arch/arm/mach-ux500/pins-db8500.h @@ -0,0 +1,742 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License terms: GNU General Public License, version 2 + * Author: Rabin Vincent <rabin.vincent@stericsson.com> + */ + +#ifndef __MACH_PINS_DB8500_H +#define __MACH_PINS_DB8500_H + +/* + * TODO: Eventually encode all non-board specific pull up/down configuration + * here. + */ + +#define GPIO0_GPIO PIN_CFG(0, GPIO) +#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A) +#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B) +#define GPIO0_IP_TDO PIN_CFG(0, ALT_C) + +#define GPIO1_GPIO PIN_CFG(1, GPIO) +#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A) +#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B) +#define GPIO1_IP_TDI PIN_CFG(1, ALT_C) + +#define GPIO2_GPIO PIN_CFG(2, GPIO) +#define GPIO2_U0_RXD PIN_CFG(2, ALT_A) +#define GPIO2_NONE PIN_CFG(2, ALT_B) +#define GPIO2_IP_TMS PIN_CFG(2, ALT_C) + +#define GPIO3_GPIO PIN_CFG(3, GPIO) +#define GPIO3_U0_TXD PIN_CFG(3, ALT_A) +#define GPIO3_NONE PIN_CFG(3, ALT_B) +#define GPIO3_IP_TCK PIN_CFG(3, ALT_C) + +#define GPIO4_GPIO PIN_CFG(4, GPIO) +#define GPIO4_U1_RXD PIN_CFG(4, ALT_A) +#define GPIO4_I2C4_SCL PIN_CFG_PULL(4, ALT_B, UP) +#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C) + +#define GPIO5_GPIO PIN_CFG(5, GPIO) +#define GPIO5_U1_TXD PIN_CFG(5, ALT_A) +#define GPIO5_I2C4_SDA PIN_CFG_PULL(5, ALT_B, UP) +#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C) + +#define GPIO6_GPIO PIN_CFG(6, GPIO) +#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A) +#define GPIO6_I2C1_SCL PIN_CFG_PULL(6, ALT_B, UP) +#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C) + +#define GPIO7_GPIO PIN_CFG(7, GPIO) +#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A) +#define GPIO7_I2C1_SDA PIN_CFG_PULL(7, ALT_B, UP) +#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C) + +#define GPIO8_GPIO PIN_CFG(8, GPIO) +#define GPIO8_IPI2C_SDA PIN_CFG_PULL(8, ALT_A, UP) +#define GPIO8_I2C2_SDA PIN_CFG_PULL(8, ALT_B, UP) + +#define GPIO9_GPIO PIN_CFG(9, GPIO) +#define GPIO9_IPI2C_SCL PIN_CFG_PULL(9, ALT_A, UP) +#define GPIO9_I2C2_SCL PIN_CFG_PULL(9, ALT_B, UP) + +#define GPIO10_GPIO PIN_CFG(10, GPIO) +#define GPIO10_IPI2C_SDA PIN_CFG_PULL(10, ALT_A, UP) +#define GPIO10_I2C2_SDA PIN_CFG_PULL(10, ALT_B, UP) +#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C) + +#define GPIO11_GPIO PIN_CFG(11, GPIO) +#define GPIO11_IPI2C_SCL PIN_CFG_PULL(11, ALT_A, UP) +#define GPIO11_I2C2_SCL PIN_CFG_PULL(11, ALT_B, UP) +#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C) + +#define GPIO12_GPIO PIN_CFG(12, GPIO) +#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A) +#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B) + +#define GPIO13_GPIO PIN_CFG(13, GPIO) +#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A) + +#define GPIO14_GPIO PIN_CFG(14, GPIO) +#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A) + +#define GPIO15_GPIO PIN_CFG(15, GPIO) +#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A) +#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B) + +#define GPIO16_GPIO PIN_CFG(16, GPIO) +#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A) +#define GPIO16_I2C1_SCL PIN_CFG_PULL(16, ALT_B, UP) +#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C) + +#define GPIO17_GPIO PIN_CFG(17, GPIO) +#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A) +#define GPIO17_I2C1_SDA PIN_CFG_PULL(17, ALT_B, UP) +#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) + +#define GPIO18_GPIO PIN_CFG(18, GPIO) +#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A) +#define GPIO18_U2_RXD PIN_CFG(18, ALT_B) +#define GPIO18_MS_IEP PIN_CFG(18, ALT_C) + +#define GPIO19_GPIO PIN_CFG(19, GPIO) +#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A) +#define GPIO19_U2_TXD PIN_CFG(19, ALT_B) +#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C) + +#define GPIO20_GPIO PIN_CFG(20, GPIO) +#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A) +#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B) +#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C) + +#define GPIO21_GPIO PIN_CFG(21, GPIO) +#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A) +#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B) +#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C) + +#define GPIO22_GPIO PIN_CFG(22, GPIO) +#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A) +#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B) +#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C) + +#define GPIO23_GPIO PIN_CFG(23, GPIO) +#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A) +#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B) +#define GPIO23_MS_CLK PIN_CFG(23, ALT_C) + +#define GPIO24_GPIO PIN_CFG(24, GPIO) +#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A) +#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B) +#define GPIO24_MS_BS PIN_CFG(24, ALT_C) + +#define GPIO25_GPIO PIN_CFG(25, GPIO) +#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A) +#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B) +#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C) + +#define GPIO26_GPIO PIN_CFG(26, GPIO) +#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A) +#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B) +#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C) + +#define GPIO27_GPIO PIN_CFG(27, GPIO) +#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A) +#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B) +#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C) + +#define GPIO28_GPIO PIN_CFG(28, GPIO) +#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A) +#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B) +#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C) + +#define GPIO29_GPIO PIN_CFG(29, GPIO) +#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A) +#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B) +#define GPIO29_U2_RXD PIN_CFG(29, ALT_C) + +#define GPIO30_GPIO PIN_CFG(30, GPIO) +#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A) +#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B) +#define GPIO30_U2_TXD PIN_CFG(30, ALT_C) + +#define GPIO31_GPIO PIN_CFG(31, GPIO) +#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A) +#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B) +#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C) + +#define GPIO32_GPIO PIN_CFG(32, GPIO) +#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A) +#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B) +#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C) + +#define GPIO33_GPIO PIN_CFG(33, GPIO) +#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A) +#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B) +#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C) + +#define GPIO34_GPIO PIN_CFG(34, GPIO) +#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A) +#define GPIO34_NONE PIN_CFG(34, ALT_B) +#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C) + +#define GPIO35_GPIO PIN_CFG(35, GPIO) +#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A) +#define GPIO35_NONE PIN_CFG(35, ALT_B) +#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C) + +#define GPIO36_GPIO PIN_CFG(36, GPIO) +#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A) +#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B) +#define GPIO36_U0_RIn PIN_CFG(36, ALT_C) + +#define GPIO64_GPIO PIN_CFG(64, GPIO) +#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A) +#define GPIO64_KP_O1 PIN_CFG(64, ALT_B) +#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C) + +#define GPIO65_GPIO PIN_CFG(65, GPIO) +#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A) +#define GPIO65_KP_O0 PIN_CFG(65, ALT_B) +#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C) + +#define GPIO66_GPIO PIN_CFG(66, GPIO) +#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A) +#define GPIO66_KP_I1 PIN_CFG(66, ALT_B) +#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C) + +#define GPIO67_GPIO PIN_CFG(67, GPIO) +#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A) +#define GPIO67_KP_I0 PIN_CFG(67, ALT_B) +#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C) + +#define GPIO68_GPIO PIN_CFG(68, GPIO) +#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A) +#define GPIO68_KP_O7 PIN_CFG(68, ALT_B) +#define GPIO68_SM_CLE PIN_CFG(68, ALT_C) + +#define GPIO69_GPIO PIN_CFG(69, GPIO) +#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A) +#define GPIO69_KP_I7 PIN_CFG(69, ALT_B) +#define GPIO69_SM_ALE PIN_CFG(69, ALT_C) + +#define GPIO70_GPIO PIN_CFG(70, GPIO) +#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A) +#define GPIO70_KP_O5 PIN_CFG(70, ALT_B) +#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C) + +#define GPIO71_GPIO PIN_CFG(71, GPIO) +#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A) +#define GPIO71_KP_O4 PIN_CFG(71, ALT_B) +#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C) + +#define GPIO72_GPIO PIN_CFG(72, GPIO) +#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A) +#define GPIO72_KP_O3 PIN_CFG(72, ALT_B) +#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C) + +#define GPIO73_GPIO PIN_CFG(73, GPIO) +#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A) +#define GPIO73_KP_O2 PIN_CFG(73, ALT_B) +#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C) + +#define GPIO74_GPIO PIN_CFG(74, GPIO) +#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A) +#define GPIO74_KP_I5 PIN_CFG(74, ALT_B) +#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C) + +#define GPIO75_GPIO PIN_CFG(75, GPIO) +#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A) +#define GPIO75_KP_I4 PIN_CFG(75, ALT_B) +#define GPIO75_U2_RXD PIN_CFG(75, ALT_C) + +#define GPIO76_GPIO PIN_CFG(76, GPIO) +#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A) +#define GPIO76_KP_I3 PIN_CFG(76, ALT_B) +#define GPIO76_U2_TXD PIN_CFG(76, ALT_C) + +#define GPIO77_GPIO PIN_CFG(77, GPIO) +#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A) +#define GPIO77_KP_I2 PIN_CFG(77, ALT_B) +#define GPIO77_NONE PIN_CFG(77, ALT_C) + +#define GPIO78_GPIO PIN_CFG(78, GPIO) +#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A) +#define GPIO78_KP_O6 PIN_CFG(78, ALT_B) +#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C) + +#define GPIO79_GPIO PIN_CFG(79, GPIO) +#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A) +#define GPIO79_KP_I6 PIN_CFG(79, ALT_B) +#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C) + +#define GPIO80_GPIO PIN_CFG(80, GPIO) +#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A) +#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B) +#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C) + +#define GPIO81_GPIO PIN_CFG(81, GPIO) +#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A) +#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B) +#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C) + +#define GPIO82_GPIO PIN_CFG(82, GPIO) +#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A) +#define GPIO82_KP_O5 PIN_CFG(82, ALT_B) + +#define GPIO83_GPIO PIN_CFG(83, GPIO) +#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A) +#define GPIO83_KP_O4 PIN_CFG(83, ALT_B) + +#define GPIO84_GPIO PIN_CFG(84, GPIO) +#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A) +#define GPIO84_KP_I5 PIN_CFG(84, ALT_B) + +#define GPIO85_GPIO PIN_CFG(85, GPIO) +#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A) +#define GPIO85_KP_I4 PIN_CFG(85, ALT_B) + +#define GPIO86_GPIO PIN_CFG(86, GPIO) +#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A) +#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B) +#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C) + +#define GPIO87_GPIO PIN_CFG(87, GPIO) +#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A) +#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B) +#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C) + +#define GPIO88_GPIO PIN_CFG(88, GPIO) +#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A) +#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B) +#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C) + +#define GPIO89_GPIO PIN_CFG(89, GPIO) +#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A) +#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B) +#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C) + +#define GPIO90_GPIO PIN_CFG(90, GPIO) +#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A) +#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B) +#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C) + +#define GPIO91_GPIO PIN_CFG(91, GPIO) +#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A) +#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B) +#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C) + +#define GPIO92_GPIO PIN_CFG(92, GPIO) +#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A) +#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B) +#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C) + +#define GPIO93_GPIO PIN_CFG(93, GPIO) +#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A) +#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B) +#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C) + +#define GPIO94_GPIO PIN_CFG(94, GPIO) +#define GPIO94_KP_O7 PIN_CFG(94, ALT_A) +#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B) +#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C) + +#define GPIO95_GPIO PIN_CFG(95, GPIO) +#define GPIO95_KP_I7 PIN_CFG(95, ALT_A) +#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B) +#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C) + +#define GPIO96_GPIO PIN_CFG(96, GPIO) +#define GPIO96_KP_O6 PIN_CFG(96, ALT_A) +#define GPIO96_SM_OEn PIN_CFG(96, ALT_B) +#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C) + +#define GPIO97_GPIO PIN_CFG(97, GPIO) +#define GPIO97_KP_I6 PIN_CFG(97, ALT_A) +#define GPIO97_SM_WEn PIN_CFG(97, ALT_B) +#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C) + +#define GPIO128_GPIO PIN_CFG(128, GPIO) +#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A) +#define GPIO128_SM_CKO PIN_CFG(128, ALT_B) + +#define GPIO129_GPIO PIN_CFG(129, GPIO) +#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A) +#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B) + +#define GPIO130_GPIO PIN_CFG(130, GPIO) +#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A) +#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B) +#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C) + +#define GPIO131_GPIO PIN_CFG(131, GPIO) +#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A) +#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B) + +#define GPIO132_GPIO PIN_CFG(132, GPIO) +#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A) +#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B) + +#define GPIO133_GPIO PIN_CFG(133, GPIO) +#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A) +#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B) + +#define GPIO134_GPIO PIN_CFG(134, GPIO) +#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A) +#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B) + +#define GPIO135_GPIO PIN_CFG(135, GPIO) +#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A) +#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B) + +#define GPIO136_GPIO PIN_CFG(136, GPIO) +#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A) +#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B) + +#define GPIO137_GPIO PIN_CFG(137, GPIO) +#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A) +#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B) + +#define GPIO138_GPIO PIN_CFG(138, GPIO) +#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A) +#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B) + +#define GPIO139_GPIO PIN_CFG(139, GPIO) +#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A) +#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B) +#define GPIO139_KP_O8 PIN_CFG(139, ALT_C) + +#define GPIO140_GPIO PIN_CFG(140, GPIO) +#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A) +#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B) +#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C) + +#define GPIO141_GPIO PIN_CFG(141, GPIO) +#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A) +#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B) +#define GPIO141_KP_O9 PIN_CFG(141, ALT_C) + +#define GPIO142_GPIO PIN_CFG(142, GPIO) +#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A) +#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B) +#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C) + +#define GPIO143_GPIO PIN_CFG(143, GPIO) +#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A) + +#define GPIO144_GPIO PIN_CFG(144, GPIO) +#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A) + +#define GPIO145_GPIO PIN_CFG(145, GPIO) +#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A) + +#define GPIO146_GPIO PIN_CFG(146, GPIO) +#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A) + +#define GPIO147_GPIO PIN_CFG(147, GPIO) +#define GPIO147_I2C0_SCL PIN_CFG_PULL(147, ALT_A, UP) + +#define GPIO148_GPIO PIN_CFG(148, GPIO) +#define GPIO148_I2C0_SDA PIN_CFG_PULL(148, ALT_A, UP) + +#define GPIO149_GPIO PIN_CFG(149, GPIO) +#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A) +#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B) +#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C) + +#define GPIO150_GPIO PIN_CFG(150, GPIO) +#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A) +#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B) + +#define GPIO151_GPIO PIN_CFG(151, GPIO) +#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A) +#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B) +#define GPIO151_KP_O8 PIN_CFG(151, ALT_C) + +#define GPIO152_GPIO PIN_CFG(152, GPIO) +#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A) +#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B) +#define GPIO152_KP_O9 PIN_CFG(152, ALT_C) + +#define GPIO153_GPIO PIN_CFG(153, GPIO) +#define GPIO153_KP_I7 PIN_CFG(153, ALT_A) +#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) +#define GPIO153_U2_RXD PIN_CFG(153, ALT_C) + +#define GPIO154_GPIO PIN_CFG(154, GPIO) +#define GPIO154_KP_I6 PIN_CFG(154, ALT_A) +#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) +#define GPIO154_U2_TXD PIN_CFG(154, ALT_C) + +#define GPIO155_GPIO PIN_CFG(155, GPIO) +#define GPIO155_KP_I5 PIN_CFG(155, ALT_A) +#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) +#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) + +#define GPIO156_GPIO PIN_CFG(156, GPIO) +#define GPIO156_KP_I4 PIN_CFG(156, ALT_A) +#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) +#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) + +#define GPIO157_GPIO PIN_CFG(157, GPIO) +#define GPIO157_KP_O7 PIN_CFG(157, ALT_A) +#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) +#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) + +#define GPIO158_GPIO PIN_CFG(158, GPIO) +#define GPIO158_KP_O6 PIN_CFG(158, ALT_A) +#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) +#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) + +#define GPIO159_GPIO PIN_CFG(159, GPIO) +#define GPIO159_KP_O5 PIN_CFG(159, ALT_A) +#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) +#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) + +#define GPIO160_GPIO PIN_CFG(160, GPIO) +#define GPIO160_KP_O4 PIN_CFG(160, ALT_A) +#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) +#define GPIO160_NONE PIN_CFG(160, ALT_C) + +#define GPIO161_GPIO PIN_CFG(161, GPIO) +#define GPIO161_KP_I3 PIN_CFG(161, ALT_A) +#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) +#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) + +#define GPIO162_GPIO PIN_CFG(162, GPIO) +#define GPIO162_KP_I2 PIN_CFG(162, ALT_A) +#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) +#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) + +#define GPIO163_GPIO PIN_CFG(163, GPIO) +#define GPIO163_KP_I1 PIN_CFG(163, ALT_A) +#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) +#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) + +#define GPIO164_GPIO PIN_CFG(164, GPIO) +#define GPIO164_KP_I0 PIN_CFG(164, ALT_A) +#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) +#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) + +#define GPIO165_GPIO PIN_CFG(165, GPIO) +#define GPIO165_KP_O3 PIN_CFG(165, ALT_A) +#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) +#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) + +#define GPIO166_GPIO PIN_CFG(166, GPIO) +#define GPIO166_KP_O2 PIN_CFG(166, ALT_A) +#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) +#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) + +#define GPIO167_GPIO PIN_CFG(167, GPIO) +#define GPIO167_KP_O1 PIN_CFG(167, ALT_A) +#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) +#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) + +#define GPIO168_GPIO PIN_CFG(168, GPIO) +#define GPIO168_KP_O0 PIN_CFG(168, ALT_A) +#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) +#define GPIO168_NONE PIN_CFG(168, ALT_C) + +#define GPIO169_GPIO PIN_CFG(169, GPIO) +#define GPIO169_RF_PURn PIN_CFG(169, ALT_A) +#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B) +#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C) + +#define GPIO170_GPIO PIN_CFG(170, GPIO) +#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A) +#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B) +#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C) + +#define GPIO171_GPIO PIN_CFG(171, GPIO) +#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A) +#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B) +#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C) + +#define GPIO192_GPIO PIN_CFG(192, GPIO) +#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A) + +#define GPIO193_GPIO PIN_CFG(193, GPIO) +#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A) + +#define GPIO194_GPIO PIN_CFG(194, GPIO) +#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A) + +#define GPIO195_GPIO PIN_CFG(195, GPIO) +#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A) + +#define GPIO196_GPIO PIN_CFG(196, GPIO) +#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A) + +#define GPIO197_GPIO PIN_CFG(197, GPIO) +#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A) + +#define GPIO198_GPIO PIN_CFG(198, GPIO) +#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A) + +#define GPIO199_GPIO PIN_CFG(199, GPIO) +#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A) + +#define GPIO200_GPIO PIN_CFG(200, GPIO) +#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A) + +#define GPIO201_GPIO PIN_CFG(201, GPIO) +#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A) + +#define GPIO202_GPIO PIN_CFG(202, GPIO) +#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A) +#define GPIO202_PWL PIN_CFG(202, ALT_B) +#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C) + +#define GPIO203_GPIO PIN_CFG(203, GPIO) +#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A) + +#define GPIO204_GPIO PIN_CFG(204, GPIO) +#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A) + +#define GPIO205_GPIO PIN_CFG(205, GPIO) +#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A) + +#define GPIO206_GPIO PIN_CFG(206, GPIO) +#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A) + +#define GPIO207_GPIO PIN_CFG(207, GPIO) +#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A) + +#define GPIO208_GPIO PIN_CFG(208, GPIO) +#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A) + +#define GPIO209_GPIO PIN_CFG(209, GPIO) +#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A) +#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B) + +#define GPIO210_GPIO PIN_CFG(210, GPIO) +#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A) + +#define GPIO211_GPIO PIN_CFG(211, GPIO) +#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A) + +#define GPIO212_GPIO PIN_CFG(212, GPIO) +#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A) +#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B) + +#define GPIO213_GPIO PIN_CFG(213, GPIO) +#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A) +#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B) + +#define GPIO214_GPIO PIN_CFG(214, GPIO) +#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A) +#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B) + +#define GPIO215_GPIO PIN_CFG(215, GPIO) +#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A) +#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B) +#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C) + +#define GPIO216_GPIO PIN_CFG(216, GPIO) +#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A) +#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B) +#define GPIO216_I2C3_SDA PIN_CFG_PULL(216, ALT_C, UP) + +#define GPIO217_GPIO PIN_CFG(217, GPIO) +#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A) +#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B) +#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C) + +#define GPIO218_GPIO PIN_CFG(218, GPIO) +#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A) +#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B) +#define GPIO218_I2C3_SCL PIN_CFG_PULL(218, ALT_C, UP) + +#define GPIO219_GPIO PIN_CFG(219, GPIO) +#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A) +#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B) + +#define GPIO220_GPIO PIN_CFG(220, GPIO) +#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A) +#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B) +#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C) + +#define GPIO221_GPIO PIN_CFG(221, GPIO) +#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A) +#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B) + +#define GPIO222_GPIO PIN_CFG(222, GPIO) +#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A) +#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B) + +#define GPIO223_GPIO PIN_CFG(223, GPIO) +#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A) +#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B) +#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C) + +#define GPIO224_GPIO PIN_CFG(224, GPIO) +#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A) +#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B) +#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C) + +#define GPIO225_GPIO PIN_CFG(225, GPIO) +#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A) +#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B) +#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C) + +#define GPIO226_GPIO PIN_CFG(226, GPIO) +#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A) +#define GPIO226_PWL PIN_CFG(226, ALT_B) +#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C) + +#define GPIO227_GPIO PIN_CFG(227, GPIO) +#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A) + +#define GPIO228_GPIO PIN_CFG(228, GPIO) +#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A) + +#define GPIO229_GPIO PIN_CFG(229, GPIO) +#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A) +#define GPIO229_PWL PIN_CFG(229, ALT_B) +#define GPIO229_I2C3_SDA PIN_CFG_PULL(229, ALT_C, UP) + +#define GPIO230_GPIO PIN_CFG(230, GPIO) +#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A) +#define GPIO230_PWL PIN_CFG(230, ALT_B) +#define GPIO230_I2C3_SCL PIN_CFG_PULL(230, ALT_C, UP) + +#define GPIO256_GPIO PIN_CFG(256, GPIO) +#define GPIO256_USB_NXT PIN_CFG(256, ALT_A) + +#define GPIO257_GPIO PIN_CFG(257, GPIO) +#define GPIO257_USB_STP PIN_CFG(257, ALT_A) + +#define GPIO258_GPIO PIN_CFG(258, GPIO) +#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A) +#define GPIO258_NONE PIN_CFG(258, ALT_B) +#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C) + +#define GPIO259_GPIO PIN_CFG(259, GPIO) +#define GPIO259_USB_DIR PIN_CFG(259, ALT_A) + +#define GPIO260_GPIO PIN_CFG(260, GPIO) +#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A) + +#define GPIO261_GPIO PIN_CFG(261, GPIO) +#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A) + +#define GPIO262_GPIO PIN_CFG(262, GPIO) +#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A) + +#define GPIO263_GPIO PIN_CFG(263, GPIO) +#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A) + +#define GPIO264_GPIO PIN_CFG(264, GPIO) +#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A) + +#define GPIO265_GPIO PIN_CFG(265, GPIO) +#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A) + +#define GPIO266_GPIO PIN_CFG(266, GPIO) +#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A) + +#define GPIO267_GPIO PIN_CFG(267, GPIO) +#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A) + +#endif diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 3dff8641b03f..e38acb0f89c8 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -28,6 +28,7 @@ #include <linux/amba/clcd.h> #include <linux/amba/pl061.h> #include <linux/amba/mmci.h> +#include <linux/amba/pl022.h> #include <linux/io.h> #include <linux/gfp.h> @@ -354,6 +355,21 @@ static struct mmci_platform_data mmc0_plat_data = { .gpio_cd = -1, }; +static struct resource char_lcd_resources[] = { + { + .start = VERSATILE_CHAR_LCD_BASE, + .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1), + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device char_lcd_device = { + .name = "arm-charlcd", + .id = -1, + .num_resources = ARRAY_SIZE(char_lcd_resources), + .resource = char_lcd_resources, +}; + /* * Clock handling */ @@ -400,8 +416,13 @@ static struct clk ref24_clk = { .rate = 24000000, }; +static struct clk dummy_apb_pclk; + static struct clk_lookup lookups[] = { - { /* UART0 */ + { /* AMBA bus clock */ + .con_id = "apb_pclk", + .clk = &dummy_apb_pclk, + }, { /* UART0 */ .dev_id = "dev:f1", .clk = &ref24_clk, }, { /* UART1 */ @@ -425,6 +446,9 @@ static struct clk_lookup lookups[] = { }, { /* MMC1 */ .dev_id = "fpga:0b", .clk = &ref24_clk, + }, { /* SSP */ + .dev_id = "dev:f4", + .clk = &ref24_clk, }, { /* CLCD */ .dev_id = "dev:20", .clk = &osc4_clk, @@ -703,6 +727,12 @@ static struct pl061_platform_data gpio1_plat_data = { .irq_base = IRQ_GPIO1_START, }; +static struct pl022_ssp_controller ssp0_plat_data = { + .bus_id = 0, + .enable_dma = 0, + .num_chipselect = 1, +}; + #define AACI_IRQ { IRQ_AACI, NO_IRQ } #define AACI_DMA { 0x80, 0x81 } #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B } @@ -772,7 +802,7 @@ AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); AMBA_DEVICE(uart1, "dev:f2", UART1, NULL); AMBA_DEVICE(uart2, "dev:f3", UART2, NULL); -AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL); +AMBA_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data); static struct amba_device *amba_devs[] __initdata = { &dmac_device, @@ -843,6 +873,7 @@ void __init versatile_init(void) platform_device_register(&versatile_flash_device); platform_device_register(&versatile_i2c_device); platform_device_register(&smc91x_device); + platform_device_register(&char_lcd_device); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c index 334f0df4e948..13c7e5f90a82 100644 --- a/arch/arm/mach-versatile/pci.c +++ b/arch/arm/mach-versatile/pci.c @@ -304,7 +304,7 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys) } -struct pci_bus *pci_versatile_scan_bus(int nr, struct pci_sys_data *sys) +struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys) { return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys); } diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index 6353459bb567..577df6cccb08 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c @@ -16,6 +16,7 @@ #include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/pmu.h> +#include <asm/smp_twd.h> #include <mach/clkdev.h> #include <mach/ct-ca9x4.h> @@ -53,6 +54,7 @@ static struct map_desc ct_ca9x4_io_desc[] __initdata = { static void __init ct_ca9x4_map_io(void) { + twd_base = MMIO_P2V(A9_MPCORE_TWD); v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc)); } diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h index 8650f04136ef..f9e2f8d22962 100644 --- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h +++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h @@ -28,6 +28,7 @@ #define A9_MPCORE_SCU (CT_CA9X4_MPIC + 0x0000) #define A9_MPCORE_GIC_CPU (CT_CA9X4_MPIC + 0x0100) #define A9_MPCORE_GIT (CT_CA9X4_MPIC + 0x0200) +#define A9_MPCORE_TWD (CT_CA9X4_MPIC + 0x0600) #define A9_MPCORE_GIC_DIST (CT_CA9X4_MPIC + 0x1000) /* diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index d250711b8c7a..817f0ad38a0b 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -241,7 +241,7 @@ static struct platform_device v2m_flash_device = { static unsigned int v2m_mmci_status(struct device *dev) { - return !(readl(MMIO_P2V(V2M_SYS_MCI)) & (1 << 0)); + return readl(MMIO_P2V(V2M_SYS_MCI)) & (1 << 0); } static struct mmci_platform_data v2m_mmci_data = { @@ -298,8 +298,13 @@ static struct clk osc2_clk = { .rate = 24000000, }; +static struct clk dummy_apb_pclk; + static struct clk_lookup v2m_lookups[] = { - { /* UART0 */ + { /* AMBA bus clock */ + .con_id = "apb_pclk", + .clk = &dummy_apb_pclk, + }, { /* UART0 */ .dev_id = "mb:uart0", .clk = &osc2_clk, }, { /* UART1 */ diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c index b2eda4dc1c34..7a1fa6adb7c3 100644 --- a/arch/arm/mach-w90x900/dev.c +++ b/arch/arm/mach-w90x900/dev.c @@ -36,6 +36,8 @@ #include <mach/nuc900_spi.h> #include <mach/map.h> #include <mach/fb.h> +#include <mach/regs-ldm.h> +#include <mach/w90p910_keypad.h> #include "cpu.h" @@ -207,7 +209,7 @@ static struct nuc900_spi_info nuc900_spiflash_data = { .divider = 24, .sleep = 0, .txnum = 0, - .txbitlen = 1, + .txbitlen = 8, .bus_num = 0, }; @@ -256,7 +258,7 @@ static struct spi_board_info nuc900_spi_board_info[] __initdata = { .modalias = "m25p80", .max_speed_hz = 20000000, .bus_num = 0, - .chip_select = 1, + .chip_select = 0, .platform_data = &nuc900_spi_flash_data, .mode = SPI_MODE_0, }, @@ -361,6 +363,39 @@ struct platform_device nuc900_device_fmi = { /* KPI controller*/ +static int nuc900_keymap[] = { + KEY(0, 0, KEY_A), + KEY(0, 1, KEY_B), + KEY(0, 2, KEY_C), + KEY(0, 3, KEY_D), + + KEY(1, 0, KEY_E), + KEY(1, 1, KEY_F), + KEY(1, 2, KEY_G), + KEY(1, 3, KEY_H), + + KEY(2, 0, KEY_I), + KEY(2, 1, KEY_J), + KEY(2, 2, KEY_K), + KEY(2, 3, KEY_L), + + KEY(3, 0, KEY_M), + KEY(3, 1, KEY_N), + KEY(3, 2, KEY_O), + KEY(3, 3, KEY_P), +}; + +static struct matrix_keymap_data nuc900_map_data = { + .keymap = nuc900_keymap, + .keymap_size = ARRAY_SIZE(nuc900_keymap), +}; + +struct w90p910_keypad_platform_data nuc900_keypad_info = { + .keymap_data = &nuc900_map_data, + .prescale = 0xfa, + .debounce = 0x50, +}; + static struct resource nuc900_kpi_resource[] = { [0] = { .start = W90X900_PA_KPI, @@ -380,9 +415,49 @@ struct platform_device nuc900_device_kpi = { .id = -1, .num_resources = ARRAY_SIZE(nuc900_kpi_resource), .resource = nuc900_kpi_resource, + .dev = { + .platform_data = &nuc900_keypad_info, + } }; -#ifdef CONFIG_FB_NUC900 +/* LCD controller*/ + +static struct nuc900fb_display __initdata nuc900_lcd_info[] = { + /* Giantplus Technology GPM1040A0 320x240 Color TFT LCD */ + [0] = { + .type = LCM_DCCS_VA_SRC_RGB565, + .width = 320, + .height = 240, + .xres = 320, + .yres = 240, + .bpp = 16, + .pixclock = 200000, + .left_margin = 34, + .right_margin = 54, + .hsync_len = 10, + .upper_margin = 18, + .lower_margin = 4, + .vsync_len = 1, + .dccs = 0x8e00041a, + .devctl = 0x060800c0, + .fbctrl = 0x00a000a0, + .scale = 0x04000400, + }, +}; + +static struct nuc900fb_mach_info nuc900_fb_info __initdata = { +#if defined(CONFIG_GPM1040A0_320X240) + .displays = &nuc900_lcd_info[0], +#else + .displays = nuc900_lcd_info, +#endif + .num_displays = ARRAY_SIZE(nuc900_lcd_info), + .default_display = 0, + .gpio_dir = 0x00000004, + .gpio_dir_mask = 0xFFFFFFFD, + .gpio_data = 0x00000004, + .gpio_data_mask = 0xFFFFFFFD, +}; static struct resource nuc900_lcd_resource[] = { [0] = { @@ -406,23 +481,10 @@ struct platform_device nuc900_device_lcd = { .dev = { .dma_mask = &nuc900_device_lcd_dmamask, .coherent_dma_mask = -1, + .platform_data = &nuc900_fb_info, } }; -void nuc900_fb_set_platdata(struct nuc900fb_mach_info *pd) -{ - struct nuc900fb_mach_info *npd; - - npd = kmalloc(sizeof(*npd), GFP_KERNEL); - if (npd) { - memcpy(npd, pd, sizeof(*npd)); - nuc900_device_lcd.dev.platform_data = npd; - } else { - printk(KERN_ERR "no memory for LCD platform data\n"); - } -} -#endif - /* AUDIO controller*/ static u64 nuc900_device_audio_dmamask = -1; static struct resource nuc900_ac97_resource[] = { diff --git a/arch/arm/mach-w90x900/include/mach/regs-gcr.h b/arch/arm/mach-w90x900/include/mach/regs-gcr.h new file mode 100644 index 000000000000..6087abd93ef5 --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/regs-gcr.h @@ -0,0 +1,39 @@ +/* + * arch/arm/mach-w90x900/include/mach/regs-gcr.h + * + * Copyright (c) 2010 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_REGS_GCR_H +#define __ASM_ARCH_REGS_GCR_H + +/* Global control registers */ + +#define GCR_BA W90X900_VA_GCR +#define REG_PDID (GCR_BA+0x000) +#define REG_PWRON (GCR_BA+0x004) +#define REG_ARBCON (GCR_BA+0x008) +#define REG_MFSEL (GCR_BA+0x00C) +#define REG_EBIDPE (GCR_BA+0x010) +#define REG_LCDDPE (GCR_BA+0x014) +#define REG_GPIOCPE (GCR_BA+0x018) +#define REG_GPIODPE (GCR_BA+0x01C) +#define REG_GPIOEPE (GCR_BA+0x020) +#define REG_GPIOFPE (GCR_BA+0x024) +#define REG_GPIOGPE (GCR_BA+0x028) +#define REG_GPIOHPE (GCR_BA+0x02C) +#define REG_GPIOIPE (GCR_BA+0x030) +#define REG_GTMP1 (GCR_BA+0x034) +#define REG_GTMP2 (GCR_BA+0x038) +#define REG_GTMP3 (GCR_BA+0x03C) + +#endif /* __ASM_ARCH_REGS_GCR_H */ diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c index b3edc3cccf52..04d295f89eb0 100644 --- a/arch/arm/mach-w90x900/mach-nuc950evb.c +++ b/arch/arm/mach-w90x900/mach-nuc950evb.c @@ -20,51 +20,10 @@ #include <asm/mach/map.h> #include <asm/mach-types.h> #include <mach/map.h> -#include <mach/regs-ldm.h> #include <mach/fb.h> #include "nuc950.h" -#ifdef CONFIG_FB_NUC900 -/* LCD Controller */ -static struct nuc900fb_display __initdata nuc950_lcd_info[] = { - /* Giantplus Technology GPM1040A0 320x240 Color TFT LCD */ - [0] = { - .type = LCM_DCCS_VA_SRC_RGB565, - .width = 320, - .height = 240, - .xres = 320, - .yres = 240, - .bpp = 16, - .pixclock = 200000, - .left_margin = 34, - .right_margin = 54, - .hsync_len = 10, - .upper_margin = 18, - .lower_margin = 4, - .vsync_len = 1, - .dccs = 0x8e00041a, - .devctl = 0x060800c0, - .fbctrl = 0x00a000a0, - .scale = 0x04000400, - }, -}; - -static struct nuc900fb_mach_info nuc950_fb_info __initdata = { -#if defined(CONFIG_GPM1040A0_320X240) - .displays = &nuc950_lcd_info[0], -#else - .displays = nuc950_lcd_info, -#endif - .num_displays = ARRAY_SIZE(nuc950_lcd_info), - .default_display = 0, - .gpio_dir = 0x00000004, - .gpio_dir_mask = 0xFFFFFFFD, - .gpio_data = 0x00000004, - .gpio_data_mask = 0xFFFFFFFD, -}; -#endif - static void __init nuc950evb_map_io(void) { nuc950_map_io(); @@ -74,9 +33,6 @@ static void __init nuc950evb_map_io(void) static void __init nuc950evb_init(void) { nuc950_board_init(); -#ifdef CONFIG_FB_NUC900 - nuc900_fb_set_platdata(&nuc950_fb_info); -#endif } MACHINE_START(W90P950EVB, "W90P950EVB") diff --git a/arch/arm/mach-w90x900/nuc910.c b/arch/arm/mach-w90x900/nuc910.c index 656f03b3b629..1523f4136985 100644 --- a/arch/arm/mach-w90x900/nuc910.c +++ b/arch/arm/mach-w90x900/nuc910.c @@ -26,6 +26,8 @@ static struct platform_device *nuc910_dev[] __initdata = { &nuc900_device_ts, &nuc900_device_rtc, + &nuc900_device_lcd, + &nuc900_device_kpi, }; /* define specific CPU platform io map */ diff --git a/arch/arm/mach-w90x900/nuc950.c b/arch/arm/mach-w90x900/nuc950.c index 4d1f1ab044c4..5704f74a50ee 100644 --- a/arch/arm/mach-w90x900/nuc950.c +++ b/arch/arm/mach-w90x900/nuc950.c @@ -26,9 +26,7 @@ static struct platform_device *nuc950_dev[] __initdata = { &nuc900_device_kpi, &nuc900_device_fmi, -#ifdef CONFIG_FB_NUC900 &nuc900_device_lcd, -#endif }; /* define specific CPU platform io map */ diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 101105e52610..87ec141fcaa6 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -717,17 +717,6 @@ config TLS_REG_EMUL a few prototypes like that in existence) and therefore access to that required register must be emulated. -config HAS_TLS_REG - bool - depends on !TLS_REG_EMUL - default y if SMP || CPU_32v7 - help - This selects support for the CP15 thread register. - It is defined to be available on some ARMv6 processors (including - all SMP capable ARMv6's) or later processors. User space may - assume directly accessing that register and always obtain the - expected value only on ARMv7 and above. - config NEEDS_SYSCALL_FOR_CMPXCHG bool help diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index e8d34a80851c..d63b6c413758 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -15,7 +15,6 @@ endif obj-$(CONFIG_MODULES) += proc-syms.o obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o -obj-$(CONFIG_DISCONTIGMEM) += discontig.o obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_CPU_ABRT_NOMMU) += abort-nommu.o diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index 6f98c358989a..d073b64ae87e 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -924,8 +924,20 @@ static int __init alignment_init(void) ai_usermode = UM_FIXUP; } - hook_fault_code(1, do_alignment, SIGILL, "alignment exception"); - hook_fault_code(3, do_alignment, SIGILL, "alignment exception"); + hook_fault_code(1, do_alignment, SIGBUS, BUS_ADRALN, + "alignment exception"); + + /* + * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section + * fault, not as alignment error. + * + * TODO: handle ARMv6K properly. Runtime check for 'K' extension is + * needed. + */ + if (cpu_architecture() <= CPU_ARCH_ARMv6) { + hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN, + "alignment exception"); + } return 0; } diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index df4955885b21..9982eb385c0f 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -32,14 +32,14 @@ static uint32_t l2x0_way_mask; /* Bitmask of active ways */ static inline void cache_wait(void __iomem *reg, unsigned long mask) { /* wait for the operation to complete */ - while (readl(reg) & mask) + while (readl_relaxed(reg) & mask) ; } static inline void cache_sync(void) { void __iomem *base = l2x0_base; - writel(0, base + L2X0_CACHE_SYNC); + writel_relaxed(0, base + L2X0_CACHE_SYNC); cache_wait(base + L2X0_CACHE_SYNC, 1); } @@ -47,14 +47,14 @@ static inline void l2x0_clean_line(unsigned long addr) { void __iomem *base = l2x0_base; cache_wait(base + L2X0_CLEAN_LINE_PA, 1); - writel(addr, base + L2X0_CLEAN_LINE_PA); + writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); } static inline void l2x0_inv_line(unsigned long addr) { void __iomem *base = l2x0_base; cache_wait(base + L2X0_INV_LINE_PA, 1); - writel(addr, base + L2X0_INV_LINE_PA); + writel_relaxed(addr, base + L2X0_INV_LINE_PA); } #ifdef CONFIG_PL310_ERRATA_588369 @@ -75,9 +75,9 @@ static inline void l2x0_flush_line(unsigned long addr) /* Clean by PA followed by Invalidate by PA */ cache_wait(base + L2X0_CLEAN_LINE_PA, 1); - writel(addr, base + L2X0_CLEAN_LINE_PA); + writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); cache_wait(base + L2X0_INV_LINE_PA, 1); - writel(addr, base + L2X0_INV_LINE_PA); + writel_relaxed(addr, base + L2X0_INV_LINE_PA); } #else @@ -90,7 +90,7 @@ static inline void l2x0_flush_line(unsigned long addr) { void __iomem *base = l2x0_base; cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); - writel(addr, base + L2X0_CLEAN_INV_LINE_PA); + writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA); } #endif @@ -109,7 +109,7 @@ static inline void l2x0_inv_all(void) /* invalidate all ways */ spin_lock_irqsave(&l2x0_lock, flags); - writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); + writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); cache_sync(); spin_unlock_irqrestore(&l2x0_lock, flags); @@ -215,8 +215,8 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) l2x0_base = base; - cache_id = readl(l2x0_base + L2X0_CACHE_ID); - aux = readl(l2x0_base + L2X0_AUX_CTRL); + cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); + aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); aux &= aux_mask; aux |= aux_val; @@ -248,15 +248,15 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) * If you are booting from non-secure mode * accessing the below registers will fault. */ - if (!(readl(l2x0_base + L2X0_CTRL) & 1)) { + if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { /* l2x0 controller is disabled */ - writel(aux, l2x0_base + L2X0_AUX_CTRL); + writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); l2x0_inv_all(); /* enable L2X0 */ - writel(1, l2x0_base + L2X0_CTRL); + writel_relaxed(1, l2x0_base + L2X0_CTRL); } outer_cache.inv_range = l2x0_inv_range; diff --git a/arch/arm/mm/discontig.c b/arch/arm/mm/discontig.c deleted file mode 100644 index c8c0c4b0f0a3..000000000000 --- a/arch/arm/mm/discontig.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * linux/arch/arm/mm/discontig.c - * - * Discontiguous memory support. - * - * Initial code: Copyright (C) 1999-2000 Nicolas Pitre - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/module.h> -#include <linux/mmzone.h> -#include <linux/bootmem.h> - -#if MAX_NUMNODES != 4 && MAX_NUMNODES != 16 -# error Fix Me Please -#endif - -/* - * Our node_data structure for discontiguous memory. - */ - -pg_data_t discontig_node_data[MAX_NUMNODES] = { - { .bdata = &bootmem_node_data[0] }, - { .bdata = &bootmem_node_data[1] }, - { .bdata = &bootmem_node_data[2] }, - { .bdata = &bootmem_node_data[3] }, -#if MAX_NUMNODES == 16 - { .bdata = &bootmem_node_data[4] }, - { .bdata = &bootmem_node_data[5] }, - { .bdata = &bootmem_node_data[6] }, - { .bdata = &bootmem_node_data[7] }, - { .bdata = &bootmem_node_data[8] }, - { .bdata = &bootmem_node_data[9] }, - { .bdata = &bootmem_node_data[10] }, - { .bdata = &bootmem_node_data[11] }, - { .bdata = &bootmem_node_data[12] }, - { .bdata = &bootmem_node_data[13] }, - { .bdata = &bootmem_node_data[14] }, - { .bdata = &bootmem_node_data[15] }, -#endif -}; - -EXPORT_SYMBOL(discontig_node_data); diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 9e7742f0a102..c704eed63c5d 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -183,6 +183,8 @@ static void * __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot) { struct arm_vmregion *c; + size_t align; + int bit; if (!consistent_pte[0]) { printk(KERN_ERR "%s: not initialised\n", __func__); @@ -191,9 +193,20 @@ __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot) } /* + * Align the virtual region allocation - maximum alignment is + * a section size, minimum is a page size. This helps reduce + * fragmentation of the DMA space, and also prevents allocations + * smaller than a section from crossing a section boundary. + */ + bit = fls(size - 1) + 1; + if (bit > SECTION_SHIFT) + bit = SECTION_SHIFT; + align = 1 << bit; + + /* * Allocate a virtual address in the consistent mapping region. */ - c = arm_vmregion_alloc(&consistent_head, size, + c = arm_vmregion_alloc(&consistent_head, align, size, gfp & ~(__GFP_DMA | __GFP_HIGHMEM)); if (c) { pte_t *pte; diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index cbfb2edcf7d1..23b0b03af5ea 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -413,7 +413,16 @@ do_translation_fault(unsigned long addr, unsigned int fsr, pmd_k = pmd_offset(pgd_k, addr); pmd = pmd_offset(pgd, addr); - if (pmd_none(*pmd_k)) + /* + * On ARM one Linux PGD entry contains two hardware entries (see page + * tables layout in pgtable.h). We normally guarantee that we always + * fill both L1 entries. But create_mapping() doesn't follow the rule. + * It can create inidividual L1 entries, so here we have to call + * pmd_none() check for the entry really corresponded to address, not + * for the first of pair. + */ + index = (addr >> SECTION_SHIFT) & 1; + if (pmd_none(pmd_k[index])) goto bad_area; copy_pmd(pmd, pmd_k); @@ -463,15 +472,10 @@ static struct fsr_info { * defines these to be "precise" aborts. */ { do_bad, SIGSEGV, 0, "vector exception" }, - { do_bad, SIGILL, BUS_ADRALN, "alignment exception" }, + { do_bad, SIGBUS, BUS_ADRALN, "alignment exception" }, { do_bad, SIGKILL, 0, "terminal exception" }, - { do_bad, SIGILL, BUS_ADRALN, "alignment exception" }, -/* Do we need runtime check ? */ -#if __LINUX_ARM_ARCH__ < 6 + { do_bad, SIGBUS, BUS_ADRALN, "alignment exception" }, { do_bad, SIGBUS, 0, "external abort on linefetch" }, -#else - { do_translation_fault, SIGSEGV, SEGV_MAPERR, "I-cache maintenance fault" }, -#endif { do_translation_fault, SIGSEGV, SEGV_MAPERR, "section translation fault" }, { do_bad, SIGBUS, 0, "external abort on linefetch" }, { do_page_fault, SIGSEGV, SEGV_MAPERR, "page translation fault" }, @@ -508,13 +512,15 @@ static struct fsr_info { void __init hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *), - int sig, const char *name) + int sig, int code, const char *name) { - if (nr >= 0 && nr < ARRAY_SIZE(fsr_info)) { - fsr_info[nr].fn = fn; - fsr_info[nr].sig = sig; - fsr_info[nr].name = name; - } + if (nr < 0 || nr >= ARRAY_SIZE(fsr_info)) + BUG(); + + fsr_info[nr].fn = fn; + fsr_info[nr].sig = sig; + fsr_info[nr].code = code; + fsr_info[nr].name = name; } /* @@ -594,3 +600,25 @@ do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs) arm_notify_die("", regs, &info, ifsr, 0); } +static int __init exceptions_init(void) +{ + if (cpu_architecture() >= CPU_ARCH_ARMv6) { + hook_fault_code(4, do_translation_fault, SIGSEGV, SEGV_MAPERR, + "I-cache maintenance fault"); + } + + if (cpu_architecture() >= CPU_ARCH_ARMv7) { + /* + * TODO: Access flag faults introduced in ARMv6K. + * Runtime check for 'K' extension is needed + */ + hook_fault_code(3, do_bad, SIGSEGV, SEGV_MAPERR, + "section access flag fault"); + hook_fault_code(6, do_bad, SIGSEGV, SEGV_MAPERR, + "section access flag fault"); + } + + return 0; +} + +arch_initcall(exceptions_init); diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c index 086816b205b8..6ab244062b4a 100644 --- a/arch/arm/mm/highmem.c +++ b/arch/arm/mm/highmem.c @@ -163,19 +163,22 @@ static DEFINE_PER_CPU(int, kmap_high_l1_vipt_depth); void *kmap_high_l1_vipt(struct page *page, pte_t *saved_pte) { - unsigned int idx, cpu = smp_processor_id(); - int *depth = &per_cpu(kmap_high_l1_vipt_depth, cpu); + unsigned int idx, cpu; + int *depth; unsigned long vaddr, flags; pte_t pte, *ptep; + if (!in_interrupt()) + preempt_disable(); + + cpu = smp_processor_id(); + depth = &per_cpu(kmap_high_l1_vipt_depth, cpu); + idx = KM_L1_CACHE + KM_TYPE_NR * cpu; vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); ptep = TOP_PTE(vaddr); pte = mk_pte(page, kmap_prot); - if (!in_interrupt()) - preempt_disable(); - raw_local_irq_save(flags); (*depth)++; if (pte_val(*ptep) == pte_val(pte)) { diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index f6a999465323..7185b00650fe 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -17,6 +17,7 @@ #include <linux/initrd.h> #include <linux/highmem.h> #include <linux/gfp.h> +#include <linux/memblock.h> #include <asm/mach-types.h> #include <asm/sections.h> @@ -79,38 +80,37 @@ struct meminfo meminfo; void show_mem(void) { int free = 0, total = 0, reserved = 0; - int shared = 0, cached = 0, slab = 0, node, i; + int shared = 0, cached = 0, slab = 0, i; struct meminfo * mi = &meminfo; printk("Mem-info:\n"); show_free_areas(); - for_each_online_node(node) { - for_each_nodebank (i,mi,node) { - struct membank *bank = &mi->bank[i]; - unsigned int pfn1, pfn2; - struct page *page, *end; - - pfn1 = bank_pfn_start(bank); - pfn2 = bank_pfn_end(bank); - - page = pfn_to_page(pfn1); - end = pfn_to_page(pfn2 - 1) + 1; - - do { - total++; - if (PageReserved(page)) - reserved++; - else if (PageSwapCache(page)) - cached++; - else if (PageSlab(page)) - slab++; - else if (!page_count(page)) - free++; - else - shared += page_count(page) - 1; - page++; - } while (page < end); - } + + for_each_bank (i, mi) { + struct membank *bank = &mi->bank[i]; + unsigned int pfn1, pfn2; + struct page *page, *end; + + pfn1 = bank_pfn_start(bank); + pfn2 = bank_pfn_end(bank); + + page = pfn_to_page(pfn1); + end = pfn_to_page(pfn2 - 1) + 1; + + do { + total++; + if (PageReserved(page)) + reserved++; + else if (PageSwapCache(page)) + cached++; + else if (PageSlab(page)) + slab++; + else if (!page_count(page)) + free++; + else + shared += page_count(page) - 1; + page++; + } while (page < end); } printk("%d pages of RAM\n", total); @@ -121,7 +121,7 @@ void show_mem(void) printk("%d pages swap cached\n", cached); } -static void __init find_node_limits(int node, struct meminfo *mi, +static void __init find_limits(struct meminfo *mi, unsigned long *min, unsigned long *max_low, unsigned long *max_high) { int i; @@ -129,7 +129,7 @@ static void __init find_node_limits(int node, struct meminfo *mi, *min = -1UL; *max_low = *max_high = 0; - for_each_nodebank(i, mi, node) { + for_each_bank (i, mi) { struct membank *bank = &mi->bank[i]; unsigned long start, end; @@ -147,155 +147,64 @@ static void __init find_node_limits(int node, struct meminfo *mi, } } -/* - * FIXME: We really want to avoid allocating the bootmap bitmap - * over the top of the initrd. Hopefully, this is located towards - * the start of a bank, so if we allocate the bootmap bitmap at - * the end, we won't clash. - */ -static unsigned int __init -find_bootmap_pfn(int node, struct meminfo *mi, unsigned int bootmap_pages) -{ - unsigned int start_pfn, i, bootmap_pfn; - - start_pfn = PAGE_ALIGN(__pa(_end)) >> PAGE_SHIFT; - bootmap_pfn = 0; - - for_each_nodebank(i, mi, node) { - struct membank *bank = &mi->bank[i]; - unsigned int start, end; - - start = bank_pfn_start(bank); - end = bank_pfn_end(bank); - - if (end < start_pfn) - continue; - - if (start < start_pfn) - start = start_pfn; - - if (end <= start) - continue; - - if (end - start >= bootmap_pages) { - bootmap_pfn = start; - break; - } - } - - if (bootmap_pfn == 0) - BUG(); - - return bootmap_pfn; -} - -static int __init check_initrd(struct meminfo *mi) -{ - int initrd_node = -2; -#ifdef CONFIG_BLK_DEV_INITRD - unsigned long end = phys_initrd_start + phys_initrd_size; - - /* - * Make sure that the initrd is within a valid area of - * memory. - */ - if (phys_initrd_size) { - unsigned int i; - - initrd_node = -1; - - for (i = 0; i < mi->nr_banks; i++) { - struct membank *bank = &mi->bank[i]; - if (bank_phys_start(bank) <= phys_initrd_start && - end <= bank_phys_end(bank)) - initrd_node = bank->node; - } - } - - if (initrd_node == -1) { - printk(KERN_ERR "INITRD: 0x%08lx+0x%08lx extends beyond " - "physical memory - disabling initrd\n", - phys_initrd_start, phys_initrd_size); - phys_initrd_start = phys_initrd_size = 0; - } -#endif - - return initrd_node; -} - -static void __init bootmem_init_node(int node, struct meminfo *mi, +static void __init arm_bootmem_init(struct meminfo *mi, unsigned long start_pfn, unsigned long end_pfn) { - unsigned long boot_pfn; unsigned int boot_pages; + phys_addr_t bitmap; pg_data_t *pgdat; int i; /* - * Allocate the bootmem bitmap page. + * Allocate the bootmem bitmap page. This must be in a region + * of memory which has already been mapped. */ boot_pages = bootmem_bootmap_pages(end_pfn - start_pfn); - boot_pfn = find_bootmap_pfn(node, mi, boot_pages); + bitmap = memblock_alloc_base(boot_pages << PAGE_SHIFT, L1_CACHE_BYTES, + __pfn_to_phys(end_pfn)); /* - * Initialise the bootmem allocator for this node, handing the + * Initialise the bootmem allocator, handing the * memory banks over to bootmem. */ - node_set_online(node); - pgdat = NODE_DATA(node); - init_bootmem_node(pgdat, boot_pfn, start_pfn, end_pfn); + node_set_online(0); + pgdat = NODE_DATA(0); + init_bootmem_node(pgdat, __phys_to_pfn(bitmap), start_pfn, end_pfn); - for_each_nodebank(i, mi, node) { + for_each_bank(i, mi) { struct membank *bank = &mi->bank[i]; if (!bank->highmem) - free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank)); + free_bootmem(bank_phys_start(bank), bank_phys_size(bank)); } /* - * Reserve the bootmem bitmap for this node. + * Reserve the memblock reserved regions in bootmem. */ - reserve_bootmem_node(pgdat, boot_pfn << PAGE_SHIFT, - boot_pages << PAGE_SHIFT, BOOTMEM_DEFAULT); -} - -static void __init bootmem_reserve_initrd(int node) -{ -#ifdef CONFIG_BLK_DEV_INITRD - pg_data_t *pgdat = NODE_DATA(node); - int res; - - res = reserve_bootmem_node(pgdat, phys_initrd_start, - phys_initrd_size, BOOTMEM_EXCLUSIVE); - - if (res == 0) { - initrd_start = __phys_to_virt(phys_initrd_start); - initrd_end = initrd_start + phys_initrd_size; - } else { - printk(KERN_ERR - "INITRD: 0x%08lx+0x%08lx overlaps in-use " - "memory region - disabling initrd\n", - phys_initrd_start, phys_initrd_size); + for (i = 0; i < memblock.reserved.cnt; i++) { + phys_addr_t start = memblock_start_pfn(&memblock.reserved, i); + if (start >= start_pfn && + memblock_end_pfn(&memblock.reserved, i) <= end_pfn) + reserve_bootmem_node(pgdat, __pfn_to_phys(start), + memblock_size_bytes(&memblock.reserved, i), + BOOTMEM_DEFAULT); } -#endif } -static void __init bootmem_free_node(int node, struct meminfo *mi) +static void __init arm_bootmem_free(struct meminfo *mi, unsigned long min, + unsigned long max_low, unsigned long max_high) { unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES]; - unsigned long min, max_low, max_high; int i; - find_node_limits(node, mi, &min, &max_low, &max_high); - /* - * initialise the zones within this node. + * initialise the zones. */ memset(zone_size, 0, sizeof(zone_size)); /* - * The size of this node has already been determined. If we need - * to do anything fancy with the allocation of this memory to the - * zones, now is the time to do it. + * The memory size has already been determined. If we need + * to do anything fancy with the allocation of this memory + * to the zones, now is the time to do it. */ zone_size[0] = max_low - min; #ifdef CONFIG_HIGHMEM @@ -303,11 +212,11 @@ static void __init bootmem_free_node(int node, struct meminfo *mi) #endif /* - * For each bank in this node, calculate the size of the holes. - * holes = node_size - sum(bank_sizes_in_node) + * Calculate the size of the holes. + * holes = node_size - sum(bank_sizes) */ memcpy(zhole_size, zone_size, sizeof(zhole_size)); - for_each_nodebank(i, mi, node) { + for_each_bank(i, mi) { int idx = 0; #ifdef CONFIG_HIGHMEM if (mi->bank[i].highmem) @@ -320,24 +229,23 @@ static void __init bootmem_free_node(int node, struct meminfo *mi) * Adjust the sizes according to any special requirements for * this machine type. */ - arch_adjust_zones(node, zone_size, zhole_size); + arch_adjust_zones(zone_size, zhole_size); - free_area_init_node(node, zone_size, min, zhole_size); + free_area_init_node(0, zone_size, min, zhole_size); } #ifndef CONFIG_SPARSEMEM int pfn_valid(unsigned long pfn) { - struct meminfo *mi = &meminfo; - unsigned int left = 0, right = mi->nr_banks; + struct memblock_region *mem = &memblock.memory; + unsigned int left = 0, right = mem->cnt; do { unsigned int mid = (right + left) / 2; - struct membank *bank = &mi->bank[mid]; - if (pfn < bank_pfn_start(bank)) + if (pfn < memblock_start_pfn(mem, mid)) right = mid; - else if (pfn >= bank_pfn_end(bank)) + else if (pfn >= memblock_end_pfn(mem, mid)) left = mid + 1; else return 1; @@ -346,73 +254,69 @@ int pfn_valid(unsigned long pfn) } EXPORT_SYMBOL(pfn_valid); -static void arm_memory_present(struct meminfo *mi, int node) +static void arm_memory_present(void) { } #else -static void arm_memory_present(struct meminfo *mi, int node) +static void arm_memory_present(void) { int i; - for_each_nodebank(i, mi, node) { - struct membank *bank = &mi->bank[i]; - memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank)); - } + for (i = 0; i < memblock.memory.cnt; i++) + memory_present(0, memblock_start_pfn(&memblock.memory, i), + memblock_end_pfn(&memblock.memory, i)); } #endif -void __init bootmem_init(void) +void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc) { - struct meminfo *mi = &meminfo; - unsigned long min, max_low, max_high; - int node, initrd_node; + int i; - /* - * Locate which node contains the ramdisk image, if any. - */ - initrd_node = check_initrd(mi); + memblock_init(); + for (i = 0; i < mi->nr_banks; i++) + memblock_add(mi->bank[i].start, mi->bank[i].size); - max_low = max_high = 0; + /* Register the kernel text, kernel data and initrd with memblock. */ +#ifdef CONFIG_XIP_KERNEL + memblock_reserve(__pa(_data), _end - _data); +#else + memblock_reserve(__pa(_stext), _end - _stext); +#endif +#ifdef CONFIG_BLK_DEV_INITRD + if (phys_initrd_size) { + memblock_reserve(phys_initrd_start, phys_initrd_size); - /* - * Run through each node initialising the bootmem allocator. - */ - for_each_node(node) { - unsigned long node_low, node_high; + /* Now convert initrd to virtual addresses */ + initrd_start = __phys_to_virt(phys_initrd_start); + initrd_end = initrd_start + phys_initrd_size; + } +#endif - find_node_limits(node, mi, &min, &node_low, &node_high); + arm_mm_memblock_reserve(); - if (node_low > max_low) - max_low = node_low; - if (node_high > max_high) - max_high = node_high; + /* reserve any platform specific memblock areas */ + if (mdesc->reserve) + mdesc->reserve(); - /* - * If there is no memory in this node, ignore it. - * (We can't have nodes which have no lowmem) - */ - if (node_low == 0) - continue; + memblock_analyze(); + memblock_dump_all(); +} - bootmem_init_node(node, mi, min, node_low); +void __init bootmem_init(void) +{ + struct meminfo *mi = &meminfo; + unsigned long min, max_low, max_high; - /* - * Reserve any special node zero regions. - */ - if (node == 0) - reserve_node_zero(NODE_DATA(node)); + max_low = max_high = 0; - /* - * If the initrd is in this node, reserve its memory. - */ - if (node == initrd_node) - bootmem_reserve_initrd(node); + find_limits(mi, &min, &max_low, &max_high); - /* - * Sparsemem tries to allocate bootmem in memory_present(), - * so must be done after the fixed reservations - */ - arm_memory_present(mi, node); - } + arm_bootmem_init(mi, min, max_low); + + /* + * Sparsemem tries to allocate bootmem in memory_present(), + * so must be done after the fixed reservations + */ + arm_memory_present(); /* * sparse_init() needs the bootmem allocator up and running. @@ -420,12 +324,11 @@ void __init bootmem_init(void) sparse_init(); /* - * Now free memory in each node - free_area_init_node needs + * Now free the memory - free_area_init_node needs * the sparse mem_map arrays initialized by sparse_init() * for memmap_init_zone(), otherwise all PFNs are invalid. */ - for_each_node(node) - bootmem_free_node(node, mi); + arm_bootmem_free(mi, min, max_low, max_high); high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1; @@ -460,7 +363,7 @@ static inline int free_area(unsigned long pfn, unsigned long end, char *s) } static inline void -free_memmap(int node, unsigned long start_pfn, unsigned long end_pfn) +free_memmap(unsigned long start_pfn, unsigned long end_pfn) { struct page *start_pg, *end_pg; unsigned long pg, pgend; @@ -483,40 +386,39 @@ free_memmap(int node, unsigned long start_pfn, unsigned long end_pfn) * free the section of the memmap array. */ if (pg < pgend) - free_bootmem_node(NODE_DATA(node), pg, pgend - pg); + free_bootmem(pg, pgend - pg); } /* * The mem_map array can get very big. Free the unused area of the memory map. */ -static void __init free_unused_memmap_node(int node, struct meminfo *mi) +static void __init free_unused_memmap(struct meminfo *mi) { unsigned long bank_start, prev_bank_end = 0; unsigned int i; /* - * [FIXME] This relies on each bank being in address order. This - * may not be the case, especially if the user has provided the - * information on the command line. + * This relies on each bank being in address order. + * The banks are sorted previously in bootmem_init(). */ - for_each_nodebank(i, mi, node) { + for_each_bank(i, mi) { struct membank *bank = &mi->bank[i]; bank_start = bank_pfn_start(bank); - if (bank_start < prev_bank_end) { - printk(KERN_ERR "MEM: unordered memory banks. " - "Not freeing memmap.\n"); - break; - } /* * If we had a previous bank, and there is a space * between the current bank and the previous, free it. */ - if (prev_bank_end && prev_bank_end != bank_start) - free_memmap(node, prev_bank_end, bank_start); + if (prev_bank_end && prev_bank_end < bank_start) + free_memmap(prev_bank_end, bank_start); - prev_bank_end = bank_pfn_end(bank); + /* + * Align up here since the VM subsystem insists that the + * memmap entries are valid from the bank end aligned to + * MAX_ORDER_NR_PAGES. + */ + prev_bank_end = ALIGN(bank_pfn_end(bank), MAX_ORDER_NR_PAGES); } } @@ -528,21 +430,19 @@ static void __init free_unused_memmap_node(int node, struct meminfo *mi) void __init mem_init(void) { unsigned long reserved_pages, free_pages; - int i, node; + int i; +#ifdef CONFIG_HAVE_TCM + /* These pointers are filled in on TCM detection */ + extern u32 dtcm_end; + extern u32 itcm_end; +#endif -#ifndef CONFIG_DISCONTIGMEM max_mapnr = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map; -#endif /* this will put all unused low memory onto the freelists */ - for_each_online_node(node) { - pg_data_t *pgdat = NODE_DATA(node); + free_unused_memmap(&meminfo); - free_unused_memmap_node(node, &meminfo); - - if (pgdat->node_spanned_pages != 0) - totalram_pages += free_all_bootmem_node(pgdat); - } + totalram_pages += free_all_bootmem(); #ifdef CONFIG_SA1111 /* now that our DMA memory is actually so designated, we can free it */ @@ -552,39 +452,35 @@ void __init mem_init(void) #ifdef CONFIG_HIGHMEM /* set highmem page free */ - for_each_online_node(node) { - for_each_nodebank (i, &meminfo, node) { - unsigned long start = bank_pfn_start(&meminfo.bank[i]); - unsigned long end = bank_pfn_end(&meminfo.bank[i]); - if (start >= max_low_pfn + PHYS_PFN_OFFSET) - totalhigh_pages += free_area(start, end, NULL); - } + for_each_bank (i, &meminfo) { + unsigned long start = bank_pfn_start(&meminfo.bank[i]); + unsigned long end = bank_pfn_end(&meminfo.bank[i]); + if (start >= max_low_pfn + PHYS_PFN_OFFSET) + totalhigh_pages += free_area(start, end, NULL); } totalram_pages += totalhigh_pages; #endif reserved_pages = free_pages = 0; - for_each_online_node(node) { - for_each_nodebank(i, &meminfo, node) { - struct membank *bank = &meminfo.bank[i]; - unsigned int pfn1, pfn2; - struct page *page, *end; - - pfn1 = bank_pfn_start(bank); - pfn2 = bank_pfn_end(bank); - - page = pfn_to_page(pfn1); - end = pfn_to_page(pfn2 - 1) + 1; - - do { - if (PageReserved(page)) - reserved_pages++; - else if (!page_count(page)) - free_pages++; - page++; - } while (page < end); - } + for_each_bank(i, &meminfo) { + struct membank *bank = &meminfo.bank[i]; + unsigned int pfn1, pfn2; + struct page *page, *end; + + pfn1 = bank_pfn_start(bank); + pfn2 = bank_pfn_end(bank); + + page = pfn_to_page(pfn1); + end = pfn_to_page(pfn2 - 1) + 1; + + do { + if (PageReserved(page)) + reserved_pages++; + else if (!page_count(page)) + free_pages++; + page++; + } while (page < end); } /* @@ -611,6 +507,10 @@ void __init mem_init(void) printk(KERN_NOTICE "Virtual kernel memory layout:\n" " vector : 0x%08lx - 0x%08lx (%4ld kB)\n" +#ifdef CONFIG_HAVE_TCM + " DTCM : 0x%08lx - 0x%08lx (%4ld kB)\n" + " ITCM : 0x%08lx - 0x%08lx (%4ld kB)\n" +#endif " fixmap : 0x%08lx - 0x%08lx (%4ld kB)\n" #ifdef CONFIG_MMU " DMA : 0x%08lx - 0x%08lx (%4ld MB)\n" @@ -627,6 +527,10 @@ void __init mem_init(void) MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) + (PAGE_SIZE)), +#ifdef CONFIG_HAVE_TCM + MLK(DTCM_OFFSET, (unsigned long) dtcm_end), + MLK(ITCM_OFFSET, (unsigned long) itcm_end), +#endif MLK(FIXADDR_START, FIXADDR_TOP), #ifdef CONFIG_MMU MLM(CONSISTENT_BASE, CONSISTENT_END), diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 28c8b950ef04..ab506272b2d3 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -42,78 +42,11 @@ */ #define VM_ARM_SECTION_MAPPING 0x80000000 -static int remap_area_pte(pmd_t *pmd, unsigned long addr, unsigned long end, - unsigned long phys_addr, const struct mem_type *type) -{ - pgprot_t prot = __pgprot(type->prot_pte); - pte_t *pte; - - pte = pte_alloc_kernel(pmd, addr); - if (!pte) - return -ENOMEM; - - do { - if (!pte_none(*pte)) - goto bad; - - set_pte_ext(pte, pfn_pte(phys_addr >> PAGE_SHIFT, prot), 0); - phys_addr += PAGE_SIZE; - } while (pte++, addr += PAGE_SIZE, addr != end); - return 0; - - bad: - printk(KERN_CRIT "remap_area_pte: page already exists\n"); - BUG(); -} - -static inline int remap_area_pmd(pgd_t *pgd, unsigned long addr, - unsigned long end, unsigned long phys_addr, - const struct mem_type *type) -{ - unsigned long next; - pmd_t *pmd; - int ret = 0; - - pmd = pmd_alloc(&init_mm, pgd, addr); - if (!pmd) - return -ENOMEM; - - do { - next = pmd_addr_end(addr, end); - ret = remap_area_pte(pmd, addr, next, phys_addr, type); - if (ret) - return ret; - phys_addr += next - addr; - } while (pmd++, addr = next, addr != end); - return ret; -} - -static int remap_area_pages(unsigned long start, unsigned long pfn, - size_t size, const struct mem_type *type) -{ - unsigned long addr = start; - unsigned long next, end = start + size; - unsigned long phys_addr = __pfn_to_phys(pfn); - pgd_t *pgd; - int err = 0; - - BUG_ON(addr >= end); - pgd = pgd_offset_k(addr); - do { - next = pgd_addr_end(addr, end); - err = remap_area_pmd(pgd, addr, next, phys_addr, type); - if (err) - break; - phys_addr += next - addr; - } while (pgd++, addr = next, addr != end); - - return err; -} - int ioremap_page(unsigned long virt, unsigned long phys, const struct mem_type *mtype) { - return remap_area_pages(virt, __phys_to_pfn(phys), PAGE_SIZE, mtype); + return ioremap_page_range(virt, virt + PAGE_SIZE, phys, + __pgprot(mtype->prot_pte)); } EXPORT_SYMBOL(ioremap_page); @@ -268,6 +201,12 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn, if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK)) return NULL; + /* + * Don't allow RAM to be mapped - this causes problems with ARMv6+ + */ + if (WARN_ON(pfn_valid(pfn))) + return NULL; + type = get_mem_type(mtype); if (!type) return NULL; @@ -294,7 +233,8 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn, err = remap_area_sections(addr, pfn, size, type); } else #endif - err = remap_area_pages(addr, pfn, size, type); + err = ioremap_page_range(addr, addr + size, __pfn_to_phys(pfn), + __pgprot(type->prot_pte)); if (err) { vunmap((void *)addr); diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index 815d08eecbb0..6630620380a4 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h @@ -28,7 +28,5 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page #endif -struct pglist_data; - void __init bootmem_init(void); -void reserve_node_zero(struct pglist_data *pgdat); +void arm_mm_memblock_reserve(void); diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c index f5abc51c5a07..4f5b39687df5 100644 --- a/arch/arm/mm/mmap.c +++ b/arch/arm/mm/mmap.c @@ -7,6 +7,7 @@ #include <linux/shm.h> #include <linux/sched.h> #include <linux/io.h> +#include <linux/random.h> #include <asm/cputype.h> #include <asm/system.h> @@ -80,6 +81,9 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, start_addr = addr = TASK_UNMAPPED_BASE; mm->cached_hole_size = 0; } + /* 8 bits of randomness in 20 address space bits */ + if (current->flags & PF_RANDOMIZE) + addr += (get_random_int() % (1 << 8)) << PAGE_SHIFT; full_search: if (do_align) diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 285894171186..6e1c4f6a2b3f 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -11,13 +11,12 @@ #include <linux/kernel.h> #include <linux/errno.h> #include <linux/init.h> -#include <linux/bootmem.h> #include <linux/mman.h> #include <linux/nodemask.h> +#include <linux/memblock.h> #include <linux/sort.h> #include <asm/cputype.h> -#include <asm/mach-types.h> #include <asm/sections.h> #include <asm/cachetype.h> #include <asm/setup.h> @@ -258,6 +257,19 @@ static struct mem_type mem_types[] = { .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, .domain = DOMAIN_KERNEL, }, + [MT_MEMORY_DTCM] = { + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | + L_PTE_DIRTY | L_PTE_WRITE, + .prot_l1 = PMD_TYPE_TABLE, + .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, + .domain = DOMAIN_KERNEL, + }, + [MT_MEMORY_ITCM] = { + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | + L_PTE_USER | L_PTE_EXEC, + .prot_l1 = PMD_TYPE_TABLE, + .domain = DOMAIN_IO, + }, }; const struct mem_type *get_mem_type(unsigned int type) @@ -488,18 +500,28 @@ static void __init build_mem_type_table(void) #define vectors_base() (vectors_high() ? 0xffff0000 : 0) -static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, - unsigned long end, unsigned long pfn, - const struct mem_type *type) +static void __init *early_alloc(unsigned long sz) { - pte_t *pte; + void *ptr = __va(memblock_alloc(sz, sz)); + memset(ptr, 0, sz); + return ptr; +} +static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) +{ if (pmd_none(*pmd)) { - pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t)); - __pmd_populate(pmd, __pa(pte) | type->prot_l1); + pte_t *pte = early_alloc(2 * PTRS_PER_PTE * sizeof(pte_t)); + __pmd_populate(pmd, __pa(pte) | prot); } + BUG_ON(pmd_bad(*pmd)); + return pte_offset_kernel(pmd, addr); +} - pte = pte_offset_kernel(pmd, addr); +static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, + unsigned long end, unsigned long pfn, + const struct mem_type *type) +{ + pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); do { set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); pfn++; @@ -668,7 +690,7 @@ void __init iotable_init(struct map_desc *io_desc, int nr) create_mapping(io_desc + i); } -static unsigned long __initdata vmalloc_reserve = SZ_128M; +static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M); /* * vmalloc=size forces the vmalloc area to be exactly 'size' @@ -677,7 +699,7 @@ static unsigned long __initdata vmalloc_reserve = SZ_128M; */ static int __init early_vmalloc(char *arg) { - vmalloc_reserve = memparse(arg, NULL); + unsigned long vmalloc_reserve = memparse(arg, NULL); if (vmalloc_reserve < SZ_16M) { vmalloc_reserve = SZ_16M; @@ -692,22 +714,26 @@ static int __init early_vmalloc(char *arg) "vmalloc area is too big, limiting to %luMB\n", vmalloc_reserve >> 20); } + + vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); return 0; } early_param("vmalloc", early_vmalloc); -#define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve) +phys_addr_t lowmem_end_addr; static void __init sanity_check_meminfo(void) { int i, j, highmem = 0; + lowmem_end_addr = __pa(vmalloc_min - 1) + 1; + for (i = 0, j = 0; i < meminfo.nr_banks; i++) { struct membank *bank = &meminfo.bank[j]; *bank = meminfo.bank[i]; #ifdef CONFIG_HIGHMEM - if (__va(bank->start) > VMALLOC_MIN || + if (__va(bank->start) > vmalloc_min || __va(bank->start) < (void *)PAGE_OFFSET) highmem = 1; @@ -717,8 +743,8 @@ static void __init sanity_check_meminfo(void) * Split those memory banks which are partially overlapping * the vmalloc area greatly simplifying things later. */ - if (__va(bank->start) < VMALLOC_MIN && - bank->size > VMALLOC_MIN - __va(bank->start)) { + if (__va(bank->start) < vmalloc_min && + bank->size > vmalloc_min - __va(bank->start)) { if (meminfo.nr_banks >= NR_BANKS) { printk(KERN_CRIT "NR_BANKS too low, " "ignoring high memory\n"); @@ -727,12 +753,12 @@ static void __init sanity_check_meminfo(void) (meminfo.nr_banks - i) * sizeof(*bank)); meminfo.nr_banks++; i++; - bank[1].size -= VMALLOC_MIN - __va(bank->start); - bank[1].start = __pa(VMALLOC_MIN - 1) + 1; + bank[1].size -= vmalloc_min - __va(bank->start); + bank[1].start = __pa(vmalloc_min - 1) + 1; bank[1].highmem = highmem = 1; j++; } - bank->size = VMALLOC_MIN - __va(bank->start); + bank->size = vmalloc_min - __va(bank->start); } #else bank->highmem = highmem; @@ -741,7 +767,7 @@ static void __init sanity_check_meminfo(void) * Check whether this memory bank would entirely overlap * the vmalloc area. */ - if (__va(bank->start) >= VMALLOC_MIN || + if (__va(bank->start) >= vmalloc_min || __va(bank->start) < (void *)PAGE_OFFSET) { printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx " "(vmalloc region overlap).\n", @@ -753,9 +779,9 @@ static void __init sanity_check_meminfo(void) * Check whether this memory bank would partially overlap * the vmalloc area. */ - if (__va(bank->start + bank->size) > VMALLOC_MIN || + if (__va(bank->start + bank->size) > vmalloc_min || __va(bank->start + bank->size) < __va(bank->start)) { - unsigned long newsize = VMALLOC_MIN - __va(bank->start); + unsigned long newsize = vmalloc_min - __va(bank->start); printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx " "to -%.8lx (vmalloc region overlap).\n", bank->start, bank->start + bank->size - 1, @@ -827,101 +853,23 @@ static inline void prepare_page_table(void) } /* - * Reserve the various regions of node 0 + * Reserve the special regions of memory */ -void __init reserve_node_zero(pg_data_t *pgdat) +void __init arm_mm_memblock_reserve(void) { - unsigned long res_size = 0; - - /* - * Register the kernel text and data with bootmem. - * Note that this can only be in node 0. - */ -#ifdef CONFIG_XIP_KERNEL - reserve_bootmem_node(pgdat, __pa(_data), _end - _data, - BOOTMEM_DEFAULT); -#else - reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext, - BOOTMEM_DEFAULT); -#endif - /* * Reserve the page tables. These are already in use, * and can only be in node 0. */ - reserve_bootmem_node(pgdat, __pa(swapper_pg_dir), - PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT); - - /* - * Hmm... This should go elsewhere, but we really really need to - * stop things allocating the low memory; ideally we need a better - * implementation of GFP_DMA which does not assume that DMA-able - * memory starts at zero. - */ - if (machine_is_integrator() || machine_is_cintegrator()) - res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; - - /* - * These should likewise go elsewhere. They pre-reserve the - * screen memory region at the start of main system memory. - */ - if (machine_is_edb7211()) - res_size = 0x00020000; - if (machine_is_p720t()) - res_size = 0x00014000; - - /* H1940, RX3715 and RX1950 need to reserve this for suspend */ - - if (machine_is_h1940() || machine_is_rx3715() - || machine_is_rx1950()) { - reserve_bootmem_node(pgdat, 0x30003000, 0x1000, - BOOTMEM_DEFAULT); - reserve_bootmem_node(pgdat, 0x30081000, 0x1000, - BOOTMEM_DEFAULT); - } - - if (machine_is_palmld() || machine_is_palmtx()) { - reserve_bootmem_node(pgdat, 0xa0000000, 0x1000, - BOOTMEM_EXCLUSIVE); - reserve_bootmem_node(pgdat, 0xa0200000, 0x1000, - BOOTMEM_EXCLUSIVE); - } - - if (machine_is_treo680() || machine_is_centro()) { - reserve_bootmem_node(pgdat, 0xa0000000, 0x1000, - BOOTMEM_EXCLUSIVE); - reserve_bootmem_node(pgdat, 0xa2000000, 0x1000, - BOOTMEM_EXCLUSIVE); - } - - if (machine_is_palmt5()) - reserve_bootmem_node(pgdat, 0xa0200000, 0x1000, - BOOTMEM_EXCLUSIVE); - - /* - * U300 - This platform family can share physical memory - * between two ARM cpus, one running Linux and the other - * running another OS. - */ - if (machine_is_u300()) { -#ifdef CONFIG_MACH_U300_SINGLE_RAM -#if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) && \ - CONFIG_MACH_U300_2MB_ALIGNMENT_FIX - res_size = 0x00100000; -#endif -#endif - } + memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t)); #ifdef CONFIG_SA1111 /* * Because of the SA1111 DMA bug, we want to preserve our * precious DMA-able memory... */ - res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; + memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); #endif - if (res_size) - reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size, - BOOTMEM_DEFAULT); } /* @@ -940,7 +888,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc) /* * Allocate the vector page early. */ - vectors = alloc_bootmem_low_pages(PAGE_SIZE); + vectors = early_alloc(PAGE_SIZE); for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) pmd_clear(pmd_off_k(addr)); @@ -1011,11 +959,8 @@ static void __init devicemaps_init(struct machine_desc *mdesc) static void __init kmap_init(void) { #ifdef CONFIG_HIGHMEM - pmd_t *pmd = pmd_off_k(PKMAP_BASE); - pte_t *pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t)); - BUG_ON(!pmd_none(*pmd) || !pte); - __pmd_populate(pmd, __pa(pte) | _PAGE_KERNEL_TABLE); - pkmap_page_table = pte + PTRS_PER_PTE; + pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), + PKMAP_BASE, _PAGE_KERNEL_TABLE); #endif } @@ -1066,17 +1011,16 @@ void __init paging_init(struct machine_desc *mdesc) sanity_check_meminfo(); prepare_page_table(); map_lowmem(); - bootmem_init(); devicemaps_init(mdesc); kmap_init(); top_pmd = pmd_off_k(0xffff0000); - /* - * allocate the zero page. Note that this always succeeds and - * returns a zeroed result. - */ - zero_page = alloc_bootmem_low_pages(PAGE_SIZE); + /* allocate the zero page. */ + zero_page = early_alloc(PAGE_SIZE); + + bootmem_init(); + empty_zero_page = virt_to_page(zero_page); __flush_dcache_page(NULL, empty_zero_page); } diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index 33b327379f07..687d02319a41 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -6,8 +6,8 @@ #include <linux/module.h> #include <linux/mm.h> #include <linux/pagemap.h> -#include <linux/bootmem.h> #include <linux/io.h> +#include <linux/memblock.h> #include <asm/cacheflush.h> #include <asm/sections.h> @@ -17,30 +17,14 @@ #include "mm.h" -/* - * Reserve the various regions of node 0 - */ -void __init reserve_node_zero(pg_data_t *pgdat) +void __init arm_mm_memblock_reserve(void) { /* - * Register the kernel text and data with bootmem. - * Note that this can only be in node 0. - */ -#ifdef CONFIG_XIP_KERNEL - reserve_bootmem_node(pgdat, __pa(_data), _end - _data, - BOOTMEM_DEFAULT); -#else - reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext, - BOOTMEM_DEFAULT); -#endif - - /* * Register the exception vector page. * some architectures which the DRAM is the exception vector to trap, * alloc_page breaks with error, although it is not NULL, but "0." */ - reserve_bootmem_node(pgdat, CONFIG_VECTORS_BASE, PAGE_SIZE, - BOOTMEM_DEFAULT); + memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE); } /* diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 72507c630ceb..203a4e944d9e 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -79,15 +79,11 @@ ENTRY(cpu_arm1020_proc_init) * cpu_arm1020_proc_fin() */ ENTRY(cpu_arm1020_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip - bl arm1020_flush_kern_cache_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr /* * cpu_arm1020_reset(loc) diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index d27829805609..1a511e765909 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -79,15 +79,11 @@ ENTRY(cpu_arm1020e_proc_init) * cpu_arm1020e_proc_fin() */ ENTRY(cpu_arm1020e_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip - bl arm1020e_flush_kern_cache_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr /* * cpu_arm1020e_reset(loc) diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index ce13e4a827de..1ffa4eb9c34f 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -68,15 +68,11 @@ ENTRY(cpu_arm1022_proc_init) * cpu_arm1022_proc_fin() */ ENTRY(cpu_arm1022_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip - bl arm1022_flush_kern_cache_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr /* * cpu_arm1022_reset(loc) diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 636672a29c6d..5697c34b95b0 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -68,15 +68,11 @@ ENTRY(cpu_arm1026_proc_init) * cpu_arm1026_proc_fin() */ ENTRY(cpu_arm1026_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip - bl arm1026_flush_kern_cache_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr /* * cpu_arm1026_reset(loc) diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S index 795dc615f43b..64e0b327c7c5 100644 --- a/arch/arm/mm/proc-arm6_7.S +++ b/arch/arm/mm/proc-arm6_7.S @@ -184,8 +184,6 @@ ENTRY(cpu_arm7_proc_init) ENTRY(cpu_arm6_proc_fin) ENTRY(cpu_arm7_proc_fin) - mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, r0 mov r0, #0x31 @ ....S..DP...M mcr p15, 0, r0, c1, c0, 0 @ disable caches mov pc, lr diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index 0b62de244666..9d96824134fc 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S @@ -54,15 +54,11 @@ ENTRY(cpu_arm720_proc_init) mov pc, lr ENTRY(cpu_arm720_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. mcr p15, 0, r0, c1, c0, 0 @ disable caches - mcr p15, 0, r1, c7, c7, 0 @ invalidate cache - ldmfd sp!, {pc} + mov pc, lr /* * Function: arm720_proc_do_idle(void) diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S index 01860cdeb2ec..6c1a9ab059ae 100644 --- a/arch/arm/mm/proc-arm740.S +++ b/arch/arm/mm/proc-arm740.S @@ -36,15 +36,11 @@ ENTRY(cpu_arm740_switch_mm) * cpu_arm740_proc_fin() */ ENTRY(cpu_arm740_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x3f000000 @ bank/f/lock/s bic r0, r0, #0x0000000c @ w-buffer/cache mcr p15, 0, r0, c1, c0, 0 @ disable caches - mcr p15, 0, r0, c7, c0, 0 @ invalidate cache - ldmfd sp!, {pc} + mov pc, lr /* * cpu_arm740_reset(loc) diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S index 1201b9863829..6a850dbba22e 100644 --- a/arch/arm/mm/proc-arm7tdmi.S +++ b/arch/arm/mm/proc-arm7tdmi.S @@ -36,8 +36,6 @@ ENTRY(cpu_arm7tdmi_switch_mm) * cpu_arm7tdmi_proc_fin() */ ENTRY(cpu_arm7tdmi_proc_fin) - mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, r0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 8be81992645d..86f80aa56216 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -69,19 +69,11 @@ ENTRY(cpu_arm920_proc_init) * cpu_arm920_proc_fin() */ ENTRY(cpu_arm920_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH - bl arm920_flush_kern_cache_all -#else - bl v4wt_flush_kern_cache_all -#endif mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr /* * cpu_arm920_reset(loc) diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index c0ff8e4b1074..f76ce9b62883 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S @@ -71,19 +71,11 @@ ENTRY(cpu_arm922_proc_init) * cpu_arm922_proc_fin() */ ENTRY(cpu_arm922_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH - bl arm922_flush_kern_cache_all -#else - bl v4wt_flush_kern_cache_all -#endif mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr /* * cpu_arm922_reset(loc) diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 3c6cffe400f6..657bd3f7c153 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -92,15 +92,11 @@ ENTRY(cpu_arm925_proc_init) * cpu_arm925_proc_fin() */ ENTRY(cpu_arm925_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip - bl arm925_flush_kern_cache_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr /* * cpu_arm925_reset(loc) diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 75b707c9cce1..73f1f3c68910 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -61,15 +61,11 @@ ENTRY(cpu_arm926_proc_init) * cpu_arm926_proc_fin() */ ENTRY(cpu_arm926_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip - bl arm926_flush_kern_cache_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr /* * cpu_arm926_reset(loc) diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S index 1af1657819eb..fffb061a45a5 100644 --- a/arch/arm/mm/proc-arm940.S +++ b/arch/arm/mm/proc-arm940.S @@ -37,15 +37,11 @@ ENTRY(cpu_arm940_switch_mm) * cpu_arm940_proc_fin() */ ENTRY(cpu_arm940_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip - bl arm940_flush_kern_cache_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x00001000 @ i-cache bic r0, r0, #0x00000004 @ d-cache mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr /* * cpu_arm940_reset(loc) diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index 1664b6aaff79..249a6053760a 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S @@ -44,15 +44,11 @@ ENTRY(cpu_arm946_switch_mm) * cpu_arm946_proc_fin() */ ENTRY(cpu_arm946_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip - bl arm946_flush_kern_cache_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x00001000 @ i-cache bic r0, r0, #0x00000004 @ d-cache mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr /* * cpu_arm946_reset(loc) diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S index 28545c29dbcd..db475667fac2 100644 --- a/arch/arm/mm/proc-arm9tdmi.S +++ b/arch/arm/mm/proc-arm9tdmi.S @@ -36,8 +36,6 @@ ENTRY(cpu_arm9tdmi_switch_mm) * cpu_arm9tdmi_proc_fin() */ ENTRY(cpu_arm9tdmi_proc_fin) - mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, r0 mov pc, lr /* diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S index 08f5ac237ad4..7803fdf70029 100644 --- a/arch/arm/mm/proc-fa526.S +++ b/arch/arm/mm/proc-fa526.S @@ -39,17 +39,13 @@ ENTRY(cpu_fa526_proc_init) * cpu_fa526_proc_fin() */ ENTRY(cpu_fa526_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip - bl fa_flush_kern_cache_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. mcr p15, 0, r0, c1, c0, 0 @ disable caches nop nop - ldmfd sp!, {pc} + mov pc, lr /* * cpu_fa526_reset(loc) diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index 53e632343849..b304d0104a4e 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -75,11 +75,6 @@ ENTRY(cpu_feroceon_proc_init) * cpu_feroceon_proc_fin() */ ENTRY(cpu_feroceon_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip - bl feroceon_flush_kern_cache_all - #if defined(CONFIG_CACHE_FEROCEON_L2) && \ !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) mov r0, #0 @@ -91,7 +86,7 @@ ENTRY(cpu_feroceon_proc_fin) bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr /* * cpu_feroceon_reset(loc) diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index caa31154e7db..5f6892fcc167 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S @@ -51,15 +51,11 @@ ENTRY(cpu_mohawk_proc_init) * cpu_mohawk_proc_fin() */ ENTRY(cpu_mohawk_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip - bl mohawk_flush_kern_cache_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1800 @ ...iz........... bic r0, r0, #0x0006 @ .............ca. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr /* * cpu_mohawk_reset(loc) diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index 7b706b389906..a201eb04b5e1 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S @@ -44,17 +44,13 @@ ENTRY(cpu_sa110_proc_init) * cpu_sa110_proc_fin() */ ENTRY(cpu_sa110_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip - bl v4wb_flush_kern_cache_all @ clean caches -1: mov r0, #0 + mov r0, #0 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr /* * cpu_sa110_reset(loc) diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 5c47760c2064..7ddc4805bf97 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S @@ -55,16 +55,12 @@ ENTRY(cpu_sa1100_proc_init) * - Clean and turn off caches. */ ENTRY(cpu_sa1100_proc_fin) - stmfd sp!, {lr} - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip - bl v4wb_flush_kern_cache_all mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr /* * cpu_sa1100_reset(loc) diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 7a5337ed7d68..22aac8515196 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -42,14 +42,11 @@ ENTRY(cpu_v6_proc_init) mov pc, lr ENTRY(cpu_v6_proc_fin) - stmfd sp!, {lr} - cpsid if @ disable interrupts - bl v6_flush_kern_cache_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x0006 @ .............ca. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr /* * cpu_v6_reset(loc) @@ -239,7 +236,8 @@ __v6_proc_info: b __v6_setup .long cpu_arch_name .long cpu_elf_name - .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA + /* See also feat_v6_fixup() for HWCAP_TLS */ + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS .long cpu_v6_name .long v6_processor_functions .long v6wbi_tlb_fns @@ -262,7 +260,7 @@ __pj4_v6_proc_info: b __v6_setup .long cpu_arch_name .long cpu_elf_name - .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS .long cpu_pj4_name .long v6_processor_functions .long v6wbi_tlb_fns diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 7aaf88a3b7aa..6a8506d99ee9 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -45,14 +45,11 @@ ENTRY(cpu_v7_proc_init) ENDPROC(cpu_v7_proc_init) ENTRY(cpu_v7_proc_fin) - stmfd sp!, {lr} - cpsid if @ disable interrupts - bl v7_flush_kern_cache_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x0006 @ .............ca. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldmfd sp!, {pc} + mov pc, lr ENDPROC(cpu_v7_proc_fin) /* @@ -344,7 +341,7 @@ __v7_proc_info: b __v7_setup .long cpu_arch_name .long cpu_elf_name - .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS .long cpu_v7_name .long v7_processor_functions .long v7wbi_tlb_fns diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index e5797f1c1db7..361a51e49030 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -90,15 +90,11 @@ ENTRY(cpu_xsc3_proc_init) * cpu_xsc3_proc_fin() */ ENTRY(cpu_xsc3_proc_fin) - str lr, [sp, #-4]! - mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE - msr cpsr_c, r0 - bl xsc3_flush_kern_cache_all @ clean caches mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1800 @ ...IZ........... bic r0, r0, #0x0006 @ .............CA. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldr pc, [sp], #4 + mov pc, lr /* * cpu_xsc3_reset(loc) diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 63037e2162f2..14075979bcba 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -124,15 +124,11 @@ ENTRY(cpu_xscale_proc_init) * cpu_xscale_proc_fin() */ ENTRY(cpu_xscale_proc_fin) - str lr, [sp, #-4]! - mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE - msr cpsr_c, r0 - bl xscale_flush_kern_cache_all @ clean caches mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1800 @ ...IZ........... bic r0, r0, #0x0006 @ .............CA. mcr p15, 0, r0, c1, c0, 0 @ disable caches - ldr pc, [sp], #4 + mov pc, lr /* * cpu_xscale_reset(loc) diff --git a/arch/arm/mm/vmregion.c b/arch/arm/mm/vmregion.c index 19e09bdb1b8a..935993e1b1ef 100644 --- a/arch/arm/mm/vmregion.c +++ b/arch/arm/mm/vmregion.c @@ -35,7 +35,8 @@ */ struct arm_vmregion * -arm_vmregion_alloc(struct arm_vmregion_head *head, size_t size, gfp_t gfp) +arm_vmregion_alloc(struct arm_vmregion_head *head, size_t align, + size_t size, gfp_t gfp) { unsigned long addr = head->vm_start, end = head->vm_end - size; unsigned long flags; @@ -58,7 +59,7 @@ arm_vmregion_alloc(struct arm_vmregion_head *head, size_t size, gfp_t gfp) goto nospc; if ((addr + size) <= c->vm_start) goto found; - addr = c->vm_end; + addr = ALIGN(c->vm_end, align); if (addr > end) goto nospc; } diff --git a/arch/arm/mm/vmregion.h b/arch/arm/mm/vmregion.h index 6b2cdbdf3a85..15e9f044db9f 100644 --- a/arch/arm/mm/vmregion.h +++ b/arch/arm/mm/vmregion.h @@ -21,7 +21,7 @@ struct arm_vmregion { int vm_active; }; -struct arm_vmregion *arm_vmregion_alloc(struct arm_vmregion_head *, size_t, gfp_t); +struct arm_vmregion *arm_vmregion_alloc(struct arm_vmregion_head *, size_t, size_t, gfp_t); struct arm_vmregion *arm_vmregion_find(struct arm_vmregion_head *, unsigned long); struct arm_vmregion *arm_vmregion_find_remove(struct arm_vmregion_head *, unsigned long); void arm_vmregion_free(struct arm_vmregion_head *, struct arm_vmregion *); diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index ce31f316ac75..43f2b158237c 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -359,7 +359,7 @@ static void __init iop3xx_atu_debug(void) DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); - hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort"); + hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, 0, "imprecise external abort"); } /* for platforms that might be host-bus-adapters */ diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index 6c8a02ad98e3..85d3e55ca4a9 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -29,6 +29,11 @@ #include <mach/time.h> /* + * Minimum clocksource/clockevent timer range in seconds + */ +#define IOP_MIN_RANGE 4 + +/* * IOP clocksource (free-running timer 1). */ static cycle_t iop_clocksource_read(struct clocksource *unused) @@ -44,27 +49,6 @@ static struct clocksource iop_clocksource = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; -static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int hz) -{ - u64 temp; - u32 shift; - - /* Find shift and mult values for hz. */ - shift = 32; - do { - temp = (u64) NSEC_PER_SEC << shift; - do_div(temp, hz); - if ((temp >> 32) == 0) - break; - } while (--shift != 0); - - cs->shift = shift; - cs->mult = (u32) temp; - - printk(KERN_INFO "clocksource: %s uses shift %u mult %#x\n", - cs->name, cs->shift, cs->mult); -} - /* * IOP sched_clock() implementation via its clocksource. */ @@ -130,27 +114,6 @@ static struct clock_event_device iop_clockevent = { .set_mode = iop_set_mode, }; -static void __init iop_clockevent_set_hz(struct clock_event_device *ce, unsigned int hz) -{ - u64 temp; - u32 shift; - - /* Find shift and mult values for hz. */ - shift = 32; - do { - temp = (u64) hz << shift; - do_div(temp, NSEC_PER_SEC); - if ((temp >> 32) == 0) - break; - } while (--shift != 0); - - ce->shift = shift; - ce->mult = (u32) temp; - - printk(KERN_INFO "clockevent: %s uses shift %u mult %#lx\n", - ce->name, ce->shift, ce->mult); -} - static irqreturn_t iop_timer_interrupt(int irq, void *dev_id) { @@ -190,7 +153,8 @@ void __init iop_init_time(unsigned long tick_rate) */ write_tmr0(timer_ctl & ~IOP_TMR_EN); setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); - iop_clockevent_set_hz(&iop_clockevent, tick_rate); + clockevents_calc_mult_shift(&iop_clockevent, + tick_rate, IOP_MIN_RANGE); iop_clockevent.max_delta_ns = clockevent_delta2ns(0xfffffffe, &iop_clockevent); iop_clockevent.min_delta_ns = @@ -207,6 +171,7 @@ void __init iop_init_time(unsigned long tick_rate) write_trr1(0xffffffff); write_tcr1(0xffffffff); write_tmr1(timer_ctl); - iop_clocksource_set_hz(&iop_clocksource, tick_rate); + clocksource_calc_mult_shift(&iop_clocksource, tick_rate, + IOP_MIN_RANGE); clocksource_register(&iop_clocksource); } diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c new file mode 100644 index 000000000000..639c54a07992 --- /dev/null +++ b/arch/arm/plat-mxc/3ds_debugboard.c @@ -0,0 +1,202 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/smsc911x.h> + +#include <mach/hardware.h> + +/* LAN9217 ethernet base address */ +#define LAN9217_BASE_ADDR(n) (n + 0x0) +/* External UART */ +#define UARTA_BASE_ADDR(n) (n + 0x8000) +#define UARTB_BASE_ADDR(n) (n + 0x10000) + +#define BOARD_IO_ADDR(n) (n + 0x20000) +/* LED switchs */ +#define LED_SWITCH_REG 0x00 +/* buttons */ +#define SWITCH_BUTTONS_REG 0x08 +/* status, interrupt */ +#define INTR_STATUS_REG 0x10 +#define INTR_MASK_REG 0x38 +#define INTR_RESET_REG 0x20 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER1_REG 0x40 +#define MAGIC_NUMBER2_REG 0x48 +/* CPLD code version */ +#define CPLD_CODE_VER_REG 0x50 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER3_REG 0x58 +/* module reset register*/ +#define MODULE_RESET_REG 0x60 +/* CPU ID and Personality ID */ +#define MCU_BOARD_ID_REG 0x68 + +#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_BOARD_IRQ_START) +#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_INTERNAL_IRQS) + +#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) +#define MXC_MAX_EXP_IO_LINES 16 + +/* interrupts like external uart , external ethernet etc*/ +#define EXPIO_INT_ENET (MXC_BOARD_IRQ_START + 0) +#define EXPIO_INT_XUART_A (MXC_BOARD_IRQ_START + 1) +#define EXPIO_INT_XUART_B (MXC_BOARD_IRQ_START + 2) +#define EXPIO_INT_BUTTON_A (MXC_BOARD_IRQ_START + 3) +#define EXPIO_INT_BUTTON_B (MXC_BOARD_IRQ_START + 4) + +static void __iomem *brd_io; +static void expio_ack_irq(u32 irq); + +static struct resource smsc911x_resources[] = { + { + .flags = IORESOURCE_MEM, + } , { + .start = EXPIO_INT_ENET, + .end = EXPIO_INT_ENET, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY, +}; + +static struct platform_device smsc_lan9217_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .platform_data = &smsc911x_config, + }, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, +}; + +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 imr_val; + u32 int_valid; + u32 expio_irq; + + desc->chip->mask(irq); /* irq = gpio irq number */ + + imr_val = __raw_readw(brd_io + INTR_MASK_REG); + int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val; + + expio_irq = MXC_BOARD_IRQ_START; + for (; int_valid != 0; int_valid >>= 1, expio_irq++) { + struct irq_desc *d; + if ((int_valid & 1) == 0) + continue; + d = irq_desc + expio_irq; + if (unlikely(!(d->handle_irq))) + pr_err("\nEXPIO irq: %d unhandled\n", expio_irq); + else + d->handle_irq(expio_irq, d); + } + + desc->chip->ack(irq); + desc->chip->unmask(irq); +} + +/* + * Disable an expio pin's interrupt by setting the bit in the imr. + * Irq is an expio virtual irq number + */ +static void expio_mask_irq(u32 irq) +{ + u16 reg; + u32 expio = MXC_IRQ_TO_EXPIO(irq); + + reg = __raw_readw(brd_io + INTR_MASK_REG); + reg |= (1 << expio); + __raw_writew(reg, brd_io + INTR_MASK_REG); +} + +static void expio_ack_irq(u32 irq) +{ + u32 expio = MXC_IRQ_TO_EXPIO(irq); + + __raw_writew(1 << expio, brd_io + INTR_RESET_REG); + __raw_writew(0, brd_io + INTR_RESET_REG); + expio_mask_irq(irq); +} + +static void expio_unmask_irq(u32 irq) +{ + u16 reg; + u32 expio = MXC_IRQ_TO_EXPIO(irq); + + reg = __raw_readw(brd_io + INTR_MASK_REG); + reg &= ~(1 << expio); + __raw_writew(reg, brd_io + INTR_MASK_REG); +} + +static struct irq_chip expio_irq_chip = { + .ack = expio_ack_irq, + .mask = expio_mask_irq, + .unmask = expio_unmask_irq, +}; + +int __init mxc_expio_init(u32 base, u32 p_irq) +{ + int i; + + brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K); + if (brd_io == NULL) + return -ENOMEM; + + if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) || + (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) || + (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) { + pr_info("3-Stack Debug board not detected\n"); + iounmap(brd_io); + brd_io = NULL; + return -ENODEV; + } + + pr_info("3-Stack Debug board detected, rev = 0x%04X\n", + readw(brd_io + CPLD_CODE_VER_REG)); + + /* + * Configure INT line as GPIO input + */ + gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq"); + gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq)); + + /* disable the interrupt and clear the status */ + __raw_writew(0, brd_io + INTR_MASK_REG); + __raw_writew(0xFFFF, brd_io + INTR_RESET_REG); + __raw_writew(0, brd_io + INTR_RESET_REG); + __raw_writew(0x1F, brd_io + INTR_MASK_REG); + for (i = MXC_EXP_IO_BASE; + i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { + set_irq_chip(i, &expio_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + set_irq_type(p_irq, IRQF_TRIGGER_LOW); + set_irq_chained_handler(p_irq, mxc_expio_irq_handler); + + /* Register Lan device on the debugboard */ + smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); + smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1; + platform_device_register(&smsc_lan9217_device); + + return 0; +} diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 7f7ad6f289bd..0527e65318f4 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -1,5 +1,7 @@ if ARCH_MXC +source "arch/arm/plat-mxc/devices/Kconfig" + menu "Freescale MXC Implementations" choice @@ -8,15 +10,12 @@ choice config ARCH_MX1 bool "MX1-based" - select CPU_ARM920T - select IMX_HAVE_IOMUX_V1 + select SOC_IMX1 help This enables support for systems based on the Freescale i.MX1 family config ARCH_MX2 bool "MX2-based" - select CPU_ARM926T - select IMX_HAVE_IOMUX_V1 help This enables support for systems based on the Freescale i.MX2 family @@ -25,6 +24,7 @@ config ARCH_MX25 select CPU_ARM926T select ARCH_MXC_IOMUX_V3 select HAVE_FB_IMX + select ARCH_MXC_AUDMUX_V2 help This enables support for systems based on the Freescale i.MX25 family @@ -48,8 +48,7 @@ config ARCH_MX5 endchoice -source "arch/arm/mach-mx1/Kconfig" -source "arch/arm/mach-mx2/Kconfig" +source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-mx3/Kconfig" source "arch/arm/mach-mx25/Kconfig" source "arch/arm/mach-mxc91231/Kconfig" @@ -81,6 +80,17 @@ config MXC_PWM help Enable support for the i.MX PWM controller(s). +config MXC_DEBUG_BOARD + bool "Enable MXC debug board(for 3-stack)" + help + The debug board is an integral part of the MXC 3-stack(PDK) + platforms, it can be attached or removed from the peripheral + board. On debug board, several debug devices(ethernet, UART, + buttons, LEDs and JTAG) are implemented. Between the MCU and + these devices, a CPLD is added as a bridge which performs + data/address de-multiplexing and decode, signal level shift, + interrupt control and various board functions. + config MXC_ULPI bool diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 895bc3c5e0c0..78d405ed8616 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -8,8 +8,6 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o # MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) obj-$(CONFIG_MXC_TZIC) += tzic.o -obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o -obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_MXC_PWM) += pwm.o @@ -17,7 +15,10 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci.o obj-$(CONFIG_MXC_ULPI) += ulpi.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o +obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o ifdef CONFIG_SND_IMX_SOC obj-y += ssi-fiq.o obj-y += ssi-fiq-ksym.o endif + +obj-y += devices/ diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c index b62917ca3f95..1180bef7664b 100644 --- a/arch/arm/plat-mxc/audmux-v1.c +++ b/arch/arm/plat-mxc/audmux-v1.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <linux/module.h> diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index 0c2cc5cd4d83..f9e7cdbd0005 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <linux/module.h> @@ -191,6 +187,7 @@ static int mxc_audmux_v2_init(void) { int ret; +#if defined(CONFIG_ARCH_MX3) if (cpu_is_mx31()) audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR); @@ -204,7 +201,19 @@ static int mxc_audmux_v2_init(void) } audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); } - +#endif +#if defined(CONFIG_ARCH_MX25) + if (cpu_is_mx25()) { + audmux_clk = clk_get(NULL, "audmux"); + if (IS_ERR(audmux_clk)) { + ret = PTR_ERR(audmux_clk); + printk(KERN_ERR "%s: cannot get clock: %d\n", __func__, + ret); + return ret; + } + audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); + } +#endif audmux_debugfs_init(); return 0; diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c index 323ff8ccc877..2ed3ab173add 100644 --- a/arch/arm/plat-mxc/clock.c +++ b/arch/arm/plat-mxc/clock.c @@ -52,13 +52,14 @@ static void __clk_disable(struct clk *clk) { if (clk == NULL || IS_ERR(clk)) return; - - __clk_disable(clk->parent); - __clk_disable(clk->secondary); - WARN_ON(!clk->usecount); - if (!(--clk->usecount) && clk->disable) - clk->disable(clk); + + if (!(--clk->usecount)) { + if (clk->disable) + clk->disable(clk); + __clk_disable(clk->parent); + __clk_disable(clk->secondary); + } } static int __clk_enable(struct clk *clk) @@ -66,12 +67,13 @@ static int __clk_enable(struct clk *clk) if (clk == NULL || IS_ERR(clk)) return -EINVAL; - __clk_enable(clk->parent); - __clk_enable(clk->secondary); - - if (clk->usecount++ == 0 && clk->enable) - clk->enable(clk); + if (clk->usecount++ == 0) { + __clk_enable(clk->parent); + __clk_enable(clk->secondary); + if (clk->enable) + clk->enable(clk); + } return 0; } @@ -160,17 +162,28 @@ EXPORT_SYMBOL(clk_set_rate); int clk_set_parent(struct clk *clk, struct clk *parent) { int ret = -EINVAL; + struct clk *old; if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent) || clk->set_parent == NULL) return ret; + if (clk->usecount) + clk_enable(parent); + mutex_lock(&clocks_mutex); ret = clk->set_parent(clk, parent); - if (ret == 0) + if (ret == 0) { + old = clk->parent; clk->parent = parent; + } else { + old = parent; + } mutex_unlock(&clocks_mutex); + if (clk->usecount) + clk_disable(old); + return ret; } EXPORT_SYMBOL(clk_set_parent); diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index 56f2fb5cc456..735776d84956 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c @@ -18,6 +18,7 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/err.h> #include <linux/platform_device.h> #include <mach/common.h> @@ -35,3 +36,35 @@ int __init mxc_register_device(struct platform_device *pdev, void *data) return ret; } +struct platform_device *__init imx_add_platform_device(const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data) +{ + int ret = -ENOMEM; + struct platform_device *pdev; + + pdev = platform_device_alloc(name, id); + if (!pdev) + goto err; + + if (res) { + ret = platform_device_add_resources(pdev, res, num_resources); + if (ret) + goto err; + } + + if (data) { + ret = platform_device_add_data(pdev, data, size_data); + if (ret) + goto err; + } + + ret = platform_device_add(pdev); + if (ret) { +err: + platform_device_put(pdev); + return ERR_PTR(ret); + } + + return pdev; +} diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig new file mode 100644 index 000000000000..9ab784b776f9 --- /dev/null +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -0,0 +1,15 @@ +config IMX_HAVE_PLATFORM_FLEXCAN + select HAVE_CAN_FLEXCAN + bool + +config IMX_HAVE_PLATFORM_IMX_I2C + bool + +config IMX_HAVE_PLATFORM_IMX_UART + bool + +config IMX_HAVE_PLATFORM_MXC_NAND + bool + +config IMX_HAVE_PLATFORM_SPI_IMX + bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile new file mode 100644 index 000000000000..347da5161f7e --- /dev/null +++ b/arch/arm/plat-mxc/devices/Makefile @@ -0,0 +1,8 @@ +ifdef CONFIG_CAN_FLEXCAN +# the ifdef can be removed once the flexcan driver has been merged +obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o +endif +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c new file mode 100644 index 000000000000..5e97a01f14f3 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-flexcan.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2010 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include <mach/devices-common.h> + +struct platform_device *__init imx_add_flexcan(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct flexcan_platform_data *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c new file mode 100644 index 000000000000..d0af9f7d8aed --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/devices-common.h> + +struct platform_device *__init imx_add_imx_i2c(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct imxi2c_platform_data *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-i2c", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c new file mode 100644 index 000000000000..fa3dff1433e8 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/devices-common.h> + +struct platform_device *__init imx_add_imx_uart_3irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irqrx, resource_size_t irqtx, + resource_size_t irqrts, + const struct imxuart_platform_data *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irqrx, + .end = irqrx, + .flags = IORESOURCE_IRQ, + }, { + .start = irqtx, + .end = irqtx, + .flags = IORESOURCE_IRQ, + }, { + .start = irqrts, + .end = irqrx, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} + +struct platform_device *__init imx_add_imx_uart_1irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct imxuart_platform_data *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c new file mode 100644 index 000000000000..1c286418d123 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/devices-common.h> + +static struct platform_device *__init imx_add_mxc_nand(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata, + resource_size_t iosize) +{ + static int id = 0; + + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_nand", id++, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} + +struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata) +{ + return imx_add_mxc_nand(iobase, irq, pdata, SZ_4K); +} + +struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata) +{ + return imx_add_mxc_nand(iobase, irq, pdata, SZ_8K); +} diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c new file mode 100644 index 000000000000..2831a6d3eb4b --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/devices-common.h> + +struct platform_device *__init imx_add_spi_imx(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct spi_imx_master *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 2a8646173c2f..35a064ff02ba 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -11,10 +11,6 @@ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software Foundation, - * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <linux/platform_device.h> @@ -73,7 +69,51 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) { unsigned int v; -#ifdef CONFIG_ARCH_MX3 +#if defined(CONFIG_ARCH_MX25) + if (cpu_is_mx25()) { + v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + + USBCTRL_OTGBASE_OFFSET)); + + switch (port) { + case 0: /* OTG port */ + v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX35_OTG_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX35_OTG_PM_BIT; + + break; + case 1: /* H1 port */ + v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | + MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX35_H1_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX35_H1_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX35_H1_TLL_BIT; + + if (flags & MXC_EHCI_INTERNAL_PHY) + v |= MX35_H1_USBTE_BIT; + + if (flags & MXC_EHCI_IPPUE_DOWN) + v |= MX35_H1_IPPUE_DOWN_BIT; + + if (flags & MXC_EHCI_IPPUE_UP) + v |= MX35_H1_IPPUE_UP_BIT; + + break; + default: + return -EINVAL; + } + + writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + + USBCTRL_OTGBASE_OFFSET)); + return 0; + } +#endif /* CONFIG_ARCH_MX25 */ +#if defined(CONFIG_ARCH_MX3) if (cpu_is_mx31()) { v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 71437c61cfd7..57ec4a896a5d 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -214,13 +214,16 @@ static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, struct mxc_gpio_port *port = container_of(chip, struct mxc_gpio_port, chip); u32 l; + unsigned long flags; + spin_lock_irqsave(&port->lock, flags); l = __raw_readl(port->base + GPIO_GDIR); if (dir) l |= 1 << offset; else l &= ~(1 << offset); __raw_writel(l, port->base + GPIO_GDIR); + spin_unlock_irqrestore(&port->lock, flags); } static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value) @@ -229,9 +232,12 @@ static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value) container_of(chip, struct mxc_gpio_port, chip); void __iomem *reg = port->base + GPIO_DR; u32 l; + unsigned long flags; + spin_lock_irqsave(&port->lock, flags); l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset); __raw_writel(l, reg); + spin_unlock_irqrestore(&port->lock, flags); } static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset) @@ -285,6 +291,8 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) port[i].chip.base = i * 32; port[i].chip.ngpio = 32; + spin_lock_init(&port[i].lock); + /* its a serious configuration bug when it fails */ BUG_ON( gpiochip_add(&port[i].chip) < 0 ); @@ -292,6 +300,12 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) /* setup one handler for each entry */ set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); set_irq_data(port[i].irq, &port[i]); + if (port[i].irq_high) { + /* setup handler for GPIO 16 to 31 */ + set_irq_chained_handler(port[i].irq_high, + mx3_gpio_irq_handler); + set_irq_data(port[i].irq_high, &port[i]); + } } } diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h new file mode 100644 index 000000000000..a384fdd49c62 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h @@ -0,0 +1,18 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_3DS_DB_H__ +#define __ASM_ARCH_MXC_3DS_DB_H__ + +extern int __init mxc_expio_init(u32 base, u32 p_irq); + +#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h deleted file mode 100644 index 0376c133c9f4..000000000000 --- a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>. - * All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__ -#define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__ - -#endif diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h deleted file mode 100644 index 93cc66f104c7..000000000000 --- a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -#ifndef __ARM_ARCH_BOARD_KZM_ARM11_H -#define __ARM_ARCH_BOARD_KZM_ARM11_H - -/* - * KZM-ARM11-01 Board Control Registers on FPGA - */ -#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000) -#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001) -#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002) -#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004) -#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008) -#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010) -#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020) -#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003) - -/* - * External UART for touch panel on FPGA - */ -#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050) - -#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */ - diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h deleted file mode 100644 index 0cf4fa29510c..000000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx21ads.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__ -#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__ - -/* - * Memory-mapped I/O on MX21ADS base board - */ -#define MX21ADS_MMIO_BASE_ADDR 0xF5000000 -#define MX21ADS_MMIO_SIZE SZ_16M - -#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \ - (MX21ADS_MMIO_BASE_ADDR + (offset)) - -#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11) -#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000) -#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000) -#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000) -#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000) - -/* MX21ADS_IO_REG bit definitions */ -#define MX21ADS_IO_SD_WP 0x0001 /* read */ -#define MX21ADS_IO_TP6 0x0001 /* write */ -#define MX21ADS_IO_SW_SEL 0x0002 /* read */ -#define MX21ADS_IO_TP7 0x0002 /* write */ -#define MX21ADS_IO_RESET_E_UART 0x0004 -#define MX21ADS_IO_RESET_BASE 0x0008 -#define MX21ADS_IO_CSI_CTL2 0x0010 -#define MX21ADS_IO_CSI_CTL1 0x0020 -#define MX21ADS_IO_CSI_CTL0 0x0040 -#define MX21ADS_IO_UART1_EN 0x0080 -#define MX21ADS_IO_UART4_EN 0x0100 -#define MX21ADS_IO_LCDON 0x0200 -#define MX21ADS_IO_IRDA_EN 0x0400 -#define MX21ADS_IO_IRDA_FIR_SEL 0x0800 -#define MX21ADS_IO_IRDA_MD0_B 0x1000 -#define MX21ADS_IO_IRDA_MD1 0x2000 -#define MX21ADS_IO_LED4_ON 0x4000 -#define MX21ADS_IO_LED3_ON 0x8000 - -#endif /* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h deleted file mode 100644 index 7776d230327f..000000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__ -#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__ - -/* external interrupt multiplexer */ -#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) - -#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES) -#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE -#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1) -#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2) - -#define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \ - MXC_MAX_VIRTUAL_INTS) - -/* - * @name Memory Size parameters - */ - -/* - * Size of SDRAM memory - */ -#define SDRAM_MEM_SIZE SZ_128M - -/* - * PBC Controller parameters - */ - -/* - * Base address of PBC controller, CS4 - */ -#define PBC_BASE_ADDRESS 0xf4300000 -#define PBC_REG_ADDR(offset) (void __force __iomem *) \ - (PBC_BASE_ADDRESS + (offset)) - -/* - * PBC Interupt name definitions - */ -#define PBC_GPIO1_0 0 -#define PBC_GPIO1_1 1 -#define PBC_GPIO1_2 2 -#define PBC_GPIO1_3 3 -#define PBC_GPIO1_4 4 -#define PBC_GPIO1_5 5 - -#define PBC_INTR_MAX_NUM 6 -#define PBC_INTR_SHARED_MAX_NUM 8 - -/* When the PBC address connection is fixed in h/w, defined as 1 */ -#define PBC_ADDR_SH 0 - -/* Offsets for the PBC Controller register */ -/* - * PBC Board version register offset - */ -#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH) -/* - * PBC Board control register 1 set address. - */ -#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH) -/* - * PBC Board control register 1 clear address. - */ -#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH) -/* - * PBC Board control register 2 set address. - */ -#define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH) -/* - * PBC Board control register 2 clear address. - */ -#define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH) -/* - * PBC Board control register 3 set address. - */ -#define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH) -/* - * PBC Board control register 3 clear address. - */ -#define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH) -/* - * PBC Board control register 3 set address. - */ -#define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH) -/* - * PBC Board control register 4 clear address. - */ -#define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH) -/*PBC_ADDR_SH - * PBC Board status register 1. - */ -#define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH) -/* - * PBC Board interrupt status register. - */ -#define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH) -/* - * PBC Board interrupt current status register. - */ -#define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH) -/* - * PBC Interrupt mask register set address. - */ -#define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH) -/* - * PBC Interrupt mask register clear address. - */ -#define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH) -/* - * External UART A. - */ -#define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH) -/* - * UART 4 Expanding Signal Status. - */ -#define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH) -/* - * UART 4 Expanding Signal Control Set. - */ -#define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH) -/* - * UART 4 Expanding Signal Control Clear. - */ -#define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH) -/* - * Ethernet Controller IO base address. - */ -#define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH) -/* - * Ethernet Controller Memory base address. - */ -#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH) -/* - * Ethernet Controller DMA base address. - */ -#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH) - -/* PBC Board Version Register bit definition */ -#define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */ -#define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */ - -/* PBC Board Control Register 1 bit definitions */ -#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */ -#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */ -#define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */ -#define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */ -#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */ - -/* PBC Board Control Register 2 bit definitions */ -#define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */ -#define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */ -#define PBC_BCTRL2_ATAFEC_EN 0X0010 -#define PBC_BCTRL2_ATAFEC_SEL 0X0020 -#define PBC_BCTRL2_ATA_EN 0X0040 -#define PBC_BCTRL2_IRDA_SD 0X0080 -#define PBC_BCTRL2_IRDA_EN 0X0100 -#define PBC_BCTRL2_CCTL10 0X0200 -#define PBC_BCTRL2_CCTL11 0X0400 - -/* PBC Board Control Register 3 bit definitions */ -#define PBC_BCTRL3_HSH_EN 0X0020 -#define PBC_BCTRL3_FSH_MOD 0X0040 -#define PBC_BCTRL3_OTG_HS_EN 0X0080 -#define PBC_BCTRL3_OTG_VBUS_EN 0X0100 -#define PBC_BCTRL3_FSH_VBUS_EN 0X0200 -#define PBC_BCTRL3_USB_OTG_ON 0X0800 -#define PBC_BCTRL3_USB_FSH_ON 0X1000 - -/* PBC Board Control Register 4 bit definitions */ -#define PBC_BCTRL4_REGEN_SEL 0X0001 -#define PBC_BCTRL4_USER_OFF 0X0002 -#define PBC_BCTRL4_VIB_EN 0X0004 -#define PBC_BCTRL4_PWRGT1_EN 0X0008 -#define PBC_BCTRL4_PWRGT2_EN 0X0010 -#define PBC_BCTRL4_STDBY_PRI 0X0020 - -#ifndef __ASSEMBLY__ -/* - * Enumerations for SD cards and memory stick card. This corresponds to - * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN. - */ -enum mxc_card_no { - MXC_CARD_SD2 = 0, - MXC_CARD_SD3, - MXC_CARD_MS, - MXC_CARD_SD1, - MXC_CARD_MIN = MXC_CARD_SD2, - MXC_CARD_MAX = MXC_CARD_SD1, -}; -#endif - -#define MXC_CPLD_VER_1_50 0x01 - -/* - * PBC BSTAT Register bit definitions - */ -#define PBC_BSTAT_PRI_INT 0X0001 -#define PBC_BSTAT_USB_BYP 0X0002 -#define PBC_BSTAT_ATA_IOCS16 0X0004 -#define PBC_BSTAT_ATA_CBLID 0X0008 -#define PBC_BSTAT_ATA_DASP 0X0010 -#define PBC_BSTAT_PWR_RDY 0X0020 -#define PBC_BSTAT_SD3_WP 0X0100 -#define PBC_BSTAT_SD2_WP 0X0200 -#define PBC_BSTAT_SD1_WP 0X0400 -#define PBC_BSTAT_SD3_DET 0X0800 -#define PBC_BSTAT_SD2_DET 0X1000 -#define PBC_BSTAT_SD1_DET 0X2000 -#define PBC_BSTAT_MS_DET 0X4000 -#define PBC_BSTAT_SD3_DET_BIT 11 -#define PBC_BSTAT_SD2_DET_BIT 12 -#define PBC_BSTAT_SD1_DET_BIT 13 -#define PBC_BSTAT_MS_DET_BIT 14 -#define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \ - ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \ - ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \ - ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \ - 0x0)))) - -/* - * PBC UART Control Register bit definitions - */ -#define PBC_UCTRL_DCE_DCD 0X0001 -#define PBC_UCTRL_DCE_DSR 0X0002 -#define PBC_UCTRL_DCE_RI 0X0004 -#define PBC_UCTRL_DTE_DTR 0X0100 - -/* - * PBC UART Status Register bit definitions - */ -#define PBC_USTAT_DTE_DCD 0X0001 -#define PBC_USTAT_DTE_DSR 0X0002 -#define PBC_USTAT_DTE_RI 0X0004 -#define PBC_USTAT_DCE_DTR 0X0100 - -/* - * PBC Interupt mask register bit definitions - */ -#define PBC_INTR_SD3_R_EN_BIT 4 -#define PBC_INTR_SD2_R_EN_BIT 0 -#define PBC_INTR_SD1_R_EN_BIT 6 -#define PBC_INTR_MS_R_EN_BIT 5 -#define PBC_INTR_SD3_EN_BIT 13 -#define PBC_INTR_SD2_EN_BIT 12 -#define PBC_INTR_MS_EN_BIT 14 -#define PBC_INTR_SD1_EN_BIT 15 - -#define PBC_INTR_SD2_R_EN 0x0001 -#define PBC_INTR_LOW_BAT 0X0002 -#define PBC_INTR_OTG_FSOVER 0X0004 -#define PBC_INTR_FSH_OVER 0X0008 -#define PBC_INTR_SD3_R_EN 0x0010 -#define PBC_INTR_MS_R_EN 0x0020 -#define PBC_INTR_SD1_R_EN 0x0040 -#define PBC_INTR_FEC_INT 0X0080 -#define PBC_INTR_ENET_INT 0X0100 -#define PBC_INTR_OTGFS_INT 0X0200 -#define PBC_INTR_XUART_INT 0X0400 -#define PBC_INTR_CCTL12 0X0800 -#define PBC_INTR_SD2_EN 0x1000 -#define PBC_INTR_SD3_EN 0x2000 -#define PBC_INTR_MS_EN 0x4000 -#define PBC_INTR_SD1_EN 0x8000 - - - -/* For interrupts like xuart, enet etc */ -#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN) -#define MXC_MAX_EXP_IO_LINES 16 - -/* - * This corresponds to PBC_INTMASK_SET_REG at offset 0x38. - * - */ -#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1) -#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2) -#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3) -#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4) -#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5) -#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6) -#define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7) -#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) -#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9) -#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) -#define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11) -#define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12) -#define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13) -#define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14) -#define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15) - -/* - * This is System IRQ used by CS8900A for interrupt generation - * taken from platform.h - */ -#define CS8900AIRQ EXPIO_INT_ENET_INT -/* This is I/O Base address used to access registers of CS8900A on MXC ADS */ -#define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300) - -#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT) - -/* -* This is used to detect if the CPLD version is for mx27 evb board rev-a -*/ -#define PBC_CPLD_VERSION_IS_REVA() \ - ((__raw_readw(PBC_VERSION_REG) & \ - (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\ - == 0) - -/* This is used to active or inactive ata signal in CPLD . - * It is dependent with hardware - */ -#define PBC_ATA_SIGNAL_ACTIVE() \ - __raw_writew( \ - PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \ - PBC_BCTRL2_CLEAR_REG) - -#define PBC_ATA_SIGNAL_INACTIVE() \ - __raw_writew( \ - PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \ - PBC_BCTRL2_SET_REG) - -#define MXC_BD_LED1 (1 << 5) -#define MXC_BD_LED2 (1 << 6) -#define MXC_BD_LED_ON(led) \ - __raw_writew(led, PBC_BCTRL1_SET_REG) -#define MXC_BD_LED_OFF(led) \ - __raw_writew(led, PBC_BCTRL1_CLEAR_REG) - -/* to determine the correct external crystal reference */ -#define CKIH_27MHZ_BIT_SET (1 << 3) - -#endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h deleted file mode 100644 index ea87551d2736..000000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx27lite.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__ -#define __ASM_ARCH_MXC_BOARD_MX27LITE_H__ - -#endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h deleted file mode 100644 index fec1bcfa9164..000000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__ -#define __ASM_ARCH_MXC_BOARD_MX27PDK_H__ - -#endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h deleted file mode 100644 index da92933a233b..000000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ -#define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ - -/* Definitions for components on the Debug board */ - -/* Base address of CPLD controller on the Debug board */ -#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(CS5_BASE_ADDR) - -/* LAN9217 ethernet base address */ -#define LAN9217_BASE_ADDR CS5_BASE_ADDR - -/* CPLD config and interrupt base address */ -#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000) - -/* LED switchs */ -#define CPLD_LED_REG (CPLD_ADDR + 0x00) -/* buttons */ -#define CPLD_SWITCH_BUTTONS_REG (EXPIO_ADDR + 0x08) -/* status, interrupt */ -#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10) -#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38) -#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20) -/* magic word for debug CPLD */ -#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40) -#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48) -/* CPLD code version */ -#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50) -/* magic word for debug CPLD */ -#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58) -/* module reset register */ -#define CPLD_MODULE_RESET_REG (CPLD_ADDR + 0x60) -/* CPU ID and Personality ID */ -#define CPLD_MCU_BOARD_ID_REG (CPLD_ADDR + 0x68) - -/* CPLD IRQ line for external uart, external ethernet etc */ -#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) - -#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) -#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) - -#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0) -#define EXPIO_INT_XUART_A (MXC_EXP_IO_BASE + 1) -#define EXPIO_INT_XUART_B (MXC_EXP_IO_BASE + 2) -#define EXPIO_INT_BUTTON_A (MXC_EXP_IO_BASE + 3) -#define EXPIO_INT_BUTTON_B (MXC_EXP_IO_BASE + 4) - -#define MXC_MAX_EXP_IO_LINES 16 - -#endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h deleted file mode 100644 index 095a199591c6..000000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ -#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ - -#include <mach/hardware.h> - -/* Base address of PBC controller */ -#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT -/* Offsets for the PBC Controller register */ - -/* PBC Board status register offset */ -#define PBC_BSTAT 0x000002 - -/* PBC Board control register 1 set address */ -#define PBC_BCTRL1_SET 0x000004 - -/* PBC Board control register 1 clear address */ -#define PBC_BCTRL1_CLEAR 0x000006 - -/* PBC Board control register 2 set address */ -#define PBC_BCTRL2_SET 0x000008 - -/* PBC Board control register 2 clear address */ -#define PBC_BCTRL2_CLEAR 0x00000A - -/* PBC Board control register 3 set address */ -#define PBC_BCTRL3_SET 0x00000C - -/* PBC Board control register 3 clear address */ -#define PBC_BCTRL3_CLEAR 0x00000E - -/* PBC Board control register 4 set address */ -#define PBC_BCTRL4_SET 0x000010 - -/* PBC Board control register 4 clear address */ -#define PBC_BCTRL4_CLEAR 0x000012 - -/* PBC Board status register 1 */ -#define PBC_BSTAT1 0x000014 - -/* PBC Board interrupt status register */ -#define PBC_INTSTATUS 0x000016 - -/* PBC Board interrupt current status register */ -#define PBC_INTCURR_STATUS 0x000018 - -/* PBC Interrupt mask register set address */ -#define PBC_INTMASK_SET 0x00001A - -/* PBC Interrupt mask register clear address */ -#define PBC_INTMASK_CLEAR 0x00001C - -/* External UART A */ -#define PBC_SC16C652_UARTA 0x010000 - -/* External UART B */ -#define PBC_SC16C652_UARTB 0x010010 - -/* Ethernet Controller IO base address */ -#define PBC_CS8900A_IOBASE 0x020000 - -/* Ethernet Controller Memory base address */ -#define PBC_CS8900A_MEMBASE 0x021000 - -/* Ethernet Controller DMA base address */ -#define PBC_CS8900A_DMABASE 0x022000 - -/* External chip select 0 */ -#define PBC_XCS0 0x040000 - -/* LCD Display enable */ -#define PBC_LCD_EN_B 0x060000 - -/* Code test debug enable */ -#define PBC_CODE_B 0x070000 - -/* PSRAM memory select */ -#define PBC_PSRAM_B 0x5000000 - -#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) -#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS) -#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS) -#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) -#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) - -#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) -#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) - -#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0) -#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1) -#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2) -#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3) -#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4) -#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5) -#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6) -#define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7) -#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) -#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9) -#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) -#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11) -#define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12) -#define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13) -#define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14) -#define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15) - -#define MXC_MAX_EXP_IO_LINES 16 - -#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h index eb5a5024622e..0df71bfefbb1 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h @@ -31,7 +31,7 @@ enum mx31lilly_boards { /* * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. + * its own devices, it calls the baseboard's init function. */ extern void mx31lilly_db_init(void); diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h index 2b2da0367578..c1ad0ae807cc 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h @@ -32,7 +32,7 @@ enum mx31lite_boards { /* * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. + * its own devices, it calls the baseboard's init function. */ extern void mx31lite_db_init(void); diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h index 36ff3cedee1a..de14543891cf 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h @@ -31,7 +31,7 @@ enum mx31moboard_boards { /* * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. + * its own devices, it calls the baseboard's init function. */ extern void mx31moboard_devboard_init(void); diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h index 410f9786ed22..6f371e35753d 100644 --- a/arch/arm/plat-mxc/include/mach/board-pcm038.h +++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h @@ -22,7 +22,7 @@ #ifndef __ASSEMBLY__ /* * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. + * its own devices, it calls the baseboard's init function. * TODO: Add your own baseboard init function and call it from * inside pcm038_init(). * diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h deleted file mode 100644 index 6d88c7af4b23..000000000000 --- a/arch/arm/plat-mxc/include/mach/board-qong.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__ -#define __ASM_ARCH_MXC_BOARD_QONG_H__ - -/* NOR FLASH */ -#define QONG_NOR_SIZE (128*1024*1024) - -#endif /* __ASM_ARCH_MXC_BOARD_QONG_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 0b6e11eaeb8c..25606409aabc 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -23,8 +23,8 @@ #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif #include <mach/mx25.h> -#define UART_PADDR UART1_BASE_ADDR -#define UART_VADDR MX25_AIPS1_IO_ADDRESS(UART1_BASE_ADDR) +#define UART_PADDR MX25_UART1_BASE_ADDR +#define UART_VADDR MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR) #endif #ifdef CONFIG_ARCH_MX2 diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h new file mode 100644 index 000000000000..c5f68c587309 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/init.h> + +struct platform_device *imx_add_platform_device(const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data); + +#if defined (CONFIG_CAN_FLEXCAN) || defined (CONFIG_CAN_FLEXCAN_MODULE) +#include <linux/can/platform/flexcan.h> +struct platform_device *__init imx_add_flexcan(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct flexcan_platform_data *pdata); +#else +/* the ifdef can be removed once the flexcan driver has been merged */ +struct flexcan_platform_data; +static inline struct platform_device *__init imx_add_flexcan(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct flexcan_platform_data *pdata) +{ + return NULL; +} +#endif + +#include <mach/i2c.h> +struct platform_device *__init imx_add_imx_i2c(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct imxi2c_platform_data *pdata); + +#include <mach/imx-uart.h> +struct platform_device *__init imx_add_imx_uart_3irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irqrx, resource_size_t irqtx, + resource_size_t irqrts, + const struct imxuart_platform_data *pdata); +struct platform_device *__init imx_add_imx_uart_1irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct imxuart_platform_data *pdata); + +#include <mach/mxc_nand.h> +struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata); +struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata); + +#include <mach/spi.h> +struct platform_device *__init imx_add_spi_imx(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct spi_imx_master *pdata); diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h index a1fd5830af48..634e3f4c454d 100644 --- a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h +++ b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Eric Benard - eric@eukrea.com + * Copyright (C) 2010 Eric Benard - eric@eukrea.com * * Based on board-pcm038.h which is : * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) @@ -19,22 +19,29 @@ * MA 02110-1301, USA. */ -#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ -#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ +#ifndef __MACH_EUKREA_BASEBOARDS_H__ +#define __MACH_EUKREA_BASEBOARDS_H__ #ifndef __ASSEMBLY__ /* * This CPU module needs a baseboard to work. After basic initializing * its own devices, it calls baseboard's init function. * TODO: Add your own baseboard init function and call it from - * inside eukrea_cpuimx27_init(). + * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init() + * eukrea_cpuimx35_init() or eukrea_cpuimx51_init(). * * This example here is for the development board. Refer - * eukrea_mbimx27-baseboard.c + * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25 + * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27 + * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35 + * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51 */ +extern void eukrea_mbimx25_baseboard_init(void); extern void eukrea_mbimx27_baseboard_init(void); +extern void eukrea_mbimx35_baseboard_init(void); +extern void eukrea_mbimx51_baseboard_init(void); #endif -#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ */ +#endif /* __MACH_EUKREA_BASEBOARDS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index 894d2f87c856..661fbc605759 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -33,9 +33,11 @@ struct mxc_gpio_port { void __iomem *base; int irq; + int irq_high; int virtual_irq_start; struct gpio_chip chip; u32 both_edges; + spinlock_t lock; }; int mxc_gpio_init(struct mxc_gpio_port*, int); diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h index f39220d1b67a..d7f52c91f82e 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h @@ -252,6 +252,7 @@ #define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CONTRAST__PWM4_PWMO IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL) #define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL) @@ -371,30 +372,41 @@ #define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL) #define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE) +#define KPP_CTL_ROW (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define KPP_CTL_COL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) + +#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, KPP_CTL_ROW) #define MX25_PAD_KPP_ROW0__GPIO_2_29 IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, PAD_CTL_PKE) +#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, KPP_CTL_ROW) #define MX25_PAD_KPP_ROW1__GPIO_2_30 IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, PAD_CTL_PKE) +#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, KPP_CTL_ROW) #define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL) #define MX25_PAD_KPP_ROW2__GPIO_2_31 IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, PAD_CTL_PKE) +#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, KPP_CTL_ROW) #define MX25_PAD_KPP_ROW3__CSI_LD1 IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL) #define MX25_PAD_KPP_ROW3__GPIO_3_0 IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) +#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL) +#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL0__AUD5_TXD IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) #define MX25_PAD_KPP_COL0__GPIO_3_1 IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) +#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL) +#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL1__AUD5_RXD IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) #define MX25_PAD_KPP_COL1__GPIO_3_2 IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) +#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL) +#define MX25_PAD_KPP_COL2__UART4_RTS IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL2__AUD5_TXC IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) #define MX25_PAD_KPP_COL2__GPIO_3_3 IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) +#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL) +#define MX25_PAD_KPP_COL3__UART4_CTS IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL3__AUD5_TXFS IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) #define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL) #define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL) diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index ab0f95d953d0..21bfa46785bb 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -27,8 +27,8 @@ typedef enum iomux_config { IOMUX_CONFIG_ALT5, IOMUX_CONFIG_ALT6, IOMUX_CONFIG_ALT7, - IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ - IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ } iomux_pin_cfg_t; /* Pad control groupings */ @@ -38,6 +38,8 @@ typedef enum iomux_config { PAD_CTL_SRE_FAST) #define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ PAD_CTL_SRE_FAST) +#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) #define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_HYS) @@ -46,289 +48,278 @@ typedef enum iomux_config { /* * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named - * GPIO_<unit>_<num> see also iomux-v3.h + * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> + * See also iomux-v3.h */ -/* - * FIXME: This was converted using scripts from existing Freescale code to - * this form used upstream. Need to verify the name format. - */ - -/* PAD MUX ALT INPSE PATH PADCTRL */ - -#define MX51_PAD_GPIO_2_0__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_1__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_2__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) - -/* Babbage UART3 */ -#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL) - -#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_GPIO_2_10__EIM_A16 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_11__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_12__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_13__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_14__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_15__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_16__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_17__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_GPIO_2_18__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_19__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_20__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_21__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_22__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_23__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_GPIO_2_24__EIM_OE IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_25__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_26__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_27__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_28__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_29__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_30__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_31__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_GPIO_3_1__EIM_LBA IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_2__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_3__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_4__NANDF_RE_B IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_5__NANDF_ALE IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_6__NANDF_CLE IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_7__NANDF_WP_B IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_8__NANDF_RB0 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_9__NANDF_RB1 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_10__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_11__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_12__GPIO_NAND IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) -/* REVISIT: Not sure of these values - - #define MX51_PAD_GPIO_1___NANDF_RB4 IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL) - #define MX51_PAD_GPIO_3_13__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL) - #define MX51_PAD_GPIO_3_15__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL) -*/ -#define MX51_PAD_GPIO_3_14__NANDF_RB6 IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_16__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_17__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_18__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_19__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_20__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_21__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_22__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_23__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_25__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_26__NANDF_D14 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_27__NANDF_D13 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_28__NANDF_D12 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_29__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_30__NANDF_D10 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_31__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_0__NANDF_D8 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_1__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_2__NANDF_D6 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_3__NANDF_D5 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_5__NANDF_D3 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_6__NANDF_D2 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_7__NANDF_D1 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_8__NANDF_D0 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_12__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_13__CSI1_D9 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_9__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_10__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_11__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_12__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_11__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_12__CSI2_D17 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_11__CSI2_D18 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_12__CSI2_D19 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_13__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_14__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_16__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_17__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_20__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_21__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_22__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_23__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_24__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_25__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_26__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_27__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) - -/* Babbage UART1 */ -#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) -#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) -#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL) -#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL) - -/* Babbage UART2 */ -#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL) -#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL) - -#define MX51_PAD_GPIO_1_22__UART3_RXD IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_23__UART3_TXD IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_24__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_3__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_4__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_19__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_29__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_30__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_31__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_0__GPIO1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_1__GPIO1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_2__GPIO1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_3__GPIO1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \ - (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)) -#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) - -/* EIM */ -#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) +/* PAD MUX ALT INPSE PATH PADCTRL */ +#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D16__GPIO_2_0 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, (4 | IOMUX_CONFIG_SION), \ + 0x09b4, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D17__GPIO_2_1 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D18__GPIO_2_2 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D19__GPIO_2_3 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, (4 | IOMUX_CONFIG_SION), \ + 0x09b0, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D20__GPIO_2_4 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D22__GPIO_2_6 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D23__GPIO_2_7 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, 0x0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, 0x0, 0, MX51_UART2_PAD_CTRL) +#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, 0x0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL) +#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A16__GPIO_2_10 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A17__GPIO_2_11 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A18__GPIO_2_12 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A19__GPIO_2_13 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A20__GPIO_2_14 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A21__GPIO_2_15 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A23__GPIO_2_17 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A24__GPIO_2_18 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A25__GPIO_2_19 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A26__GPIO_2_20 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A27__GPIO_2_21 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WE_B__GPIO_3_3 IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RE_B__GPIO_3_4 IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_ALE__GPIO_3_5 IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CLE__GPIO_3_6 IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WP_B__GPIO_3_7 IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D11__GPIO_3_29 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D10__GPIO_3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D9__GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D8__GPIO_4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D7__GPIO_4_1 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D6__GPIO_4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D5__GPIO_4_3 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D4__GPIO_4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D3__GPIO_4_5 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D2__GPIO_4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D1__GPIO_4_7 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D0__GPIO_4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D8__GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D9__GPIO_3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x000, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x000, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x000, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D12__GPIO_4_9 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D13__GPIO_4_10 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D14__GPIO_4_11 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D15__GPIO_4_12 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D16__GPIO_4_11 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D17__GPIO_4_12 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D18__GPIO_4_11 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D19__GPIO_4_12 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_VSYNC__GPIO_4_13 IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_HSYNC__GPIO_4_14 IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15 IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_CLK__GPIO_4_16 IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) +#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) +#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL) +#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0, 0, MX51_UART1_PAD_CTRL) +#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL) +#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, 0, 0x0, 0, MX51_UART2_PAD_CTRL) +#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL) +#define MX51_PAD_UART3_RXD__GPIO_1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_UART3_TXD__GPIO_1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_OWIRE_LINE__GPIO_1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65C, 0x26C, 2, 0x9f0, 4, MX51_UART3_PAD_CTRL) +#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65C, 0x26C, (3 | IOMUX_CONFIG_SION), \ + 0x09b8, 1, MX51_I2C_PAD_CTRL) +#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, (3 | IOMUX_CONFIG_SION), \ + 0x09bc, 1, MX51_I2C_PAD_CTRL) +#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT6__GPIO_1_19 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT7__GPIO_1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT8__GPIO_1_30 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT9__GPIO_1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \ + 0x9b8, 3, MX51_I2C_PAD_CTRL) +#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \ + 0x9bc, 3, MX51_I2C_PAD_CTRL) +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) #endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h index 3887f3fe29d4..15d59510f597 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __MACH_IOMUX_MXC91231_H__ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index f2f73d31d5ba..0880a4a1aed1 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -89,6 +89,21 @@ struct pad_desc { #define PAD_CTL_SRE_FAST (1 << 0) #define PAD_CTL_SRE_SLOW (0 << 0) + +#define MX51_NUM_GPIO_PORT 4 + +#define GPIO_PIN_MASK 0x1f + +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) + +#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) +#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) +#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) +#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) +#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) +#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) + /* * setups a single pad in the iomuxer */ diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index c4b40c35a6a1..564ec9dbc93d 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -44,12 +44,12 @@ */ #define CONSISTENT_DMA_SIZE SZ_8M -#elif defined(CONFIG_MX1_VIDEO) +#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_VIDEO_MX2_HOSTSUPPORT) /* * Increase size of DMA-consistent memory region. * This is required for i.MX camera driver to capture at least four VGA frames. */ #define CONSISTENT_DMA_SIZE SZ_4M -#endif /* CONFIG_MX1_VIDEO */ +#endif /* CONFIG_MX1_VIDEO || CONFIG_VIDEO_MX2_HOSTSUPPORT */ #endif /* __ASM_ARCH_MXC_MEMORY_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h index de2128dada5c..29115f405af9 100644 --- a/arch/arm/plat-mxc/include/mach/mmc.h +++ b/arch/arm/plat-mxc/include/mach/mmc.h @@ -31,6 +31,9 @@ struct imxmmc_platform_data { /* adjust slot voltage */ void (*setpower)(struct device *, unsigned int vdd); + + /* enable card detect using DAT3 */ + int dat3_card_detect; }; #endif diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 5eba7e6785de..641b24618239 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -91,24 +91,24 @@ #define MX1_SIM_DATA_INT 16 #define MX1_RTC_INT 17 #define MX1_RTC_SAMINT 18 -#define MX1_UART2_MINT_PFERR 19 -#define MX1_UART2_MINT_RTS 20 -#define MX1_UART2_MINT_DTR 21 -#define MX1_UART2_MINT_UARTC 22 -#define MX1_UART2_MINT_TX 23 -#define MX1_UART2_MINT_RX 24 -#define MX1_UART1_MINT_PFERR 25 -#define MX1_UART1_MINT_RTS 26 -#define MX1_UART1_MINT_DTR 27 -#define MX1_UART1_MINT_UARTC 28 -#define MX1_UART1_MINT_TX 29 -#define MX1_UART1_MINT_RX 30 +#define MX1_INT_UART2PFERR 19 +#define MX1_INT_UART2RTS 20 +#define MX1_INT_UART2DTR 21 +#define MX1_INT_UART2UARTC 22 +#define MX1_INT_UART2TX 23 +#define MX1_INT_UART2RX 24 +#define MX1_INT_UART1PFERR 25 +#define MX1_INT_UART1RTS 26 +#define MX1_INT_UART1DTR 27 +#define MX1_INT_UART1UARTC 28 +#define MX1_INT_UART1TX 29 +#define MX1_INT_UART1RX 30 #define MX1_VOICE_DAC_INT 31 #define MX1_VOICE_ADC_INT 32 #define MX1_PEN_DATA_INT 33 #define MX1_PWM_INT 34 #define MX1_SDHC_INT 35 -#define MX1_I2C_INT 39 +#define MX1_INT_I2C 39 #define MX1_CSPI_INT 41 #define MX1_SSI_TX_INT 42 #define MX1_SSI_TX_ERR_INT 43 @@ -245,7 +245,7 @@ #define PEN_DATA_INT MX1_PEN_DATA_INT #define PWM_INT MX1_PWM_INT #define SDHC_INT MX1_SDHC_INT -#define I2C_INT MX1_I2C_INT +#define I2C_INT MX1_INT_I2C #define CSPI_INT MX1_CSPI_INT #define SSI_TX_INT MX1_SSI_TX_INT #define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 4eb6e334bda5..4a6f800990f8 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -11,6 +11,12 @@ #define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX25_AVIC_SIZE SZ_1M +#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) +#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000) +#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000) +#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000) +#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000) +#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000) #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) @@ -27,22 +33,48 @@ IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ IMX_IO_ADDRESS(x, MX25_AVIC)) +#define MX25_AIPS1_IO_ADDRESS(x) \ + (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) + #define MX25_UART1_BASE_ADDR 0x43f90000 #define MX25_UART2_BASE_ADDR 0x43f94000 +#define MX25_AUDMUX_BASE_ADDR 0x43fb0000 +#define MX25_UART3_BASE_ADDR 0x5000c000 +#define MX25_UART4_BASE_ADDR 0x50008000 +#define MX25_UART5_BASE_ADDR 0x5002c000 +#define MX25_CSPI3_BASE_ADDR 0x50004000 +#define MX25_CSPI2_BASE_ADDR 0x50010000 #define MX25_FEC_BASE_ADDR 0x50038000 +#define MX25_SSI2_BASE_ADDR 0x50014000 +#define MX25_SSI1_BASE_ADDR 0x50034000 #define MX25_NFC_BASE_ADDR 0xbb000000 #define MX25_DRYICE_BASE_ADDR 0x53ffc000 #define MX25_LCDC_BASE_ADDR 0x53fbc000 +#define MX25_KPP_BASE_ADDR 0x43fa8000 +#define MX25_OTG_BASE_ADDR 0x53ff4000 +#define MX25_CSI_BASE_ADDR 0x53ff8000 -#define MX25_INT_DRYICE 25 -#define MX25_INT_FEC 57 -#define MX25_INT_NANDFC 33 -#define MX25_INT_LCDC 39 - -#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS) -#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR -#define UART2_BASE_ADDR MX25_UART2_BASE_ADDR -#endif +#define MX25_INT_CSPI3 0 +#define MX25_INT_I2C1 3 +#define MX25_INT_I2C2 4 +#define MX25_INT_UART4 5 +#define MX25_INT_I2C3 10 +#define MX25_INT_SSI2 11 +#define MX25_INT_SSI1 12 +#define MX25_INT_CSPI2 13 +#define MX25_INT_CSPI1 14 +#define MX25_INT_CSI 17 +#define MX25_INT_UART3 18 +#define MX25_INT_KPP 24 +#define MX25_INT_DRYICE 25 +#define MX25_INT_UART2 32 +#define MX25_INT_NANDFC 33 +#define MX25_INT_LCDC 39 +#define MX25_INT_UART5 40 +#define MX25_INT_CAN1 43 +#define MX25_INT_CAN2 44 +#define MX25_INT_UART1 45 +#define MX25_INT_FEC 57 #endif /* ifndef __MACH_MX25_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index bae9cd75beee..a8ab2e02a8ca 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -48,7 +48,7 @@ #define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) #define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) #define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) -#define MX27_I2C_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) +#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) @@ -150,7 +150,7 @@ static inline void mx27_setup_weimcs(size_t cs, #define MX27_INT_SDHC3 9 #define MX27_INT_SDHC2 10 #define MX27_INT_SDHC1 11 -#define MX27_INT_I2C 12 +#define MX27_INT_I2C1 12 #define MX27_INT_SSI2 13 #define MX27_INT_SSI1 14 #define MX27_INT_CSPI2 15 diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/arch/arm/plat-mxc/include/mach/mx2_cam.h new file mode 100644 index 000000000000..3c080a32dbf5 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx2_cam.h @@ -0,0 +1,46 @@ +/* + * mx2-cam.h - i.MX27/i.MX25 camera driver header file + * + * Copyright (C) 2003, Intel Corporation + * Copyright (C) 2008, Sascha Hauer <s.hauer@pengutronix.de> + * Copyright (C) 2010, Baruch Siach <baruch@tkos.co.il> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_MX2_CAM_H_ +#define __MACH_MX2_CAM_H_ + +#define MX2_CAMERA_SWAP16 (1 << 0) +#define MX2_CAMERA_EXT_VSYNC (1 << 1) +#define MX2_CAMERA_CCIR (1 << 2) +#define MX2_CAMERA_CCIR_INTERLACE (1 << 3) +#define MX2_CAMERA_HSYNC_HIGH (1 << 4) +#define MX2_CAMERA_GATED_CLOCK (1 << 5) +#define MX2_CAMERA_INV_DATA (1 << 6) +#define MX2_CAMERA_PCLK_SAMPLE_RISING (1 << 7) +#define MX2_CAMERA_PACK_DIR_MSB (1 << 8) + +/** + * struct mx2_camera_platform_data - optional platform data for mx2_camera + * @flags: any combination of MX2_CAMERA_* + * @clk: clock rate of the csi block / 2 + */ +struct mx2_camera_platform_data { + unsigned long flags; + unsigned long clk; +}; + +#endif /* __MACH_MX2_CAM_H_ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index fb90e119c2b5..afee3ab9d62e 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -23,7 +23,7 @@ #define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000) #define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000) #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) -#define MX31_I2C_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) +#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) #define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) @@ -145,7 +145,7 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_FIRI 7 #define MX31_INT_MMC_SDHC2 8 #define MX31_INT_MMC_SDHC1 9 -#define MX31_INT_I2C 10 +#define MX31_INT_I2C1 10 #define MX31_INT_SSI2 11 #define MX31_INT_SSI1 12 #define MX31_INT_CSPI2 13 diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 526a55842ae5..af3038c12e39 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -18,7 +18,7 @@ #define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) #define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) #define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) -#define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) +#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) #define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) #define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) #define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) @@ -60,6 +60,8 @@ #define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000) #define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000) #define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000) +#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000) +#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) #define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) #define MX35_OTG_BASE_ADDR 0x53ff4000 @@ -123,7 +125,7 @@ #define MX35_INT_MMC_SDHC1 7 #define MX35_INT_MMC_SDHC2 8 #define MX35_INT_MMC_SDHC3 9 -#define MX35_INT_I2C 10 +#define MX35_INT_I2C1 10 #define MX35_INT_SSI1 11 #define MX35_INT_SSI2 12 #define MX35_INT_CSPI2 13 diff --git a/arch/arm/plat-mxc/include/mach/mx3_camera.h b/arch/arm/plat-mxc/include/mach/mx3_camera.h index 36d7ff27b5e2..f226ee3777e1 100644 --- a/arch/arm/plat-mxc/include/mach/mx3_camera.h +++ b/arch/arm/plat-mxc/include/mach/mx3_camera.h @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef _MX3_CAMERA_H_ diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h index 5182b986b785..0ca3101ebf36 100644 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __MACH_MXC91231_H__ #define __MACH_MXC91231_H__ diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h index 5d2d21d414e0..04c0d060d814 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_nand.h +++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h @@ -20,9 +20,13 @@ #ifndef __ASM_ARCH_NAND_H #define __ASM_ARCH_NAND_H +#include <linux/mtd/partitions.h> + struct mxc_nand_platform_data { - int width; /* data bus width in bytes */ - int hw_ecc:1; /* 0 if supress hardware ECC */ - int flash_bbt:1; /* set to 1 to use a flash based bbt */ + unsigned int width; /* data bus width in bytes */ + unsigned int hw_ecc:1; /* 0 if supress hardware ECC */ + unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */ + struct mtd_partition *parts; /* partition table */ + int nr_parts; /* size of parts */ }; #endif /* __ASM_ARCH_NAND_H */ diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index ef00199568de..4acd1143a9bd 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_ARCH_MXC_SYSTEM_H__ diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index 024416ed11cd..2d9624697cc9 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -11,10 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_ARCH_MXC_TIMEX_H__ diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index b6d3d0fddc48..d9bd37e4667a 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__ #define __ASM_ARCH_MXC_UNCOMPRESS_H__ diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h index 44243a278434..ef6379c474be 100644 --- a/arch/arm/plat-mxc/include/mach/vmalloc.h +++ b/arch/arm/plat-mxc/include/mach/vmalloc.h @@ -11,10 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_ARCH_MXC_VMALLOC_H__ diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c index 778ddfe57d89..7331f2ace5fe 100644 --- a/arch/arm/plat-mxc/irq.c +++ b/arch/arm/plat-mxc/irq.c @@ -142,9 +142,6 @@ void __init mxc_init_irq(void __iomem *irqbase) for (i = 0; i < 8; i++) __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); - /* init architectures chained interrupt handler */ - mxc_register_gpios(); - #ifdef CONFIG_FIQ /* Initialize FIQ */ init_FIQ(); diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 97f42799fa58..925bce4607e7 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -14,10 +14,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/kernel.h> diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index 9b86d2a60d43..b3da9aad4295 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -145,8 +145,6 @@ void __init tzic_init_irq(void __iomem *irqbase) set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } - mxc_register_gpios(); - pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); } diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c index 5a6ef252c38b..977c8f9a07a2 100644 --- a/arch/arm/plat-nomadik/gpio.c +++ b/arch/arm/plat-nomadik/gpio.c @@ -23,6 +23,7 @@ #include <linux/irq.h> #include <linux/slab.h> +#include <plat/pincfg.h> #include <mach/hardware.h> #include <mach/gpio.h> @@ -46,28 +47,217 @@ struct nmk_gpio_chip { u32 edge_falling; }; +static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, + unsigned offset, int gpio_mode) +{ + u32 bit = 1 << offset; + u32 afunc, bfunc; + + afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; + bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; + if (gpio_mode & NMK_GPIO_ALT_A) + afunc |= bit; + if (gpio_mode & NMK_GPIO_ALT_B) + bfunc |= bit; + writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); + writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); +} + +static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, + unsigned offset, enum nmk_gpio_slpm mode) +{ + u32 bit = 1 << offset; + u32 slpm; + + slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); + if (mode == NMK_GPIO_SLPM_NOCHANGE) + slpm |= bit; + else + slpm &= ~bit; + writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); +} + +static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, + unsigned offset, enum nmk_gpio_pull pull) +{ + u32 bit = 1 << offset; + u32 pdis; + + pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); + if (pull == NMK_GPIO_PULL_NONE) + pdis |= bit; + else + pdis &= ~bit; + writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); + + if (pull == NMK_GPIO_PULL_UP) + writel(bit, nmk_chip->addr + NMK_GPIO_DATS); + else if (pull == NMK_GPIO_PULL_DOWN) + writel(bit, nmk_chip->addr + NMK_GPIO_DATC); +} + +static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, + unsigned offset) +{ + writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); +} + +static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, + pin_cfg_t cfg) +{ + static const char *afnames[] = { + [NMK_GPIO_ALT_GPIO] = "GPIO", + [NMK_GPIO_ALT_A] = "A", + [NMK_GPIO_ALT_B] = "B", + [NMK_GPIO_ALT_C] = "C" + }; + static const char *pullnames[] = { + [NMK_GPIO_PULL_NONE] = "none", + [NMK_GPIO_PULL_UP] = "up", + [NMK_GPIO_PULL_DOWN] = "down", + [3] /* illegal */ = "??" + }; + static const char *slpmnames[] = { + [NMK_GPIO_SLPM_INPUT] = "input", + [NMK_GPIO_SLPM_NOCHANGE] = "no-change", + }; + + int pin = PIN_NUM(cfg); + int pull = PIN_PULL(cfg); + int af = PIN_ALT(cfg); + int slpm = PIN_SLPM(cfg); + + dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s\n", + pin, afnames[af], pullnames[pull], slpmnames[slpm]); + + __nmk_gpio_make_input(nmk_chip, offset); + __nmk_gpio_set_pull(nmk_chip, offset, pull); + __nmk_gpio_set_slpm(nmk_chip, offset, slpm); + __nmk_gpio_set_mode(nmk_chip, offset, af); +} + +/** + * nmk_config_pin - configure a pin's mux attributes + * @cfg: pin confguration + * + * Configures a pin's mode (alternate function or GPIO), its pull up status, + * and its sleep mode based on the specified configuration. The @cfg is + * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These + * are constructed using, and can be further enhanced with, the macros in + * plat/pincfg.h. + * + * If a pin's mode is set to GPIO, it is configured as an input to avoid + * side-effects. The gpio can be manipulated later using standard GPIO API + * calls. + */ +int nmk_config_pin(pin_cfg_t cfg) +{ + struct nmk_gpio_chip *nmk_chip; + int gpio = PIN_NUM(cfg); + unsigned long flags; + + nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + if (!nmk_chip) + return -EINVAL; + + spin_lock_irqsave(&nmk_chip->lock, flags); + __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg); + spin_unlock_irqrestore(&nmk_chip->lock, flags); + + return 0; +} +EXPORT_SYMBOL(nmk_config_pin); + +/** + * nmk_config_pins - configure several pins at once + * @cfgs: array of pin configurations + * @num: number of elments in the array + * + * Configures several pins using nmk_config_pin(). Refer to that function for + * further information. + */ +int nmk_config_pins(pin_cfg_t *cfgs, int num) +{ + int ret = 0; + int i; + + for (i = 0; i < num; i++) { + int ret = nmk_config_pin(cfgs[i]); + if (ret) + break; + } + + return ret; +} +EXPORT_SYMBOL(nmk_config_pins); + +/** + * nmk_gpio_set_slpm() - configure the sleep mode of a pin + * @gpio: pin number + * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, + * + * Sets the sleep mode of a pin. If @mode is NMK_GPIO_SLPM_INPUT, the pin is + * changed to an input (with pullup/down enabled) in sleep and deep sleep. If + * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was + * configured even when in sleep and deep sleep. + */ +int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) +{ + struct nmk_gpio_chip *nmk_chip; + unsigned long flags; + + nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + if (!nmk_chip) + return -EINVAL; + + spin_lock_irqsave(&nmk_chip->lock, flags); + __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode); + spin_unlock_irqrestore(&nmk_chip->lock, flags); + + return 0; +} + +/** + * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio + * @gpio: pin number + * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE + * + * Enables/disables pull up/down on a specified pin. This only takes effect if + * the pin is configured as an input (either explicitly or by the alternate + * function). + * + * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is + * configured as an input. Otherwise, due to the way the controller registers + * work, this function will change the value output on the pin. + */ +int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) +{ + struct nmk_gpio_chip *nmk_chip; + unsigned long flags; + + nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + if (!nmk_chip) + return -EINVAL; + + spin_lock_irqsave(&nmk_chip->lock, flags); + __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull); + spin_unlock_irqrestore(&nmk_chip->lock, flags); + + return 0; +} + /* Mode functions */ int nmk_gpio_set_mode(int gpio, int gpio_mode) { struct nmk_gpio_chip *nmk_chip; unsigned long flags; - u32 afunc, bfunc, bit; nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; - bit = 1 << (gpio - nmk_chip->chip.base); - spin_lock_irqsave(&nmk_chip->lock, flags); - afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; - bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; - if (gpio_mode & NMK_GPIO_ALT_A) - afunc |= bit; - if (gpio_mode & NMK_GPIO_ALT_B) - bfunc |= bit; - writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); - writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); + __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode); spin_unlock_irqrestore(&nmk_chip->lock, flags); return 0; @@ -111,32 +301,41 @@ static void nmk_gpio_irq_ack(unsigned int irq) writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); } +enum nmk_gpio_irq_type { + NORMAL, + WAKE, +}; + static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, - int gpio, bool enable) + int gpio, enum nmk_gpio_irq_type which, + bool enable) { + u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC; + u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC; u32 bitmask = nmk_gpio_get_bitmask(gpio); u32 reg; /* we must individually set/clear the two edges */ if (nmk_chip->edge_rising & bitmask) { - reg = readl(nmk_chip->addr + NMK_GPIO_RIMSC); + reg = readl(nmk_chip->addr + rimsc); if (enable) reg |= bitmask; else reg &= ~bitmask; - writel(reg, nmk_chip->addr + NMK_GPIO_RIMSC); + writel(reg, nmk_chip->addr + rimsc); } if (nmk_chip->edge_falling & bitmask) { - reg = readl(nmk_chip->addr + NMK_GPIO_FIMSC); + reg = readl(nmk_chip->addr + fimsc); if (enable) reg |= bitmask; else reg &= ~bitmask; - writel(reg, nmk_chip->addr + NMK_GPIO_FIMSC); + writel(reg, nmk_chip->addr + fimsc); } } -static void nmk_gpio_irq_modify(unsigned int irq, bool enable) +static int nmk_gpio_irq_modify(unsigned int irq, enum nmk_gpio_irq_type which, + bool enable) { int gpio; struct nmk_gpio_chip *nmk_chip; @@ -147,26 +346,35 @@ static void nmk_gpio_irq_modify(unsigned int irq, bool enable) nmk_chip = get_irq_chip_data(irq); bitmask = nmk_gpio_get_bitmask(gpio); if (!nmk_chip) - return; + return -EINVAL; spin_lock_irqsave(&nmk_chip->lock, flags); - __nmk_gpio_irq_modify(nmk_chip, gpio, enable); + __nmk_gpio_irq_modify(nmk_chip, gpio, which, enable); spin_unlock_irqrestore(&nmk_chip->lock, flags); + + return 0; } static void nmk_gpio_irq_mask(unsigned int irq) { - nmk_gpio_irq_modify(irq, false); -}; + nmk_gpio_irq_modify(irq, NORMAL, false); +} static void nmk_gpio_irq_unmask(unsigned int irq) { - nmk_gpio_irq_modify(irq, true); + nmk_gpio_irq_modify(irq, NORMAL, true); +} + +static int nmk_gpio_irq_set_wake(unsigned int irq, unsigned int on) +{ + return nmk_gpio_irq_modify(irq, WAKE, on); } static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type) { - bool enabled = !(irq_to_desc(irq)->status & IRQ_DISABLED); + struct irq_desc *desc = irq_to_desc(irq); + bool enabled = !(desc->status & IRQ_DISABLED); + bool wake = desc->wake_depth; int gpio; struct nmk_gpio_chip *nmk_chip; unsigned long flags; @@ -186,7 +394,10 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type) spin_lock_irqsave(&nmk_chip->lock, flags); if (enabled) - __nmk_gpio_irq_modify(nmk_chip, gpio, false); + __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false); + + if (wake) + __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false); nmk_chip->edge_rising &= ~bitmask; if (type & IRQ_TYPE_EDGE_RISING) @@ -197,7 +408,10 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type) nmk_chip->edge_falling |= bitmask; if (enabled) - __nmk_gpio_irq_modify(nmk_chip, gpio, true); + __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true); + + if (wake) + __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true); spin_unlock_irqrestore(&nmk_chip->lock, flags); @@ -210,6 +424,7 @@ static struct irq_chip nmk_gpio_irq_chip = { .mask = nmk_gpio_irq_mask, .unmask = nmk_gpio_irq_unmask, .set_type = nmk_gpio_irq_set_type, + .set_wake = nmk_gpio_irq_set_wake, }; static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) @@ -266,16 +481,6 @@ static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) return 0; } -static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, - int val) -{ - struct nmk_gpio_chip *nmk_chip = - container_of(chip, struct nmk_gpio_chip, chip); - - writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); - return 0; -} - static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) { struct nmk_gpio_chip *nmk_chip = @@ -298,12 +503,33 @@ static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, writel(bit, nmk_chip->addr + NMK_GPIO_DATC); } +static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, + int val) +{ + struct nmk_gpio_chip *nmk_chip = + container_of(chip, struct nmk_gpio_chip, chip); + + writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); + nmk_gpio_set_output(chip, offset, val); + + return 0; +} + +static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct nmk_gpio_chip *nmk_chip = + container_of(chip, struct nmk_gpio_chip, chip); + + return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset; +} + /* This structure is replicated for each GPIO block allocated at probe time */ static struct gpio_chip nmk_gpio_template = { .direction_input = nmk_gpio_make_input, .get = nmk_gpio_get_input, .direction_output = nmk_gpio_make_output, .set = nmk_gpio_set_output, + .to_irq = nmk_gpio_to_irq, .ngpio = NMK_GPIO_PER_CHIP, .can_sleep = 0, }; @@ -393,30 +619,12 @@ out: return ret; } -static int __exit nmk_gpio_remove(struct platform_device *dev) -{ - struct nmk_gpio_chip *nmk_chip; - struct resource *res; - - res = platform_get_resource(dev, IORESOURCE_MEM, 0); - - nmk_chip = platform_get_drvdata(dev); - gpiochip_remove(&nmk_chip->chip); - clk_disable(nmk_chip->clk); - clk_put(nmk_chip->clk); - kfree(nmk_chip); - release_mem_region(res->start, resource_size(res)); - return 0; -} - - static struct platform_driver nmk_gpio_driver = { .driver = { .owner = THIS_MODULE, .name = "gpio", }, .probe = nmk_gpio_probe, - .remove = __exit_p(nmk_gpio_remove), .suspend = NULL, /* to be done */ .resume = NULL, }; @@ -426,7 +634,7 @@ static int __init nmk_gpio_init(void) return platform_driver_register(&nmk_gpio_driver); } -arch_initcall(nmk_gpio_init); +core_initcall(nmk_gpio_init); MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); MODULE_DESCRIPTION("Nomadik GPIO Driver"); diff --git a/arch/arm/plat-nomadik/include/plat/gpio.h b/arch/arm/plat-nomadik/include/plat/gpio.h index 4200811249ca..aba355101f49 100644 --- a/arch/arm/plat-nomadik/include/plat/gpio.h +++ b/arch/arm/plat-nomadik/include/plat/gpio.h @@ -55,6 +55,21 @@ #define NMK_GPIO_ALT_B 2 #define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B) +/* Pull up/down values */ +enum nmk_gpio_pull { + NMK_GPIO_PULL_NONE, + NMK_GPIO_PULL_UP, + NMK_GPIO_PULL_DOWN, +}; + +/* Sleep mode */ +enum nmk_gpio_slpm { + NMK_GPIO_SLPM_INPUT, + NMK_GPIO_SLPM_NOCHANGE, +}; + +extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode); +extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull); extern int nmk_gpio_set_mode(int gpio, int gpio_mode); extern int nmk_gpio_get_mode(int gpio); diff --git a/arch/arm/plat-nomadik/include/plat/mtu.h b/arch/arm/plat-nomadik/include/plat/mtu.h index 42c907258b14..65704a3d4241 100644 --- a/arch/arm/plat-nomadik/include/plat/mtu.h +++ b/arch/arm/plat-nomadik/include/plat/mtu.h @@ -1,6 +1,12 @@ #ifndef __PLAT_MTU_H #define __PLAT_MTU_H +/* + * Guaranteed runtime conversion range in seconds for + * the clocksource and clockevent. + */ +#define MTU_MIN_RANGE 4 + /* should be set by the platform code */ extern void __iomem *mtu_base; diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h new file mode 100644 index 000000000000..7eed11c1038d --- /dev/null +++ b/arch/arm/plat-nomadik/include/plat/pincfg.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License terms: GNU General Public License, version 2 + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * + * Based on arch/arm/mach-pxa/include/mach/mfp.h: + * Copyright (C) 2007 Marvell International Ltd. + * eric miao <eric.miao@marvell.com> + */ + +#ifndef __PLAT_PINCFG_H +#define __PLAT_PINCFG_H + +/* + * pin configurations are represented by 32-bit integers: + * + * bit 0.. 8 - Pin Number (512 Pins Maximum) + * bit 9..10 - Alternate Function Selection + * bit 11..12 - Pull up/down state + * bit 13 - Sleep mode behaviour + * + * to facilitate the definition, the following macros are provided + * + * PIN_CFG_DEFAULT - default config (0): + * pull up/down = disabled + * sleep mode = input + * + * PIN_CFG - default config with alternate function + * PIN_CFG_PULL - default config with alternate function and pull up/down + */ + +typedef unsigned long pin_cfg_t; + +#define PIN_NUM_MASK 0x1ff +#define PIN_NUM(x) ((x) & PIN_NUM_MASK) + +#define PIN_ALT_SHIFT 9 +#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) +#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) +#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) +#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) +#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) +#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) + +#define PIN_PULL_SHIFT 11 +#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) +#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) +#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) +#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) +#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) + +#define PIN_SLPM_SHIFT 13 +#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) +#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) +#define PIN_SLPM_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) +#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) + +#define PIN_CFG_DEFAULT (PIN_PULL_NONE | PIN_SLPM_INPUT) + +#define PIN_CFG(num, alt) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt)) + +#define PIN_CFG_PULL(num, alt, pull) \ + ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\ + (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull)) + +extern int nmk_config_pin(pin_cfg_t cfg); +extern int nmk_config_pins(pin_cfg_t *cfgs, int num); + +#endif diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c index 08aaa4a7f65f..ea3ca86c5283 100644 --- a/arch/arm/plat-nomadik/timer.c +++ b/arch/arm/plat-nomadik/timer.c @@ -42,7 +42,6 @@ static struct clocksource nmdk_clksrc = { .rating = 200, .read = nmdk_read_timer_dummy, .mask = CLOCKSOURCE_MASK(32), - .shift = 20, .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; @@ -82,6 +81,12 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode, case CLOCK_EVT_MODE_UNUSED: /* disable irq */ writel(0, mtu_base + MTU_IMSC); + /* disable timer */ + cr = readl(mtu_base + MTU_CR(1)); + cr &= ~MTU_CRn_ENA; + writel(cr, mtu_base + MTU_CR(1)); + /* load some high default value */ + writel(0xffffffff, mtu_base + MTU_LR(1)); break; case CLOCK_EVT_MODE_RESUME: break; @@ -98,7 +103,6 @@ static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev) static struct clock_event_device nmdk_clkevt = { .name = "mtu_1", .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .rating = 200, .set_mode = nmdk_clkevt_mode, .set_next_event = nmdk_clkevt_next, @@ -151,6 +155,7 @@ void __init nmdk_timer_init(void) } else { cr |= MTU_CRn_PRESCALE_1; } + clocksource_calc_mult_shift(&nmdk_clksrc, rate, MTU_MIN_RANGE); /* Timer 0 is the free running clocksource */ writel(cr, mtu_base + MTU_CR(0)); @@ -158,7 +163,6 @@ void __init nmdk_timer_init(void) writel(0, mtu_base + MTU_BGLR(0)); writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0)); - nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift); /* Now the scheduling clock is ready */ nmdk_clksrc.read = nmdk_read_timer; @@ -175,8 +179,10 @@ void __init nmdk_timer_init(void) } else { cr |= MTU_CRn_PRESCALE_1; } + clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE); + writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */ - nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift); + nmdk_clkevt.max_delta_ns = clockevent_delta2ns(0xffffffff, &nmdk_clkevt); nmdk_clkevt.min_delta_ns = diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 219c01e82bc5..ebed82699eb2 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -22,6 +22,7 @@ #include <linux/serial_reg.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/omapfb.h> #include <mach/hardware.h> #include <asm/system.h> @@ -35,6 +36,7 @@ #include <plat/mux.h> #include <plat/fpga.h> #include <plat/serial.h> +#include <plat/vram.h> #include <plat/clock.h> @@ -81,6 +83,12 @@ const void *omap_get_var_config(u16 tag, size_t *len) } EXPORT_SYMBOL(omap_get_var_config); +void __init omap_reserve(void) +{ + omapfb_reserve_sdram_memblock(); + omap_vram_reserve_sdram_memblock(); +} + /* * 32KHz clocksource ... always available, on pretty most chips except * OMAP 730 and 1510. Other timers could be used as clocksources, with diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c index d3eea4f47533..0054b9501a53 100644 --- a/arch/arm/plat-omap/fb.c +++ b/arch/arm/plat-omap/fb.c @@ -26,7 +26,7 @@ #include <linux/mm.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/bootmem.h> +#include <linux/memblock.h> #include <linux/io.h> #include <linux/omapfb.h> @@ -171,49 +171,78 @@ static int check_fbmem_region(int region_idx, struct omapfb_mem_region *rg, return 0; } +static int valid_sdram(unsigned long addr, unsigned long size) +{ + struct memblock_property res; + + res.base = addr; + res.size = size; + return !memblock_find(&res) && res.base == addr && res.size == size; +} + +static int reserve_sdram(unsigned long addr, unsigned long size) +{ + if (memblock_is_region_reserved(addr, size)) + return -EBUSY; + if (memblock_reserve(addr, size)) + return -ENOMEM; + return 0; +} + /* * Called from map_io. We need to call to this early enough so that we * can reserve the fixed SDRAM regions before VM could get hold of them. */ -void __init omapfb_reserve_sdram(void) +void __init omapfb_reserve_sdram_memblock(void) { - struct bootmem_data *bdata; - unsigned long sdram_start, sdram_size; - unsigned long reserved; - int i; + unsigned long reserved = 0; + int i; if (config_invalid) return; - bdata = NODE_DATA(0)->bdata; - sdram_start = bdata->node_min_pfn << PAGE_SHIFT; - sdram_size = (bdata->node_low_pfn << PAGE_SHIFT) - sdram_start; - reserved = 0; for (i = 0; ; i++) { - struct omapfb_mem_region rg; + struct omapfb_mem_region rg; if (get_fbmem_region(i, &rg) < 0) break; + if (i == OMAPFB_PLANE_NUM) { - printk(KERN_ERR - "Extraneous FB mem configuration entries\n"); + pr_err("Extraneous FB mem configuration entries\n"); config_invalid = 1; return; } + /* Check if it's our memory type. */ - if (set_fbmem_region_type(&rg, OMAPFB_MEMTYPE_SDRAM, - sdram_start, sdram_size) < 0 || - (rg.type != OMAPFB_MEMTYPE_SDRAM)) + if (rg.type != OMAPFB_MEMTYPE_SDRAM) continue; - BUG_ON(omapfb_config.mem_desc.region[i].size); - if (check_fbmem_region(i, &rg, sdram_start, sdram_size) < 0) { + + /* Check if the region falls within SDRAM */ + if (rg.paddr && !valid_sdram(rg.paddr, rg.size)) + continue; + + if (rg.size == 0) { + pr_err("Zero size for FB region %d\n", i); config_invalid = 1; return; } + if (rg.paddr) { - reserve_bootmem(rg.paddr, rg.size, BOOTMEM_DEFAULT); + if (reserve_sdram(rg.paddr, rg.size)) { + pr_err("Trying to use reserved memory for FB region %d\n", + i); + config_invalid = 1; + return; + } reserved += rg.size; } + + if (omapfb_config.mem_desc.region[i].size) { + pr_err("FB region %d already set\n", i); + config_invalid = 1; + return; + } + omapfb_config.mem_desc.region[i] = rg; configured_regions++; } @@ -359,7 +388,10 @@ static inline int omap_init_fb(void) arch_initcall(omap_init_fb); -void omapfb_reserve_sdram(void) {} +void omapfb_reserve_sdram_memblock(void) +{ +} + unsigned long omapfb_reserve_sram(unsigned long sram_pstart, unsigned long sram_vstart, unsigned long sram_size, @@ -375,7 +407,10 @@ void omapfb_set_platform_data(struct omapfb_platform_data *data) { } -void omapfb_reserve_sdram(void) {} +void omapfb_reserve_sdram_memblock(void) +{ +} + unsigned long omapfb_reserve_sram(unsigned long sram_pstart, unsigned long sram_vstart, unsigned long sram_size, diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index d265018f5e6b..5e4afbee0fd7 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -34,6 +34,8 @@ struct sys_timer; extern void omap_map_common_io(void); extern struct sys_timer omap_timer; +extern void omap_reserve(void); + /* * IO bases for various OMAP processors * Except the tap base, rest all the io bases diff --git a/arch/arm/plat-omap/include/plat/vram.h b/arch/arm/plat-omap/include/plat/vram.h index edd4987758a6..0aa4ecd12c7d 100644 --- a/arch/arm/plat-omap/include/plat/vram.h +++ b/arch/arm/plat-omap/include/plat/vram.h @@ -38,7 +38,7 @@ extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram, extern void omap_vram_set_sdram_vram(u32 size, u32 start); extern void omap_vram_set_sram_vram(u32 size, u32 start); -extern void omap_vram_reserve_sdram(void); +extern void omap_vram_reserve_sdram_memblock(void); extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart, unsigned long sram_vstart, unsigned long sram_size, @@ -48,7 +48,7 @@ extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart, static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { } static inline void omap_vram_set_sram_vram(u32 size, u32 start) { } -static inline void omap_vram_reserve_sdram(void) { } +static inline void omap_vram_reserve_sdram_memblock(void) { } static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart, unsigned long sram_vstart, unsigned long sram_size, diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c index 54c84a492a0f..779553a1595e 100644 --- a/arch/arm/plat-orion/pcie.c +++ b/arch/arm/plat-orion/pcie.c @@ -13,6 +13,7 @@ #include <linux/mbus.h> #include <asm/mach/pci.h> #include <plat/pcie.h> +#include <linux/delay.h> /* * PCIe unit register offsets. @@ -46,6 +47,8 @@ #define PCIE_STAT_BUS_OFFS 8 #define PCIE_STAT_BUS_MASK 0xff #define PCIE_STAT_LINK_DOWN 1 +#define PCIE_DEBUG_CTRL 0x1a60 +#define PCIE_DEBUG_SOFT_RESET (1<<20) u32 __init orion_pcie_dev_id(void __iomem *base) @@ -85,6 +88,32 @@ void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr) writel(stat, base + PCIE_STAT_OFF); } +void __init orion_pcie_reset(void __iomem *base) +{ + u32 reg; + int i; + + /* + * MV-S104860-U0, Rev. C: + * PCI Express Unit Soft Reset + * When set, generates an internal reset in the PCI Express unit. + * This bit should be cleared after the link is re-established. + */ + reg = readl(base + PCIE_DEBUG_CTRL); + reg |= PCIE_DEBUG_SOFT_RESET; + writel(reg, base + PCIE_DEBUG_CTRL); + + for (i = 0; i < 20; i++) { + mdelay(10); + + if (orion_pcie_link_up(base)) + break; + } + + reg &= ~(PCIE_DEBUG_SOFT_RESET); + writel(reg, base + PCIE_DEBUG_CTRL); +} + /* * Setup PCIE BARs and Address Decode Wins: * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks @@ -153,6 +182,11 @@ void __init orion_pcie_setup(void __iomem *base, u32 mask; /* + * soft reset PCIe unit + */ + orion_pcie_reset(base); + + /* * Point PCIe unit MBUS decode windows to DRAM space. */ orion_pcie_setup_wins(base, dram); diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c index a1025d38f383..ab211652e4ca 100644 --- a/arch/arm/plat-spear/time.c +++ b/arch/arm/plat-spear/time.c @@ -58,6 +58,11 @@ #define INT_STATUS 0x1 +/* + * Minimum clocksource/clockevent timer range in seconds + */ +#define SPEAR_MIN_RANGE 4 + static __iomem void *gpt_base; static struct clk *gpt_clk; @@ -66,44 +71,6 @@ static void clockevent_set_mode(enum clock_event_mode mode, static int clockevent_next_event(unsigned long evt, struct clock_event_device *clk_event_dev); -/* - * Following clocksource_set_clock and clockevent_set_clock picked - * from arch/mips/kernel/time.c - */ - -void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock) -{ - u64 temp; - u32 shift; - - /* Find a shift value */ - for (shift = 32; shift > 0; shift--) { - temp = (u64) NSEC_PER_SEC << shift; - do_div(temp, clock); - if ((temp >> 32) == 0) - break; - } - cs->shift = shift; - cs->mult = (u32) temp; -} - -void __init clockevent_set_clock(struct clock_event_device *cd, - unsigned int clock) -{ - u64 temp; - u32 shift; - - /* Find a shift value */ - for (shift = 32; shift > 0; shift--) { - temp = (u64) clock << shift; - do_div(temp, NSEC_PER_SEC); - if ((temp >> 32) == 0) - break; - } - cd->shift = shift; - cd->mult = (u32) temp; -} - static cycle_t clocksource_read_cycles(struct clocksource *cs) { return (cycle_t) readw(gpt_base + COUNT(CLKSRC)); @@ -138,7 +105,7 @@ static void spear_clocksource_init(void) val |= CTRL_ENABLE ; writew(val, gpt_base + CR(CLKSRC)); - clocksource_set_clock(&clksrc, tick_rate); + clocksource_calc_mult_shift(&clksrc, tick_rate, SPEAR_MIN_RANGE); /* register the clocksource */ clocksource_register(&clksrc); @@ -233,7 +200,7 @@ static void __init spear_clockevent_init(void) tick_rate = clk_get_rate(gpt_clk); tick_rate >>= CTRL_PRESCALER16; - clockevent_set_clock(&clkevt, tick_rate); + clockevents_calc_mult_shift(&clkevt, tick_rate, SPEAR_MIN_RANGE); clkevt.max_delta_ns = clockevent_delta2ns(0xfff0, &clkevt); diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile index 9b1a66816aa6..5cf88e8427b1 100644 --- a/arch/arm/plat-versatile/Makefile +++ b/arch/arm/plat-versatile/Makefile @@ -2,3 +2,7 @@ obj-y := clock.o obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o obj-$(CONFIG_ARCH_REALVIEW) += sched-clock.o obj-$(CONFIG_ARCH_VERSATILE) += sched-clock.o +ifeq ($(CONFIG_LEDS_CLASS),y) +obj-$(CONFIG_ARCH_REALVIEW) += leds.o +obj-$(CONFIG_ARCH_VERSATILE) += leds.o +endif diff --git a/arch/arm/plat-versatile/leds.c b/arch/arm/plat-versatile/leds.c new file mode 100644 index 000000000000..3169fa555ea6 --- /dev/null +++ b/arch/arm/plat-versatile/leds.c @@ -0,0 +1,103 @@ +/* + * Driver for the 8 user LEDs found on the RealViews and Versatiles + * Based on DaVinci's DM365 board code + * + * License terms: GNU General Public License (GPL) version 2 + * Author: Linus Walleij <triad@df.lth.se> + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/leds.h> + +#include <mach/hardware.h> +#include <mach/platform.h> + +#ifdef VERSATILE_SYS_BASE +#define LEDREG (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET) +#endif + +#ifdef REALVIEW_SYS_BASE +#define LEDREG (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET) +#endif + +struct versatile_led { + struct led_classdev cdev; + u8 mask; +}; + +/* + * The triggers lines up below will only be used if the + * LED triggers are compiled in. + */ +static const struct { + const char *name; + const char *trigger; +} versatile_leds[] = { + { "versatile:0", "heartbeat", }, + { "versatile:1", "mmc0", }, + { "versatile:2", }, + { "versatile:3", }, + { "versatile:4", }, + { "versatile:5", }, + { "versatile:6", }, + { "versatile:7", }, +}; + +static void versatile_led_set(struct led_classdev *cdev, + enum led_brightness b) +{ + struct versatile_led *led = container_of(cdev, + struct versatile_led, cdev); + u32 reg = readl(LEDREG); + + if (b != LED_OFF) + reg |= led->mask; + else + reg &= ~led->mask; + writel(reg, LEDREG); +} + +static enum led_brightness versatile_led_get(struct led_classdev *cdev) +{ + struct versatile_led *led = container_of(cdev, + struct versatile_led, cdev); + u32 reg = readl(LEDREG); + + return (reg & led->mask) ? LED_FULL : LED_OFF; +} + +static int __init versatile_leds_init(void) +{ + int i; + + /* All ON */ + writel(0xff, LEDREG); + for (i = 0; i < ARRAY_SIZE(versatile_leds); i++) { + struct versatile_led *led; + + led = kzalloc(sizeof(*led), GFP_KERNEL); + if (!led) + break; + + led->cdev.name = versatile_leds[i].name; + led->cdev.brightness_set = versatile_led_set; + led->cdev.brightness_get = versatile_led_get; + led->cdev.default_trigger = versatile_leds[i].trigger; + led->mask = BIT(i); + + if (led_classdev_register(NULL, &led->cdev) < 0) { + kfree(led); + break; + } + } + + return 0; +} + +/* + * Since we may have triggers on any subsystem, defer registration + * until after subsystem_init. + */ +fs_initcall(versatile_leds_init); diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 315a540c7ce5..8063a322c790 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -15,6 +15,7 @@ #include <linux/sched.h> #include <linux/init.h> +#include <asm/cputype.h> #include <asm/thread_notify.h> #include <asm/vfp.h> @@ -549,10 +550,13 @@ static int __init vfp_init(void) /* * Check for the presence of the Advanced SIMD * load/store instructions, integer and single - * precision floating point operations. + * precision floating point operations. Only check + * for NEON if the hardware has the MVFR registers. */ - if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100) - elf_hwcap |= HWCAP_NEON; + if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) { + if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100) + elf_hwcap |= HWCAP_NEON; + } #endif } return 0; diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S index d5e3e6007447..bea9ee37ac9d 100644 --- a/arch/s390/kernel/entry.S +++ b/arch/s390/kernel/entry.S @@ -535,8 +535,16 @@ pgm_no_vtime2: l %r3,__LC_PGM_ILC # load program interruption code la %r8,0x7f nr %r8,%r3 # clear per-event-bit and ilc - be BASED(pgm_exit) # only per or per+check ? - b BASED(pgm_do_call) + be BASED(pgm_exit2) # only per or per+check ? + l %r7,BASED(.Ljump_table) + sll %r8,2 + l %r7,0(%r8,%r7) # load address of handler routine + la %r2,SP_PTREGS(%r15) # address of register-save area + basr %r14,%r7 # branch to interrupt-handler +pgm_exit2: + TRACE_IRQS_ON + stosm __SF_EMPTY(%r15),0x03 # reenable interrupts + b BASED(sysc_return) # # it was a single stepped SVC that is causing all the trouble diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S index e7192e1cb678..8bccec15ea90 100644 --- a/arch/s390/kernel/entry64.S +++ b/arch/s390/kernel/entry64.S @@ -544,8 +544,16 @@ pgm_no_vtime2: lgf %r3,__LC_PGM_ILC # load program interruption code lghi %r8,0x7f ngr %r8,%r3 # clear per-event-bit and ilc - je pgm_exit - j pgm_do_call + je pgm_exit2 + sll %r8,3 + larl %r1,pgm_check_table + lg %r1,0(%r8,%r1) # load address of handler routine + la %r2,SP_PTREGS(%r15) # address of register-save area + basr %r14,%r1 # branch to interrupt-handler +pgm_exit2: + TRACE_IRQS_ON + stosm __SF_EMPTY(%r15),0x03 # reenable interrupts + j sysc_return # # it was a single stepped SVC that is causing all the trouble diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c index a2163c95eb98..15a7536452d5 100644 --- a/arch/s390/kernel/time.c +++ b/arch/s390/kernel/time.c @@ -524,8 +524,11 @@ void etr_switch_to_local(void) if (!etr_eacr.sl) return; disable_sync_clock(NULL); - set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events); - queue_work(time_sync_wq, &etr_work); + if (!test_and_set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) { + etr_eacr.es = etr_eacr.sl = 0; + etr_setr(&etr_eacr); + queue_work(time_sync_wq, &etr_work); + } } /* @@ -539,8 +542,11 @@ void etr_sync_check(void) if (!etr_eacr.es) return; disable_sync_clock(NULL); - set_bit(ETR_EVENT_SYNC_CHECK, &etr_events); - queue_work(time_sync_wq, &etr_work); + if (!test_and_set_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) { + etr_eacr.es = 0; + etr_setr(&etr_eacr); + queue_work(time_sync_wq, &etr_work); + } } /* @@ -902,7 +908,7 @@ static struct etr_eacr etr_handle_update(struct etr_aib *aib, * Do not try to get the alternate port aib if the clock * is not in sync yet. */ - if (!check_sync_clock()) + if (!eacr.es || !check_sync_clock()) return eacr; /* @@ -1064,7 +1070,7 @@ static void etr_work_fn(struct work_struct *work) * If the clock is in sync just update the eacr and return. * If there is no valid sync port wait for a port update. */ - if (check_sync_clock() || sync_port < 0) { + if ((eacr.es && check_sync_clock()) || sync_port < 0) { etr_update_eacr(eacr); etr_set_tolec_timeout(now); goto out_unlock; diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index f60b2b6a0931..d31590e7011b 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -122,6 +122,31 @@ static int __init amba_init(void) postcore_initcall(amba_init); +static int amba_get_enable_pclk(struct amba_device *pcdev) +{ + struct clk *pclk = clk_get(&pcdev->dev, "apb_pclk"); + int ret; + + pcdev->pclk = pclk; + + if (IS_ERR(pclk)) + return PTR_ERR(pclk); + + ret = clk_enable(pclk); + if (ret) + clk_put(pclk); + + return ret; +} + +static void amba_put_disable_pclk(struct amba_device *pcdev) +{ + struct clk *pclk = pcdev->pclk; + + clk_disable(pclk); + clk_put(pclk); +} + /* * These are the device model conversion veneers; they convert the * device model structures to our more specific structures. @@ -130,17 +155,33 @@ static int amba_probe(struct device *dev) { struct amba_device *pcdev = to_amba_device(dev); struct amba_driver *pcdrv = to_amba_driver(dev->driver); - struct amba_id *id; + struct amba_id *id = amba_lookup(pcdrv->id_table, pcdev); + int ret; - id = amba_lookup(pcdrv->id_table, pcdev); + do { + ret = amba_get_enable_pclk(pcdev); + if (ret) + break; + + ret = pcdrv->probe(pcdev, id); + if (ret == 0) + break; - return pcdrv->probe(pcdev, id); + amba_put_disable_pclk(pcdev); + } while (0); + + return ret; } static int amba_remove(struct device *dev) { + struct amba_device *pcdev = to_amba_device(dev); struct amba_driver *drv = to_amba_driver(dev->driver); - return drv->remove(to_amba_device(dev)); + int ret = drv->remove(pcdev); + + amba_put_disable_pclk(pcdev); + + return ret; } static void amba_shutdown(struct device *dev) @@ -203,7 +244,6 @@ static void amba_device_release(struct device *dev) */ int amba_device_register(struct amba_device *dev, struct resource *parent) { - u32 pid, cid; u32 size; void __iomem *tmp; int i, ret; @@ -241,25 +281,35 @@ int amba_device_register(struct amba_device *dev, struct resource *parent) goto err_release; } - /* - * Read pid and cid based on size of resource - * they are located at end of region - */ - for (pid = 0, i = 0; i < 4; i++) - pid |= (readl(tmp + size - 0x20 + 4 * i) & 255) << (i * 8); - for (cid = 0, i = 0; i < 4; i++) - cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << (i * 8); + ret = amba_get_enable_pclk(dev); + if (ret == 0) { + u32 pid, cid; - iounmap(tmp); + /* + * Read pid and cid based on size of resource + * they are located at end of region + */ + for (pid = 0, i = 0; i < 4; i++) + pid |= (readl(tmp + size - 0x20 + 4 * i) & 255) << + (i * 8); + for (cid = 0, i = 0; i < 4; i++) + cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << + (i * 8); - if (cid == 0xb105f00d) - dev->periphid = pid; + amba_put_disable_pclk(dev); - if (!dev->periphid) { - ret = -ENODEV; - goto err_release; + if (cid == 0xb105f00d) + dev->periphid = pid; + + if (!dev->periphid) + ret = -ENODEV; } + iounmap(tmp); + + if (ret) + goto err_release; + ret = device_add(&dev->dev); if (ret) goto err_release; diff --git a/drivers/gpio/pl061.c b/drivers/gpio/pl061.c index ee568c8fcbd0..5005990f751f 100644 --- a/drivers/gpio/pl061.c +++ b/drivers/gpio/pl061.c @@ -232,7 +232,7 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc) desc->chip->unmask(irq); } -static int __init pl061_probe(struct amba_device *dev, struct amba_id *id) +static int pl061_probe(struct amba_device *dev, struct amba_id *id) { struct pl061_platform_data *pdata; struct pl061_gpio *chip; @@ -333,7 +333,7 @@ free_mem: return ret; } -static struct amba_id pl061_ids[] __initdata = { +static struct amba_id pl061_ids[] = { { .id = 0x00041061, .mask = 0x000fffff, diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index c1981861bbbd..f87bf104df7a 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -864,8 +864,8 @@ drm_mode_std(struct drm_connector *connector, struct edid *edid, mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, false); mode->hdisplay = 1366; - mode->vsync_start = mode->vsync_start - 1; - mode->vsync_end = mode->vsync_end - 1; + mode->hsync_start = mode->hsync_start - 1; + mode->hsync_end = mode->hsync_end - 1; return mode; } diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 115d26b762cc..3fa6984d9896 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -333,6 +333,7 @@ static ssize_t radeon_get_pm_profile(struct device *dev, return snprintf(buf, PAGE_SIZE, "%s\n", (cp == PM_PROFILE_AUTO) ? "auto" : (cp == PM_PROFILE_LOW) ? "low" : + (cp == PM_PROFILE_MID) ? "mid" : (cp == PM_PROFILE_HIGH) ? "high" : "default"); } diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 81bf25e67ce1..e4112622e5a2 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -302,6 +302,15 @@ config LEDS_MC13783 This option enable support for on-chip LED drivers found on Freescale Semiconductor MC13783 PMIC. +config LEDS_NS2 + tristate "LED support for Network Space v2 GPIO LEDs" + depends on MACH_NETSPACE_V2 || MACH_INETSPACE_V2 || MACH_NETSPACE_MAX_V2 + default y + help + This option enable support for the dual-GPIO LED found on the + Network Space v2 board (and parents). This include Internet Space v2, + Network Space (Max) v2 and d2 Network v2 boards. + config LEDS_TRIGGERS bool "LED Trigger support" help diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index 2493de499374..7d6b95831f8e 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o obj-$(CONFIG_LEDS_DELL_NETBOOKS) += dell-led.o obj-$(CONFIG_LEDS_MC13783) += leds-mc13783.o +obj-$(CONFIG_LEDS_NS2) += leds-ns2.o # LED SPI Drivers obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o diff --git a/drivers/leds/leds-ns2.c b/drivers/leds/leds-ns2.c new file mode 100644 index 000000000000..74dce4ba0262 --- /dev/null +++ b/drivers/leds/leds-ns2.c @@ -0,0 +1,338 @@ +/* + * leds-ns2.c - Driver for the Network Space v2 (and parents) dual-GPIO LED + * + * Copyright (C) 2010 LaCie + * + * Author: Simon Guinot <sguinot@lacie.com> + * + * Based on leds-gpio.c by Raphael Assenat <raph@8d.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/gpio.h> +#include <linux/leds.h> +#include <mach/leds-ns2.h> + +/* + * The Network Space v2 dual-GPIO LED is wired to a CPLD and can blink in + * relation with the SATA activity. This capability is exposed through the + * "sata" sysfs attribute. + * + * The following array detail the different LED registers and the combination + * of their possible values: + * + * cmd_led | slow_led | /SATA active | LED state + * | | | + * 1 | 0 | x | off + * - | 1 | x | on + * 0 | 0 | 1 | on + * 0 | 0 | 0 | blink (rate 300ms) + */ + +enum ns2_led_modes { + NS_V2_LED_OFF, + NS_V2_LED_ON, + NS_V2_LED_SATA, +}; + +struct ns2_led_mode_value { + enum ns2_led_modes mode; + int cmd_level; + int slow_level; +}; + +static struct ns2_led_mode_value ns2_led_modval[] = { + { NS_V2_LED_OFF , 1, 0 }, + { NS_V2_LED_ON , 0, 1 }, + { NS_V2_LED_ON , 1, 1 }, + { NS_V2_LED_SATA, 0, 0 }, +}; + +struct ns2_led_data { + struct led_classdev cdev; + unsigned cmd; + unsigned slow; + unsigned char sata; /* True when SATA mode active. */ + rwlock_t rw_lock; /* Lock GPIOs. */ +}; + +static int ns2_led_get_mode(struct ns2_led_data *led_dat, + enum ns2_led_modes *mode) +{ + int i; + int ret = -EINVAL; + int cmd_level; + int slow_level; + + read_lock(&led_dat->rw_lock); + + cmd_level = gpio_get_value(led_dat->cmd); + slow_level = gpio_get_value(led_dat->slow); + + for (i = 0; i < ARRAY_SIZE(ns2_led_modval); i++) { + if (cmd_level == ns2_led_modval[i].cmd_level && + slow_level == ns2_led_modval[i].slow_level) { + *mode = ns2_led_modval[i].mode; + ret = 0; + break; + } + } + + read_unlock(&led_dat->rw_lock); + + return ret; +} + +static void ns2_led_set_mode(struct ns2_led_data *led_dat, + enum ns2_led_modes mode) +{ + int i; + + write_lock(&led_dat->rw_lock); + + for (i = 0; i < ARRAY_SIZE(ns2_led_modval); i++) { + if (mode == ns2_led_modval[i].mode) { + gpio_set_value(led_dat->cmd, + ns2_led_modval[i].cmd_level); + gpio_set_value(led_dat->slow, + ns2_led_modval[i].slow_level); + } + } + + write_unlock(&led_dat->rw_lock); +} + +static void ns2_led_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + struct ns2_led_data *led_dat = + container_of(led_cdev, struct ns2_led_data, cdev); + enum ns2_led_modes mode; + + if (value == LED_OFF) + mode = NS_V2_LED_OFF; + else if (led_dat->sata) + mode = NS_V2_LED_SATA; + else + mode = NS_V2_LED_ON; + + ns2_led_set_mode(led_dat, mode); +} + +static ssize_t ns2_led_sata_store(struct device *dev, + struct device_attribute *attr, + const char *buff, size_t count) +{ + int ret; + unsigned long enable; + enum ns2_led_modes mode; + struct ns2_led_data *led_dat = dev_get_drvdata(dev); + + ret = strict_strtoul(buff, 10, &enable); + if (ret < 0) + return ret; + + enable = !!enable; + + if (led_dat->sata == enable) + return count; + + ret = ns2_led_get_mode(led_dat, &mode); + if (ret < 0) + return ret; + + if (enable && mode == NS_V2_LED_ON) + ns2_led_set_mode(led_dat, NS_V2_LED_SATA); + if (!enable && mode == NS_V2_LED_SATA) + ns2_led_set_mode(led_dat, NS_V2_LED_ON); + + led_dat->sata = enable; + + return count; +} + +static ssize_t ns2_led_sata_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ns2_led_data *led_dat = dev_get_drvdata(dev); + + return sprintf(buf, "%d\n", led_dat->sata); +} + +static DEVICE_ATTR(sata, 0644, ns2_led_sata_show, ns2_led_sata_store); + +static int __devinit +create_ns2_led(struct platform_device *pdev, struct ns2_led_data *led_dat, + const struct ns2_led *template) +{ + int ret; + enum ns2_led_modes mode; + + ret = gpio_request(template->cmd, template->name); + if (ret == 0) { + ret = gpio_direction_output(template->cmd, + gpio_get_value(template->cmd)); + if (ret) + gpio_free(template->cmd); + } + if (ret) { + dev_err(&pdev->dev, "%s: failed to setup command GPIO\n", + template->name); + } + + ret = gpio_request(template->slow, template->name); + if (ret == 0) { + ret = gpio_direction_output(template->slow, + gpio_get_value(template->slow)); + if (ret) + gpio_free(template->slow); + } + if (ret) { + dev_err(&pdev->dev, "%s: failed to setup slow GPIO\n", + template->name); + goto err_free_cmd; + } + + rwlock_init(&led_dat->rw_lock); + + led_dat->cdev.name = template->name; + led_dat->cdev.default_trigger = template->default_trigger; + led_dat->cdev.blink_set = NULL; + led_dat->cdev.brightness_set = ns2_led_set; + led_dat->cdev.flags |= LED_CORE_SUSPENDRESUME; + led_dat->cmd = template->cmd; + led_dat->slow = template->slow; + + ret = ns2_led_get_mode(led_dat, &mode); + if (ret < 0) + goto err_free_slow; + + /* Set LED initial state. */ + led_dat->sata = (mode == NS_V2_LED_SATA) ? 1 : 0; + led_dat->cdev.brightness = + (mode == NS_V2_LED_OFF) ? LED_OFF : LED_FULL; + + ret = led_classdev_register(&pdev->dev, &led_dat->cdev); + if (ret < 0) + goto err_free_slow; + + dev_set_drvdata(led_dat->cdev.dev, led_dat); + ret = device_create_file(led_dat->cdev.dev, &dev_attr_sata); + if (ret < 0) + goto err_free_cdev; + + return 0; + +err_free_cdev: + led_classdev_unregister(&led_dat->cdev); +err_free_slow: + gpio_free(led_dat->slow); +err_free_cmd: + gpio_free(led_dat->cmd); + + return ret; +} + +static void __devexit delete_ns2_led(struct ns2_led_data *led_dat) +{ + device_remove_file(led_dat->cdev.dev, &dev_attr_sata); + led_classdev_unregister(&led_dat->cdev); + gpio_free(led_dat->cmd); + gpio_free(led_dat->slow); +} + +static int __devinit ns2_led_probe(struct platform_device *pdev) +{ + struct ns2_led_platform_data *pdata = pdev->dev.platform_data; + struct ns2_led_data *leds_data; + int i; + int ret; + + if (!pdata) + return -EINVAL; + + leds_data = kzalloc(sizeof(struct ns2_led_data) * + pdata->num_leds, GFP_KERNEL); + if (!leds_data) + return -ENOMEM; + + for (i = 0; i < pdata->num_leds; i++) { + ret = create_ns2_led(pdev, &leds_data[i], &pdata->leds[i]); + if (ret < 0) + goto err; + + } + + platform_set_drvdata(pdev, leds_data); + + return 0; + +err: + for (i = i - 1; i >= 0; i--) + delete_ns2_led(&leds_data[i]); + + kfree(leds_data); + + return ret; +} + +static int __devexit ns2_led_remove(struct platform_device *pdev) +{ + int i; + struct ns2_led_platform_data *pdata = pdev->dev.platform_data; + struct ns2_led_data *leds_data; + + leds_data = platform_get_drvdata(pdev); + + for (i = 0; i < pdata->num_leds; i++) + delete_ns2_led(&leds_data[i]); + + kfree(leds_data); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_driver ns2_led_driver = { + .probe = ns2_led_probe, + .remove = __devexit_p(ns2_led_remove), + .driver = { + .name = "leds-ns2", + .owner = THIS_MODULE, + }, +}; +MODULE_ALIAS("platform:leds-ns2"); + +static int __init ns2_led_init(void) +{ + return platform_driver_register(&ns2_led_driver); +} + +static void __exit ns2_led_exit(void) +{ + platform_driver_unregister(&ns2_led_driver); +} + +module_init(ns2_led_init); +module_exit(ns2_led_exit); + +MODULE_AUTHOR("Simon Guinot <sguinot@lacie.com>"); +MODULE_DESCRIPTION("Network Space v2 LED driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig index bdbc9d305419..27e2acce3c3a 100644 --- a/drivers/media/video/Kconfig +++ b/drivers/media/video/Kconfig @@ -969,6 +969,19 @@ config VIDEO_OMAP2 ---help--- This is a v4l2 driver for the TI OMAP2 camera capture interface +config VIDEO_MX2_HOSTSUPPORT + bool + +config VIDEO_MX2 + tristate "i.MX27/i.MX25 Camera Sensor Interface driver" + depends on VIDEO_DEV && SOC_CAMERA && (MACH_MX27 || ARCH_MX25) + select VIDEOBUF_DMA_CONTIG + select VIDEO_MX2_HOSTSUPPORT + ---help--- + This is a v4l2 driver for the i.MX27 and the i.MX25 Camera Sensor + Interface + + # # USB Multimedia device configuration # diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile index cc93859d3164..b08bd2b65cd0 100644 --- a/drivers/media/video/Makefile +++ b/drivers/media/video/Makefile @@ -162,6 +162,7 @@ obj-$(CONFIG_SOC_CAMERA) += soc_camera.o soc_mediabus.o obj-$(CONFIG_SOC_CAMERA_PLATFORM) += soc_camera_platform.o # soc-camera host drivers have to be linked after camera drivers obj-$(CONFIG_VIDEO_MX1) += mx1_camera.o +obj-$(CONFIG_VIDEO_MX2) += mx2_camera.o obj-$(CONFIG_VIDEO_MX3) += mx3_camera.o obj-$(CONFIG_VIDEO_PXA27x) += pxa_camera.o obj-$(CONFIG_VIDEO_SH_MOBILE_CEU) += sh_mobile_ceu_camera.o diff --git a/drivers/media/video/mx2_camera.c b/drivers/media/video/mx2_camera.c new file mode 100644 index 000000000000..026bef0ba403 --- /dev/null +++ b/drivers/media/video/mx2_camera.c @@ -0,0 +1,1513 @@ +/* + * V4L2 Driver for i.MX27/i.MX25 camera host + * + * Copyright (C) 2008, Sascha Hauer, Pengutronix + * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/dma-mapping.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/moduleparam.h> +#include <linux/time.h> +#include <linux/version.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/mutex.h> +#include <linux/clk.h> + +#include <media/v4l2-common.h> +#include <media/v4l2-dev.h> +#include <media/videobuf-dma-contig.h> +#include <media/soc_camera.h> +#include <media/soc_mediabus.h> + +#include <linux/videodev2.h> + +#include <mach/mx2_cam.h> +#ifdef CONFIG_MACH_MX27 +#include <mach/dma-mx1-mx2.h> +#endif +#include <mach/hardware.h> + +#include <asm/dma.h> + +#define MX2_CAM_DRV_NAME "mx2-camera" +#define MX2_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) +#define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera" + +/* reset values */ +#define CSICR1_RESET_VAL 0x40000800 +#define CSICR2_RESET_VAL 0x0 +#define CSICR3_RESET_VAL 0x0 + +/* csi control reg 1 */ +#define CSICR1_SWAP16_EN (1 << 31) +#define CSICR1_EXT_VSYNC (1 << 30) +#define CSICR1_EOF_INTEN (1 << 29) +#define CSICR1_PRP_IF_EN (1 << 28) +#define CSICR1_CCIR_MODE (1 << 27) +#define CSICR1_COF_INTEN (1 << 26) +#define CSICR1_SF_OR_INTEN (1 << 25) +#define CSICR1_RF_OR_INTEN (1 << 24) +#define CSICR1_STATFF_LEVEL (3 << 22) +#define CSICR1_STATFF_INTEN (1 << 21) +#define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */ +#define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */ +#define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */ +#define CSICR1_RXFF_INTEN (1 << 18) +#define CSICR1_SOF_POL (1 << 17) +#define CSICR1_SOF_INTEN (1 << 16) +#define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12) +#define CSICR1_HSYNC_POL (1 << 11) +#define CSICR1_CCIR_EN (1 << 10) +#define CSICR1_MCLKEN (1 << 9) +#define CSICR1_FCC (1 << 8) +#define CSICR1_PACK_DIR (1 << 7) +#define CSICR1_CLR_STATFIFO (1 << 6) +#define CSICR1_CLR_RXFIFO (1 << 5) +#define CSICR1_GCLK_MODE (1 << 4) +#define CSICR1_INV_DATA (1 << 3) +#define CSICR1_INV_PCLK (1 << 2) +#define CSICR1_REDGE (1 << 1) + +#define SHIFT_STATFF_LEVEL 22 +#define SHIFT_RXFF_LEVEL 19 +#define SHIFT_MCLKDIV 12 + +/* control reg 3 */ +#define CSICR3_FRMCNT (0xFFFF << 16) +#define CSICR3_FRMCNT_RST (1 << 15) +#define CSICR3_DMA_REFLASH_RFF (1 << 14) +#define CSICR3_DMA_REFLASH_SFF (1 << 13) +#define CSICR3_DMA_REQ_EN_RFF (1 << 12) +#define CSICR3_DMA_REQ_EN_SFF (1 << 11) +#define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */ +#define CSICR3_CSI_SUP (1 << 3) +#define CSICR3_ZERO_PACK_EN (1 << 2) +#define CSICR3_ECC_INT_EN (1 << 1) +#define CSICR3_ECC_AUTO_EN (1 << 0) + +#define SHIFT_FRMCNT 16 + +/* csi status reg */ +#define CSISR_SFF_OR_INT (1 << 25) +#define CSISR_RFF_OR_INT (1 << 24) +#define CSISR_STATFF_INT (1 << 21) +#define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */ +#define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */ +#define CSISR_RXFF_INT (1 << 18) +#define CSISR_EOF_INT (1 << 17) +#define CSISR_SOF_INT (1 << 16) +#define CSISR_F2_INT (1 << 15) +#define CSISR_F1_INT (1 << 14) +#define CSISR_COF_INT (1 << 13) +#define CSISR_ECC_INT (1 << 1) +#define CSISR_DRDY (1 << 0) + +#define CSICR1 0x00 +#define CSICR2 0x04 +#define CSISR (cpu_is_mx27() ? 0x08 : 0x18) +#define CSISTATFIFO 0x0c +#define CSIRFIFO 0x10 +#define CSIRXCNT 0x14 +#define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08) +#define CSIDMASA_STATFIFO 0x20 +#define CSIDMATA_STATFIFO 0x24 +#define CSIDMASA_FB1 0x28 +#define CSIDMASA_FB2 0x2c +#define CSIFBUF_PARA 0x30 +#define CSIIMAG_PARA 0x34 + +/* EMMA PrP */ +#define PRP_CNTL 0x00 +#define PRP_INTR_CNTL 0x04 +#define PRP_INTRSTATUS 0x08 +#define PRP_SOURCE_Y_PTR 0x0c +#define PRP_SOURCE_CB_PTR 0x10 +#define PRP_SOURCE_CR_PTR 0x14 +#define PRP_DEST_RGB1_PTR 0x18 +#define PRP_DEST_RGB2_PTR 0x1c +#define PRP_DEST_Y_PTR 0x20 +#define PRP_DEST_CB_PTR 0x24 +#define PRP_DEST_CR_PTR 0x28 +#define PRP_SRC_FRAME_SIZE 0x2c +#define PRP_DEST_CH1_LINE_STRIDE 0x30 +#define PRP_SRC_PIXEL_FORMAT_CNTL 0x34 +#define PRP_CH1_PIXEL_FORMAT_CNTL 0x38 +#define PRP_CH1_OUT_IMAGE_SIZE 0x3c +#define PRP_CH2_OUT_IMAGE_SIZE 0x40 +#define PRP_SRC_LINE_STRIDE 0x44 +#define PRP_CSC_COEF_012 0x48 +#define PRP_CSC_COEF_345 0x4c +#define PRP_CSC_COEF_678 0x50 +#define PRP_CH1_RZ_HORI_COEF1 0x54 +#define PRP_CH1_RZ_HORI_COEF2 0x58 +#define PRP_CH1_RZ_HORI_VALID 0x5c +#define PRP_CH1_RZ_VERT_COEF1 0x60 +#define PRP_CH1_RZ_VERT_COEF2 0x64 +#define PRP_CH1_RZ_VERT_VALID 0x68 +#define PRP_CH2_RZ_HORI_COEF1 0x6c +#define PRP_CH2_RZ_HORI_COEF2 0x70 +#define PRP_CH2_RZ_HORI_VALID 0x74 +#define PRP_CH2_RZ_VERT_COEF1 0x78 +#define PRP_CH2_RZ_VERT_COEF2 0x7c +#define PRP_CH2_RZ_VERT_VALID 0x80 + +#define PRP_CNTL_CH1EN (1 << 0) +#define PRP_CNTL_CH2EN (1 << 1) +#define PRP_CNTL_CSIEN (1 << 2) +#define PRP_CNTL_DATA_IN_YUV420 (0 << 3) +#define PRP_CNTL_DATA_IN_YUV422 (1 << 3) +#define PRP_CNTL_DATA_IN_RGB16 (2 << 3) +#define PRP_CNTL_DATA_IN_RGB32 (3 << 3) +#define PRP_CNTL_CH1_OUT_RGB8 (0 << 5) +#define PRP_CNTL_CH1_OUT_RGB16 (1 << 5) +#define PRP_CNTL_CH1_OUT_RGB32 (2 << 5) +#define PRP_CNTL_CH1_OUT_YUV422 (3 << 5) +#define PRP_CNTL_CH2_OUT_YUV420 (0 << 7) +#define PRP_CNTL_CH2_OUT_YUV422 (1 << 7) +#define PRP_CNTL_CH2_OUT_YUV444 (2 << 7) +#define PRP_CNTL_CH1_LEN (1 << 9) +#define PRP_CNTL_CH2_LEN (1 << 10) +#define PRP_CNTL_SKIP_FRAME (1 << 11) +#define PRP_CNTL_SWRST (1 << 12) +#define PRP_CNTL_CLKEN (1 << 13) +#define PRP_CNTL_WEN (1 << 14) +#define PRP_CNTL_CH1BYP (1 << 15) +#define PRP_CNTL_IN_TSKIP(x) ((x) << 16) +#define PRP_CNTL_CH1_TSKIP(x) ((x) << 19) +#define PRP_CNTL_CH2_TSKIP(x) ((x) << 22) +#define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25) +#define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27) +#define PRP_CNTL_CH2B1EN (1 << 29) +#define PRP_CNTL_CH2B2EN (1 << 30) +#define PRP_CNTL_CH2FEN (1 << 31) + +/* IRQ Enable and status register */ +#define PRP_INTR_RDERR (1 << 0) +#define PRP_INTR_CH1WERR (1 << 1) +#define PRP_INTR_CH2WERR (1 << 2) +#define PRP_INTR_CH1FC (1 << 3) +#define PRP_INTR_CH2FC (1 << 5) +#define PRP_INTR_LBOVF (1 << 7) +#define PRP_INTR_CH2OVF (1 << 8) + +#define mx27_camera_emma(pcdev) (cpu_is_mx27() && pcdev->use_emma) + +#define MAX_VIDEO_MEM 16 + +struct mx2_camera_dev { + struct device *dev; + struct soc_camera_host soc_host; + struct soc_camera_device *icd; + struct clk *clk_csi, *clk_emma; + + unsigned int irq_csi, irq_emma; + void __iomem *base_csi, *base_emma; + unsigned long base_dma; + + struct mx2_camera_platform_data *pdata; + struct resource *res_csi, *res_emma; + unsigned long platform_flags; + + struct list_head capture; + struct list_head active_bufs; + + spinlock_t lock; + + int dma; + struct mx2_buffer *active; + struct mx2_buffer *fb1_active; + struct mx2_buffer *fb2_active; + + int use_emma; + + u32 csicr1; + + void *discard_buffer; + dma_addr_t discard_buffer_dma; + size_t discard_size; +}; + +/* buffer for one video frame */ +struct mx2_buffer { + /* common v4l buffer stuff -- must be first */ + struct videobuf_buffer vb; + + enum v4l2_mbus_pixelcode code; + + int bufnum; +}; + +static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev) +{ + unsigned long flags; + + clk_disable(pcdev->clk_csi); + writel(0, pcdev->base_csi + CSICR1); + if (mx27_camera_emma(pcdev)) { + writel(0, pcdev->base_emma + PRP_CNTL); + } else if (cpu_is_mx25()) { + spin_lock_irqsave(&pcdev->lock, flags); + pcdev->fb1_active = NULL; + pcdev->fb2_active = NULL; + writel(0, pcdev->base_csi + CSIDMASA_FB1); + writel(0, pcdev->base_csi + CSIDMASA_FB2); + spin_unlock_irqrestore(&pcdev->lock, flags); + } +} + +/* + * The following two functions absolutely depend on the fact, that + * there can be only one camera on mx2 camera sensor interface + */ +static int mx2_camera_add_device(struct soc_camera_device *icd) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + int ret; + u32 csicr1; + + if (pcdev->icd) + return -EBUSY; + + ret = clk_enable(pcdev->clk_csi); + if (ret < 0) + return ret; + + csicr1 = CSICR1_MCLKEN; + + if (mx27_camera_emma(pcdev)) { + csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC | + CSICR1_RXFF_LEVEL(0); + } else if (cpu_is_mx27()) + csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2); + + pcdev->csicr1 = csicr1; + writel(pcdev->csicr1, pcdev->base_csi + CSICR1); + + pcdev->icd = icd; + + dev_info(icd->dev.parent, "Camera driver attached to camera %d\n", + icd->devnum); + + return 0; +} + +static void mx2_camera_remove_device(struct soc_camera_device *icd) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + + BUG_ON(icd != pcdev->icd); + + dev_info(icd->dev.parent, "Camera driver detached from camera %d\n", + icd->devnum); + + mx2_camera_deactivate(pcdev); + + if (pcdev->discard_buffer) { + dma_free_coherent(ici->v4l2_dev.dev, pcdev->discard_size, + pcdev->discard_buffer, + pcdev->discard_buffer_dma); + pcdev->discard_buffer = NULL; + } + + pcdev->icd = NULL; +} + +#ifdef CONFIG_MACH_MX27 +static void mx27_camera_dma_enable(struct mx2_camera_dev *pcdev) +{ + u32 tmp; + + imx_dma_enable(pcdev->dma); + + tmp = readl(pcdev->base_csi + CSICR1); + tmp |= CSICR1_RF_OR_INTEN; + writel(tmp, pcdev->base_csi + CSICR1); +} + +static irqreturn_t mx27_camera_irq(int irq_csi, void *data) +{ + struct mx2_camera_dev *pcdev = data; + u32 status = readl(pcdev->base_csi + CSISR); + + if (status & CSISR_SOF_INT && pcdev->active) { + u32 tmp; + + tmp = readl(pcdev->base_csi + CSICR1); + writel(tmp | CSICR1_CLR_RXFIFO, pcdev->base_csi + CSICR1); + mx27_camera_dma_enable(pcdev); + } + + writel(CSISR_SOF_INT | CSISR_RFF_OR_INT, pcdev->base_csi + CSISR); + + return IRQ_HANDLED; +} +#else +static irqreturn_t mx27_camera_irq(int irq_csi, void *data) +{ + return IRQ_NONE; +} +#endif /* CONFIG_MACH_MX27 */ + +static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb, + int state) +{ + struct videobuf_buffer *vb; + struct mx2_buffer *buf; + struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active : + &pcdev->fb2_active; + u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2; + unsigned long flags; + + spin_lock_irqsave(&pcdev->lock, flags); + + vb = &(*fb_active)->vb; + dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + vb, vb->baddr, vb->bsize); + + vb->state = state; + do_gettimeofday(&vb->ts); + vb->field_count++; + + wake_up(&vb->done); + + if (list_empty(&pcdev->capture)) { + buf = NULL; + writel(0, pcdev->base_csi + fb_reg); + } else { + buf = list_entry(pcdev->capture.next, struct mx2_buffer, + vb.queue); + vb = &buf->vb; + list_del(&vb->queue); + vb->state = VIDEOBUF_ACTIVE; + writel(videobuf_to_dma_contig(vb), pcdev->base_csi + fb_reg); + } + + *fb_active = buf; + + spin_unlock_irqrestore(&pcdev->lock, flags); +} + +static irqreturn_t mx25_camera_irq(int irq_csi, void *data) +{ + struct mx2_camera_dev *pcdev = data; + u32 status = readl(pcdev->base_csi + CSISR); + + if (status & CSISR_DMA_TSF_FB1_INT) + mx25_camera_frame_done(pcdev, 1, VIDEOBUF_DONE); + else if (status & CSISR_DMA_TSF_FB2_INT) + mx25_camera_frame_done(pcdev, 2, VIDEOBUF_DONE); + + /* FIXME: handle CSISR_RFF_OR_INT */ + + writel(status, pcdev->base_csi + CSISR); + + return IRQ_HANDLED; +} + +/* + * Videobuf operations + */ +static int mx2_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, + unsigned int *size) +{ + struct soc_camera_device *icd = vq->priv_data; + int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, + icd->current_fmt->host_fmt); + + dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); + + if (bytes_per_line < 0) + return bytes_per_line; + + *size = bytes_per_line * icd->user_height; + + if (0 == *count) + *count = 32; + if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024) + *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size; + + return 0; +} + +static void free_buffer(struct videobuf_queue *vq, struct mx2_buffer *buf) +{ + struct soc_camera_device *icd = vq->priv_data; + struct videobuf_buffer *vb = &buf->vb; + + dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + vb, vb->baddr, vb->bsize); + + /* + * This waits until this buffer is out of danger, i.e., until it is no + * longer in STATE_QUEUED or STATE_ACTIVE + */ + videobuf_waiton(vb, 0, 0); + + videobuf_dma_contig_free(vq, vb); + dev_dbg(&icd->dev, "%s freed\n", __func__); + + vb->state = VIDEOBUF_NEEDS_INIT; +} + +static int mx2_videobuf_prepare(struct videobuf_queue *vq, + struct videobuf_buffer *vb, enum v4l2_field field) +{ + struct soc_camera_device *icd = vq->priv_data; + struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); + int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, + icd->current_fmt->host_fmt); + int ret = 0; + + dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + vb, vb->baddr, vb->bsize); + + if (bytes_per_line < 0) + return bytes_per_line; + +#ifdef DEBUG + /* + * This can be useful if you want to see if we actually fill + * the buffer with something + */ + memset((void *)vb->baddr, 0xaa, vb->bsize); +#endif + + if (buf->code != icd->current_fmt->code || + vb->width != icd->user_width || + vb->height != icd->user_height || + vb->field != field) { + buf->code = icd->current_fmt->code; + vb->width = icd->user_width; + vb->height = icd->user_height; + vb->field = field; + vb->state = VIDEOBUF_NEEDS_INIT; + } + + vb->size = bytes_per_line * vb->height; + if (vb->baddr && vb->bsize < vb->size) { + ret = -EINVAL; + goto out; + } + + if (vb->state == VIDEOBUF_NEEDS_INIT) { + ret = videobuf_iolock(vq, vb, NULL); + if (ret) + goto fail; + + vb->state = VIDEOBUF_PREPARED; + } + + return 0; + +fail: + free_buffer(vq, buf); +out: + return ret; +} + +static void mx2_videobuf_queue(struct videobuf_queue *vq, + struct videobuf_buffer *vb) +{ + struct soc_camera_device *icd = vq->priv_data; + struct soc_camera_host *ici = + to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); + unsigned long flags; + + dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + vb, vb->baddr, vb->bsize); + + spin_lock_irqsave(&pcdev->lock, flags); + + vb->state = VIDEOBUF_QUEUED; + list_add_tail(&vb->queue, &pcdev->capture); + + if (mx27_camera_emma(pcdev)) { + goto out; +#ifdef CONFIG_MACH_MX27 + } else if (cpu_is_mx27()) { + int ret; + + if (pcdev->active == NULL) { + ret = imx_dma_setup_single(pcdev->dma, + videobuf_to_dma_contig(vb), vb->size, + (u32)pcdev->base_dma + 0x10, + DMA_MODE_READ); + if (ret) { + vb->state = VIDEOBUF_ERROR; + wake_up(&vb->done); + goto out; + } + + vb->state = VIDEOBUF_ACTIVE; + pcdev->active = buf; + } +#endif + } else { /* cpu_is_mx25() */ + u32 csicr3, dma_inten = 0; + + if (pcdev->fb1_active == NULL) { + writel(videobuf_to_dma_contig(vb), + pcdev->base_csi + CSIDMASA_FB1); + pcdev->fb1_active = buf; + dma_inten = CSICR1_FB1_DMA_INTEN; + } else if (pcdev->fb2_active == NULL) { + writel(videobuf_to_dma_contig(vb), + pcdev->base_csi + CSIDMASA_FB2); + pcdev->fb2_active = buf; + dma_inten = CSICR1_FB2_DMA_INTEN; + } + + if (dma_inten) { + list_del(&vb->queue); + vb->state = VIDEOBUF_ACTIVE; + + csicr3 = readl(pcdev->base_csi + CSICR3); + + /* Reflash DMA */ + writel(csicr3 | CSICR3_DMA_REFLASH_RFF, + pcdev->base_csi + CSICR3); + + /* clear & enable interrupts */ + writel(dma_inten, pcdev->base_csi + CSISR); + pcdev->csicr1 |= dma_inten; + writel(pcdev->csicr1, pcdev->base_csi + CSICR1); + + /* enable DMA */ + csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1); + writel(csicr3, pcdev->base_csi + CSICR3); + } + } + +out: + spin_unlock_irqrestore(&pcdev->lock, flags); +} + +static void mx2_videobuf_release(struct videobuf_queue *vq, + struct videobuf_buffer *vb) +{ + struct soc_camera_device *icd = vq->priv_data; + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); + unsigned long flags; + +#ifdef DEBUG + dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + vb, vb->baddr, vb->bsize); + + switch (vb->state) { + case VIDEOBUF_ACTIVE: + dev_info(&icd->dev, "%s (active)\n", __func__); + break; + case VIDEOBUF_QUEUED: + dev_info(&icd->dev, "%s (queued)\n", __func__); + break; + case VIDEOBUF_PREPARED: + dev_info(&icd->dev, "%s (prepared)\n", __func__); + break; + default: + dev_info(&icd->dev, "%s (unknown) %d\n", __func__, + vb->state); + break; + } +#endif + + /* + * Terminate only queued but inactive buffers. Active buffers are + * released when they become inactive after videobuf_waiton(). + * + * FIXME: implement forced termination of active buffers, so that the + * user won't get stuck in an uninterruptible state. This requires a + * specific handling for each of the three DMA types that this driver + * supports. + */ + spin_lock_irqsave(&pcdev->lock, flags); + if (vb->state == VIDEOBUF_QUEUED) { + list_del(&vb->queue); + vb->state = VIDEOBUF_ERROR; + } + spin_unlock_irqrestore(&pcdev->lock, flags); + + free_buffer(vq, buf); +} + +static struct videobuf_queue_ops mx2_videobuf_ops = { + .buf_setup = mx2_videobuf_setup, + .buf_prepare = mx2_videobuf_prepare, + .buf_queue = mx2_videobuf_queue, + .buf_release = mx2_videobuf_release, +}; + +static void mx2_camera_init_videobuf(struct videobuf_queue *q, + struct soc_camera_device *icd) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + + videobuf_queue_dma_contig_init(q, &mx2_videobuf_ops, pcdev->dev, + &pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_NONE, sizeof(struct mx2_buffer), icd); +} + +#define MX2_BUS_FLAGS (SOCAM_DATAWIDTH_8 | \ + SOCAM_MASTER | \ + SOCAM_VSYNC_ACTIVE_HIGH | \ + SOCAM_VSYNC_ACTIVE_LOW | \ + SOCAM_HSYNC_ACTIVE_HIGH | \ + SOCAM_HSYNC_ACTIVE_LOW | \ + SOCAM_PCLK_SAMPLE_RISING | \ + SOCAM_PCLK_SAMPLE_FALLING | \ + SOCAM_DATA_ACTIVE_HIGH | \ + SOCAM_DATA_ACTIVE_LOW) + +static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev) +{ + u32 cntl; + int count = 0; + + cntl = readl(pcdev->base_emma + PRP_CNTL); + writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL); + while (count++ < 100) { + if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST)) + return 0; + barrier(); + udelay(1); + } + + return -ETIMEDOUT; +} + +static void mx27_camera_emma_buf_init(struct soc_camera_device *icd, + int bytesperline) +{ + struct soc_camera_host *ici = + to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + + writel(pcdev->discard_buffer_dma, + pcdev->base_emma + PRP_DEST_RGB1_PTR); + writel(pcdev->discard_buffer_dma, + pcdev->base_emma + PRP_DEST_RGB2_PTR); + + /* + * We only use the EMMA engine to get rid of the broken + * DMA Engine. No color space consversion at the moment. + * We adjust incoming and outgoing pixelformat to rgb16 + * and adjust the bytesperline accordingly. + */ + writel(PRP_CNTL_CH1EN | + PRP_CNTL_CSIEN | + PRP_CNTL_DATA_IN_RGB16 | + PRP_CNTL_CH1_OUT_RGB16 | + PRP_CNTL_CH1_LEN | + PRP_CNTL_CH1BYP | + PRP_CNTL_CH1_TSKIP(0) | + PRP_CNTL_IN_TSKIP(0), + pcdev->base_emma + PRP_CNTL); + + writel(((bytesperline >> 1) << 16) | icd->user_height, + pcdev->base_emma + PRP_SRC_FRAME_SIZE); + writel(((bytesperline >> 1) << 16) | icd->user_height, + pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE); + writel(bytesperline, + pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE); + writel(0x2ca00565, /* RGB565 */ + pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL); + writel(0x2ca00565, /* RGB565 */ + pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL); + + /* Enable interrupts */ + writel(PRP_INTR_RDERR | + PRP_INTR_CH1WERR | + PRP_INTR_CH2WERR | + PRP_INTR_CH1FC | + PRP_INTR_CH2FC | + PRP_INTR_LBOVF | + PRP_INTR_CH2OVF, + pcdev->base_emma + PRP_INTR_CNTL); +} + +static int mx2_camera_set_bus_param(struct soc_camera_device *icd, + __u32 pixfmt) +{ + struct soc_camera_host *ici = + to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + unsigned long camera_flags, common_flags; + int ret = 0; + int bytesperline; + u32 csicr1 = pcdev->csicr1; + + camera_flags = icd->ops->query_bus_param(icd); + + common_flags = soc_camera_bus_param_compatible(camera_flags, + MX2_BUS_FLAGS); + if (!common_flags) + return -EINVAL; + + if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && + (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { + if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH) + common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; + else + common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; + } + + if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && + (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { + if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING) + common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; + else + common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; + } + + ret = icd->ops->set_bus_param(icd, common_flags); + if (ret < 0) + return ret; + + if (common_flags & SOCAM_PCLK_SAMPLE_FALLING) + csicr1 |= CSICR1_INV_PCLK; + if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH) + csicr1 |= CSICR1_SOF_POL; + if (common_flags & SOCAM_HSYNC_ACTIVE_HIGH) + csicr1 |= CSICR1_HSYNC_POL; + if (pcdev->platform_flags & MX2_CAMERA_SWAP16) + csicr1 |= CSICR1_SWAP16_EN; + if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC) + csicr1 |= CSICR1_EXT_VSYNC; + if (pcdev->platform_flags & MX2_CAMERA_CCIR) + csicr1 |= CSICR1_CCIR_EN; + if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE) + csicr1 |= CSICR1_CCIR_MODE; + if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK) + csicr1 |= CSICR1_GCLK_MODE; + if (pcdev->platform_flags & MX2_CAMERA_INV_DATA) + csicr1 |= CSICR1_INV_DATA; + if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB) + csicr1 |= CSICR1_PACK_DIR; + + pcdev->csicr1 = csicr1; + + bytesperline = soc_mbus_bytes_per_line(icd->user_width, + icd->current_fmt->host_fmt); + if (bytesperline < 0) + return bytesperline; + + if (mx27_camera_emma(pcdev)) { + ret = mx27_camera_emma_prp_reset(pcdev); + if (ret) + return ret; + + if (pcdev->discard_buffer) + dma_free_coherent(ici->v4l2_dev.dev, + pcdev->discard_size, pcdev->discard_buffer, + pcdev->discard_buffer_dma); + + /* + * I didn't manage to properly enable/disable the prp + * on a per frame basis during running transfers, + * thus we allocate a buffer here and use it to + * discard frames when no buffer is available. + * Feel free to work on this ;) + */ + pcdev->discard_size = icd->user_height * bytesperline; + pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev, + pcdev->discard_size, &pcdev->discard_buffer_dma, + GFP_KERNEL); + if (!pcdev->discard_buffer) + return -ENOMEM; + + mx27_camera_emma_buf_init(icd, bytesperline); + } else if (cpu_is_mx25()) { + writel((bytesperline * icd->user_height) >> 2, + pcdev->base_csi + CSIRXCNT); + writel((bytesperline << 16) | icd->user_height, + pcdev->base_csi + CSIIMAG_PARA); + } + + writel(pcdev->csicr1, pcdev->base_csi + CSICR1); + + return 0; +} + +static int mx2_camera_set_crop(struct soc_camera_device *icd, + struct v4l2_crop *a) +{ + struct v4l2_rect *rect = &a->c; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + struct v4l2_mbus_framefmt mf; + int ret; + + soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096); + soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096); + + ret = v4l2_subdev_call(sd, video, s_crop, a); + if (ret < 0) + return ret; + + /* The capture device might have changed its output */ + ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); + if (ret < 0) + return ret; + + dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n", + mf.width, mf.height); + + icd->user_width = mf.width; + icd->user_height = mf.height; + + return ret; +} + +static int mx2_camera_set_fmt(struct soc_camera_device *icd, + struct v4l2_format *f) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + const struct soc_camera_format_xlate *xlate; + struct v4l2_pix_format *pix = &f->fmt.pix; + struct v4l2_mbus_framefmt mf; + int ret; + + xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); + if (!xlate) { + dev_warn(icd->dev.parent, "Format %x not found\n", + pix->pixelformat); + return -EINVAL; + } + + /* eMMA can only do RGB565 */ + if (mx27_camera_emma(pcdev) && pix->pixelformat != V4L2_PIX_FMT_RGB565) + return -EINVAL; + + mf.width = pix->width; + mf.height = pix->height; + mf.field = pix->field; + mf.colorspace = pix->colorspace; + mf.code = xlate->code; + + ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); + if (ret < 0 && ret != -ENOIOCTLCMD) + return ret; + + if (mf.code != xlate->code) + return -EINVAL; + + pix->width = mf.width; + pix->height = mf.height; + pix->field = mf.field; + pix->colorspace = mf.colorspace; + icd->current_fmt = xlate; + + return 0; +} + +static int mx2_camera_try_fmt(struct soc_camera_device *icd, + struct v4l2_format *f) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + const struct soc_camera_format_xlate *xlate; + struct v4l2_pix_format *pix = &f->fmt.pix; + struct v4l2_mbus_framefmt mf; + __u32 pixfmt = pix->pixelformat; + unsigned int width_limit; + int ret; + + xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); + if (pixfmt && !xlate) { + dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt); + return -EINVAL; + } + + /* FIXME: implement MX27 limits */ + + /* eMMA can only do RGB565 */ + if (mx27_camera_emma(pcdev) && pixfmt != V4L2_PIX_FMT_RGB565) + return -EINVAL; + + /* limit to MX25 hardware capabilities */ + if (cpu_is_mx25()) { + if (xlate->host_fmt->bits_per_sample <= 8) + width_limit = 0xffff * 4; + else + width_limit = 0xffff * 2; + /* CSIIMAG_PARA limit */ + if (pix->width > width_limit) + pix->width = width_limit; + if (pix->height > 0xffff) + pix->height = 0xffff; + + pix->bytesperline = soc_mbus_bytes_per_line(pix->width, + xlate->host_fmt); + if (pix->bytesperline < 0) + return pix->bytesperline; + pix->sizeimage = pix->height * pix->bytesperline; + if (pix->sizeimage > (4 * 0x3ffff)) { /* CSIRXCNT limit */ + dev_warn(icd->dev.parent, + "Image size (%u) above limit\n", + pix->sizeimage); + return -EINVAL; + } + } + + /* limit to sensor capabilities */ + mf.width = pix->width; + mf.height = pix->height; + mf.field = pix->field; + mf.colorspace = pix->colorspace; + mf.code = xlate->code; + + ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); + if (ret < 0) + return ret; + + if (mf.field == V4L2_FIELD_ANY) + mf.field = V4L2_FIELD_NONE; + if (mf.field != V4L2_FIELD_NONE) { + dev_err(icd->dev.parent, "Field type %d unsupported.\n", + mf.field); + return -EINVAL; + } + + pix->width = mf.width; + pix->height = mf.height; + pix->field = mf.field; + pix->colorspace = mf.colorspace; + + return 0; +} + +static int mx2_camera_querycap(struct soc_camera_host *ici, + struct v4l2_capability *cap) +{ + /* cap->name is set by the friendly caller:-> */ + strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card)); + cap->version = MX2_CAM_VERSION_CODE; + cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + + return 0; +} + +static int mx2_camera_reqbufs(struct soc_camera_file *icf, + struct v4l2_requestbuffers *p) +{ + int i; + + for (i = 0; i < p->count; i++) { + struct mx2_buffer *buf = container_of(icf->vb_vidq.bufs[i], + struct mx2_buffer, vb); + INIT_LIST_HEAD(&buf->vb.queue); + } + + return 0; +} + +#ifdef CONFIG_MACH_MX27 +static void mx27_camera_frame_done(struct mx2_camera_dev *pcdev, int state) +{ + struct videobuf_buffer *vb; + struct mx2_buffer *buf; + unsigned long flags; + int ret; + + spin_lock_irqsave(&pcdev->lock, flags); + + if (!pcdev->active) { + dev_err(pcdev->dev, "%s called with no active buffer!\n", + __func__); + goto out; + } + + vb = &pcdev->active->vb; + buf = container_of(vb, struct mx2_buffer, vb); + WARN_ON(list_empty(&vb->queue)); + dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + vb, vb->baddr, vb->bsize); + + /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ + list_del_init(&vb->queue); + vb->state = state; + do_gettimeofday(&vb->ts); + vb->field_count++; + + wake_up(&vb->done); + + if (list_empty(&pcdev->capture)) { + pcdev->active = NULL; + goto out; + } + + pcdev->active = list_entry(pcdev->capture.next, + struct mx2_buffer, vb.queue); + + vb = &pcdev->active->vb; + vb->state = VIDEOBUF_ACTIVE; + + ret = imx_dma_setup_single(pcdev->dma, videobuf_to_dma_contig(vb), + vb->size, (u32)pcdev->base_dma + 0x10, DMA_MODE_READ); + + if (ret) { + vb->state = VIDEOBUF_ERROR; + pcdev->active = NULL; + wake_up(&vb->done); + } + +out: + spin_unlock_irqrestore(&pcdev->lock, flags); +} + +static void mx27_camera_dma_err_callback(int channel, void *data, int err) +{ + struct mx2_camera_dev *pcdev = data; + + mx27_camera_frame_done(pcdev, VIDEOBUF_ERROR); +} + +static void mx27_camera_dma_callback(int channel, void *data) +{ + struct mx2_camera_dev *pcdev = data; + + mx27_camera_frame_done(pcdev, VIDEOBUF_DONE); +} + +#define DMA_REQ_CSI_RX 31 /* FIXME: Add this to a resource */ + +static int __devinit mx27_camera_dma_init(struct platform_device *pdev, + struct mx2_camera_dev *pcdev) +{ + int err; + + pcdev->dma = imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH); + if (pcdev->dma < 0) { + dev_err(&pdev->dev, "%s failed to request DMA channel\n", + __func__); + return pcdev->dma; + } + + err = imx_dma_setup_handlers(pcdev->dma, mx27_camera_dma_callback, + mx27_camera_dma_err_callback, pcdev); + if (err) { + dev_err(&pdev->dev, "%s failed to set DMA callback\n", + __func__); + goto err_out; + } + + err = imx_dma_config_channel(pcdev->dma, + IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO, + IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR, + DMA_REQ_CSI_RX, 1); + if (err) { + dev_err(&pdev->dev, "%s failed to config DMA channel\n", + __func__); + goto err_out; + } + + imx_dma_config_burstlen(pcdev->dma, 64); + + return 0; + +err_out: + imx_dma_free(pcdev->dma); + + return err; +} +#endif /* CONFIG_MACH_MX27 */ + +static unsigned int mx2_camera_poll(struct file *file, poll_table *pt) +{ + struct soc_camera_file *icf = file->private_data; + + return videobuf_poll_stream(file, &icf->vb_vidq, pt); +} + +static struct soc_camera_host_ops mx2_soc_camera_host_ops = { + .owner = THIS_MODULE, + .add = mx2_camera_add_device, + .remove = mx2_camera_remove_device, + .set_fmt = mx2_camera_set_fmt, + .set_crop = mx2_camera_set_crop, + .try_fmt = mx2_camera_try_fmt, + .init_videobuf = mx2_camera_init_videobuf, + .reqbufs = mx2_camera_reqbufs, + .poll = mx2_camera_poll, + .querycap = mx2_camera_querycap, + .set_bus_param = mx2_camera_set_bus_param, +}; + +static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev, + int bufnum, int state) +{ + struct mx2_buffer *buf; + struct videobuf_buffer *vb; + unsigned long phys; + + if (!list_empty(&pcdev->active_bufs)) { + buf = list_entry(pcdev->active_bufs.next, + struct mx2_buffer, vb.queue); + + BUG_ON(buf->bufnum != bufnum); + + vb = &buf->vb; +#ifdef DEBUG + phys = videobuf_to_dma_contig(vb); + if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum) + != phys) { + dev_err(pcdev->dev, "%p != %p\n", phys, + readl(pcdev->base_emma + + PRP_DEST_RGB1_PTR + + 4 * bufnum)); + } +#endif + dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb, + vb->baddr, vb->bsize); + + list_del(&vb->queue); + vb->state = state; + do_gettimeofday(&vb->ts); + vb->field_count++; + + wake_up(&vb->done); + } + + if (list_empty(&pcdev->capture)) { + writel(pcdev->discard_buffer_dma, pcdev->base_emma + + PRP_DEST_RGB1_PTR + 4 * bufnum); + return; + } + + buf = list_entry(pcdev->capture.next, + struct mx2_buffer, vb.queue); + + buf->bufnum = bufnum; + + list_move_tail(pcdev->capture.next, &pcdev->active_bufs); + + vb = &buf->vb; + vb->state = VIDEOBUF_ACTIVE; + + phys = videobuf_to_dma_contig(vb); + writel(phys, pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum); +} + +static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data) +{ + struct mx2_camera_dev *pcdev = data; + unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS); + struct mx2_buffer *buf; + + if (status & (1 << 7)) { /* overflow */ + u32 cntl; + /* + * We only disable channel 1 here since this is the only + * enabled channel + * + * FIXME: the correct DMA overflow handling should be resetting + * the buffer, returning an error frame, and continuing with + * the next one. + */ + cntl = readl(pcdev->base_emma + PRP_CNTL); + writel(cntl & ~PRP_CNTL_CH1EN, pcdev->base_emma + PRP_CNTL); + writel(cntl, pcdev->base_emma + PRP_CNTL); + } + if ((status & (3 << 5)) == (3 << 5) + && !list_empty(&pcdev->active_bufs)) { + /* + * Both buffers have triggered, process the one we're expecting + * to first + */ + buf = list_entry(pcdev->active_bufs.next, + struct mx2_buffer, vb.queue); + mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE); + status &= ~(1 << (6 - buf->bufnum)); /* mark processed */ + } + if (status & (1 << 6)) + mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE); + if (status & (1 << 5)) + mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE); + + writel(status, pcdev->base_emma + PRP_INTRSTATUS); + + return IRQ_HANDLED; +} + +static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev) +{ + struct resource *res_emma = pcdev->res_emma; + int err = 0; + + if (!request_mem_region(res_emma->start, resource_size(res_emma), + MX2_CAM_DRV_NAME)) { + err = -EBUSY; + goto out; + } + + pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma)); + if (!pcdev->base_emma) { + err = -ENOMEM; + goto exit_release; + } + + err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0, + MX2_CAM_DRV_NAME, pcdev); + if (err) { + dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n"); + goto exit_iounmap; + } + + pcdev->clk_emma = clk_get(NULL, "emma"); + if (IS_ERR(pcdev->clk_emma)) { + err = PTR_ERR(pcdev->clk_emma); + goto exit_free_irq; + } + + clk_enable(pcdev->clk_emma); + + err = mx27_camera_emma_prp_reset(pcdev); + if (err) + goto exit_clk_emma_put; + + return err; + +exit_clk_emma_put: + clk_disable(pcdev->clk_emma); + clk_put(pcdev->clk_emma); +exit_free_irq: + free_irq(pcdev->irq_emma, pcdev); +exit_iounmap: + iounmap(pcdev->base_emma); +exit_release: + release_mem_region(res_emma->start, resource_size(res_emma)); +out: + return err; +} + +static int __devinit mx2_camera_probe(struct platform_device *pdev) +{ + struct mx2_camera_dev *pcdev; + struct resource *res_csi, *res_emma; + void __iomem *base_csi; + int irq_csi, irq_emma; + irq_handler_t mx2_cam_irq_handler = cpu_is_mx25() ? mx25_camera_irq + : mx27_camera_irq; + int err = 0; + + dev_dbg(&pdev->dev, "initialising\n"); + + res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq_csi = platform_get_irq(pdev, 0); + if (res_csi == NULL || irq_csi < 0) { + dev_err(&pdev->dev, "Missing platform resources data\n"); + err = -ENODEV; + goto exit; + } + + pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); + if (!pcdev) { + dev_err(&pdev->dev, "Could not allocate pcdev\n"); + err = -ENOMEM; + goto exit; + } + + pcdev->clk_csi = clk_get(&pdev->dev, NULL); + if (IS_ERR(pcdev->clk_csi)) { + err = PTR_ERR(pcdev->clk_csi); + goto exit_kfree; + } + + dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n", + clk_get_rate(pcdev->clk_csi)); + + /* Initialize DMA */ +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) { + err = mx27_camera_dma_init(pdev, pcdev); + if (err) + goto exit_clk_put; + } +#endif /* CONFIG_MACH_MX27 */ + + pcdev->res_csi = res_csi; + pcdev->pdata = pdev->dev.platform_data; + if (pcdev->pdata) { + long rate; + + pcdev->platform_flags = pcdev->pdata->flags; + + rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2); + if (rate <= 0) { + err = -ENODEV; + goto exit_dma_free; + } + err = clk_set_rate(pcdev->clk_csi, rate); + if (err < 0) + goto exit_dma_free; + } + + INIT_LIST_HEAD(&pcdev->capture); + INIT_LIST_HEAD(&pcdev->active_bufs); + spin_lock_init(&pcdev->lock); + + /* + * Request the regions. + */ + if (!request_mem_region(res_csi->start, resource_size(res_csi), + MX2_CAM_DRV_NAME)) { + err = -EBUSY; + goto exit_dma_free; + } + + base_csi = ioremap(res_csi->start, resource_size(res_csi)); + if (!base_csi) { + err = -ENOMEM; + goto exit_release; + } + pcdev->irq_csi = irq_csi; + pcdev->base_csi = base_csi; + pcdev->base_dma = res_csi->start; + pcdev->dev = &pdev->dev; + + err = request_irq(pcdev->irq_csi, mx2_cam_irq_handler, 0, + MX2_CAM_DRV_NAME, pcdev); + if (err) { + dev_err(pcdev->dev, "Camera interrupt register failed \n"); + goto exit_iounmap; + } + + if (cpu_is_mx27()) { + /* EMMA support */ + res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1); + irq_emma = platform_get_irq(pdev, 1); + + if (res_emma && irq_emma >= 0) { + dev_info(&pdev->dev, "Using EMMA\n"); + pcdev->use_emma = 1; + pcdev->res_emma = res_emma; + pcdev->irq_emma = irq_emma; + if (mx27_camera_emma_init(pcdev)) + goto exit_free_irq; + } + } + + pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME, + pcdev->soc_host.ops = &mx2_soc_camera_host_ops, + pcdev->soc_host.priv = pcdev; + pcdev->soc_host.v4l2_dev.dev = &pdev->dev; + pcdev->soc_host.nr = pdev->id; + err = soc_camera_host_register(&pcdev->soc_host); + if (err) + goto exit_free_emma; + + return 0; + +exit_free_emma: + if (mx27_camera_emma(pcdev)) { + free_irq(pcdev->irq_emma, pcdev); + clk_disable(pcdev->clk_emma); + clk_put(pcdev->clk_emma); + iounmap(pcdev->base_emma); + release_mem_region(res_emma->start, resource_size(res_emma)); + } +exit_free_irq: + free_irq(pcdev->irq_csi, pcdev); +exit_iounmap: + iounmap(base_csi); +exit_release: + release_mem_region(res_csi->start, resource_size(res_csi)); +exit_dma_free: +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) + imx_dma_free(pcdev->dma); +exit_clk_put: + clk_put(pcdev->clk_csi); +#endif /* CONFIG_MACH_MX27 */ +exit_kfree: + kfree(pcdev); +exit: + return err; +} + +static int __devexit mx2_camera_remove(struct platform_device *pdev) +{ + struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); + struct mx2_camera_dev *pcdev = container_of(soc_host, + struct mx2_camera_dev, soc_host); + struct resource *res; + + clk_put(pcdev->clk_csi); +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) + imx_dma_free(pcdev->dma); +#endif /* CONFIG_MACH_MX27 */ + free_irq(pcdev->irq_csi, pcdev); + if (mx27_camera_emma(pcdev)) + free_irq(pcdev->irq_emma, pcdev); + + soc_camera_host_unregister(&pcdev->soc_host); + + iounmap(pcdev->base_csi); + + if (mx27_camera_emma(pcdev)) { + clk_disable(pcdev->clk_emma); + clk_put(pcdev->clk_emma); + iounmap(pcdev->base_emma); + res = pcdev->res_emma; + release_mem_region(res->start, resource_size(res)); + } + + res = pcdev->res_csi; + release_mem_region(res->start, resource_size(res)); + + kfree(pcdev); + + dev_info(&pdev->dev, "MX2 Camera driver unloaded\n"); + + return 0; +} + +static struct platform_driver mx2_camera_driver = { + .driver = { + .name = MX2_CAM_DRV_NAME, + }, + .remove = __devexit_p(mx2_camera_remove), +}; + + +static int __init mx2_camera_init(void) +{ + return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe); +} + +static void __exit mx2_camera_exit(void) +{ + return platform_driver_unregister(&mx2_camera_driver); +} + +module_init(mx2_camera_init); +module_exit(mx2_camera_exit); + +MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver"); +MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 26386a92f5aa..9b089dfb173e 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -353,6 +353,16 @@ config VMWARE_BALLOON To compile this driver as a module, choose M here: the module will be called vmware_balloon. +config ARM_CHARLCD + bool "ARM Ltd. Character LCD Driver" + depends on PLAT_VERSATILE + help + This is a driver for the character LCD found on the ARM Ltd. + Versatile and RealView Platform Baseboards. It doesn't do + very much more than display the text "ARM Linux" on the first + line and the Linux version on the second line, but that's + still useful. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 6ed06a19474a..67552d6e9327 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_IWMC3200TOP) += iwmc3200top/ obj-y += eeprom/ obj-y += cb710/ obj-$(CONFIG_VMWARE_BALLOON) += vmware_balloon.o +obj-$(CONFIG_ARM_CHARLCD) += arm-charlcd.o diff --git a/drivers/misc/arm-charlcd.c b/drivers/misc/arm-charlcd.c new file mode 100644 index 000000000000..9e3879ef58f2 --- /dev/null +++ b/drivers/misc/arm-charlcd.c @@ -0,0 +1,396 @@ +/* + * Driver for the on-board character LCD found on some ARM reference boards + * This is basically an Hitachi HD44780 LCD with a custom IP block to drive it + * http://en.wikipedia.org/wiki/HD44780_Character_LCD + * Currently it will just display the text "ARM Linux" and the linux version + * + * License terms: GNU General Public License (GPL) version 2 + * Author: Linus Walleij <triad@df.lth.se> + */ +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/completion.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/workqueue.h> +#include <generated/utsrelease.h> + +#define DRIVERNAME "arm-charlcd" +#define CHARLCD_TIMEOUT (msecs_to_jiffies(1000)) + +/* Offsets to registers */ +#define CHAR_COM 0x00U +#define CHAR_DAT 0x04U +#define CHAR_RD 0x08U +#define CHAR_RAW 0x0CU +#define CHAR_MASK 0x10U +#define CHAR_STAT 0x14U + +#define CHAR_RAW_CLEAR 0x00000000U +#define CHAR_RAW_VALID 0x00000100U + +/* Hitachi HD44780 display commands */ +#define HD_CLEAR 0x01U +#define HD_HOME 0x02U +#define HD_ENTRYMODE 0x04U +#define HD_ENTRYMODE_INCREMENT 0x02U +#define HD_ENTRYMODE_SHIFT 0x01U +#define HD_DISPCTRL 0x08U +#define HD_DISPCTRL_ON 0x04U +#define HD_DISPCTRL_CURSOR_ON 0x02U +#define HD_DISPCTRL_CURSOR_BLINK 0x01U +#define HD_CRSR_SHIFT 0x10U +#define HD_CRSR_SHIFT_DISPLAY 0x08U +#define HD_CRSR_SHIFT_DISPLAY_RIGHT 0x04U +#define HD_FUNCSET 0x20U +#define HD_FUNCSET_8BIT 0x10U +#define HD_FUNCSET_2_LINES 0x08U +#define HD_FUNCSET_FONT_5X10 0x04U +#define HD_SET_CGRAM 0x40U +#define HD_SET_DDRAM 0x80U +#define HD_BUSY_FLAG 0x80U + +/** + * @dev: a pointer back to containing device + * @phybase: the offset to the controller in physical memory + * @physize: the size of the physical page + * @virtbase: the offset to the controller in virtual memory + * @irq: reserved interrupt number + * @complete: completion structure for the last LCD command + */ +struct charlcd { + struct device *dev; + u32 phybase; + u32 physize; + void __iomem *virtbase; + int irq; + struct completion complete; + struct delayed_work init_work; +}; + +static irqreturn_t charlcd_interrupt(int irq, void *data) +{ + struct charlcd *lcd = data; + u8 status; + + status = readl(lcd->virtbase + CHAR_STAT) & 0x01; + /* Clear IRQ */ + writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); + if (status) + complete(&lcd->complete); + else + dev_info(lcd->dev, "Spurious IRQ (%02x)\n", status); + return IRQ_HANDLED; +} + + +static void charlcd_wait_complete_irq(struct charlcd *lcd) +{ + int ret; + + ret = wait_for_completion_interruptible_timeout(&lcd->complete, + CHARLCD_TIMEOUT); + /* Disable IRQ after completion */ + writel(0x00, lcd->virtbase + CHAR_MASK); + + if (ret < 0) { + dev_err(lcd->dev, + "wait_for_completion_interruptible_timeout() " + "returned %d waiting for ready\n", ret); + return; + } + + if (ret == 0) { + dev_err(lcd->dev, "charlcd controller timed out " + "waiting for ready\n"); + return; + } +} + +static u8 charlcd_4bit_read_char(struct charlcd *lcd) +{ + u8 data; + u32 val; + int i; + + /* If we can, use an IRQ to wait for the data, else poll */ + if (lcd->irq >= 0) + charlcd_wait_complete_irq(lcd); + else { + i = 0; + val = 0; + while (!(val & CHAR_RAW_VALID) && i < 10) { + udelay(100); + val = readl(lcd->virtbase + CHAR_RAW); + i++; + } + + writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); + } + msleep(1); + + /* Read the 4 high bits of the data */ + data = readl(lcd->virtbase + CHAR_RD) & 0xf0; + + /* + * The second read for the low bits does not trigger an IRQ + * so in this case we have to poll for the 4 lower bits + */ + i = 0; + val = 0; + while (!(val & CHAR_RAW_VALID) && i < 10) { + udelay(100); + val = readl(lcd->virtbase + CHAR_RAW); + i++; + } + writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); + msleep(1); + + /* Read the 4 low bits of the data */ + data |= (readl(lcd->virtbase + CHAR_RD) >> 4) & 0x0f; + + return data; +} + +static bool charlcd_4bit_read_bf(struct charlcd *lcd) +{ + if (lcd->irq >= 0) { + /* + * If we'll use IRQs to wait for the busyflag, clear any + * pending flag and enable IRQ + */ + writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); + init_completion(&lcd->complete); + writel(0x01, lcd->virtbase + CHAR_MASK); + } + readl(lcd->virtbase + CHAR_COM); + return charlcd_4bit_read_char(lcd) & HD_BUSY_FLAG ? true : false; +} + +static void charlcd_4bit_wait_busy(struct charlcd *lcd) +{ + int retries = 50; + + udelay(100); + while (charlcd_4bit_read_bf(lcd) && retries) + retries--; + if (!retries) + dev_err(lcd->dev, "timeout waiting for busyflag\n"); +} + +static void charlcd_4bit_command(struct charlcd *lcd, u8 cmd) +{ + u32 cmdlo = (cmd << 4) & 0xf0; + u32 cmdhi = (cmd & 0xf0); + + writel(cmdhi, lcd->virtbase + CHAR_COM); + udelay(10); + writel(cmdlo, lcd->virtbase + CHAR_COM); + charlcd_4bit_wait_busy(lcd); +} + +static void charlcd_4bit_char(struct charlcd *lcd, u8 ch) +{ + u32 chlo = (ch << 4) & 0xf0; + u32 chhi = (ch & 0xf0); + + writel(chhi, lcd->virtbase + CHAR_DAT); + udelay(10); + writel(chlo, lcd->virtbase + CHAR_DAT); + charlcd_4bit_wait_busy(lcd); +} + +static void charlcd_4bit_print(struct charlcd *lcd, int line, const char *str) +{ + u8 offset; + int i; + + /* + * We support line 0, 1 + * Line 1 runs from 0x00..0x27 + * Line 2 runs from 0x28..0x4f + */ + if (line == 0) + offset = 0; + else if (line == 1) + offset = 0x28; + else + return; + + /* Set offset */ + charlcd_4bit_command(lcd, HD_SET_DDRAM | offset); + + /* Send string */ + for (i = 0; i < strlen(str) && i < 0x28; i++) + charlcd_4bit_char(lcd, str[i]); +} + +static void charlcd_4bit_init(struct charlcd *lcd) +{ + /* These commands cannot be checked with the busy flag */ + writel(HD_FUNCSET | HD_FUNCSET_8BIT, lcd->virtbase + CHAR_COM); + msleep(5); + writel(HD_FUNCSET | HD_FUNCSET_8BIT, lcd->virtbase + CHAR_COM); + udelay(100); + writel(HD_FUNCSET | HD_FUNCSET_8BIT, lcd->virtbase + CHAR_COM); + udelay(100); + /* Go to 4bit mode */ + writel(HD_FUNCSET, lcd->virtbase + CHAR_COM); + udelay(100); + /* + * 4bit mode, 2 lines, 5x8 font, after this the number of lines + * and the font cannot be changed until the next initialization sequence + */ + charlcd_4bit_command(lcd, HD_FUNCSET | HD_FUNCSET_2_LINES); + charlcd_4bit_command(lcd, HD_DISPCTRL | HD_DISPCTRL_ON); + charlcd_4bit_command(lcd, HD_ENTRYMODE | HD_ENTRYMODE_INCREMENT); + charlcd_4bit_command(lcd, HD_CLEAR); + charlcd_4bit_command(lcd, HD_HOME); + /* Put something useful in the display */ + charlcd_4bit_print(lcd, 0, "ARM Linux"); + charlcd_4bit_print(lcd, 1, UTS_RELEASE); +} + +static void charlcd_init_work(struct work_struct *work) +{ + struct charlcd *lcd = + container_of(work, struct charlcd, init_work.work); + + charlcd_4bit_init(lcd); +} + +static int __init charlcd_probe(struct platform_device *pdev) +{ + int ret; + struct charlcd *lcd; + struct resource *res; + + lcd = kzalloc(sizeof(struct charlcd), GFP_KERNEL); + if (!lcd) + return -ENOMEM; + + lcd->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -ENOENT; + goto out_no_resource; + } + lcd->phybase = res->start; + lcd->physize = resource_size(res); + + if (request_mem_region(lcd->phybase, lcd->physize, + DRIVERNAME) == NULL) { + ret = -EBUSY; + goto out_no_memregion; + } + + lcd->virtbase = ioremap(lcd->phybase, lcd->physize); + if (!lcd->virtbase) { + ret = -ENOMEM; + goto out_no_remap; + } + + lcd->irq = platform_get_irq(pdev, 0); + /* If no IRQ is supplied, we'll survive without it */ + if (lcd->irq >= 0) { + if (request_irq(lcd->irq, charlcd_interrupt, IRQF_DISABLED, + DRIVERNAME, lcd)) { + ret = -EIO; + goto out_no_irq; + } + } + + platform_set_drvdata(pdev, lcd); + + /* + * Initialize the display in a delayed work, because + * it is VERY slow and would slow down the boot of the system. + */ + INIT_DELAYED_WORK(&lcd->init_work, charlcd_init_work); + schedule_delayed_work(&lcd->init_work, 0); + + dev_info(&pdev->dev, "initalized ARM character LCD at %08x\n", + lcd->phybase); + + return 0; + +out_no_irq: + iounmap(lcd->virtbase); +out_no_remap: + platform_set_drvdata(pdev, NULL); +out_no_memregion: + release_mem_region(lcd->phybase, SZ_4K); +out_no_resource: + kfree(lcd); + return ret; +} + +static int __exit charlcd_remove(struct platform_device *pdev) +{ + struct charlcd *lcd = platform_get_drvdata(pdev); + + if (lcd) { + free_irq(lcd->irq, lcd); + iounmap(lcd->virtbase); + release_mem_region(lcd->phybase, lcd->physize); + platform_set_drvdata(pdev, NULL); + kfree(lcd); + } + + return 0; +} + +static int charlcd_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct charlcd *lcd = platform_get_drvdata(pdev); + + /* Power the display off */ + charlcd_4bit_command(lcd, HD_DISPCTRL); + return 0; +} + +static int charlcd_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct charlcd *lcd = platform_get_drvdata(pdev); + + /* Turn the display back on */ + charlcd_4bit_command(lcd, HD_DISPCTRL | HD_DISPCTRL_ON); + return 0; +} + +static const struct dev_pm_ops charlcd_pm_ops = { + .suspend = charlcd_suspend, + .resume = charlcd_resume, +}; + +static struct platform_driver charlcd_driver = { + .driver = { + .name = DRIVERNAME, + .owner = THIS_MODULE, + .pm = &charlcd_pm_ops, + }, + .remove = __exit_p(charlcd_remove), +}; + +static int __init charlcd_init(void) +{ + return platform_driver_probe(&charlcd_driver, charlcd_probe); +} + +static void __exit charlcd_exit(void) +{ + platform_driver_unregister(&charlcd_driver); +} + +module_init(charlcd_init); +module_exit(charlcd_exit); + +MODULE_AUTHOR("Linus Walleij <triad@df.lth.se>"); +MODULE_DESCRIPTION("ARM Character LCD Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 4917af96bae1..840b301b5671 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -26,7 +26,6 @@ #include <linux/amba/mmci.h> #include <linux/regulator/consumer.h> -#include <asm/cacheflush.h> #include <asm/div64.h> #include <asm/io.h> #include <asm/sizes.h> @@ -37,12 +36,39 @@ static unsigned int fmax = 515633; +/** + * struct variant_data - MMCI variant-specific quirks + * @clkreg: default value for MCICLOCK register + * @clkreg_enable: enable value for MMCICLOCK register + * @datalength_bits: number of bits in the MMCIDATALENGTH register + */ +struct variant_data { + unsigned int clkreg; + unsigned int clkreg_enable; + unsigned int datalength_bits; +}; + +static struct variant_data variant_arm = { + .datalength_bits = 16, +}; + +static struct variant_data variant_u300 = { + .clkreg_enable = 1 << 13, /* HWFCEN */ + .datalength_bits = 16, +}; + +static struct variant_data variant_ux500 = { + .clkreg = MCI_CLK_ENABLE, + .clkreg_enable = 1 << 14, /* HWFCEN */ + .datalength_bits = 24, +}; /* * This must be called with host->lock held */ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) { - u32 clk = 0; + struct variant_data *variant = host->variant; + u32 clk = variant->clkreg; if (desired) { if (desired >= host->mclk) { @@ -54,8 +80,8 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) clk = 255; host->cclk = host->mclk / (2 * (clk + 1)); } - if (host->hw_designer == AMBA_VENDOR_ST) - clk |= MCI_ST_FCEN; /* Bug fix in ST IP block */ + + clk |= variant->clkreg_enable; clk |= MCI_CLK_ENABLE; /* This hasn't proven to be worthwhile */ /* clk |= MCI_CLK_PWRSAVE; */ @@ -98,6 +124,18 @@ static void mmci_stop_data(struct mmci_host *host) host->data = NULL; } +static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) +{ + unsigned int flags = SG_MITER_ATOMIC; + + if (data->flags & MMC_DATA_READ) + flags |= SG_MITER_TO_SG; + else + flags |= SG_MITER_FROM_SG; + + sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); +} + static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) { unsigned int datactrl, timeout, irqmask; @@ -109,7 +147,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) data->blksz, data->blocks, data->flags); host->data = data; - host->size = data->blksz; + host->size = data->blksz * data->blocks; host->data_xfered = 0; mmci_init_sg(host, data); @@ -210,8 +248,17 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data, * We hit an error condition. Ensure that any data * partially written to a page is properly coherent. */ - if (host->sg_len && data->flags & MMC_DATA_READ) - flush_dcache_page(sg_page(host->sg_ptr)); + if (data->flags & MMC_DATA_READ) { + struct sg_mapping_iter *sg_miter = &host->sg_miter; + unsigned long flags; + + local_irq_save(flags); + if (sg_miter_next(sg_miter)) { + flush_dcache_page(sg_miter->page); + sg_miter_stop(sg_miter); + } + local_irq_restore(flags); + } } if (status & MCI_DATAEND) { mmci_stop_data(host); @@ -314,15 +361,18 @@ static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int rem static irqreturn_t mmci_pio_irq(int irq, void *dev_id) { struct mmci_host *host = dev_id; + struct sg_mapping_iter *sg_miter = &host->sg_miter; void __iomem *base = host->base; + unsigned long flags; u32 status; status = readl(base + MMCISTATUS); dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); + local_irq_save(flags); + do { - unsigned long flags; unsigned int remain, len; char *buffer; @@ -336,11 +386,11 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id) if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) break; - /* - * Map the current scatter buffer. - */ - buffer = mmci_kmap_atomic(host, &flags) + host->sg_off; - remain = host->sg_ptr->length - host->sg_off; + if (!sg_miter_next(sg_miter)) + break; + + buffer = sg_miter->addr; + remain = sg_miter->length; len = 0; if (status & MCI_RXACTIVE) @@ -348,31 +398,24 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id) if (status & MCI_TXACTIVE) len = mmci_pio_write(host, buffer, remain, status); - /* - * Unmap the buffer. - */ - mmci_kunmap_atomic(host, buffer, &flags); + sg_miter->consumed = len; - host->sg_off += len; host->size -= len; remain -= len; if (remain) break; - /* - * If we were reading, and we have completed this - * page, ensure that the data cache is coherent. - */ if (status & MCI_RXACTIVE) - flush_dcache_page(sg_page(host->sg_ptr)); - - if (!mmci_next_sg(host)) - break; + flush_dcache_page(sg_miter->page); status = readl(base + MMCISTATUS); } while (1); + sg_miter_stop(sg_miter); + + local_irq_restore(flags); + /* * If we're nearing the end of the read, switch to * "any data available" mode. @@ -477,16 +520,9 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) /* This implicitly enables the regulator */ mmc_regulator_set_ocr(host->vcc, ios->vdd); #endif - /* - * The translate_vdd function is not used if you have - * an external regulator, or your design is really weird. - * Using it would mean sending in power control BOTH using - * a regulator AND the 4 MMCIPWR bits. If we don't have - * a regulator, we might have some other platform specific - * power control behind this translate function. - */ - if (!host->vcc && host->plat->translate_vdd) - pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd); + if (host->plat->vdd_handler) + pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd, + ios->power_mode); /* The ST version does not have this, fall through to POWER_ON */ if (host->hw_designer != AMBA_VENDOR_ST) { pwr |= MCI_PWR_UP; @@ -539,9 +575,13 @@ static int mmci_get_cd(struct mmc_host *mmc) if (host->gpio_cd == -ENOSYS) status = host->plat->status(mmc_dev(host->mmc)); else - status = gpio_get_value(host->gpio_cd); + status = !gpio_get_value(host->gpio_cd); - return !status; + /* + * Use positive logic throughout - status is zero for no card, + * non-zero for card inserted. + */ + return status; } static const struct mmc_host_ops mmci_ops = { @@ -551,21 +591,10 @@ static const struct mmc_host_ops mmci_ops = { .get_cd = mmci_get_cd, }; -static void mmci_check_status(unsigned long data) -{ - struct mmci_host *host = (struct mmci_host *)data; - unsigned int status = mmci_get_cd(host->mmc); - - if (status ^ host->oldstat) - mmc_detect_change(host->mmc, 0); - - host->oldstat = status; - mod_timer(&host->timer, jiffies + HZ); -} - static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) { struct mmci_platform_data *plat = dev->dev.platform_data; + struct variant_data *variant = id->data; struct mmci_host *host; struct mmc_host *mmc; int ret; @@ -609,6 +638,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) goto clk_free; host->plat = plat; + host->variant = variant; host->mclk = clk_get_rate(host->clk); /* * According to the spec, mclk is max 100 MHz, @@ -669,6 +699,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) if (host->vcc == NULL) mmc->ocr_avail = plat->ocr_mask; mmc->caps = plat->capabilities; + mmc->caps |= MMC_CAP_NEEDS_POLL; /* * We can do SGIO @@ -677,10 +708,11 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) mmc->max_phys_segs = NR_SG; /* - * Since we only have a 16-bit data length register, we must - * ensure that we don't exceed 2^16-1 bytes in a single request. + * Since only a certain number of bits are valid in the data length + * register, we must ensure that we don't exceed 2^num-1 bytes in a + * single request. */ - mmc->max_req_size = 65535; + mmc->max_req_size = (1 << variant->datalength_bits) - 1; /* * Set the maximum segment size. Since we aren't doing DMA @@ -734,7 +766,6 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) writel(MCI_IRQENABLE, host->base + MMCIMASK0); amba_set_drvdata(dev, mmc); - host->oldstat = mmci_get_cd(host->mmc); mmc_add_host(mmc); @@ -742,12 +773,6 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) mmc_hostname(mmc), amba_rev(dev), amba_config(dev), (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); - init_timer(&host->timer); - host->timer.data = (unsigned long)host; - host->timer.function = mmci_check_status; - host->timer.expires = jiffies + HZ; - add_timer(&host->timer); - return 0; irq0_free: @@ -781,8 +806,6 @@ static int __devexit mmci_remove(struct amba_device *dev) if (mmc) { struct mmci_host *host = mmc_priv(mmc); - del_timer_sync(&host->timer); - mmc_remove_host(mmc); writel(0, host->base + MMCIMASK0); @@ -856,19 +879,28 @@ static struct amba_id mmci_ids[] = { { .id = 0x00041180, .mask = 0x000fffff, + .data = &variant_arm, }, { .id = 0x00041181, .mask = 0x000fffff, + .data = &variant_arm, }, /* ST Micro variants */ { .id = 0x00180180, .mask = 0x00ffffff, + .data = &variant_u300, }, { .id = 0x00280180, .mask = 0x00ffffff, + .data = &variant_u300, + }, + { + .id = 0x00480180, + .mask = 0x00ffffff, + .data = &variant_ux500, }, { 0, 0 }, }; diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index d77062e5e3af..68970cfb81e1 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -28,8 +28,6 @@ #define MCI_4BIT_BUS (1 << 11) /* 8bit wide buses supported in ST Micro versions */ #define MCI_ST_8BIT_BUS (1 << 12) -/* HW flow control on the ST Micro version */ -#define MCI_ST_FCEN (1 << 13) #define MMCIARGUMENT 0x008 #define MMCICOMMAND 0x00c @@ -145,6 +143,7 @@ #define NR_SG 16 struct clk; +struct variant_data; struct mmci_host { void __iomem *base; @@ -164,6 +163,7 @@ struct mmci_host { unsigned int cclk; u32 pwr; struct mmci_platform_data *plat; + struct variant_data *variant; u8 hw_designer; u8 hw_revision:4; @@ -171,42 +171,9 @@ struct mmci_host { struct timer_list timer; unsigned int oldstat; - unsigned int sg_len; - /* pio stuff */ - struct scatterlist *sg_ptr; - unsigned int sg_off; + struct sg_mapping_iter sg_miter; unsigned int size; struct regulator *vcc; }; -static inline void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) -{ - /* - * Ideally, we want the higher levels to pass us a scatter list. - */ - host->sg_len = data->sg_len; - host->sg_ptr = data->sg; - host->sg_off = 0; -} - -static inline int mmci_next_sg(struct mmci_host *host) -{ - host->sg_ptr++; - host->sg_off = 0; - return --host->sg_len; -} - -static inline char *mmci_kmap_atomic(struct mmci_host *host, unsigned long *flags) -{ - struct scatterlist *sg = host->sg_ptr; - - local_irq_save(*flags); - return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; -} - -static inline void mmci_kunmap_atomic(struct mmci_host *host, void *buffer, unsigned long *flags) -{ - kunmap_atomic(buffer, KM_BIO_SRC_IRQ); - local_irq_restore(*flags); -} diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c index d9d4a72e0ec7..350f78e86245 100644 --- a/drivers/mmc/host/mxcmmc.c +++ b/drivers/mmc/host/mxcmmc.c @@ -119,6 +119,7 @@ struct mxcmci_host { int detect_irq; int dma; int do_dma; + int default_irq_mask; int use_sdio; unsigned int power_mode; struct imxmmc_platform_data *pdata; @@ -228,7 +229,7 @@ static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, unsigned int cmdat) { - u32 int_cntr; + u32 int_cntr = host->default_irq_mask; unsigned long flags; WARN_ON(host->cmd != NULL); @@ -275,7 +276,7 @@ static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, static void mxcmci_finish_request(struct mxcmci_host *host, struct mmc_request *req) { - u32 int_cntr = 0; + u32 int_cntr = host->default_irq_mask; unsigned long flags; spin_lock_irqsave(&host->lock, flags); @@ -585,6 +586,9 @@ static irqreturn_t mxcmci_irq(int irq, void *devid) (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE))) mxcmci_data_done(host, stat); #endif + if (host->default_irq_mask && + (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL))) + mmc_detect_change(host->mmc, msecs_to_jiffies(200)); return IRQ_HANDLED; } @@ -809,6 +813,12 @@ static int mxcmci_probe(struct platform_device *pdev) else mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; + if (host->pdata && host->pdata->dat3_card_detect) + host->default_irq_mask = + INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN; + else + host->default_irq_mask = 0; + host->res = r; host->irq = irq; @@ -835,7 +845,7 @@ static int mxcmci_probe(struct platform_device *pdev) /* recommended in data sheet */ writew(0x2db4, host->base + MMC_REG_READ_TO); - writel(0, host->base + MMC_REG_INT_CNTR); + writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR); #ifdef HAS_DMA host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW); @@ -926,43 +936,47 @@ static int mxcmci_remove(struct platform_device *pdev) } #ifdef CONFIG_PM -static int mxcmci_suspend(struct platform_device *dev, pm_message_t state) +static int mxcmci_suspend(struct device *dev) { - struct mmc_host *mmc = platform_get_drvdata(dev); + struct mmc_host *mmc = dev_get_drvdata(dev); + struct mxcmci_host *host = mmc_priv(mmc); int ret = 0; if (mmc) ret = mmc_suspend_host(mmc); + clk_disable(host->clk); return ret; } -static int mxcmci_resume(struct platform_device *dev) +static int mxcmci_resume(struct device *dev) { - struct mmc_host *mmc = platform_get_drvdata(dev); - struct mxcmci_host *host; + struct mmc_host *mmc = dev_get_drvdata(dev); + struct mxcmci_host *host = mmc_priv(mmc); int ret = 0; - if (mmc) { - host = mmc_priv(mmc); + clk_enable(host->clk); + if (mmc) ret = mmc_resume_host(mmc); - } return ret; } -#else -#define mxcmci_suspend NULL -#define mxcmci_resume NULL -#endif /* CONFIG_PM */ + +static const struct dev_pm_ops mxcmci_pm_ops = { + .suspend = mxcmci_suspend, + .resume = mxcmci_resume, +}; +#endif static struct platform_driver mxcmci_driver = { .probe = mxcmci_probe, .remove = mxcmci_remove, - .suspend = mxcmci_suspend, - .resume = mxcmci_resume, .driver = { .name = DRIVER_NAME, .owner = THIS_MODULE, +#ifdef CONFIG_PM + .pm = &mxcmci_pm_ops, +#endif } }; diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 82e94389824e..0d76b169482f 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -623,8 +623,7 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command, else host->buf_start = column + mtd->writesize; - if (mtd->writesize > 512) - command = NAND_CMD_READ0; /* only READ0 is valid */ + command = NAND_CMD_READ0; /* only READ0 is valid */ send_cmd(host, command, false); mxc_do_addr_cycle(mtd, column, page_addr); @@ -639,31 +638,11 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command, break; case NAND_CMD_SEQIN: - if (column >= mtd->writesize) { - /* - * FIXME: before send SEQIN command for write OOB, - * We must read one page out. - * For K9F1GXX has no READ1 command to set current HW - * pointer to spare area, we must write the whole page - * including OOB together. - */ - if (mtd->writesize > 512) - /* call ourself to read a page */ - mxc_nand_command(mtd, NAND_CMD_READ0, 0, - page_addr); - - host->buf_start = column; - - /* Set program pointer to spare region */ - if (mtd->writesize == 512) - send_cmd(host, NAND_CMD_READOOB, false); - } else { - host->buf_start = column; + if (column >= mtd->writesize) + /* call ourself to read a page */ + mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr); - /* Set program pointer to page start */ - if (mtd->writesize == 512) - send_cmd(host, NAND_CMD_READ0, false); - } + host->buf_start = column; send_cmd(host, command, false); mxc_do_addr_cycle(mtd, column, page_addr); @@ -853,6 +832,8 @@ static int __init mxcnd_probe(struct platform_device *pdev) parse_mtd_partitions(mtd, part_probes, &host->parts, 0); if (nr_parts > 0) add_mtd_partitions(mtd, host->parts, nr_parts); + else if (pdata->parts) + add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts); else #endif { diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 13b05cb33b08..78ae89488a4f 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -593,6 +593,7 @@ static int attach_by_scanning(struct ubi_device *ubi) ubi->good_peb_count = ubi->peb_count - ubi->bad_peb_count; ubi->max_ec = si->max_ec; ubi->mean_ec = si->mean_ec; + ubi_msg("max. sequence number: %llu", si->max_sqnum); err = ubi_read_volume_table(ubi, si); if (err) @@ -981,7 +982,7 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset) ubi_msg("number of PEBs reserved for bad PEB handling: %d", ubi->beb_rsvd_pebs); ubi_msg("max/mean erase counter: %d/%d", ubi->max_ec, ubi->mean_ec); - ubi_msg("image sequence number: %d", ubi->image_seq); + ubi_msg("image sequence number: %d", ubi->image_seq); /* * The below lock makes sure we do not race with 'ubi_thread()' which diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c index 9f87c99189a9..fe74749e0dae 100644 --- a/drivers/mtd/ubi/eba.c +++ b/drivers/mtd/ubi/eba.c @@ -418,7 +418,8 @@ retry: * may try to recover data. FIXME: but this is * not implemented. */ - if (err == UBI_IO_BAD_VID_HDR) { + if (err == UBI_IO_BAD_HDR_READ || + err == UBI_IO_BAD_HDR) { ubi_warn("corrupted VID header at PEB " "%d, LEB %d:%d", pnum, vol_id, lnum); @@ -961,8 +962,8 @@ write_error: */ static int is_error_sane(int err) { - if (err == -EIO || err == -ENOMEM || err == UBI_IO_BAD_VID_HDR || - err == -ETIMEDOUT) + if (err == -EIO || err == -ENOMEM || err == UBI_IO_BAD_HDR || + err == UBI_IO_BAD_HDR_READ || err == -ETIMEDOUT) return 0; return 1; } @@ -1165,6 +1166,44 @@ out_unlock_leb: } /** + * print_rsvd_warning - warn about not having enough reserved PEBs. + * @ubi: UBI device description object + * + * This is a helper function for 'ubi_eba_init_scan()' which is called when UBI + * cannot reserve enough PEBs for bad block handling. This function makes a + * decision whether we have to print a warning or not. The algorithm is as + * follows: + * o if this is a new UBI image, then just print the warning + * o if this is an UBI image which has already been used for some time, print + * a warning only if we can reserve less than 10% of the expected amount of + * the reserved PEB. + * + * The idea is that when UBI is used, PEBs become bad, and the reserved pool + * of PEBs becomes smaller, which is normal and we do not want to scare users + * with a warning every time they attach the MTD device. This was an issue + * reported by real users. + */ +static void print_rsvd_warning(struct ubi_device *ubi, + struct ubi_scan_info *si) +{ + /* + * The 1 << 18 (256KiB) number is picked randomly, just a reasonably + * large number to distinguish between newly flashed and used images. + */ + if (si->max_sqnum > (1 << 18)) { + int min = ubi->beb_rsvd_level / 10; + + if (!min) + min = 1; + if (ubi->beb_rsvd_pebs > min) + return; + } + + ubi_warn("cannot reserve enough PEBs for bad PEB handling, reserved %d," + " need %d", ubi->beb_rsvd_pebs, ubi->beb_rsvd_level); +} + +/** * ubi_eba_init_scan - initialize the EBA sub-system using scanning information. * @ubi: UBI device description object * @si: scanning information @@ -1236,9 +1275,7 @@ int ubi_eba_init_scan(struct ubi_device *ubi, struct ubi_scan_info *si) if (ubi->avail_pebs < ubi->beb_rsvd_level) { /* No enough free physical eraseblocks */ ubi->beb_rsvd_pebs = ubi->avail_pebs; - ubi_warn("cannot reserve enough PEBs for bad PEB " - "handling, reserved %d, need %d", - ubi->beb_rsvd_pebs, ubi->beb_rsvd_level); + print_rsvd_warning(ubi, si); } else ubi->beb_rsvd_pebs = ubi->beb_rsvd_level; diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index 4b979e34b159..332f992f13d9 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -150,6 +150,8 @@ int ubi_io_read(const struct ubi_device *ubi, void *buf, int pnum, int offset, retry: err = ubi->mtd->read(ubi->mtd, addr, len, &read, buf); if (err) { + const char *errstr = (err == -EBADMSG) ? " (ECC error)" : ""; + if (err == -EUCLEAN) { /* * -EUCLEAN is reported if there was a bit-flip which @@ -165,15 +167,15 @@ retry: } if (read != len && retries++ < UBI_IO_RETRIES) { - dbg_io("error %d while reading %d bytes from PEB %d:%d," + dbg_io("error %d%s while reading %d bytes from PEB %d:%d," " read only %zd bytes, retry", - err, len, pnum, offset, read); + err, errstr, len, pnum, offset, read); yield(); goto retry; } - ubi_err("error %d while reading %d bytes from PEB %d:%d, " - "read %zd bytes", err, len, pnum, offset, read); + ubi_err("error %d%s while reading %d bytes from PEB %d:%d, " + "read %zd bytes", err, errstr, len, pnum, offset, read); ubi_dbg_dump_stack(); /* @@ -515,7 +517,7 @@ static int nor_erase_prepare(struct ubi_device *ubi, int pnum) * In this case we probably anyway have garbage in this PEB. */ err1 = ubi_io_read_vid_hdr(ubi, pnum, &vid_hdr, 0); - if (err1 == UBI_IO_BAD_VID_HDR) + if (err1 == UBI_IO_BAD_HDR_READ || err1 == UBI_IO_BAD_HDR) /* * The VID header is corrupted, so we can safely erase this * PEB and not afraid that it will be treated as a valid PEB in @@ -709,7 +711,7 @@ bad: * o %UBI_IO_BITFLIPS if the CRC is correct, but bit-flips were detected * and corrected by the flash driver; this is harmless but may indicate that * this eraseblock may become bad soon (but may be not); - * o %UBI_IO_BAD_EC_HDR if the erase counter header is corrupted (a CRC error); + * o %UBI_IO_BAD_HDR if the erase counter header is corrupted (a CRC error); * o %UBI_IO_PEB_EMPTY if the physical eraseblock is empty; * o a negative error code in case of failure. */ @@ -736,23 +738,21 @@ int ubi_io_read_ec_hdr(struct ubi_device *ubi, int pnum, * header is still OK, we just report this as there was a * bit-flip. */ - read_err = err; + if (err == -EBADMSG) + read_err = UBI_IO_BAD_HDR_READ; } magic = be32_to_cpu(ec_hdr->magic); if (magic != UBI_EC_HDR_MAGIC) { + if (read_err) + return read_err; + /* * The magic field is wrong. Let's check if we have read all * 0xFF. If yes, this physical eraseblock is assumed to be * empty. - * - * But if there was a read error, we do not test it for all - * 0xFFs. Even if it does contain all 0xFFs, this error - * indicates that something is still wrong with this physical - * eraseblock and we anyway cannot treat it as empty. */ - if (read_err != -EBADMSG && - check_pattern(ec_hdr, 0xFF, UBI_EC_HDR_SIZE)) { + if (check_pattern(ec_hdr, 0xFF, UBI_EC_HDR_SIZE)) { /* The physical eraseblock is supposedly empty */ if (verbose) ubi_warn("no EC header found at PEB %d, " @@ -774,7 +774,7 @@ int ubi_io_read_ec_hdr(struct ubi_device *ubi, int pnum, } else if (UBI_IO_DEBUG) dbg_msg("bad magic number at PEB %d: %08x instead of " "%08x", pnum, magic, UBI_EC_HDR_MAGIC); - return UBI_IO_BAD_EC_HDR; + return UBI_IO_BAD_HDR; } crc = crc32(UBI_CRC32_INIT, ec_hdr, UBI_EC_HDR_SIZE_CRC); @@ -788,7 +788,7 @@ int ubi_io_read_ec_hdr(struct ubi_device *ubi, int pnum, } else if (UBI_IO_DEBUG) dbg_msg("bad EC header CRC at PEB %d, calculated " "%#08x, read %#08x", pnum, crc, hdr_crc); - return UBI_IO_BAD_EC_HDR; + return read_err ?: UBI_IO_BAD_HDR; } /* And of course validate what has just been read from the media */ @@ -798,6 +798,10 @@ int ubi_io_read_ec_hdr(struct ubi_device *ubi, int pnum, return -EINVAL; } + /* + * If there was %-EBADMSG, but the header CRC is still OK, report about + * a bit-flip to force scrubbing on this PEB. + */ return read_err ? UBI_IO_BITFLIPS : 0; } @@ -977,7 +981,7 @@ bad: * o %UBI_IO_BITFLIPS if the CRC is correct, but bit-flips were detected * and corrected by the flash driver; this is harmless but may indicate that * this eraseblock may become bad soon; - * o %UBI_IO_BAD_VID_HDR if the volume identifier header is corrupted (a CRC + * o %UBI_IO_BAD_HDR if the volume identifier header is corrupted (a CRC * error detected); * o %UBI_IO_PEB_FREE if the physical eraseblock is free (i.e., there is no VID * header there); @@ -1008,22 +1012,20 @@ int ubi_io_read_vid_hdr(struct ubi_device *ubi, int pnum, * CRC check-sum and we will identify this. If the VID header is * still OK, we just report this as there was a bit-flip. */ - read_err = err; + if (err == -EBADMSG) + read_err = UBI_IO_BAD_HDR_READ; } magic = be32_to_cpu(vid_hdr->magic); if (magic != UBI_VID_HDR_MAGIC) { + if (read_err) + return read_err; + /* * If we have read all 0xFF bytes, the VID header probably does * not exist and the physical eraseblock is assumed to be free. - * - * But if there was a read error, we do not test the data for - * 0xFFs. Even if it does contain all 0xFFs, this error - * indicates that something is still wrong with this physical - * eraseblock and it cannot be regarded as free. */ - if (read_err != -EBADMSG && - check_pattern(vid_hdr, 0xFF, UBI_VID_HDR_SIZE)) { + if (check_pattern(vid_hdr, 0xFF, UBI_VID_HDR_SIZE)) { /* The physical eraseblock is supposedly free */ if (verbose) ubi_warn("no VID header found at PEB %d, " @@ -1045,7 +1047,7 @@ int ubi_io_read_vid_hdr(struct ubi_device *ubi, int pnum, } else if (UBI_IO_DEBUG) dbg_msg("bad magic number at PEB %d: %08x instead of " "%08x", pnum, magic, UBI_VID_HDR_MAGIC); - return UBI_IO_BAD_VID_HDR; + return UBI_IO_BAD_HDR; } crc = crc32(UBI_CRC32_INIT, vid_hdr, UBI_VID_HDR_SIZE_CRC); @@ -1059,7 +1061,7 @@ int ubi_io_read_vid_hdr(struct ubi_device *ubi, int pnum, } else if (UBI_IO_DEBUG) dbg_msg("bad CRC at PEB %d, calculated %#08x, " "read %#08x", pnum, crc, hdr_crc); - return UBI_IO_BAD_VID_HDR; + return read_err ?: UBI_IO_BAD_HDR; } /* Validate the VID header that we have just read */ @@ -1069,6 +1071,10 @@ int ubi_io_read_vid_hdr(struct ubi_device *ubi, int pnum, return -EINVAL; } + /* + * If there was a read error (%-EBADMSG), but the header CRC is still + * OK, report about a bit-flip to force scrubbing on this PEB. + */ return read_err ? UBI_IO_BITFLIPS : 0; } diff --git a/drivers/mtd/ubi/scan.c b/drivers/mtd/ubi/scan.c index aed19f33b8f3..372a15ac9995 100644 --- a/drivers/mtd/ubi/scan.c +++ b/drivers/mtd/ubi/scan.c @@ -44,6 +44,7 @@ #include <linux/slab.h> #include <linux/crc32.h> #include <linux/math64.h> +#include <linux/random.h> #include "ubi.h" #ifdef CONFIG_MTD_UBI_DEBUG_PARANOID @@ -72,16 +73,19 @@ static int add_to_list(struct ubi_scan_info *si, int pnum, int ec, { struct ubi_scan_leb *seb; - if (list == &si->free) + if (list == &si->free) { dbg_bld("add to free: PEB %d, EC %d", pnum, ec); - else if (list == &si->erase) + si->free_peb_count += 1; + } else if (list == &si->erase) { dbg_bld("add to erase: PEB %d, EC %d", pnum, ec); - else if (list == &si->corr) { + si->erase_peb_count += 1; + } else if (list == &si->corr) { dbg_bld("add to corrupted: PEB %d, EC %d", pnum, ec); - si->corr_count += 1; - } else if (list == &si->alien) + si->corr_peb_count += 1; + } else if (list == &si->alien) { dbg_bld("add to alien: PEB %d, EC %d", pnum, ec); - else + si->alien_peb_count += 1; + } else BUG(); seb = kmalloc(sizeof(struct ubi_scan_leb), GFP_KERNEL); @@ -517,6 +521,7 @@ int ubi_scan_add_used(struct ubi_device *ubi, struct ubi_scan_info *si, sv->leb_count += 1; rb_link_node(&seb->u.rb, parent, p); rb_insert_color(&seb->u.rb, &sv->root); + si->used_peb_count += 1; return 0; } @@ -745,19 +750,17 @@ static int process_eb(struct ubi_device *ubi, struct ubi_scan_info *si, bitflips = 1; else if (err == UBI_IO_PEB_EMPTY) return add_to_list(si, pnum, UBI_SCAN_UNKNOWN_EC, &si->erase); - else if (err == UBI_IO_BAD_EC_HDR) { + else if (err == UBI_IO_BAD_HDR_READ || err == UBI_IO_BAD_HDR) { /* * We have to also look at the VID header, possibly it is not * corrupted. Set %bitflips flag in order to make this PEB be * moved and EC be re-created. */ - ec_corr = 1; + ec_corr = err; ec = UBI_SCAN_UNKNOWN_EC; bitflips = 1; } - si->is_empty = 0; - if (!ec_corr) { int image_seq; @@ -813,9 +816,12 @@ static int process_eb(struct ubi_device *ubi, struct ubi_scan_info *si, return err; else if (err == UBI_IO_BITFLIPS) bitflips = 1; - else if (err == UBI_IO_BAD_VID_HDR || + else if (err == UBI_IO_BAD_HDR_READ || err == UBI_IO_BAD_HDR || (err == UBI_IO_PEB_FREE && ec_corr)) { /* VID header is corrupted */ + if (err == UBI_IO_BAD_HDR_READ || + ec_corr == UBI_IO_BAD_HDR_READ) + si->read_err_count += 1; err = add_to_list(si, pnum, ec, &si->corr); if (err) return err; @@ -836,11 +842,11 @@ static int process_eb(struct ubi_device *ubi, struct ubi_scan_info *si, switch (vidh->compat) { case UBI_COMPAT_DELETE: ubi_msg("\"delete\" compatible internal volume %d:%d" - " found, remove it", vol_id, lnum); + " found, will remove it", vol_id, lnum); err = add_to_list(si, pnum, ec, &si->corr); if (err) return err; - break; + return 0; case UBI_COMPAT_RO: ubi_msg("read-only compatible internal volume %d:%d" @@ -855,7 +861,6 @@ static int process_eb(struct ubi_device *ubi, struct ubi_scan_info *si, err = add_to_list(si, pnum, ec, &si->alien); if (err) return err; - si->alien_peb_count += 1; return 0; case UBI_COMPAT_REJECT: @@ -886,6 +891,85 @@ adjust_mean_ec: } /** + * check_what_we_have - check what PEB were found by scanning. + * @ubi: UBI device description object + * @si: scanning information + * + * This is a helper function which takes a look what PEBs were found by + * scanning, and decides whether the flash is empty and should be formatted and + * whether there are too many corrupted PEBs and we should not attach this + * MTD device. Returns zero if we should proceed with attaching the MTD device, + * and %-EINVAL if we should not. + */ +static int check_what_we_have(struct ubi_device *ubi, struct ubi_scan_info *si) +{ + struct ubi_scan_leb *seb; + int max_corr; + + max_corr = ubi->peb_count - si->bad_peb_count - si->alien_peb_count; + max_corr = max_corr / 20 ?: 8; + + /* + * Few corrupted PEBs are not a problem and may be just a result of + * unclean reboots. However, many of them may indicate some problems + * with the flash HW or driver. + */ + if (si->corr_peb_count >= 8) { + ubi_warn("%d PEBs are corrupted", si->corr_peb_count); + printk(KERN_WARNING "corrupted PEBs are:"); + list_for_each_entry(seb, &si->corr, u.list) + printk(KERN_CONT " %d", seb->pnum); + printk(KERN_CONT "\n"); + + /* + * If too many PEBs are corrupted, we refuse attaching, + * otherwise, only print a warning. + */ + if (si->corr_peb_count >= max_corr) { + ubi_err("too many corrupted PEBs, refusing this device"); + return -EINVAL; + } + } + + if (si->free_peb_count + si->used_peb_count + + si->alien_peb_count == 0) { + /* No UBI-formatted eraseblocks were found */ + if (si->corr_peb_count == si->read_err_count && + si->corr_peb_count < 8) { + /* No or just few corrupted PEBs, and all of them had a + * read error. We assume that those are bad PEBs, which + * were just not marked as bad so far. + * + * This piece of code basically tries to distinguish + * between the following 2 situations: + * + * 1. Flash is empty, but there are few bad PEBs, which + * are not marked as bad so far, and which were read + * with error. We want to go ahead and format this + * flash. While formating, the faulty PEBs will + * probably be marked as bad. + * + * 2. Flash probably contains non-UBI data and we do + * not want to format it and destroy possibly needed + * data (e.g., consider the case when the bootloader + * MTD partition was accidentally fed to UBI). + */ + si->is_empty = 1; + ubi_msg("empty MTD device detected"); + get_random_bytes(&ubi->image_seq, sizeof(ubi->image_seq)); + } else { + ubi_err("MTD device possibly contains non-UBI data, " + "refusing it"); + return -EINVAL; + } + } + + if (si->corr_peb_count > 0) + ubi_msg("corrupted PEBs will be formatted"); + return 0; +} + +/** * ubi_scan - scan an MTD device. * @ubi: UBI device description object * @@ -909,7 +993,6 @@ struct ubi_scan_info *ubi_scan(struct ubi_device *ubi) INIT_LIST_HEAD(&si->erase); INIT_LIST_HEAD(&si->alien); si->volumes = RB_ROOT; - si->is_empty = 1; err = -ENOMEM; ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL); @@ -935,21 +1018,9 @@ struct ubi_scan_info *ubi_scan(struct ubi_device *ubi) if (si->ec_count) si->mean_ec = div_u64(si->ec_sum, si->ec_count); - if (si->is_empty) - ubi_msg("empty MTD device detected"); - - /* - * Few corrupted PEBs are not a problem and may be just a result of - * unclean reboots. However, many of them may indicate some problems - * with the flash HW or driver. Print a warning in this case. - */ - if (si->corr_count >= 8 || si->corr_count >= ubi->peb_count / 4) { - ubi_warn("%d PEBs are corrupted", si->corr_count); - printk(KERN_WARNING "corrupted PEBs are:"); - list_for_each_entry(seb, &si->corr, u.list) - printk(KERN_CONT " %d", seb->pnum); - printk(KERN_CONT "\n"); - } + err = check_what_we_have(ubi, si); + if (err) + goto out_vidh; /* * In case of unknown erase counter we use the mean erase counter diff --git a/drivers/mtd/ubi/scan.h b/drivers/mtd/ubi/scan.h index ff179ad7ca55..2576a8d1532b 100644 --- a/drivers/mtd/ubi/scan.h +++ b/drivers/mtd/ubi/scan.h @@ -91,10 +91,16 @@ struct ubi_scan_volume { * @erase: list of physical eraseblocks which have to be erased * @alien: list of physical eraseblocks which should not be used by UBI (e.g., * those belonging to "preserve"-compatible internal volumes) + * @used_peb_count: count of used PEBs + * @corr_peb_count: count of PEBs in the @corr list + * @read_err_count: count of PEBs read with error (%UBI_IO_BAD_HDR_READ was + * returned) + * @free_peb_count: count of PEBs in the @free list + * @erase_peb_count: count of PEBs in the @erase list + * @alien_peb_count: count of PEBs in the @alien list * @bad_peb_count: count of bad physical eraseblocks * @vols_found: number of volumes found during scanning * @highest_vol_id: highest volume ID - * @alien_peb_count: count of physical eraseblocks in the @alien list * @is_empty: flag indicating whether the MTD device is empty or not * @min_ec: lowest erase counter value * @max_ec: highest erase counter value @@ -102,7 +108,6 @@ struct ubi_scan_volume { * @mean_ec: mean erase counter value * @ec_sum: a temporary variable used when calculating @mean_ec * @ec_count: a temporary variable used when calculating @mean_ec - * @corr_count: count of corrupted PEBs * * This data structure contains the result of scanning and may be used by other * UBI sub-systems to build final UBI data structures, further error-recovery @@ -114,10 +119,15 @@ struct ubi_scan_info { struct list_head free; struct list_head erase; struct list_head alien; + int used_peb_count; + int corr_peb_count; + int read_err_count; + int free_peb_count; + int erase_peb_count; + int alien_peb_count; int bad_peb_count; int vols_found; int highest_vol_id; - int alien_peb_count; int is_empty; int min_ec; int max_ec; @@ -125,7 +135,6 @@ struct ubi_scan_info { int mean_ec; uint64_t ec_sum; int ec_count; - int corr_count; }; struct ubi_device; @@ -135,7 +144,7 @@ struct ubi_vid_hdr; * ubi_scan_move_to_list - move a PEB from the volume tree to a list. * * @sv: volume scanning information - * @seb: scanning eraseblock infprmation + * @seb: scanning eraseblock information * @list: the list to move to */ static inline void ubi_scan_move_to_list(struct ubi_scan_volume *sv, diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h index a637f0283add..0359e0cce482 100644 --- a/drivers/mtd/ubi/ubi.h +++ b/drivers/mtd/ubi/ubi.h @@ -89,16 +89,16 @@ * %0xFF bytes * UBI_IO_PEB_FREE: the physical eraseblock is free, i.e. it contains only a * valid erase counter header, and the rest are %0xFF bytes - * UBI_IO_BAD_EC_HDR: the erase counter header is corrupted (bad magic or CRC) - * UBI_IO_BAD_VID_HDR: the volume identifier header is corrupted (bad magic or - * CRC) + * UBI_IO_BAD_HDR: the EC or VID header is corrupted (bad magic or CRC) + * UBI_IO_BAD_HDR_READ: the same as %UBI_IO_BAD_HDR, but also there was a read + * error reported by the flash driver * UBI_IO_BITFLIPS: bit-flips were detected and corrected */ enum { UBI_IO_PEB_EMPTY = 1, UBI_IO_PEB_FREE, - UBI_IO_BAD_EC_HDR, - UBI_IO_BAD_VID_HDR, + UBI_IO_BAD_HDR, + UBI_IO_BAD_HDR_READ, UBI_IO_BITFLIPS }; diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 78b74e83ce5d..5a1bd5db2a93 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -29,6 +29,7 @@ #include <linux/mii.h> #include <linux/ethtool.h> #include <linux/phy.h> +#include <linux/marvell_phy.h> #include <asm/io.h> #include <asm/irq.h> @@ -48,8 +49,6 @@ #define MII_M1145_RGMII_RX_DELAY 0x0080 #define MII_M1145_RGMII_TX_DELAY 0x0002 -#define M1145_DEV_FLAGS_RESISTANCE 0x00000001 - #define MII_M1111_PHY_LED_CONTROL 0x18 #define MII_M1111_PHY_LED_DIRECT 0x4100 #define MII_M1111_PHY_LED_COMBINE 0x411c @@ -350,7 +349,10 @@ static int m88e1118_config_init(struct phy_device *phydev) return err; /* Adjust LED Control */ - err = phy_write(phydev, 0x10, 0x021e); + if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS) + err = phy_write(phydev, 0x10, 0x1100); + else + err = phy_write(phydev, 0x10, 0x021e); if (err < 0) return err; @@ -398,7 +400,7 @@ static int m88e1145_config_init(struct phy_device *phydev) if (err < 0) return err; - if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) { + if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) { err = phy_write(phydev, 0x1d, 0x0012); if (err < 0) return err; @@ -529,8 +531,8 @@ static int m88e1121_did_interrupt(struct phy_device *phydev) static struct phy_driver marvell_drivers[] = { { - .phy_id = 0x01410c60, - .phy_id_mask = 0xfffffff0, + .phy_id = MARVELL_PHY_ID_88E1101, + .phy_id_mask = MARVELL_PHY_ID_MASK, .name = "Marvell 88E1101", .features = PHY_GBIT_FEATURES, .flags = PHY_HAS_INTERRUPT, @@ -541,8 +543,8 @@ static struct phy_driver marvell_drivers[] = { .driver = { .owner = THIS_MODULE }, }, { - .phy_id = 0x01410c90, - .phy_id_mask = 0xfffffff0, + .phy_id = MARVELL_PHY_ID_88E1112, + .phy_id_mask = MARVELL_PHY_ID_MASK, .name = "Marvell 88E1112", .features = PHY_GBIT_FEATURES, .flags = PHY_HAS_INTERRUPT, @@ -554,8 +556,8 @@ static struct phy_driver marvell_drivers[] = { .driver = { .owner = THIS_MODULE }, }, { - .phy_id = 0x01410cc0, - .phy_id_mask = 0xfffffff0, + .phy_id = MARVELL_PHY_ID_88E1111, + .phy_id_mask = MARVELL_PHY_ID_MASK, .name = "Marvell 88E1111", .features = PHY_GBIT_FEATURES, .flags = PHY_HAS_INTERRUPT, @@ -567,8 +569,8 @@ static struct phy_driver marvell_drivers[] = { .driver = { .owner = THIS_MODULE }, }, { - .phy_id = 0x01410e10, - .phy_id_mask = 0xfffffff0, + .phy_id = MARVELL_PHY_ID_88E1118, + .phy_id_mask = MARVELL_PHY_ID_MASK, .name = "Marvell 88E1118", .features = PHY_GBIT_FEATURES, .flags = PHY_HAS_INTERRUPT, @@ -580,8 +582,8 @@ static struct phy_driver marvell_drivers[] = { .driver = {.owner = THIS_MODULE,}, }, { - .phy_id = 0x01410cb0, - .phy_id_mask = 0xfffffff0, + .phy_id = MARVELL_PHY_ID_88E1121R, + .phy_id_mask = MARVELL_PHY_ID_MASK, .name = "Marvell 88E1121R", .features = PHY_GBIT_FEATURES, .flags = PHY_HAS_INTERRUPT, @@ -593,8 +595,8 @@ static struct phy_driver marvell_drivers[] = { .driver = { .owner = THIS_MODULE }, }, { - .phy_id = 0x01410cd0, - .phy_id_mask = 0xfffffff0, + .phy_id = MARVELL_PHY_ID_88E1145, + .phy_id_mask = MARVELL_PHY_ID_MASK, .name = "Marvell 88E1145", .features = PHY_GBIT_FEATURES, .flags = PHY_HAS_INTERRUPT, @@ -606,8 +608,8 @@ static struct phy_driver marvell_drivers[] = { .driver = { .owner = THIS_MODULE }, }, { - .phy_id = 0x01410e30, - .phy_id_mask = 0xfffffff0, + .phy_id = MARVELL_PHY_ID_88E1240, + .phy_id_mask = MARVELL_PHY_ID_MASK, .name = "Marvell 88E1240", .features = PHY_GBIT_FEATURES, .flags = PHY_HAS_INTERRUPT, diff --git a/drivers/parisc/led.c b/drivers/parisc/led.c index 188bc8496a26..d02be78a4138 100644 --- a/drivers/parisc/led.c +++ b/drivers/parisc/led.c @@ -176,16 +176,18 @@ static ssize_t led_proc_write(struct file *file, const char *buf, size_t count, loff_t *pos) { void *data = PDE(file->f_path.dentry->d_inode)->data; - char *cur, lbuf[count + 1]; + char *cur, lbuf[32]; int d; if (!capable(CAP_SYS_ADMIN)) return -EACCES; - memset(lbuf, 0, count + 1); + if (count >= sizeof(lbuf)) + count = sizeof(lbuf)-1; if (copy_from_user(lbuf, buf, count)) return -EFAULT; + lbuf[count] = 0; cur = lbuf; diff --git a/drivers/rtc/rtc-pl031.c b/drivers/rtc/rtc-pl031.c index 3587d9922f28..71bbefc3544e 100644 --- a/drivers/rtc/rtc-pl031.c +++ b/drivers/rtc/rtc-pl031.c @@ -456,7 +456,7 @@ static struct rtc_class_ops stv2_pl031_ops = { .irq_set_freq = pl031_irq_set_freq, }; -static struct amba_id pl031_ids[] __initdata = { +static struct amba_id pl031_ids[] = { { .id = 0x00041031, .mask = 0x000fffff, diff --git a/drivers/serial/amba-pl010.c b/drivers/serial/amba-pl010.c index b09a638d051f..50441ffe8e38 100644 --- a/drivers/serial/amba-pl010.c +++ b/drivers/serial/amba-pl010.c @@ -782,7 +782,7 @@ static int pl010_resume(struct amba_device *dev) return 0; } -static struct amba_id pl010_ids[] __initdata = { +static struct amba_id pl010_ids[] = { { .id = 0x00041010, .mask = 0x000fffff, diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c index eb4cb480b93e..6ca7a44f29c2 100644 --- a/drivers/serial/amba-pl011.c +++ b/drivers/serial/amba-pl011.c @@ -69,9 +69,12 @@ struct uart_amba_port { struct uart_port port; struct clk *clk; - unsigned int im; /* interrupt mask */ + unsigned int im; /* interrupt mask */ unsigned int old_status; - unsigned int ifls; /* vendor-specific */ + unsigned int ifls; /* vendor-specific */ + unsigned int lcrh_tx; /* vendor-specific */ + unsigned int lcrh_rx; /* vendor-specific */ + bool oversampling; /* vendor-specific */ bool autorts; }; @@ -79,16 +82,25 @@ struct uart_amba_port { struct vendor_data { unsigned int ifls; unsigned int fifosize; + unsigned int lcrh_tx; + unsigned int lcrh_rx; + bool oversampling; }; static struct vendor_data vendor_arm = { .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, .fifosize = 16, + .lcrh_tx = UART011_LCRH, + .lcrh_rx = UART011_LCRH, + .oversampling = false, }; static struct vendor_data vendor_st = { .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, .fifosize = 64, + .lcrh_tx = ST_UART011_LCRH_TX, + .lcrh_rx = ST_UART011_LCRH_RX, + .oversampling = true, }; static void pl011_stop_tx(struct uart_port *port) @@ -327,12 +339,12 @@ static void pl011_break_ctl(struct uart_port *port, int break_state) unsigned int lcr_h; spin_lock_irqsave(&uap->port.lock, flags); - lcr_h = readw(uap->port.membase + UART011_LCRH); + lcr_h = readw(uap->port.membase + uap->lcrh_tx); if (break_state == -1) lcr_h |= UART01x_LCRH_BRK; else lcr_h &= ~UART01x_LCRH_BRK; - writew(lcr_h, uap->port.membase + UART011_LCRH); + writew(lcr_h, uap->port.membase + uap->lcrh_tx); spin_unlock_irqrestore(&uap->port.lock, flags); } @@ -393,7 +405,17 @@ static int pl011_startup(struct uart_port *port) writew(cr, uap->port.membase + UART011_CR); writew(0, uap->port.membase + UART011_FBRD); writew(1, uap->port.membase + UART011_IBRD); - writew(0, uap->port.membase + UART011_LCRH); + writew(0, uap->port.membase + uap->lcrh_rx); + if (uap->lcrh_tx != uap->lcrh_rx) { + int i; + /* + * Wait 10 PCLKs before writing LCRH_TX register, + * to get this delay write read only register 10 times + */ + for (i = 0; i < 10; ++i) + writew(0xff, uap->port.membase + UART011_MIS); + writew(0, uap->port.membase + uap->lcrh_tx); + } writew(0, uap->port.membase + UART01x_DR); while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) barrier(); @@ -422,10 +444,19 @@ static int pl011_startup(struct uart_port *port) return retval; } +static void pl011_shutdown_channel(struct uart_amba_port *uap, + unsigned int lcrh) +{ + unsigned long val; + + val = readw(uap->port.membase + lcrh); + val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); + writew(val, uap->port.membase + lcrh); +} + static void pl011_shutdown(struct uart_port *port) { struct uart_amba_port *uap = (struct uart_amba_port *)port; - unsigned long val; /* * disable all interrupts @@ -450,9 +481,9 @@ static void pl011_shutdown(struct uart_port *port) /* * disable break condition and fifos */ - val = readw(uap->port.membase + UART011_LCRH); - val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); - writew(val, uap->port.membase + UART011_LCRH); + pl011_shutdown_channel(uap, uap->lcrh_rx); + if (uap->lcrh_rx != uap->lcrh_tx) + pl011_shutdown_channel(uap, uap->lcrh_tx); /* * Shut down the clock producer @@ -472,8 +503,13 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios, /* * Ask the core to calculate the divisor for us. */ - baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); - quot = port->uartclk * 4 / baud; + baud = uart_get_baud_rate(port, termios, old, 0, + port->uartclk/(uap->oversampling ? 8 : 16)); + + if (baud > port->uartclk/16) + quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); + else + quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); switch (termios->c_cflag & CSIZE) { case CS5: @@ -552,6 +588,13 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios, uap->autorts = false; } + if (uap->oversampling) { + if (baud > port->uartclk/16) + old_cr |= ST_UART011_CR_OVSFACT; + else + old_cr &= ~ST_UART011_CR_OVSFACT; + } + /* Set baud rate */ writew(quot & 0x3f, port->membase + UART011_FBRD); writew(quot >> 6, port->membase + UART011_IBRD); @@ -561,7 +604,17 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios, * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L * ----------^----------^----------^----------^----- */ - writew(lcr_h, port->membase + UART011_LCRH); + writew(lcr_h, port->membase + uap->lcrh_rx); + if (uap->lcrh_rx != uap->lcrh_tx) { + int i; + /* + * Wait 10 PCLKs before writing LCRH_TX register, + * to get this delay write read only register 10 times + */ + for (i = 0; i < 10; ++i) + writew(0xff, uap->port.membase + UART011_MIS); + writew(lcr_h, port->membase + uap->lcrh_tx); + } writew(old_cr, port->membase + UART011_CR); spin_unlock_irqrestore(&port->lock, flags); @@ -688,7 +741,7 @@ pl011_console_get_options(struct uart_amba_port *uap, int *baud, if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { unsigned int lcr_h, ibrd, fbrd; - lcr_h = readw(uap->port.membase + UART011_LCRH); + lcr_h = readw(uap->port.membase + uap->lcrh_tx); *parity = 'n'; if (lcr_h & UART01x_LCRH_PEN) { @@ -707,6 +760,12 @@ pl011_console_get_options(struct uart_amba_port *uap, int *baud, fbrd = readw(uap->port.membase + UART011_FBRD); *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); + + if (uap->oversampling) { + if (readw(uap->port.membase + UART011_CR) + & ST_UART011_CR_OVSFACT) + *baud *= 2; + } } } @@ -800,6 +859,9 @@ static int pl011_probe(struct amba_device *dev, struct amba_id *id) } uap->ifls = vendor->ifls; + uap->lcrh_rx = vendor->lcrh_rx; + uap->lcrh_tx = vendor->lcrh_tx; + uap->oversampling = vendor->oversampling; uap->port.dev = &dev->dev; uap->port.mapbase = dev->res.start; uap->port.membase = base; @@ -868,7 +930,7 @@ static int pl011_resume(struct amba_device *dev) } #endif -static struct amba_id pl011_ids[] __initdata = { +static struct amba_id pl011_ids[] = { { .id = 0x00041011, .mask = 0x000fffff, diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c index eaa79c8a9b8c..93ead19507b6 100644 --- a/drivers/usb/gadget/at91_udc.c +++ b/drivers/usb/gadget/at91_udc.c @@ -76,11 +76,12 @@ static const char driver_name [] = "at91_udc"; static const char ep0name[] = "ep0"; +#define VBUS_POLL_TIMEOUT msecs_to_jiffies(1000) -#define at91_udp_read(dev, reg) \ - __raw_readl((dev)->udp_baseaddr + (reg)) -#define at91_udp_write(dev, reg, val) \ - __raw_writel((val), (dev)->udp_baseaddr + (reg)) +#define at91_udp_read(udc, reg) \ + __raw_readl((udc)->udp_baseaddr + (reg)) +#define at91_udp_write(udc, reg, val) \ + __raw_writel((val), (udc)->udp_baseaddr + (reg)) /*-------------------------------------------------------------------------*/ @@ -102,8 +103,9 @@ static void proc_ep_show(struct seq_file *s, struct at91_ep *ep) u32 csr; struct at91_request *req; unsigned long flags; + struct at91_udc *udc = ep->udc; - local_irq_save(flags); + spin_lock_irqsave(&udc->lock, flags); csr = __raw_readl(ep->creg); @@ -147,7 +149,7 @@ static void proc_ep_show(struct seq_file *s, struct at91_ep *ep) &req->req, length, req->req.length, req->req.buf); } - local_irq_restore(flags); + spin_unlock_irqrestore(&udc->lock, flags); } static void proc_irq_show(struct seq_file *s, const char *label, u32 mask) @@ -272,7 +274,9 @@ static void done(struct at91_ep *ep, struct at91_request *req, int status) VDBG("%s done %p, status %d\n", ep->ep.name, req, status); ep->stopped = 1; + spin_unlock(&udc->lock); req->req.complete(&ep->ep, &req->req); + spin_lock(&udc->lock); ep->stopped = stopped; /* ep0 is always ready; other endpoints need a non-empty queue */ @@ -472,7 +476,7 @@ static int at91_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc) { struct at91_ep *ep = container_of(_ep, struct at91_ep, ep); - struct at91_udc *dev = ep->udc; + struct at91_udc *udc = ep->udc; u16 maxpacket; u32 tmp; unsigned long flags; @@ -487,7 +491,7 @@ static int at91_ep_enable(struct usb_ep *_ep, return -EINVAL; } - if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { + if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { DBG("bogus device state\n"); return -ESHUTDOWN; } @@ -521,7 +525,7 @@ bogus_max: } ok: - local_irq_save(flags); + spin_lock_irqsave(&udc->lock, flags); /* initialize endpoint to match this descriptor */ ep->is_in = usb_endpoint_dir_in(desc); @@ -540,10 +544,10 @@ ok: * reset/init endpoint fifo. NOTE: leaves fifo_bank alone, * since endpoint resets don't reset hw pingpong state. */ - at91_udp_write(dev, AT91_UDP_RST_EP, ep->int_mask); - at91_udp_write(dev, AT91_UDP_RST_EP, 0); + at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask); + at91_udp_write(udc, AT91_UDP_RST_EP, 0); - local_irq_restore(flags); + spin_unlock_irqrestore(&udc->lock, flags); return 0; } @@ -556,7 +560,7 @@ static int at91_ep_disable (struct usb_ep * _ep) if (ep == &ep->udc->ep[0]) return -EINVAL; - local_irq_save(flags); + spin_lock_irqsave(&udc->lock, flags); nuke(ep, -ESHUTDOWN); @@ -571,7 +575,7 @@ static int at91_ep_disable (struct usb_ep * _ep) __raw_writel(0, ep->creg); } - local_irq_restore(flags); + spin_unlock_irqrestore(&udc->lock, flags); return 0; } @@ -607,7 +611,7 @@ static int at91_ep_queue(struct usb_ep *_ep, { struct at91_request *req; struct at91_ep *ep; - struct at91_udc *dev; + struct at91_udc *udc; int status; unsigned long flags; @@ -625,9 +629,9 @@ static int at91_ep_queue(struct usb_ep *_ep, return -EINVAL; } - dev = ep->udc; + udc = ep->udc; - if (!dev || !dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { + if (!udc || !udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { DBG("invalid device\n"); return -EINVAL; } @@ -635,7 +639,7 @@ static int at91_ep_queue(struct usb_ep *_ep, _req->status = -EINPROGRESS; _req->actual = 0; - local_irq_save(flags); + spin_lock_irqsave(&udc->lock, flags); /* try to kickstart any empty and idle queue */ if (list_empty(&ep->queue) && !ep->stopped) { @@ -653,7 +657,7 @@ static int at91_ep_queue(struct usb_ep *_ep, if (is_ep0) { u32 tmp; - if (!dev->req_pending) { + if (!udc->req_pending) { status = -EINVAL; goto done; } @@ -662,11 +666,11 @@ static int at91_ep_queue(struct usb_ep *_ep, * defer changing CONFG until after the gadget driver * reconfigures the endpoints. */ - if (dev->wait_for_config_ack) { - tmp = at91_udp_read(dev, AT91_UDP_GLB_STAT); + if (udc->wait_for_config_ack) { + tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); tmp ^= AT91_UDP_CONFG; VDBG("toggle config\n"); - at91_udp_write(dev, AT91_UDP_GLB_STAT, tmp); + at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp); } if (req->req.length == 0) { ep0_in_status: @@ -676,7 +680,7 @@ ep0_in_status: tmp &= ~SET_FX; tmp |= CLR_FX | AT91_UDP_TXPKTRDY; __raw_writel(tmp, ep->creg); - dev->req_pending = 0; + udc->req_pending = 0; goto done; } } @@ -695,31 +699,40 @@ ep0_in_status: if (req && !status) { list_add_tail (&req->queue, &ep->queue); - at91_udp_write(dev, AT91_UDP_IER, ep->int_mask); + at91_udp_write(udc, AT91_UDP_IER, ep->int_mask); } done: - local_irq_restore(flags); + spin_unlock_irqrestore(&udc->lock, flags); return (status < 0) ? status : 0; } static int at91_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) { - struct at91_ep *ep; + struct at91_ep *ep; struct at91_request *req; + unsigned long flags; + struct at91_udc *udc; ep = container_of(_ep, struct at91_ep, ep); if (!_ep || ep->ep.name == ep0name) return -EINVAL; + udc = ep->udc; + + spin_lock_irqsave(&udc->lock, flags); + /* make sure it's actually queued on this endpoint */ list_for_each_entry (req, &ep->queue, queue) { if (&req->req == _req) break; } - if (&req->req != _req) + if (&req->req != _req) { + spin_unlock_irqrestore(&udc->lock, flags); return -EINVAL; + } done(ep, req, -ECONNRESET); + spin_unlock_irqrestore(&udc->lock, flags); return 0; } @@ -736,7 +749,7 @@ static int at91_ep_set_halt(struct usb_ep *_ep, int value) return -EINVAL; creg = ep->creg; - local_irq_save(flags); + spin_lock_irqsave(&udc->lock, flags); csr = __raw_readl(creg); @@ -761,7 +774,7 @@ static int at91_ep_set_halt(struct usb_ep *_ep, int value) __raw_writel(csr, creg); } - local_irq_restore(flags); + spin_unlock_irqrestore(&udc->lock, flags); return status; } @@ -795,7 +808,7 @@ static int at91_wakeup(struct usb_gadget *gadget) unsigned long flags; DBG("%s\n", __func__ ); - local_irq_save(flags); + spin_lock_irqsave(&udc->lock, flags); if (!udc->clocked || !udc->suspended) goto done; @@ -809,7 +822,7 @@ static int at91_wakeup(struct usb_gadget *gadget) at91_udp_write(udc, AT91_UDP_GLB_STAT, glbstate); done: - local_irq_restore(flags); + spin_unlock_irqrestore(&udc->lock, flags); return status; } @@ -851,8 +864,11 @@ static void stop_activity(struct at91_udc *udc) ep->stopped = 1; nuke(ep, -ESHUTDOWN); } - if (driver) + if (driver) { + spin_unlock(&udc->lock); driver->disconnect(&udc->gadget); + spin_lock(&udc->lock); + } udc_reinit(udc); } @@ -935,13 +951,13 @@ static int at91_vbus_session(struct usb_gadget *gadget, int is_active) unsigned long flags; // VDBG("vbus %s\n", is_active ? "on" : "off"); - local_irq_save(flags); + spin_lock_irqsave(&udc->lock, flags); udc->vbus = (is_active != 0); if (udc->driver) pullup(udc, is_active); else pullup(udc, 0); - local_irq_restore(flags); + spin_unlock_irqrestore(&udc->lock, flags); return 0; } @@ -950,10 +966,10 @@ static int at91_pullup(struct usb_gadget *gadget, int is_on) struct at91_udc *udc = to_udc(gadget); unsigned long flags; - local_irq_save(flags); + spin_lock_irqsave(&udc->lock, flags); udc->enabled = is_on = !!is_on; pullup(udc, is_on); - local_irq_restore(flags); + spin_unlock_irqrestore(&udc->lock, flags); return 0; } @@ -962,9 +978,9 @@ static int at91_set_selfpowered(struct usb_gadget *gadget, int is_on) struct at91_udc *udc = to_udc(gadget); unsigned long flags; - local_irq_save(flags); + spin_lock_irqsave(&udc->lock, flags); udc->selfpowered = (is_on != 0); - local_irq_restore(flags); + spin_unlock_irqrestore(&udc->lock, flags); return 0; } @@ -1226,8 +1242,11 @@ static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr) #undef w_length /* pass request up to the gadget driver */ - if (udc->driver) + if (udc->driver) { + spin_unlock(&udc->lock); status = udc->driver->setup(&udc->gadget, &pkt.r); + spin_lock(&udc->lock); + } else status = -ENODEV; if (status < 0) { @@ -1378,6 +1397,9 @@ static irqreturn_t at91_udc_irq (int irq, void *_udc) struct at91_udc *udc = _udc; u32 rescans = 5; int disable_clock = 0; + unsigned long flags; + + spin_lock_irqsave(&udc->lock, flags); if (!udc->clocked) { clk_on(udc); @@ -1433,8 +1455,11 @@ static irqreturn_t at91_udc_irq (int irq, void *_udc) * and then into standby to avoid drawing more than * 500uA power (2500uA for some high-power configs). */ - if (udc->driver && udc->driver->suspend) + if (udc->driver && udc->driver->suspend) { + spin_unlock(&udc->lock); udc->driver->suspend(&udc->gadget); + spin_lock(&udc->lock); + } /* host initiated resume */ } else if (status & AT91_UDP_RXRSM) { @@ -1451,8 +1476,11 @@ static irqreturn_t at91_udc_irq (int irq, void *_udc) * would normally want to switch out of slow clock * mode into normal mode. */ - if (udc->driver && udc->driver->resume) + if (udc->driver && udc->driver->resume) { + spin_unlock(&udc->lock); udc->driver->resume(&udc->gadget); + spin_lock(&udc->lock); + } /* endpoint IRQs are cleared by handling them */ } else { @@ -1474,6 +1502,8 @@ static irqreturn_t at91_udc_irq (int irq, void *_udc) if (disable_clock) clk_off(udc); + spin_unlock_irqrestore(&udc->lock, flags); + return IRQ_HANDLED; } @@ -1556,24 +1586,53 @@ static struct at91_udc controller = { /* ep6 and ep7 are also reserved (custom silicon might use them) */ }; +static void at91_vbus_update(struct at91_udc *udc, unsigned value) +{ + value ^= udc->board.vbus_active_low; + if (value != udc->vbus) + at91_vbus_session(&udc->gadget, value); +} + static irqreturn_t at91_vbus_irq(int irq, void *_udc) { struct at91_udc *udc = _udc; - unsigned value; /* vbus needs at least brief debouncing */ udelay(10); - value = gpio_get_value(udc->board.vbus_pin); - if (value != udc->vbus) - at91_vbus_session(&udc->gadget, value); + at91_vbus_update(udc, gpio_get_value(udc->board.vbus_pin)); return IRQ_HANDLED; } +static void at91_vbus_timer_work(struct work_struct *work) +{ + struct at91_udc *udc = container_of(work, struct at91_udc, + vbus_timer_work); + + at91_vbus_update(udc, gpio_get_value_cansleep(udc->board.vbus_pin)); + + if (!timer_pending(&udc->vbus_timer)) + mod_timer(&udc->vbus_timer, jiffies + VBUS_POLL_TIMEOUT); +} + +static void at91_vbus_timer(unsigned long data) +{ + struct at91_udc *udc = (struct at91_udc *)data; + + /* + * If we are polling vbus it is likely that the gpio is on an + * bus such as i2c or spi which may sleep, so schedule some work + * to read the vbus gpio + */ + if (!work_pending(&udc->vbus_timer_work)) + schedule_work(&udc->vbus_timer_work); +} + int usb_gadget_register_driver (struct usb_gadget_driver *driver) { struct at91_udc *udc = &controller; int retval; + unsigned long flags; if (!driver || driver->speed < USB_SPEED_FULL @@ -1605,9 +1664,9 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver) return retval; } - local_irq_disable(); + spin_lock_irqsave(&udc->lock, flags); pullup(udc, 1); - local_irq_enable(); + spin_unlock_irqrestore(&udc->lock, flags); DBG("bound to %s\n", driver->driver.name); return 0; @@ -1617,15 +1676,16 @@ EXPORT_SYMBOL (usb_gadget_register_driver); int usb_gadget_unregister_driver (struct usb_gadget_driver *driver) { struct at91_udc *udc = &controller; + unsigned long flags; if (!driver || driver != udc->driver || !driver->unbind) return -EINVAL; - local_irq_disable(); + spin_lock_irqsave(&udc->lock, flags); udc->enabled = 0; at91_udp_write(udc, AT91_UDP_IDR, ~0); pullup(udc, 0); - local_irq_enable(); + spin_unlock_irqrestore(&udc->lock, flags); driver->unbind(&udc->gadget); udc->gadget.dev.driver = NULL; @@ -1641,8 +1701,13 @@ EXPORT_SYMBOL (usb_gadget_unregister_driver); static void at91udc_shutdown(struct platform_device *dev) { + struct at91_udc *udc = platform_get_drvdata(dev); + unsigned long flags; + /* force disconnect on reboot */ + spin_lock_irqsave(&udc->lock, flags); pullup(platform_get_drvdata(dev), 0); + spin_unlock_irqrestore(&udc->lock, flags); } static int __init at91udc_probe(struct platform_device *pdev) @@ -1683,6 +1748,7 @@ static int __init at91udc_probe(struct platform_device *pdev) udc->board = *(struct at91_udc_data *) dev->platform_data; udc->pdev = pdev; udc->enabled = 0; + spin_lock_init(&udc->lock); /* rm9200 needs manual D+ pullup; off by default */ if (cpu_is_at91rm9200()) { @@ -1763,13 +1829,23 @@ static int __init at91udc_probe(struct platform_device *pdev) * Get the initial state of VBUS - we cannot expect * a pending interrupt. */ - udc->vbus = gpio_get_value(udc->board.vbus_pin); - if (request_irq(udc->board.vbus_pin, at91_vbus_irq, - IRQF_DISABLED, driver_name, udc)) { - DBG("request vbus irq %d failed\n", - udc->board.vbus_pin); - retval = -EBUSY; - goto fail3; + udc->vbus = gpio_get_value_cansleep(udc->board.vbus_pin) ^ + udc->board.vbus_active_low; + + if (udc->board.vbus_polled) { + INIT_WORK(&udc->vbus_timer_work, at91_vbus_timer_work); + setup_timer(&udc->vbus_timer, at91_vbus_timer, + (unsigned long)udc); + mod_timer(&udc->vbus_timer, + jiffies + VBUS_POLL_TIMEOUT); + } else { + if (request_irq(udc->board.vbus_pin, at91_vbus_irq, + IRQF_DISABLED, driver_name, udc)) { + DBG("request vbus irq %d failed\n", + udc->board.vbus_pin); + retval = -EBUSY; + goto fail3; + } } } else { DBG("no VBUS detection, assuming always-on\n"); @@ -1804,13 +1880,16 @@ static int __exit at91udc_remove(struct platform_device *pdev) { struct at91_udc *udc = platform_get_drvdata(pdev); struct resource *res; + unsigned long flags; DBG("remove\n"); if (udc->driver) return -EBUSY; + spin_lock_irqsave(&udc->lock, flags); pullup(udc, 0); + spin_unlock_irqrestore(&udc->lock, flags); device_init_wakeup(&pdev->dev, 0); remove_debug_file(udc); @@ -1840,6 +1919,7 @@ static int at91udc_suspend(struct platform_device *pdev, pm_message_t mesg) { struct at91_udc *udc = platform_get_drvdata(pdev); int wake = udc->driver && device_may_wakeup(&pdev->dev); + unsigned long flags; /* Unless we can act normally to the host (letting it wake us up * whenever it has work for us) force disconnect. Wakeup requires @@ -1849,13 +1929,15 @@ static int at91udc_suspend(struct platform_device *pdev, pm_message_t mesg) if ((!udc->suspended && udc->addr) || !wake || at91_suspend_entering_slow_clock()) { + spin_lock_irqsave(&udc->lock, flags); pullup(udc, 0); wake = 0; + spin_unlock_irqrestore(&udc->lock, flags); } else enable_irq_wake(udc->udp_irq); udc->active_suspend = wake; - if (udc->board.vbus_pin > 0 && wake) + if (udc->board.vbus_pin > 0 && !udc->board.vbus_polled && wake) enable_irq_wake(udc->board.vbus_pin); return 0; } @@ -1863,15 +1945,20 @@ static int at91udc_suspend(struct platform_device *pdev, pm_message_t mesg) static int at91udc_resume(struct platform_device *pdev) { struct at91_udc *udc = platform_get_drvdata(pdev); + unsigned long flags; - if (udc->board.vbus_pin > 0 && udc->active_suspend) + if (udc->board.vbus_pin > 0 && !udc->board.vbus_polled && + udc->active_suspend) disable_irq_wake(udc->board.vbus_pin); /* maybe reconnect to host; if so, clocks on */ if (udc->active_suspend) disable_irq_wake(udc->udp_irq); - else + else { + spin_lock_irqsave(&udc->lock, flags); pullup(udc, 1); + spin_unlock_irqrestore(&udc->lock, flags); + } return 0; } #else diff --git a/drivers/usb/gadget/at91_udc.h b/drivers/usb/gadget/at91_udc.h index c65d62295890..108ca54f9092 100644 --- a/drivers/usb/gadget/at91_udc.h +++ b/drivers/usb/gadget/at91_udc.h @@ -144,6 +144,9 @@ struct at91_udc { struct proc_dir_entry *pde; void __iomem *udp_baseaddr; int udp_irq; + spinlock_t lock; + struct timer_list vbus_timer; + struct work_struct vbus_timer_work; }; static inline struct at91_udc *to_udc(struct usb_gadget *g) diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c index d0b8bde59e59..eafa6d2c5ed7 100644 --- a/drivers/usb/gadget/fsl_mxc_udc.c +++ b/drivers/usb/gadget/fsl_mxc_udc.c @@ -30,7 +30,7 @@ int fsl_udc_clk_init(struct platform_device *pdev) pdata = pdev->dev.platform_data; - if (!cpu_is_mx35()) { + if (!cpu_is_mx35() && !cpu_is_mx25()) { mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb"); if (IS_ERR(mxc_ahb_clk)) return PTR_ERR(mxc_ahb_clk); diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index bd4027745aa7..a8ad8ac120a2 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -182,7 +182,7 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev) } clk_enable(priv->usbclk); - if (!cpu_is_mx35()) { + if (!cpu_is_mx35() && !cpu_is_mx25()) { priv->ahbclk = clk_get(dev, "usb_ahb"); if (IS_ERR(priv->ahbclk)) { ret = PTR_ERR(priv->ahbclk); diff --git a/drivers/video/cyber2000fb.c b/drivers/video/cyber2000fb.c index 3a561df2e8a2..0c1afd13ddd3 100644 --- a/drivers/video/cyber2000fb.c +++ b/drivers/video/cyber2000fb.c @@ -388,6 +388,7 @@ cyber2000fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, pseudo_val |= convert_bitfield(red, &var->red); pseudo_val |= convert_bitfield(green, &var->green); pseudo_val |= convert_bitfield(blue, &var->blue); + ret = 0; break; } @@ -436,6 +437,8 @@ static void cyber2000fb_write_ramdac_ctrl(struct cfb_info *cfb) cyber2000fb_writeb(i | 4, 0x3cf, cfb); cyber2000fb_writeb(val, 0x3c6, cfb); cyber2000fb_writeb(i, 0x3cf, cfb); + /* prevent card lock-up observed on x86 with CyberPro 2000 */ + cyber2000fb_readb(0x3cf, cfb); } static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw) diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c index b4b6deceed15..43f0639b1c10 100644 --- a/drivers/video/imxfb.c +++ b/drivers/video/imxfb.c @@ -175,6 +175,7 @@ struct imxfb_info { struct imx_fb_videomode *mode; int num_modes; + struct backlight_device *bl; void (*lcd_power)(int); void (*backlight_power)(int); @@ -449,6 +450,73 @@ static int imxfb_set_par(struct fb_info *info) return 0; } + + +static int imxfb_bl_get_brightness(struct backlight_device *bl) +{ + struct imxfb_info *fbi = bl_get_data(bl); + + return readl(fbi->regs + LCDC_PWMR) & 0xFF; +} + +static int imxfb_bl_update_status(struct backlight_device *bl) +{ + struct imxfb_info *fbi = bl_get_data(bl); + int brightness = bl->props.brightness; + + if (bl->props.power != FB_BLANK_UNBLANK) + brightness = 0; + if (bl->props.fb_blank != FB_BLANK_UNBLANK) + brightness = 0; + + fbi->pwmr = (fbi->pwmr & ~0xFF) | brightness; + + if (bl->props.fb_blank != FB_BLANK_UNBLANK) + clk_enable(fbi->clk); + writel(fbi->pwmr, fbi->regs + LCDC_PWMR); + if (bl->props.fb_blank != FB_BLANK_UNBLANK) + clk_disable(fbi->clk); + + return 0; +} + +static const struct backlight_ops imxfb_lcdc_bl_ops = { + .update_status = imxfb_bl_update_status, + .get_brightness = imxfb_bl_get_brightness, +}; + +static void imxfb_init_backlight(struct imxfb_info *fbi) +{ + struct backlight_properties props; + struct backlight_device *bl; + + if (fbi->bl) + return; + + memset(&props, 0, sizeof(struct backlight_properties)); + props.max_brightness = 0xff; + writel(fbi->pwmr, fbi->regs + LCDC_PWMR); + + bl = backlight_device_register("imxfb-bl", &fbi->pdev->dev, fbi, + &imxfb_lcdc_bl_ops, &props); + if (IS_ERR(bl)) { + dev_err(&fbi->pdev->dev, "error %ld on backlight register\n", + PTR_ERR(bl)); + return; + } + + fbi->bl = bl; + bl->props.power = FB_BLANK_UNBLANK; + bl->props.fb_blank = FB_BLANK_UNBLANK; + bl->props.brightness = imxfb_bl_get_brightness(bl); +} + +static void imxfb_exit_backlight(struct imxfb_info *fbi) +{ + if (fbi->bl) + backlight_device_unregister(fbi->bl); +} + static void imxfb_enable_controller(struct imxfb_info *fbi) { pr_debug("Enabling LCD controller\n"); @@ -579,7 +647,6 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf fbi->regs + LCDC_SIZE); writel(fbi->pcr, fbi->regs + LCDC_PCR); - writel(fbi->pwmr, fbi->regs + LCDC_PWMR); writel(fbi->lscr1, fbi->regs + LCDC_LSCR1); writel(fbi->dmacr, fbi->regs + LCDC_DMACR); @@ -779,6 +846,8 @@ static int __init imxfb_probe(struct platform_device *pdev) } imxfb_enable_controller(fbi); + fbi->pdev = pdev; + imxfb_init_backlight(fbi); return 0; @@ -816,6 +885,7 @@ static int __devexit imxfb_remove(struct platform_device *pdev) imxfb_disable_controller(fbi); + imxfb_exit_backlight(fbi); unregister_framebuffer(info); pdata = pdev->dev.platform_data; diff --git a/drivers/video/omap2/vram.c b/drivers/video/omap2/vram.c index 3b1237ad85ed..f6fdc2085f3e 100644 --- a/drivers/video/omap2/vram.c +++ b/drivers/video/omap2/vram.c @@ -25,7 +25,7 @@ #include <linux/list.h> #include <linux/slab.h> #include <linux/seq_file.h> -#include <linux/bootmem.h> +#include <linux/memblock.h> #include <linux/completion.h> #include <linux/debugfs.h> #include <linux/jiffies.h> @@ -525,10 +525,8 @@ early_param("vram", omap_vram_early_vram); * Called from map_io. We need to call to this early enough so that we * can reserve the fixed SDRAM regions before VM could get hold of them. */ -void __init omap_vram_reserve_sdram(void) +void __init omap_vram_reserve_sdram_memblock(void) { - struct bootmem_data *bdata; - unsigned long sdram_start, sdram_size; u32 paddr; u32 size = 0; @@ -555,29 +553,28 @@ void __init omap_vram_reserve_sdram(void) size = PAGE_ALIGN(size); - bdata = NODE_DATA(0)->bdata; - sdram_start = bdata->node_min_pfn << PAGE_SHIFT; - sdram_size = (bdata->node_low_pfn << PAGE_SHIFT) - sdram_start; - if (paddr) { - if ((paddr & ~PAGE_MASK) || paddr < sdram_start || - paddr + size > sdram_start + sdram_size) { + struct memblock_property res; + + res.base = paddr; + res.size = size; + if ((paddr & ~PAGE_MASK) || memblock_find(&res) || + res.base != paddr || res.size != size) { pr_err("Illegal SDRAM region for VRAM\n"); return; } - if (reserve_bootmem(paddr, size, BOOTMEM_EXCLUSIVE) < 0) { - pr_err("FB: failed to reserve VRAM\n"); + if (memblock_is_region_reserved(paddr, size)) { + pr_err("FB: failed to reserve VRAM - busy\n"); return; } - } else { - if (size > sdram_size) { - pr_err("Illegal SDRAM size for VRAM\n"); + + if (memblock_reserve(paddr, size) < 0) { + pr_err("FB: failed to reserve VRAM - no memory\n"); return; } - - paddr = virt_to_phys(alloc_bootmem_pages(size)); - BUG_ON(paddr & ~PAGE_MASK); + } else { + paddr = memblock_alloc_base(size, PAGE_SIZE, MEMBLOCK_REAL_LIMIT); } omap_vram_add_region(paddr, size); diff --git a/fs/9p/Makefile b/fs/9p/Makefile index 1a940ec7af61..91fba025fcbe 100644 --- a/fs/9p/Makefile +++ b/fs/9p/Makefile @@ -8,6 +8,8 @@ obj-$(CONFIG_9P_FS) := 9p.o vfs_dir.o \ vfs_dentry.o \ v9fs.o \ - fid.o + fid.o \ + xattr.o \ + xattr_user.o 9p-$(CONFIG_9P_FSCACHE) += cache.o diff --git a/fs/9p/fid.c b/fs/9p/fid.c index 7317b39b2815..358563689064 100644 --- a/fs/9p/fid.c +++ b/fs/9p/fid.c @@ -97,6 +97,34 @@ static struct p9_fid *v9fs_fid_find(struct dentry *dentry, u32 uid, int any) return ret; } +/* + * We need to hold v9ses->rename_sem as long as we hold references + * to returned path array. Array element contain pointers to + * dentry names. + */ +static int build_path_from_dentry(struct v9fs_session_info *v9ses, + struct dentry *dentry, char ***names) +{ + int n = 0, i; + char **wnames; + struct dentry *ds; + + for (ds = dentry; !IS_ROOT(ds); ds = ds->d_parent) + n++; + + wnames = kmalloc(sizeof(char *) * n, GFP_KERNEL); + if (!wnames) + goto err_out; + + for (ds = dentry, i = (n-1); i >= 0; i--, ds = ds->d_parent) + wnames[i] = (char *)ds->d_name.name; + + *names = wnames; + return n; +err_out: + return -ENOMEM; +} + /** * v9fs_fid_lookup - lookup for a fid, try to walk if not found * @dentry: dentry to look for fid in @@ -112,7 +140,7 @@ struct p9_fid *v9fs_fid_lookup(struct dentry *dentry) int i, n, l, clone, any, access; u32 uid; struct p9_fid *fid, *old_fid = NULL; - struct dentry *d, *ds; + struct dentry *ds; struct v9fs_session_info *v9ses; char **wnames, *uname; @@ -139,49 +167,62 @@ struct p9_fid *v9fs_fid_lookup(struct dentry *dentry) fid = v9fs_fid_find(dentry, uid, any); if (fid) return fid; - + /* + * we don't have a matching fid. To do a TWALK we need + * parent fid. We need to prevent rename when we want to + * look at the parent. + */ + down_read(&v9ses->rename_sem); ds = dentry->d_parent; fid = v9fs_fid_find(ds, uid, any); - if (!fid) { /* walk from the root */ - n = 0; - for (ds = dentry; !IS_ROOT(ds); ds = ds->d_parent) - n++; + if (fid) { + /* Found the parent fid do a lookup with that */ + fid = p9_client_walk(fid, 1, (char **)&dentry->d_name.name, 1); + goto fid_out; + } + up_read(&v9ses->rename_sem); - fid = v9fs_fid_find(ds, uid, any); - if (!fid) { /* the user is not attached to the fs yet */ - if (access == V9FS_ACCESS_SINGLE) - return ERR_PTR(-EPERM); + /* start from the root and try to do a lookup */ + fid = v9fs_fid_find(dentry->d_sb->s_root, uid, any); + if (!fid) { + /* the user is not attached to the fs yet */ + if (access == V9FS_ACCESS_SINGLE) + return ERR_PTR(-EPERM); - if (v9fs_proto_dotu(v9ses)) + if (v9fs_proto_dotu(v9ses) || v9fs_proto_dotl(v9ses)) uname = NULL; - else - uname = v9ses->uname; + else + uname = v9ses->uname; - fid = p9_client_attach(v9ses->clnt, NULL, uname, uid, - v9ses->aname); - - if (IS_ERR(fid)) - return fid; - - v9fs_fid_add(ds, fid); - } - } else /* walk from the parent */ - n = 1; + fid = p9_client_attach(v9ses->clnt, NULL, uname, uid, + v9ses->aname); + if (IS_ERR(fid)) + return fid; - if (ds == dentry) + v9fs_fid_add(dentry->d_sb->s_root, fid); + } + /* If we are root ourself just return that */ + if (dentry->d_sb->s_root == dentry) return fid; - - wnames = kmalloc(sizeof(char *) * n, GFP_KERNEL); - if (!wnames) - return ERR_PTR(-ENOMEM); - - for (d = dentry, i = (n-1); i >= 0; i--, d = d->d_parent) - wnames[i] = (char *) d->d_name.name; - + /* + * Do a multipath walk with attached root. + * When walking parent we need to make sure we + * don't have a parallel rename happening + */ + down_read(&v9ses->rename_sem); + n = build_path_from_dentry(v9ses, dentry, &wnames); + if (n < 0) { + fid = ERR_PTR(n); + goto err_out; + } clone = 1; i = 0; while (i < n) { l = min(n - i, P9_MAXWELEM); + /* + * We need to hold rename lock when doing a multipath + * walk to ensure none of the patch component change + */ fid = p9_client_walk(fid, l, &wnames[i], clone); if (IS_ERR(fid)) { if (old_fid) { @@ -193,15 +234,17 @@ struct p9_fid *v9fs_fid_lookup(struct dentry *dentry) p9_client_clunk(old_fid); } kfree(wnames); - return fid; + goto err_out; } old_fid = fid; i += l; clone = 0; } - kfree(wnames); +fid_out: v9fs_fid_add(dentry, fid); +err_out: + up_read(&v9ses->rename_sem); return fid; } diff --git a/fs/9p/v9fs.c b/fs/9p/v9fs.c index f8b86e92cd66..38dc0e067599 100644 --- a/fs/9p/v9fs.c +++ b/fs/9p/v9fs.c @@ -237,6 +237,7 @@ struct p9_fid *v9fs_session_init(struct v9fs_session_info *v9ses, __putname(v9ses->uname); return ERR_PTR(-ENOMEM); } + init_rwsem(&v9ses->rename_sem); rc = bdi_setup_and_register(&v9ses->bdi, "9p", BDI_CAP_MAP_COPY); if (rc) { @@ -278,7 +279,7 @@ struct p9_fid *v9fs_session_init(struct v9fs_session_info *v9ses, v9ses->maxdata = v9ses->clnt->msize - P9_IOHDRSZ; /* for legacy mode, fall back to V9FS_ACCESS_ANY */ - if (!v9fs_proto_dotu(v9ses) && + if (!(v9fs_proto_dotu(v9ses) || v9fs_proto_dotl(v9ses)) && ((v9ses->flags&V9FS_ACCESS_MASK) == V9FS_ACCESS_USER)) { v9ses->flags &= ~V9FS_ACCESS_MASK; diff --git a/fs/9p/v9fs.h b/fs/9p/v9fs.h index bec4d0bcb458..4c963c9fc41f 100644 --- a/fs/9p/v9fs.h +++ b/fs/9p/v9fs.h @@ -104,6 +104,7 @@ struct v9fs_session_info { struct p9_client *clnt; /* 9p client */ struct list_head slist; /* list of sessions registered with v9fs */ struct backing_dev_info bdi; + struct rw_semaphore rename_sem; }; struct p9_fid *v9fs_session_init(struct v9fs_session_info *, const char *, diff --git a/fs/9p/v9fs_vfs.h b/fs/9p/v9fs_vfs.h index 32ef4009d030..f47c6bbb01b3 100644 --- a/fs/9p/v9fs_vfs.h +++ b/fs/9p/v9fs_vfs.h @@ -55,6 +55,7 @@ struct inode *v9fs_get_inode(struct super_block *sb, int mode); void v9fs_clear_inode(struct inode *inode); ino_t v9fs_qid2ino(struct p9_qid *qid); void v9fs_stat2inode(struct p9_wstat *, struct inode *, struct super_block *); +void v9fs_stat2inode_dotl(struct p9_stat_dotl *, struct inode *); int v9fs_dir_release(struct inode *inode, struct file *filp); int v9fs_file_open(struct inode *inode, struct file *file); void v9fs_inode2stat(struct inode *inode, struct p9_wstat *stat); diff --git a/fs/9p/vfs_dir.c b/fs/9p/vfs_dir.c index 36d961f342af..16c8a2a98c1b 100644 --- a/fs/9p/vfs_dir.c +++ b/fs/9p/vfs_dir.c @@ -87,29 +87,19 @@ static void p9stat_init(struct p9_wstat *stbuf) } /** - * v9fs_dir_readdir - read a directory + * v9fs_alloc_rdir_buf - Allocate buffer used for read and readdir * @filp: opened file structure - * @dirent: directory structure ??? - * @filldir: function to populate directory structure ??? + * @buflen: Length in bytes of buffer to allocate * */ -static int v9fs_dir_readdir(struct file *filp, void *dirent, filldir_t filldir) +static int v9fs_alloc_rdir_buf(struct file *filp, int buflen) { - int over; - struct p9_wstat st; - int err = 0; - struct p9_fid *fid; - int buflen; - int reclen = 0; struct p9_rdir *rdir; + struct p9_fid *fid; + int err = 0; - P9_DPRINTK(P9_DEBUG_VFS, "name %s\n", filp->f_path.dentry->d_name.name); fid = filp->private_data; - - buflen = fid->clnt->msize - P9_IOHDRSZ; - - /* allocate rdir on demand */ if (!fid->rdir) { rdir = kmalloc(sizeof(struct p9_rdir) + buflen, GFP_KERNEL); @@ -128,6 +118,36 @@ static int v9fs_dir_readdir(struct file *filp, void *dirent, filldir_t filldir) spin_unlock(&filp->f_dentry->d_lock); kfree(rdir); } +exit: + return err; +} + +/** + * v9fs_dir_readdir - read a directory + * @filp: opened file structure + * @dirent: directory structure ??? + * @filldir: function to populate directory structure ??? + * + */ + +static int v9fs_dir_readdir(struct file *filp, void *dirent, filldir_t filldir) +{ + int over; + struct p9_wstat st; + int err = 0; + struct p9_fid *fid; + int buflen; + int reclen = 0; + struct p9_rdir *rdir; + + P9_DPRINTK(P9_DEBUG_VFS, "name %s\n", filp->f_path.dentry->d_name.name); + fid = filp->private_data; + + buflen = fid->clnt->msize - P9_IOHDRSZ; + + err = v9fs_alloc_rdir_buf(filp, buflen); + if (err) + goto exit; rdir = (struct p9_rdir *) fid->rdir; err = mutex_lock_interruptible(&rdir->mutex); @@ -176,6 +196,88 @@ exit: return err; } +/** + * v9fs_dir_readdir_dotl - read a directory + * @filp: opened file structure + * @dirent: buffer to fill dirent structures + * @filldir: function to populate dirent structures + * + */ +static int v9fs_dir_readdir_dotl(struct file *filp, void *dirent, + filldir_t filldir) +{ + int over; + int err = 0; + struct p9_fid *fid; + int buflen; + struct p9_rdir *rdir; + struct p9_dirent curdirent; + u64 oldoffset = 0; + + P9_DPRINTK(P9_DEBUG_VFS, "name %s\n", filp->f_path.dentry->d_name.name); + fid = filp->private_data; + + buflen = fid->clnt->msize - P9_READDIRHDRSZ; + + err = v9fs_alloc_rdir_buf(filp, buflen); + if (err) + goto exit; + rdir = (struct p9_rdir *) fid->rdir; + + err = mutex_lock_interruptible(&rdir->mutex); + if (err) + return err; + + while (err == 0) { + if (rdir->tail == rdir->head) { + err = p9_client_readdir(fid, rdir->buf, buflen, + filp->f_pos); + if (err <= 0) + goto unlock_and_exit; + + rdir->head = 0; + rdir->tail = err; + } + + while (rdir->head < rdir->tail) { + + err = p9dirent_read(rdir->buf + rdir->head, + buflen - rdir->head, &curdirent, + fid->clnt->proto_version); + if (err < 0) { + P9_DPRINTK(P9_DEBUG_VFS, "returned %d\n", err); + err = -EIO; + goto unlock_and_exit; + } + + /* d_off in dirent structure tracks the offset into + * the next dirent in the dir. However, filldir() + * expects offset into the current dirent. Hence + * while calling filldir send the offset from the + * previous dirent structure. + */ + over = filldir(dirent, curdirent.d_name, + strlen(curdirent.d_name), + oldoffset, v9fs_qid2ino(&curdirent.qid), + curdirent.d_type); + oldoffset = curdirent.d_off; + + if (over) { + err = 0; + goto unlock_and_exit; + } + + filp->f_pos = curdirent.d_off; + rdir->head += err; + } + } + +unlock_and_exit: + mutex_unlock(&rdir->mutex); +exit: + return err; +} + /** * v9fs_dir_release - close a directory @@ -207,7 +309,7 @@ const struct file_operations v9fs_dir_operations = { const struct file_operations v9fs_dir_operations_dotl = { .read = generic_read_dir, .llseek = generic_file_llseek, - .readdir = v9fs_dir_readdir, + .readdir = v9fs_dir_readdir_dotl, .open = v9fs_file_open, .release = v9fs_dir_release, }; diff --git a/fs/9p/vfs_file.c b/fs/9p/vfs_file.c index 2bedc6c94fc2..e97c92bd6f16 100644 --- a/fs/9p/vfs_file.c +++ b/fs/9p/vfs_file.c @@ -59,9 +59,13 @@ int v9fs_file_open(struct inode *inode, struct file *file) struct p9_fid *fid; int omode; - P9_DPRINTK(P9_DEBUG_VFS, "inode: %p file: %p \n", inode, file); + P9_DPRINTK(P9_DEBUG_VFS, "inode: %p file: %p\n", inode, file); v9ses = v9fs_inode2v9ses(inode); - omode = v9fs_uflags2omode(file->f_flags, v9fs_proto_dotu(v9ses)); + if (v9fs_proto_dotl(v9ses)) + omode = file->f_flags; + else + omode = v9fs_uflags2omode(file->f_flags, + v9fs_proto_dotu(v9ses)); fid = file->private_data; if (!fid) { fid = v9fs_fid_clone(file->f_path.dentry); @@ -73,11 +77,12 @@ int v9fs_file_open(struct inode *inode, struct file *file) p9_client_clunk(fid); return err; } - if (omode & P9_OTRUNC) { + if (file->f_flags & O_TRUNC) { i_size_write(inode, 0); inode->i_blocks = 0; } - if ((file->f_flags & O_APPEND) && (!v9fs_proto_dotu(v9ses))) + if ((file->f_flags & O_APPEND) && + (!v9fs_proto_dotu(v9ses) && !v9fs_proto_dotl(v9ses))) generic_file_llseek(file, 0, SEEK_END); } @@ -139,7 +144,7 @@ ssize_t v9fs_file_readn(struct file *filp, char *data, char __user *udata, u32 count, u64 offset) { - int n, total; + int n, total, size; struct p9_fid *fid = filp->private_data; P9_DPRINTK(P9_DEBUG_VFS, "fid %d offset %llu count %d\n", fid->fid, @@ -147,6 +152,7 @@ v9fs_file_readn(struct file *filp, char *data, char __user *udata, u32 count, n = 0; total = 0; + size = fid->iounit ? fid->iounit : fid->clnt->msize - P9_IOHDRSZ; do { n = p9_client_read(fid, data, udata, offset, count); if (n <= 0) @@ -160,7 +166,7 @@ v9fs_file_readn(struct file *filp, char *data, char __user *udata, u32 count, offset += n; count -= n; total += n; - } while (count > 0 && n == (fid->clnt->msize - P9_IOHDRSZ)); + } while (count > 0 && n == size); if (n < 0) total = n; @@ -183,11 +189,13 @@ v9fs_file_read(struct file *filp, char __user *udata, size_t count, { int ret; struct p9_fid *fid; + size_t size; P9_DPRINTK(P9_DEBUG_VFS, "count %zu offset %lld\n", count, *offset); fid = filp->private_data; - if (count > (fid->clnt->msize - P9_IOHDRSZ)) + size = fid->iounit ? fid->iounit : fid->clnt->msize - P9_IOHDRSZ; + if (count > size) ret = v9fs_file_readn(filp, NULL, udata, count, *offset); else ret = p9_client_read(fid, NULL, udata, *offset, count); @@ -224,9 +232,7 @@ v9fs_file_write(struct file *filp, const char __user * data, fid = filp->private_data; clnt = fid->clnt; - rsize = fid->iounit; - if (!rsize || rsize > clnt->msize-P9_IOHDRSZ) - rsize = clnt->msize - P9_IOHDRSZ; + rsize = fid->iounit ? fid->iounit : clnt->msize - P9_IOHDRSZ; do { if (count < rsize) diff --git a/fs/9p/vfs_inode.c b/fs/9p/vfs_inode.c index 4331b3b5ee1c..6e94f3247cec 100644 --- a/fs/9p/vfs_inode.c +++ b/fs/9p/vfs_inode.c @@ -35,6 +35,7 @@ #include <linux/idr.h> #include <linux/sched.h> #include <linux/slab.h> +#include <linux/xattr.h> #include <net/9p/9p.h> #include <net/9p/client.h> @@ -42,6 +43,7 @@ #include "v9fs_vfs.h" #include "fid.h" #include "cache.h" +#include "xattr.h" static const struct inode_operations v9fs_dir_inode_operations; static const struct inode_operations v9fs_dir_inode_operations_dotu; @@ -236,6 +238,41 @@ void v9fs_destroy_inode(struct inode *inode) #endif /** + * v9fs_get_fsgid_for_create - Helper function to get the gid for creating a + * new file system object. This checks the S_ISGID to determine the owning + * group of the new file system object. + */ + +static gid_t v9fs_get_fsgid_for_create(struct inode *dir_inode) +{ + BUG_ON(dir_inode == NULL); + + if (dir_inode->i_mode & S_ISGID) { + /* set_gid bit is set.*/ + return dir_inode->i_gid; + } + return current_fsgid(); +} + +/** + * v9fs_dentry_from_dir_inode - helper function to get the dentry from + * dir inode. + * + */ + +static struct dentry *v9fs_dentry_from_dir_inode(struct inode *inode) +{ + struct dentry *dentry; + + spin_lock(&dcache_lock); + /* Directory should have only one entry. */ + BUG_ON(S_ISDIR(inode->i_mode) && !list_is_singular(&inode->i_dentry)); + dentry = list_entry(inode->i_dentry.next, struct dentry, d_alias); + spin_unlock(&dcache_lock); + return dentry; +} + +/** * v9fs_get_inode - helper function to setup an inode * @sb: superblock * @mode: mode to setup inode with @@ -267,7 +304,13 @@ struct inode *v9fs_get_inode(struct super_block *sb, int mode) case S_IFBLK: case S_IFCHR: case S_IFSOCK: - if (!v9fs_proto_dotu(v9ses)) { + if (v9fs_proto_dotl(v9ses)) { + inode->i_op = &v9fs_file_inode_operations_dotl; + inode->i_fop = &v9fs_file_operations_dotl; + } else if (v9fs_proto_dotu(v9ses)) { + inode->i_op = &v9fs_file_inode_operations; + inode->i_fop = &v9fs_file_operations; + } else { P9_DPRINTK(P9_DEBUG_ERROR, "special files without extended mode\n"); err = -EINVAL; @@ -396,23 +439,14 @@ void v9fs_clear_inode(struct inode *inode) #endif } -/** - * v9fs_inode_from_fid - populate an inode by issuing a attribute request - * @v9ses: session information - * @fid: fid to issue attribute request for - * @sb: superblock on which to create inode - * - */ - static struct inode * -v9fs_inode_from_fid(struct v9fs_session_info *v9ses, struct p9_fid *fid, +v9fs_inode(struct v9fs_session_info *v9ses, struct p9_fid *fid, struct super_block *sb) { int err, umode; - struct inode *ret; + struct inode *ret = NULL; struct p9_wstat *st; - ret = NULL; st = p9_client_stat(fid); if (IS_ERR(st)) return ERR_CAST(st); @@ -433,15 +467,62 @@ v9fs_inode_from_fid(struct v9fs_session_info *v9ses, struct p9_fid *fid, #endif p9stat_free(st); kfree(st); - return ret; - error: p9stat_free(st); kfree(st); return ERR_PTR(err); } +static struct inode * +v9fs_inode_dotl(struct v9fs_session_info *v9ses, struct p9_fid *fid, + struct super_block *sb) +{ + struct inode *ret = NULL; + int err; + struct p9_stat_dotl *st; + + st = p9_client_getattr_dotl(fid, P9_STATS_BASIC); + if (IS_ERR(st)) + return ERR_CAST(st); + + ret = v9fs_get_inode(sb, st->st_mode); + if (IS_ERR(ret)) { + err = PTR_ERR(ret); + goto error; + } + + v9fs_stat2inode_dotl(st, ret); + ret->i_ino = v9fs_qid2ino(&st->qid); +#ifdef CONFIG_9P_FSCACHE + v9fs_vcookie_set_qid(ret, &st->qid); + v9fs_cache_inode_get_cookie(ret); +#endif + kfree(st); + return ret; +error: + kfree(st); + return ERR_PTR(err); +} + +/** + * v9fs_inode_from_fid - Helper routine to populate an inode by + * issuing a attribute request + * @v9ses: session information + * @fid: fid to issue attribute request for + * @sb: superblock on which to create inode + * + */ +static inline struct inode * +v9fs_inode_from_fid(struct v9fs_session_info *v9ses, struct p9_fid *fid, + struct super_block *sb) +{ + if (v9fs_proto_dotl(v9ses)) + return v9fs_inode_dotl(v9ses, fid, sb); + else + return v9fs_inode(v9ses, fid, sb); +} + /** * v9fs_remove - helper function to remove files and directories * @dir: directory inode that is being deleted @@ -563,6 +644,118 @@ error: } /** + * v9fs_vfs_create_dotl - VFS hook to create files for 9P2000.L protocol. + * @dir: directory inode that is being created + * @dentry: dentry that is being deleted + * @mode: create permissions + * @nd: path information + * + */ + +static int +v9fs_vfs_create_dotl(struct inode *dir, struct dentry *dentry, int mode, + struct nameidata *nd) +{ + int err = 0; + char *name = NULL; + gid_t gid; + int flags; + struct v9fs_session_info *v9ses; + struct p9_fid *fid = NULL; + struct p9_fid *dfid, *ofid; + struct file *filp; + struct p9_qid qid; + struct inode *inode; + + v9ses = v9fs_inode2v9ses(dir); + if (nd && nd->flags & LOOKUP_OPEN) + flags = nd->intent.open.flags - 1; + else + flags = O_RDWR; + + name = (char *) dentry->d_name.name; + P9_DPRINTK(P9_DEBUG_VFS, "v9fs_vfs_create_dotl: name:%s flags:0x%x " + "mode:0x%x\n", name, flags, mode); + + dfid = v9fs_fid_lookup(dentry->d_parent); + if (IS_ERR(dfid)) { + err = PTR_ERR(dfid); + P9_DPRINTK(P9_DEBUG_VFS, "fid lookup failed %d\n", err); + return err; + } + + /* clone a fid to use for creation */ + ofid = p9_client_walk(dfid, 0, NULL, 1); + if (IS_ERR(ofid)) { + err = PTR_ERR(ofid); + P9_DPRINTK(P9_DEBUG_VFS, "p9_client_walk failed %d\n", err); + return err; + } + + gid = v9fs_get_fsgid_for_create(dir); + err = p9_client_create_dotl(ofid, name, flags, mode, gid, &qid); + if (err < 0) { + P9_DPRINTK(P9_DEBUG_VFS, + "p9_client_open_dotl failed in creat %d\n", + err); + goto error; + } + + /* No need to populate the inode if we are not opening the file AND + * not in cached mode. + */ + if (!v9ses->cache && !(nd && nd->flags & LOOKUP_OPEN)) { + /* Not in cached mode. No need to populate inode with stat */ + dentry->d_op = &v9fs_dentry_operations; + p9_client_clunk(ofid); + d_instantiate(dentry, NULL); + return 0; + } + + /* Now walk from the parent so we can get an unopened fid. */ + fid = p9_client_walk(dfid, 1, &name, 1); + if (IS_ERR(fid)) { + err = PTR_ERR(fid); + P9_DPRINTK(P9_DEBUG_VFS, "p9_client_walk failed %d\n", err); + fid = NULL; + goto error; + } + + /* instantiate inode and assign the unopened fid to dentry */ + inode = v9fs_inode_from_fid(v9ses, fid, dir->i_sb); + if (IS_ERR(inode)) { + err = PTR_ERR(inode); + P9_DPRINTK(P9_DEBUG_VFS, "inode creation failed %d\n", err); + goto error; + } + dentry->d_op = &v9fs_cached_dentry_operations; + d_instantiate(dentry, inode); + err = v9fs_fid_add(dentry, fid); + if (err < 0) + goto error; + + /* if we are opening a file, assign the open fid to the file */ + if (nd && nd->flags & LOOKUP_OPEN) { + filp = lookup_instantiate_filp(nd, dentry, v9fs_open_created); + if (IS_ERR(filp)) { + p9_client_clunk(ofid); + return PTR_ERR(filp); + } + filp->private_data = ofid; + } else + p9_client_clunk(ofid); + + return 0; + +error: + if (ofid) + p9_client_clunk(ofid); + if (fid) + p9_client_clunk(fid); + return err; +} + +/** * v9fs_vfs_create - VFS hook to create files * @dir: directory inode that is being created * @dentry: dentry that is being deleted @@ -652,6 +845,83 @@ static int v9fs_vfs_mkdir(struct inode *dir, struct dentry *dentry, int mode) return err; } + +/** + * v9fs_vfs_mkdir_dotl - VFS mkdir hook to create a directory + * @dir: inode that is being unlinked + * @dentry: dentry that is being unlinked + * @mode: mode for new directory + * + */ + +static int v9fs_vfs_mkdir_dotl(struct inode *dir, struct dentry *dentry, + int mode) +{ + int err; + struct v9fs_session_info *v9ses; + struct p9_fid *fid = NULL, *dfid = NULL; + gid_t gid; + char *name; + struct inode *inode; + struct p9_qid qid; + struct dentry *dir_dentry; + + P9_DPRINTK(P9_DEBUG_VFS, "name %s\n", dentry->d_name.name); + err = 0; + v9ses = v9fs_inode2v9ses(dir); + + mode |= S_IFDIR; + dir_dentry = v9fs_dentry_from_dir_inode(dir); + dfid = v9fs_fid_lookup(dir_dentry); + if (IS_ERR(dfid)) { + err = PTR_ERR(dfid); + P9_DPRINTK(P9_DEBUG_VFS, "fid lookup failed %d\n", err); + dfid = NULL; + goto error; + } + + gid = v9fs_get_fsgid_for_create(dir); + if (gid < 0) { + P9_DPRINTK(P9_DEBUG_VFS, "v9fs_get_fsgid_for_create failed\n"); + goto error; + } + + name = (char *) dentry->d_name.name; + err = p9_client_mkdir_dotl(dfid, name, mode, gid, &qid); + if (err < 0) + goto error; + + /* instantiate inode and assign the unopened fid to the dentry */ + if (v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) { + fid = p9_client_walk(dfid, 1, &name, 1); + if (IS_ERR(fid)) { + err = PTR_ERR(fid); + P9_DPRINTK(P9_DEBUG_VFS, "p9_client_walk failed %d\n", + err); + fid = NULL; + goto error; + } + + inode = v9fs_inode_from_fid(v9ses, fid, dir->i_sb); + if (IS_ERR(inode)) { + err = PTR_ERR(inode); + P9_DPRINTK(P9_DEBUG_VFS, "inode creation failed %d\n", + err); + goto error; + } + dentry->d_op = &v9fs_cached_dentry_operations; + d_instantiate(dentry, inode); + err = v9fs_fid_add(dentry, fid); + if (err < 0) + goto error; + fid = NULL; + } +error: + if (fid) + p9_client_clunk(fid); + return err; +} + /** * v9fs_vfs_lookup - VFS lookup hook to "walk" to a new inode * @dir: inode that is being walked from @@ -678,6 +948,7 @@ static struct dentry *v9fs_vfs_lookup(struct inode *dir, struct dentry *dentry, sb = dir->i_sb; v9ses = v9fs_inode2v9ses(dir); + /* We can walk d_parent because we hold the dir->i_mutex */ dfid = v9fs_fid_lookup(dentry->d_parent); if (IS_ERR(dfid)) return ERR_CAST(dfid); @@ -785,27 +1056,33 @@ v9fs_vfs_rename(struct inode *old_dir, struct dentry *old_dentry, goto clunk_olddir; } + down_write(&v9ses->rename_sem); if (v9fs_proto_dotl(v9ses)) { retval = p9_client_rename(oldfid, newdirfid, (char *) new_dentry->d_name.name); if (retval != -ENOSYS) goto clunk_newdir; } + if (old_dentry->d_parent != new_dentry->d_parent) { + /* + * 9P .u can only handle file rename in the same directory + */ - /* 9P can only handle file rename in the same directory */ - if (memcmp(&olddirfid->qid, &newdirfid->qid, sizeof(newdirfid->qid))) { P9_DPRINTK(P9_DEBUG_ERROR, "old dir and new dir are different\n"); retval = -EXDEV; goto clunk_newdir; } - v9fs_blank_wstat(&wstat); wstat.muid = v9ses->uname; wstat.name = (char *) new_dentry->d_name.name; retval = p9_client_wstat(oldfid, &wstat); clunk_newdir: + if (!retval) + /* successful rename */ + d_move(old_dentry, new_dentry); + up_write(&v9ses->rename_sem); p9_client_clunk(newdirfid); clunk_olddir: @@ -853,6 +1130,42 @@ v9fs_vfs_getattr(struct vfsmount *mnt, struct dentry *dentry, return 0; } +static int +v9fs_vfs_getattr_dotl(struct vfsmount *mnt, struct dentry *dentry, + struct kstat *stat) +{ + int err; + struct v9fs_session_info *v9ses; + struct p9_fid *fid; + struct p9_stat_dotl *st; + + P9_DPRINTK(P9_DEBUG_VFS, "dentry: %p\n", dentry); + err = -EPERM; + v9ses = v9fs_inode2v9ses(dentry->d_inode); + if (v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) + return simple_getattr(mnt, dentry, stat); + + fid = v9fs_fid_lookup(dentry); + if (IS_ERR(fid)) + return PTR_ERR(fid); + + /* Ask for all the fields in stat structure. Server will return + * whatever it supports + */ + + st = p9_client_getattr_dotl(fid, P9_STATS_ALL); + if (IS_ERR(st)) + return PTR_ERR(st); + + v9fs_stat2inode_dotl(st, dentry->d_inode); + generic_fillattr(dentry->d_inode, stat); + /* Change block size to what the server returned */ + stat->blksize = st->st_blksize; + + kfree(st); + return 0; +} + /** * v9fs_vfs_setattr - set file metadata * @dentry: file whose metadata to set @@ -903,6 +1216,49 @@ static int v9fs_vfs_setattr(struct dentry *dentry, struct iattr *iattr) } /** + * v9fs_vfs_setattr_dotl - set file metadata + * @dentry: file whose metadata to set + * @iattr: metadata assignment structure + * + */ + +static int v9fs_vfs_setattr_dotl(struct dentry *dentry, struct iattr *iattr) +{ + int retval; + struct v9fs_session_info *v9ses; + struct p9_fid *fid; + struct p9_iattr_dotl p9attr; + + P9_DPRINTK(P9_DEBUG_VFS, "\n"); + + retval = inode_change_ok(dentry->d_inode, iattr); + if (retval) + return retval; + + p9attr.valid = iattr->ia_valid; + p9attr.mode = iattr->ia_mode; + p9attr.uid = iattr->ia_uid; + p9attr.gid = iattr->ia_gid; + p9attr.size = iattr->ia_size; + p9attr.atime_sec = iattr->ia_atime.tv_sec; + p9attr.atime_nsec = iattr->ia_atime.tv_nsec; + p9attr.mtime_sec = iattr->ia_mtime.tv_sec; + p9attr.mtime_nsec = iattr->ia_mtime.tv_nsec; + + retval = -EPERM; + v9ses = v9fs_inode2v9ses(dentry->d_inode); + fid = v9fs_fid_lookup(dentry); + if (IS_ERR(fid)) + return PTR_ERR(fid); + + retval = p9_client_setattr(fid, &p9attr); + if (retval >= 0) + retval = inode_setattr(dentry->d_inode, iattr); + + return retval; +} + +/** * v9fs_stat2inode - populate an inode structure with mistat info * @stat: Plan 9 metadata (mistat) structure * @inode: inode to populate @@ -980,6 +1336,77 @@ v9fs_stat2inode(struct p9_wstat *stat, struct inode *inode, } /** + * v9fs_stat2inode_dotl - populate an inode structure with stat info + * @stat: stat structure + * @inode: inode to populate + * @sb: superblock of filesystem + * + */ + +void +v9fs_stat2inode_dotl(struct p9_stat_dotl *stat, struct inode *inode) +{ + + if ((stat->st_result_mask & P9_STATS_BASIC) == P9_STATS_BASIC) { + inode->i_atime.tv_sec = stat->st_atime_sec; + inode->i_atime.tv_nsec = stat->st_atime_nsec; + inode->i_mtime.tv_sec = stat->st_mtime_sec; + inode->i_mtime.tv_nsec = stat->st_mtime_nsec; + inode->i_ctime.tv_sec = stat->st_ctime_sec; + inode->i_ctime.tv_nsec = stat->st_ctime_nsec; + inode->i_uid = stat->st_uid; + inode->i_gid = stat->st_gid; + inode->i_nlink = stat->st_nlink; + inode->i_mode = stat->st_mode; + inode->i_rdev = new_decode_dev(stat->st_rdev); + + if ((S_ISBLK(inode->i_mode)) || (S_ISCHR(inode->i_mode))) + init_special_inode(inode, inode->i_mode, inode->i_rdev); + + i_size_write(inode, stat->st_size); + inode->i_blocks = stat->st_blocks; + } else { + if (stat->st_result_mask & P9_STATS_ATIME) { + inode->i_atime.tv_sec = stat->st_atime_sec; + inode->i_atime.tv_nsec = stat->st_atime_nsec; + } + if (stat->st_result_mask & P9_STATS_MTIME) { + inode->i_mtime.tv_sec = stat->st_mtime_sec; + inode->i_mtime.tv_nsec = stat->st_mtime_nsec; + } + if (stat->st_result_mask & P9_STATS_CTIME) { + inode->i_ctime.tv_sec = stat->st_ctime_sec; + inode->i_ctime.tv_nsec = stat->st_ctime_nsec; + } + if (stat->st_result_mask & P9_STATS_UID) + inode->i_uid = stat->st_uid; + if (stat->st_result_mask & P9_STATS_GID) + inode->i_gid = stat->st_gid; + if (stat->st_result_mask & P9_STATS_NLINK) + inode->i_nlink = stat->st_nlink; + if (stat->st_result_mask & P9_STATS_MODE) { + inode->i_mode = stat->st_mode; + if ((S_ISBLK(inode->i_mode)) || + (S_ISCHR(inode->i_mode))) + init_special_inode(inode, inode->i_mode, + inode->i_rdev); + } + if (stat->st_result_mask & P9_STATS_RDEV) + inode->i_rdev = new_decode_dev(stat->st_rdev); + if (stat->st_result_mask & P9_STATS_SIZE) + i_size_write(inode, stat->st_size); + if (stat->st_result_mask & P9_STATS_BLOCKS) + inode->i_blocks = stat->st_blocks; + } + if (stat->st_result_mask & P9_STATS_GEN) + inode->i_generation = stat->st_gen; + + /* Currently we don't support P9_STATS_BTIME and P9_STATS_DATA_VERSION + * because the inode structure does not have fields for them. + */ +} + +/** * v9fs_qid2ino - convert qid into inode number * @qid: qid to hash * @@ -1022,7 +1449,7 @@ static int v9fs_readlink(struct dentry *dentry, char *buffer, int buflen) if (IS_ERR(fid)) return PTR_ERR(fid); - if (!v9fs_proto_dotu(v9ses)) + if (!v9fs_proto_dotu(v9ses) && !v9fs_proto_dotl(v9ses)) return -EBADF; st = p9_client_stat(fid); @@ -1128,6 +1555,99 @@ static int v9fs_vfs_mkspecial(struct inode *dir, struct dentry *dentry, } /** + * v9fs_vfs_symlink_dotl - helper function to create symlinks + * @dir: directory inode containing symlink + * @dentry: dentry for symlink + * @symname: symlink data + * + * See Also: 9P2000.L RFC for more information + * + */ + +static int +v9fs_vfs_symlink_dotl(struct inode *dir, struct dentry *dentry, + const char *symname) +{ + struct v9fs_session_info *v9ses; + struct p9_fid *dfid; + struct p9_fid *fid = NULL; + struct inode *inode; + struct p9_qid qid; + char *name; + int err; + gid_t gid; + + name = (char *) dentry->d_name.name; + P9_DPRINTK(P9_DEBUG_VFS, "v9fs_vfs_symlink_dotl : %lu,%s,%s\n", + dir->i_ino, name, symname); + v9ses = v9fs_inode2v9ses(dir); + + dfid = v9fs_fid_lookup(dentry->d_parent); + if (IS_ERR(dfid)) { + err = PTR_ERR(dfid); + P9_DPRINTK(P9_DEBUG_VFS, "fid lookup failed %d\n", err); + return err; + } + + gid = v9fs_get_fsgid_for_create(dir); + + if (gid < 0) { + P9_DPRINTK(P9_DEBUG_VFS, "v9fs_get_egid failed %d\n", gid); + goto error; + } + + /* Server doesn't alter fid on TSYMLINK. Hence no need to clone it. */ + err = p9_client_symlink(dfid, name, (char *)symname, gid, &qid); + + if (err < 0) { + P9_DPRINTK(P9_DEBUG_VFS, "p9_client_symlink failed %d\n", err); + goto error; + } + + if (v9ses->cache) { + /* Now walk from the parent so we can get an unopened fid. */ + fid = p9_client_walk(dfid, 1, &name, 1); + if (IS_ERR(fid)) { + err = PTR_ERR(fid); + P9_DPRINTK(P9_DEBUG_VFS, "p9_client_walk failed %d\n", + err); + fid = NULL; + goto error; + } + + /* instantiate inode and assign the unopened fid to dentry */ + inode = v9fs_inode_from_fid(v9ses, fid, dir->i_sb); + if (IS_ERR(inode)) { + err = PTR_ERR(inode); + P9_DPRINTK(P9_DEBUG_VFS, "inode creation failed %d\n", + err); + goto error; + } + dentry->d_op = &v9fs_cached_dentry_operations; + d_instantiate(dentry, inode); + err = v9fs_fid_add(dentry, fid); + if (err < 0) + goto error; + fid = NULL; + } else { + /* Not in cached mode. No need to populate inode with stat */ + inode = v9fs_get_inode(dir->i_sb, S_IFLNK); + if (IS_ERR(inode)) { + err = PTR_ERR(inode); + goto error; + } + dentry->d_op = &v9fs_dentry_operations; + d_instantiate(dentry, inode); + } + +error: + if (fid) + p9_client_clunk(fid); + + return err; +} + +/** * v9fs_vfs_symlink - helper function to create symlinks * @dir: directory inode containing symlink * @dentry: dentry for symlink @@ -1186,6 +1706,76 @@ clunk_fid: } /** + * v9fs_vfs_link_dotl - create a hardlink for dotl + * @old_dentry: dentry for file to link to + * @dir: inode destination for new link + * @dentry: dentry for link + * + */ + +static int +v9fs_vfs_link_dotl(struct dentry *old_dentry, struct inode *dir, + struct dentry *dentry) +{ + int err; + struct p9_fid *dfid, *oldfid; + char *name; + struct v9fs_session_info *v9ses; + struct dentry *dir_dentry; + + P9_DPRINTK(P9_DEBUG_VFS, "dir ino: %lu, old_name: %s, new_name: %s\n", + dir->i_ino, old_dentry->d_name.name, + dentry->d_name.name); + + v9ses = v9fs_inode2v9ses(dir); + dir_dentry = v9fs_dentry_from_dir_inode(dir); + dfid = v9fs_fid_lookup(dir_dentry); + if (IS_ERR(dfid)) + return PTR_ERR(dfid); + + oldfid = v9fs_fid_lookup(old_dentry); + if (IS_ERR(oldfid)) + return PTR_ERR(oldfid); + + name = (char *) dentry->d_name.name; + + err = p9_client_link(dfid, oldfid, (char *)dentry->d_name.name); + + if (err < 0) { + P9_DPRINTK(P9_DEBUG_VFS, "p9_client_link failed %d\n", err); + return err; + } + + if (v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) { + /* Get the latest stat info from server. */ + struct p9_fid *fid; + struct p9_stat_dotl *st; + + fid = v9fs_fid_lookup(old_dentry); + if (IS_ERR(fid)) + return PTR_ERR(fid); + + st = p9_client_getattr_dotl(fid, P9_STATS_BASIC); + if (IS_ERR(st)) + return PTR_ERR(st); + + v9fs_stat2inode_dotl(st, old_dentry->d_inode); + + kfree(st); + } else { + /* Caching disabled. No need to get upto date stat info. + * This dentry will be released immediately. So, just i_count++ + */ + atomic_inc(&old_dentry->d_inode->i_count); + } + + dentry->d_op = old_dentry->d_op; + d_instantiate(dentry, old_dentry->d_inode); + + return err; +} + +/** * v9fs_vfs_mknod - create a special file * @dir: inode destination for new link * @dentry: dentry for file @@ -1230,6 +1820,100 @@ v9fs_vfs_mknod(struct inode *dir, struct dentry *dentry, int mode, dev_t rdev) return retval; } +/** + * v9fs_vfs_mknod_dotl - create a special file + * @dir: inode destination for new link + * @dentry: dentry for file + * @mode: mode for creation + * @rdev: device associated with special file + * + */ +static int +v9fs_vfs_mknod_dotl(struct inode *dir, struct dentry *dentry, int mode, + dev_t rdev) +{ + int err; + char *name; + struct v9fs_session_info *v9ses; + struct p9_fid *fid = NULL, *dfid = NULL; + struct inode *inode; + gid_t gid; + struct p9_qid qid; + struct dentry *dir_dentry; + + P9_DPRINTK(P9_DEBUG_VFS, + " %lu,%s mode: %x MAJOR: %u MINOR: %u\n", dir->i_ino, + dentry->d_name.name, mode, MAJOR(rdev), MINOR(rdev)); + + if (!new_valid_dev(rdev)) + return -EINVAL; + + v9ses = v9fs_inode2v9ses(dir); + dir_dentry = v9fs_dentry_from_dir_inode(dir); + dfid = v9fs_fid_lookup(dir_dentry); + if (IS_ERR(dfid)) { + err = PTR_ERR(dfid); + P9_DPRINTK(P9_DEBUG_VFS, "fid lookup failed %d\n", err); + dfid = NULL; + goto error; + } + + gid = v9fs_get_fsgid_for_create(dir); + if (gid < 0) { + P9_DPRINTK(P9_DEBUG_VFS, "v9fs_get_fsgid_for_create failed\n"); + goto error; + } + + name = (char *) dentry->d_name.name; + + err = p9_client_mknod_dotl(dfid, name, mode, rdev, gid, &qid); + if (err < 0) + goto error; + + /* instantiate inode and assign the unopened fid to the dentry */ + if (v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) { + fid = p9_client_walk(dfid, 1, &name, 1); + if (IS_ERR(fid)) { + err = PTR_ERR(fid); + P9_DPRINTK(P9_DEBUG_VFS, "p9_client_walk failed %d\n", + err); + fid = NULL; + goto error; + } + + inode = v9fs_inode_from_fid(v9ses, fid, dir->i_sb); + if (IS_ERR(inode)) { + err = PTR_ERR(inode); + P9_DPRINTK(P9_DEBUG_VFS, "inode creation failed %d\n", + err); + goto error; + } + dentry->d_op = &v9fs_cached_dentry_operations; + d_instantiate(dentry, inode); + err = v9fs_fid_add(dentry, fid); + if (err < 0) + goto error; + fid = NULL; + } else { + /* + * Not in cached mode. No need to populate inode with stat. + * socket syscall returns a fd, so we need instantiate + */ + inode = v9fs_get_inode(dir->i_sb, mode); + if (IS_ERR(inode)) { + err = PTR_ERR(inode); + goto error; + } + dentry->d_op = &v9fs_dentry_operations; + d_instantiate(dentry, inode); + } + +error: + if (fid) + p9_client_clunk(fid); + return err; +} + static const struct inode_operations v9fs_dir_inode_operations_dotu = { .create = v9fs_vfs_create, .lookup = v9fs_vfs_lookup, @@ -1238,24 +1922,29 @@ static const struct inode_operations v9fs_dir_inode_operations_dotu = { .unlink = v9fs_vfs_unlink, .mkdir = v9fs_vfs_mkdir, .rmdir = v9fs_vfs_rmdir, - .mknod = v9fs_vfs_mknod, + .mknod = v9fs_vfs_mknod_dotl, .rename = v9fs_vfs_rename, .getattr = v9fs_vfs_getattr, .setattr = v9fs_vfs_setattr, }; static const struct inode_operations v9fs_dir_inode_operations_dotl = { - .create = v9fs_vfs_create, + .create = v9fs_vfs_create_dotl, .lookup = v9fs_vfs_lookup, - .symlink = v9fs_vfs_symlink, - .link = v9fs_vfs_link, + .link = v9fs_vfs_link_dotl, + .symlink = v9fs_vfs_symlink_dotl, .unlink = v9fs_vfs_unlink, - .mkdir = v9fs_vfs_mkdir, + .mkdir = v9fs_vfs_mkdir_dotl, .rmdir = v9fs_vfs_rmdir, - .mknod = v9fs_vfs_mknod, + .mknod = v9fs_vfs_mknod_dotl, .rename = v9fs_vfs_rename, - .getattr = v9fs_vfs_getattr, - .setattr = v9fs_vfs_setattr, + .getattr = v9fs_vfs_getattr_dotl, + .setattr = v9fs_vfs_setattr_dotl, + .setxattr = generic_setxattr, + .getxattr = generic_getxattr, + .removexattr = generic_removexattr, + .listxattr = v9fs_listxattr, + }; static const struct inode_operations v9fs_dir_inode_operations = { @@ -1276,8 +1965,12 @@ static const struct inode_operations v9fs_file_inode_operations = { }; static const struct inode_operations v9fs_file_inode_operations_dotl = { - .getattr = v9fs_vfs_getattr, - .setattr = v9fs_vfs_setattr, + .getattr = v9fs_vfs_getattr_dotl, + .setattr = v9fs_vfs_setattr_dotl, + .setxattr = generic_setxattr, + .getxattr = generic_getxattr, + .removexattr = generic_removexattr, + .listxattr = v9fs_listxattr, }; static const struct inode_operations v9fs_symlink_inode_operations = { @@ -1292,6 +1985,10 @@ static const struct inode_operations v9fs_symlink_inode_operations_dotl = { .readlink = generic_readlink, .follow_link = v9fs_vfs_follow_link, .put_link = v9fs_vfs_put_link, - .getattr = v9fs_vfs_getattr, - .setattr = v9fs_vfs_setattr, + .getattr = v9fs_vfs_getattr_dotl, + .setattr = v9fs_vfs_setattr_dotl, + .setxattr = generic_setxattr, + .getxattr = generic_getxattr, + .removexattr = generic_removexattr, + .listxattr = v9fs_listxattr, }; diff --git a/fs/9p/vfs_super.c b/fs/9p/vfs_super.c index be74d020436e..4b9ede0b41b7 100644 --- a/fs/9p/vfs_super.c +++ b/fs/9p/vfs_super.c @@ -45,6 +45,7 @@ #include "v9fs.h" #include "v9fs_vfs.h" #include "fid.h" +#include "xattr.h" static const struct super_operations v9fs_super_ops, v9fs_super_ops_dotl; @@ -77,9 +78,10 @@ v9fs_fill_super(struct super_block *sb, struct v9fs_session_info *v9ses, sb->s_blocksize_bits = fls(v9ses->maxdata - 1); sb->s_blocksize = 1 << sb->s_blocksize_bits; sb->s_magic = V9FS_MAGIC; - if (v9fs_proto_dotl(v9ses)) + if (v9fs_proto_dotl(v9ses)) { sb->s_op = &v9fs_super_ops_dotl; - else + sb->s_xattr = v9fs_xattr_handlers; + } else sb->s_op = &v9fs_super_ops; sb->s_bdi = &v9ses->bdi; @@ -107,7 +109,6 @@ static int v9fs_get_sb(struct file_system_type *fs_type, int flags, struct inode *inode = NULL; struct dentry *root = NULL; struct v9fs_session_info *v9ses = NULL; - struct p9_wstat *st = NULL; int mode = S_IRWXUGO | S_ISVTX; struct p9_fid *fid; int retval = 0; @@ -124,16 +125,10 @@ static int v9fs_get_sb(struct file_system_type *fs_type, int flags, goto close_session; } - st = p9_client_stat(fid); - if (IS_ERR(st)) { - retval = PTR_ERR(st); - goto clunk_fid; - } - sb = sget(fs_type, NULL, v9fs_set_super, v9ses); if (IS_ERR(sb)) { retval = PTR_ERR(sb); - goto free_stat; + goto clunk_fid; } v9fs_fill_super(sb, v9ses, flags, data); @@ -151,22 +146,38 @@ static int v9fs_get_sb(struct file_system_type *fs_type, int flags, } sb->s_root = root; - root->d_inode->i_ino = v9fs_qid2ino(&st->qid); - v9fs_stat2inode(st, root->d_inode, sb); + if (v9fs_proto_dotl(v9ses)) { + struct p9_stat_dotl *st = NULL; + st = p9_client_getattr_dotl(fid, P9_STATS_BASIC); + if (IS_ERR(st)) { + retval = PTR_ERR(st); + goto clunk_fid; + } + + v9fs_stat2inode_dotl(st, root->d_inode); + kfree(st); + } else { + struct p9_wstat *st = NULL; + st = p9_client_stat(fid); + if (IS_ERR(st)) { + retval = PTR_ERR(st); + goto clunk_fid; + } + + root->d_inode->i_ino = v9fs_qid2ino(&st->qid); + v9fs_stat2inode(st, root->d_inode, sb); + + p9stat_free(st); + kfree(st); + } v9fs_fid_add(root, fid); - p9stat_free(st); - kfree(st); P9_DPRINTK(P9_DEBUG_VFS, " simple set mount, return 0\n"); simple_set_mnt(mnt, sb); return 0; -free_stat: - p9stat_free(st); - kfree(st); - clunk_fid: p9_client_clunk(fid); @@ -176,8 +187,6 @@ close_session: return retval; release_sb: - p9stat_free(st); - kfree(st); deactivate_locked_super(sb); return retval; } @@ -278,4 +287,5 @@ struct file_system_type v9fs_fs_type = { .get_sb = v9fs_get_sb, .kill_sb = v9fs_kill_super, .owner = THIS_MODULE, + .fs_flags = FS_RENAME_DOES_D_MOVE, }; diff --git a/fs/9p/xattr.c b/fs/9p/xattr.c new file mode 100644 index 000000000000..f88e5c2dc873 --- /dev/null +++ b/fs/9p/xattr.c @@ -0,0 +1,160 @@ +/* + * Copyright IBM Corporation, 2010 + * Author Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2.1 of the GNU Lesser General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include <linux/module.h> +#include <linux/fs.h> +#include <linux/sched.h> +#include <net/9p/9p.h> +#include <net/9p/client.h> + +#include "fid.h" +#include "xattr.h" + +/* + * v9fs_xattr_get() + * + * Copy an extended attribute into the buffer + * provided, or compute the buffer size required. + * Buffer is NULL to compute the size of the buffer required. + * + * Returns a negative error number on failure, or the number of bytes + * used / required on success. + */ +ssize_t v9fs_xattr_get(struct dentry *dentry, const char *name, + void *buffer, size_t buffer_size) +{ + ssize_t retval; + int msize, read_count; + u64 offset = 0, attr_size; + struct p9_fid *fid, *attr_fid; + + P9_DPRINTK(P9_DEBUG_VFS, "%s: name = %s value_len = %zu\n", + __func__, name, buffer_size); + + fid = v9fs_fid_lookup(dentry); + if (IS_ERR(fid)) + return PTR_ERR(fid); + + attr_fid = p9_client_xattrwalk(fid, name, &attr_size); + if (IS_ERR(attr_fid)) { + retval = PTR_ERR(attr_fid); + P9_DPRINTK(P9_DEBUG_VFS, + "p9_client_attrwalk failed %zd\n", retval); + attr_fid = NULL; + goto error; + } + if (!buffer_size) { + /* request to get the attr_size */ + retval = attr_size; + goto error; + } + if (attr_size > buffer_size) { + retval = -ERANGE; + goto error; + } + msize = attr_fid->clnt->msize; + while (attr_size) { + if (attr_size > (msize - P9_IOHDRSZ)) + read_count = msize - P9_IOHDRSZ; + else + read_count = attr_size; + read_count = p9_client_read(attr_fid, ((char *)buffer)+offset, + NULL, offset, read_count); + if (read_count < 0) { + /* error in xattr read */ + retval = read_count; + goto error; + } + offset += read_count; + attr_size -= read_count; + } + /* Total read xattr bytes */ + retval = offset; +error: + if (attr_fid) + p9_client_clunk(attr_fid); + return retval; + +} + +/* + * v9fs_xattr_set() + * + * Create, replace or remove an extended attribute for this inode. Buffer + * is NULL to remove an existing extended attribute, and non-NULL to + * either replace an existing extended attribute, or create a new extended + * attribute. The flags XATTR_REPLACE and XATTR_CREATE + * specify that an extended attribute must exist and must not exist + * previous to the call, respectively. + * + * Returns 0, or a negative error number on failure. + */ +int v9fs_xattr_set(struct dentry *dentry, const char *name, + const void *value, size_t value_len, int flags) +{ + u64 offset = 0; + int retval, msize, write_count; + struct p9_fid *fid = NULL; + + P9_DPRINTK(P9_DEBUG_VFS, "%s: name = %s value_len = %zu flags = %d\n", + __func__, name, value_len, flags); + + fid = v9fs_fid_clone(dentry); + if (IS_ERR(fid)) { + retval = PTR_ERR(fid); + fid = NULL; + goto error; + } + /* + * On success fid points to xattr + */ + retval = p9_client_xattrcreate(fid, name, value_len, flags); + if (retval < 0) { + P9_DPRINTK(P9_DEBUG_VFS, + "p9_client_xattrcreate failed %d\n", retval); + goto error; + } + msize = fid->clnt->msize;; + while (value_len) { + if (value_len > (msize - P9_IOHDRSZ)) + write_count = msize - P9_IOHDRSZ; + else + write_count = value_len; + write_count = p9_client_write(fid, ((char *)value)+offset, + NULL, offset, write_count); + if (write_count < 0) { + /* error in xattr write */ + retval = write_count; + goto error; + } + offset += write_count; + value_len -= write_count; + } + /* Total read xattr bytes */ + retval = offset; +error: + if (fid) + retval = p9_client_clunk(fid); + return retval; +} + +ssize_t v9fs_listxattr(struct dentry *dentry, char *buffer, size_t buffer_size) +{ + return v9fs_xattr_get(dentry, NULL, buffer, buffer_size); +} + +const struct xattr_handler *v9fs_xattr_handlers[] = { + &v9fs_xattr_user_handler, + NULL +}; diff --git a/fs/9p/xattr.h b/fs/9p/xattr.h new file mode 100644 index 000000000000..9ddf672ae5c4 --- /dev/null +++ b/fs/9p/xattr.h @@ -0,0 +1,27 @@ +/* + * Copyright IBM Corporation, 2010 + * Author Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2.1 of the GNU Lesser General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + */ +#ifndef FS_9P_XATTR_H +#define FS_9P_XATTR_H + +#include <linux/xattr.h> + +extern const struct xattr_handler *v9fs_xattr_handlers[]; +extern struct xattr_handler v9fs_xattr_user_handler; + +extern ssize_t v9fs_xattr_get(struct dentry *, const char *, + void *, size_t); +extern int v9fs_xattr_set(struct dentry *, const char *, + const void *, size_t, int); +extern ssize_t v9fs_listxattr(struct dentry *, char *, size_t); +#endif /* FS_9P_XATTR_H */ diff --git a/fs/9p/xattr_user.c b/fs/9p/xattr_user.c new file mode 100644 index 000000000000..d0b701b72080 --- /dev/null +++ b/fs/9p/xattr_user.c @@ -0,0 +1,80 @@ +/* + * Copyright IBM Corporation, 2010 + * Author Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2.1 of the GNU Lesser General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + */ + + +#include <linux/module.h> +#include <linux/string.h> +#include <linux/fs.h> +#include <linux/slab.h> +#include "xattr.h" + +static int v9fs_xattr_user_get(struct dentry *dentry, const char *name, + void *buffer, size_t size, int type) +{ + int retval; + char *full_name; + size_t name_len; + size_t prefix_len = XATTR_USER_PREFIX_LEN; + + if (name == NULL) + return -EINVAL; + + if (strcmp(name, "") == 0) + return -EINVAL; + + name_len = strlen(name); + full_name = kmalloc(prefix_len + name_len + 1 , GFP_KERNEL); + if (!full_name) + return -ENOMEM; + memcpy(full_name, XATTR_USER_PREFIX, prefix_len); + memcpy(full_name+prefix_len, name, name_len); + full_name[prefix_len + name_len] = '\0'; + + retval = v9fs_xattr_get(dentry, full_name, buffer, size); + kfree(full_name); + return retval; +} + +static int v9fs_xattr_user_set(struct dentry *dentry, const char *name, + const void *value, size_t size, int flags, int type) +{ + int retval; + char *full_name; + size_t name_len; + size_t prefix_len = XATTR_USER_PREFIX_LEN; + + if (name == NULL) + return -EINVAL; + + if (strcmp(name, "") == 0) + return -EINVAL; + + name_len = strlen(name); + full_name = kmalloc(prefix_len + name_len + 1 , GFP_KERNEL); + if (!full_name) + return -ENOMEM; + memcpy(full_name, XATTR_USER_PREFIX, prefix_len); + memcpy(full_name + prefix_len, name, name_len); + full_name[prefix_len + name_len] = '\0'; + + retval = v9fs_xattr_set(dentry, full_name, value, size, flags); + kfree(full_name); + return retval; +} + +struct xattr_handler v9fs_xattr_user_handler = { + .prefix = XATTR_USER_PREFIX, + .get = v9fs_xattr_user_get, + .set = v9fs_xattr_user_set, +}; diff --git a/fs/cifs/Kconfig b/fs/cifs/Kconfig index 80f352596807..5739fd7f88b4 100644 --- a/fs/cifs/Kconfig +++ b/fs/cifs/Kconfig @@ -131,6 +131,15 @@ config CIFS_DFS_UPCALL IP addresses) which is needed for implicit mounts of DFS junction points. If unsure, say N. +config CIFS_FSCACHE + bool "Provide CIFS client caching support (EXPERIMENTAL)" + depends on EXPERIMENTAL + depends on CIFS=m && FSCACHE || CIFS=y && FSCACHE=y + help + Makes CIFS FS-Cache capable. Say Y here if you want your CIFS data + to be cached locally on disk through the general filesystem cache + manager. If unsure, say N. + config CIFS_EXPERIMENTAL bool "CIFS Experimental Features (EXPERIMENTAL)" depends on CIFS && EXPERIMENTAL diff --git a/fs/cifs/Makefile b/fs/cifs/Makefile index 9948c0030e86..adefa60a9bdc 100644 --- a/fs/cifs/Makefile +++ b/fs/cifs/Makefile @@ -11,3 +11,5 @@ cifs-y := cifsfs.o cifssmb.o cifs_debug.o connect.o dir.o file.o inode.o \ cifs-$(CONFIG_CIFS_UPCALL) += cifs_spnego.o cifs-$(CONFIG_CIFS_DFS_UPCALL) += dns_resolve.o cifs_dfs_ref.o + +cifs-$(CONFIG_CIFS_FSCACHE) += fscache.o cache.o diff --git a/fs/cifs/cache.c b/fs/cifs/cache.c new file mode 100644 index 000000000000..224d7bbd1fcc --- /dev/null +++ b/fs/cifs/cache.c @@ -0,0 +1,331 @@ +/* + * fs/cifs/cache.c - CIFS filesystem cache index structure definitions + * + * Copyright (c) 2010 Novell, Inc. + * Authors(s): Suresh Jayaraman (sjayaraman@suse.de> + * + * This library is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; either version 2.1 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + * the GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include "fscache.h" +#include "cifs_debug.h" + +/* + * CIFS filesystem definition for FS-Cache + */ +struct fscache_netfs cifs_fscache_netfs = { + .name = "cifs", + .version = 0, +}; + +/* + * Register CIFS for caching with FS-Cache + */ +int cifs_fscache_register(void) +{ + return fscache_register_netfs(&cifs_fscache_netfs); +} + +/* + * Unregister CIFS for caching + */ +void cifs_fscache_unregister(void) +{ + fscache_unregister_netfs(&cifs_fscache_netfs); +} + +/* + * Key layout of CIFS server cache index object + */ +struct cifs_server_key { + uint16_t family; /* address family */ + uint16_t port; /* IP port */ + union { + struct in_addr ipv4_addr; + struct in6_addr ipv6_addr; + } addr[0]; +}; + +/* + * Server object keyed by {IPaddress,port,family} tuple + */ +static uint16_t cifs_server_get_key(const void *cookie_netfs_data, + void *buffer, uint16_t maxbuf) +{ + const struct TCP_Server_Info *server = cookie_netfs_data; + const struct sockaddr *sa = (struct sockaddr *) &server->addr.sockAddr; + struct cifs_server_key *key = buffer; + uint16_t key_len = sizeof(struct cifs_server_key); + + memset(key, 0, key_len); + + /* + * Should not be a problem as sin_family/sin6_family overlays + * sa_family field + */ + switch (sa->sa_family) { + case AF_INET: + key->family = server->addr.sockAddr.sin_family; + key->port = server->addr.sockAddr.sin_port; + key->addr[0].ipv4_addr = server->addr.sockAddr.sin_addr; + key_len += sizeof(key->addr[0].ipv4_addr); + break; + + case AF_INET6: + key->family = server->addr.sockAddr6.sin6_family; + key->port = server->addr.sockAddr6.sin6_port; + key->addr[0].ipv6_addr = server->addr.sockAddr6.sin6_addr; + key_len += sizeof(key->addr[0].ipv6_addr); + break; + + default: + cERROR(1, "CIFS: Unknown network family '%d'", sa->sa_family); + key_len = 0; + break; + } + + return key_len; +} + +/* + * Server object for FS-Cache + */ +const struct fscache_cookie_def cifs_fscache_server_index_def = { + .name = "CIFS.server", + .type = FSCACHE_COOKIE_TYPE_INDEX, + .get_key = cifs_server_get_key, +}; + +/* + * Auxiliary data attached to CIFS superblock within the cache + */ +struct cifs_fscache_super_auxdata { + u64 resource_id; /* unique server resource id */ +}; + +static char *extract_sharename(const char *treename) +{ + const char *src; + char *delim, *dst; + int len; + + /* skip double chars at the beginning */ + src = treename + 2; + + /* share name is always preceded by '\\' now */ + delim = strchr(src, '\\'); + if (!delim) + return ERR_PTR(-EINVAL); + delim++; + len = strlen(delim); + + /* caller has to free the memory */ + dst = kstrndup(delim, len, GFP_KERNEL); + if (!dst) + return ERR_PTR(-ENOMEM); + + return dst; +} + +/* + * Superblock object currently keyed by share name + */ +static uint16_t cifs_super_get_key(const void *cookie_netfs_data, void *buffer, + uint16_t maxbuf) +{ + const struct cifsTconInfo *tcon = cookie_netfs_data; + char *sharename; + uint16_t len; + + sharename = extract_sharename(tcon->treeName); + if (IS_ERR(sharename)) { + cFYI(1, "CIFS: couldn't extract sharename\n"); + sharename = NULL; + return 0; + } + + len = strlen(sharename); + if (len > maxbuf) + return 0; + + memcpy(buffer, sharename, len); + + kfree(sharename); + + return len; +} + +static uint16_t +cifs_fscache_super_get_aux(const void *cookie_netfs_data, void *buffer, + uint16_t maxbuf) +{ + struct cifs_fscache_super_auxdata auxdata; + const struct cifsTconInfo *tcon = cookie_netfs_data; + + memset(&auxdata, 0, sizeof(auxdata)); + auxdata.resource_id = tcon->resource_id; + + if (maxbuf > sizeof(auxdata)) + maxbuf = sizeof(auxdata); + + memcpy(buffer, &auxdata, maxbuf); + + return maxbuf; +} + +static enum +fscache_checkaux cifs_fscache_super_check_aux(void *cookie_netfs_data, + const void *data, + uint16_t datalen) +{ + struct cifs_fscache_super_auxdata auxdata; + const struct cifsTconInfo *tcon = cookie_netfs_data; + + if (datalen != sizeof(auxdata)) + return FSCACHE_CHECKAUX_OBSOLETE; + + memset(&auxdata, 0, sizeof(auxdata)); + auxdata.resource_id = tcon->resource_id; + + if (memcmp(data, &auxdata, datalen) != 0) + return FSCACHE_CHECKAUX_OBSOLETE; + + return FSCACHE_CHECKAUX_OKAY; +} + +/* + * Superblock object for FS-Cache + */ +const struct fscache_cookie_def cifs_fscache_super_index_def = { + .name = "CIFS.super", + .type = FSCACHE_COOKIE_TYPE_INDEX, + .get_key = cifs_super_get_key, + .get_aux = cifs_fscache_super_get_aux, + .check_aux = cifs_fscache_super_check_aux, +}; + +/* + * Auxiliary data attached to CIFS inode within the cache + */ +struct cifs_fscache_inode_auxdata { + struct timespec last_write_time; + struct timespec last_change_time; + u64 eof; +}; + +static uint16_t cifs_fscache_inode_get_key(const void *cookie_netfs_data, + void *buffer, uint16_t maxbuf) +{ + const struct cifsInodeInfo *cifsi = cookie_netfs_data; + uint16_t keylen; + + /* use the UniqueId as the key */ + keylen = sizeof(cifsi->uniqueid); + if (keylen > maxbuf) + keylen = 0; + else + memcpy(buffer, &cifsi->uniqueid, keylen); + + return keylen; +} + +static void +cifs_fscache_inode_get_attr(const void *cookie_netfs_data, uint64_t *size) +{ + const struct cifsInodeInfo *cifsi = cookie_netfs_data; + + *size = cifsi->vfs_inode.i_size; +} + +static uint16_t +cifs_fscache_inode_get_aux(const void *cookie_netfs_data, void *buffer, + uint16_t maxbuf) +{ + struct cifs_fscache_inode_auxdata auxdata; + const struct cifsInodeInfo *cifsi = cookie_netfs_data; + + memset(&auxdata, 0, sizeof(auxdata)); + auxdata.eof = cifsi->server_eof; + auxdata.last_write_time = cifsi->vfs_inode.i_mtime; + auxdata.last_change_time = cifsi->vfs_inode.i_ctime; + + if (maxbuf > sizeof(auxdata)) + maxbuf = sizeof(auxdata); + + memcpy(buffer, &auxdata, maxbuf); + + return maxbuf; +} + +static enum +fscache_checkaux cifs_fscache_inode_check_aux(void *cookie_netfs_data, + const void *data, + uint16_t datalen) +{ + struct cifs_fscache_inode_auxdata auxdata; + struct cifsInodeInfo *cifsi = cookie_netfs_data; + + if (datalen != sizeof(auxdata)) + return FSCACHE_CHECKAUX_OBSOLETE; + + memset(&auxdata, 0, sizeof(auxdata)); + auxdata.eof = cifsi->server_eof; + auxdata.last_write_time = cifsi->vfs_inode.i_mtime; + auxdata.last_change_time = cifsi->vfs_inode.i_ctime; + + if (memcmp(data, &auxdata, datalen) != 0) + return FSCACHE_CHECKAUX_OBSOLETE; + + return FSCACHE_CHECKAUX_OKAY; +} + +static void cifs_fscache_inode_now_uncached(void *cookie_netfs_data) +{ + struct cifsInodeInfo *cifsi = cookie_netfs_data; + struct pagevec pvec; + pgoff_t first; + int loop, nr_pages; + + pagevec_init(&pvec, 0); + first = 0; + + cFYI(1, "cifs inode 0x%p now uncached", cifsi); + + for (;;) { + nr_pages = pagevec_lookup(&pvec, + cifsi->vfs_inode.i_mapping, first, + PAGEVEC_SIZE - pagevec_count(&pvec)); + if (!nr_pages) + break; + + for (loop = 0; loop < nr_pages; loop++) + ClearPageFsCache(pvec.pages[loop]); + + first = pvec.pages[nr_pages - 1]->index + 1; + + pvec.nr = nr_pages; + pagevec_release(&pvec); + cond_resched(); + } +} + +const struct fscache_cookie_def cifs_fscache_inode_object_def = { + .name = "CIFS.uniqueid", + .type = FSCACHE_COOKIE_TYPE_DATAFILE, + .get_key = cifs_fscache_inode_get_key, + .get_attr = cifs_fscache_inode_get_attr, + .get_aux = cifs_fscache_inode_get_aux, + .check_aux = cifs_fscache_inode_check_aux, + .now_uncached = cifs_fscache_inode_now_uncached, +}; diff --git a/fs/cifs/cifs_dfs_ref.c b/fs/cifs/cifs_dfs_ref.c index ac19a6f3dae0..dc1ed50ea06e 100644 --- a/fs/cifs/cifs_dfs_ref.c +++ b/fs/cifs/cifs_dfs_ref.c @@ -230,28 +230,22 @@ compose_mount_options_err: goto compose_mount_options_out; } - -static struct vfsmount *cifs_dfs_do_refmount(const struct vfsmount *mnt_parent, - struct dentry *dentry, const struct dfs_info3_param *ref) +/** + * cifs_dfs_do_refmount - mounts specified path using provided refferal + * @cifs_sb: parent/root superblock + * @fullpath: full path in UNC format + * @ref: server's referral + */ +static struct vfsmount *cifs_dfs_do_refmount(struct cifs_sb_info *cifs_sb, + const char *fullpath, const struct dfs_info3_param *ref) { - struct cifs_sb_info *cifs_sb; struct vfsmount *mnt; char *mountdata; char *devname = NULL; - char *fullpath; - - cifs_sb = CIFS_SB(dentry->d_inode->i_sb); - /* - * this function gives us a path with a double backslash prefix. We - * require a single backslash for DFS. - */ - fullpath = build_path_from_dentry(dentry); - if (!fullpath) - return ERR_PTR(-ENOMEM); + /* strip first '\' from fullpath */ mountdata = cifs_compose_mount_options(cifs_sb->mountdata, fullpath + 1, ref, &devname); - kfree(fullpath); if (IS_ERR(mountdata)) return (struct vfsmount *)mountdata; @@ -357,8 +351,8 @@ cifs_dfs_follow_mountpoint(struct dentry *dentry, struct nameidata *nd) rc = -EINVAL; goto out_err; } - mnt = cifs_dfs_do_refmount(nd->path.mnt, - nd->path.dentry, referrals + i); + mnt = cifs_dfs_do_refmount(cifs_sb, + full_path, referrals + i); cFYI(1, "%s: cifs_dfs_do_refmount:%s , mnt:%p", __func__, referrals[i].node_name, mnt); diff --git a/fs/cifs/cifs_fs_sb.h b/fs/cifs/cifs_fs_sb.h index 246a167cb913..9e771450c3b8 100644 --- a/fs/cifs/cifs_fs_sb.h +++ b/fs/cifs/cifs_fs_sb.h @@ -35,6 +35,7 @@ #define CIFS_MOUNT_DYNPERM 0x1000 /* allow in-memory only mode setting */ #define CIFS_MOUNT_NOPOSIXBRL 0x2000 /* mandatory not posix byte range lock */ #define CIFS_MOUNT_NOSSYNC 0x4000 /* don't do slow SMBflush on every sync*/ +#define CIFS_MOUNT_FSCACHE 0x8000 /* local caching enabled */ struct cifs_sb_info { struct cifsTconInfo *tcon; /* primary mount */ diff --git a/fs/cifs/cifs_spnego.c b/fs/cifs/cifs_spnego.c index 379bd7d9c05f..6effccff85a5 100644 --- a/fs/cifs/cifs_spnego.c +++ b/fs/cifs/cifs_spnego.c @@ -144,6 +144,9 @@ cifs_get_spnego_key(struct cifsSesInfo *sesInfo) sprintf(dp, ";uid=0x%x", sesInfo->linux_uid); dp = description + strlen(description); + sprintf(dp, ";creduid=0x%x", sesInfo->cred_uid); + + dp = description + strlen(description); sprintf(dp, ";user=%s", sesInfo->userName); dp = description + strlen(description); diff --git a/fs/cifs/cifsfs.c b/fs/cifs/cifsfs.c index 2cb1a70214d7..8a2cf129e535 100644 --- a/fs/cifs/cifsfs.c +++ b/fs/cifs/cifsfs.c @@ -47,6 +47,7 @@ #include <linux/key-type.h> #include "dns_resolve.h" #include "cifs_spnego.h" +#include "fscache.h" #define CIFS_MAGIC_NUMBER 0xFF534D42 /* the first four bytes of SMB PDUs */ int cifsFYI = 0; @@ -329,6 +330,12 @@ cifs_destroy_inode(struct inode *inode) } static void +cifs_clear_inode(struct inode *inode) +{ + cifs_fscache_release_inode_cookie(inode); +} + +static void cifs_show_address(struct seq_file *s, struct TCP_Server_Info *server) { seq_printf(s, ",addr="); @@ -489,6 +496,7 @@ static const struct super_operations cifs_super_ops = { .alloc_inode = cifs_alloc_inode, .destroy_inode = cifs_destroy_inode, .drop_inode = cifs_drop_inode, + .clear_inode = cifs_clear_inode, /* .delete_inode = cifs_delete_inode, */ /* Do not need above function unless later we add lazy close of inodes or unless the kernel forgets to call us with the same number of releases (closes) @@ -902,6 +910,10 @@ init_cifs(void) cFYI(1, "cifs_max_pending set to max of 256"); } + rc = cifs_fscache_register(); + if (rc) + goto out; + rc = cifs_init_inodecache(); if (rc) goto out_clean_proc; @@ -951,6 +963,8 @@ init_cifs(void) cifs_destroy_inodecache(); out_clean_proc: cifs_proc_clean(); + cifs_fscache_unregister(); + out: return rc; } @@ -959,6 +973,7 @@ exit_cifs(void) { cFYI(DBG2, "exit_cifs"); cifs_proc_clean(); + cifs_fscache_unregister(); #ifdef CONFIG_CIFS_DFS_UPCALL cifs_dfs_release_automount_timer(); cifs_exit_dns_resolver(); diff --git a/fs/cifs/cifsfs.h b/fs/cifs/cifsfs.h index a7eb65c84b1c..d82f5fb4761e 100644 --- a/fs/cifs/cifsfs.h +++ b/fs/cifs/cifsfs.h @@ -114,5 +114,5 @@ extern long cifs_ioctl(struct file *filep, unsigned int cmd, unsigned long arg); extern const struct export_operations cifs_export_ops; #endif /* EXPERIMENTAL */ -#define CIFS_VERSION "1.64" +#define CIFS_VERSION "1.65" #endif /* _CIFSFS_H */ diff --git a/fs/cifs/cifsglob.h b/fs/cifs/cifsglob.h index a88479ceaad5..59906146ad36 100644 --- a/fs/cifs/cifsglob.h +++ b/fs/cifs/cifsglob.h @@ -16,6 +16,9 @@ * the GNU Lesser General Public License for more details. * */ +#ifndef _CIFS_GLOB_H +#define _CIFS_GLOB_H + #include <linux/in.h> #include <linux/in6.h> #include <linux/slab.h> @@ -34,7 +37,7 @@ #define MAX_SHARE_SIZE 64 /* used to be 20, this should still be enough */ #define MAX_USERNAME_SIZE 32 /* 32 is to allow for 15 char names + null termination then *2 for unicode versions */ -#define MAX_PASSWORD_SIZE 16 +#define MAX_PASSWORD_SIZE 512 /* max for windows seems to be 256 wide chars */ #define CIFS_MIN_RCV_POOL 4 @@ -80,8 +83,7 @@ enum statusEnum { }; enum securityEnum { - PLAINTXT = 0, /* Legacy with Plaintext passwords */ - LANMAN, /* Legacy LANMAN auth */ + LANMAN = 0, /* Legacy LANMAN auth */ NTLM, /* Legacy NTLM012 auth with NTLM hash */ NTLMv2, /* Legacy NTLM auth with NTLMv2 hash */ RawNTLMSSP, /* NTLMSSP without SPNEGO, NTLMv2 hash */ @@ -142,7 +144,6 @@ struct TCP_Server_Info { struct list_head pending_mid_q; void *Server_NlsInfo; /* BB - placeholder for future NLS info */ unsigned short server_codepage; /* codepage for the server */ - unsigned long ip_address; /* IP addr for the server if known */ enum protocolEnum protocolType; char versionMajor; char versionMinor; @@ -190,19 +191,9 @@ struct TCP_Server_Info { bool sec_mskerberos; /* supports legacy MS Kerberos */ bool sec_kerberosu2u; /* supports U2U Kerberos */ bool sec_ntlmssp; /* supports NTLMSSP */ -}; - -/* - * The following is our shortcut to user information. We surface the uid, - * and name. We always get the password on the fly in case it - * has changed. We also hang a list of sessions owned by this user off here. - */ -struct cifsUidInfo { - struct list_head userList; - struct list_head sessionList; /* SMB sessions for this user */ - uid_t linux_uid; - char user[MAX_USERNAME_SIZE + 1]; /* ascii name of user */ - /* BB may need ptr or callback for PAM or WinBind info */ +#ifdef CONFIG_CIFS_FSCACHE + struct fscache_cookie *fscache; /* client index cache cookie */ +#endif }; /* @@ -212,9 +203,6 @@ struct cifsSesInfo { struct list_head smb_ses_list; struct list_head tcon_list; struct mutex session_mutex; -#if 0 - struct cifsUidInfo *uidInfo; /* pointer to user info */ -#endif struct TCP_Server_Info *server; /* pointer to server info */ int ses_count; /* reference counter */ enum statusEnum status; @@ -226,7 +214,8 @@ struct cifsSesInfo { char *serverNOS; /* name of network operating system of server */ char *serverDomain; /* security realm of server */ int Suid; /* remote smb uid */ - uid_t linux_uid; /* local Linux uid */ + uid_t linux_uid; /* overriding owner of files on the mount */ + uid_t cred_uid; /* owner of credentials */ int capabilities; char serverName[SERVER_NAME_LEN_WITH_NULL * 2]; /* BB make bigger for TCP names - will ipv6 and sctp addresses fit? */ @@ -311,6 +300,10 @@ struct cifsTconInfo { bool local_lease:1; /* check leases (only) on local system not remote */ bool broken_posix_open; /* e.g. Samba server versions < 3.3.2, 3.2.9 */ bool need_reconnect:1; /* connection reset, tid now invalid */ +#ifdef CONFIG_CIFS_FSCACHE + u64 resource_id; /* server resource id */ + struct fscache_cookie *fscache; /* cookie for share */ +#endif /* BB add field for back pointer to sb struct(s)? */ }; @@ -398,6 +391,9 @@ struct cifsInodeInfo { bool invalid_mapping:1; /* pagecache is invalid */ u64 server_eof; /* current file size on server */ u64 uniqueid; /* server inode number */ +#ifdef CONFIG_CIFS_FSCACHE + struct fscache_cookie *fscache; +#endif struct inode vfs_inode; }; @@ -733,3 +729,5 @@ GLOBAL_EXTERN unsigned int cifs_min_small; /* min size of small buf pool */ GLOBAL_EXTERN unsigned int cifs_max_pending; /* MAX requests at once to server*/ extern const struct slow_work_ops cifs_oplock_break_ops; + +#endif /* _CIFS_GLOB_H */ diff --git a/fs/cifs/cifsproto.h b/fs/cifs/cifsproto.h index fb6318b81509..2eaebbd31132 100644 --- a/fs/cifs/cifsproto.h +++ b/fs/cifs/cifsproto.h @@ -86,7 +86,9 @@ extern unsigned int smbCalcSize(struct smb_hdr *ptr); extern unsigned int smbCalcSize_LE(struct smb_hdr *ptr); extern int decode_negTokenInit(unsigned char *security_blob, int length, struct TCP_Server_Info *server); -extern int cifs_convert_address(char *src, void *dst); +extern int cifs_convert_address(struct sockaddr *dst, char *src); +extern int cifs_fill_sockaddr(struct sockaddr *dst, char *src, + unsigned short int port); extern int map_smb_to_linux_error(struct smb_hdr *smb, int logErr); extern void header_assemble(struct smb_hdr *, char /* command */ , const struct cifsTconInfo *, int /* length of diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c index 2208f06e4c45..2a43a0aca965 100644 --- a/fs/cifs/connect.c +++ b/fs/cifs/connect.c @@ -48,6 +48,7 @@ #include "nterr.h" #include "rfc1002pdu.h" #include "cn_cifs.h" +#include "fscache.h" #define CIFS_PORT 445 #define RFC1001_PORT 139 @@ -66,6 +67,7 @@ struct smb_vol { char *iocharset; /* local code page for mapping to and from Unicode */ char source_rfc1001_name[16]; /* netbios name of client */ char target_rfc1001_name[16]; /* netbios name of server for Win9x/ME */ + uid_t cred_uid; uid_t linux_uid; gid_t linux_gid; mode_t file_mode; @@ -97,6 +99,7 @@ struct smb_vol { bool noblocksnd:1; bool noautotune:1; bool nostrictsync:1; /* do not force expensive SMBflush on every sync */ + bool fsc:1; /* enable fscache */ unsigned int rsize; unsigned int wsize; bool sockopt_tcp_nodelay:1; @@ -830,7 +833,8 @@ cifs_parse_mount_options(char *options, const char *devname, /* null target name indicates to use *SMBSERVR default called name if we end up sending RFC1001 session initialize */ vol->target_rfc1001_name[0] = 0; - vol->linux_uid = current_uid(); /* use current_euid() instead? */ + vol->cred_uid = current_uid(); + vol->linux_uid = current_uid(); vol->linux_gid = current_gid(); /* default to only allowing write access to owner of the mount */ @@ -1257,6 +1261,12 @@ cifs_parse_mount_options(char *options, const char *devname, } else if ((strnicmp(data, "nocase", 6) == 0) || (strnicmp(data, "ignorecase", 10) == 0)) { vol->nocase = 1; + } else if (strnicmp(data, "mand", 4) == 0) { + /* ignore */ + } else if (strnicmp(data, "nomand", 6) == 0) { + /* ignore */ + } else if (strnicmp(data, "_netdev", 7) == 0) { + /* ignore */ } else if (strnicmp(data, "brl", 3) == 0) { vol->nobrl = 0; } else if ((strnicmp(data, "nobrl", 5) == 0) || @@ -1331,6 +1341,8 @@ cifs_parse_mount_options(char *options, const char *devname, printk(KERN_WARNING "CIFS: Mount option noac not " "supported. Instead set " "/proc/fs/cifs/LookupCacheEnabled to 0\n"); + } else if (strnicmp(data, "fsc", 3) == 0) { + vol->fsc = true; } else printk(KERN_WARNING "CIFS: Unknown mount option %s\n", data); @@ -1380,18 +1392,92 @@ cifs_parse_mount_options(char *options, const char *devname, return 0; } +static bool +match_address(struct TCP_Server_Info *server, struct sockaddr *addr) +{ + struct sockaddr_in *addr4 = (struct sockaddr_in *)addr; + struct sockaddr_in6 *addr6 = (struct sockaddr_in6 *)addr; + + switch (addr->sa_family) { + case AF_INET: + if (addr4->sin_addr.s_addr != + server->addr.sockAddr.sin_addr.s_addr) + return false; + if (addr4->sin_port && + addr4->sin_port != server->addr.sockAddr.sin_port) + return false; + break; + case AF_INET6: + if (!ipv6_addr_equal(&addr6->sin6_addr, + &server->addr.sockAddr6.sin6_addr)) + return false; + if (addr6->sin6_scope_id != + server->addr.sockAddr6.sin6_scope_id) + return false; + if (addr6->sin6_port && + addr6->sin6_port != server->addr.sockAddr6.sin6_port) + return false; + break; + } + + return true; +} + +static bool +match_security(struct TCP_Server_Info *server, struct smb_vol *vol) +{ + unsigned int secFlags; + + if (vol->secFlg & (~(CIFSSEC_MUST_SIGN | CIFSSEC_MUST_SEAL))) + secFlags = vol->secFlg; + else + secFlags = global_secflags | vol->secFlg; + + switch (server->secType) { + case LANMAN: + if (!(secFlags & (CIFSSEC_MAY_LANMAN|CIFSSEC_MAY_PLNTXT))) + return false; + break; + case NTLMv2: + if (!(secFlags & CIFSSEC_MAY_NTLMV2)) + return false; + break; + case NTLM: + if (!(secFlags & CIFSSEC_MAY_NTLM)) + return false; + break; + case Kerberos: + if (!(secFlags & CIFSSEC_MAY_KRB5)) + return false; + break; + case RawNTLMSSP: + if (!(secFlags & CIFSSEC_MAY_NTLMSSP)) + return false; + break; + default: + /* shouldn't happen */ + return false; + } + + /* now check if signing mode is acceptible */ + if ((secFlags & CIFSSEC_MAY_SIGN) == 0 && + (server->secMode & SECMODE_SIGN_REQUIRED)) + return false; + else if (((secFlags & CIFSSEC_MUST_SIGN) == CIFSSEC_MUST_SIGN) && + (server->secMode & + (SECMODE_SIGN_ENABLED|SECMODE_SIGN_REQUIRED)) == 0) + return false; + + return true; +} + static struct TCP_Server_Info * -cifs_find_tcp_session(struct sockaddr_storage *addr, unsigned short int port) +cifs_find_tcp_session(struct sockaddr *addr, struct smb_vol *vol) { - struct list_head *tmp; struct TCP_Server_Info *server; - struct sockaddr_in *addr4 = (struct sockaddr_in *) addr; - struct sockaddr_in6 *addr6 = (struct sockaddr_in6 *) addr; write_lock(&cifs_tcp_ses_lock); - list_for_each(tmp, &cifs_tcp_ses_list) { - server = list_entry(tmp, struct TCP_Server_Info, - tcp_ses_list); + list_for_each_entry(server, &cifs_tcp_ses_list, tcp_ses_list) { /* * the demux thread can exit on its own while still in CifsNew * so don't accept any sockets in that state. Since the @@ -1401,37 +1487,11 @@ cifs_find_tcp_session(struct sockaddr_storage *addr, unsigned short int port) if (server->tcpStatus == CifsNew) continue; - switch (addr->ss_family) { - case AF_INET: - if (addr4->sin_addr.s_addr == - server->addr.sockAddr.sin_addr.s_addr) { - addr4->sin_port = htons(port); - /* user overrode default port? */ - if (addr4->sin_port) { - if (addr4->sin_port != - server->addr.sockAddr.sin_port) - continue; - } - break; - } else - continue; + if (!match_address(server, addr)) + continue; - case AF_INET6: - if (ipv6_addr_equal(&addr6->sin6_addr, - &server->addr.sockAddr6.sin6_addr) && - (addr6->sin6_scope_id == - server->addr.sockAddr6.sin6_scope_id)) { - addr6->sin6_port = htons(port); - /* user overrode default port? */ - if (addr6->sin6_port) { - if (addr6->sin6_port != - server->addr.sockAddr6.sin6_port) - continue; - } - break; - } else - continue; - } + if (!match_security(server, vol)) + continue; ++server->srv_count; write_unlock(&cifs_tcp_ses_lock); @@ -1460,6 +1520,8 @@ cifs_put_tcp_session(struct TCP_Server_Info *server) server->tcpStatus = CifsExiting; spin_unlock(&GlobalMid_Lock); + cifs_fscache_release_client_cookie(server); + task = xchg(&server->tsk, NULL); if (task) force_sig(SIGKILL, task); @@ -1479,7 +1541,9 @@ cifs_get_tcp_session(struct smb_vol *volume_info) cFYI(1, "UNC: %s ip: %s", volume_info->UNC, volume_info->UNCip); if (volume_info->UNCip && volume_info->UNC) { - rc = cifs_convert_address(volume_info->UNCip, &addr); + rc = cifs_fill_sockaddr((struct sockaddr *)&addr, + volume_info->UNCip, + volume_info->port); if (!rc) { /* we failed translating address */ rc = -EINVAL; @@ -1499,7 +1563,7 @@ cifs_get_tcp_session(struct smb_vol *volume_info) } /* see if we already have a matching tcp_ses */ - tcp_ses = cifs_find_tcp_session(&addr, volume_info->port); + tcp_ses = cifs_find_tcp_session((struct sockaddr *)&addr, volume_info); if (tcp_ses) return tcp_ses; @@ -1543,12 +1607,10 @@ cifs_get_tcp_session(struct smb_vol *volume_info) cFYI(1, "attempting ipv6 connect"); /* BB should we allow ipv6 on port 139? */ /* other OS never observed in Wild doing 139 with v6 */ - sin_server6->sin6_port = htons(volume_info->port); memcpy(&tcp_ses->addr.sockAddr6, sin_server6, sizeof(struct sockaddr_in6)); rc = ipv6_connect(tcp_ses); } else { - sin_server->sin_port = htons(volume_info->port); memcpy(&tcp_ses->addr.sockAddr, sin_server, sizeof(struct sockaddr_in)); rc = ipv4_connect(tcp_ses); @@ -1577,6 +1639,8 @@ cifs_get_tcp_session(struct smb_vol *volume_info) list_add(&tcp_ses->tcp_ses_list, &cifs_tcp_ses_list); write_unlock(&cifs_tcp_ses_lock); + cifs_fscache_get_client_cookie(tcp_ses); + return tcp_ses; out_err: @@ -1591,17 +1655,27 @@ out_err: } static struct cifsSesInfo * -cifs_find_smb_ses(struct TCP_Server_Info *server, char *username) +cifs_find_smb_ses(struct TCP_Server_Info *server, struct smb_vol *vol) { - struct list_head *tmp; struct cifsSesInfo *ses; write_lock(&cifs_tcp_ses_lock); - list_for_each(tmp, &server->smb_ses_list) { - ses = list_entry(tmp, struct cifsSesInfo, smb_ses_list); - if (strncmp(ses->userName, username, MAX_USERNAME_SIZE)) - continue; - + list_for_each_entry(ses, &server->smb_ses_list, smb_ses_list) { + switch (server->secType) { + case Kerberos: + if (vol->cred_uid != ses->cred_uid) + continue; + break; + default: + /* anything else takes username/password */ + if (strncmp(ses->userName, vol->username, + MAX_USERNAME_SIZE)) + continue; + if (strlen(vol->username) != 0 && + strncmp(ses->password, vol->password, + MAX_PASSWORD_SIZE)) + continue; + } ++ses->ses_count; write_unlock(&cifs_tcp_ses_lock); return ses; @@ -1643,7 +1717,7 @@ cifs_get_smb_ses(struct TCP_Server_Info *server, struct smb_vol *volume_info) xid = GetXid(); - ses = cifs_find_smb_ses(server, volume_info->username); + ses = cifs_find_smb_ses(server, volume_info); if (ses) { cFYI(1, "Existing smb sess found (status=%d)", ses->status); @@ -1706,6 +1780,7 @@ cifs_get_smb_ses(struct TCP_Server_Info *server, struct smb_vol *volume_info) if (ses->domainName) strcpy(ses->domainName, volume_info->domainname); } + ses->cred_uid = volume_info->cred_uid; ses->linux_uid = volume_info->linux_uid; ses->overrideSecFlg = volume_info->secFlg; @@ -1773,6 +1848,7 @@ cifs_put_tcon(struct cifsTconInfo *tcon) CIFSSMBTDis(xid, tcon); _FreeXid(xid); + cifs_fscache_release_super_cookie(tcon); tconInfoFree(tcon); cifs_put_smb_ses(ses); } @@ -1843,6 +1919,8 @@ cifs_get_tcon(struct cifsSesInfo *ses, struct smb_vol *volume_info) list_add(&tcon->tcon_list, &ses->tcon_list); write_unlock(&cifs_tcp_ses_lock); + cifs_fscache_get_super_cookie(tcon); + return tcon; out_fail: @@ -2397,6 +2475,8 @@ static void setup_cifs_sb(struct smb_vol *pvolume_info, cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_OVERR_GID; if (pvolume_info->dynperm) cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_DYNPERM; + if (pvolume_info->fsc) + cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_FSCACHE; if (pvolume_info->direct_io) { cFYI(1, "mounting share using direct i/o"); cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_DIRECT_IO; diff --git a/fs/cifs/dir.c b/fs/cifs/dir.c index e7ae78b66fa1..a7de5e9fff11 100644 --- a/fs/cifs/dir.c +++ b/fs/cifs/dir.c @@ -130,12 +130,6 @@ cifs_bp_rename_retry: return full_path; } -/* - * When called with struct file pointer set to NULL, there is no way we could - * update file->private_data, but getting it stuck on openFileList provides a - * way to access it from cifs_fill_filedata and thereby set file->private_data - * from cifs_open. - */ struct cifsFileInfo * cifs_new_fileinfo(struct inode *newinode, __u16 fileHandle, struct file *file, struct vfsmount *mnt, unsigned int oflags) diff --git a/fs/cifs/dns_resolve.c b/fs/cifs/dns_resolve.c index 49315cbf742d..3ad7f4300c45 100644 --- a/fs/cifs/dns_resolve.c +++ b/fs/cifs/dns_resolve.c @@ -44,7 +44,7 @@ is_ip(char *name) { struct sockaddr_storage ss; - return cifs_convert_address(name, &ss); + return cifs_convert_address((struct sockaddr *)&ss, name); } static int @@ -227,7 +227,7 @@ failed_put_cred: return ret; } -void __exit cifs_exit_dns_resolver(void) +void cifs_exit_dns_resolver(void) { key_revoke(dns_resolver_cache->thread_keyring); unregister_key_type(&key_type_dns_resolver); diff --git a/fs/cifs/dns_resolve.h b/fs/cifs/dns_resolve.h index 26b9eaa9f5ee..5d7f291df162 100644 --- a/fs/cifs/dns_resolve.h +++ b/fs/cifs/dns_resolve.h @@ -25,7 +25,7 @@ #ifdef __KERNEL__ extern int __init cifs_init_dns_resolver(void); -extern void __exit cifs_exit_dns_resolver(void); +extern void cifs_exit_dns_resolver(void); extern int dns_resolve_server_name_to_ip(const char *unc, char **ip_addr); #endif /* KERNEL */ diff --git a/fs/cifs/file.c b/fs/cifs/file.c index 409e4f523e61..fa04a00d126d 100644 --- a/fs/cifs/file.c +++ b/fs/cifs/file.c @@ -40,6 +40,7 @@ #include "cifs_unicode.h" #include "cifs_debug.h" #include "cifs_fs_sb.h" +#include "fscache.h" static inline int cifs_convert_flags(unsigned int flags) { @@ -282,6 +283,9 @@ int cifs_open(struct inode *inode, struct file *file) CIFSSMBClose(xid, tcon, netfid); rc = -ENOMEM; } + + cifs_fscache_set_inode_cookie(inode, file); + goto out; } else if ((rc == -EINVAL) || (rc == -EOPNOTSUPP)) { if (tcon->ses->serverNOS) @@ -373,6 +377,8 @@ int cifs_open(struct inode *inode, struct file *file) goto out; } + cifs_fscache_set_inode_cookie(inode, file); + if (oplock & CIFS_CREATE_ACTION) { /* time to set mode which we can not set earlier due to problems creating new read-only files */ @@ -427,7 +433,7 @@ static int cifs_reopen_file(struct file *file, bool can_flush) __u16 netfid; if (file->private_data) - pCifsFile = (struct cifsFileInfo *)file->private_data; + pCifsFile = file->private_data; else return -EBADF; @@ -565,8 +571,7 @@ int cifs_close(struct inode *inode, struct file *file) int xid, timeout; struct cifs_sb_info *cifs_sb; struct cifsTconInfo *pTcon; - struct cifsFileInfo *pSMBFile = - (struct cifsFileInfo *)file->private_data; + struct cifsFileInfo *pSMBFile = file->private_data; xid = GetXid(); @@ -641,8 +646,7 @@ int cifs_closedir(struct inode *inode, struct file *file) { int rc = 0; int xid; - struct cifsFileInfo *pCFileStruct = - (struct cifsFileInfo *)file->private_data; + struct cifsFileInfo *pCFileStruct = file->private_data; char *ptmp; cFYI(1, "Closedir inode = 0x%p", inode); @@ -863,8 +867,7 @@ int cifs_lock(struct file *file, int cmd, struct file_lock *pfLock) length, pfLock, posix_lock_type, wait_flag); } else { - struct cifsFileInfo *fid = - (struct cifsFileInfo *)file->private_data; + struct cifsFileInfo *fid = file->private_data; if (numLock) { rc = CIFSSMBLock(xid, tcon, netfid, length, @@ -965,7 +968,7 @@ ssize_t cifs_user_write(struct file *file, const char __user *write_data, if (file->private_data == NULL) return -EBADF; - open_file = (struct cifsFileInfo *) file->private_data; + open_file = file->private_data; rc = generic_write_checks(file, poffset, &write_size, 0); if (rc) @@ -1067,7 +1070,7 @@ static ssize_t cifs_write(struct file *file, const char *write_data, if (file->private_data == NULL) return -EBADF; - open_file = (struct cifsFileInfo *)file->private_data; + open_file = file->private_data; xid = GetXid(); @@ -1651,8 +1654,7 @@ int cifs_fsync(struct file *file, int datasync) int xid; int rc = 0; struct cifsTconInfo *tcon; - struct cifsFileInfo *smbfile = - (struct cifsFileInfo *)file->private_data; + struct cifsFileInfo *smbfile = file->private_data; struct inode *inode = file->f_path.dentry->d_inode; xid = GetXid(); @@ -1756,7 +1758,7 @@ ssize_t cifs_user_read(struct file *file, char __user *read_data, FreeXid(xid); return rc; } - open_file = (struct cifsFileInfo *)file->private_data; + open_file = file->private_data; if ((file->f_flags & O_ACCMODE) == O_WRONLY) cFYI(1, "attempting read on write only file instance"); @@ -1837,7 +1839,7 @@ static ssize_t cifs_read(struct file *file, char *read_data, size_t read_size, FreeXid(xid); return rc; } - open_file = (struct cifsFileInfo *)file->private_data; + open_file = file->private_data; if ((file->f_flags & O_ACCMODE) == O_WRONLY) cFYI(1, "attempting read on write only file instance"); @@ -1942,6 +1944,9 @@ static void cifs_copy_cache_pages(struct address_space *mapping, SetPageUptodate(page); unlock_page(page); data += PAGE_CACHE_SIZE; + + /* add page to FS-Cache */ + cifs_readpage_to_fscache(mapping->host, page); } return; } @@ -1968,10 +1973,19 @@ static int cifs_readpages(struct file *file, struct address_space *mapping, FreeXid(xid); return rc; } - open_file = (struct cifsFileInfo *)file->private_data; + open_file = file->private_data; cifs_sb = CIFS_SB(file->f_path.dentry->d_sb); pTcon = cifs_sb->tcon; + /* + * Reads as many pages as possible from fscache. Returns -ENOBUFS + * immediately if the cookie is negative + */ + rc = cifs_readpages_from_fscache(mapping->host, mapping, page_list, + &num_pages); + if (rc == 0) + goto read_complete; + cFYI(DBG2, "rpages: num pages %d", num_pages); for (i = 0; i < num_pages; ) { unsigned contig_pages; @@ -2082,6 +2096,7 @@ static int cifs_readpages(struct file *file, struct address_space *mapping, smb_read_data = NULL; } +read_complete: FreeXid(xid); return rc; } @@ -2092,6 +2107,11 @@ static int cifs_readpage_worker(struct file *file, struct page *page, char *read_data; int rc; + /* Is the page cached? */ + rc = cifs_readpage_from_fscache(file->f_path.dentry->d_inode, page); + if (rc == 0) + goto read_complete; + page_cache_get(page); read_data = kmap(page); /* for reads over a certain size could initiate async read ahead */ @@ -2111,11 +2131,17 @@ static int cifs_readpage_worker(struct file *file, struct page *page, flush_dcache_page(page); SetPageUptodate(page); + + /* send this page to the cache */ + cifs_readpage_to_fscache(file->f_path.dentry->d_inode, page); + rc = 0; io_error: kunmap(page); page_cache_release(page); + +read_complete: return rc; } @@ -2265,6 +2291,22 @@ out: return rc; } +static int cifs_release_page(struct page *page, gfp_t gfp) +{ + if (PagePrivate(page)) + return 0; + + return cifs_fscache_release_page(page, gfp); +} + +static void cifs_invalidate_page(struct page *page, unsigned long offset) +{ + struct cifsInodeInfo *cifsi = CIFS_I(page->mapping->host); + + if (offset == 0) + cifs_fscache_invalidate_page(page, &cifsi->vfs_inode); +} + static void cifs_oplock_break(struct slow_work *work) { @@ -2338,6 +2380,8 @@ const struct address_space_operations cifs_addr_ops = { .write_begin = cifs_write_begin, .write_end = cifs_write_end, .set_page_dirty = __set_page_dirty_nobuffers, + .releasepage = cifs_release_page, + .invalidatepage = cifs_invalidate_page, /* .sync_page = cifs_sync_page, */ /* .direct_IO = */ }; @@ -2354,6 +2398,8 @@ const struct address_space_operations cifs_addr_ops_smallbuf = { .write_begin = cifs_write_begin, .write_end = cifs_write_end, .set_page_dirty = __set_page_dirty_nobuffers, + .releasepage = cifs_release_page, + .invalidatepage = cifs_invalidate_page, /* .sync_page = cifs_sync_page, */ /* .direct_IO = */ }; diff --git a/fs/cifs/fscache.c b/fs/cifs/fscache.c new file mode 100644 index 000000000000..9f3f5c4be161 --- /dev/null +++ b/fs/cifs/fscache.c @@ -0,0 +1,236 @@ +/* + * fs/cifs/fscache.c - CIFS filesystem cache interface + * + * Copyright (c) 2010 Novell, Inc. + * Author(s): Suresh Jayaraman (sjayaraman@suse.de> + * + * This library is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; either version 2.1 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + * the GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include "fscache.h" +#include "cifsglob.h" +#include "cifs_debug.h" +#include "cifs_fs_sb.h" + +void cifs_fscache_get_client_cookie(struct TCP_Server_Info *server) +{ + server->fscache = + fscache_acquire_cookie(cifs_fscache_netfs.primary_index, + &cifs_fscache_server_index_def, server); + cFYI(1, "CIFS: get client cookie (0x%p/0x%p)", server, + server->fscache); +} + +void cifs_fscache_release_client_cookie(struct TCP_Server_Info *server) +{ + cFYI(1, "CIFS: release client cookie (0x%p/0x%p)", server, + server->fscache); + fscache_relinquish_cookie(server->fscache, 0); + server->fscache = NULL; +} + +void cifs_fscache_get_super_cookie(struct cifsTconInfo *tcon) +{ + struct TCP_Server_Info *server = tcon->ses->server; + + tcon->fscache = + fscache_acquire_cookie(server->fscache, + &cifs_fscache_super_index_def, tcon); + cFYI(1, "CIFS: get superblock cookie (0x%p/0x%p)", + server->fscache, tcon->fscache); +} + +void cifs_fscache_release_super_cookie(struct cifsTconInfo *tcon) +{ + cFYI(1, "CIFS: releasing superblock cookie (0x%p)", tcon->fscache); + fscache_relinquish_cookie(tcon->fscache, 0); + tcon->fscache = NULL; +} + +static void cifs_fscache_enable_inode_cookie(struct inode *inode) +{ + struct cifsInodeInfo *cifsi = CIFS_I(inode); + struct cifs_sb_info *cifs_sb = CIFS_SB(inode->i_sb); + + if (cifsi->fscache) + return; + + cifsi->fscache = fscache_acquire_cookie(cifs_sb->tcon->fscache, + &cifs_fscache_inode_object_def, + cifsi); + cFYI(1, "CIFS: got FH cookie (0x%p/0x%p)", + cifs_sb->tcon->fscache, cifsi->fscache); +} + +void cifs_fscache_release_inode_cookie(struct inode *inode) +{ + struct cifsInodeInfo *cifsi = CIFS_I(inode); + + if (cifsi->fscache) { + cFYI(1, "CIFS releasing inode cookie (0x%p)", + cifsi->fscache); + fscache_relinquish_cookie(cifsi->fscache, 0); + cifsi->fscache = NULL; + } +} + +static void cifs_fscache_disable_inode_cookie(struct inode *inode) +{ + struct cifsInodeInfo *cifsi = CIFS_I(inode); + + if (cifsi->fscache) { + cFYI(1, "CIFS disabling inode cookie (0x%p)", + cifsi->fscache); + fscache_relinquish_cookie(cifsi->fscache, 1); + cifsi->fscache = NULL; + } +} + +void cifs_fscache_set_inode_cookie(struct inode *inode, struct file *filp) +{ + if ((filp->f_flags & O_ACCMODE) != O_RDONLY) + cifs_fscache_disable_inode_cookie(inode); + else { + cifs_fscache_enable_inode_cookie(inode); + cFYI(1, "CIFS: fscache inode cookie set"); + } +} + +void cifs_fscache_reset_inode_cookie(struct inode *inode) +{ + struct cifsInodeInfo *cifsi = CIFS_I(inode); + struct cifs_sb_info *cifs_sb = CIFS_SB(inode->i_sb); + struct fscache_cookie *old = cifsi->fscache; + + if (cifsi->fscache) { + /* retire the current fscache cache and get a new one */ + fscache_relinquish_cookie(cifsi->fscache, 1); + + cifsi->fscache = fscache_acquire_cookie(cifs_sb->tcon->fscache, + &cifs_fscache_inode_object_def, + cifsi); + cFYI(1, "CIFS: new cookie 0x%p oldcookie 0x%p", + cifsi->fscache, old); + } +} + +int cifs_fscache_release_page(struct page *page, gfp_t gfp) +{ + if (PageFsCache(page)) { + struct inode *inode = page->mapping->host; + struct cifsInodeInfo *cifsi = CIFS_I(inode); + + cFYI(1, "CIFS: fscache release page (0x%p/0x%p)", + page, cifsi->fscache); + if (!fscache_maybe_release_page(cifsi->fscache, page, gfp)) + return 0; + } + + return 1; +} + +static void cifs_readpage_from_fscache_complete(struct page *page, void *ctx, + int error) +{ + cFYI(1, "CFS: readpage_from_fscache_complete (0x%p/%d)", + page, error); + if (!error) + SetPageUptodate(page); + unlock_page(page); +} + +/* + * Retrieve a page from FS-Cache + */ +int __cifs_readpage_from_fscache(struct inode *inode, struct page *page) +{ + int ret; + + cFYI(1, "CIFS: readpage_from_fscache(fsc:%p, p:%p, i:0x%p", + CIFS_I(inode)->fscache, page, inode); + ret = fscache_read_or_alloc_page(CIFS_I(inode)->fscache, page, + cifs_readpage_from_fscache_complete, + NULL, + GFP_KERNEL); + switch (ret) { + + case 0: /* page found in fscache, read submitted */ + cFYI(1, "CIFS: readpage_from_fscache: submitted"); + return ret; + case -ENOBUFS: /* page won't be cached */ + case -ENODATA: /* page not in cache */ + cFYI(1, "CIFS: readpage_from_fscache %d", ret); + return 1; + + default: + cERROR(1, "unknown error ret = %d", ret); + } + return ret; +} + +/* + * Retrieve a set of pages from FS-Cache + */ +int __cifs_readpages_from_fscache(struct inode *inode, + struct address_space *mapping, + struct list_head *pages, + unsigned *nr_pages) +{ + int ret; + + cFYI(1, "CIFS: __cifs_readpages_from_fscache (0x%p/%u/0x%p)", + CIFS_I(inode)->fscache, *nr_pages, inode); + ret = fscache_read_or_alloc_pages(CIFS_I(inode)->fscache, mapping, + pages, nr_pages, + cifs_readpage_from_fscache_complete, + NULL, + mapping_gfp_mask(mapping)); + switch (ret) { + case 0: /* read submitted to the cache for all pages */ + cFYI(1, "CIFS: readpages_from_fscache: submitted"); + return ret; + + case -ENOBUFS: /* some pages are not cached and can't be */ + case -ENODATA: /* some pages are not cached */ + cFYI(1, "CIFS: readpages_from_fscache: no page"); + return 1; + + default: + cFYI(1, "unknown error ret = %d", ret); + } + + return ret; +} + +void __cifs_readpage_to_fscache(struct inode *inode, struct page *page) +{ + int ret; + + cFYI(1, "CIFS: readpage_to_fscache(fsc: %p, p: %p, i: %p", + CIFS_I(inode)->fscache, page, inode); + ret = fscache_write_page(CIFS_I(inode)->fscache, page, GFP_KERNEL); + if (ret != 0) + fscache_uncache_page(CIFS_I(inode)->fscache, page); +} + +void __cifs_fscache_invalidate_page(struct page *page, struct inode *inode) +{ + struct cifsInodeInfo *cifsi = CIFS_I(inode); + struct fscache_cookie *cookie = cifsi->fscache; + + cFYI(1, "CIFS: fscache invalidatepage (0x%p/0x%p)", page, cookie); + fscache_wait_on_page_write(cookie, page); + fscache_uncache_page(cookie, page); +} + diff --git a/fs/cifs/fscache.h b/fs/cifs/fscache.h new file mode 100644 index 000000000000..31b88ec2341e --- /dev/null +++ b/fs/cifs/fscache.h @@ -0,0 +1,136 @@ +/* + * fs/cifs/fscache.h - CIFS filesystem cache interface definitions + * + * Copyright (c) 2010 Novell, Inc. + * Authors(s): Suresh Jayaraman (sjayaraman@suse.de> + * + * This library is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; either version 2.1 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + * the GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _CIFS_FSCACHE_H +#define _CIFS_FSCACHE_H + +#include <linux/fscache.h> + +#include "cifsglob.h" + +#ifdef CONFIG_CIFS_FSCACHE + +extern struct fscache_netfs cifs_fscache_netfs; +extern const struct fscache_cookie_def cifs_fscache_server_index_def; +extern const struct fscache_cookie_def cifs_fscache_super_index_def; +extern const struct fscache_cookie_def cifs_fscache_inode_object_def; + +extern int cifs_fscache_register(void); +extern void cifs_fscache_unregister(void); + +/* + * fscache.c + */ +extern void cifs_fscache_get_client_cookie(struct TCP_Server_Info *); +extern void cifs_fscache_release_client_cookie(struct TCP_Server_Info *); +extern void cifs_fscache_get_super_cookie(struct cifsTconInfo *); +extern void cifs_fscache_release_super_cookie(struct cifsTconInfo *); + +extern void cifs_fscache_release_inode_cookie(struct inode *); +extern void cifs_fscache_set_inode_cookie(struct inode *, struct file *); +extern void cifs_fscache_reset_inode_cookie(struct inode *); + +extern void __cifs_fscache_invalidate_page(struct page *, struct inode *); +extern int cifs_fscache_release_page(struct page *page, gfp_t gfp); +extern int __cifs_readpage_from_fscache(struct inode *, struct page *); +extern int __cifs_readpages_from_fscache(struct inode *, + struct address_space *, + struct list_head *, + unsigned *); + +extern void __cifs_readpage_to_fscache(struct inode *, struct page *); + +static inline void cifs_fscache_invalidate_page(struct page *page, + struct inode *inode) +{ + if (PageFsCache(page)) + __cifs_fscache_invalidate_page(page, inode); +} + +static inline int cifs_readpage_from_fscache(struct inode *inode, + struct page *page) +{ + if (CIFS_I(inode)->fscache) + return __cifs_readpage_from_fscache(inode, page); + + return -ENOBUFS; +} + +static inline int cifs_readpages_from_fscache(struct inode *inode, + struct address_space *mapping, + struct list_head *pages, + unsigned *nr_pages) +{ + if (CIFS_I(inode)->fscache) + return __cifs_readpages_from_fscache(inode, mapping, pages, + nr_pages); + return -ENOBUFS; +} + +static inline void cifs_readpage_to_fscache(struct inode *inode, + struct page *page) +{ + if (PageFsCache(page)) + __cifs_readpage_to_fscache(inode, page); +} + +#else /* CONFIG_CIFS_FSCACHE */ +static inline int cifs_fscache_register(void) { return 0; } +static inline void cifs_fscache_unregister(void) {} + +static inline void +cifs_fscache_get_client_cookie(struct TCP_Server_Info *server) {} +static inline void +cifs_fscache_release_client_cookie(struct TCP_Server_Info *server) {} +static inline void cifs_fscache_get_super_cookie(struct cifsTconInfo *tcon) {} +static inline void +cifs_fscache_release_super_cookie(struct cifsTconInfo *tcon) {} + +static inline void cifs_fscache_release_inode_cookie(struct inode *inode) {} +static inline void cifs_fscache_set_inode_cookie(struct inode *inode, + struct file *filp) {} +static inline void cifs_fscache_reset_inode_cookie(struct inode *inode) {} +static inline int cifs_fscache_release_page(struct page *page, gfp_t gfp) +{ + return 1; /* May release page */ +} + +static inline void cifs_fscache_invalidate_page(struct page *page, + struct inode *inode) {} +static inline int +cifs_readpage_from_fscache(struct inode *inode, struct page *page) +{ + return -ENOBUFS; +} + +static inline int cifs_readpages_from_fscache(struct inode *inode, + struct address_space *mapping, + struct list_head *pages, + unsigned *nr_pages) +{ + return -ENOBUFS; +} + +static inline void cifs_readpage_to_fscache(struct inode *inode, + struct page *page) {} + +#endif /* CONFIG_CIFS_FSCACHE */ + +#endif /* _CIFS_FSCACHE_H */ diff --git a/fs/cifs/inode.c b/fs/cifs/inode.c index 6f0683c68952..a15b3a9bbff4 100644 --- a/fs/cifs/inode.c +++ b/fs/cifs/inode.c @@ -29,6 +29,7 @@ #include "cifsproto.h" #include "cifs_debug.h" #include "cifs_fs_sb.h" +#include "fscache.h" static void cifs_set_ops(struct inode *inode, const bool is_dfs_referral) @@ -288,7 +289,7 @@ int cifs_get_file_info_unix(struct file *filp) struct inode *inode = filp->f_path.dentry->d_inode; struct cifs_sb_info *cifs_sb = CIFS_SB(inode->i_sb); struct cifsTconInfo *tcon = cifs_sb->tcon; - struct cifsFileInfo *cfile = (struct cifsFileInfo *) filp->private_data; + struct cifsFileInfo *cfile = filp->private_data; xid = GetXid(); rc = CIFSSMBUnixQFileInfo(xid, tcon, cfile->netfid, &find_data); @@ -515,7 +516,7 @@ int cifs_get_file_info(struct file *filp) struct inode *inode = filp->f_path.dentry->d_inode; struct cifs_sb_info *cifs_sb = CIFS_SB(inode->i_sb); struct cifsTconInfo *tcon = cifs_sb->tcon; - struct cifsFileInfo *cfile = (struct cifsFileInfo *) filp->private_data; + struct cifsFileInfo *cfile = filp->private_data; xid = GetXid(); rc = CIFSSMBQFileInfo(xid, tcon, cfile->netfid, &find_data); @@ -723,9 +724,14 @@ cifs_find_inode(struct inode *inode, void *opaque) { struct cifs_fattr *fattr = (struct cifs_fattr *) opaque; + /* don't match inode with different uniqueid */ if (CIFS_I(inode)->uniqueid != fattr->cf_uniqueid) return 0; + /* don't match inode of different type */ + if ((inode->i_mode & S_IFMT) != (fattr->cf_mode & S_IFMT)) + return 0; + /* * uh oh -- it's a directory. We can't use it since hardlinked dirs are * verboten. Disable serverino and return it as if it were found, the @@ -776,6 +782,10 @@ retry_iget5_locked: inode->i_flags |= S_NOATIME | S_NOCMTIME; if (inode->i_state & I_NEW) { inode->i_ino = hash; +#ifdef CONFIG_CIFS_FSCACHE + /* initialize per-inode cache cookie pointer */ + CIFS_I(inode)->fscache = NULL; +#endif unlock_new_inode(inode); } } @@ -807,6 +817,11 @@ struct inode *cifs_root_iget(struct super_block *sb, unsigned long ino) if (!inode) return ERR_PTR(-ENOMEM); +#ifdef CONFIG_CIFS_FSCACHE + /* populate tcon->resource_id */ + cifs_sb->tcon->resource_id = CIFS_I(inode)->uniqueid; +#endif + if (rc && cifs_sb->tcon->ipc) { cFYI(1, "ipc connection - fake read inode"); inode->i_mode |= S_IFDIR; @@ -1568,6 +1583,7 @@ cifs_invalidate_mapping(struct inode *inode) cifs_i->write_behind_rc = rc; } invalidate_remote_inode(inode); + cifs_fscache_reset_inode_cookie(inode); } int cifs_revalidate_file(struct file *filp) diff --git a/fs/cifs/ioctl.c b/fs/cifs/ioctl.c index 505926f1ee6b..9d38a71c8e14 100644 --- a/fs/cifs/ioctl.c +++ b/fs/cifs/ioctl.c @@ -41,8 +41,7 @@ long cifs_ioctl(struct file *filep, unsigned int command, unsigned long arg) __u64 ExtAttrMask = 0; __u64 caps; struct cifsTconInfo *tcon; - struct cifsFileInfo *pSMBFile = - (struct cifsFileInfo *)filep->private_data; + struct cifsFileInfo *pSMBFile = filep->private_data; #endif /* CONFIG_CIFS_POSIX */ xid = GetXid(); diff --git a/fs/cifs/netmisc.c b/fs/cifs/netmisc.c index d35d52889cb5..c6721ee26dbc 100644 --- a/fs/cifs/netmisc.c +++ b/fs/cifs/netmisc.c @@ -61,6 +61,7 @@ static const struct smb_to_posix_error mapping_table_ERRDOS[] = { {ERRremcd, -EACCES}, {ERRdiffdevice, -EXDEV}, {ERRnofiles, -ENOENT}, + {ERRwriteprot, -EROFS}, {ERRbadshare, -ETXTBSY}, {ERRlock, -EACCES}, {ERRunsup, -EINVAL}, @@ -164,7 +165,7 @@ cifs_inet_pton(const int address_family, const char *cp, void *dst) * Returns 0 on failure. */ int -cifs_convert_address(char *src, void *dst) +cifs_convert_address(struct sockaddr *dst, char *src) { int rc; char *pct, *endp; @@ -201,6 +202,27 @@ cifs_convert_address(char *src, void *dst) return rc; } +int +cifs_fill_sockaddr(struct sockaddr *dst, char *src, + const unsigned short int port) +{ + if (!cifs_convert_address(dst, src)) + return 0; + + switch (dst->sa_family) { + case AF_INET: + ((struct sockaddr_in *)dst)->sin_port = htons(port); + break; + case AF_INET6: + ((struct sockaddr_in6 *)dst)->sin6_port = htons(port); + break; + default: + return 0; + } + + return 1; +} + /***************************************************************************** convert a NT status code to a dos class/code *****************************************************************************/ diff --git a/fs/cifs/readdir.c b/fs/cifs/readdir.c index daf1753af674..d5e591fab475 100644 --- a/fs/cifs/readdir.c +++ b/fs/cifs/readdir.c @@ -847,6 +847,11 @@ int cifs_readdir(struct file *file, void *direntry, filldir_t filldir) end_of_smb = cifsFile->srch_inf.ntwrk_buf_start + max_len; tmp_buf = kmalloc(UNICODE_NAME_MAX, GFP_KERNEL); + if (tmp_buf == NULL) { + rc = -ENOMEM; + break; + } + for (i = 0; (i < num_to_fill) && (rc == 0); i++) { if (current_entry == NULL) { /* evaluate whether this case is an error */ diff --git a/fs/cifs/smberr.h b/fs/cifs/smberr.h index c5084d27db7c..7f16cb825fe5 100644 --- a/fs/cifs/smberr.h +++ b/fs/cifs/smberr.h @@ -76,6 +76,7 @@ #define ERRnofiles 18 /* A File Search command can find no more files matching the specified criteria. */ +#define ERRwriteprot 19 /* media is write protected */ #define ERRgeneral 31 #define ERRbadshare 32 /* The sharing mode specified for an Open conflicts with existing FIDs on diff --git a/fs/direct-io.c b/fs/direct-io.c index 7600aacf531d..a10cb91cadea 100644 --- a/fs/direct-io.c +++ b/fs/direct-io.c @@ -218,7 +218,7 @@ static struct page *dio_get_page(struct dio *dio) * filesystems can use it to hold additional state between get_block calls and * dio_complete. */ -static int dio_complete(struct dio *dio, loff_t offset, int ret) +static int dio_complete(struct dio *dio, loff_t offset, int ret, bool is_async) { ssize_t transferred = 0; @@ -239,14 +239,6 @@ static int dio_complete(struct dio *dio, loff_t offset, int ret) transferred = dio->i_size - offset; } - if (dio->end_io && dio->result) - dio->end_io(dio->iocb, offset, transferred, - dio->map_bh.b_private); - - if (dio->flags & DIO_LOCKING) - /* lockdep: non-owner release */ - up_read_non_owner(&dio->inode->i_alloc_sem); - if (ret == 0) ret = dio->page_errors; if (ret == 0) @@ -254,6 +246,17 @@ static int dio_complete(struct dio *dio, loff_t offset, int ret) if (ret == 0) ret = transferred; + if (dio->end_io && dio->result) { + dio->end_io(dio->iocb, offset, transferred, + dio->map_bh.b_private, ret, is_async); + } else if (is_async) { + aio_complete(dio->iocb, ret, 0); + } + + if (dio->flags & DIO_LOCKING) + /* lockdep: non-owner release */ + up_read_non_owner(&dio->inode->i_alloc_sem); + return ret; } @@ -277,8 +280,7 @@ static void dio_bio_end_aio(struct bio *bio, int error) spin_unlock_irqrestore(&dio->bio_lock, flags); if (remaining == 0) { - int ret = dio_complete(dio, dio->iocb->ki_pos, 0); - aio_complete(dio->iocb, ret, 0); + dio_complete(dio, dio->iocb->ki_pos, 0, true); kfree(dio); } } @@ -1126,7 +1128,7 @@ direct_io_worker(int rw, struct kiocb *iocb, struct inode *inode, spin_unlock_irqrestore(&dio->bio_lock, flags); if (ret2 == 0) { - ret = dio_complete(dio, offset, ret); + ret = dio_complete(dio, offset, ret, false); kfree(dio); } else BUG_ON(ret != -EIOCBQUEUED); diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c index 42272d67955a..0afc8c1d8cf3 100644 --- a/fs/ext4/inode.c +++ b/fs/ext4/inode.c @@ -3775,7 +3775,8 @@ static ext4_io_end_t *ext4_init_io_end (struct inode *inode, gfp_t flags) } static void ext4_end_io_dio(struct kiocb *iocb, loff_t offset, - ssize_t size, void *private) + ssize_t size, void *private, int ret, + bool is_async) { ext4_io_end_t *io_end = iocb->private; struct workqueue_struct *wq; @@ -3784,7 +3785,7 @@ static void ext4_end_io_dio(struct kiocb *iocb, loff_t offset, /* if not async direct IO or dio with 0 bytes write, just return */ if (!io_end || !size) - return; + goto out; ext_debug("ext4_end_io_dio(): io_end 0x%p" "for inode %lu, iocb 0x%p, offset %llu, size %llu\n", @@ -3795,7 +3796,7 @@ static void ext4_end_io_dio(struct kiocb *iocb, loff_t offset, if (io_end->flag != EXT4_IO_UNWRITTEN){ ext4_free_io_end(io_end); iocb->private = NULL; - return; + goto out; } io_end->offset = offset; @@ -3812,6 +3813,9 @@ static void ext4_end_io_dio(struct kiocb *iocb, loff_t offset, list_add_tail(&io_end->list, &ei->i_completed_io_list); spin_unlock_irqrestore(&ei->i_completed_io_lock, flags); iocb->private = NULL; +out: + if (is_async) + aio_complete(iocb, ret, 0); } static void ext4_end_io_buffer_write(struct buffer_head *bh, int uptodate) diff --git a/fs/nfs/file.c b/fs/nfs/file.c index 36a5e74f51b4..f036153d9f50 100644 --- a/fs/nfs/file.c +++ b/fs/nfs/file.c @@ -27,6 +27,7 @@ #include <linux/pagemap.h> #include <linux/aio.h> #include <linux/gfp.h> +#include <linux/swap.h> #include <asm/uaccess.h> #include <asm/system.h> @@ -493,11 +494,19 @@ static void nfs_invalidate_page(struct page *page, unsigned long offset) */ static int nfs_release_page(struct page *page, gfp_t gfp) { + struct address_space *mapping = page->mapping; + dfprintk(PAGECACHE, "NFS: release_page(%p)\n", page); /* Only do I/O if gfp is a superset of GFP_KERNEL */ - if ((gfp & GFP_KERNEL) == GFP_KERNEL) - nfs_wb_page(page->mapping->host, page); + if (mapping && (gfp & GFP_KERNEL) == GFP_KERNEL) { + int how = FLUSH_SYNC; + + /* Don't let kswapd deadlock waiting for OOM RPC calls */ + if (current_is_kswapd()) + how = 0; + nfs_commit_inode(mapping->host, how); + } /* If PagePrivate() is set, then the page is not freeable */ if (PagePrivate(page)) return 0; diff --git a/fs/nfs/nfsroot.c b/fs/nfs/nfsroot.c index 6bd19d843af7..df101d9f546a 100644 --- a/fs/nfs/nfsroot.c +++ b/fs/nfs/nfsroot.c @@ -105,7 +105,7 @@ static char nfs_root_name[256] __initdata = ""; static __be32 servaddr __initdata = 0; /* Name of directory to mount */ -static char nfs_export_path[NFS_MAXPATHLEN] __initdata = { 0, }; +static char nfs_export_path[NFS_MAXPATHLEN + 1] __initdata = { 0, }; /* NFS-related data */ static struct nfs_mount_data nfs_data __initdata = { 0, };/* NFS mount info */ diff --git a/fs/nfs/write.c b/fs/nfs/write.c index 91679e2631ee..9f81bdd91c55 100644 --- a/fs/nfs/write.c +++ b/fs/nfs/write.c @@ -222,7 +222,7 @@ static void nfs_end_page_writeback(struct page *page) clear_bdi_congested(&nfss->backing_dev_info, BLK_RW_ASYNC); } -static struct nfs_page *nfs_find_and_lock_request(struct page *page) +static struct nfs_page *nfs_find_and_lock_request(struct page *page, bool nonblock) { struct inode *inode = page->mapping->host; struct nfs_page *req; @@ -241,7 +241,10 @@ static struct nfs_page *nfs_find_and_lock_request(struct page *page) * request as dirty (in which case we don't care). */ spin_unlock(&inode->i_lock); - ret = nfs_wait_on_request(req); + if (!nonblock) + ret = nfs_wait_on_request(req); + else + ret = -EAGAIN; nfs_release_request(req); if (ret != 0) return ERR_PTR(ret); @@ -256,12 +259,12 @@ static struct nfs_page *nfs_find_and_lock_request(struct page *page) * May return an error if the user signalled nfs_wait_on_request(). */ static int nfs_page_async_flush(struct nfs_pageio_descriptor *pgio, - struct page *page) + struct page *page, bool nonblock) { struct nfs_page *req; int ret = 0; - req = nfs_find_and_lock_request(page); + req = nfs_find_and_lock_request(page, nonblock); if (!req) goto out; ret = PTR_ERR(req); @@ -283,12 +286,20 @@ out: static int nfs_do_writepage(struct page *page, struct writeback_control *wbc, struct nfs_pageio_descriptor *pgio) { struct inode *inode = page->mapping->host; + int ret; nfs_inc_stats(inode, NFSIOS_VFSWRITEPAGE); nfs_add_stats(inode, NFSIOS_WRITEPAGES, 1); nfs_pageio_cond_complete(pgio, page->index); - return nfs_page_async_flush(pgio, page); + ret = nfs_page_async_flush(pgio, page, + wbc->sync_mode == WB_SYNC_NONE || + wbc->nonblocking != 0); + if (ret == -EAGAIN) { + redirty_page_for_writepage(wbc, page); + ret = 0; + } + return ret; } /* @@ -1379,7 +1390,7 @@ static const struct rpc_call_ops nfs_commit_ops = { .rpc_release = nfs_commit_release, }; -static int nfs_commit_inode(struct inode *inode, int how) +int nfs_commit_inode(struct inode *inode, int how) { LIST_HEAD(head); int may_wait = how & FLUSH_SYNC; @@ -1443,11 +1454,6 @@ out_mark_dirty: return ret; } #else -static int nfs_commit_inode(struct inode *inode, int how) -{ - return 0; -} - static int nfs_commit_unstable_pages(struct inode *inode, struct writeback_control *wbc) { return 0; @@ -1546,7 +1552,7 @@ int nfs_migrate_page(struct address_space *mapping, struct page *newpage, nfs_fscache_release_page(page, GFP_KERNEL); - req = nfs_find_and_lock_request(page); + req = nfs_find_and_lock_request(page, false); ret = PTR_ERR(req); if (IS_ERR(req)) goto out; diff --git a/fs/ocfs2/aops.c b/fs/ocfs2/aops.c index 356e976772bf..96337a4fbbdf 100644 --- a/fs/ocfs2/aops.c +++ b/fs/ocfs2/aops.c @@ -578,7 +578,9 @@ bail: static void ocfs2_dio_end_io(struct kiocb *iocb, loff_t offset, ssize_t bytes, - void *private) + void *private, + int ret, + bool is_async) { struct inode *inode = iocb->ki_filp->f_path.dentry->d_inode; int level; @@ -592,6 +594,9 @@ static void ocfs2_dio_end_io(struct kiocb *iocb, if (!level) up_read(&inode->i_alloc_sem); ocfs2_rw_unlock(inode, level); + + if (is_async) + aio_complete(iocb, ret, 0); } /* diff --git a/fs/proc/array.c b/fs/proc/array.c index 9b58d38bc911..fff6572676ae 100644 --- a/fs/proc/array.c +++ b/fs/proc/array.c @@ -176,7 +176,7 @@ static inline void task_state(struct seq_file *m, struct pid_namespace *ns, if (tracer) tpid = task_pid_nr_ns(tracer, ns); } - cred = get_cred((struct cred *) __task_cred(p)); + cred = get_task_cred(p); seq_printf(m, "State:\t%s\n" "Tgid:\t%d\n" diff --git a/fs/ubifs/lpt.c b/fs/ubifs/lpt.c index ad7f67b827ea..0084a33c4c69 100644 --- a/fs/ubifs/lpt.c +++ b/fs/ubifs/lpt.c @@ -1457,13 +1457,13 @@ struct ubifs_lprops *ubifs_lpt_lookup(struct ubifs_info *c, int lnum) shft -= UBIFS_LPT_FANOUT_SHIFT; nnode = ubifs_get_nnode(c, nnode, iip); if (IS_ERR(nnode)) - return ERR_PTR(PTR_ERR(nnode)); + return ERR_CAST(nnode); } iip = ((i >> shft) & (UBIFS_LPT_FANOUT - 1)); shft -= UBIFS_LPT_FANOUT_SHIFT; pnode = ubifs_get_pnode(c, nnode, iip); if (IS_ERR(pnode)) - return ERR_PTR(PTR_ERR(pnode)); + return ERR_CAST(pnode); iip = (i & (UBIFS_LPT_FANOUT - 1)); dbg_lp("LEB %d, free %d, dirty %d, flags %d", lnum, pnode->lprops[iip].free, pnode->lprops[iip].dirty, @@ -1586,7 +1586,7 @@ struct ubifs_lprops *ubifs_lpt_lookup_dirty(struct ubifs_info *c, int lnum) nnode = c->nroot; nnode = dirty_cow_nnode(c, nnode); if (IS_ERR(nnode)) - return ERR_PTR(PTR_ERR(nnode)); + return ERR_CAST(nnode); i = lnum - c->main_first; shft = c->lpt_hght * UBIFS_LPT_FANOUT_SHIFT; for (h = 1; h < c->lpt_hght; h++) { @@ -1594,19 +1594,19 @@ struct ubifs_lprops *ubifs_lpt_lookup_dirty(struct ubifs_info *c, int lnum) shft -= UBIFS_LPT_FANOUT_SHIFT; nnode = ubifs_get_nnode(c, nnode, iip); if (IS_ERR(nnode)) - return ERR_PTR(PTR_ERR(nnode)); + return ERR_CAST(nnode); nnode = dirty_cow_nnode(c, nnode); if (IS_ERR(nnode)) - return ERR_PTR(PTR_ERR(nnode)); + return ERR_CAST(nnode); } iip = ((i >> shft) & (UBIFS_LPT_FANOUT - 1)); shft -= UBIFS_LPT_FANOUT_SHIFT; pnode = ubifs_get_pnode(c, nnode, iip); if (IS_ERR(pnode)) - return ERR_PTR(PTR_ERR(pnode)); + return ERR_CAST(pnode); pnode = dirty_cow_pnode(c, pnode); if (IS_ERR(pnode)) - return ERR_PTR(PTR_ERR(pnode)); + return ERR_CAST(pnode); iip = (i & (UBIFS_LPT_FANOUT - 1)); dbg_lp("LEB %d, free %d, dirty %d, flags %d", lnum, pnode->lprops[iip].free, pnode->lprops[iip].dirty, diff --git a/fs/ubifs/lpt_commit.c b/fs/ubifs/lpt_commit.c index 13cb7a4237bf..d12535b7fc78 100644 --- a/fs/ubifs/lpt_commit.c +++ b/fs/ubifs/lpt_commit.c @@ -646,7 +646,7 @@ static struct ubifs_pnode *pnode_lookup(struct ubifs_info *c, int i) shft -= UBIFS_LPT_FANOUT_SHIFT; nnode = ubifs_get_nnode(c, nnode, iip); if (IS_ERR(nnode)) - return ERR_PTR(PTR_ERR(nnode)); + return ERR_CAST(nnode); } iip = ((i >> shft) & (UBIFS_LPT_FANOUT - 1)); return ubifs_get_pnode(c, nnode, iip); diff --git a/fs/ubifs/recovery.c b/fs/ubifs/recovery.c index 109c6ea03bb5..daae9e1f5382 100644 --- a/fs/ubifs/recovery.c +++ b/fs/ubifs/recovery.c @@ -24,7 +24,7 @@ * This file implements functions needed to recover from unclean un-mounts. * When UBIFS is mounted, it checks a flag on the master node to determine if * an un-mount was completed successfully. If not, the process of mounting - * incorparates additional checking and fixing of on-flash data structures. + * incorporates additional checking and fixing of on-flash data structures. * UBIFS always cleans away all remnants of an unclean un-mount, so that * errors do not accumulate. However UBIFS defers recovery if it is mounted * read-only, and the flash is not modified in that case. @@ -1063,8 +1063,21 @@ int ubifs_rcvry_gc_commit(struct ubifs_info *c) } err = ubifs_find_dirty_leb(c, &lp, wbuf->offs, 2); if (err) { - if (err == -ENOSPC) - dbg_err("could not find a dirty LEB"); + /* + * There are no dirty or empty LEBs subject to here being + * enough for the index. Try to use + * 'ubifs_find_free_leb_for_idx()', which will return any empty + * LEBs (ignoring index requirements). If the index then + * doesn't have enough LEBs the recovery commit will fail - + * which is the same result anyway i.e. recovery fails. So + * there is no problem ignoring index requirements and just + * grabbing a free LEB since we have already established there + * is not a dirty LEB we could have used instead. + */ + if (err == -ENOSPC) { + dbg_rcvry("could not find a dirty LEB"); + goto find_free; + } return err; } ubifs_assert(!(lp.flags & LPROPS_INDEX)); @@ -1139,8 +1152,8 @@ int ubifs_rcvry_gc_commit(struct ubifs_info *c) find_free: /* * There is no GC head LEB or the free space in the GC head LEB is too - * small. Allocate gc_lnum by calling 'ubifs_find_free_leb_for_idx()' so - * GC is not run. + * small, or there are not dirty LEBs. Allocate gc_lnum by calling + * 'ubifs_find_free_leb_for_idx()' so GC is not run. */ lnum = ubifs_find_free_leb_for_idx(c); if (lnum < 0) { diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index 4d2f2157dd3f..5fc5a0988970 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -1307,6 +1307,8 @@ static int mount_ubifs(struct ubifs_info *c) if (err) goto out_orphans; err = ubifs_rcvry_gc_commit(c); + if (err) + goto out_orphans; } else { err = take_gc_lnum(c); if (err) @@ -1318,7 +1320,7 @@ static int mount_ubifs(struct ubifs_info *c) */ err = ubifs_leb_unmap(c, c->gc_lnum); if (err) - return err; + goto out_orphans; } err = dbg_check_lprops(c); diff --git a/fs/xfs/Makefile b/fs/xfs/Makefile index c8fb13f83b3f..0dce969d6cad 100644 --- a/fs/xfs/Makefile +++ b/fs/xfs/Makefile @@ -87,11 +87,9 @@ xfs-y += xfs_alloc.o \ xfs_trans_buf.o \ xfs_trans_extfree.o \ xfs_trans_inode.o \ - xfs_trans_item.o \ xfs_utils.o \ xfs_vnodeops.o \ - xfs_rw.o \ - xfs_dmops.o + xfs_rw.o xfs-$(CONFIG_XFS_TRACE) += xfs_btree_trace.o diff --git a/fs/xfs/linux-2.6/xfs_acl.c b/fs/xfs/linux-2.6/xfs_acl.c index 9f769b5b38fc..b2771862fd3d 100644 --- a/fs/xfs/linux-2.6/xfs_acl.c +++ b/fs/xfs/linux-2.6/xfs_acl.c @@ -225,7 +225,7 @@ xfs_check_acl(struct inode *inode, int mask) struct posix_acl *acl; int error = -EAGAIN; - xfs_itrace_entry(ip); + trace_xfs_check_acl(ip); /* * If there is no attribute fork no ACL exists on this inode and diff --git a/fs/xfs/linux-2.6/xfs_aops.c b/fs/xfs/linux-2.6/xfs_aops.c index 34640d6dbdcb..d24e78f32f3e 100644 --- a/fs/xfs/linux-2.6/xfs_aops.c +++ b/fs/xfs/linux-2.6/xfs_aops.c @@ -21,19 +21,12 @@ #include "xfs_inum.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" #include "xfs_trans.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_alloc.h" -#include "xfs_btree.h" #include "xfs_error.h" #include "xfs_rw.h" #include "xfs_iomap.h" @@ -92,18 +85,15 @@ void xfs_count_page_state( struct page *page, int *delalloc, - int *unmapped, int *unwritten) { struct buffer_head *bh, *head; - *delalloc = *unmapped = *unwritten = 0; + *delalloc = *unwritten = 0; bh = head = page_buffers(page); do { - if (buffer_uptodate(bh) && !buffer_mapped(bh)) - (*unmapped) = 1; - else if (buffer_unwritten(bh)) + if (buffer_unwritten(bh)) (*unwritten) = 1; else if (buffer_delay(bh)) (*delalloc) = 1; @@ -212,23 +202,17 @@ xfs_setfilesize( } /* - * Schedule IO completion handling on a xfsdatad if this was - * the final hold on this ioend. If we are asked to wait, - * flush the workqueue. + * Schedule IO completion handling on the final put of an ioend. */ STATIC void xfs_finish_ioend( - xfs_ioend_t *ioend, - int wait) + struct xfs_ioend *ioend) { if (atomic_dec_and_test(&ioend->io_remaining)) { - struct workqueue_struct *wq; - - wq = (ioend->io_type == IO_UNWRITTEN) ? - xfsconvertd_workqueue : xfsdatad_workqueue; - queue_work(wq, &ioend->io_work); - if (wait) - flush_workqueue(wq); + if (ioend->io_type == IO_UNWRITTEN) + queue_work(xfsconvertd_workqueue, &ioend->io_work); + else + queue_work(xfsdatad_workqueue, &ioend->io_work); } } @@ -272,11 +256,25 @@ xfs_end_io( */ if (error == EAGAIN) { atomic_inc(&ioend->io_remaining); - xfs_finish_ioend(ioend, 0); + xfs_finish_ioend(ioend); /* ensure we don't spin on blocked ioends */ delay(1); - } else + } else { + if (ioend->io_iocb) + aio_complete(ioend->io_iocb, ioend->io_result, 0); xfs_destroy_ioend(ioend); + } +} + +/* + * Call IO completion handling in caller context on the final put of an ioend. + */ +STATIC void +xfs_finish_ioend_sync( + struct xfs_ioend *ioend) +{ + if (atomic_dec_and_test(&ioend->io_remaining)) + xfs_end_io(&ioend->io_work); } /* @@ -309,6 +307,8 @@ xfs_alloc_ioend( atomic_inc(&XFS_I(ioend->io_inode)->i_iocount); ioend->io_offset = 0; ioend->io_size = 0; + ioend->io_iocb = NULL; + ioend->io_result = 0; INIT_WORK(&ioend->io_work, xfs_end_io); return ioend; @@ -358,7 +358,7 @@ xfs_end_bio( bio->bi_end_io = NULL; bio_put(bio); - xfs_finish_ioend(ioend, 0); + xfs_finish_ioend(ioend); } STATIC void @@ -500,7 +500,7 @@ xfs_submit_ioend( } if (bio) xfs_submit_ioend_bio(wbc, ioend, bio); - xfs_finish_ioend(ioend, 0); + xfs_finish_ioend(ioend); } while ((ioend = next) != NULL); } @@ -614,31 +614,30 @@ xfs_map_at_offset( STATIC unsigned int xfs_probe_page( struct page *page, - unsigned int pg_offset, - int mapped) + unsigned int pg_offset) { + struct buffer_head *bh, *head; int ret = 0; if (PageWriteback(page)) return 0; + if (!PageDirty(page)) + return 0; + if (!page->mapping) + return 0; + if (!page_has_buffers(page)) + return 0; - if (page->mapping && PageDirty(page)) { - if (page_has_buffers(page)) { - struct buffer_head *bh, *head; - - bh = head = page_buffers(page); - do { - if (!buffer_uptodate(bh)) - break; - if (mapped != buffer_mapped(bh)) - break; - ret += bh->b_size; - if (ret >= pg_offset) - break; - } while ((bh = bh->b_this_page) != head); - } else - ret = mapped ? 0 : PAGE_CACHE_SIZE; - } + bh = head = page_buffers(page); + do { + if (!buffer_uptodate(bh)) + break; + if (!buffer_mapped(bh)) + break; + ret += bh->b_size; + if (ret >= pg_offset) + break; + } while ((bh = bh->b_this_page) != head); return ret; } @@ -648,8 +647,7 @@ xfs_probe_cluster( struct inode *inode, struct page *startpage, struct buffer_head *bh, - struct buffer_head *head, - int mapped) + struct buffer_head *head) { struct pagevec pvec; pgoff_t tindex, tlast, tloff; @@ -658,7 +656,7 @@ xfs_probe_cluster( /* First sum forwards in this page */ do { - if (!buffer_uptodate(bh) || (mapped != buffer_mapped(bh))) + if (!buffer_uptodate(bh) || !buffer_mapped(bh)) return total; total += bh->b_size; } while ((bh = bh->b_this_page) != head); @@ -692,7 +690,7 @@ xfs_probe_cluster( pg_offset = PAGE_CACHE_SIZE; if (page->index == tindex && trylock_page(page)) { - pg_len = xfs_probe_page(page, pg_offset, mapped); + pg_len = xfs_probe_page(page, pg_offset); unlock_page(page); } @@ -761,7 +759,6 @@ xfs_convert_page( struct xfs_bmbt_irec *imap, xfs_ioend_t **ioendp, struct writeback_control *wbc, - int startio, int all_bh) { struct buffer_head *bh, *head; @@ -832,19 +829,14 @@ xfs_convert_page( ASSERT(imap->br_startblock != DELAYSTARTBLOCK); xfs_map_at_offset(inode, bh, imap, offset); - if (startio) { - xfs_add_to_ioend(inode, bh, offset, - type, ioendp, done); - } else { - set_buffer_dirty(bh); - unlock_buffer(bh); - mark_buffer_dirty(bh); - } + xfs_add_to_ioend(inode, bh, offset, type, + ioendp, done); + page_dirty--; count++; } else { type = IO_NEW; - if (buffer_mapped(bh) && all_bh && startio) { + if (buffer_mapped(bh) && all_bh) { lock_buffer(bh); xfs_add_to_ioend(inode, bh, offset, type, ioendp, done); @@ -859,14 +851,12 @@ xfs_convert_page( if (uptodate && bh == head) SetPageUptodate(page); - if (startio) { - if (count) { - wbc->nr_to_write--; - if (wbc->nr_to_write <= 0) - done = 1; - } - xfs_start_page_writeback(page, !page_dirty, count); + if (count) { + wbc->nr_to_write--; + if (wbc->nr_to_write <= 0) + done = 1; } + xfs_start_page_writeback(page, !page_dirty, count); return done; fail_unlock_page: @@ -886,7 +876,6 @@ xfs_cluster_write( struct xfs_bmbt_irec *imap, xfs_ioend_t **ioendp, struct writeback_control *wbc, - int startio, int all_bh, pgoff_t tlast) { @@ -902,7 +891,7 @@ xfs_cluster_write( for (i = 0; i < pagevec_count(&pvec); i++) { done = xfs_convert_page(inode, pvec.pages[i], tindex++, - imap, ioendp, wbc, startio, all_bh); + imap, ioendp, wbc, all_bh); if (done) break; } @@ -981,7 +970,7 @@ xfs_aops_discard_page( */ error = xfs_bmapi(NULL, ip, offset_fsb, 1, XFS_BMAPI_ENTIRE, NULL, 0, &imap, - &nimaps, NULL, NULL); + &nimaps, NULL); if (error) { /* something screwed, just bail */ @@ -1009,7 +998,7 @@ xfs_aops_discard_page( */ xfs_bmap_init(&flist, &firstblock); error = xfs_bunmapi(NULL, ip, offset_fsb, 1, 0, 1, &firstblock, - &flist, NULL, &done); + &flist, &done); ASSERT(!flist.xbf_count && !flist.xbf_first); if (error) { @@ -1032,50 +1021,66 @@ out_invalidate: } /* - * Calling this without startio set means we are being asked to make a dirty - * page ready for freeing it's buffers. When called with startio set then - * we are coming from writepage. + * Write out a dirty page. + * + * For delalloc space on the page we need to allocate space and flush it. + * For unwritten space on the page we need to start the conversion to + * regular allocated space. + * For any other dirty buffer heads on the page we should flush them. * - * When called with startio set it is important that we write the WHOLE - * page if possible. - * The bh->b_state's cannot know if any of the blocks or which block for - * that matter are dirty due to mmap writes, and therefore bh uptodate is - * only valid if the page itself isn't completely uptodate. Some layers - * may clear the page dirty flag prior to calling write page, under the - * assumption the entire page will be written out; by not writing out the - * whole page the page can be reused before all valid dirty data is - * written out. Note: in the case of a page that has been dirty'd by - * mapwrite and but partially setup by block_prepare_write the - * bh->b_states's will not agree and only ones setup by BPW/BCW will have - * valid state, thus the whole page must be written out thing. + * If we detect that a transaction would be required to flush the page, we + * have to check the process flags first, if we are already in a transaction + * or disk I/O during allocations is off, we need to fail the writepage and + * redirty the page. */ - STATIC int -xfs_page_state_convert( - struct inode *inode, - struct page *page, - struct writeback_control *wbc, - int startio, - int unmapped) /* also implies page uptodate */ +xfs_vm_writepage( + struct page *page, + struct writeback_control *wbc) { + struct inode *inode = page->mapping->host; + int delalloc, unwritten; struct buffer_head *bh, *head; struct xfs_bmbt_irec imap; xfs_ioend_t *ioend = NULL, *iohead = NULL; loff_t offset; - unsigned long p_offset = 0; unsigned int type; __uint64_t end_offset; pgoff_t end_index, last_index; ssize_t size, len; int flags, err, imap_valid = 0, uptodate = 1; - int page_dirty, count = 0; - int trylock = 0; - int all_bh = unmapped; + int count = 0; + int all_bh = 0; - if (startio) { - if (wbc->sync_mode == WB_SYNC_NONE && wbc->nonblocking) - trylock |= BMAPI_TRYLOCK; - } + trace_xfs_writepage(inode, page, 0); + + ASSERT(page_has_buffers(page)); + + /* + * Refuse to write the page out if we are called from reclaim context. + * + * This avoids stack overflows when called from deeply used stacks in + * random callers for direct reclaim or memcg reclaim. We explicitly + * allow reclaim from kswapd as the stack usage there is relatively low. + * + * This should really be done by the core VM, but until that happens + * filesystems like XFS, btrfs and ext4 have to take care of this + * by themselves. + */ + if ((current->flags & (PF_MEMALLOC|PF_KSWAPD)) == PF_MEMALLOC) + goto out_fail; + + /* + * We need a transaction if there are delalloc or unwritten buffers + * on the page. + * + * If we need a transaction and the process flags say we are already + * in a transaction, or no IO is allowed then mark the page dirty + * again and leave the page as is. + */ + xfs_count_page_state(page, &delalloc, &unwritten); + if ((current->flags & PF_FSTRANS) && (delalloc || unwritten)) + goto out_fail; /* Is this page beyond the end of the file? */ offset = i_size_read(inode); @@ -1084,50 +1089,33 @@ xfs_page_state_convert( if (page->index >= end_index) { if ((page->index >= end_index + 1) || !(i_size_read(inode) & (PAGE_CACHE_SIZE - 1))) { - if (startio) - unlock_page(page); + unlock_page(page); return 0; } } - /* - * page_dirty is initially a count of buffers on the page before - * EOF and is decremented as we move each into a cleanable state. - * - * Derivation: - * - * End offset is the highest offset that this page should represent. - * If we are on the last page, (end_offset & (PAGE_CACHE_SIZE - 1)) - * will evaluate non-zero and be less than PAGE_CACHE_SIZE and - * hence give us the correct page_dirty count. On any other page, - * it will be zero and in that case we need page_dirty to be the - * count of buffers on the page. - */ end_offset = min_t(unsigned long long, - (xfs_off_t)(page->index + 1) << PAGE_CACHE_SHIFT, offset); + (xfs_off_t)(page->index + 1) << PAGE_CACHE_SHIFT, + offset); len = 1 << inode->i_blkbits; - p_offset = min_t(unsigned long, end_offset & (PAGE_CACHE_SIZE - 1), - PAGE_CACHE_SIZE); - p_offset = p_offset ? roundup(p_offset, len) : PAGE_CACHE_SIZE; - page_dirty = p_offset / len; bh = head = page_buffers(page); offset = page_offset(page); flags = BMAPI_READ; type = IO_NEW; - /* TODO: cleanup count and page_dirty */ - do { if (offset >= end_offset) break; if (!buffer_uptodate(bh)) uptodate = 0; - if (!(PageUptodate(page) || buffer_uptodate(bh)) && !startio) { - /* - * the iomap is actually still valid, but the ioend - * isn't. shouldn't happen too often. - */ + + /* + * A hole may still be marked uptodate because discard_buffer + * leaves the flag set. + */ + if (!buffer_mapped(bh) && buffer_uptodate(bh)) { + ASSERT(!buffer_dirty(bh)); imap_valid = 0; continue; } @@ -1135,19 +1123,7 @@ xfs_page_state_convert( if (imap_valid) imap_valid = xfs_imap_valid(inode, &imap, offset); - /* - * First case, map an unwritten extent and prepare for - * extent state conversion transaction on completion. - * - * Second case, allocate space for a delalloc buffer. - * We can return EAGAIN here in the release page case. - * - * Third case, an unmapped buffer was found, and we are - * in a path where we need to write the whole page out. - */ - if (buffer_unwritten(bh) || buffer_delay(bh) || - ((buffer_uptodate(bh) || PageUptodate(page)) && - !buffer_mapped(bh) && (unmapped || startio))) { + if (buffer_unwritten(bh) || buffer_delay(bh)) { int new_ioend = 0; /* @@ -1161,15 +1137,16 @@ xfs_page_state_convert( flags = BMAPI_WRITE | BMAPI_IGNSTATE; } else if (buffer_delay(bh)) { type = IO_DELAY; - flags = BMAPI_ALLOCATE | trylock; - } else { - type = IO_NEW; - flags = BMAPI_WRITE | BMAPI_MMAP; + flags = BMAPI_ALLOCATE; + + if (wbc->sync_mode == WB_SYNC_NONE && + wbc->nonblocking) + flags |= BMAPI_TRYLOCK; } if (!imap_valid) { /* - * if we didn't have a valid mapping then we + * If we didn't have a valid mapping then we * need to ensure that we put the new mapping * in a new ioend structure. This needs to be * done to ensure that the ioends correctly @@ -1177,14 +1154,7 @@ xfs_page_state_convert( * for unwritten extent conversion. */ new_ioend = 1; - if (type == IO_NEW) { - size = xfs_probe_cluster(inode, - page, bh, head, 0); - } else { - size = len; - } - - err = xfs_map_blocks(inode, offset, size, + err = xfs_map_blocks(inode, offset, len, &imap, flags); if (err) goto error; @@ -1193,19 +1163,11 @@ xfs_page_state_convert( } if (imap_valid) { xfs_map_at_offset(inode, bh, &imap, offset); - if (startio) { - xfs_add_to_ioend(inode, bh, offset, - type, &ioend, - new_ioend); - } else { - set_buffer_dirty(bh); - unlock_buffer(bh); - mark_buffer_dirty(bh); - } - page_dirty--; + xfs_add_to_ioend(inode, bh, offset, type, + &ioend, new_ioend); count++; } - } else if (buffer_uptodate(bh) && startio) { + } else if (buffer_uptodate(bh)) { /* * we got here because the buffer is already mapped. * That means it must already have extents allocated @@ -1213,8 +1175,7 @@ xfs_page_state_convert( */ if (!imap_valid || flags != BMAPI_READ) { flags = BMAPI_READ; - size = xfs_probe_cluster(inode, page, bh, - head, 1); + size = xfs_probe_cluster(inode, page, bh, head); err = xfs_map_blocks(inode, offset, size, &imap, flags); if (err) @@ -1233,18 +1194,16 @@ xfs_page_state_convert( */ type = IO_NEW; if (trylock_buffer(bh)) { - ASSERT(buffer_mapped(bh)); if (imap_valid) all_bh = 1; xfs_add_to_ioend(inode, bh, offset, type, &ioend, !imap_valid); - page_dirty--; count++; } else { imap_valid = 0; } - } else if ((buffer_uptodate(bh) || PageUptodate(page)) && - (unmapped || startio)) { + } else if (PageUptodate(page)) { + ASSERT(buffer_mapped(bh)); imap_valid = 0; } @@ -1256,8 +1215,7 @@ xfs_page_state_convert( if (uptodate && bh == head) SetPageUptodate(page); - if (startio) - xfs_start_page_writeback(page, 1, count); + xfs_start_page_writeback(page, 1, count); if (ioend && imap_valid) { xfs_off_t end_index; @@ -1275,131 +1233,27 @@ xfs_page_state_convert( end_index = last_index; xfs_cluster_write(inode, page->index + 1, &imap, &ioend, - wbc, startio, all_bh, end_index); + wbc, all_bh, end_index); } if (iohead) xfs_submit_ioend(wbc, iohead); - return page_dirty; + return 0; error: if (iohead) xfs_cancel_ioend(iohead); - /* - * If it's delalloc and we have nowhere to put it, - * throw it away, unless the lower layers told - * us to try again. - */ - if (err != -EAGAIN) { - if (!unmapped) - xfs_aops_discard_page(page); - ClearPageUptodate(page); - } + xfs_aops_discard_page(page); + ClearPageUptodate(page); + unlock_page(page); return err; -} - -/* - * writepage: Called from one of two places: - * - * 1. we are flushing a delalloc buffer head. - * - * 2. we are writing out a dirty page. Typically the page dirty - * state is cleared before we get here. In this case is it - * conceivable we have no buffer heads. - * - * For delalloc space on the page we need to allocate space and - * flush it. For unmapped buffer heads on the page we should - * allocate space if the page is uptodate. For any other dirty - * buffer heads on the page we should flush them. - * - * If we detect that a transaction would be required to flush - * the page, we have to check the process flags first, if we - * are already in a transaction or disk I/O during allocations - * is off, we need to fail the writepage and redirty the page. - */ - -STATIC int -xfs_vm_writepage( - struct page *page, - struct writeback_control *wbc) -{ - int error; - int need_trans; - int delalloc, unmapped, unwritten; - struct inode *inode = page->mapping->host; - - trace_xfs_writepage(inode, page, 0); - - /* - * Refuse to write the page out if we are called from reclaim context. - * - * This is primarily to avoid stack overflows when called from deep - * used stacks in random callers for direct reclaim, but disabling - * reclaim for kswap is a nice side-effect as kswapd causes rather - * suboptimal I/O patters, too. - * - * This should really be done by the core VM, but until that happens - * filesystems like XFS, btrfs and ext4 have to take care of this - * by themselves. - */ - if (current->flags & PF_MEMALLOC) - goto out_fail; - - /* - * We need a transaction if: - * 1. There are delalloc buffers on the page - * 2. The page is uptodate and we have unmapped buffers - * 3. The page is uptodate and we have no buffers - * 4. There are unwritten buffers on the page - */ - - if (!page_has_buffers(page)) { - unmapped = 1; - need_trans = 1; - } else { - xfs_count_page_state(page, &delalloc, &unmapped, &unwritten); - if (!PageUptodate(page)) - unmapped = 0; - need_trans = delalloc + unmapped + unwritten; - } - - /* - * If we need a transaction and the process flags say - * we are already in a transaction, or no IO is allowed - * then mark the page dirty again and leave the page - * as is. - */ - if (current_test_flags(PF_FSTRANS) && need_trans) - goto out_fail; - - /* - * Delay hooking up buffer heads until we have - * made our go/no-go decision. - */ - if (!page_has_buffers(page)) - create_empty_buffers(page, 1 << inode->i_blkbits, 0); - - /* - * Convert delayed allocate, unwritten or unmapped space - * to real space and flush out to disk. - */ - error = xfs_page_state_convert(inode, page, wbc, 1, unmapped); - if (error == -EAGAIN) - goto out_fail; - if (unlikely(error < 0)) - goto out_unlock; - - return 0; out_fail: redirty_page_for_writepage(wbc, page); unlock_page(page); return 0; -out_unlock: - unlock_page(page); - return error; } STATIC int @@ -1413,65 +1267,27 @@ xfs_vm_writepages( /* * Called to move a page into cleanable state - and from there - * to be released. Possibly the page is already clean. We always + * to be released. The page should already be clean. We always * have buffer heads in this call. * - * Returns 0 if the page is ok to release, 1 otherwise. - * - * Possible scenarios are: - * - * 1. We are being called to release a page which has been written - * to via regular I/O. buffer heads will be dirty and possibly - * delalloc. If no delalloc buffer heads in this case then we - * can just return zero. - * - * 2. We are called to release a page which has been written via - * mmap, all we need to do is ensure there is no delalloc - * state in the buffer heads, if not we can let the caller - * free them and we should come back later via writepage. + * Returns 1 if the page is ok to release, 0 otherwise. */ STATIC int xfs_vm_releasepage( struct page *page, gfp_t gfp_mask) { - struct inode *inode = page->mapping->host; - int dirty, delalloc, unmapped, unwritten; - struct writeback_control wbc = { - .sync_mode = WB_SYNC_ALL, - .nr_to_write = 1, - }; + int delalloc, unwritten; - trace_xfs_releasepage(inode, page, 0); - - if (!page_has_buffers(page)) - return 0; + trace_xfs_releasepage(page->mapping->host, page, 0); - xfs_count_page_state(page, &delalloc, &unmapped, &unwritten); - if (!delalloc && !unwritten) - goto free_buffers; + xfs_count_page_state(page, &delalloc, &unwritten); - if (!(gfp_mask & __GFP_FS)) + if (WARN_ON(delalloc)) return 0; - - /* If we are already inside a transaction or the thread cannot - * do I/O, we cannot release this page. - */ - if (current_test_flags(PF_FSTRANS)) + if (WARN_ON(unwritten)) return 0; - /* - * Convert delalloc space to real space, do not flush the - * data out to disk, that will be done by the caller. - * Never need to allocate space here - we will always - * come back to writepage in that case. - */ - dirty = xfs_page_state_convert(inode, page, &wbc, 0, 0); - if (dirty == 0 && !unwritten) - goto free_buffers; - return 0; - -free_buffers: return try_to_free_buffers(page); } @@ -1481,9 +1297,9 @@ __xfs_get_blocks( sector_t iblock, struct buffer_head *bh_result, int create, - int direct, - bmapi_flags_t flags) + int direct) { + int flags = create ? BMAPI_WRITE : BMAPI_READ; struct xfs_bmbt_irec imap; xfs_off_t offset; ssize_t size; @@ -1498,8 +1314,11 @@ __xfs_get_blocks( if (!create && direct && offset >= i_size_read(inode)) return 0; - error = xfs_iomap(XFS_I(inode), offset, size, - create ? flags : BMAPI_READ, &imap, &nimap, &new); + if (direct && create) + flags |= BMAPI_DIRECT; + + error = xfs_iomap(XFS_I(inode), offset, size, flags, &imap, &nimap, + &new); if (error) return -error; if (nimap == 0) @@ -1579,8 +1398,7 @@ xfs_get_blocks( struct buffer_head *bh_result, int create) { - return __xfs_get_blocks(inode, iblock, - bh_result, create, 0, BMAPI_WRITE); + return __xfs_get_blocks(inode, iblock, bh_result, create, 0); } STATIC int @@ -1590,61 +1408,59 @@ xfs_get_blocks_direct( struct buffer_head *bh_result, int create) { - return __xfs_get_blocks(inode, iblock, - bh_result, create, 1, BMAPI_WRITE|BMAPI_DIRECT); + return __xfs_get_blocks(inode, iblock, bh_result, create, 1); } +/* + * Complete a direct I/O write request. + * + * If the private argument is non-NULL __xfs_get_blocks signals us that we + * need to issue a transaction to convert the range from unwritten to written + * extents. In case this is regular synchronous I/O we just call xfs_end_io + * to do this and we are done. But in case this was a successfull AIO + * request this handler is called from interrupt context, from which we + * can't start transactions. In that case offload the I/O completion to + * the workqueues we also use for buffered I/O completion. + */ STATIC void -xfs_end_io_direct( - struct kiocb *iocb, - loff_t offset, - ssize_t size, - void *private) +xfs_end_io_direct_write( + struct kiocb *iocb, + loff_t offset, + ssize_t size, + void *private, + int ret, + bool is_async) { - xfs_ioend_t *ioend = iocb->private; + struct xfs_ioend *ioend = iocb->private; /* - * Non-NULL private data means we need to issue a transaction to - * convert a range from unwritten to written extents. This needs - * to happen from process context but aio+dio I/O completion - * happens from irq context so we need to defer it to a workqueue. - * This is not necessary for synchronous direct I/O, but we do - * it anyway to keep the code uniform and simpler. - * - * Well, if only it were that simple. Because synchronous direct I/O - * requires extent conversion to occur *before* we return to userspace, - * we have to wait for extent conversion to complete. Look at the - * iocb that has been passed to us to determine if this is AIO or - * not. If it is synchronous, tell xfs_finish_ioend() to kick the - * workqueue and wait for it to complete. - * - * The core direct I/O code might be changed to always call the - * completion handler in the future, in which case all this can - * go away. + * blockdev_direct_IO can return an error even after the I/O + * completion handler was called. Thus we need to protect + * against double-freeing. */ + iocb->private = NULL; + ioend->io_offset = offset; ioend->io_size = size; - if (ioend->io_type == IO_READ) { - xfs_finish_ioend(ioend, 0); - } else if (private && size > 0) { - xfs_finish_ioend(ioend, is_sync_kiocb(iocb)); - } else { + if (private && size > 0) + ioend->io_type = IO_UNWRITTEN; + + if (is_async) { /* - * A direct I/O write ioend starts it's life in unwritten - * state in case they map an unwritten extent. This write - * didn't map an unwritten extent so switch it's completion - * handler. + * If we are converting an unwritten extent we need to delay + * the AIO completion until after the unwrittent extent + * conversion has completed, otherwise do it ASAP. */ - ioend->io_type = IO_NEW; - xfs_finish_ioend(ioend, 0); + if (ioend->io_type == IO_UNWRITTEN) { + ioend->io_iocb = iocb; + ioend->io_result = ret; + } else { + aio_complete(iocb, ret, 0); + } + xfs_finish_ioend(ioend); + } else { + xfs_finish_ioend_sync(ioend); } - - /* - * blockdev_direct_IO can return an error even after the I/O - * completion handler was called. Thus we need to protect - * against double-freeing. - */ - iocb->private = NULL; } STATIC ssize_t @@ -1655,23 +1471,26 @@ xfs_vm_direct_IO( loff_t offset, unsigned long nr_segs) { - struct file *file = iocb->ki_filp; - struct inode *inode = file->f_mapping->host; - struct block_device *bdev; - ssize_t ret; - - bdev = xfs_find_bdev_for_inode(inode); - - iocb->private = xfs_alloc_ioend(inode, rw == WRITE ? - IO_UNWRITTEN : IO_READ); - - ret = blockdev_direct_IO_no_locking(rw, iocb, inode, bdev, iov, - offset, nr_segs, - xfs_get_blocks_direct, - xfs_end_io_direct); + struct inode *inode = iocb->ki_filp->f_mapping->host; + struct block_device *bdev = xfs_find_bdev_for_inode(inode); + ssize_t ret; + + if (rw & WRITE) { + iocb->private = xfs_alloc_ioend(inode, IO_NEW); + + ret = blockdev_direct_IO_no_locking(rw, iocb, inode, bdev, iov, + offset, nr_segs, + xfs_get_blocks_direct, + xfs_end_io_direct_write); + if (ret != -EIOCBQUEUED && iocb->private) + xfs_destroy_ioend(iocb->private); + } else { + ret = blockdev_direct_IO_no_locking(rw, iocb, inode, bdev, iov, + offset, nr_segs, + xfs_get_blocks_direct, + NULL); + } - if (unlikely(ret != -EIOCBQUEUED && iocb->private)) - xfs_destroy_ioend(iocb->private); return ret; } @@ -1686,8 +1505,8 @@ xfs_vm_write_begin( void **fsdata) { *pagep = NULL; - return block_write_begin(file, mapping, pos, len, flags, pagep, fsdata, - xfs_get_blocks); + return block_write_begin(file, mapping, pos, len, flags | AOP_FLAG_NOFS, + pagep, fsdata, xfs_get_blocks); } STATIC sector_t @@ -1698,7 +1517,7 @@ xfs_vm_bmap( struct inode *inode = (struct inode *)mapping->host; struct xfs_inode *ip = XFS_I(inode); - xfs_itrace_entry(XFS_I(inode)); + trace_xfs_vm_bmap(XFS_I(inode)); xfs_ilock(ip, XFS_IOLOCK_SHARED); xfs_flush_pages(ip, (xfs_off_t)0, -1, 0, FI_REMAPF); xfs_iunlock(ip, XFS_IOLOCK_SHARED); diff --git a/fs/xfs/linux-2.6/xfs_aops.h b/fs/xfs/linux-2.6/xfs_aops.h index 4cfc6ea87df8..c5057fb6237a 100644 --- a/fs/xfs/linux-2.6/xfs_aops.h +++ b/fs/xfs/linux-2.6/xfs_aops.h @@ -37,6 +37,8 @@ typedef struct xfs_ioend { size_t io_size; /* size of the extent */ xfs_off_t io_offset; /* offset in the file */ struct work_struct io_work; /* xfsdatad work queue */ + struct kiocb *io_iocb; + int io_result; } xfs_ioend_t; extern const struct address_space_operations xfs_address_space_operations; @@ -45,6 +47,6 @@ extern int xfs_get_blocks(struct inode *, sector_t, struct buffer_head *, int); extern void xfs_ioend_init(void); extern void xfs_ioend_wait(struct xfs_inode *); -extern void xfs_count_page_state(struct page *, int *, int *, int *); +extern void xfs_count_page_state(struct page *, int *, int *); #endif /* __XFS_AOPS_H__ */ diff --git a/fs/xfs/linux-2.6/xfs_buf.c b/fs/xfs/linux-2.6/xfs_buf.c index 2ee3f7a60163..ea79072f5210 100644 --- a/fs/xfs/linux-2.6/xfs_buf.c +++ b/fs/xfs/linux-2.6/xfs_buf.c @@ -39,7 +39,6 @@ #include "xfs_inum.h" #include "xfs_log.h" #include "xfs_ag.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_trace.h" @@ -579,9 +578,9 @@ _xfs_buf_read( XBF_READ_AHEAD | _XBF_RUN_QUEUES); status = xfs_buf_iorequest(bp); - if (!status && !(flags & XBF_ASYNC)) - status = xfs_buf_iowait(bp); - return status; + if (status || XFS_BUF_ISERROR(bp) || (flags & XBF_ASYNC)) + return status; + return xfs_buf_iowait(bp); } xfs_buf_t * @@ -897,36 +896,6 @@ xfs_buf_unlock( trace_xfs_buf_unlock(bp, _RET_IP_); } - -/* - * Pinning Buffer Storage in Memory - * Ensure that no attempt to force a buffer to disk will succeed. - */ -void -xfs_buf_pin( - xfs_buf_t *bp) -{ - trace_xfs_buf_pin(bp, _RET_IP_); - atomic_inc(&bp->b_pin_count); -} - -void -xfs_buf_unpin( - xfs_buf_t *bp) -{ - trace_xfs_buf_unpin(bp, _RET_IP_); - - if (atomic_dec_and_test(&bp->b_pin_count)) - wake_up_all(&bp->b_waiters); -} - -int -xfs_buf_ispin( - xfs_buf_t *bp) -{ - return atomic_read(&bp->b_pin_count); -} - STATIC void xfs_buf_wait_unpin( xfs_buf_t *bp) @@ -1018,13 +987,12 @@ xfs_bwrite( { int error; - bp->b_strat = xfs_bdstrat_cb; bp->b_mount = mp; bp->b_flags |= XBF_WRITE; bp->b_flags &= ~(XBF_ASYNC | XBF_READ); xfs_buf_delwri_dequeue(bp); - xfs_buf_iostrategy(bp); + xfs_bdstrat_cb(bp); error = xfs_buf_iowait(bp); if (error) @@ -1040,7 +1008,6 @@ xfs_bdwrite( { trace_xfs_buf_bdwrite(bp, _RET_IP_); - bp->b_strat = xfs_bdstrat_cb; bp->b_mount = mp; bp->b_flags &= ~XBF_READ; @@ -1075,7 +1042,6 @@ xfs_bioerror( XFS_BUF_UNDONE(bp); XFS_BUF_STALE(bp); - XFS_BUF_CLR_BDSTRAT_FUNC(bp); xfs_biodone(bp); return EIO; @@ -1105,7 +1071,6 @@ xfs_bioerror_relse( XFS_BUF_DONE(bp); XFS_BUF_STALE(bp); XFS_BUF_CLR_IODONE_FUNC(bp); - XFS_BUF_CLR_BDSTRAT_FUNC(bp); if (!(fl & XBF_ASYNC)) { /* * Mark b_error and B_ERROR _both_. @@ -1311,8 +1276,19 @@ submit_io: if (size) goto next_chunk; } else { - bio_put(bio); + /* + * if we get here, no pages were added to the bio. However, + * we can't just error out here - if the pages are locked then + * we have to unlock them otherwise we can hang on a later + * access to the page. + */ xfs_buf_ioerror(bp, EIO); + if (bp->b_flags & _XBF_PAGE_LOCKED) { + int i; + for (i = 0; i < bp->b_page_count; i++) + unlock_page(bp->b_pages[i]); + } + bio_put(bio); } } @@ -1804,7 +1780,7 @@ xfs_buf_delwri_split( trace_xfs_buf_delwri_split(bp, _RET_IP_); ASSERT(bp->b_flags & XBF_DELWRI); - if (!xfs_buf_ispin(bp) && !xfs_buf_cond_lock(bp)) { + if (!XFS_BUF_ISPINNED(bp) && !xfs_buf_cond_lock(bp)) { if (!force && time_before(jiffies, bp->b_queuetime + age)) { xfs_buf_unlock(bp); @@ -1889,7 +1865,7 @@ xfsbufd( struct xfs_buf *bp; bp = list_first_entry(&tmp, struct xfs_buf, b_list); list_del_init(&bp->b_list); - xfs_buf_iostrategy(bp); + xfs_bdstrat_cb(bp); count++; } if (count) @@ -1936,7 +1912,7 @@ xfs_flush_buftarg( bp->b_flags &= ~XBF_ASYNC; list_add(&bp->b_list, &wait_list); } - xfs_buf_iostrategy(bp); + xfs_bdstrat_cb(bp); } if (wait) { diff --git a/fs/xfs/linux-2.6/xfs_buf.h b/fs/xfs/linux-2.6/xfs_buf.h index 5fbecefa5dfd..d072e5ff923b 100644 --- a/fs/xfs/linux-2.6/xfs_buf.h +++ b/fs/xfs/linux-2.6/xfs_buf.h @@ -44,57 +44,57 @@ typedef enum { XBRW_ZERO = 3, /* Zero target memory */ } xfs_buf_rw_t; -typedef enum { - XBF_READ = (1 << 0), /* buffer intended for reading from device */ - XBF_WRITE = (1 << 1), /* buffer intended for writing to device */ - XBF_MAPPED = (1 << 2), /* buffer mapped (b_addr valid) */ - XBF_ASYNC = (1 << 4), /* initiator will not wait for completion */ - XBF_DONE = (1 << 5), /* all pages in the buffer uptodate */ - XBF_DELWRI = (1 << 6), /* buffer has dirty pages */ - XBF_STALE = (1 << 7), /* buffer has been staled, do not find it */ - XBF_FS_MANAGED = (1 << 8), /* filesystem controls freeing memory */ - XBF_ORDERED = (1 << 11), /* use ordered writes */ - XBF_READ_AHEAD = (1 << 12), /* asynchronous read-ahead */ - XBF_LOG_BUFFER = (1 << 13), /* this is a buffer used for the log */ - - /* flags used only as arguments to access routines */ - XBF_LOCK = (1 << 14), /* lock requested */ - XBF_TRYLOCK = (1 << 15), /* lock requested, but do not wait */ - XBF_DONT_BLOCK = (1 << 16), /* do not block in current thread */ - - /* flags used only internally */ - _XBF_PAGE_CACHE = (1 << 17),/* backed by pagecache */ - _XBF_PAGES = (1 << 18), /* backed by refcounted pages */ - _XBF_RUN_QUEUES = (1 << 19),/* run block device task queue */ - _XBF_DELWRI_Q = (1 << 21), /* buffer on delwri queue */ - - /* - * Special flag for supporting metadata blocks smaller than a FSB. - * - * In this case we can have multiple xfs_buf_t on a single page and - * need to lock out concurrent xfs_buf_t readers as they only - * serialise access to the buffer. - * - * If the FSB size >= PAGE_CACHE_SIZE case, we have no serialisation - * between reads of the page. Hence we can have one thread read the - * page and modify it, but then race with another thread that thinks - * the page is not up-to-date and hence reads it again. - * - * The result is that the first modifcation to the page is lost. - * This sort of AGF/AGI reading race can happen when unlinking inodes - * that require truncation and results in the AGI unlinked list - * modifications being lost. - */ - _XBF_PAGE_LOCKED = (1 << 22), - - /* - * If we try a barrier write, but it fails we have to communicate - * this to the upper layers. Unfortunately b_error gets overwritten - * when the buffer is re-issued so we have to add another flag to - * keep this information. - */ - _XFS_BARRIER_FAILED = (1 << 23), -} xfs_buf_flags_t; +#define XBF_READ (1 << 0) /* buffer intended for reading from device */ +#define XBF_WRITE (1 << 1) /* buffer intended for writing to device */ +#define XBF_MAPPED (1 << 2) /* buffer mapped (b_addr valid) */ +#define XBF_ASYNC (1 << 4) /* initiator will not wait for completion */ +#define XBF_DONE (1 << 5) /* all pages in the buffer uptodate */ +#define XBF_DELWRI (1 << 6) /* buffer has dirty pages */ +#define XBF_STALE (1 << 7) /* buffer has been staled, do not find it */ +#define XBF_FS_MANAGED (1 << 8) /* filesystem controls freeing memory */ +#define XBF_ORDERED (1 << 11)/* use ordered writes */ +#define XBF_READ_AHEAD (1 << 12)/* asynchronous read-ahead */ +#define XBF_LOG_BUFFER (1 << 13)/* this is a buffer used for the log */ + +/* flags used only as arguments to access routines */ +#define XBF_LOCK (1 << 14)/* lock requested */ +#define XBF_TRYLOCK (1 << 15)/* lock requested, but do not wait */ +#define XBF_DONT_BLOCK (1 << 16)/* do not block in current thread */ + +/* flags used only internally */ +#define _XBF_PAGE_CACHE (1 << 17)/* backed by pagecache */ +#define _XBF_PAGES (1 << 18)/* backed by refcounted pages */ +#define _XBF_RUN_QUEUES (1 << 19)/* run block device task queue */ +#define _XBF_DELWRI_Q (1 << 21)/* buffer on delwri queue */ + +/* + * Special flag for supporting metadata blocks smaller than a FSB. + * + * In this case we can have multiple xfs_buf_t on a single page and + * need to lock out concurrent xfs_buf_t readers as they only + * serialise access to the buffer. + * + * If the FSB size >= PAGE_CACHE_SIZE case, we have no serialisation + * between reads of the page. Hence we can have one thread read the + * page and modify it, but then race with another thread that thinks + * the page is not up-to-date and hence reads it again. + * + * The result is that the first modifcation to the page is lost. + * This sort of AGF/AGI reading race can happen when unlinking inodes + * that require truncation and results in the AGI unlinked list + * modifications being lost. + */ +#define _XBF_PAGE_LOCKED (1 << 22) + +/* + * If we try a barrier write, but it fails we have to communicate + * this to the upper layers. Unfortunately b_error gets overwritten + * when the buffer is re-issued so we have to add another flag to + * keep this information. + */ +#define _XFS_BARRIER_FAILED (1 << 23) + +typedef unsigned int xfs_buf_flags_t; #define XFS_BUF_FLAGS \ { XBF_READ, "READ" }, \ @@ -187,7 +187,6 @@ typedef struct xfs_buf { atomic_t b_io_remaining; /* #outstanding I/O requests */ xfs_buf_iodone_t b_iodone; /* I/O completion function */ xfs_buf_relse_t b_relse; /* releasing function */ - xfs_buf_bdstrat_t b_strat; /* pre-write function */ struct completion b_iowait; /* queue for I/O waiters */ void *b_fspriv; void *b_fspriv2; @@ -245,11 +244,6 @@ extern int xfs_buf_iowait(xfs_buf_t *); extern void xfs_buf_iomove(xfs_buf_t *, size_t, size_t, void *, xfs_buf_rw_t); -static inline int xfs_buf_iostrategy(xfs_buf_t *bp) -{ - return bp->b_strat ? bp->b_strat(bp) : xfs_buf_iorequest(bp); -} - static inline int xfs_buf_geterror(xfs_buf_t *bp) { return bp ? bp->b_error : ENOMEM; @@ -258,11 +252,6 @@ static inline int xfs_buf_geterror(xfs_buf_t *bp) /* Buffer Utility Routines */ extern xfs_caddr_t xfs_buf_offset(xfs_buf_t *, size_t); -/* Pinning Buffer Storage in Memory */ -extern void xfs_buf_pin(xfs_buf_t *); -extern void xfs_buf_unpin(xfs_buf_t *); -extern int xfs_buf_ispin(xfs_buf_t *); - /* Delayed Write Buffer Routines */ extern void xfs_buf_delwri_dequeue(xfs_buf_t *); extern void xfs_buf_delwri_promote(xfs_buf_t *); @@ -326,8 +315,6 @@ extern void xfs_buf_terminate(void); #define XFS_BUF_IODONE_FUNC(bp) ((bp)->b_iodone) #define XFS_BUF_SET_IODONE_FUNC(bp, func) ((bp)->b_iodone = (func)) #define XFS_BUF_CLR_IODONE_FUNC(bp) ((bp)->b_iodone = NULL) -#define XFS_BUF_SET_BDSTRAT_FUNC(bp, func) ((bp)->b_strat = (func)) -#define XFS_BUF_CLR_BDSTRAT_FUNC(bp) ((bp)->b_strat = NULL) #define XFS_BUF_FSPRIVATE(bp, type) ((type)(bp)->b_fspriv) #define XFS_BUF_SET_FSPRIVATE(bp, val) ((bp)->b_fspriv = (void*)(val)) @@ -351,7 +338,7 @@ extern void xfs_buf_terminate(void); #define XFS_BUF_SET_VTYPE(bp, type) do { } while (0) #define XFS_BUF_SET_REF(bp, ref) do { } while (0) -#define XFS_BUF_ISPINNED(bp) xfs_buf_ispin(bp) +#define XFS_BUF_ISPINNED(bp) atomic_read(&((bp)->b_pin_count)) #define XFS_BUF_VALUSEMA(bp) xfs_buf_lock_value(bp) #define XFS_BUF_CPSEMA(bp) (xfs_buf_cond_lock(bp) == 0) @@ -370,8 +357,6 @@ static inline void xfs_buf_relse(xfs_buf_t *bp) xfs_buf_rele(bp); } -#define xfs_bpin(bp) xfs_buf_pin(bp) -#define xfs_bunpin(bp) xfs_buf_unpin(bp) #define xfs_biodone(bp) xfs_buf_ioend(bp, 0) #define xfs_biomove(bp, off, len, data, rw) \ diff --git a/fs/xfs/linux-2.6/xfs_dmapi_priv.h b/fs/xfs/linux-2.6/xfs_dmapi_priv.h deleted file mode 100644 index a8b0b1685eed..000000000000 --- a/fs/xfs/linux-2.6/xfs_dmapi_priv.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2000-2006 Silicon Graphics, Inc. - * All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it would be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#ifndef __XFS_DMAPI_PRIV_H__ -#define __XFS_DMAPI_PRIV_H__ - -/* - * Based on IO_ISDIRECT, decide which i_ flag is set. - */ -#define DM_SEM_FLAG_RD(ioflags) (((ioflags) & IO_ISDIRECT) ? \ - DM_FLAGS_IMUX : 0) -#define DM_SEM_FLAG_WR (DM_FLAGS_IALLOCSEM_WR | DM_FLAGS_IMUX) - -#endif /*__XFS_DMAPI_PRIV_H__*/ diff --git a/fs/xfs/linux-2.6/xfs_export.c b/fs/xfs/linux-2.6/xfs_export.c index e7839ee49e43..3764d74790ec 100644 --- a/fs/xfs/linux-2.6/xfs_export.c +++ b/fs/xfs/linux-2.6/xfs_export.c @@ -23,13 +23,13 @@ #include "xfs_sb.h" #include "xfs_ag.h" #include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_export.h" #include "xfs_vnodeops.h" #include "xfs_bmap_btree.h" #include "xfs_inode.h" #include "xfs_inode_item.h" +#include "xfs_trace.h" /* * Note that we only accept fileids which are long enough rather than allow @@ -132,8 +132,7 @@ xfs_nfs_get_inode( * fine and not an indication of a corrupted filesystem as clients can * send invalid file handles and we have to handle it gracefully.. */ - error = xfs_iget(mp, NULL, ino, XFS_IGET_UNTRUSTED, - XFS_ILOCK_SHARED, &ip); + error = xfs_iget(mp, NULL, ino, XFS_IGET_UNTRUSTED, 0, &ip); if (error) { /* * EINVAL means the inode cluster doesn't exist anymore. @@ -148,11 +147,10 @@ xfs_nfs_get_inode( } if (ip->i_d.di_gen != generation) { - xfs_iput_new(ip, XFS_ILOCK_SHARED); + IRELE(ip); return ERR_PTR(-ENOENT); } - xfs_iunlock(ip, XFS_ILOCK_SHARED); return VFS_I(ip); } diff --git a/fs/xfs/linux-2.6/xfs_file.c b/fs/xfs/linux-2.6/xfs_file.c index 257a56b127cf..ba8ad422a165 100644 --- a/fs/xfs/linux-2.6/xfs_file.c +++ b/fs/xfs/linux-2.6/xfs_file.c @@ -22,23 +22,15 @@ #include "xfs_inum.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" #include "xfs_trans.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" #include "xfs_alloc.h" -#include "xfs_btree.h" -#include "xfs_attr_sf.h" -#include "xfs_dir2_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_inode_item.h" #include "xfs_bmap.h" #include "xfs_error.h" -#include "xfs_rw.h" #include "xfs_vnodeops.h" #include "xfs_da_btree.h" #include "xfs_ioctl.h" @@ -108,7 +100,7 @@ xfs_file_fsync( int error = 0; int log_flushed = 0; - xfs_itrace_entry(ip); + trace_xfs_file_fsync(ip); if (XFS_FORCED_SHUTDOWN(ip->i_mount)) return -XFS_ERROR(EIO); @@ -166,8 +158,7 @@ xfs_file_fsync( * transaction. So we play it safe and fire off the * transaction anyway. */ - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); xfs_trans_log_inode(tp, ip, XFS_ILOG_CORE); xfs_trans_set_sync(tp); error = _xfs_trans_commit(tp, 0, &log_flushed); @@ -275,20 +266,6 @@ xfs_file_aio_read( mutex_lock(&inode->i_mutex); xfs_ilock(ip, XFS_IOLOCK_SHARED); - if (DM_EVENT_ENABLED(ip, DM_EVENT_READ) && !(ioflags & IO_INVIS)) { - int dmflags = FILP_DELAY_FLAG(file) | DM_SEM_FLAG_RD(ioflags); - int iolock = XFS_IOLOCK_SHARED; - - ret = -XFS_SEND_DATA(mp, DM_EVENT_READ, ip, iocb->ki_pos, size, - dmflags, &iolock); - if (ret) { - xfs_iunlock(ip, XFS_IOLOCK_SHARED); - if (unlikely(ioflags & IO_ISDIRECT)) - mutex_unlock(&inode->i_mutex); - return ret; - } - } - if (unlikely(ioflags & IO_ISDIRECT)) { if (inode->i_mapping->nrpages) { ret = -xfs_flushinval_pages(ip, @@ -321,7 +298,6 @@ xfs_file_splice_read( unsigned int flags) { struct xfs_inode *ip = XFS_I(infilp->f_mapping->host); - struct xfs_mount *mp = ip->i_mount; int ioflags = 0; ssize_t ret; @@ -335,18 +311,6 @@ xfs_file_splice_read( xfs_ilock(ip, XFS_IOLOCK_SHARED); - if (DM_EVENT_ENABLED(ip, DM_EVENT_READ) && !(ioflags & IO_INVIS)) { - int iolock = XFS_IOLOCK_SHARED; - int error; - - error = XFS_SEND_DATA(mp, DM_EVENT_READ, ip, *ppos, count, - FILP_DELAY_FLAG(infilp), &iolock); - if (error) { - xfs_iunlock(ip, XFS_IOLOCK_SHARED); - return -error; - } - } - trace_xfs_file_splice_read(ip, count, *ppos, ioflags); ret = generic_file_splice_read(infilp, ppos, pipe, count, flags); @@ -367,7 +331,6 @@ xfs_file_splice_write( { struct inode *inode = outfilp->f_mapping->host; struct xfs_inode *ip = XFS_I(inode); - struct xfs_mount *mp = ip->i_mount; xfs_fsize_t isize, new_size; int ioflags = 0; ssize_t ret; @@ -382,18 +345,6 @@ xfs_file_splice_write( xfs_ilock(ip, XFS_IOLOCK_EXCL); - if (DM_EVENT_ENABLED(ip, DM_EVENT_WRITE) && !(ioflags & IO_INVIS)) { - int iolock = XFS_IOLOCK_EXCL; - int error; - - error = XFS_SEND_DATA(mp, DM_EVENT_WRITE, ip, *ppos, count, - FILP_DELAY_FLAG(outfilp), &iolock); - if (error) { - xfs_iunlock(ip, XFS_IOLOCK_EXCL); - return -error; - } - } - new_size = *ppos + count; xfs_ilock(ip, XFS_ILOCK_EXCL); @@ -463,7 +414,7 @@ xfs_zero_last_block( last_fsb = XFS_B_TO_FSBT(mp, isize); nimaps = 1; error = xfs_bmapi(NULL, ip, last_fsb, 1, 0, NULL, 0, &imap, - &nimaps, NULL, NULL); + &nimaps, NULL); if (error) { return error; } @@ -558,7 +509,7 @@ xfs_zero_eof( nimaps = 1; zero_count_fsb = end_zero_fsb - start_zero_fsb + 1; error = xfs_bmapi(NULL, ip, start_zero_fsb, zero_count_fsb, - 0, NULL, 0, &imap, &nimaps, NULL, NULL); + 0, NULL, 0, &imap, &nimaps, NULL); if (error) { ASSERT(xfs_isilocked(ip, XFS_ILOCK_EXCL|XFS_IOLOCK_EXCL)); return error; @@ -627,7 +578,6 @@ xfs_file_aio_write( int ioflags = 0; xfs_fsize_t isize, new_size; int iolock; - int eventsent = 0; size_t ocount = 0, count; int need_i_mutex; @@ -673,33 +623,6 @@ start: goto out_unlock_mutex; } - if ((DM_EVENT_ENABLED(ip, DM_EVENT_WRITE) && - !(ioflags & IO_INVIS) && !eventsent)) { - int dmflags = FILP_DELAY_FLAG(file); - - if (need_i_mutex) - dmflags |= DM_FLAGS_IMUX; - - xfs_iunlock(ip, XFS_ILOCK_EXCL); - error = XFS_SEND_DATA(ip->i_mount, DM_EVENT_WRITE, ip, - pos, count, dmflags, &iolock); - if (error) { - goto out_unlock_internal; - } - xfs_ilock(ip, XFS_ILOCK_EXCL); - eventsent = 1; - - /* - * The iolock was dropped and reacquired in XFS_SEND_DATA - * so we have to recheck the size when appending. - * We will only "goto start;" once, since having sent the - * event prevents another call to XFS_SEND_DATA, which is - * what allows the size to change in the first place. - */ - if ((file->f_flags & O_APPEND) && pos != ip->i_size) - goto start; - } - if (ioflags & IO_ISDIRECT) { xfs_buftarg_t *target = XFS_IS_REALTIME_INODE(ip) ? @@ -830,22 +753,6 @@ write_retry: xfs_iunlock(ip, XFS_ILOCK_EXCL); } - if (ret == -ENOSPC && - DM_EVENT_ENABLED(ip, DM_EVENT_NOSPACE) && !(ioflags & IO_INVIS)) { - xfs_iunlock(ip, iolock); - if (need_i_mutex) - mutex_unlock(&inode->i_mutex); - error = XFS_SEND_NAMESP(ip->i_mount, DM_EVENT_NOSPACE, ip, - DM_RIGHT_NULL, ip, DM_RIGHT_NULL, NULL, NULL, - 0, 0, 0); /* Delay flag intentionally unused */ - if (need_i_mutex) - mutex_lock(&inode->i_mutex); - xfs_ilock(ip, iolock); - if (error) - goto out_unlock_internal; - goto start; - } - error = -ret; if (ret <= 0) goto out_unlock_internal; @@ -1014,9 +921,6 @@ const struct file_operations xfs_file_operations = { .open = xfs_file_open, .release = xfs_file_release, .fsync = xfs_file_fsync, -#ifdef HAVE_FOP_OPEN_EXEC - .open_exec = xfs_file_open_exec, -#endif }; const struct file_operations xfs_dir_file_operations = { diff --git a/fs/xfs/linux-2.6/xfs_fs_subr.c b/fs/xfs/linux-2.6/xfs_fs_subr.c index b6918d76bc7b..1f279b012f94 100644 --- a/fs/xfs/linux-2.6/xfs_fs_subr.c +++ b/fs/xfs/linux-2.6/xfs_fs_subr.c @@ -21,10 +21,6 @@ #include "xfs_inode.h" #include "xfs_trace.h" -int fs_noerr(void) { return 0; } -int fs_nosys(void) { return ENOSYS; } -void fs_noval(void) { return; } - /* * note: all filemap functions return negative error codes. These * need to be inverted before returning to the xfs core functions. diff --git a/fs/xfs/linux-2.6/xfs_fs_subr.h b/fs/xfs/linux-2.6/xfs_fs_subr.h deleted file mode 100644 index 82bb19b2599e..000000000000 --- a/fs/xfs/linux-2.6/xfs_fs_subr.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2000,2002,2005 Silicon Graphics, Inc. - * All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it would be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#ifndef __XFS_FS_SUBR_H__ -#define __XFS_FS_SUBR_H__ - -extern int fs_noerr(void); -extern int fs_nosys(void); -extern void fs_noval(void); - -#endif /* __XFS_FS_SUBR_H__ */ diff --git a/fs/xfs/linux-2.6/xfs_ioctl.c b/fs/xfs/linux-2.6/xfs_ioctl.c index e59a81062830..237f5ffb2ee8 100644 --- a/fs/xfs/linux-2.6/xfs_ioctl.c +++ b/fs/xfs/linux-2.6/xfs_ioctl.c @@ -23,24 +23,15 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" #include "xfs_alloc.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" -#include "xfs_attr_sf.h" -#include "xfs_dir2_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_ioctl.h" -#include "xfs_btree.h" -#include "xfs_ialloc.h" #include "xfs_rtalloc.h" #include "xfs_itable.h" #include "xfs_error.h" -#include "xfs_rw.h" #include "xfs_attr.h" #include "xfs_bmap.h" #include "xfs_buf_item.h" @@ -908,7 +899,7 @@ xfs_ioctl_setattr( struct xfs_dquot *olddquot = NULL; int code; - xfs_itrace_entry(ip); + trace_xfs_ioctl_setattr(ip); if (mp->m_flags & XFS_MOUNT_RDONLY) return XFS_ERROR(EROFS); @@ -1043,8 +1034,7 @@ xfs_ioctl_setattr( } } - xfs_trans_ijoin(tp, ip, lock_flags); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); /* * Change file ownership. Must be the owner or privileged. @@ -1116,16 +1106,7 @@ xfs_ioctl_setattr( xfs_qm_dqrele(udqp); xfs_qm_dqrele(gdqp); - if (code) - return code; - - if (DM_EVENT_ENABLED(ip, DM_EVENT_ATTRIBUTE)) { - XFS_SEND_NAMESP(mp, DM_EVENT_ATTRIBUTE, ip, DM_RIGHT_NULL, - NULL, DM_RIGHT_NULL, NULL, NULL, 0, 0, - (mask & FSX_NONBLOCK) ? DM_FLAGS_NDELAY : 0); - } - - return 0; + return code; error_return: xfs_qm_dqrele(udqp); @@ -1301,7 +1282,7 @@ xfs_file_ioctl( if (filp->f_mode & FMODE_NOCMTIME) ioflags |= IO_INVIS; - xfs_itrace_entry(ip); + trace_xfs_file_ioctl(ip); switch (cmd) { case XFS_IOC_ALLOCSP: diff --git a/fs/xfs/linux-2.6/xfs_ioctl32.c b/fs/xfs/linux-2.6/xfs_ioctl32.c index 52ed49e6465c..6c83f7f62dc9 100644 --- a/fs/xfs/linux-2.6/xfs_ioctl32.c +++ b/fs/xfs/linux-2.6/xfs_ioctl32.c @@ -28,12 +28,8 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_attr_sf.h" -#include "xfs_dir2_sf.h" #include "xfs_vnode.h" #include "xfs_dinode.h" #include "xfs_inode.h" @@ -544,7 +540,7 @@ xfs_file_compat_ioctl( if (filp->f_mode & FMODE_NOCMTIME) ioflags |= IO_INVIS; - xfs_itrace_entry(ip); + trace_xfs_file_compat_ioctl(ip); switch (cmd) { /* No size or alignment issues on any arch */ diff --git a/fs/xfs/linux-2.6/xfs_iops.c b/fs/xfs/linux-2.6/xfs_iops.c index 44f0b2de153e..536b81e63a3d 100644 --- a/fs/xfs/linux-2.6/xfs_iops.c +++ b/fs/xfs/linux-2.6/xfs_iops.c @@ -24,21 +24,13 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" #include "xfs_alloc.h" -#include "xfs_dmapi.h" #include "xfs_quota.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_bmap.h" -#include "xfs_btree.h" -#include "xfs_ialloc.h" #include "xfs_rtalloc.h" #include "xfs_error.h" #include "xfs_itable.h" @@ -496,7 +488,7 @@ xfs_vn_getattr( struct xfs_inode *ip = XFS_I(inode); struct xfs_mount *mp = ip->i_mount; - xfs_itrace_entry(ip); + trace_xfs_getattr(ip); if (XFS_FORCED_SHUTDOWN(mp)) return XFS_ERROR(EIO); diff --git a/fs/xfs/linux-2.6/xfs_linux.h b/fs/xfs/linux-2.6/xfs_linux.h index facfb323a706..998a9d7fb9c8 100644 --- a/fs/xfs/linux-2.6/xfs_linux.h +++ b/fs/xfs/linux-2.6/xfs_linux.h @@ -87,7 +87,6 @@ #include <xfs_aops.h> #include <xfs_super.h> #include <xfs_globals.h> -#include <xfs_fs_subr.h> #include <xfs_buf.h> /* diff --git a/fs/xfs/linux-2.6/xfs_quotaops.c b/fs/xfs/linux-2.6/xfs_quotaops.c index 067cafbfc635..bfd5ac9d1f6f 100644 --- a/fs/xfs/linux-2.6/xfs_quotaops.c +++ b/fs/xfs/linux-2.6/xfs_quotaops.c @@ -16,7 +16,6 @@ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "xfs.h" -#include "xfs_dmapi.h" #include "xfs_sb.h" #include "xfs_inum.h" #include "xfs_log.h" diff --git a/fs/xfs/linux-2.6/xfs_super.c b/fs/xfs/linux-2.6/xfs_super.c index 80938c736c27..758df94690ed 100644 --- a/fs/xfs/linux-2.6/xfs_super.c +++ b/fs/xfs/linux-2.6/xfs_super.c @@ -25,14 +25,11 @@ #include "xfs_ag.h" #include "xfs_dir2.h" #include "xfs_alloc.h" -#include "xfs_dmapi.h" #include "xfs_quota.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_btree.h" @@ -43,7 +40,6 @@ #include "xfs_error.h" #include "xfs_itable.h" #include "xfs_fsops.h" -#include "xfs_rw.h" #include "xfs_attr.h" #include "xfs_buf_item.h" #include "xfs_utils.h" @@ -94,7 +90,6 @@ mempool_t *xfs_ioend_pool; #define MNTOPT_BARRIER "barrier" /* use writer barriers for log write and * unwritten extent conversion */ #define MNTOPT_NOBARRIER "nobarrier" /* .. disable */ -#define MNTOPT_OSYNCISOSYNC "osyncisosync" /* o_sync is REALLY o_sync */ #define MNTOPT_64BITINODE "inode64" /* inodes can be allocated anywhere */ #define MNTOPT_IKEEP "ikeep" /* do not free empty inode clusters */ #define MNTOPT_NOIKEEP "noikeep" /* free empty inode clusters */ @@ -116,9 +111,6 @@ mempool_t *xfs_ioend_pool; #define MNTOPT_GQUOTANOENF "gqnoenforce"/* group quota limit enforcement */ #define MNTOPT_PQUOTANOENF "pqnoenforce"/* project quota limit enforcement */ #define MNTOPT_QUOTANOENF "qnoenforce" /* same as uqnoenforce */ -#define MNTOPT_DMAPI "dmapi" /* DMI enabled (DMAPI / XDSM) */ -#define MNTOPT_XDSM "xdsm" /* DMI enabled (DMAPI / XDSM) */ -#define MNTOPT_DMI "dmi" /* DMI enabled (DMAPI / XDSM) */ #define MNTOPT_DELAYLOG "delaylog" /* Delayed loging enabled */ #define MNTOPT_NODELAYLOG "nodelaylog" /* Delayed loging disabled */ @@ -172,15 +164,13 @@ suffix_strtoul(char *s, char **endp, unsigned int base) STATIC int xfs_parseargs( struct xfs_mount *mp, - char *options, - char **mtpt) + char *options) { struct super_block *sb = mp->m_super; char *this_char, *value, *eov; int dsunit = 0; int dswidth = 0; int iosize = 0; - int dmapi_implies_ikeep = 1; __uint8_t iosizelog = 0; /* @@ -243,15 +233,10 @@ xfs_parseargs( if (!mp->m_logname) return ENOMEM; } else if (!strcmp(this_char, MNTOPT_MTPT)) { - if (!value || !*value) { - cmn_err(CE_WARN, - "XFS: %s option requires an argument", - this_char); - return EINVAL; - } - *mtpt = kstrndup(value, MAXNAMELEN, GFP_KERNEL); - if (!*mtpt) - return ENOMEM; + cmn_err(CE_WARN, + "XFS: %s option not allowed on this system", + this_char); + return EINVAL; } else if (!strcmp(this_char, MNTOPT_RTDEV)) { if (!value || !*value) { cmn_err(CE_WARN, @@ -288,8 +273,6 @@ xfs_parseargs( mp->m_flags &= ~XFS_MOUNT_GRPID; } else if (!strcmp(this_char, MNTOPT_WSYNC)) { mp->m_flags |= XFS_MOUNT_WSYNC; - } else if (!strcmp(this_char, MNTOPT_OSYNCISOSYNC)) { - mp->m_flags |= XFS_MOUNT_OSYNCISOSYNC; } else if (!strcmp(this_char, MNTOPT_NORECOVERY)) { mp->m_flags |= XFS_MOUNT_NORECOVERY; } else if (!strcmp(this_char, MNTOPT_NOALIGN)) { @@ -329,7 +312,6 @@ xfs_parseargs( } else if (!strcmp(this_char, MNTOPT_IKEEP)) { mp->m_flags |= XFS_MOUNT_IKEEP; } else if (!strcmp(this_char, MNTOPT_NOIKEEP)) { - dmapi_implies_ikeep = 0; mp->m_flags &= ~XFS_MOUNT_IKEEP; } else if (!strcmp(this_char, MNTOPT_LARGEIO)) { mp->m_flags &= ~XFS_MOUNT_COMPAT_IOSIZE; @@ -370,12 +352,6 @@ xfs_parseargs( } else if (!strcmp(this_char, MNTOPT_GQUOTANOENF)) { mp->m_qflags |= (XFS_GQUOTA_ACCT | XFS_GQUOTA_ACTIVE); mp->m_qflags &= ~XFS_OQUOTA_ENFD; - } else if (!strcmp(this_char, MNTOPT_DMAPI)) { - mp->m_flags |= XFS_MOUNT_DMAPI; - } else if (!strcmp(this_char, MNTOPT_XDSM)) { - mp->m_flags |= XFS_MOUNT_DMAPI; - } else if (!strcmp(this_char, MNTOPT_DMI)) { - mp->m_flags |= XFS_MOUNT_DMAPI; } else if (!strcmp(this_char, MNTOPT_DELAYLOG)) { mp->m_flags |= XFS_MOUNT_DELAYLOG; cmn_err(CE_WARN, @@ -387,9 +363,11 @@ xfs_parseargs( cmn_err(CE_WARN, "XFS: ihashsize no longer used, option is deprecated."); } else if (!strcmp(this_char, "osyncisdsync")) { - /* no-op, this is now the default */ cmn_err(CE_WARN, - "XFS: osyncisdsync is now the default, option is deprecated."); + "XFS: osyncisdsync has no effect, option is deprecated."); + } else if (!strcmp(this_char, "osyncisosync")) { + cmn_err(CE_WARN, + "XFS: osyncisosync has no effect, option is deprecated."); } else if (!strcmp(this_char, "irixsgid")) { cmn_err(CE_WARN, "XFS: irixsgid is now a sysctl(2) variable, option is deprecated."); @@ -430,12 +408,6 @@ xfs_parseargs( return EINVAL; } - if ((mp->m_flags & XFS_MOUNT_DMAPI) && (!*mtpt || *mtpt[0] == '\0')) { - printk("XFS: %s option needs the mount point option as well\n", - MNTOPT_DMAPI); - return EINVAL; - } - if ((dsunit && !dswidth) || (!dsunit && dswidth)) { cmn_err(CE_WARN, "XFS: sunit and swidth must be specified together"); @@ -449,18 +421,6 @@ xfs_parseargs( return EINVAL; } - /* - * Applications using DMI filesystems often expect the - * inode generation number to be monotonically increasing. - * If we delete inode chunks we break this assumption, so - * keep unused inode chunks on disk for DMI filesystems - * until we come up with a better solution. - * Note that if "ikeep" or "noikeep" mount options are - * supplied, then they are honored. - */ - if ((mp->m_flags & XFS_MOUNT_DMAPI) && dmapi_implies_ikeep) - mp->m_flags |= XFS_MOUNT_IKEEP; - done: if (!(mp->m_flags & XFS_MOUNT_NOALIGN)) { /* @@ -539,10 +499,8 @@ xfs_showargs( { XFS_MOUNT_SWALLOC, "," MNTOPT_SWALLOC }, { XFS_MOUNT_NOUUID, "," MNTOPT_NOUUID }, { XFS_MOUNT_NORECOVERY, "," MNTOPT_NORECOVERY }, - { XFS_MOUNT_OSYNCISOSYNC, "," MNTOPT_OSYNCISOSYNC }, { XFS_MOUNT_ATTR2, "," MNTOPT_ATTR2 }, { XFS_MOUNT_FILESTREAMS, "," MNTOPT_FILESTREAM }, - { XFS_MOUNT_DMAPI, "," MNTOPT_DMAPI }, { XFS_MOUNT_GRPID, "," MNTOPT_GRPID }, { XFS_MOUNT_DELAYLOG, "," MNTOPT_DELAYLOG }, { 0, NULL } @@ -947,7 +905,7 @@ xfs_fs_destroy_inode( { struct xfs_inode *ip = XFS_I(inode); - xfs_itrace_entry(ip); + trace_xfs_destroy_inode(ip); XFS_STATS_INC(vn_reclaim); @@ -1063,10 +1021,8 @@ xfs_log_inode( * an inode in another recent transaction. So we play it safe and * fire off the transaction anyway. */ - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); xfs_trans_log_inode(tp, ip, XFS_ILOG_CORE); - xfs_trans_set_sync(tp); error = xfs_trans_commit(tp, 0); xfs_ilock_demote(ip, XFS_ILOCK_EXCL); @@ -1082,27 +1038,18 @@ xfs_fs_write_inode( struct xfs_mount *mp = ip->i_mount; int error = EAGAIN; - xfs_itrace_entry(ip); + trace_xfs_write_inode(ip); if (XFS_FORCED_SHUTDOWN(mp)) return XFS_ERROR(EIO); if (wbc->sync_mode == WB_SYNC_ALL) { /* - * Make sure the inode has hit stable storage. By using the - * log and the fsync transactions we reduce the IOs we have - * to do here from two (log and inode) to just the log. - * - * Note: We still need to do a delwri write of the inode after - * this to flush it to the backing buffer so that bulkstat - * works properly if this is the first time the inode has been - * written. Because we hold the ilock atomically over the - * transaction commit and the inode flush we are guaranteed - * that the inode is not pinned when it returns. If the flush - * lock is already held, then the inode has already been - * flushed once and we don't need to flush it again. Hence - * the code will only flush the inode if it isn't already - * being flushed. + * Make sure the inode has made it it into the log. Instead + * of forcing it all the way to stable storage using a + * synchronous transaction we let the log force inside the + * ->sync_fs call do that for thus, which reduces the number + * of synchronous log foces dramatically. */ xfs_ioend_wait(ip); xfs_ilock(ip, XFS_ILOCK_SHARED); @@ -1116,27 +1063,29 @@ xfs_fs_write_inode( * We make this non-blocking if the inode is contended, return * EAGAIN to indicate to the caller that they did not succeed. * This prevents the flush path from blocking on inodes inside - * another operation right now, they get caught later by xfs_sync. + * another operation right now, they get caught later by + * xfs_sync. */ if (!xfs_ilock_nowait(ip, XFS_ILOCK_SHARED)) goto out; - } - if (xfs_ipincount(ip) || !xfs_iflock_nowait(ip)) - goto out_unlock; + if (xfs_ipincount(ip) || !xfs_iflock_nowait(ip)) + goto out_unlock; - /* - * Now we have the flush lock and the inode is not pinned, we can check - * if the inode is really clean as we know that there are no pending - * transaction completions, it is not waiting on the delayed write - * queue and there is no IO in progress. - */ - if (xfs_inode_clean(ip)) { - xfs_ifunlock(ip); - error = 0; - goto out_unlock; + /* + * Now we have the flush lock and the inode is not pinned, we + * can check if the inode is really clean as we know that + * there are no pending transaction completions, it is not + * waiting on the delayed write queue and there is no IO in + * progress. + */ + if (xfs_inode_clean(ip)) { + xfs_ifunlock(ip); + error = 0; + goto out_unlock; + } + error = xfs_iflush(ip, 0); } - error = xfs_iflush(ip, 0); out_unlock: xfs_iunlock(ip, XFS_ILOCK_SHARED); @@ -1156,7 +1105,8 @@ xfs_fs_clear_inode( { xfs_inode_t *ip = XFS_I(inode); - xfs_itrace_entry(ip); + trace_xfs_clear_inode(ip); + XFS_STATS_INC(vn_rele); XFS_STATS_INC(vn_remove); XFS_STATS_DEC(vn_active); @@ -1193,22 +1143,13 @@ xfs_fs_put_super( { struct xfs_mount *mp = XFS_M(sb); + /* + * Unregister the memory shrinker before we tear down the mount + * structure so we don't have memory reclaim racing with us here. + */ + xfs_inode_shrinker_unregister(mp); xfs_syncd_stop(mp); - if (!(sb->s_flags & MS_RDONLY)) { - /* - * XXX(hch): this should be SYNC_WAIT. - * - * Or more likely not needed at all because the VFS is already - * calling ->sync_fs after shutting down all filestem - * operations and just before calling ->put_super. - */ - xfs_sync_data(mp, 0); - xfs_sync_attr(mp, 0); - } - - XFS_SEND_PREUNMOUNT(mp); - /* * Blow away any referenced inode in the filestreams cache. * This can and will cause log traffic as inodes go inactive @@ -1218,14 +1159,10 @@ xfs_fs_put_super( XFS_bflush(mp->m_ddev_targp); - XFS_SEND_UNMOUNT(mp); - xfs_unmountfs(mp); xfs_freesb(mp); - xfs_inode_shrinker_unregister(mp); xfs_icsb_destroy_counters(mp); xfs_close_devices(mp); - xfs_dmops_put(mp); xfs_free_fsname(mp); kfree(mp); } @@ -1543,7 +1480,6 @@ xfs_fs_fill_super( struct inode *root; struct xfs_mount *mp = NULL; int flags = 0, error = ENOMEM; - char *mtpt = NULL; mp = kzalloc(sizeof(struct xfs_mount), GFP_KERNEL); if (!mp) @@ -1559,7 +1495,7 @@ xfs_fs_fill_super( mp->m_super = sb; sb->s_fs_info = mp; - error = xfs_parseargs(mp, (char *)data, &mtpt); + error = xfs_parseargs(mp, (char *)data); if (error) goto out_free_fsname; @@ -1571,16 +1507,12 @@ xfs_fs_fill_super( #endif sb->s_op = &xfs_super_operations; - error = xfs_dmops_get(mp); - if (error) - goto out_free_fsname; - if (silent) flags |= XFS_MFSI_QUIET; error = xfs_open_devices(mp); if (error) - goto out_put_dmops; + goto out_free_fsname; if (xfs_icsb_init_counters(mp)) mp->m_flags |= XFS_MOUNT_NO_PERCPU_SB; @@ -1608,8 +1540,6 @@ xfs_fs_fill_super( if (error) goto out_filestream_unmount; - XFS_SEND_MOUNT(mp, DM_RIGHT_NULL, mtpt, mp->m_fsname); - sb->s_magic = XFS_SB_MAGIC; sb->s_blocksize = mp->m_sb.sb_blocksize; sb->s_blocksize_bits = ffs(sb->s_blocksize) - 1; @@ -1638,7 +1568,6 @@ xfs_fs_fill_super( xfs_inode_shrinker_register(mp); - kfree(mtpt); return 0; out_filestream_unmount: @@ -1648,11 +1577,8 @@ xfs_fs_fill_super( out_destroy_counters: xfs_icsb_destroy_counters(mp); xfs_close_devices(mp); - out_put_dmops: - xfs_dmops_put(mp); out_free_fsname: xfs_free_fsname(mp); - kfree(mtpt); kfree(mp); out: return -error; @@ -1759,6 +1685,12 @@ xfs_init_zones(void) if (!xfs_trans_zone) goto out_destroy_ifork_zone; + xfs_log_item_desc_zone = + kmem_zone_init(sizeof(struct xfs_log_item_desc), + "xfs_log_item_desc"); + if (!xfs_log_item_desc_zone) + goto out_destroy_trans_zone; + /* * The size of the zone allocated buf log item is the maximum * size possible under XFS. This wastes a little bit of memory, @@ -1768,7 +1700,7 @@ xfs_init_zones(void) (((XFS_MAX_BLOCKSIZE / XFS_BLF_CHUNK) / NBWORD) * sizeof(int))), "xfs_buf_item"); if (!xfs_buf_item_zone) - goto out_destroy_trans_zone; + goto out_destroy_log_item_desc_zone; xfs_efd_zone = kmem_zone_init((sizeof(xfs_efd_log_item_t) + ((XFS_EFD_MAX_FAST_EXTENTS - 1) * @@ -1805,6 +1737,8 @@ xfs_init_zones(void) kmem_zone_destroy(xfs_efd_zone); out_destroy_buf_item_zone: kmem_zone_destroy(xfs_buf_item_zone); + out_destroy_log_item_desc_zone: + kmem_zone_destroy(xfs_log_item_desc_zone); out_destroy_trans_zone: kmem_zone_destroy(xfs_trans_zone); out_destroy_ifork_zone: @@ -1835,6 +1769,7 @@ xfs_destroy_zones(void) kmem_zone_destroy(xfs_efi_zone); kmem_zone_destroy(xfs_efd_zone); kmem_zone_destroy(xfs_buf_item_zone); + kmem_zone_destroy(xfs_log_item_desc_zone); kmem_zone_destroy(xfs_trans_zone); kmem_zone_destroy(xfs_ifork_zone); kmem_zone_destroy(xfs_dabuf_zone); diff --git a/fs/xfs/linux-2.6/xfs_super.h b/fs/xfs/linux-2.6/xfs_super.h index 519618e9279e..1ef4a4d2d997 100644 --- a/fs/xfs/linux-2.6/xfs_super.h +++ b/fs/xfs/linux-2.6/xfs_super.h @@ -56,12 +56,6 @@ extern void xfs_qm_exit(void); # define XFS_BIGFS_STRING #endif -#ifdef CONFIG_XFS_DMAPI -# define XFS_DMAPI_STRING "dmapi support, " -#else -# define XFS_DMAPI_STRING -#endif - #ifdef DEBUG # define XFS_DBG_STRING "debug" #else @@ -72,7 +66,6 @@ extern void xfs_qm_exit(void); XFS_SECURITY_STRING \ XFS_REALTIME_STRING \ XFS_BIGFS_STRING \ - XFS_DMAPI_STRING \ XFS_DBG_STRING /* DBG must be last */ struct xfs_inode; diff --git a/fs/xfs/linux-2.6/xfs_sync.c b/fs/xfs/linux-2.6/xfs_sync.c index a51a07c3a70c..dfcbd98d1599 100644 --- a/fs/xfs/linux-2.6/xfs_sync.c +++ b/fs/xfs/linux-2.6/xfs_sync.c @@ -24,25 +24,14 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" -#include "xfs_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_inode.h" #include "xfs_dinode.h" #include "xfs_error.h" -#include "xfs_mru_cache.h" #include "xfs_filestream.h" #include "xfs_vnodeops.h" -#include "xfs_utils.h" -#include "xfs_buf_item.h" #include "xfs_inode_item.h" -#include "xfs_rw.h" #include "xfs_quota.h" #include "xfs_trace.h" @@ -319,7 +308,7 @@ xfs_sync_inode_attr( /* * Write out pagecache data for the whole filesystem. */ -int +STATIC int xfs_sync_data( struct xfs_mount *mp, int flags) @@ -340,7 +329,7 @@ xfs_sync_data( /* * Write out inode metadata (attributes) for the whole filesystem. */ -int +STATIC int xfs_sync_attr( struct xfs_mount *mp, int flags) @@ -373,8 +362,7 @@ xfs_commit_dummy_trans( xfs_ilock(ip, XFS_ILOCK_EXCL); - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); xfs_trans_log_inode(tp, ip, XFS_ILOG_CORE); error = xfs_trans_commit(tp, 0); xfs_iunlock(ip, XFS_ILOCK_EXCL); @@ -867,7 +855,36 @@ out: reclaim: xfs_ifunlock(ip); xfs_iunlock(ip, XFS_ILOCK_EXCL); - xfs_ireclaim(ip); + + XFS_STATS_INC(xs_ig_reclaims); + /* + * Remove the inode from the per-AG radix tree. + * + * Because radix_tree_delete won't complain even if the item was never + * added to the tree assert that it's been there before to catch + * problems with the inode life time early on. + */ + write_lock(&pag->pag_ici_lock); + if (!radix_tree_delete(&pag->pag_ici_root, + XFS_INO_TO_AGINO(ip->i_mount, ip->i_ino))) + ASSERT(0); + write_unlock(&pag->pag_ici_lock); + + /* + * Here we do an (almost) spurious inode lock in order to coordinate + * with inode cache radix tree lookups. This is because the lookup + * can reference the inodes in the cache without taking references. + * + * We make that OK here by ensuring that we wait until the inode is + * unlocked after the lookup before we go ahead and free it. We get + * both the ilock and the iolock because the code may need to drop the + * ilock one but will still hold the iolock. + */ + xfs_ilock(ip, XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); + xfs_qm_dqdetach(ip); + xfs_iunlock(ip, XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); + + xfs_inode_free(ip); return error; } diff --git a/fs/xfs/linux-2.6/xfs_sync.h b/fs/xfs/linux-2.6/xfs_sync.h index e28139aaa4aa..fe78726196f8 100644 --- a/fs/xfs/linux-2.6/xfs_sync.h +++ b/fs/xfs/linux-2.6/xfs_sync.h @@ -35,9 +35,6 @@ typedef struct xfs_sync_work { int xfs_syncd_init(struct xfs_mount *mp); void xfs_syncd_stop(struct xfs_mount *mp); -int xfs_sync_attr(struct xfs_mount *mp, int flags); -int xfs_sync_data(struct xfs_mount *mp, int flags); - int xfs_quiesce_data(struct xfs_mount *mp); void xfs_quiesce_attr(struct xfs_mount *mp); diff --git a/fs/xfs/linux-2.6/xfs_trace.c b/fs/xfs/linux-2.6/xfs_trace.c index d12be8470cba..88d25d4aa56e 100644 --- a/fs/xfs/linux-2.6/xfs_trace.c +++ b/fs/xfs/linux-2.6/xfs_trace.c @@ -24,17 +24,13 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" #include "xfs_da_btree.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_btree.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_ialloc.h" #include "xfs_itable.h" diff --git a/fs/xfs/linux-2.6/xfs_trace.h b/fs/xfs/linux-2.6/xfs_trace.h index 302820690904..c657cdca2cd2 100644 --- a/fs/xfs/linux-2.6/xfs_trace.h +++ b/fs/xfs/linux-2.6/xfs_trace.h @@ -317,8 +317,6 @@ DEFINE_BUF_EVENT(xfs_buf_init); DEFINE_BUF_EVENT(xfs_buf_free); DEFINE_BUF_EVENT(xfs_buf_hold); DEFINE_BUF_EVENT(xfs_buf_rele); -DEFINE_BUF_EVENT(xfs_buf_pin); -DEFINE_BUF_EVENT(xfs_buf_unpin); DEFINE_BUF_EVENT(xfs_buf_iodone); DEFINE_BUF_EVENT(xfs_buf_iorequest); DEFINE_BUF_EVENT(xfs_buf_bawrite); @@ -541,7 +539,7 @@ DEFINE_LOCK_EVENT(xfs_ilock_nowait); DEFINE_LOCK_EVENT(xfs_ilock_demote); DEFINE_LOCK_EVENT(xfs_iunlock); -DECLARE_EVENT_CLASS(xfs_iget_class, +DECLARE_EVENT_CLASS(xfs_inode_class, TP_PROTO(struct xfs_inode *ip), TP_ARGS(ip), TP_STRUCT__entry( @@ -557,16 +555,38 @@ DECLARE_EVENT_CLASS(xfs_iget_class, __entry->ino) ) -#define DEFINE_IGET_EVENT(name) \ -DEFINE_EVENT(xfs_iget_class, name, \ +#define DEFINE_INODE_EVENT(name) \ +DEFINE_EVENT(xfs_inode_class, name, \ TP_PROTO(struct xfs_inode *ip), \ TP_ARGS(ip)) -DEFINE_IGET_EVENT(xfs_iget_skip); -DEFINE_IGET_EVENT(xfs_iget_reclaim); -DEFINE_IGET_EVENT(xfs_iget_found); -DEFINE_IGET_EVENT(xfs_iget_alloc); - -DECLARE_EVENT_CLASS(xfs_inode_class, +DEFINE_INODE_EVENT(xfs_iget_skip); +DEFINE_INODE_EVENT(xfs_iget_reclaim); +DEFINE_INODE_EVENT(xfs_iget_reclaim_fail); +DEFINE_INODE_EVENT(xfs_iget_hit); +DEFINE_INODE_EVENT(xfs_iget_miss); + +DEFINE_INODE_EVENT(xfs_getattr); +DEFINE_INODE_EVENT(xfs_setattr); +DEFINE_INODE_EVENT(xfs_readlink); +DEFINE_INODE_EVENT(xfs_alloc_file_space); +DEFINE_INODE_EVENT(xfs_free_file_space); +DEFINE_INODE_EVENT(xfs_readdir); +#ifdef CONFIG_XFS_POSIX_ACL +DEFINE_INODE_EVENT(xfs_check_acl); +#endif +DEFINE_INODE_EVENT(xfs_vm_bmap); +DEFINE_INODE_EVENT(xfs_file_ioctl); +DEFINE_INODE_EVENT(xfs_file_compat_ioctl); +DEFINE_INODE_EVENT(xfs_ioctl_setattr); +DEFINE_INODE_EVENT(xfs_file_fsync); +DEFINE_INODE_EVENT(xfs_destroy_inode); +DEFINE_INODE_EVENT(xfs_write_inode); +DEFINE_INODE_EVENT(xfs_clear_inode); + +DEFINE_INODE_EVENT(xfs_dquot_dqalloc); +DEFINE_INODE_EVENT(xfs_dquot_dqdetach); + +DECLARE_EVENT_CLASS(xfs_iref_class, TP_PROTO(struct xfs_inode *ip, unsigned long caller_ip), TP_ARGS(ip, caller_ip), TP_STRUCT__entry( @@ -591,20 +611,71 @@ DECLARE_EVENT_CLASS(xfs_inode_class, (char *)__entry->caller_ip) ) -#define DEFINE_INODE_EVENT(name) \ -DEFINE_EVENT(xfs_inode_class, name, \ +#define DEFINE_IREF_EVENT(name) \ +DEFINE_EVENT(xfs_iref_class, name, \ TP_PROTO(struct xfs_inode *ip, unsigned long caller_ip), \ TP_ARGS(ip, caller_ip)) -DEFINE_INODE_EVENT(xfs_ihold); -DEFINE_INODE_EVENT(xfs_irele); -DEFINE_INODE_EVENT(xfs_inode_pin); -DEFINE_INODE_EVENT(xfs_inode_unpin); -DEFINE_INODE_EVENT(xfs_inode_unpin_nowait); +DEFINE_IREF_EVENT(xfs_ihold); +DEFINE_IREF_EVENT(xfs_irele); +DEFINE_IREF_EVENT(xfs_inode_pin); +DEFINE_IREF_EVENT(xfs_inode_unpin); +DEFINE_IREF_EVENT(xfs_inode_unpin_nowait); + +DECLARE_EVENT_CLASS(xfs_namespace_class, + TP_PROTO(struct xfs_inode *dp, struct xfs_name *name), + TP_ARGS(dp, name), + TP_STRUCT__entry( + __field(dev_t, dev) + __field(xfs_ino_t, dp_ino) + __dynamic_array(char, name, name->len) + ), + TP_fast_assign( + __entry->dev = VFS_I(dp)->i_sb->s_dev; + __entry->dp_ino = dp->i_ino; + memcpy(__get_str(name), name->name, name->len); + ), + TP_printk("dev %d:%d dp ino 0x%llx name %s", + MAJOR(__entry->dev), MINOR(__entry->dev), + __entry->dp_ino, + __get_str(name)) +) -/* the old xfs_itrace_entry tracer - to be replaced by s.th. in the VFS */ -DEFINE_INODE_EVENT(xfs_inode); -#define xfs_itrace_entry(ip) \ - trace_xfs_inode(ip, _THIS_IP_) +#define DEFINE_NAMESPACE_EVENT(name) \ +DEFINE_EVENT(xfs_namespace_class, name, \ + TP_PROTO(struct xfs_inode *dp, struct xfs_name *name), \ + TP_ARGS(dp, name)) +DEFINE_NAMESPACE_EVENT(xfs_remove); +DEFINE_NAMESPACE_EVENT(xfs_link); +DEFINE_NAMESPACE_EVENT(xfs_lookup); +DEFINE_NAMESPACE_EVENT(xfs_create); +DEFINE_NAMESPACE_EVENT(xfs_symlink); + +TRACE_EVENT(xfs_rename, + TP_PROTO(struct xfs_inode *src_dp, struct xfs_inode *target_dp, + struct xfs_name *src_name, struct xfs_name *target_name), + TP_ARGS(src_dp, target_dp, src_name, target_name), + TP_STRUCT__entry( + __field(dev_t, dev) + __field(xfs_ino_t, src_dp_ino) + __field(xfs_ino_t, target_dp_ino) + __dynamic_array(char, src_name, src_name->len) + __dynamic_array(char, target_name, target_name->len) + ), + TP_fast_assign( + __entry->dev = VFS_I(src_dp)->i_sb->s_dev; + __entry->src_dp_ino = src_dp->i_ino; + __entry->target_dp_ino = target_dp->i_ino; + memcpy(__get_str(src_name), src_name->name, src_name->len); + memcpy(__get_str(target_name), target_name->name, target_name->len); + ), + TP_printk("dev %d:%d src dp ino 0x%llx target dp ino 0x%llx" + " src name %s target name %s", + MAJOR(__entry->dev), MINOR(__entry->dev), + __entry->src_dp_ino, + __entry->target_dp_ino, + __get_str(src_name), + __get_str(target_name)) +) DECLARE_EVENT_CLASS(xfs_dquot_class, TP_PROTO(struct xfs_dquot *dqp), @@ -684,9 +755,6 @@ DEFINE_DQUOT_EVENT(xfs_dqrele); DEFINE_DQUOT_EVENT(xfs_dqflush); DEFINE_DQUOT_EVENT(xfs_dqflush_force); DEFINE_DQUOT_EVENT(xfs_dqflush_done); -/* not really iget events, but we re-use the format */ -DEFINE_IGET_EVENT(xfs_dquot_dqalloc); -DEFINE_IGET_EVENT(xfs_dquot_dqdetach); DECLARE_EVENT_CLASS(xfs_loggrant_class, TP_PROTO(struct log *log, struct xlog_ticket *tic), @@ -834,33 +902,29 @@ DECLARE_EVENT_CLASS(xfs_page_class, __field(loff_t, size) __field(unsigned long, offset) __field(int, delalloc) - __field(int, unmapped) __field(int, unwritten) ), TP_fast_assign( - int delalloc = -1, unmapped = -1, unwritten = -1; + int delalloc = -1, unwritten = -1; if (page_has_buffers(page)) - xfs_count_page_state(page, &delalloc, - &unmapped, &unwritten); + xfs_count_page_state(page, &delalloc, &unwritten); __entry->dev = inode->i_sb->s_dev; __entry->ino = XFS_I(inode)->i_ino; __entry->pgoff = page_offset(page); __entry->size = i_size_read(inode); __entry->offset = off; __entry->delalloc = delalloc; - __entry->unmapped = unmapped; __entry->unwritten = unwritten; ), TP_printk("dev %d:%d ino 0x%llx pgoff 0x%lx size 0x%llx offset %lx " - "delalloc %d unmapped %d unwritten %d", + "delalloc %d unwritten %d", MAJOR(__entry->dev), MINOR(__entry->dev), __entry->ino, __entry->pgoff, __entry->size, __entry->offset, __entry->delalloc, - __entry->unmapped, __entry->unwritten) ) diff --git a/fs/xfs/quota/xfs_dquot.c b/fs/xfs/quota/xfs_dquot.c index 585e7633dfc7..e1a2f6800e01 100644 --- a/fs/xfs/quota/xfs_dquot.c +++ b/fs/xfs/quota/xfs_dquot.c @@ -23,25 +23,15 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" #include "xfs_alloc.h" -#include "xfs_dmapi.h" #include "xfs_quota.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" -#include "xfs_dinode.h" #include "xfs_inode.h" -#include "xfs_btree.h" -#include "xfs_ialloc.h" #include "xfs_bmap.h" #include "xfs_rtalloc.h" #include "xfs_error.h" #include "xfs_itable.h" -#include "xfs_rw.h" #include "xfs_attr.h" #include "xfs_buf_item.h" #include "xfs_trans_space.h" @@ -64,8 +54,6 @@ flush lock - ditto. */ -STATIC void xfs_qm_dqflush_done(xfs_buf_t *, xfs_dq_logitem_t *); - #ifdef DEBUG xfs_buftarg_t *xfs_dqerror_target; int xfs_do_dqerror; @@ -390,21 +378,14 @@ xfs_qm_dqalloc( return (ESRCH); } - /* - * xfs_trans_commit normally decrements the vnode ref count - * when it unlocks the inode. Since we want to keep the quota - * inode around, we bump the vnode ref count now. - */ - IHOLD(quotip); - - xfs_trans_ijoin(tp, quotip, XFS_ILOCK_EXCL); + xfs_trans_ijoin_ref(tp, quotip, XFS_ILOCK_EXCL); nmaps = 1; if ((error = xfs_bmapi(tp, quotip, offset_fsb, XFS_DQUOT_CLUSTER_SIZE_FSB, XFS_BMAPI_METADATA | XFS_BMAPI_WRITE, &firstblock, XFS_QM_DQALLOC_SPACE_RES(mp), - &map, &nmaps, &flist, NULL))) { + &map, &nmaps, &flist))) { goto error0; } ASSERT(map.br_blockcount == XFS_DQUOT_CLUSTER_SIZE_FSB); @@ -520,7 +501,7 @@ xfs_qm_dqtobp( error = xfs_bmapi(NULL, quotip, dqp->q_fileoffset, XFS_DQUOT_CLUSTER_SIZE_FSB, XFS_BMAPI_METADATA, - NULL, 0, &map, &nmaps, NULL, NULL); + NULL, 0, &map, &nmaps, NULL); xfs_iunlock(quotip, XFS_ILOCK_SHARED); if (error) @@ -1141,6 +1122,46 @@ xfs_qm_dqrele( xfs_qm_dqput(dqp); } +/* + * This is the dquot flushing I/O completion routine. It is called + * from interrupt level when the buffer containing the dquot is + * flushed to disk. It is responsible for removing the dquot logitem + * from the AIL if it has not been re-logged, and unlocking the dquot's + * flush lock. This behavior is very similar to that of inodes.. + */ +STATIC void +xfs_qm_dqflush_done( + struct xfs_buf *bp, + struct xfs_log_item *lip) +{ + xfs_dq_logitem_t *qip = (struct xfs_dq_logitem *)lip; + xfs_dquot_t *dqp = qip->qli_dquot; + struct xfs_ail *ailp = lip->li_ailp; + + /* + * We only want to pull the item from the AIL if its + * location in the log has not changed since we started the flush. + * Thus, we only bother if the dquot's lsn has + * not changed. First we check the lsn outside the lock + * since it's cheaper, and then we recheck while + * holding the lock before removing the dquot from the AIL. + */ + if ((lip->li_flags & XFS_LI_IN_AIL) && + lip->li_lsn == qip->qli_flush_lsn) { + + /* xfs_trans_ail_delete() drops the AIL lock. */ + spin_lock(&ailp->xa_lock); + if (lip->li_lsn == qip->qli_flush_lsn) + xfs_trans_ail_delete(ailp, lip); + else + spin_unlock(&ailp->xa_lock); + } + + /* + * Release the dq's flush lock since we're done with it. + */ + xfs_dqfunlock(dqp); +} /* * Write a modified dquot to disk. @@ -1222,8 +1243,9 @@ xfs_qm_dqflush( * Attach an iodone routine so that we can remove this dquot from the * AIL and release the flush lock once the dquot is synced to disk. */ - xfs_buf_attach_iodone(bp, (void(*)(xfs_buf_t *, xfs_log_item_t *)) - xfs_qm_dqflush_done, &(dqp->q_logitem.qli_item)); + xfs_buf_attach_iodone(bp, xfs_qm_dqflush_done, + &dqp->q_logitem.qli_item); + /* * If the buffer is pinned then push on the log so we won't * get stuck waiting in the write for too long. @@ -1247,50 +1269,6 @@ xfs_qm_dqflush( } -/* - * This is the dquot flushing I/O completion routine. It is called - * from interrupt level when the buffer containing the dquot is - * flushed to disk. It is responsible for removing the dquot logitem - * from the AIL if it has not been re-logged, and unlocking the dquot's - * flush lock. This behavior is very similar to that of inodes.. - */ -/*ARGSUSED*/ -STATIC void -xfs_qm_dqflush_done( - xfs_buf_t *bp, - xfs_dq_logitem_t *qip) -{ - xfs_dquot_t *dqp; - struct xfs_ail *ailp; - - dqp = qip->qli_dquot; - ailp = qip->qli_item.li_ailp; - - /* - * We only want to pull the item from the AIL if its - * location in the log has not changed since we started the flush. - * Thus, we only bother if the dquot's lsn has - * not changed. First we check the lsn outside the lock - * since it's cheaper, and then we recheck while - * holding the lock before removing the dquot from the AIL. - */ - if ((qip->qli_item.li_flags & XFS_LI_IN_AIL) && - qip->qli_item.li_lsn == qip->qli_flush_lsn) { - - /* xfs_trans_ail_delete() drops the AIL lock. */ - spin_lock(&ailp->xa_lock); - if (qip->qli_item.li_lsn == qip->qli_flush_lsn) - xfs_trans_ail_delete(ailp, (xfs_log_item_t*)qip); - else - spin_unlock(&ailp->xa_lock); - } - - /* - * Release the dq's flush lock since we're done with it. - */ - xfs_dqfunlock(dqp); -} - int xfs_qm_dqlock_nowait( xfs_dquot_t *dqp) diff --git a/fs/xfs/quota/xfs_dquot_item.c b/fs/xfs/quota/xfs_dquot_item.c index 8d89a24ae324..2a1f3dc10a02 100644 --- a/fs/xfs/quota/xfs_dquot_item.c +++ b/fs/xfs/quota/xfs_dquot_item.c @@ -23,42 +23,36 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" #include "xfs_alloc.h" -#include "xfs_dmapi.h" #include "xfs_quota.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" -#include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_bmap.h" -#include "xfs_btree.h" -#include "xfs_ialloc.h" #include "xfs_rtalloc.h" #include "xfs_error.h" #include "xfs_itable.h" -#include "xfs_rw.h" #include "xfs_attr.h" #include "xfs_buf_item.h" #include "xfs_trans_priv.h" #include "xfs_qm.h" +static inline struct xfs_dq_logitem *DQUOT_ITEM(struct xfs_log_item *lip) +{ + return container_of(lip, struct xfs_dq_logitem, qli_item); +} + /* * returns the number of iovecs needed to log the given dquot item. */ -/* ARGSUSED */ STATIC uint xfs_qm_dquot_logitem_size( - xfs_dq_logitem_t *logitem) + struct xfs_log_item *lip) { /* * we need only two iovecs, one for the format, one for the real thing */ - return (2); + return 2; } /* @@ -66,22 +60,21 @@ xfs_qm_dquot_logitem_size( */ STATIC void xfs_qm_dquot_logitem_format( - xfs_dq_logitem_t *logitem, - xfs_log_iovec_t *logvec) + struct xfs_log_item *lip, + struct xfs_log_iovec *logvec) { - ASSERT(logitem); - ASSERT(logitem->qli_dquot); + struct xfs_dq_logitem *qlip = DQUOT_ITEM(lip); - logvec->i_addr = (xfs_caddr_t)&logitem->qli_format; + logvec->i_addr = &qlip->qli_format; logvec->i_len = sizeof(xfs_dq_logformat_t); logvec->i_type = XLOG_REG_TYPE_QFORMAT; logvec++; - logvec->i_addr = (xfs_caddr_t)&logitem->qli_dquot->q_core; + logvec->i_addr = &qlip->qli_dquot->q_core; logvec->i_len = sizeof(xfs_disk_dquot_t); logvec->i_type = XLOG_REG_TYPE_DQUOT; - ASSERT(2 == logitem->qli_item.li_desc->lid_size); - logitem->qli_format.qlf_size = 2; + ASSERT(2 == lip->li_desc->lid_size); + qlip->qli_format.qlf_size = 2; } @@ -90,9 +83,9 @@ xfs_qm_dquot_logitem_format( */ STATIC void xfs_qm_dquot_logitem_pin( - xfs_dq_logitem_t *logitem) + struct xfs_log_item *lip) { - xfs_dquot_t *dqp = logitem->qli_dquot; + struct xfs_dquot *dqp = DQUOT_ITEM(lip)->qli_dquot; ASSERT(XFS_DQ_IS_LOCKED(dqp)); atomic_inc(&dqp->q_pincount); @@ -104,27 +97,18 @@ xfs_qm_dquot_logitem_pin( * dquot must have been previously pinned with a call to * xfs_qm_dquot_logitem_pin(). */ -/* ARGSUSED */ STATIC void xfs_qm_dquot_logitem_unpin( - xfs_dq_logitem_t *logitem) + struct xfs_log_item *lip, + int remove) { - xfs_dquot_t *dqp = logitem->qli_dquot; + struct xfs_dquot *dqp = DQUOT_ITEM(lip)->qli_dquot; ASSERT(atomic_read(&dqp->q_pincount) > 0); if (atomic_dec_and_test(&dqp->q_pincount)) wake_up(&dqp->q_pinwait); } -/* ARGSUSED */ -STATIC void -xfs_qm_dquot_logitem_unpin_remove( - xfs_dq_logitem_t *logitem, - xfs_trans_t *tp) -{ - xfs_qm_dquot_logitem_unpin(logitem); -} - /* * Given the logitem, this writes the corresponding dquot entry to disk * asynchronously. This is called with the dquot entry securely locked; @@ -133,12 +117,10 @@ xfs_qm_dquot_logitem_unpin_remove( */ STATIC void xfs_qm_dquot_logitem_push( - xfs_dq_logitem_t *logitem) + struct xfs_log_item *lip) { - xfs_dquot_t *dqp; - int error; - - dqp = logitem->qli_dquot; + struct xfs_dquot *dqp = DQUOT_ITEM(lip)->qli_dquot; + int error; ASSERT(XFS_DQ_IS_LOCKED(dqp)); ASSERT(!completion_done(&dqp->q_flush)); @@ -160,27 +142,25 @@ xfs_qm_dquot_logitem_push( xfs_dqunlock(dqp); } -/*ARGSUSED*/ STATIC xfs_lsn_t xfs_qm_dquot_logitem_committed( - xfs_dq_logitem_t *l, + struct xfs_log_item *lip, xfs_lsn_t lsn) { /* * We always re-log the entire dquot when it becomes dirty, * so, the latest copy _is_ the only one that matters. */ - return (lsn); + return lsn; } - /* * This is called to wait for the given dquot to be unpinned. * Most of these pin/unpin routines are plagiarized from inode code. */ void xfs_qm_dqunpin_wait( - xfs_dquot_t *dqp) + struct xfs_dquot *dqp) { ASSERT(XFS_DQ_IS_LOCKED(dqp)); if (atomic_read(&dqp->q_pincount) == 0) @@ -206,13 +186,12 @@ xfs_qm_dqunpin_wait( */ STATIC void xfs_qm_dquot_logitem_pushbuf( - xfs_dq_logitem_t *qip) + struct xfs_log_item *lip) { - xfs_dquot_t *dqp; - xfs_mount_t *mp; - xfs_buf_t *bp; + struct xfs_dq_logitem *qlip = DQUOT_ITEM(lip); + struct xfs_dquot *dqp = qlip->qli_dquot; + struct xfs_buf *bp; - dqp = qip->qli_dquot; ASSERT(XFS_DQ_IS_LOCKED(dqp)); /* @@ -220,22 +199,20 @@ xfs_qm_dquot_logitem_pushbuf( * inode flush completed and the inode was taken off the AIL. * So, just get out. */ - if (completion_done(&dqp->q_flush) || - ((qip->qli_item.li_flags & XFS_LI_IN_AIL) == 0)) { + if (completion_done(&dqp->q_flush) || + !(lip->li_flags & XFS_LI_IN_AIL)) { xfs_dqunlock(dqp); return; } - mp = dqp->q_mount; - bp = xfs_incore(mp->m_ddev_targp, qip->qli_format.qlf_blkno, - mp->m_quotainfo->qi_dqchunklen, XBF_TRYLOCK); + + bp = xfs_incore(dqp->q_mount->m_ddev_targp, qlip->qli_format.qlf_blkno, + dqp->q_mount->m_quotainfo->qi_dqchunklen, XBF_TRYLOCK); xfs_dqunlock(dqp); if (!bp) return; if (XFS_BUF_ISDELAYWRITE(bp)) xfs_buf_delwri_promote(bp); xfs_buf_relse(bp); - return; - } /* @@ -250,15 +227,14 @@ xfs_qm_dquot_logitem_pushbuf( */ STATIC uint xfs_qm_dquot_logitem_trylock( - xfs_dq_logitem_t *qip) + struct xfs_log_item *lip) { - xfs_dquot_t *dqp; + struct xfs_dquot *dqp = DQUOT_ITEM(lip)->qli_dquot; - dqp = qip->qli_dquot; if (atomic_read(&dqp->q_pincount) > 0) return XFS_ITEM_PINNED; - if (! xfs_qm_dqlock_nowait(dqp)) + if (!xfs_qm_dqlock_nowait(dqp)) return XFS_ITEM_LOCKED; if (!xfs_dqflock_nowait(dqp)) { @@ -269,11 +245,10 @@ xfs_qm_dquot_logitem_trylock( return XFS_ITEM_PUSHBUF; } - ASSERT(qip->qli_item.li_flags & XFS_LI_IN_AIL); + ASSERT(lip->li_flags & XFS_LI_IN_AIL); return XFS_ITEM_SUCCESS; } - /* * Unlock the dquot associated with the log item. * Clear the fields of the dquot and dquot log item that @@ -282,12 +257,10 @@ xfs_qm_dquot_logitem_trylock( */ STATIC void xfs_qm_dquot_logitem_unlock( - xfs_dq_logitem_t *ql) + struct xfs_log_item *lip) { - xfs_dquot_t *dqp; + struct xfs_dquot *dqp = DQUOT_ITEM(lip)->qli_dquot; - ASSERT(ql != NULL); - dqp = ql->qli_dquot; ASSERT(XFS_DQ_IS_LOCKED(dqp)); /* @@ -304,43 +277,32 @@ xfs_qm_dquot_logitem_unlock( xfs_dqunlock(dqp); } - /* * this needs to stamp an lsn into the dquot, I think. * rpc's that look at user dquot's would then have to * push on the dependency recorded in the dquot */ -/* ARGSUSED */ STATIC void xfs_qm_dquot_logitem_committing( - xfs_dq_logitem_t *l, + struct xfs_log_item *lip, xfs_lsn_t lsn) { - return; } - /* * This is the ops vector for dquots */ static struct xfs_item_ops xfs_dquot_item_ops = { - .iop_size = (uint(*)(xfs_log_item_t*))xfs_qm_dquot_logitem_size, - .iop_format = (void(*)(xfs_log_item_t*, xfs_log_iovec_t*)) - xfs_qm_dquot_logitem_format, - .iop_pin = (void(*)(xfs_log_item_t*))xfs_qm_dquot_logitem_pin, - .iop_unpin = (void(*)(xfs_log_item_t*))xfs_qm_dquot_logitem_unpin, - .iop_unpin_remove = (void(*)(xfs_log_item_t*, xfs_trans_t*)) - xfs_qm_dquot_logitem_unpin_remove, - .iop_trylock = (uint(*)(xfs_log_item_t*)) - xfs_qm_dquot_logitem_trylock, - .iop_unlock = (void(*)(xfs_log_item_t*))xfs_qm_dquot_logitem_unlock, - .iop_committed = (xfs_lsn_t(*)(xfs_log_item_t*, xfs_lsn_t)) - xfs_qm_dquot_logitem_committed, - .iop_push = (void(*)(xfs_log_item_t*))xfs_qm_dquot_logitem_push, - .iop_pushbuf = (void(*)(xfs_log_item_t*)) - xfs_qm_dquot_logitem_pushbuf, - .iop_committing = (void(*)(xfs_log_item_t*, xfs_lsn_t)) - xfs_qm_dquot_logitem_committing + .iop_size = xfs_qm_dquot_logitem_size, + .iop_format = xfs_qm_dquot_logitem_format, + .iop_pin = xfs_qm_dquot_logitem_pin, + .iop_unpin = xfs_qm_dquot_logitem_unpin, + .iop_trylock = xfs_qm_dquot_logitem_trylock, + .iop_unlock = xfs_qm_dquot_logitem_unlock, + .iop_committed = xfs_qm_dquot_logitem_committed, + .iop_push = xfs_qm_dquot_logitem_push, + .iop_pushbuf = xfs_qm_dquot_logitem_pushbuf, + .iop_committing = xfs_qm_dquot_logitem_committing }; /* @@ -350,10 +312,9 @@ static struct xfs_item_ops xfs_dquot_item_ops = { */ void xfs_qm_dquot_logitem_init( - struct xfs_dquot *dqp) + struct xfs_dquot *dqp) { - xfs_dq_logitem_t *lp; - lp = &dqp->q_logitem; + struct xfs_dq_logitem *lp = &dqp->q_logitem; xfs_log_item_init(dqp->q_mount, &lp->qli_item, XFS_LI_DQUOT, &xfs_dquot_item_ops); @@ -374,16 +335,22 @@ xfs_qm_dquot_logitem_init( /*------------------ QUOTAOFF LOG ITEMS -------------------*/ +static inline struct xfs_qoff_logitem *QOFF_ITEM(struct xfs_log_item *lip) +{ + return container_of(lip, struct xfs_qoff_logitem, qql_item); +} + + /* * This returns the number of iovecs needed to log the given quotaoff item. * We only need 1 iovec for an quotaoff item. It just logs the * quotaoff_log_format structure. */ -/*ARGSUSED*/ STATIC uint -xfs_qm_qoff_logitem_size(xfs_qoff_logitem_t *qf) +xfs_qm_qoff_logitem_size( + struct xfs_log_item *lip) { - return (1); + return 1; } /* @@ -394,53 +361,46 @@ xfs_qm_qoff_logitem_size(xfs_qoff_logitem_t *qf) * slots in the quotaoff item have been filled. */ STATIC void -xfs_qm_qoff_logitem_format(xfs_qoff_logitem_t *qf, - xfs_log_iovec_t *log_vector) +xfs_qm_qoff_logitem_format( + struct xfs_log_item *lip, + struct xfs_log_iovec *log_vector) { - ASSERT(qf->qql_format.qf_type == XFS_LI_QUOTAOFF); + struct xfs_qoff_logitem *qflip = QOFF_ITEM(lip); + + ASSERT(qflip->qql_format.qf_type == XFS_LI_QUOTAOFF); - log_vector->i_addr = (xfs_caddr_t)&(qf->qql_format); + log_vector->i_addr = &qflip->qql_format; log_vector->i_len = sizeof(xfs_qoff_logitem_t); log_vector->i_type = XLOG_REG_TYPE_QUOTAOFF; - qf->qql_format.qf_size = 1; + qflip->qql_format.qf_size = 1; } - /* * Pinning has no meaning for an quotaoff item, so just return. */ -/*ARGSUSED*/ STATIC void -xfs_qm_qoff_logitem_pin(xfs_qoff_logitem_t *qf) +xfs_qm_qoff_logitem_pin( + struct xfs_log_item *lip) { - return; } - /* * Since pinning has no meaning for an quotaoff item, unpinning does * not either. */ -/*ARGSUSED*/ STATIC void -xfs_qm_qoff_logitem_unpin(xfs_qoff_logitem_t *qf) +xfs_qm_qoff_logitem_unpin( + struct xfs_log_item *lip, + int remove) { - return; -} - -/*ARGSUSED*/ -STATIC void -xfs_qm_qoff_logitem_unpin_remove(xfs_qoff_logitem_t *qf, xfs_trans_t *tp) -{ - return; } /* * Quotaoff items have no locking, so just return success. */ -/*ARGSUSED*/ STATIC uint -xfs_qm_qoff_logitem_trylock(xfs_qoff_logitem_t *qf) +xfs_qm_qoff_logitem_trylock( + struct xfs_log_item *lip) { return XFS_ITEM_LOCKED; } @@ -449,53 +409,51 @@ xfs_qm_qoff_logitem_trylock(xfs_qoff_logitem_t *qf) * Quotaoff items have no locking or pushing, so return failure * so that the caller doesn't bother with us. */ -/*ARGSUSED*/ STATIC void -xfs_qm_qoff_logitem_unlock(xfs_qoff_logitem_t *qf) +xfs_qm_qoff_logitem_unlock( + struct xfs_log_item *lip) { - return; } /* * The quotaoff-start-item is logged only once and cannot be moved in the log, * so simply return the lsn at which it's been logged. */ -/*ARGSUSED*/ STATIC xfs_lsn_t -xfs_qm_qoff_logitem_committed(xfs_qoff_logitem_t *qf, xfs_lsn_t lsn) +xfs_qm_qoff_logitem_committed( + struct xfs_log_item *lip, + xfs_lsn_t lsn) { - return (lsn); + return lsn; } /* * There isn't much you can do to push on an quotaoff item. It is simply * stuck waiting for the log to be flushed to disk. */ -/*ARGSUSED*/ STATIC void -xfs_qm_qoff_logitem_push(xfs_qoff_logitem_t *qf) +xfs_qm_qoff_logitem_push( + struct xfs_log_item *lip) { - return; } -/*ARGSUSED*/ STATIC xfs_lsn_t xfs_qm_qoffend_logitem_committed( - xfs_qoff_logitem_t *qfe, - xfs_lsn_t lsn) + struct xfs_log_item *lip, + xfs_lsn_t lsn) { - xfs_qoff_logitem_t *qfs; - struct xfs_ail *ailp; + struct xfs_qoff_logitem *qfe = QOFF_ITEM(lip); + struct xfs_qoff_logitem *qfs = qfe->qql_start_lip; + struct xfs_ail *ailp = qfs->qql_item.li_ailp; - qfs = qfe->qql_start_lip; - ailp = qfs->qql_item.li_ailp; - spin_lock(&ailp->xa_lock); /* * Delete the qoff-start logitem from the AIL. * xfs_trans_ail_delete() drops the AIL lock. */ + spin_lock(&ailp->xa_lock); xfs_trans_ail_delete(ailp, (xfs_log_item_t *)qfs); + kmem_free(qfs); kmem_free(qfe); return (xfs_lsn_t)-1; @@ -515,71 +473,52 @@ xfs_qm_qoffend_logitem_committed( * (truly makes the quotaoff irrevocable). If we do something else, * then maybe we don't need two. */ -/* ARGSUSED */ -STATIC void -xfs_qm_qoff_logitem_committing(xfs_qoff_logitem_t *qip, xfs_lsn_t commit_lsn) -{ - return; -} - -/* ARGSUSED */ STATIC void -xfs_qm_qoffend_logitem_committing(xfs_qoff_logitem_t *qip, xfs_lsn_t commit_lsn) +xfs_qm_qoff_logitem_committing( + struct xfs_log_item *lip, + xfs_lsn_t commit_lsn) { - return; } static struct xfs_item_ops xfs_qm_qoffend_logitem_ops = { - .iop_size = (uint(*)(xfs_log_item_t*))xfs_qm_qoff_logitem_size, - .iop_format = (void(*)(xfs_log_item_t*, xfs_log_iovec_t*)) - xfs_qm_qoff_logitem_format, - .iop_pin = (void(*)(xfs_log_item_t*))xfs_qm_qoff_logitem_pin, - .iop_unpin = (void(*)(xfs_log_item_t*))xfs_qm_qoff_logitem_unpin, - .iop_unpin_remove = (void(*)(xfs_log_item_t*,xfs_trans_t*)) - xfs_qm_qoff_logitem_unpin_remove, - .iop_trylock = (uint(*)(xfs_log_item_t*))xfs_qm_qoff_logitem_trylock, - .iop_unlock = (void(*)(xfs_log_item_t*))xfs_qm_qoff_logitem_unlock, - .iop_committed = (xfs_lsn_t(*)(xfs_log_item_t*, xfs_lsn_t)) - xfs_qm_qoffend_logitem_committed, - .iop_push = (void(*)(xfs_log_item_t*))xfs_qm_qoff_logitem_push, - .iop_pushbuf = NULL, - .iop_committing = (void(*)(xfs_log_item_t*, xfs_lsn_t)) - xfs_qm_qoffend_logitem_committing + .iop_size = xfs_qm_qoff_logitem_size, + .iop_format = xfs_qm_qoff_logitem_format, + .iop_pin = xfs_qm_qoff_logitem_pin, + .iop_unpin = xfs_qm_qoff_logitem_unpin, + .iop_trylock = xfs_qm_qoff_logitem_trylock, + .iop_unlock = xfs_qm_qoff_logitem_unlock, + .iop_committed = xfs_qm_qoffend_logitem_committed, + .iop_push = xfs_qm_qoff_logitem_push, + .iop_committing = xfs_qm_qoff_logitem_committing }; /* * This is the ops vector shared by all quotaoff-start log items. */ static struct xfs_item_ops xfs_qm_qoff_logitem_ops = { - .iop_size = (uint(*)(xfs_log_item_t*))xfs_qm_qoff_logitem_size, - .iop_format = (void(*)(xfs_log_item_t*, xfs_log_iovec_t*)) - xfs_qm_qoff_logitem_format, - .iop_pin = (void(*)(xfs_log_item_t*))xfs_qm_qoff_logitem_pin, - .iop_unpin = (void(*)(xfs_log_item_t*))xfs_qm_qoff_logitem_unpin, - .iop_unpin_remove = (void(*)(xfs_log_item_t*,xfs_trans_t*)) - xfs_qm_qoff_logitem_unpin_remove, - .iop_trylock = (uint(*)(xfs_log_item_t*))xfs_qm_qoff_logitem_trylock, - .iop_unlock = (void(*)(xfs_log_item_t*))xfs_qm_qoff_logitem_unlock, - .iop_committed = (xfs_lsn_t(*)(xfs_log_item_t*, xfs_lsn_t)) - xfs_qm_qoff_logitem_committed, - .iop_push = (void(*)(xfs_log_item_t*))xfs_qm_qoff_logitem_push, - .iop_pushbuf = NULL, - .iop_committing = (void(*)(xfs_log_item_t*, xfs_lsn_t)) - xfs_qm_qoff_logitem_committing + .iop_size = xfs_qm_qoff_logitem_size, + .iop_format = xfs_qm_qoff_logitem_format, + .iop_pin = xfs_qm_qoff_logitem_pin, + .iop_unpin = xfs_qm_qoff_logitem_unpin, + .iop_trylock = xfs_qm_qoff_logitem_trylock, + .iop_unlock = xfs_qm_qoff_logitem_unlock, + .iop_committed = xfs_qm_qoff_logitem_committed, + .iop_push = xfs_qm_qoff_logitem_push, + .iop_committing = xfs_qm_qoff_logitem_committing }; /* * Allocate and initialize an quotaoff item of the correct quota type(s). */ -xfs_qoff_logitem_t * +struct xfs_qoff_logitem * xfs_qm_qoff_logitem_init( - struct xfs_mount *mp, - xfs_qoff_logitem_t *start, - uint flags) + struct xfs_mount *mp, + struct xfs_qoff_logitem *start, + uint flags) { - xfs_qoff_logitem_t *qf; + struct xfs_qoff_logitem *qf; - qf = (xfs_qoff_logitem_t*) kmem_zalloc(sizeof(xfs_qoff_logitem_t), KM_SLEEP); + qf = kmem_zalloc(sizeof(struct xfs_qoff_logitem), KM_SLEEP); xfs_log_item_init(mp, &qf->qql_item, XFS_LI_QUOTAOFF, start ? &xfs_qm_qoffend_logitem_ops : &xfs_qm_qoff_logitem_ops); @@ -587,5 +526,5 @@ xfs_qm_qoff_logitem_init( qf->qql_format.qf_type = XFS_LI_QUOTAOFF; qf->qql_format.qf_flags = flags; qf->qql_start_lip = start; - return (qf); + return qf; } diff --git a/fs/xfs/quota/xfs_qm.c b/fs/xfs/quota/xfs_qm.c index 67c018392d62..9a92407109a1 100644 --- a/fs/xfs/quota/xfs_qm.c +++ b/fs/xfs/quota/xfs_qm.c @@ -23,25 +23,18 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" #include "xfs_alloc.h" -#include "xfs_dmapi.h" #include "xfs_quota.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" -#include "xfs_btree.h" #include "xfs_ialloc.h" #include "xfs_itable.h" #include "xfs_rtalloc.h" #include "xfs_error.h" #include "xfs_bmap.h" -#include "xfs_rw.h" #include "xfs_attr.h" #include "xfs_buf_item.h" #include "xfs_trans_space.h" @@ -1497,7 +1490,7 @@ xfs_qm_dqiterate( maxlblkcnt - lblkno, XFS_BMAPI_METADATA, NULL, - 0, map, &nmaps, NULL, NULL); + 0, map, &nmaps, NULL); xfs_iunlock(qip, XFS_ILOCK_SHARED); if (error) break; @@ -1669,7 +1662,8 @@ xfs_qm_dqusage_adjust( * making us disable quotas for the file system. */ if ((error = xfs_qm_dqget_noattach(ip, &udqp, &gdqp))) { - xfs_iput(ip, XFS_ILOCK_EXCL); + xfs_iunlock(ip, XFS_ILOCK_EXCL); + IRELE(ip); *res = BULKSTAT_RV_GIVEUP; return error; } @@ -1682,7 +1676,8 @@ xfs_qm_dqusage_adjust( * Walk thru the extent list and count the realtime blocks. */ if ((error = xfs_qm_get_rtblks(ip, &rtblks))) { - xfs_iput(ip, XFS_ILOCK_EXCL); + xfs_iunlock(ip, XFS_ILOCK_EXCL); + IRELE(ip); if (udqp) xfs_qm_dqput(udqp); if (gdqp) diff --git a/fs/xfs/quota/xfs_qm_bhv.c b/fs/xfs/quota/xfs_qm_bhv.c index 97b410c12794..bea02d786c5d 100644 --- a/fs/xfs/quota/xfs_qm_bhv.c +++ b/fs/xfs/quota/xfs_qm_bhv.c @@ -23,25 +23,15 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" #include "xfs_alloc.h" -#include "xfs_dmapi.h" #include "xfs_quota.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" -#include "xfs_dinode.h" #include "xfs_inode.h" -#include "xfs_ialloc.h" #include "xfs_itable.h" -#include "xfs_btree.h" #include "xfs_bmap.h" #include "xfs_rtalloc.h" #include "xfs_error.h" -#include "xfs_rw.h" #include "xfs_attr.h" #include "xfs_buf_item.h" #include "xfs_qm.h" diff --git a/fs/xfs/quota/xfs_qm_stats.c b/fs/xfs/quota/xfs_qm_stats.c index 3d1fc79532e2..8671a0b32644 100644 --- a/fs/xfs/quota/xfs_qm_stats.c +++ b/fs/xfs/quota/xfs_qm_stats.c @@ -23,25 +23,15 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" #include "xfs_alloc.h" -#include "xfs_dmapi.h" #include "xfs_quota.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" -#include "xfs_dinode.h" #include "xfs_inode.h" -#include "xfs_ialloc.h" #include "xfs_itable.h" #include "xfs_bmap.h" -#include "xfs_btree.h" #include "xfs_rtalloc.h" #include "xfs_error.h" -#include "xfs_rw.h" #include "xfs_attr.h" #include "xfs_buf_item.h" #include "xfs_qm.h" diff --git a/fs/xfs/quota/xfs_qm_syscalls.c b/fs/xfs/quota/xfs_qm_syscalls.c index b4487764e923..d257eb8557c4 100644 --- a/fs/xfs/quota/xfs_qm_syscalls.c +++ b/fs/xfs/quota/xfs_qm_syscalls.c @@ -26,25 +26,15 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" #include "xfs_alloc.h" -#include "xfs_dmapi.h" #include "xfs_quota.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" -#include "xfs_dinode.h" #include "xfs_inode.h" -#include "xfs_ialloc.h" #include "xfs_itable.h" #include "xfs_bmap.h" -#include "xfs_btree.h" #include "xfs_rtalloc.h" #include "xfs_error.h" -#include "xfs_rw.h" #include "xfs_attr.h" #include "xfs_buf_item.h" #include "xfs_utils.h" @@ -248,40 +238,74 @@ out_unlock: return error; } +STATIC int +xfs_qm_scall_trunc_qfile( + struct xfs_mount *mp, + xfs_ino_t ino) +{ + struct xfs_inode *ip; + struct xfs_trans *tp; + int error; + + if (ino == NULLFSINO) + return 0; + + error = xfs_iget(mp, NULL, ino, 0, 0, &ip); + if (error) + return error; + + xfs_ilock(ip, XFS_IOLOCK_EXCL); + + tp = xfs_trans_alloc(mp, XFS_TRANS_TRUNCATE_FILE); + error = xfs_trans_reserve(tp, 0, XFS_ITRUNCATE_LOG_RES(mp), 0, + XFS_TRANS_PERM_LOG_RES, + XFS_ITRUNCATE_LOG_COUNT); + if (error) { + xfs_trans_cancel(tp, 0); + xfs_iunlock(ip, XFS_IOLOCK_EXCL); + goto out_put; + } + + xfs_ilock(ip, XFS_ILOCK_EXCL); + xfs_trans_ijoin(tp, ip); + + error = xfs_itruncate_finish(&tp, ip, 0, XFS_DATA_FORK, 1); + if (error) { + xfs_trans_cancel(tp, XFS_TRANS_RELEASE_LOG_RES | + XFS_TRANS_ABORT); + goto out_unlock; + } + + xfs_ichgtime(ip, XFS_ICHGTIME_MOD | XFS_ICHGTIME_CHG); + error = xfs_trans_commit(tp, XFS_TRANS_RELEASE_LOG_RES); + +out_unlock: + xfs_iunlock(ip, XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); +out_put: + IRELE(ip); + return error; +} + int xfs_qm_scall_trunc_qfiles( xfs_mount_t *mp, uint flags) { int error = 0, error2 = 0; - xfs_inode_t *qip; if (!xfs_sb_version_hasquota(&mp->m_sb) || flags == 0) { qdprintk("qtrunc flags=%x m_qflags=%x\n", flags, mp->m_qflags); return XFS_ERROR(EINVAL); } - if ((flags & XFS_DQ_USER) && mp->m_sb.sb_uquotino != NULLFSINO) { - error = xfs_iget(mp, NULL, mp->m_sb.sb_uquotino, 0, 0, &qip); - if (!error) { - error = xfs_truncate_file(mp, qip); - IRELE(qip); - } - } - - if ((flags & (XFS_DQ_GROUP|XFS_DQ_PROJ)) && - mp->m_sb.sb_gquotino != NULLFSINO) { - error2 = xfs_iget(mp, NULL, mp->m_sb.sb_gquotino, 0, 0, &qip); - if (!error2) { - error2 = xfs_truncate_file(mp, qip); - IRELE(qip); - } - } + if (flags & XFS_DQ_USER) + error = xfs_qm_scall_trunc_qfile(mp, mp->m_sb.sb_uquotino); + if (flags & (XFS_DQ_GROUP|XFS_DQ_PROJ)) + error2 = xfs_qm_scall_trunc_qfile(mp, mp->m_sb.sb_gquotino); return error ? error : error2; } - /* * Switch on (a given) quota enforcement for a filesystem. This takes * effect immediately. @@ -875,8 +899,9 @@ xfs_dqrele_inode( xfs_qm_dqrele(ip->i_gdquot); ip->i_gdquot = NULL; } - xfs_iput(ip, XFS_ILOCK_EXCL); + xfs_iunlock(ip, XFS_ILOCK_EXCL); + IRELE(ip); return 0; } @@ -1143,7 +1168,8 @@ xfs_qm_internalqcheck_adjust( * of those now. */ if (! ipreleased) { - xfs_iput(ip, lock_flags); + xfs_iunlock(ip, lock_flags); + IRELE(ip); ipreleased = B_TRUE; goto again; } @@ -1160,7 +1186,8 @@ xfs_qm_internalqcheck_adjust( ASSERT(gd); xfs_qm_internalqcheck_dqadjust(ip, gd); } - xfs_iput(ip, lock_flags); + xfs_iunlock(ip, lock_flags); + IRELE(ip); *res = BULKSTAT_RV_DIDONE; return (0); } diff --git a/fs/xfs/quota/xfs_trans_dquot.c b/fs/xfs/quota/xfs_trans_dquot.c index 061d827da33c..7de91d1b75c0 100644 --- a/fs/xfs/quota/xfs_trans_dquot.c +++ b/fs/xfs/quota/xfs_trans_dquot.c @@ -23,25 +23,15 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" #include "xfs_alloc.h" -#include "xfs_dmapi.h" #include "xfs_quota.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" -#include "xfs_attr_sf.h" -#include "xfs_dir2_sf.h" -#include "xfs_dinode.h" #include "xfs_inode.h" -#include "xfs_ialloc.h" #include "xfs_itable.h" -#include "xfs_btree.h" #include "xfs_bmap.h" #include "xfs_rtalloc.h" #include "xfs_error.h" -#include "xfs_rw.h" #include "xfs_attr.h" #include "xfs_buf_item.h" #include "xfs_trans_priv.h" @@ -59,16 +49,14 @@ xfs_trans_dqjoin( xfs_trans_t *tp, xfs_dquot_t *dqp) { - xfs_dq_logitem_t *lp = &dqp->q_logitem; - ASSERT(dqp->q_transp != tp); ASSERT(XFS_DQ_IS_LOCKED(dqp)); - ASSERT(lp->qli_dquot == dqp); + ASSERT(dqp->q_logitem.qli_dquot == dqp); /* * Get a log_item_desc to point at the new item. */ - (void) xfs_trans_add_item(tp, (xfs_log_item_t*)(lp)); + xfs_trans_add_item(tp, &dqp->q_logitem.qli_item); /* * Initialize i_transp so we can later determine if this dquot is @@ -93,16 +81,11 @@ xfs_trans_log_dquot( xfs_trans_t *tp, xfs_dquot_t *dqp) { - xfs_log_item_desc_t *lidp; - ASSERT(dqp->q_transp == tp); ASSERT(XFS_DQ_IS_LOCKED(dqp)); - lidp = xfs_trans_find_item(tp, (xfs_log_item_t*)(&dqp->q_logitem)); - ASSERT(lidp != NULL); - tp->t_flags |= XFS_TRANS_DIRTY; - lidp->lid_flags |= XFS_LID_DIRTY; + dqp->q_logitem.qli_item.li_desc->lid_flags |= XFS_LID_DIRTY; } /* @@ -874,9 +857,8 @@ xfs_trans_get_qoff_item( /* * Get a log_item_desc to point at the new item. */ - (void) xfs_trans_add_item(tp, (xfs_log_item_t*)q); - - return (q); + xfs_trans_add_item(tp, &q->qql_item); + return q; } @@ -890,13 +872,8 @@ xfs_trans_log_quotaoff_item( xfs_trans_t *tp, xfs_qoff_logitem_t *qlp) { - xfs_log_item_desc_t *lidp; - - lidp = xfs_trans_find_item(tp, (xfs_log_item_t *)qlp); - ASSERT(lidp != NULL); - tp->t_flags |= XFS_TRANS_DIRTY; - lidp->lid_flags |= XFS_LID_DIRTY; + qlp->qql_item.li_desc->lid_flags |= XFS_LID_DIRTY; } STATIC void diff --git a/fs/xfs/support/debug.c b/fs/xfs/support/debug.c index 3f3610a7ee05..975aa10e1a47 100644 --- a/fs/xfs/support/debug.c +++ b/fs/xfs/support/debug.c @@ -22,7 +22,6 @@ #include "xfs_sb.h" #include "xfs_inum.h" #include "xfs_ag.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_error.h" diff --git a/fs/xfs/xfs_alloc.c b/fs/xfs/xfs_alloc.c index a7fbe8a99b12..af168faccc7a 100644 --- a/fs/xfs/xfs_alloc.c +++ b/fs/xfs/xfs_alloc.c @@ -24,18 +24,13 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_btree.h" -#include "xfs_ialloc.h" #include "xfs_alloc.h" #include "xfs_error.h" #include "xfs_trace.h" @@ -688,8 +683,6 @@ xfs_alloc_ag_vextent_near( xfs_agblock_t ltbno; /* start bno of left side entry */ xfs_agblock_t ltbnoa; /* aligned ... */ xfs_extlen_t ltdiff; /* difference to left side entry */ - /*REFERENCED*/ - xfs_agblock_t ltend; /* end bno of left side entry */ xfs_extlen_t ltlen; /* length of left side entry */ xfs_extlen_t ltlena; /* aligned ... */ xfs_agblock_t ltnew; /* useful start bno of left side */ @@ -814,8 +807,7 @@ xfs_alloc_ag_vextent_near( if ((error = xfs_alloc_get_rec(cnt_cur, <bno, <len, &i))) goto error0; XFS_WANT_CORRUPTED_GOTO(i == 1, error0); - ltend = ltbno + ltlen; - ASSERT(ltend <= be32_to_cpu(XFS_BUF_TO_AGF(args->agbp)->agf_length)); + ASSERT(ltbno + ltlen <= be32_to_cpu(XFS_BUF_TO_AGF(args->agbp)->agf_length)); args->len = blen; if (!xfs_alloc_fix_minleft(args)) { xfs_btree_del_cursor(cnt_cur, XFS_BTREE_NOERROR); @@ -828,7 +820,7 @@ xfs_alloc_ag_vextent_near( */ args->agbno = bnew; ASSERT(bnew >= ltbno); - ASSERT(bnew + blen <= ltend); + ASSERT(bnew + blen <= ltbno + ltlen); /* * Set up a cursor for the by-bno tree. */ @@ -1157,7 +1149,6 @@ xfs_alloc_ag_vextent_near( /* * Fix up the length and compute the useful address. */ - ltend = ltbno + ltlen; args->len = XFS_EXTLEN_MIN(ltlena, args->maxlen); xfs_alloc_fix_len(args); if (!xfs_alloc_fix_minleft(args)) { @@ -1170,7 +1161,7 @@ xfs_alloc_ag_vextent_near( (void)xfs_alloc_compute_diff(args->agbno, rlen, args->alignment, ltbno, ltlen, <new); ASSERT(ltnew >= ltbno); - ASSERT(ltnew + rlen <= ltend); + ASSERT(ltnew + rlen <= ltbno + ltlen); ASSERT(ltnew + rlen <= be32_to_cpu(XFS_BUF_TO_AGF(args->agbp)->agf_length)); args->agbno = ltnew; if ((error = xfs_alloc_fixup_trees(cnt_cur, bno_cur_lt, ltbno, ltlen, diff --git a/fs/xfs/xfs_alloc.h b/fs/xfs/xfs_alloc.h index 6d05199b667c..895009a97271 100644 --- a/fs/xfs/xfs_alloc.h +++ b/fs/xfs/xfs_alloc.h @@ -27,16 +27,16 @@ struct xfs_busy_extent; /* * Freespace allocation types. Argument to xfs_alloc_[v]extent. */ -typedef enum xfs_alloctype -{ - XFS_ALLOCTYPE_ANY_AG, /* allocate anywhere, use rotor */ - XFS_ALLOCTYPE_FIRST_AG, /* ... start at ag 0 */ - XFS_ALLOCTYPE_START_AG, /* anywhere, start in this a.g. */ - XFS_ALLOCTYPE_THIS_AG, /* anywhere in this a.g. */ - XFS_ALLOCTYPE_START_BNO, /* near this block else anywhere */ - XFS_ALLOCTYPE_NEAR_BNO, /* in this a.g. and near this block */ - XFS_ALLOCTYPE_THIS_BNO /* at exactly this block */ -} xfs_alloctype_t; +#define XFS_ALLOCTYPE_ANY_AG 0x01 /* allocate anywhere, use rotor */ +#define XFS_ALLOCTYPE_FIRST_AG 0x02 /* ... start at ag 0 */ +#define XFS_ALLOCTYPE_START_AG 0x04 /* anywhere, start in this a.g. */ +#define XFS_ALLOCTYPE_THIS_AG 0x08 /* anywhere in this a.g. */ +#define XFS_ALLOCTYPE_START_BNO 0x10 /* near this block else anywhere */ +#define XFS_ALLOCTYPE_NEAR_BNO 0x20 /* in this a.g. and near this block */ +#define XFS_ALLOCTYPE_THIS_BNO 0x40 /* at exactly this block */ + +/* this should become an enum again when the tracing code is fixed */ +typedef unsigned int xfs_alloctype_t; #define XFS_ALLOC_TYPES \ { XFS_ALLOCTYPE_ANY_AG, "ANY_AG" }, \ diff --git a/fs/xfs/xfs_alloc_btree.c b/fs/xfs/xfs_alloc_btree.c index 83f494218759..97f7328967fd 100644 --- a/fs/xfs/xfs_alloc_btree.c +++ b/fs/xfs/xfs_alloc_btree.c @@ -24,19 +24,14 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_btree.h" #include "xfs_btree_trace.h" -#include "xfs_ialloc.h" #include "xfs_alloc.h" #include "xfs_error.h" #include "xfs_trace.h" diff --git a/fs/xfs/xfs_attr.c b/fs/xfs/xfs_attr.c index b9c196a53c42..c2568242a901 100644 --- a/fs/xfs/xfs_attr.c +++ b/fs/xfs/xfs_attr.c @@ -25,19 +25,13 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_da_btree.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" #include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_alloc.h" -#include "xfs_btree.h" #include "xfs_inode_item.h" #include "xfs_bmap.h" #include "xfs_attr.h" @@ -325,8 +319,7 @@ xfs_attr_set_int( return (error); } - xfs_trans_ijoin(args.trans, dp, XFS_ILOCK_EXCL); - xfs_trans_ihold(args.trans, dp); + xfs_trans_ijoin(args.trans, dp); /* * If the attribute list is non-existent or a shortform list, @@ -396,10 +389,8 @@ xfs_attr_set_int( * bmap_finish() may have committed the last trans and started * a new one. We need the inode to be in all transactions. */ - if (committed) { - xfs_trans_ijoin(args.trans, dp, XFS_ILOCK_EXCL); - xfs_trans_ihold(args.trans, dp); - } + if (committed) + xfs_trans_ijoin(args.trans, dp); /* * Commit the leaf transformation. We'll need another (linked) @@ -544,8 +535,7 @@ xfs_attr_remove_int(xfs_inode_t *dp, struct xfs_name *name, int flags) * No need to make quota reservations here. We expect to release some * blocks not allocate in the common case. */ - xfs_trans_ijoin(args.trans, dp, XFS_ILOCK_EXCL); - xfs_trans_ihold(args.trans, dp); + xfs_trans_ijoin(args.trans, dp); /* * Decide on what work routines to call based on the inode size. @@ -821,8 +811,7 @@ xfs_attr_inactive(xfs_inode_t *dp) * No need to make quota reservations here. We expect to release some * blocks, not allocate, in the common case. */ - xfs_trans_ijoin(trans, dp, XFS_ILOCK_EXCL); - xfs_trans_ihold(trans, dp); + xfs_trans_ijoin(trans, dp); /* * Decide on what work routines to call based on the inode size. @@ -981,10 +970,8 @@ xfs_attr_leaf_addname(xfs_da_args_t *args) * bmap_finish() may have committed the last trans and started * a new one. We need the inode to be in all transactions. */ - if (committed) { - xfs_trans_ijoin(args->trans, dp, XFS_ILOCK_EXCL); - xfs_trans_ihold(args->trans, dp); - } + if (committed) + xfs_trans_ijoin(args->trans, dp); /* * Commit the current trans (including the inode) and start @@ -1085,10 +1072,8 @@ xfs_attr_leaf_addname(xfs_da_args_t *args) * and started a new one. We need the inode to be * in all transactions. */ - if (committed) { - xfs_trans_ijoin(args->trans, dp, XFS_ILOCK_EXCL); - xfs_trans_ihold(args->trans, dp); - } + if (committed) + xfs_trans_ijoin(args->trans, dp); } else xfs_da_buf_done(bp); @@ -1161,10 +1146,8 @@ xfs_attr_leaf_removename(xfs_da_args_t *args) * bmap_finish() may have committed the last trans and started * a new one. We need the inode to be in all transactions. */ - if (committed) { - xfs_trans_ijoin(args->trans, dp, XFS_ILOCK_EXCL); - xfs_trans_ihold(args->trans, dp); - } + if (committed) + xfs_trans_ijoin(args->trans, dp); } else xfs_da_buf_done(bp); return(0); @@ -1317,10 +1300,8 @@ restart: * and started a new one. We need the inode to be * in all transactions. */ - if (committed) { - xfs_trans_ijoin(args->trans, dp, XFS_ILOCK_EXCL); - xfs_trans_ihold(args->trans, dp); - } + if (committed) + xfs_trans_ijoin(args->trans, dp); /* * Commit the node conversion and start the next @@ -1356,10 +1337,8 @@ restart: * bmap_finish() may have committed the last trans and started * a new one. We need the inode to be in all transactions. */ - if (committed) { - xfs_trans_ijoin(args->trans, dp, XFS_ILOCK_EXCL); - xfs_trans_ihold(args->trans, dp); - } + if (committed) + xfs_trans_ijoin(args->trans, dp); } else { /* * Addition succeeded, update Btree hashvals. @@ -1470,10 +1449,8 @@ restart: * and started a new one. We need the inode to be * in all transactions. */ - if (committed) { - xfs_trans_ijoin(args->trans, dp, XFS_ILOCK_EXCL); - xfs_trans_ihold(args->trans, dp); - } + if (committed) + xfs_trans_ijoin(args->trans, dp); } /* @@ -1604,10 +1581,8 @@ xfs_attr_node_removename(xfs_da_args_t *args) * bmap_finish() may have committed the last trans and started * a new one. We need the inode to be in all transactions. */ - if (committed) { - xfs_trans_ijoin(args->trans, dp, XFS_ILOCK_EXCL); - xfs_trans_ihold(args->trans, dp); - } + if (committed) + xfs_trans_ijoin(args->trans, dp); /* * Commit the Btree join operation and start a new trans. @@ -1658,10 +1633,8 @@ xfs_attr_node_removename(xfs_da_args_t *args) * and started a new one. We need the inode to be * in all transactions. */ - if (committed) { - xfs_trans_ijoin(args->trans, dp, XFS_ILOCK_EXCL); - xfs_trans_ihold(args->trans, dp); - } + if (committed) + xfs_trans_ijoin(args->trans, dp); } else xfs_da_brelse(args->trans, bp); } @@ -2004,7 +1977,7 @@ xfs_attr_rmtval_get(xfs_da_args_t *args) error = xfs_bmapi(args->trans, args->dp, (xfs_fileoff_t)lblkno, args->rmtblkcnt, XFS_BMAPI_ATTRFORK | XFS_BMAPI_METADATA, - NULL, 0, map, &nmap, NULL, NULL); + NULL, 0, map, &nmap, NULL); if (error) return(error); ASSERT(nmap >= 1); @@ -2083,7 +2056,7 @@ xfs_attr_rmtval_set(xfs_da_args_t *args) XFS_BMAPI_ATTRFORK | XFS_BMAPI_METADATA | XFS_BMAPI_WRITE, args->firstblock, args->total, &map, &nmap, - args->flist, NULL); + args->flist); if (!error) { error = xfs_bmap_finish(&args->trans, args->flist, &committed); @@ -2099,10 +2072,8 @@ xfs_attr_rmtval_set(xfs_da_args_t *args) * bmap_finish() may have committed the last trans and started * a new one. We need the inode to be in all transactions. */ - if (committed) { - xfs_trans_ijoin(args->trans, dp, XFS_ILOCK_EXCL); - xfs_trans_ihold(args->trans, dp); - } + if (committed) + xfs_trans_ijoin(args->trans, dp); ASSERT(nmap == 1); ASSERT((map.br_startblock != DELAYSTARTBLOCK) && @@ -2136,7 +2107,7 @@ xfs_attr_rmtval_set(xfs_da_args_t *args) args->rmtblkcnt, XFS_BMAPI_ATTRFORK | XFS_BMAPI_METADATA, args->firstblock, 0, &map, &nmap, - NULL, NULL); + NULL); if (error) { return(error); } @@ -2201,7 +2172,7 @@ xfs_attr_rmtval_remove(xfs_da_args_t *args) args->rmtblkcnt, XFS_BMAPI_ATTRFORK | XFS_BMAPI_METADATA, args->firstblock, 0, &map, &nmap, - args->flist, NULL); + args->flist); if (error) { return(error); } @@ -2239,7 +2210,7 @@ xfs_attr_rmtval_remove(xfs_da_args_t *args) error = xfs_bunmapi(args->trans, args->dp, lblkno, blkcnt, XFS_BMAPI_ATTRFORK | XFS_BMAPI_METADATA, 1, args->firstblock, args->flist, - NULL, &done); + &done); if (!error) { error = xfs_bmap_finish(&args->trans, args->flist, &committed); @@ -2255,10 +2226,8 @@ xfs_attr_rmtval_remove(xfs_da_args_t *args) * bmap_finish() may have committed the last trans and started * a new one. We need the inode to be in all transactions. */ - if (committed) { - xfs_trans_ijoin(args->trans, args->dp, XFS_ILOCK_EXCL); - xfs_trans_ihold(args->trans, args->dp); - } + if (committed) + xfs_trans_ijoin(args->trans, args->dp); /* * Close out trans and start the next one in the chain. diff --git a/fs/xfs/xfs_attr_leaf.c b/fs/xfs/xfs_attr_leaf.c index a90ce74fc256..a6cff8edcdb6 100644 --- a/fs/xfs/xfs_attr_leaf.c +++ b/fs/xfs/xfs_attr_leaf.c @@ -24,8 +24,6 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_da_btree.h" #include "xfs_bmap_btree.h" @@ -33,7 +31,6 @@ #include "xfs_ialloc_btree.h" #include "xfs_alloc.h" #include "xfs_btree.h" -#include "xfs_dir2_sf.h" #include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" @@ -2931,7 +2928,7 @@ xfs_attr_leaf_freextent(xfs_trans_t **trans, xfs_inode_t *dp, nmap = 1; error = xfs_bmapi(*trans, dp, (xfs_fileoff_t)tblkno, tblkcnt, XFS_BMAPI_ATTRFORK | XFS_BMAPI_METADATA, - NULL, 0, &map, &nmap, NULL, NULL); + NULL, 0, &map, &nmap, NULL); if (error) { return(error); } diff --git a/fs/xfs/xfs_bmap.c b/fs/xfs/xfs_bmap.c index 99587ded043f..23f14e595c18 100644 --- a/fs/xfs/xfs_bmap.c +++ b/fs/xfs/xfs_bmap.c @@ -30,13 +30,10 @@ #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" #include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_btree.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" -#include "xfs_ialloc.h" #include "xfs_itable.h" #include "xfs_dir2_data.h" #include "xfs_dir2_leaf.h" @@ -104,7 +101,6 @@ xfs_bmap_add_extent( xfs_fsblock_t *first, /* pointer to firstblock variable */ xfs_bmap_free_t *flist, /* list of extents to be freed */ int *logflagsp, /* inode logging flags */ - xfs_extdelta_t *delta, /* Change made to incore extents */ int whichfork, /* data or attr fork */ int rsvd); /* OK to allocate reserved blocks */ @@ -122,7 +118,6 @@ xfs_bmap_add_extent_delay_real( xfs_fsblock_t *first, /* pointer to firstblock variable */ xfs_bmap_free_t *flist, /* list of extents to be freed */ int *logflagsp, /* inode logging flags */ - xfs_extdelta_t *delta, /* Change made to incore extents */ int rsvd); /* OK to allocate reserved blocks */ /* @@ -135,7 +130,6 @@ xfs_bmap_add_extent_hole_delay( xfs_extnum_t idx, /* extent number to update/insert */ xfs_bmbt_irec_t *new, /* new data to add to file extents */ int *logflagsp,/* inode logging flags */ - xfs_extdelta_t *delta, /* Change made to incore extents */ int rsvd); /* OK to allocate reserved blocks */ /* @@ -149,7 +143,6 @@ xfs_bmap_add_extent_hole_real( xfs_btree_cur_t *cur, /* if null, not a btree */ xfs_bmbt_irec_t *new, /* new data to add to file extents */ int *logflagsp, /* inode logging flags */ - xfs_extdelta_t *delta, /* Change made to incore extents */ int whichfork); /* data or attr fork */ /* @@ -162,8 +155,7 @@ xfs_bmap_add_extent_unwritten_real( xfs_extnum_t idx, /* extent number to update/insert */ xfs_btree_cur_t **curp, /* if *curp is null, not a btree */ xfs_bmbt_irec_t *new, /* new data to add to file extents */ - int *logflagsp, /* inode logging flags */ - xfs_extdelta_t *delta); /* Change made to incore extents */ + int *logflagsp); /* inode logging flags */ /* * xfs_bmap_alloc is called by xfs_bmapi to allocate an extent for a file. @@ -200,7 +192,6 @@ xfs_bmap_del_extent( xfs_btree_cur_t *cur, /* if null, not a btree */ xfs_bmbt_irec_t *new, /* new data to add to file extents */ int *logflagsp,/* inode logging flags */ - xfs_extdelta_t *delta, /* Change made to incore extents */ int whichfork, /* data or attr fork */ int rsvd); /* OK to allocate reserved blocks */ @@ -489,7 +480,6 @@ xfs_bmap_add_extent( xfs_fsblock_t *first, /* pointer to firstblock variable */ xfs_bmap_free_t *flist, /* list of extents to be freed */ int *logflagsp, /* inode logging flags */ - xfs_extdelta_t *delta, /* Change made to incore extents */ int whichfork, /* data or attr fork */ int rsvd) /* OK to use reserved data blocks */ { @@ -524,15 +514,6 @@ xfs_bmap_add_extent( logflags = XFS_ILOG_CORE | xfs_ilog_fext(whichfork); } else logflags = 0; - /* DELTA: single new extent */ - if (delta) { - if (delta->xed_startoff > new->br_startoff) - delta->xed_startoff = new->br_startoff; - if (delta->xed_blockcount < - new->br_startoff + new->br_blockcount) - delta->xed_blockcount = new->br_startoff + - new->br_blockcount; - } } /* * Any kind of new delayed allocation goes here. @@ -542,7 +523,7 @@ xfs_bmap_add_extent( ASSERT((cur->bc_private.b.flags & XFS_BTCUR_BPRV_WASDEL) == 0); if ((error = xfs_bmap_add_extent_hole_delay(ip, idx, new, - &logflags, delta, rsvd))) + &logflags, rsvd))) goto done; } /* @@ -553,7 +534,7 @@ xfs_bmap_add_extent( ASSERT((cur->bc_private.b.flags & XFS_BTCUR_BPRV_WASDEL) == 0); if ((error = xfs_bmap_add_extent_hole_real(ip, idx, cur, new, - &logflags, delta, whichfork))) + &logflags, whichfork))) goto done; } else { xfs_bmbt_irec_t prev; /* old extent at offset idx */ @@ -578,17 +559,17 @@ xfs_bmap_add_extent( XFS_BTCUR_BPRV_WASDEL); if ((error = xfs_bmap_add_extent_delay_real(ip, idx, &cur, new, &da_new, first, flist, - &logflags, delta, rsvd))) + &logflags, rsvd))) goto done; } else if (new->br_state == XFS_EXT_NORM) { ASSERT(new->br_state == XFS_EXT_NORM); if ((error = xfs_bmap_add_extent_unwritten_real( - ip, idx, &cur, new, &logflags, delta))) + ip, idx, &cur, new, &logflags))) goto done; } else { ASSERT(new->br_state == XFS_EXT_UNWRITTEN); if ((error = xfs_bmap_add_extent_unwritten_real( - ip, idx, &cur, new, &logflags, delta))) + ip, idx, &cur, new, &logflags))) goto done; } ASSERT(*curp == cur || *curp == NULL); @@ -601,7 +582,7 @@ xfs_bmap_add_extent( ASSERT((cur->bc_private.b.flags & XFS_BTCUR_BPRV_WASDEL) == 0); if ((error = xfs_bmap_add_extent_hole_real(ip, idx, cur, - new, &logflags, delta, whichfork))) + new, &logflags, whichfork))) goto done; } } @@ -666,7 +647,6 @@ xfs_bmap_add_extent_delay_real( xfs_fsblock_t *first, /* pointer to firstblock variable */ xfs_bmap_free_t *flist, /* list of extents to be freed */ int *logflagsp, /* inode logging flags */ - xfs_extdelta_t *delta, /* Change made to incore extents */ int rsvd) /* OK to use reserved data block allocation */ { xfs_btree_cur_t *cur; /* btree cursor */ @@ -797,11 +777,6 @@ xfs_bmap_add_extent_delay_real( goto done; } *dnew = 0; - /* DELTA: Three in-core extents are replaced by one. */ - temp = LEFT.br_startoff; - temp2 = LEFT.br_blockcount + - PREV.br_blockcount + - RIGHT.br_blockcount; break; case BMAP_LEFT_FILLING | BMAP_RIGHT_FILLING | BMAP_LEFT_CONTIG: @@ -832,10 +807,6 @@ xfs_bmap_add_extent_delay_real( goto done; } *dnew = 0; - /* DELTA: Two in-core extents are replaced by one. */ - temp = LEFT.br_startoff; - temp2 = LEFT.br_blockcount + - PREV.br_blockcount; break; case BMAP_LEFT_FILLING | BMAP_RIGHT_FILLING | BMAP_RIGHT_CONTIG: @@ -867,10 +838,6 @@ xfs_bmap_add_extent_delay_real( goto done; } *dnew = 0; - /* DELTA: Two in-core extents are replaced by one. */ - temp = PREV.br_startoff; - temp2 = PREV.br_blockcount + - RIGHT.br_blockcount; break; case BMAP_LEFT_FILLING | BMAP_RIGHT_FILLING: @@ -900,9 +867,6 @@ xfs_bmap_add_extent_delay_real( XFS_WANT_CORRUPTED_GOTO(i == 1, done); } *dnew = 0; - /* DELTA: The in-core extent described by new changed type. */ - temp = new->br_startoff; - temp2 = new->br_blockcount; break; case BMAP_LEFT_FILLING | BMAP_LEFT_CONTIG: @@ -942,10 +906,6 @@ xfs_bmap_add_extent_delay_real( xfs_bmbt_set_startblock(ep, nullstartblock((int)temp)); trace_xfs_bmap_post_update(ip, idx, state, _THIS_IP_); *dnew = temp; - /* DELTA: The boundary between two in-core extents moved. */ - temp = LEFT.br_startoff; - temp2 = LEFT.br_blockcount + - PREV.br_blockcount; break; case BMAP_LEFT_FILLING: @@ -990,9 +950,6 @@ xfs_bmap_add_extent_delay_real( xfs_bmbt_set_startblock(ep, nullstartblock((int)temp)); trace_xfs_bmap_post_update(ip, idx + 1, state, _THIS_IP_); *dnew = temp; - /* DELTA: One in-core extent is split in two. */ - temp = PREV.br_startoff; - temp2 = PREV.br_blockcount; break; case BMAP_RIGHT_FILLING | BMAP_RIGHT_CONTIG: @@ -1031,10 +988,6 @@ xfs_bmap_add_extent_delay_real( xfs_bmbt_set_startblock(ep, nullstartblock((int)temp)); trace_xfs_bmap_post_update(ip, idx, state, _THIS_IP_); *dnew = temp; - /* DELTA: The boundary between two in-core extents moved. */ - temp = PREV.br_startoff; - temp2 = PREV.br_blockcount + - RIGHT.br_blockcount; break; case BMAP_RIGHT_FILLING: @@ -1078,9 +1031,6 @@ xfs_bmap_add_extent_delay_real( xfs_bmbt_set_startblock(ep, nullstartblock((int)temp)); trace_xfs_bmap_post_update(ip, idx, state, _THIS_IP_); *dnew = temp; - /* DELTA: One in-core extent is split in two. */ - temp = PREV.br_startoff; - temp2 = PREV.br_blockcount; break; case 0: @@ -1161,9 +1111,6 @@ xfs_bmap_add_extent_delay_real( nullstartblock((int)temp2)); trace_xfs_bmap_post_update(ip, idx + 2, state, _THIS_IP_); *dnew = temp + temp2; - /* DELTA: One in-core extent is split in three. */ - temp = PREV.br_startoff; - temp2 = PREV.br_blockcount; break; case BMAP_LEFT_FILLING | BMAP_LEFT_CONTIG | BMAP_RIGHT_CONTIG: @@ -1179,13 +1126,6 @@ xfs_bmap_add_extent_delay_real( ASSERT(0); } *curp = cur; - if (delta) { - temp2 += temp; - if (delta->xed_startoff > temp) - delta->xed_startoff = temp; - if (delta->xed_blockcount < temp2) - delta->xed_blockcount = temp2; - } done: *logflagsp = rval; return error; @@ -1204,8 +1144,7 @@ xfs_bmap_add_extent_unwritten_real( xfs_extnum_t idx, /* extent number to update/insert */ xfs_btree_cur_t **curp, /* if *curp is null, not a btree */ xfs_bmbt_irec_t *new, /* new data to add to file extents */ - int *logflagsp, /* inode logging flags */ - xfs_extdelta_t *delta) /* Change made to incore extents */ + int *logflagsp) /* inode logging flags */ { xfs_btree_cur_t *cur; /* btree cursor */ xfs_bmbt_rec_host_t *ep; /* extent entry for idx */ @@ -1219,8 +1158,6 @@ xfs_bmap_add_extent_unwritten_real( /* left is 0, right is 1, prev is 2 */ int rval=0; /* return value (logging flags) */ int state = 0;/* state bits, accessed thru macros */ - xfs_filblks_t temp=0; - xfs_filblks_t temp2=0; #define LEFT r[0] #define RIGHT r[1] @@ -1341,11 +1278,6 @@ xfs_bmap_add_extent_unwritten_real( RIGHT.br_blockcount, LEFT.br_state))) goto done; } - /* DELTA: Three in-core extents are replaced by one. */ - temp = LEFT.br_startoff; - temp2 = LEFT.br_blockcount + - PREV.br_blockcount + - RIGHT.br_blockcount; break; case BMAP_LEFT_FILLING | BMAP_RIGHT_FILLING | BMAP_LEFT_CONTIG: @@ -1382,10 +1314,6 @@ xfs_bmap_add_extent_unwritten_real( LEFT.br_state))) goto done; } - /* DELTA: Two in-core extents are replaced by one. */ - temp = LEFT.br_startoff; - temp2 = LEFT.br_blockcount + - PREV.br_blockcount; break; case BMAP_LEFT_FILLING | BMAP_RIGHT_FILLING | BMAP_RIGHT_CONTIG: @@ -1422,10 +1350,6 @@ xfs_bmap_add_extent_unwritten_real( newext))) goto done; } - /* DELTA: Two in-core extents are replaced by one. */ - temp = PREV.br_startoff; - temp2 = PREV.br_blockcount + - RIGHT.br_blockcount; break; case BMAP_LEFT_FILLING | BMAP_RIGHT_FILLING: @@ -1453,9 +1377,6 @@ xfs_bmap_add_extent_unwritten_real( newext))) goto done; } - /* DELTA: The in-core extent described by new changed type. */ - temp = new->br_startoff; - temp2 = new->br_blockcount; break; case BMAP_LEFT_FILLING | BMAP_LEFT_CONTIG: @@ -1501,10 +1422,6 @@ xfs_bmap_add_extent_unwritten_real( LEFT.br_state)) goto done; } - /* DELTA: The boundary between two in-core extents moved. */ - temp = LEFT.br_startoff; - temp2 = LEFT.br_blockcount + - PREV.br_blockcount; break; case BMAP_LEFT_FILLING: @@ -1544,9 +1461,6 @@ xfs_bmap_add_extent_unwritten_real( goto done; XFS_WANT_CORRUPTED_GOTO(i == 1, done); } - /* DELTA: One in-core extent is split in two. */ - temp = PREV.br_startoff; - temp2 = PREV.br_blockcount; break; case BMAP_RIGHT_FILLING | BMAP_RIGHT_CONTIG: @@ -1587,10 +1501,6 @@ xfs_bmap_add_extent_unwritten_real( newext))) goto done; } - /* DELTA: The boundary between two in-core extents moved. */ - temp = PREV.br_startoff; - temp2 = PREV.br_blockcount + - RIGHT.br_blockcount; break; case BMAP_RIGHT_FILLING: @@ -1630,9 +1540,6 @@ xfs_bmap_add_extent_unwritten_real( goto done; XFS_WANT_CORRUPTED_GOTO(i == 1, done); } - /* DELTA: One in-core extent is split in two. */ - temp = PREV.br_startoff; - temp2 = PREV.br_blockcount; break; case 0: @@ -1692,9 +1599,6 @@ xfs_bmap_add_extent_unwritten_real( goto done; XFS_WANT_CORRUPTED_GOTO(i == 1, done); } - /* DELTA: One in-core extent is split in three. */ - temp = PREV.br_startoff; - temp2 = PREV.br_blockcount; break; case BMAP_LEFT_FILLING | BMAP_LEFT_CONTIG | BMAP_RIGHT_CONTIG: @@ -1710,13 +1614,6 @@ xfs_bmap_add_extent_unwritten_real( ASSERT(0); } *curp = cur; - if (delta) { - temp2 += temp; - if (delta->xed_startoff > temp) - delta->xed_startoff = temp; - if (delta->xed_blockcount < temp2) - delta->xed_blockcount = temp2; - } done: *logflagsp = rval; return error; @@ -1736,7 +1633,6 @@ xfs_bmap_add_extent_hole_delay( xfs_extnum_t idx, /* extent number to update/insert */ xfs_bmbt_irec_t *new, /* new data to add to file extents */ int *logflagsp, /* inode logging flags */ - xfs_extdelta_t *delta, /* Change made to incore extents */ int rsvd) /* OK to allocate reserved blocks */ { xfs_bmbt_rec_host_t *ep; /* extent record for idx */ @@ -1747,7 +1643,6 @@ xfs_bmap_add_extent_hole_delay( xfs_bmbt_irec_t right; /* right neighbor extent entry */ int state; /* state bits, accessed thru macros */ xfs_filblks_t temp=0; /* temp for indirect calculations */ - xfs_filblks_t temp2=0; ifp = XFS_IFORK_PTR(ip, XFS_DATA_FORK); ep = xfs_iext_get_ext(ifp, idx); @@ -1819,9 +1714,6 @@ xfs_bmap_add_extent_hole_delay( xfs_iext_remove(ip, idx, 1, state); ip->i_df.if_lastex = idx - 1; - /* DELTA: Two in-core extents were replaced by one. */ - temp2 = temp; - temp = left.br_startoff; break; case BMAP_LEFT_CONTIG: @@ -1841,9 +1733,6 @@ xfs_bmap_add_extent_hole_delay( trace_xfs_bmap_post_update(ip, idx - 1, state, _THIS_IP_); ip->i_df.if_lastex = idx - 1; - /* DELTA: One in-core extent grew into a hole. */ - temp2 = temp; - temp = left.br_startoff; break; case BMAP_RIGHT_CONTIG: @@ -1862,9 +1751,6 @@ xfs_bmap_add_extent_hole_delay( trace_xfs_bmap_post_update(ip, idx, state, _THIS_IP_); ip->i_df.if_lastex = idx; - /* DELTA: One in-core extent grew into a hole. */ - temp2 = temp; - temp = new->br_startoff; break; case 0: @@ -1876,9 +1762,6 @@ xfs_bmap_add_extent_hole_delay( oldlen = newlen = 0; xfs_iext_insert(ip, idx, 1, new, state); ip->i_df.if_lastex = idx; - /* DELTA: A new in-core extent was added in a hole. */ - temp2 = new->br_blockcount; - temp = new->br_startoff; break; } if (oldlen != newlen) { @@ -1889,13 +1772,6 @@ xfs_bmap_add_extent_hole_delay( * Nothing to do for disk quota accounting here. */ } - if (delta) { - temp2 += temp; - if (delta->xed_startoff > temp) - delta->xed_startoff = temp; - if (delta->xed_blockcount < temp2) - delta->xed_blockcount = temp2; - } *logflagsp = 0; return 0; } @@ -1911,7 +1787,6 @@ xfs_bmap_add_extent_hole_real( xfs_btree_cur_t *cur, /* if null, not a btree */ xfs_bmbt_irec_t *new, /* new data to add to file extents */ int *logflagsp, /* inode logging flags */ - xfs_extdelta_t *delta, /* Change made to incore extents */ int whichfork) /* data or attr fork */ { xfs_bmbt_rec_host_t *ep; /* pointer to extent entry ins. point */ @@ -1922,8 +1797,6 @@ xfs_bmap_add_extent_hole_real( xfs_bmbt_irec_t right; /* right neighbor extent entry */ int rval=0; /* return value (logging flags) */ int state; /* state bits, accessed thru macros */ - xfs_filblks_t temp=0; - xfs_filblks_t temp2=0; ifp = XFS_IFORK_PTR(ip, whichfork); ASSERT(idx <= ifp->if_bytes / (uint)sizeof(xfs_bmbt_rec_t)); @@ -2020,11 +1893,6 @@ xfs_bmap_add_extent_hole_real( left.br_state))) goto done; } - /* DELTA: Two in-core extents were replaced by one. */ - temp = left.br_startoff; - temp2 = left.br_blockcount + - new->br_blockcount + - right.br_blockcount; break; case BMAP_LEFT_CONTIG: @@ -2056,10 +1924,6 @@ xfs_bmap_add_extent_hole_real( left.br_state))) goto done; } - /* DELTA: One in-core extent grew. */ - temp = left.br_startoff; - temp2 = left.br_blockcount + - new->br_blockcount; break; case BMAP_RIGHT_CONTIG: @@ -2092,10 +1956,6 @@ xfs_bmap_add_extent_hole_real( right.br_state))) goto done; } - /* DELTA: One in-core extent grew. */ - temp = new->br_startoff; - temp2 = new->br_blockcount + - right.br_blockcount; break; case 0: @@ -2123,18 +1983,8 @@ xfs_bmap_add_extent_hole_real( goto done; XFS_WANT_CORRUPTED_GOTO(i == 1, done); } - /* DELTA: A new extent was added in a hole. */ - temp = new->br_startoff; - temp2 = new->br_blockcount; break; } - if (delta) { - temp2 += temp; - if (delta->xed_startoff > temp) - delta->xed_startoff = temp; - if (delta->xed_blockcount < temp2) - delta->xed_blockcount = temp2; - } done: *logflagsp = rval; return error; @@ -2959,7 +2809,6 @@ xfs_bmap_del_extent( xfs_btree_cur_t *cur, /* if null, not a btree */ xfs_bmbt_irec_t *del, /* data to remove from extents */ int *logflagsp, /* inode logging flags */ - xfs_extdelta_t *delta, /* Change made to incore extents */ int whichfork, /* data or attr fork */ int rsvd) /* OK to allocate reserved blocks */ { @@ -3265,14 +3114,6 @@ xfs_bmap_del_extent( if (da_old > da_new) xfs_mod_incore_sb(mp, XFS_SBS_FDBLOCKS, (int64_t)(da_old - da_new), rsvd); - if (delta) { - /* DELTA: report the original extent. */ - if (delta->xed_startoff > got.br_startoff) - delta->xed_startoff = got.br_startoff; - if (delta->xed_blockcount < got.br_startoff+got.br_blockcount) - delta->xed_blockcount = got.br_startoff + - got.br_blockcount; - } done: *logflagsp = flags; return error; @@ -3754,9 +3595,10 @@ xfs_bmap_add_attrfork( ip->i_d.di_aformat = XFS_DINODE_FMT_EXTENTS; } ASSERT(ip->i_d.di_anextents == 0); - IHOLD(ip); - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL); + + xfs_trans_ijoin_ref(tp, ip, XFS_ILOCK_EXCL); xfs_trans_log_inode(tp, ip, XFS_ILOG_CORE); + switch (ip->i_d.di_format) { case XFS_DINODE_FMT_DEV: ip->i_d.di_forkoff = roundup(sizeof(xfs_dev_t), 8) >> 3; @@ -4483,8 +4325,7 @@ xfs_bmapi( xfs_extlen_t total, /* total blocks needed */ xfs_bmbt_irec_t *mval, /* output: map values */ int *nmap, /* i/o: mval size/count */ - xfs_bmap_free_t *flist, /* i/o: list extents to free */ - xfs_extdelta_t *delta) /* o: change made to incore extents */ + xfs_bmap_free_t *flist) /* i/o: list extents to free */ { xfs_fsblock_t abno; /* allocated block number */ xfs_extlen_t alen; /* allocated extent length */ @@ -4596,10 +4437,7 @@ xfs_bmapi( end = bno + len; obno = bno; bma.ip = NULL; - if (delta) { - delta->xed_startoff = NULLFILEOFF; - delta->xed_blockcount = 0; - } + while (bno < end && n < *nmap) { /* * Reading past eof, act as though there's a hole @@ -4620,19 +4458,13 @@ xfs_bmapi( * allocate the stuff asked for in this bmap call * but that wouldn't be as good. */ - if (wasdelay && !(flags & XFS_BMAPI_EXACT)) { + if (wasdelay) { alen = (xfs_extlen_t)got.br_blockcount; aoff = got.br_startoff; if (lastx != NULLEXTNUM && lastx) { ep = xfs_iext_get_ext(ifp, lastx - 1); xfs_bmbt_get_all(ep, &prev); } - } else if (wasdelay) { - alen = (xfs_extlen_t) - XFS_FILBLKS_MIN(len, - (got.br_startoff + - got.br_blockcount) - bno); - aoff = bno; } else { alen = (xfs_extlen_t) XFS_FILBLKS_MIN(len, MAXEXTLEN); @@ -4831,7 +4663,7 @@ xfs_bmapi( got.br_state = XFS_EXT_UNWRITTEN; } error = xfs_bmap_add_extent(ip, lastx, &cur, &got, - firstblock, flist, &tmp_logflags, delta, + firstblock, flist, &tmp_logflags, whichfork, (flags & XFS_BMAPI_RSVBLOCKS)); logflags |= tmp_logflags; if (error) @@ -4927,7 +4759,7 @@ xfs_bmapi( } mval->br_state = XFS_EXT_NORM; error = xfs_bmap_add_extent(ip, lastx, &cur, mval, - firstblock, flist, &tmp_logflags, delta, + firstblock, flist, &tmp_logflags, whichfork, (flags & XFS_BMAPI_RSVBLOCKS)); logflags |= tmp_logflags; if (error) @@ -5017,14 +4849,6 @@ xfs_bmapi( ASSERT(XFS_IFORK_FORMAT(ip, whichfork) != XFS_DINODE_FMT_BTREE || XFS_IFORK_NEXTENTS(ip, whichfork) > ifp->if_ext_max); error = 0; - if (delta && delta->xed_startoff != NULLFILEOFF) { - /* A change was actually made. - * Note that delta->xed_blockount is an offset at this - * point and needs to be converted to a block count. - */ - ASSERT(delta->xed_blockcount > delta->xed_startoff); - delta->xed_blockcount -= delta->xed_startoff; - } error0: /* * Log everything. Do this after conversion, there's no point in @@ -5136,8 +4960,6 @@ xfs_bunmapi( xfs_fsblock_t *firstblock, /* first allocated block controls a.g. for allocs */ xfs_bmap_free_t *flist, /* i/o: list extents to free */ - xfs_extdelta_t *delta, /* o: change made to incore - extents */ int *done) /* set if not done yet */ { xfs_btree_cur_t *cur; /* bmap btree cursor */ @@ -5196,10 +5018,7 @@ xfs_bunmapi( bno = start + len - 1; ep = xfs_bmap_search_extents(ip, bno, whichfork, &eof, &lastx, &got, &prev); - if (delta) { - delta->xed_startoff = NULLFILEOFF; - delta->xed_blockcount = 0; - } + /* * Check to see if the given block number is past the end of the * file, back up to the last block if so... @@ -5297,7 +5116,7 @@ xfs_bunmapi( } del.br_state = XFS_EXT_UNWRITTEN; error = xfs_bmap_add_extent(ip, lastx, &cur, &del, - firstblock, flist, &logflags, delta, + firstblock, flist, &logflags, XFS_DATA_FORK, 0); if (error) goto error0; @@ -5352,7 +5171,7 @@ xfs_bunmapi( prev.br_state = XFS_EXT_UNWRITTEN; error = xfs_bmap_add_extent(ip, lastx - 1, &cur, &prev, firstblock, flist, &logflags, - delta, XFS_DATA_FORK, 0); + XFS_DATA_FORK, 0); if (error) goto error0; goto nodelete; @@ -5361,7 +5180,7 @@ xfs_bunmapi( del.br_state = XFS_EXT_UNWRITTEN; error = xfs_bmap_add_extent(ip, lastx, &cur, &del, firstblock, flist, &logflags, - delta, XFS_DATA_FORK, 0); + XFS_DATA_FORK, 0); if (error) goto error0; goto nodelete; @@ -5414,7 +5233,7 @@ xfs_bunmapi( goto error0; } error = xfs_bmap_del_extent(ip, tp, lastx, flist, cur, &del, - &tmp_logflags, delta, whichfork, rsvd); + &tmp_logflags, whichfork, rsvd); logflags |= tmp_logflags; if (error) goto error0; @@ -5471,14 +5290,6 @@ nodelete: ASSERT(ifp->if_ext_max == XFS_IFORK_SIZE(ip, whichfork) / (uint)sizeof(xfs_bmbt_rec_t)); error = 0; - if (delta && delta->xed_startoff != NULLFILEOFF) { - /* A change was actually made. - * Note that delta->xed_blockount is an offset at this - * point and needs to be converted to a block count. - */ - ASSERT(delta->xed_blockcount > delta->xed_startoff); - delta->xed_blockcount -= delta->xed_startoff; - } error0: /* * Log everything. Do this after conversion, there's no point in @@ -5605,28 +5416,6 @@ xfs_getbmap( prealloced = 0; fixlen = 1LL << 32; } else { - /* - * If the BMV_IF_NO_DMAPI_READ interface bit specified, do - * not generate a DMAPI read event. Otherwise, if the - * DM_EVENT_READ bit is set for the file, generate a read - * event in order that the DMAPI application may do its thing - * before we return the extents. Usually this means restoring - * user file data to regions of the file that look like holes. - * - * The "old behavior" (from XFS_IOC_GETBMAP) is to not specify - * BMV_IF_NO_DMAPI_READ so that read events are generated. - * If this were not true, callers of ioctl(XFS_IOC_GETBMAP) - * could misinterpret holes in a DMAPI file as true holes, - * when in fact they may represent offline user data. - */ - if (DM_EVENT_ENABLED(ip, DM_EVENT_READ) && - !(iflags & BMV_IF_NO_DMAPI_READ)) { - error = XFS_SEND_DATA(mp, DM_EVENT_READ, ip, - 0, 0, 0, NULL); - if (error) - return XFS_ERROR(error); - } - if (ip->i_d.di_format != XFS_DINODE_FMT_EXTENTS && ip->i_d.di_format != XFS_DINODE_FMT_BTREE && ip->i_d.di_format != XFS_DINODE_FMT_LOCAL) @@ -5713,7 +5502,7 @@ xfs_getbmap( error = xfs_bmapi(NULL, ip, XFS_BB_TO_FSBT(mp, bmv->bmv_offset), XFS_BB_TO_FSB(mp, bmv->bmv_length), bmapi_flags, NULL, 0, map, &nmap, - NULL, NULL); + NULL); if (error) goto out_free_map; ASSERT(nmap <= subnex); @@ -5859,66 +5648,34 @@ xfs_bmap_eof( } #ifdef DEBUG -STATIC -xfs_buf_t * +STATIC struct xfs_buf * xfs_bmap_get_bp( - xfs_btree_cur_t *cur, + struct xfs_btree_cur *cur, xfs_fsblock_t bno) { - int i; - xfs_buf_t *bp; + struct xfs_log_item_desc *lidp; + int i; if (!cur) - return(NULL); - - bp = NULL; - for(i = 0; i < XFS_BTREE_MAXLEVELS; i++) { - bp = cur->bc_bufs[i]; - if (!bp) break; - if (XFS_BUF_ADDR(bp) == bno) - break; /* Found it */ - } - if (i == XFS_BTREE_MAXLEVELS) - bp = NULL; - - if (!bp) { /* Chase down all the log items to see if the bp is there */ - xfs_log_item_chunk_t *licp; - xfs_trans_t *tp; - - tp = cur->bc_tp; - licp = &tp->t_items; - while (!bp && licp != NULL) { - if (xfs_lic_are_all_free(licp)) { - licp = licp->lic_next; - continue; - } - for (i = 0; i < licp->lic_unused; i++) { - xfs_log_item_desc_t *lidp; - xfs_log_item_t *lip; - xfs_buf_log_item_t *bip; - xfs_buf_t *lbp; - - if (xfs_lic_isfree(licp, i)) { - continue; - } - - lidp = xfs_lic_slot(licp, i); - lip = lidp->lid_item; - if (lip->li_type != XFS_LI_BUF) - continue; + return NULL; - bip = (xfs_buf_log_item_t *)lip; - lbp = bip->bli_buf; + for (i = 0; i < XFS_BTREE_MAXLEVELS; i++) { + if (!cur->bc_bufs[i]) + break; + if (XFS_BUF_ADDR(cur->bc_bufs[i]) == bno) + return cur->bc_bufs[i]; + } - if (XFS_BUF_ADDR(lbp) == bno) { - bp = lbp; - break; /* Found it */ - } - } - licp = licp->lic_next; - } + /* Chase down all the log items to see if the bp is there */ + list_for_each_entry(lidp, &cur->bc_tp->t_items, lid_trans) { + struct xfs_buf_log_item *bip; + bip = (struct xfs_buf_log_item *)lidp->lid_item; + if (bip->bli_item.li_type == XFS_LI_BUF && + XFS_BUF_ADDR(bip->bli_buf) == bno) + return bip->bli_buf; } - return(bp); + + return NULL; } STATIC void diff --git a/fs/xfs/xfs_bmap.h b/fs/xfs/xfs_bmap.h index 419dafb9d87d..b13569a6179b 100644 --- a/fs/xfs/xfs_bmap.h +++ b/fs/xfs/xfs_bmap.h @@ -28,20 +28,6 @@ struct xfs_trans; extern kmem_zone_t *xfs_bmap_free_item_zone; /* - * DELTA: describe a change to the in-core extent list. - * - * Internally the use of xed_blockount is somewhat funky. - * xed_blockcount contains an offset much of the time because this - * makes merging changes easier. (xfs_fileoff_t and xfs_filblks_t are - * the same underlying type). - */ -typedef struct xfs_extdelta -{ - xfs_fileoff_t xed_startoff; /* offset of range */ - xfs_filblks_t xed_blockcount; /* blocks in range */ -} xfs_extdelta_t; - -/* * List of extents to be free "later". * The list is kept sorted on xbf_startblock. */ @@ -82,16 +68,13 @@ typedef struct xfs_bmap_free #define XFS_BMAPI_DELAY 0x002 /* delayed write operation */ #define XFS_BMAPI_ENTIRE 0x004 /* return entire extent, not trimmed */ #define XFS_BMAPI_METADATA 0x008 /* mapping metadata not user data */ -#define XFS_BMAPI_EXACT 0x010 /* allocate only to spec'd bounds */ -#define XFS_BMAPI_ATTRFORK 0x020 /* use attribute fork not data */ -#define XFS_BMAPI_ASYNC 0x040 /* bunmapi xactions can be async */ -#define XFS_BMAPI_RSVBLOCKS 0x080 /* OK to alloc. reserved data blocks */ -#define XFS_BMAPI_PREALLOC 0x100 /* preallocation op: unwritten space */ -#define XFS_BMAPI_IGSTATE 0x200 /* Ignore state - */ +#define XFS_BMAPI_ATTRFORK 0x010 /* use attribute fork not data */ +#define XFS_BMAPI_RSVBLOCKS 0x020 /* OK to alloc. reserved data blocks */ +#define XFS_BMAPI_PREALLOC 0x040 /* preallocation op: unwritten space */ +#define XFS_BMAPI_IGSTATE 0x080 /* Ignore state - */ /* combine contig. space */ -#define XFS_BMAPI_CONTIG 0x400 /* must allocate only one extent */ -/* XFS_BMAPI_DIRECT_IO 0x800 */ -#define XFS_BMAPI_CONVERT 0x1000 /* unwritten extent conversion - */ +#define XFS_BMAPI_CONTIG 0x100 /* must allocate only one extent */ +#define XFS_BMAPI_CONVERT 0x200 /* unwritten extent conversion - */ /* need write cache flushing and no */ /* additional allocation alignments */ @@ -100,9 +83,7 @@ typedef struct xfs_bmap_free { XFS_BMAPI_DELAY, "DELAY" }, \ { XFS_BMAPI_ENTIRE, "ENTIRE" }, \ { XFS_BMAPI_METADATA, "METADATA" }, \ - { XFS_BMAPI_EXACT, "EXACT" }, \ { XFS_BMAPI_ATTRFORK, "ATTRFORK" }, \ - { XFS_BMAPI_ASYNC, "ASYNC" }, \ { XFS_BMAPI_RSVBLOCKS, "RSVBLOCKS" }, \ { XFS_BMAPI_PREALLOC, "PREALLOC" }, \ { XFS_BMAPI_IGSTATE, "IGSTATE" }, \ @@ -310,9 +291,7 @@ xfs_bmapi( xfs_extlen_t total, /* total blocks needed */ struct xfs_bmbt_irec *mval, /* output: map values */ int *nmap, /* i/o: mval size/count */ - xfs_bmap_free_t *flist, /* i/o: list extents to free */ - xfs_extdelta_t *delta); /* o: change made to incore - extents */ + xfs_bmap_free_t *flist); /* i/o: list extents to free */ /* * Map file blocks to filesystem blocks, simple version. @@ -346,8 +325,6 @@ xfs_bunmapi( xfs_fsblock_t *firstblock, /* first allocated block controls a.g. for allocs */ xfs_bmap_free_t *flist, /* i/o: list extents to free */ - xfs_extdelta_t *delta, /* o: change made to incore - extents */ int *done); /* set if not done yet */ /* diff --git a/fs/xfs/xfs_bmap_btree.c b/fs/xfs/xfs_bmap_btree.c index 416e47e54b83..87d3c10b6954 100644 --- a/fs/xfs/xfs_bmap_btree.c +++ b/fs/xfs/xfs_bmap_btree.c @@ -24,21 +24,16 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_inode_item.h" #include "xfs_alloc.h" #include "xfs_btree.h" #include "xfs_btree_trace.h" -#include "xfs_ialloc.h" #include "xfs_itable.h" #include "xfs_bmap.h" #include "xfs_error.h" diff --git a/fs/xfs/xfs_btree.c b/fs/xfs/xfs_btree.c index 96be4b0f2496..829af92f0fba 100644 --- a/fs/xfs/xfs_btree.c +++ b/fs/xfs/xfs_btree.c @@ -24,20 +24,15 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_inode_item.h" #include "xfs_btree.h" #include "xfs_btree_trace.h" -#include "xfs_ialloc.h" #include "xfs_error.h" #include "xfs_trace.h" diff --git a/fs/xfs/xfs_buf_item.c b/fs/xfs/xfs_buf_item.c index 02a80984aa05..1b09d7a280df 100644 --- a/fs/xfs/xfs_buf_item.c +++ b/fs/xfs/xfs_buf_item.c @@ -24,7 +24,6 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_buf_item.h" #include "xfs_trans_priv.h" @@ -34,6 +33,12 @@ kmem_zone_t *xfs_buf_item_zone; +static inline struct xfs_buf_log_item *BUF_ITEM(struct xfs_log_item *lip) +{ + return container_of(lip, struct xfs_buf_log_item, bli_item); +} + + #ifdef XFS_TRANS_DEBUG /* * This function uses an alternate strategy for tracking the bytes @@ -151,12 +156,13 @@ STATIC void xfs_buf_do_callbacks(xfs_buf_t *bp, xfs_log_item_t *lip); */ STATIC uint xfs_buf_item_size( - xfs_buf_log_item_t *bip) + struct xfs_log_item *lip) { - uint nvecs; - int next_bit; - int last_bit; - xfs_buf_t *bp; + struct xfs_buf_log_item *bip = BUF_ITEM(lip); + struct xfs_buf *bp = bip->bli_buf; + uint nvecs; + int next_bit; + int last_bit; ASSERT(atomic_read(&bip->bli_refcount) > 0); if (bip->bli_flags & XFS_BLI_STALE) { @@ -170,7 +176,6 @@ xfs_buf_item_size( return 1; } - bp = bip->bli_buf; ASSERT(bip->bli_flags & XFS_BLI_LOGGED); nvecs = 1; last_bit = xfs_next_bit(bip->bli_format.blf_data_map, @@ -219,13 +224,13 @@ xfs_buf_item_size( */ STATIC void xfs_buf_item_format( - xfs_buf_log_item_t *bip, - xfs_log_iovec_t *log_vector) + struct xfs_log_item *lip, + struct xfs_log_iovec *vecp) { + struct xfs_buf_log_item *bip = BUF_ITEM(lip); + struct xfs_buf *bp = bip->bli_buf; uint base_size; uint nvecs; - xfs_log_iovec_t *vecp; - xfs_buf_t *bp; int first_bit; int last_bit; int next_bit; @@ -235,8 +240,6 @@ xfs_buf_item_format( ASSERT(atomic_read(&bip->bli_refcount) > 0); ASSERT((bip->bli_flags & XFS_BLI_LOGGED) || (bip->bli_flags & XFS_BLI_STALE)); - bp = bip->bli_buf; - vecp = log_vector; /* * The size of the base structure is the size of the @@ -248,7 +251,7 @@ xfs_buf_item_format( base_size = (uint)(sizeof(xfs_buf_log_format_t) + ((bip->bli_format.blf_map_size - 1) * sizeof(uint))); - vecp->i_addr = (xfs_caddr_t)&bip->bli_format; + vecp->i_addr = &bip->bli_format; vecp->i_len = base_size; vecp->i_type = XLOG_REG_TYPE_BFORMAT; vecp++; @@ -263,7 +266,7 @@ xfs_buf_item_format( */ if (bip->bli_flags & XFS_BLI_INODE_BUF) { if (!((bip->bli_flags & XFS_BLI_INODE_ALLOC_BUF) && - xfs_log_item_in_current_chkpt(&bip->bli_item))) + xfs_log_item_in_current_chkpt(lip))) bip->bli_format.blf_flags |= XFS_BLF_INODE_BUF; bip->bli_flags &= ~XFS_BLI_INODE_BUF; } @@ -356,66 +359,90 @@ xfs_buf_item_format( /* * This is called to pin the buffer associated with the buf log item in memory - * so it cannot be written out. Simply call bpin() on the buffer to do this. + * so it cannot be written out. * * We also always take a reference to the buffer log item here so that the bli * is held while the item is pinned in memory. This means that we can * unconditionally drop the reference count a transaction holds when the * transaction is completed. */ - STATIC void xfs_buf_item_pin( - xfs_buf_log_item_t *bip) + struct xfs_log_item *lip) { - xfs_buf_t *bp; + struct xfs_buf_log_item *bip = BUF_ITEM(lip); - bp = bip->bli_buf; - ASSERT(XFS_BUF_ISBUSY(bp)); + ASSERT(XFS_BUF_ISBUSY(bip->bli_buf)); ASSERT(atomic_read(&bip->bli_refcount) > 0); ASSERT((bip->bli_flags & XFS_BLI_LOGGED) || (bip->bli_flags & XFS_BLI_STALE)); - atomic_inc(&bip->bli_refcount); + trace_xfs_buf_item_pin(bip); - xfs_bpin(bp); -} + atomic_inc(&bip->bli_refcount); + atomic_inc(&bip->bli_buf->b_pin_count); +} /* * This is called to unpin the buffer associated with the buf log * item which was previously pinned with a call to xfs_buf_item_pin(). - * Just call bunpin() on the buffer to do this. * * Also drop the reference to the buf item for the current transaction. * If the XFS_BLI_STALE flag is set and we are the last reference, * then free up the buf log item and unlock the buffer. + * + * If the remove flag is set we are called from uncommit in the + * forced-shutdown path. If that is true and the reference count on + * the log item is going to drop to zero we need to free the item's + * descriptor in the transaction. */ STATIC void xfs_buf_item_unpin( - xfs_buf_log_item_t *bip) + struct xfs_log_item *lip, + int remove) { - struct xfs_ail *ailp; - xfs_buf_t *bp; - int freed; + struct xfs_buf_log_item *bip = BUF_ITEM(lip); + xfs_buf_t *bp = bip->bli_buf; + struct xfs_ail *ailp = lip->li_ailp; int stale = bip->bli_flags & XFS_BLI_STALE; + int freed; - bp = bip->bli_buf; - ASSERT(bp != NULL); ASSERT(XFS_BUF_FSPRIVATE(bp, xfs_buf_log_item_t *) == bip); ASSERT(atomic_read(&bip->bli_refcount) > 0); + trace_xfs_buf_item_unpin(bip); freed = atomic_dec_and_test(&bip->bli_refcount); - ailp = bip->bli_item.li_ailp; - xfs_bunpin(bp); + + if (atomic_dec_and_test(&bp->b_pin_count)) + wake_up_all(&bp->b_waiters); + if (freed && stale) { ASSERT(bip->bli_flags & XFS_BLI_STALE); ASSERT(XFS_BUF_VALUSEMA(bp) <= 0); ASSERT(!(XFS_BUF_ISDELAYWRITE(bp))); ASSERT(XFS_BUF_ISSTALE(bp)); ASSERT(bip->bli_format.blf_flags & XFS_BLF_CANCEL); + trace_xfs_buf_item_unpin_stale(bip); + if (remove) { + /* + * We have to remove the log item from the transaction + * as we are about to release our reference to the + * buffer. If we don't, the unlock that occurs later + * in xfs_trans_uncommit() will ry to reference the + * buffer which we no longer have a hold on. + */ + xfs_trans_del_item(lip); + + /* + * Since the transaction no longer refers to the buffer, + * the buffer should no longer refer to the transaction. + */ + XFS_BUF_SET_FSPRIVATE2(bp, NULL); + } + /* * If we get called here because of an IO error, we may * or may not have the item on the AIL. xfs_trans_ail_delete() @@ -437,48 +464,6 @@ xfs_buf_item_unpin( } /* - * this is called from uncommit in the forced-shutdown path. - * we need to check to see if the reference count on the log item - * is going to drop to zero. If so, unpin will free the log item - * so we need to free the item's descriptor (that points to the item) - * in the transaction. - */ -STATIC void -xfs_buf_item_unpin_remove( - xfs_buf_log_item_t *bip, - xfs_trans_t *tp) -{ - /* will xfs_buf_item_unpin() call xfs_buf_item_relse()? */ - if ((atomic_read(&bip->bli_refcount) == 1) && - (bip->bli_flags & XFS_BLI_STALE)) { - /* - * yes -- We can safely do some work here and then call - * buf_item_unpin to do the rest because we are - * are holding the buffer locked so no one else will be - * able to bump up the refcount. We have to remove the - * log item from the transaction as we are about to release - * our reference to the buffer. If we don't, the unlock that - * occurs later in the xfs_trans_uncommit() will try to - * reference the buffer which we no longer have a hold on. - */ - struct xfs_log_item_desc *lidp; - - ASSERT(XFS_BUF_VALUSEMA(bip->bli_buf) <= 0); - trace_xfs_buf_item_unpin_stale(bip); - - lidp = xfs_trans_find_item(tp, (xfs_log_item_t *)bip); - xfs_trans_free_item(tp, lidp); - - /* - * Since the transaction no longer refers to the buffer, the - * buffer should no longer refer to the transaction. - */ - XFS_BUF_SET_FSPRIVATE2(bip->bli_buf, NULL); - } - xfs_buf_item_unpin(bip); -} - -/* * This is called to attempt to lock the buffer associated with this * buf log item. Don't sleep on the buffer lock. If we can't get * the lock right away, return 0. If we can get the lock, take a @@ -488,11 +473,11 @@ xfs_buf_item_unpin_remove( */ STATIC uint xfs_buf_item_trylock( - xfs_buf_log_item_t *bip) + struct xfs_log_item *lip) { - xfs_buf_t *bp; + struct xfs_buf_log_item *bip = BUF_ITEM(lip); + struct xfs_buf *bp = bip->bli_buf; - bp = bip->bli_buf; if (XFS_BUF_ISPINNED(bp)) return XFS_ITEM_PINNED; if (!XFS_BUF_CPSEMA(bp)) @@ -529,13 +514,12 @@ xfs_buf_item_trylock( */ STATIC void xfs_buf_item_unlock( - xfs_buf_log_item_t *bip) + struct xfs_log_item *lip) { - int aborted; - xfs_buf_t *bp; - uint hold; - - bp = bip->bli_buf; + struct xfs_buf_log_item *bip = BUF_ITEM(lip); + struct xfs_buf *bp = bip->bli_buf; + int aborted; + uint hold; /* Clear the buffer's association with this transaction. */ XFS_BUF_SET_FSPRIVATE2(bp, NULL); @@ -546,7 +530,7 @@ xfs_buf_item_unlock( * (cancelled) buffers at unpin time, but we'll never go through the * pin/unpin cycle if we abort inside commit. */ - aborted = (bip->bli_item.li_flags & XFS_LI_ABORTED) != 0; + aborted = (lip->li_flags & XFS_LI_ABORTED) != 0; /* * Before possibly freeing the buf item, determine if we should @@ -607,16 +591,16 @@ xfs_buf_item_unlock( */ STATIC xfs_lsn_t xfs_buf_item_committed( - xfs_buf_log_item_t *bip, + struct xfs_log_item *lip, xfs_lsn_t lsn) { + struct xfs_buf_log_item *bip = BUF_ITEM(lip); + trace_xfs_buf_item_committed(bip); - if ((bip->bli_flags & XFS_BLI_INODE_ALLOC_BUF) && - (bip->bli_item.li_lsn != 0)) { - return bip->bli_item.li_lsn; - } - return (lsn); + if ((bip->bli_flags & XFS_BLI_INODE_ALLOC_BUF) && lip->li_lsn != 0) + return lip->li_lsn; + return lsn; } /* @@ -626,15 +610,16 @@ xfs_buf_item_committed( */ STATIC void xfs_buf_item_push( - xfs_buf_log_item_t *bip) + struct xfs_log_item *lip) { - xfs_buf_t *bp; + struct xfs_buf_log_item *bip = BUF_ITEM(lip); + struct xfs_buf *bp = bip->bli_buf; ASSERT(!(bip->bli_flags & XFS_BLI_STALE)); + ASSERT(!XFS_BUF_ISDELAYWRITE(bp)); + trace_xfs_buf_item_push(bip); - bp = bip->bli_buf; - ASSERT(!XFS_BUF_ISDELAYWRITE(bp)); xfs_buf_relse(bp); } @@ -646,22 +631,24 @@ xfs_buf_item_push( */ STATIC void xfs_buf_item_pushbuf( - xfs_buf_log_item_t *bip) + struct xfs_log_item *lip) { - xfs_buf_t *bp; + struct xfs_buf_log_item *bip = BUF_ITEM(lip); + struct xfs_buf *bp = bip->bli_buf; ASSERT(!(bip->bli_flags & XFS_BLI_STALE)); + ASSERT(XFS_BUF_ISDELAYWRITE(bp)); + trace_xfs_buf_item_pushbuf(bip); - bp = bip->bli_buf; - ASSERT(XFS_BUF_ISDELAYWRITE(bp)); xfs_buf_delwri_promote(bp); xfs_buf_relse(bp); } -/* ARGSUSED */ STATIC void -xfs_buf_item_committing(xfs_buf_log_item_t *bip, xfs_lsn_t commit_lsn) +xfs_buf_item_committing( + struct xfs_log_item *lip, + xfs_lsn_t commit_lsn) { } @@ -669,21 +656,16 @@ xfs_buf_item_committing(xfs_buf_log_item_t *bip, xfs_lsn_t commit_lsn) * This is the ops vector shared by all buf log items. */ static struct xfs_item_ops xfs_buf_item_ops = { - .iop_size = (uint(*)(xfs_log_item_t*))xfs_buf_item_size, - .iop_format = (void(*)(xfs_log_item_t*, xfs_log_iovec_t*)) - xfs_buf_item_format, - .iop_pin = (void(*)(xfs_log_item_t*))xfs_buf_item_pin, - .iop_unpin = (void(*)(xfs_log_item_t*))xfs_buf_item_unpin, - .iop_unpin_remove = (void(*)(xfs_log_item_t*, xfs_trans_t *)) - xfs_buf_item_unpin_remove, - .iop_trylock = (uint(*)(xfs_log_item_t*))xfs_buf_item_trylock, - .iop_unlock = (void(*)(xfs_log_item_t*))xfs_buf_item_unlock, - .iop_committed = (xfs_lsn_t(*)(xfs_log_item_t*, xfs_lsn_t)) - xfs_buf_item_committed, - .iop_push = (void(*)(xfs_log_item_t*))xfs_buf_item_push, - .iop_pushbuf = (void(*)(xfs_log_item_t*))xfs_buf_item_pushbuf, - .iop_committing = (void(*)(xfs_log_item_t*, xfs_lsn_t)) - xfs_buf_item_committing + .iop_size = xfs_buf_item_size, + .iop_format = xfs_buf_item_format, + .iop_pin = xfs_buf_item_pin, + .iop_unpin = xfs_buf_item_unpin, + .iop_trylock = xfs_buf_item_trylock, + .iop_unlock = xfs_buf_item_unlock, + .iop_committed = xfs_buf_item_committed, + .iop_push = xfs_buf_item_push, + .iop_pushbuf = xfs_buf_item_pushbuf, + .iop_committing = xfs_buf_item_committing }; @@ -712,7 +694,6 @@ xfs_buf_item_init( */ if (bp->b_mount != mp) bp->b_mount = mp; - XFS_BUF_SET_BDSTRAT_FUNC(bp, xfs_bdstrat_cb); if (XFS_BUF_FSPRIVATE(bp, void *) != NULL) { lip = XFS_BUF_FSPRIVATE(bp, xfs_log_item_t *); if (lip->li_type == XFS_LI_BUF) { @@ -1098,15 +1079,14 @@ xfs_buf_error_relse( * It is called by xfs_buf_iodone_callbacks() above which will take * care of cleaning up the buffer itself. */ -/* ARGSUSED */ void xfs_buf_iodone( - xfs_buf_t *bp, - xfs_buf_log_item_t *bip) + struct xfs_buf *bp, + struct xfs_log_item *lip) { - struct xfs_ail *ailp = bip->bli_item.li_ailp; + struct xfs_ail *ailp = lip->li_ailp; - ASSERT(bip->bli_buf == bp); + ASSERT(BUF_ITEM(lip)->bli_buf == bp); xfs_buf_rele(bp); @@ -1120,6 +1100,6 @@ xfs_buf_iodone( * Either way, AIL is useless if we're forcing a shutdown. */ spin_lock(&ailp->xa_lock); - xfs_trans_ail_delete(ailp, (xfs_log_item_t *)bip); - xfs_buf_item_free(bip); + xfs_trans_ail_delete(ailp, lip); + xfs_buf_item_free(BUF_ITEM(lip)); } diff --git a/fs/xfs/xfs_buf_item.h b/fs/xfs/xfs_buf_item.h index f20bb472d582..0e2ed43f16c7 100644 --- a/fs/xfs/xfs_buf_item.h +++ b/fs/xfs/xfs_buf_item.h @@ -124,7 +124,7 @@ void xfs_buf_attach_iodone(struct xfs_buf *, void(*)(struct xfs_buf *, xfs_log_item_t *), xfs_log_item_t *); void xfs_buf_iodone_callbacks(struct xfs_buf *); -void xfs_buf_iodone(struct xfs_buf *, xfs_buf_log_item_t *); +void xfs_buf_iodone(struct xfs_buf *, struct xfs_log_item *); #ifdef XFS_TRANS_DEBUG void diff --git a/fs/xfs/xfs_da_btree.c b/fs/xfs/xfs_da_btree.c index 0ca556b4bf31..30fa0e206fba 100644 --- a/fs/xfs/xfs_da_btree.c +++ b/fs/xfs/xfs_da_btree.c @@ -25,19 +25,14 @@ #include "xfs_sb.h" #include "xfs_ag.h" #include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_da_btree.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" #include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_inode_item.h" #include "xfs_alloc.h" -#include "xfs_btree.h" #include "xfs_bmap.h" #include "xfs_attr.h" #include "xfs_attr_leaf.h" @@ -581,16 +576,14 @@ xfs_da_node_add(xfs_da_state_t *state, xfs_da_state_blk_t *oldblk, xfs_da_intnode_t *node; xfs_da_node_entry_t *btree; int tmp; - xfs_mount_t *mp; node = oldblk->bp->data; - mp = state->mp; ASSERT(be16_to_cpu(node->hdr.info.magic) == XFS_DA_NODE_MAGIC); ASSERT((oldblk->index >= 0) && (oldblk->index <= be16_to_cpu(node->hdr.count))); ASSERT(newblk->blkno != 0); if (state->args->whichfork == XFS_DATA_FORK) - ASSERT(newblk->blkno >= mp->m_dirleafblk && - newblk->blkno < mp->m_dirfreeblk); + ASSERT(newblk->blkno >= state->mp->m_dirleafblk && + newblk->blkno < state->mp->m_dirfreeblk); /* * We may need to make some room before we insert the new node. @@ -1601,7 +1594,7 @@ xfs_da_grow_inode(xfs_da_args_t *args, xfs_dablk_t *new_blkno) xfs_bmapi_aflag(w)|XFS_BMAPI_WRITE|XFS_BMAPI_METADATA| XFS_BMAPI_CONTIG, args->firstblock, args->total, &map, &nmap, - args->flist, NULL))) { + args->flist))) { return error; } ASSERT(nmap <= 1); @@ -1622,8 +1615,7 @@ xfs_da_grow_inode(xfs_da_args_t *args, xfs_dablk_t *new_blkno) xfs_bmapi_aflag(w)|XFS_BMAPI_WRITE| XFS_BMAPI_METADATA, args->firstblock, args->total, - &mapp[mapi], &nmap, args->flist, - NULL))) { + &mapp[mapi], &nmap, args->flist))) { kmem_free(mapp); return error; } @@ -1884,7 +1876,7 @@ xfs_da_shrink_inode(xfs_da_args_t *args, xfs_dablk_t dead_blkno, */ if ((error = xfs_bunmapi(tp, dp, dead_blkno, count, xfs_bmapi_aflag(w)|XFS_BMAPI_METADATA, - 0, args->firstblock, args->flist, NULL, + 0, args->firstblock, args->flist, &done)) == ENOSPC) { if (w != XFS_DATA_FORK) break; @@ -1989,7 +1981,7 @@ xfs_da_do_buf( nfsb, XFS_BMAPI_METADATA | xfs_bmapi_aflag(whichfork), - NULL, 0, mapp, &nmap, NULL, NULL))) + NULL, 0, mapp, &nmap, NULL))) goto exit0; } } else { diff --git a/fs/xfs/xfs_dfrag.c b/fs/xfs/xfs_dfrag.c index 7f159d2a429a..3b9582c60a22 100644 --- a/fs/xfs/xfs_dfrag.c +++ b/fs/xfs/xfs_dfrag.c @@ -24,24 +24,15 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_inode_item.h" #include "xfs_bmap.h" -#include "xfs_btree.h" -#include "xfs_ialloc.h" #include "xfs_itable.h" #include "xfs_dfrag.h" #include "xfs_error.h" -#include "xfs_rw.h" #include "xfs_vnodeops.h" #include "xfs_trace.h" @@ -425,11 +416,8 @@ xfs_swap_extents( } - IHOLD(ip); - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); - - IHOLD(tip); - xfs_trans_ijoin(tp, tip, XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); + xfs_trans_ijoin_ref(tp, ip, XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); + xfs_trans_ijoin_ref(tp, tip, XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); xfs_trans_log_inode(tp, ip, ilf_fields); xfs_trans_log_inode(tp, tip, tilf_fields); diff --git a/fs/xfs/xfs_dir2.c b/fs/xfs/xfs_dir2.c index 42520f041265..a1321bc7f192 100644 --- a/fs/xfs/xfs_dir2.c +++ b/fs/xfs/xfs_dir2.c @@ -25,13 +25,11 @@ #include "xfs_sb.h" #include "xfs_ag.h" #include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_da_btree.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_inode_item.h" @@ -382,7 +380,7 @@ xfs_readdir( int rval; /* return value */ int v; /* type-checking value */ - xfs_itrace_entry(dp); + trace_xfs_readdir(dp); if (XFS_FORCED_SHUTDOWN(dp->i_mount)) return XFS_ERROR(EIO); @@ -549,7 +547,7 @@ xfs_dir2_grow_inode( if ((error = xfs_bmapi(tp, dp, bno, count, XFS_BMAPI_WRITE|XFS_BMAPI_METADATA|XFS_BMAPI_CONTIG, args->firstblock, args->total, &map, &nmap, - args->flist, NULL))) + args->flist))) return error; ASSERT(nmap <= 1); if (nmap == 1) { @@ -581,8 +579,7 @@ xfs_dir2_grow_inode( if ((error = xfs_bmapi(tp, dp, b, c, XFS_BMAPI_WRITE|XFS_BMAPI_METADATA, args->firstblock, args->total, - &mapp[mapi], &nmap, args->flist, - NULL))) { + &mapp[mapi], &nmap, args->flist))) { kmem_free(mapp); return error; } @@ -715,7 +712,7 @@ xfs_dir2_shrink_inode( */ if ((error = xfs_bunmapi(tp, dp, da, mp->m_dirblkfsbs, XFS_BMAPI_METADATA, 0, args->firstblock, args->flist, - NULL, &done))) { + &done))) { /* * ENOSPC actually can happen if we're in a removename with * no space reservation, and the resulting block removal diff --git a/fs/xfs/xfs_dir2_block.c b/fs/xfs/xfs_dir2_block.c index 779a267b0a84..580d99cef9e7 100644 --- a/fs/xfs/xfs_dir2_block.c +++ b/fs/xfs/xfs_dir2_block.c @@ -24,12 +24,10 @@ #include "xfs_sb.h" #include "xfs_ag.h" #include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_da_btree.h" #include "xfs_bmap_btree.h" #include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_inode_item.h" @@ -1073,10 +1071,10 @@ xfs_dir2_sf_to_block( */ buf_len = dp->i_df.if_bytes; - buf = kmem_alloc(dp->i_df.if_bytes, KM_SLEEP); + buf = kmem_alloc(buf_len, KM_SLEEP); - memcpy(buf, sfp, dp->i_df.if_bytes); - xfs_idata_realloc(dp, -dp->i_df.if_bytes, XFS_DATA_FORK); + memcpy(buf, sfp, buf_len); + xfs_idata_realloc(dp, -buf_len, XFS_DATA_FORK); dp->i_d.di_size = 0; xfs_trans_log_inode(tp, dp, XFS_ILOG_CORE); /* diff --git a/fs/xfs/xfs_dir2_data.c b/fs/xfs/xfs_dir2_data.c index 498f8d694330..921595b84f5b 100644 --- a/fs/xfs/xfs_dir2_data.c +++ b/fs/xfs/xfs_dir2_data.c @@ -24,12 +24,10 @@ #include "xfs_sb.h" #include "xfs_ag.h" #include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_da_btree.h" #include "xfs_bmap_btree.h" #include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_dir2_data.h" diff --git a/fs/xfs/xfs_dir2_leaf.c b/fs/xfs/xfs_dir2_leaf.c index e2d89854ec9e..504be8640e91 100644 --- a/fs/xfs/xfs_dir2_leaf.c +++ b/fs/xfs/xfs_dir2_leaf.c @@ -25,11 +25,9 @@ #include "xfs_sb.h" #include "xfs_ag.h" #include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_da_btree.h" #include "xfs_bmap_btree.h" -#include "xfs_attr_sf.h" #include "xfs_dir2_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" @@ -875,7 +873,7 @@ xfs_dir2_leaf_getdents( xfs_dir2_byte_to_da(mp, XFS_DIR2_LEAF_OFFSET) - map_off, XFS_BMAPI_METADATA, NULL, 0, - &map[map_valid], &nmap, NULL, NULL); + &map[map_valid], &nmap, NULL); /* * Don't know if we should ignore this or * try to return an error. diff --git a/fs/xfs/xfs_dir2_node.c b/fs/xfs/xfs_dir2_node.c index 78fc4d9ae756..f9a0864b696a 100644 --- a/fs/xfs/xfs_dir2_node.c +++ b/fs/xfs/xfs_dir2_node.c @@ -24,12 +24,10 @@ #include "xfs_sb.h" #include "xfs_ag.h" #include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_da_btree.h" #include "xfs_bmap_btree.h" #include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_bmap.h" diff --git a/fs/xfs/xfs_dir2_sf.c b/fs/xfs/xfs_dir2_sf.c index c1a5945d463a..b1bae6b1eed9 100644 --- a/fs/xfs/xfs_dir2_sf.c +++ b/fs/xfs/xfs_dir2_sf.c @@ -24,12 +24,10 @@ #include "xfs_sb.h" #include "xfs_ag.h" #include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_da_btree.h" #include "xfs_bmap_btree.h" #include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_inode_item.h" diff --git a/fs/xfs/xfs_dmapi.h b/fs/xfs/xfs_dmapi.h deleted file mode 100644 index 2813cdd72375..000000000000 --- a/fs/xfs/xfs_dmapi.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (c) 2000-2005 Silicon Graphics, Inc. - * All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it would be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#ifndef __XFS_DMAPI_H__ -#define __XFS_DMAPI_H__ - -/* Values used to define the on-disk version of dm_attrname_t. All - * on-disk attribute names start with the 8-byte string "SGI_DMI_". - * - * In the on-disk inode, DMAPI attribute names consist of the user-provided - * name with the DMATTR_PREFIXSTRING pre-pended. This string must NEVER be - * changed. - */ - -#define DMATTR_PREFIXLEN 8 -#define DMATTR_PREFIXSTRING "SGI_DMI_" - -typedef enum { - DM_EVENT_INVALID = -1, - DM_EVENT_CANCEL = 0, /* not supported */ - DM_EVENT_MOUNT = 1, - DM_EVENT_PREUNMOUNT = 2, - DM_EVENT_UNMOUNT = 3, - DM_EVENT_DEBUT = 4, /* not supported */ - DM_EVENT_CREATE = 5, - DM_EVENT_CLOSE = 6, /* not supported */ - DM_EVENT_POSTCREATE = 7, - DM_EVENT_REMOVE = 8, - DM_EVENT_POSTREMOVE = 9, - DM_EVENT_RENAME = 10, - DM_EVENT_POSTRENAME = 11, - DM_EVENT_LINK = 12, - DM_EVENT_POSTLINK = 13, - DM_EVENT_SYMLINK = 14, - DM_EVENT_POSTSYMLINK = 15, - DM_EVENT_READ = 16, - DM_EVENT_WRITE = 17, - DM_EVENT_TRUNCATE = 18, - DM_EVENT_ATTRIBUTE = 19, - DM_EVENT_DESTROY = 20, - DM_EVENT_NOSPACE = 21, - DM_EVENT_USER = 22, - DM_EVENT_MAX = 23 -} dm_eventtype_t; -#define HAVE_DM_EVENTTYPE_T - -typedef enum { - DM_RIGHT_NULL, - DM_RIGHT_SHARED, - DM_RIGHT_EXCL -} dm_right_t; -#define HAVE_DM_RIGHT_T - -/* Defines for determining if an event message should be sent. */ -#ifdef HAVE_DMAPI -#define DM_EVENT_ENABLED(ip, event) ( \ - unlikely ((ip)->i_mount->m_flags & XFS_MOUNT_DMAPI) && \ - ( ((ip)->i_d.di_dmevmask & (1 << event)) || \ - ((ip)->i_mount->m_dmevmask & (1 << event)) ) \ - ) -#else -#define DM_EVENT_ENABLED(ip, event) (0) -#endif - -#define DM_XFS_VALID_FS_EVENTS ( \ - (1 << DM_EVENT_PREUNMOUNT) | \ - (1 << DM_EVENT_UNMOUNT) | \ - (1 << DM_EVENT_NOSPACE) | \ - (1 << DM_EVENT_DEBUT) | \ - (1 << DM_EVENT_CREATE) | \ - (1 << DM_EVENT_POSTCREATE) | \ - (1 << DM_EVENT_REMOVE) | \ - (1 << DM_EVENT_POSTREMOVE) | \ - (1 << DM_EVENT_RENAME) | \ - (1 << DM_EVENT_POSTRENAME) | \ - (1 << DM_EVENT_LINK) | \ - (1 << DM_EVENT_POSTLINK) | \ - (1 << DM_EVENT_SYMLINK) | \ - (1 << DM_EVENT_POSTSYMLINK) | \ - (1 << DM_EVENT_ATTRIBUTE) | \ - (1 << DM_EVENT_DESTROY) ) - -/* Events valid in dm_set_eventlist() when called with a file handle for - a regular file or a symlink. These events are persistent. -*/ - -#define DM_XFS_VALID_FILE_EVENTS ( \ - (1 << DM_EVENT_ATTRIBUTE) | \ - (1 << DM_EVENT_DESTROY) ) - -/* Events valid in dm_set_eventlist() when called with a file handle for - a directory. These events are persistent. -*/ - -#define DM_XFS_VALID_DIRECTORY_EVENTS ( \ - (1 << DM_EVENT_CREATE) | \ - (1 << DM_EVENT_POSTCREATE) | \ - (1 << DM_EVENT_REMOVE) | \ - (1 << DM_EVENT_POSTREMOVE) | \ - (1 << DM_EVENT_RENAME) | \ - (1 << DM_EVENT_POSTRENAME) | \ - (1 << DM_EVENT_LINK) | \ - (1 << DM_EVENT_POSTLINK) | \ - (1 << DM_EVENT_SYMLINK) | \ - (1 << DM_EVENT_POSTSYMLINK) | \ - (1 << DM_EVENT_ATTRIBUTE) | \ - (1 << DM_EVENT_DESTROY) ) - -/* Events supported by the XFS filesystem. */ -#define DM_XFS_SUPPORTED_EVENTS ( \ - (1 << DM_EVENT_MOUNT) | \ - (1 << DM_EVENT_PREUNMOUNT) | \ - (1 << DM_EVENT_UNMOUNT) | \ - (1 << DM_EVENT_NOSPACE) | \ - (1 << DM_EVENT_CREATE) | \ - (1 << DM_EVENT_POSTCREATE) | \ - (1 << DM_EVENT_REMOVE) | \ - (1 << DM_EVENT_POSTREMOVE) | \ - (1 << DM_EVENT_RENAME) | \ - (1 << DM_EVENT_POSTRENAME) | \ - (1 << DM_EVENT_LINK) | \ - (1 << DM_EVENT_POSTLINK) | \ - (1 << DM_EVENT_SYMLINK) | \ - (1 << DM_EVENT_POSTSYMLINK) | \ - (1 << DM_EVENT_READ) | \ - (1 << DM_EVENT_WRITE) | \ - (1 << DM_EVENT_TRUNCATE) | \ - (1 << DM_EVENT_ATTRIBUTE) | \ - (1 << DM_EVENT_DESTROY) ) - - -/* - * Definitions used for the flags field on dm_send_*_event(). - */ - -#define DM_FLAGS_NDELAY 0x001 /* return EAGAIN after dm_pending() */ -#define DM_FLAGS_UNWANTED 0x002 /* event not in fsys dm_eventset_t */ -#define DM_FLAGS_IMUX 0x004 /* thread holds i_mutex */ -#define DM_FLAGS_IALLOCSEM_RD 0x010 /* thread holds i_alloc_sem rd */ -#define DM_FLAGS_IALLOCSEM_WR 0x020 /* thread holds i_alloc_sem wr */ - -/* - * Pull in platform specific event flags defines - */ -#include "xfs_dmapi_priv.h" - -/* - * Macros to turn caller specified delay/block flags into - * dm_send_xxxx_event flag DM_FLAGS_NDELAY. - */ - -#define FILP_DELAY_FLAG(filp) ((filp->f_flags&(O_NDELAY|O_NONBLOCK)) ? \ - DM_FLAGS_NDELAY : 0) -#define AT_DELAY_FLAG(f) ((f & XFS_ATTR_NONBLOCK) ? DM_FLAGS_NDELAY : 0) - -#endif /* __XFS_DMAPI_H__ */ diff --git a/fs/xfs/xfs_dmops.c b/fs/xfs/xfs_dmops.c deleted file mode 100644 index e71e2581c0c3..000000000000 --- a/fs/xfs/xfs_dmops.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2000-2003,2005 Silicon Graphics, Inc. - * All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it would be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include "xfs.h" -#include "xfs_fs.h" -#include "xfs_types.h" -#include "xfs_log.h" -#include "xfs_trans.h" -#include "xfs_sb.h" -#include "xfs_dmapi.h" -#include "xfs_inum.h" -#include "xfs_ag.h" -#include "xfs_mount.h" - - -static struct xfs_dmops xfs_dmcore_stub = { - .xfs_send_data = (xfs_send_data_t)fs_nosys, - .xfs_send_mmap = (xfs_send_mmap_t)fs_noerr, - .xfs_send_destroy = (xfs_send_destroy_t)fs_nosys, - .xfs_send_namesp = (xfs_send_namesp_t)fs_nosys, - .xfs_send_mount = (xfs_send_mount_t)fs_nosys, - .xfs_send_unmount = (xfs_send_unmount_t)fs_noerr, -}; - -int -xfs_dmops_get(struct xfs_mount *mp) -{ - if (mp->m_flags & XFS_MOUNT_DMAPI) { - cmn_err(CE_WARN, - "XFS: dmapi support not available in this kernel."); - return EINVAL; - } - - mp->m_dm_ops = &xfs_dmcore_stub; - return 0; -} - -void -xfs_dmops_put(struct xfs_mount *mp) -{ -} diff --git a/fs/xfs/xfs_error.c b/fs/xfs/xfs_error.c index 047b8a8e5c29..ed9990267661 100644 --- a/fs/xfs/xfs_error.c +++ b/fs/xfs/xfs_error.c @@ -23,12 +23,8 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_utils.h" diff --git a/fs/xfs/xfs_extfree_item.c b/fs/xfs/xfs_extfree_item.c index 409fe81585fd..a55e687bf562 100644 --- a/fs/xfs/xfs_extfree_item.c +++ b/fs/xfs/xfs_extfree_item.c @@ -24,7 +24,6 @@ #include "xfs_buf_item.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_trans_priv.h" #include "xfs_extfree_item.h" @@ -33,18 +32,19 @@ kmem_zone_t *xfs_efi_zone; kmem_zone_t *xfs_efd_zone; -STATIC void xfs_efi_item_unlock(xfs_efi_log_item_t *); +static inline struct xfs_efi_log_item *EFI_ITEM(struct xfs_log_item *lip) +{ + return container_of(lip, struct xfs_efi_log_item, efi_item); +} void -xfs_efi_item_free(xfs_efi_log_item_t *efip) +xfs_efi_item_free( + struct xfs_efi_log_item *efip) { - int nexts = efip->efi_format.efi_nextents; - - if (nexts > XFS_EFI_MAX_FAST_EXTENTS) { + if (efip->efi_format.efi_nextents > XFS_EFI_MAX_FAST_EXTENTS) kmem_free(efip); - } else { + else kmem_zone_free(xfs_efi_zone, efip); - } } /* @@ -52,9 +52,9 @@ xfs_efi_item_free(xfs_efi_log_item_t *efip) * We only need 1 iovec for an efi item. It just logs the efi_log_format * structure. */ -/*ARGSUSED*/ STATIC uint -xfs_efi_item_size(xfs_efi_log_item_t *efip) +xfs_efi_item_size( + struct xfs_log_item *lip) { return 1; } @@ -67,10 +67,12 @@ xfs_efi_item_size(xfs_efi_log_item_t *efip) * slots in the efi item have been filled. */ STATIC void -xfs_efi_item_format(xfs_efi_log_item_t *efip, - xfs_log_iovec_t *log_vector) +xfs_efi_item_format( + struct xfs_log_item *lip, + struct xfs_log_iovec *log_vector) { - uint size; + struct xfs_efi_log_item *efip = EFI_ITEM(lip); + uint size; ASSERT(efip->efi_next_extent == efip->efi_format.efi_nextents); @@ -80,7 +82,7 @@ xfs_efi_item_format(xfs_efi_log_item_t *efip, size += (efip->efi_format.efi_nextents - 1) * sizeof(xfs_extent_t); efip->efi_format.efi_size = 1; - log_vector->i_addr = (xfs_caddr_t)&(efip->efi_format); + log_vector->i_addr = &efip->efi_format; log_vector->i_len = size; log_vector->i_type = XLOG_REG_TYPE_EFI_FORMAT; ASSERT(size >= sizeof(xfs_efi_log_format_t)); @@ -90,60 +92,33 @@ xfs_efi_item_format(xfs_efi_log_item_t *efip, /* * Pinning has no meaning for an efi item, so just return. */ -/*ARGSUSED*/ STATIC void -xfs_efi_item_pin(xfs_efi_log_item_t *efip) +xfs_efi_item_pin( + struct xfs_log_item *lip) { - return; } - /* * While EFIs cannot really be pinned, the unpin operation is the * last place at which the EFI is manipulated during a transaction. * Here we coordinate with xfs_efi_cancel() to determine who gets to * free the EFI. */ -/*ARGSUSED*/ -STATIC void -xfs_efi_item_unpin(xfs_efi_log_item_t *efip) -{ - struct xfs_ail *ailp = efip->efi_item.li_ailp; - - spin_lock(&ailp->xa_lock); - if (efip->efi_flags & XFS_EFI_CANCELED) { - /* xfs_trans_ail_delete() drops the AIL lock. */ - xfs_trans_ail_delete(ailp, (xfs_log_item_t *)efip); - xfs_efi_item_free(efip); - } else { - efip->efi_flags |= XFS_EFI_COMMITTED; - spin_unlock(&ailp->xa_lock); - } -} - -/* - * like unpin only we have to also clear the xaction descriptor - * pointing the log item if we free the item. This routine duplicates - * unpin because efi_flags is protected by the AIL lock. Freeing - * the descriptor and then calling unpin would force us to drop the AIL - * lock which would open up a race condition. - */ STATIC void -xfs_efi_item_unpin_remove(xfs_efi_log_item_t *efip, xfs_trans_t *tp) +xfs_efi_item_unpin( + struct xfs_log_item *lip, + int remove) { - struct xfs_ail *ailp = efip->efi_item.li_ailp; - xfs_log_item_desc_t *lidp; + struct xfs_efi_log_item *efip = EFI_ITEM(lip); + struct xfs_ail *ailp = lip->li_ailp; spin_lock(&ailp->xa_lock); if (efip->efi_flags & XFS_EFI_CANCELED) { - /* - * free the xaction descriptor pointing to this item - */ - lidp = xfs_trans_find_item(tp, (xfs_log_item_t *) efip); - xfs_trans_free_item(tp, lidp); + if (remove) + xfs_trans_del_item(lip); /* xfs_trans_ail_delete() drops the AIL lock. */ - xfs_trans_ail_delete(ailp, (xfs_log_item_t *)efip); + xfs_trans_ail_delete(ailp, lip); xfs_efi_item_free(efip); } else { efip->efi_flags |= XFS_EFI_COMMITTED; @@ -158,9 +133,9 @@ xfs_efi_item_unpin_remove(xfs_efi_log_item_t *efip, xfs_trans_t *tp) * XFS_ITEM_PINNED so that the caller will eventually flush the log. * This should help in getting the EFI out of the AIL. */ -/*ARGSUSED*/ STATIC uint -xfs_efi_item_trylock(xfs_efi_log_item_t *efip) +xfs_efi_item_trylock( + struct xfs_log_item *lip) { return XFS_ITEM_PINNED; } @@ -168,13 +143,12 @@ xfs_efi_item_trylock(xfs_efi_log_item_t *efip) /* * Efi items have no locking, so just return. */ -/*ARGSUSED*/ STATIC void -xfs_efi_item_unlock(xfs_efi_log_item_t *efip) +xfs_efi_item_unlock( + struct xfs_log_item *lip) { - if (efip->efi_item.li_flags & XFS_LI_ABORTED) - xfs_efi_item_free(efip); - return; + if (lip->li_flags & XFS_LI_ABORTED) + xfs_efi_item_free(EFI_ITEM(lip)); } /* @@ -183,9 +157,10 @@ xfs_efi_item_unlock(xfs_efi_log_item_t *efip) * flag is not paid any attention here. Checking for that is delayed * until the EFI is unpinned. */ -/*ARGSUSED*/ STATIC xfs_lsn_t -xfs_efi_item_committed(xfs_efi_log_item_t *efip, xfs_lsn_t lsn) +xfs_efi_item_committed( + struct xfs_log_item *lip, + xfs_lsn_t lsn) { return lsn; } @@ -195,11 +170,10 @@ xfs_efi_item_committed(xfs_efi_log_item_t *efip, xfs_lsn_t lsn) * stuck waiting for all of its corresponding efd items to be * committed to disk. */ -/*ARGSUSED*/ STATIC void -xfs_efi_item_push(xfs_efi_log_item_t *efip) +xfs_efi_item_push( + struct xfs_log_item *lip) { - return; } /* @@ -209,61 +183,55 @@ xfs_efi_item_push(xfs_efi_log_item_t *efip) * example, for inodes, the inode is locked throughout the extent freeing * so the dependency should be recorded there. */ -/*ARGSUSED*/ STATIC void -xfs_efi_item_committing(xfs_efi_log_item_t *efip, xfs_lsn_t lsn) +xfs_efi_item_committing( + struct xfs_log_item *lip, + xfs_lsn_t lsn) { - return; } /* * This is the ops vector shared by all efi log items. */ static struct xfs_item_ops xfs_efi_item_ops = { - .iop_size = (uint(*)(xfs_log_item_t*))xfs_efi_item_size, - .iop_format = (void(*)(xfs_log_item_t*, xfs_log_iovec_t*)) - xfs_efi_item_format, - .iop_pin = (void(*)(xfs_log_item_t*))xfs_efi_item_pin, - .iop_unpin = (void(*)(xfs_log_item_t*))xfs_efi_item_unpin, - .iop_unpin_remove = (void(*)(xfs_log_item_t*, xfs_trans_t *)) - xfs_efi_item_unpin_remove, - .iop_trylock = (uint(*)(xfs_log_item_t*))xfs_efi_item_trylock, - .iop_unlock = (void(*)(xfs_log_item_t*))xfs_efi_item_unlock, - .iop_committed = (xfs_lsn_t(*)(xfs_log_item_t*, xfs_lsn_t)) - xfs_efi_item_committed, - .iop_push = (void(*)(xfs_log_item_t*))xfs_efi_item_push, - .iop_pushbuf = NULL, - .iop_committing = (void(*)(xfs_log_item_t*, xfs_lsn_t)) - xfs_efi_item_committing + .iop_size = xfs_efi_item_size, + .iop_format = xfs_efi_item_format, + .iop_pin = xfs_efi_item_pin, + .iop_unpin = xfs_efi_item_unpin, + .iop_trylock = xfs_efi_item_trylock, + .iop_unlock = xfs_efi_item_unlock, + .iop_committed = xfs_efi_item_committed, + .iop_push = xfs_efi_item_push, + .iop_committing = xfs_efi_item_committing }; /* * Allocate and initialize an efi item with the given number of extents. */ -xfs_efi_log_item_t * -xfs_efi_init(xfs_mount_t *mp, - uint nextents) +struct xfs_efi_log_item * +xfs_efi_init( + struct xfs_mount *mp, + uint nextents) { - xfs_efi_log_item_t *efip; + struct xfs_efi_log_item *efip; uint size; ASSERT(nextents > 0); if (nextents > XFS_EFI_MAX_FAST_EXTENTS) { size = (uint)(sizeof(xfs_efi_log_item_t) + ((nextents - 1) * sizeof(xfs_extent_t))); - efip = (xfs_efi_log_item_t*)kmem_zalloc(size, KM_SLEEP); + efip = kmem_zalloc(size, KM_SLEEP); } else { - efip = (xfs_efi_log_item_t*)kmem_zone_zalloc(xfs_efi_zone, - KM_SLEEP); + efip = kmem_zone_zalloc(xfs_efi_zone, KM_SLEEP); } xfs_log_item_init(mp, &efip->efi_item, XFS_LI_EFI, &xfs_efi_item_ops); efip->efi_format.efi_nextents = nextents; efip->efi_format.efi_id = (__psint_t)(void*)efip; - return (efip); + return efip; } /* @@ -276,7 +244,7 @@ xfs_efi_init(xfs_mount_t *mp, int xfs_efi_copy_format(xfs_log_iovec_t *buf, xfs_efi_log_format_t *dst_efi_fmt) { - xfs_efi_log_format_t *src_efi_fmt = (xfs_efi_log_format_t *)buf->i_addr; + xfs_efi_log_format_t *src_efi_fmt = buf->i_addr; uint i; uint len = sizeof(xfs_efi_log_format_t) + (src_efi_fmt->efi_nextents - 1) * sizeof(xfs_extent_t); @@ -289,8 +257,7 @@ xfs_efi_copy_format(xfs_log_iovec_t *buf, xfs_efi_log_format_t *dst_efi_fmt) memcpy((char *)dst_efi_fmt, (char*)src_efi_fmt, len); return 0; } else if (buf->i_len == len32) { - xfs_efi_log_format_32_t *src_efi_fmt_32 = - (xfs_efi_log_format_32_t *)buf->i_addr; + xfs_efi_log_format_32_t *src_efi_fmt_32 = buf->i_addr; dst_efi_fmt->efi_type = src_efi_fmt_32->efi_type; dst_efi_fmt->efi_size = src_efi_fmt_32->efi_size; @@ -304,8 +271,7 @@ xfs_efi_copy_format(xfs_log_iovec_t *buf, xfs_efi_log_format_t *dst_efi_fmt) } return 0; } else if (buf->i_len == len64) { - xfs_efi_log_format_64_t *src_efi_fmt_64 = - (xfs_efi_log_format_64_t *)buf->i_addr; + xfs_efi_log_format_64_t *src_efi_fmt_64 = buf->i_addr; dst_efi_fmt->efi_type = src_efi_fmt_64->efi_type; dst_efi_fmt->efi_size = src_efi_fmt_64->efi_size; @@ -356,16 +322,18 @@ xfs_efi_release(xfs_efi_log_item_t *efip, } } -STATIC void -xfs_efd_item_free(xfs_efd_log_item_t *efdp) +static inline struct xfs_efd_log_item *EFD_ITEM(struct xfs_log_item *lip) { - int nexts = efdp->efd_format.efd_nextents; + return container_of(lip, struct xfs_efd_log_item, efd_item); +} - if (nexts > XFS_EFD_MAX_FAST_EXTENTS) { +STATIC void +xfs_efd_item_free(struct xfs_efd_log_item *efdp) +{ + if (efdp->efd_format.efd_nextents > XFS_EFD_MAX_FAST_EXTENTS) kmem_free(efdp); - } else { + else kmem_zone_free(xfs_efd_zone, efdp); - } } /* @@ -373,9 +341,9 @@ xfs_efd_item_free(xfs_efd_log_item_t *efdp) * We only need 1 iovec for an efd item. It just logs the efd_log_format * structure. */ -/*ARGSUSED*/ STATIC uint -xfs_efd_item_size(xfs_efd_log_item_t *efdp) +xfs_efd_item_size( + struct xfs_log_item *lip) { return 1; } @@ -388,10 +356,12 @@ xfs_efd_item_size(xfs_efd_log_item_t *efdp) * slots in the efd item have been filled. */ STATIC void -xfs_efd_item_format(xfs_efd_log_item_t *efdp, - xfs_log_iovec_t *log_vector) +xfs_efd_item_format( + struct xfs_log_item *lip, + struct xfs_log_iovec *log_vector) { - uint size; + struct xfs_efd_log_item *efdp = EFD_ITEM(lip); + uint size; ASSERT(efdp->efd_next_extent == efdp->efd_format.efd_nextents); @@ -401,48 +371,38 @@ xfs_efd_item_format(xfs_efd_log_item_t *efdp, size += (efdp->efd_format.efd_nextents - 1) * sizeof(xfs_extent_t); efdp->efd_format.efd_size = 1; - log_vector->i_addr = (xfs_caddr_t)&(efdp->efd_format); + log_vector->i_addr = &efdp->efd_format; log_vector->i_len = size; log_vector->i_type = XLOG_REG_TYPE_EFD_FORMAT; ASSERT(size >= sizeof(xfs_efd_log_format_t)); } - /* * Pinning has no meaning for an efd item, so just return. */ -/*ARGSUSED*/ STATIC void -xfs_efd_item_pin(xfs_efd_log_item_t *efdp) +xfs_efd_item_pin( + struct xfs_log_item *lip) { - return; } - /* * Since pinning has no meaning for an efd item, unpinning does * not either. */ -/*ARGSUSED*/ -STATIC void -xfs_efd_item_unpin(xfs_efd_log_item_t *efdp) -{ - return; -} - -/*ARGSUSED*/ STATIC void -xfs_efd_item_unpin_remove(xfs_efd_log_item_t *efdp, xfs_trans_t *tp) +xfs_efd_item_unpin( + struct xfs_log_item *lip, + int remove) { - return; } /* * Efd items have no locking, so just return success. */ -/*ARGSUSED*/ STATIC uint -xfs_efd_item_trylock(xfs_efd_log_item_t *efdp) +xfs_efd_item_trylock( + struct xfs_log_item *lip) { return XFS_ITEM_LOCKED; } @@ -451,13 +411,12 @@ xfs_efd_item_trylock(xfs_efd_log_item_t *efdp) * Efd items have no locking or pushing, so return failure * so that the caller doesn't bother with us. */ -/*ARGSUSED*/ STATIC void -xfs_efd_item_unlock(xfs_efd_log_item_t *efdp) +xfs_efd_item_unlock( + struct xfs_log_item *lip) { - if (efdp->efd_item.li_flags & XFS_LI_ABORTED) - xfs_efd_item_free(efdp); - return; + if (lip->li_flags & XFS_LI_ABORTED) + xfs_efd_item_free(EFD_ITEM(lip)); } /* @@ -467,15 +426,18 @@ xfs_efd_item_unlock(xfs_efd_log_item_t *efdp) * return -1 to keep the transaction code from further referencing * this item. */ -/*ARGSUSED*/ STATIC xfs_lsn_t -xfs_efd_item_committed(xfs_efd_log_item_t *efdp, xfs_lsn_t lsn) +xfs_efd_item_committed( + struct xfs_log_item *lip, + xfs_lsn_t lsn) { + struct xfs_efd_log_item *efdp = EFD_ITEM(lip); + /* * If we got a log I/O error, it's always the case that the LR with the * EFI got unpinned and freed before the EFD got aborted. */ - if ((efdp->efd_item.li_flags & XFS_LI_ABORTED) == 0) + if (!(lip->li_flags & XFS_LI_ABORTED)) xfs_efi_release(efdp->efd_efip, efdp->efd_format.efd_nextents); xfs_efd_item_free(efdp); @@ -486,11 +448,10 @@ xfs_efd_item_committed(xfs_efd_log_item_t *efdp, xfs_lsn_t lsn) * There isn't much you can do to push on an efd item. It is simply * stuck waiting for the log to be flushed to disk. */ -/*ARGSUSED*/ STATIC void -xfs_efd_item_push(xfs_efd_log_item_t *efdp) +xfs_efd_item_push( + struct xfs_log_item *lip) { - return; } /* @@ -500,55 +461,48 @@ xfs_efd_item_push(xfs_efd_log_item_t *efdp) * example, for inodes, the inode is locked throughout the extent freeing * so the dependency should be recorded there. */ -/*ARGSUSED*/ STATIC void -xfs_efd_item_committing(xfs_efd_log_item_t *efip, xfs_lsn_t lsn) +xfs_efd_item_committing( + struct xfs_log_item *lip, + xfs_lsn_t lsn) { - return; } /* * This is the ops vector shared by all efd log items. */ static struct xfs_item_ops xfs_efd_item_ops = { - .iop_size = (uint(*)(xfs_log_item_t*))xfs_efd_item_size, - .iop_format = (void(*)(xfs_log_item_t*, xfs_log_iovec_t*)) - xfs_efd_item_format, - .iop_pin = (void(*)(xfs_log_item_t*))xfs_efd_item_pin, - .iop_unpin = (void(*)(xfs_log_item_t*))xfs_efd_item_unpin, - .iop_unpin_remove = (void(*)(xfs_log_item_t*, xfs_trans_t*)) - xfs_efd_item_unpin_remove, - .iop_trylock = (uint(*)(xfs_log_item_t*))xfs_efd_item_trylock, - .iop_unlock = (void(*)(xfs_log_item_t*))xfs_efd_item_unlock, - .iop_committed = (xfs_lsn_t(*)(xfs_log_item_t*, xfs_lsn_t)) - xfs_efd_item_committed, - .iop_push = (void(*)(xfs_log_item_t*))xfs_efd_item_push, - .iop_pushbuf = NULL, - .iop_committing = (void(*)(xfs_log_item_t*, xfs_lsn_t)) - xfs_efd_item_committing + .iop_size = xfs_efd_item_size, + .iop_format = xfs_efd_item_format, + .iop_pin = xfs_efd_item_pin, + .iop_unpin = xfs_efd_item_unpin, + .iop_trylock = xfs_efd_item_trylock, + .iop_unlock = xfs_efd_item_unlock, + .iop_committed = xfs_efd_item_committed, + .iop_push = xfs_efd_item_push, + .iop_committing = xfs_efd_item_committing }; - /* * Allocate and initialize an efd item with the given number of extents. */ -xfs_efd_log_item_t * -xfs_efd_init(xfs_mount_t *mp, - xfs_efi_log_item_t *efip, - uint nextents) +struct xfs_efd_log_item * +xfs_efd_init( + struct xfs_mount *mp, + struct xfs_efi_log_item *efip, + uint nextents) { - xfs_efd_log_item_t *efdp; + struct xfs_efd_log_item *efdp; uint size; ASSERT(nextents > 0); if (nextents > XFS_EFD_MAX_FAST_EXTENTS) { size = (uint)(sizeof(xfs_efd_log_item_t) + ((nextents - 1) * sizeof(xfs_extent_t))); - efdp = (xfs_efd_log_item_t*)kmem_zalloc(size, KM_SLEEP); + efdp = kmem_zalloc(size, KM_SLEEP); } else { - efdp = (xfs_efd_log_item_t*)kmem_zone_zalloc(xfs_efd_zone, - KM_SLEEP); + efdp = kmem_zone_zalloc(xfs_efd_zone, KM_SLEEP); } xfs_log_item_init(mp, &efdp->efd_item, XFS_LI_EFD, &xfs_efd_item_ops); @@ -556,5 +510,5 @@ xfs_efd_init(xfs_mount_t *mp, efdp->efd_format.efd_nextents = nextents; efdp->efd_format.efd_efi_id = efip->efi_format.efi_id; - return (efdp); + return efdp; } diff --git a/fs/xfs/xfs_filestream.c b/fs/xfs/xfs_filestream.c index 390850ee6603..9b715dce5699 100644 --- a/fs/xfs/xfs_filestream.c +++ b/fs/xfs/xfs_filestream.c @@ -18,13 +18,9 @@ #include "xfs.h" #include "xfs_bmap_btree.h" #include "xfs_inum.h" -#include "xfs_dir2.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_ag.h" -#include "xfs_dmapi.h" #include "xfs_log.h" #include "xfs_trans.h" #include "xfs_sb.h" @@ -127,6 +123,82 @@ typedef struct fstrm_item xfs_inode_t *pip; /* Parent directory inode pointer. */ } fstrm_item_t; +/* + * Allocation group filestream associations are tracked with per-ag atomic + * counters. These counters allow _xfs_filestream_pick_ag() to tell whether a + * particular AG already has active filestreams associated with it. The mount + * point's m_peraglock is used to protect these counters from per-ag array + * re-allocation during a growfs operation. When xfs_growfs_data_private() is + * about to reallocate the array, it calls xfs_filestream_flush() with the + * m_peraglock held in write mode. + * + * Since xfs_mru_cache_flush() guarantees that all the free functions for all + * the cache elements have finished executing before it returns, it's safe for + * the free functions to use the atomic counters without m_peraglock protection. + * This allows the implementation of xfs_fstrm_free_func() to be agnostic about + * whether it was called with the m_peraglock held in read mode, write mode or + * not held at all. The race condition this addresses is the following: + * + * - The work queue scheduler fires and pulls a filestream directory cache + * element off the LRU end of the cache for deletion, then gets pre-empted. + * - A growfs operation grabs the m_peraglock in write mode, flushes all the + * remaining items from the cache and reallocates the mount point's per-ag + * array, resetting all the counters to zero. + * - The work queue thread resumes and calls the free function for the element + * it started cleaning up earlier. In the process it decrements the + * filestreams counter for an AG that now has no references. + * + * With a shrinkfs feature, the above scenario could panic the system. + * + * All other uses of the following macros should be protected by either the + * m_peraglock held in read mode, or the cache's internal locking exposed by the + * interval between a call to xfs_mru_cache_lookup() and a call to + * xfs_mru_cache_done(). In addition, the m_peraglock must be held in read mode + * when new elements are added to the cache. + * + * Combined, these locking rules ensure that no associations will ever exist in + * the cache that reference per-ag array elements that have since been + * reallocated. + */ +static int +xfs_filestream_peek_ag( + xfs_mount_t *mp, + xfs_agnumber_t agno) +{ + struct xfs_perag *pag; + int ret; + + pag = xfs_perag_get(mp, agno); + ret = atomic_read(&pag->pagf_fstrms); + xfs_perag_put(pag); + return ret; +} + +static int +xfs_filestream_get_ag( + xfs_mount_t *mp, + xfs_agnumber_t agno) +{ + struct xfs_perag *pag; + int ret; + + pag = xfs_perag_get(mp, agno); + ret = atomic_inc_return(&pag->pagf_fstrms); + xfs_perag_put(pag); + return ret; +} + +static void +xfs_filestream_put_ag( + xfs_mount_t *mp, + xfs_agnumber_t agno) +{ + struct xfs_perag *pag; + + pag = xfs_perag_get(mp, agno); + atomic_dec(&pag->pagf_fstrms); + xfs_perag_put(pag); +} /* * Scan the AGs starting at startag looking for an AG that isn't in use and has @@ -355,16 +427,14 @@ xfs_fstrm_free_func( { fstrm_item_t *item = (fstrm_item_t *)data; xfs_inode_t *ip = item->ip; - int ref; ASSERT(ip->i_ino == ino); xfs_iflags_clear(ip, XFS_IFILESTREAM); /* Drop the reference taken on the AG when the item was added. */ - ref = xfs_filestream_put_ag(ip->i_mount, item->ag); + xfs_filestream_put_ag(ip->i_mount, item->ag); - ASSERT(ref >= 0); TRACE_FREE(ip->i_mount, ip, item->pip, item->ag, xfs_filestream_peek_ag(ip->i_mount, item->ag)); diff --git a/fs/xfs/xfs_filestream.h b/fs/xfs/xfs_filestream.h index 260f757bbc5d..09dd9af45434 100644 --- a/fs/xfs/xfs_filestream.h +++ b/fs/xfs/xfs_filestream.h @@ -42,88 +42,6 @@ extern ktrace_t *xfs_filestreams_trace_buf; #endif -/* - * Allocation group filestream associations are tracked with per-ag atomic - * counters. These counters allow _xfs_filestream_pick_ag() to tell whether a - * particular AG already has active filestreams associated with it. The mount - * point's m_peraglock is used to protect these counters from per-ag array - * re-allocation during a growfs operation. When xfs_growfs_data_private() is - * about to reallocate the array, it calls xfs_filestream_flush() with the - * m_peraglock held in write mode. - * - * Since xfs_mru_cache_flush() guarantees that all the free functions for all - * the cache elements have finished executing before it returns, it's safe for - * the free functions to use the atomic counters without m_peraglock protection. - * This allows the implementation of xfs_fstrm_free_func() to be agnostic about - * whether it was called with the m_peraglock held in read mode, write mode or - * not held at all. The race condition this addresses is the following: - * - * - The work queue scheduler fires and pulls a filestream directory cache - * element off the LRU end of the cache for deletion, then gets pre-empted. - * - A growfs operation grabs the m_peraglock in write mode, flushes all the - * remaining items from the cache and reallocates the mount point's per-ag - * array, resetting all the counters to zero. - * - The work queue thread resumes and calls the free function for the element - * it started cleaning up earlier. In the process it decrements the - * filestreams counter for an AG that now has no references. - * - * With a shrinkfs feature, the above scenario could panic the system. - * - * All other uses of the following macros should be protected by either the - * m_peraglock held in read mode, or the cache's internal locking exposed by the - * interval between a call to xfs_mru_cache_lookup() and a call to - * xfs_mru_cache_done(). In addition, the m_peraglock must be held in read mode - * when new elements are added to the cache. - * - * Combined, these locking rules ensure that no associations will ever exist in - * the cache that reference per-ag array elements that have since been - * reallocated. - */ -/* - * xfs_filestream_peek_ag is only used in tracing code - */ -static inline int -xfs_filestream_peek_ag( - xfs_mount_t *mp, - xfs_agnumber_t agno) -{ - struct xfs_perag *pag; - int ret; - - pag = xfs_perag_get(mp, agno); - ret = atomic_read(&pag->pagf_fstrms); - xfs_perag_put(pag); - return ret; -} - -static inline int -xfs_filestream_get_ag( - xfs_mount_t *mp, - xfs_agnumber_t agno) -{ - struct xfs_perag *pag; - int ret; - - pag = xfs_perag_get(mp, agno); - ret = atomic_inc_return(&pag->pagf_fstrms); - xfs_perag_put(pag); - return ret; -} - -static inline int -xfs_filestream_put_ag( - xfs_mount_t *mp, - xfs_agnumber_t agno) -{ - struct xfs_perag *pag; - int ret; - - pag = xfs_perag_get(mp, agno); - ret = atomic_dec_return(&pag->pagf_fstrms); - xfs_perag_put(pag); - return ret; -} - /* allocation selection flags */ typedef enum xfs_fstrm_alloc { XFS_PICK_USERDATA = 1, diff --git a/fs/xfs/xfs_fsops.c b/fs/xfs/xfs_fsops.c index 37a6f62c57b6..dbca5f5c37ba 100644 --- a/fs/xfs/xfs_fsops.c +++ b/fs/xfs/xfs_fsops.c @@ -24,14 +24,10 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_inode_item.h" @@ -626,8 +622,7 @@ xfs_fs_log_dummy( ip = mp->m_rootip; xfs_ilock(ip, XFS_ILOCK_EXCL); - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); xfs_trans_log_inode(tp, ip, XFS_ILOG_CORE); xfs_trans_set_sync(tp); error = xfs_trans_commit(tp, 0); diff --git a/fs/xfs/xfs_ialloc.c b/fs/xfs/xfs_ialloc.c index c7142a064c48..abf80ae1e95b 100644 --- a/fs/xfs/xfs_ialloc.c +++ b/fs/xfs/xfs_ialloc.c @@ -24,14 +24,10 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_btree.h" diff --git a/fs/xfs/xfs_ialloc_btree.c b/fs/xfs/xfs_ialloc_btree.c index c282a9af5393..d352862cefa0 100644 --- a/fs/xfs/xfs_ialloc_btree.c +++ b/fs/xfs/xfs_ialloc_btree.c @@ -24,14 +24,10 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_btree.h" diff --git a/fs/xfs/xfs_iget.c b/fs/xfs/xfs_iget.c index 8f8b91be2c99..b1ecc6f97ade 100644 --- a/fs/xfs/xfs_iget.c +++ b/fs/xfs/xfs_iget.c @@ -25,14 +25,10 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_btree.h" @@ -95,7 +91,7 @@ xfs_inode_alloc( return ip; } -STATIC void +void xfs_inode_free( struct xfs_inode *ip) { @@ -212,7 +208,7 @@ xfs_iget_cache_hit( ip->i_flags &= ~XFS_INEW; ip->i_flags |= XFS_IRECLAIMABLE; __xfs_inode_set_reclaim_tag(pag, ip); - trace_xfs_iget_reclaim(ip); + trace_xfs_iget_reclaim_fail(ip); goto out_error; } @@ -227,6 +223,7 @@ xfs_iget_cache_hit( } else { /* If the VFS inode is being torn down, pause and try again. */ if (!igrab(inode)) { + trace_xfs_iget_skip(ip); error = EAGAIN; goto out_error; } @@ -234,6 +231,7 @@ xfs_iget_cache_hit( /* We've got a live one. */ spin_unlock(&ip->i_flags_lock); read_unlock(&pag->pag_ici_lock); + trace_xfs_iget_hit(ip); } if (lock_flags != 0) @@ -242,7 +240,6 @@ xfs_iget_cache_hit( xfs_iflags_clear(ip, XFS_ISTALE); XFS_STATS_INC(xs_ig_found); - trace_xfs_iget_found(ip); return 0; out_error: @@ -264,7 +261,6 @@ xfs_iget_cache_miss( { struct xfs_inode *ip; int error; - unsigned long first_index, mask; xfs_agino_t agino = XFS_INO_TO_AGINO(mp, ino); ip = xfs_inode_alloc(mp, ino); @@ -275,7 +271,7 @@ xfs_iget_cache_miss( if (error) goto out_destroy; - xfs_itrace_entry(ip); + trace_xfs_iget_miss(ip); if ((ip->i_d.di_mode == 0) && !(flags & XFS_IGET_CREATE)) { error = ENOENT; @@ -301,8 +297,6 @@ xfs_iget_cache_miss( BUG(); } - mask = ~(((XFS_INODE_CLUSTER_SIZE(mp) >> mp->m_sb.sb_inodelog)) - 1); - first_index = agino & mask; write_lock(&pag->pag_ici_lock); /* insert the new inode */ @@ -321,7 +315,6 @@ xfs_iget_cache_miss( write_unlock(&pag->pag_ici_lock); radix_tree_preload_end(); - trace_xfs_iget_alloc(ip); *ipp = ip; return 0; @@ -422,97 +415,6 @@ out_error_or_again: } /* - * Decrement reference count of an inode structure and unlock it. - * - * ip -- the inode being released - * lock_flags -- this parameter indicates the inode's locks to be - * to be released. See the comment on xfs_iunlock() for a list - * of valid values. - */ -void -xfs_iput(xfs_inode_t *ip, - uint lock_flags) -{ - xfs_itrace_entry(ip); - xfs_iunlock(ip, lock_flags); - IRELE(ip); -} - -/* - * Special iput for brand-new inodes that are still locked - */ -void -xfs_iput_new( - xfs_inode_t *ip, - uint lock_flags) -{ - struct inode *inode = VFS_I(ip); - - xfs_itrace_entry(ip); - - if ((ip->i_d.di_mode == 0)) { - ASSERT(!xfs_iflags_test(ip, XFS_IRECLAIMABLE)); - make_bad_inode(inode); - } - if (inode->i_state & I_NEW) - unlock_new_inode(inode); - if (lock_flags) - xfs_iunlock(ip, lock_flags); - IRELE(ip); -} - -/* - * This is called free all the memory associated with an inode. - * It must free the inode itself and any buffers allocated for - * if_extents/if_data and if_broot. It must also free the lock - * associated with the inode. - * - * Note: because we don't initialise everything on reallocation out - * of the zone, we must ensure we nullify everything correctly before - * freeing the structure. - */ -void -xfs_ireclaim( - struct xfs_inode *ip) -{ - struct xfs_mount *mp = ip->i_mount; - struct xfs_perag *pag; - xfs_agino_t agino = XFS_INO_TO_AGINO(mp, ip->i_ino); - - XFS_STATS_INC(xs_ig_reclaims); - - /* - * Remove the inode from the per-AG radix tree. - * - * Because radix_tree_delete won't complain even if the item was never - * added to the tree assert that it's been there before to catch - * problems with the inode life time early on. - */ - pag = xfs_perag_get(mp, XFS_INO_TO_AGNO(mp, ip->i_ino)); - write_lock(&pag->pag_ici_lock); - if (!radix_tree_delete(&pag->pag_ici_root, agino)) - ASSERT(0); - write_unlock(&pag->pag_ici_lock); - xfs_perag_put(pag); - - /* - * Here we do an (almost) spurious inode lock in order to coordinate - * with inode cache radix tree lookups. This is because the lookup - * can reference the inodes in the cache without taking references. - * - * We make that OK here by ensuring that we wait until the inode is - * unlocked after the lookup before we go ahead and free it. We get - * both the ilock and the iolock because the code may need to drop the - * ilock one but will still hold the iolock. - */ - xfs_ilock(ip, XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); - xfs_qm_dqdetach(ip); - xfs_iunlock(ip, XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); - - xfs_inode_free(ip); -} - -/* * This is a wrapper routine around the xfs_ilock() routine * used to centralize some grungy code. It is used in places * that wish to lock the inode solely for reading the extents. diff --git a/fs/xfs/xfs_inode.c b/fs/xfs/xfs_inode.c index b76a829d7e20..68415cb4f23c 100644 --- a/fs/xfs/xfs_inode.c +++ b/fs/xfs/xfs_inode.c @@ -27,13 +27,10 @@ #include "xfs_trans_priv.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" #include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" @@ -44,7 +41,6 @@ #include "xfs_alloc.h" #include "xfs_ialloc.h" #include "xfs_bmap.h" -#include "xfs_rw.h" #include "xfs_error.h" #include "xfs_utils.h" #include "xfs_quota.h" @@ -426,7 +422,7 @@ xfs_iformat( if (!XFS_DFORK_Q(dip)) return 0; ASSERT(ip->i_afp == NULL); - ip->i_afp = kmem_zone_zalloc(xfs_ifork_zone, KM_SLEEP); + ip->i_afp = kmem_zone_zalloc(xfs_ifork_zone, KM_SLEEP | KM_NOFS); ip->i_afp->if_ext_max = XFS_IFORK_ASIZE(ip) / (uint)sizeof(xfs_bmbt_rec_t); switch (dip->di_aformat) { @@ -509,7 +505,7 @@ xfs_iformat_local( ifp->if_u1.if_data = ifp->if_u2.if_inline_data; else { real_size = roundup(size, 4); - ifp->if_u1.if_data = kmem_alloc(real_size, KM_SLEEP); + ifp->if_u1.if_data = kmem_alloc(real_size, KM_SLEEP | KM_NOFS); } ifp->if_bytes = size; ifp->if_real_bytes = real_size; @@ -636,7 +632,7 @@ xfs_iformat_btree( } ifp->if_broot_bytes = size; - ifp->if_broot = kmem_alloc(size, KM_SLEEP); + ifp->if_broot = kmem_alloc(size, KM_SLEEP | KM_NOFS); ASSERT(ifp->if_broot != NULL); /* * Copy and convert from the on-disk structure @@ -922,7 +918,6 @@ xfs_iread_extents( int error; xfs_ifork_t *ifp; xfs_extnum_t nextents; - size_t size; if (unlikely(XFS_IFORK_FORMAT(ip, whichfork) != XFS_DINODE_FMT_BTREE)) { XFS_ERROR_REPORT("xfs_iread_extents", XFS_ERRLEVEL_LOW, @@ -930,7 +925,6 @@ xfs_iread_extents( return XFS_ERROR(EFSCORRUPTED); } nextents = XFS_IFORK_NEXTENTS(ip, whichfork); - size = nextents * sizeof(xfs_bmbt_rec_t); ifp = XFS_IFORK_PTR(ip, whichfork); /* @@ -1226,7 +1220,7 @@ xfs_isize_check( (xfs_ufsize_t)XFS_MAXIOFFSET(mp)) - map_first), XFS_BMAPI_ENTIRE, NULL, 0, imaps, &nimaps, - NULL, NULL)) + NULL)) return; ASSERT(nimaps == 1); ASSERT(imaps[0].br_startblock == HOLESTARTBLOCK); @@ -1460,7 +1454,7 @@ xfs_itruncate_finish( ASSERT((*tp)->t_flags & XFS_TRANS_PERM_LOG_RES); ASSERT(ip->i_transp == *tp); ASSERT(ip->i_itemp != NULL); - ASSERT(ip->i_itemp->ili_flags & XFS_ILI_HOLD); + ASSERT(ip->i_itemp->ili_lock_flags == 0); ntp = *tp; @@ -1589,11 +1583,10 @@ xfs_itruncate_finish( xfs_bmap_init(&free_list, &first_block); error = xfs_bunmapi(ntp, ip, first_unmap_block, unmap_len, - xfs_bmapi_aflag(fork) | - (sync ? 0 : XFS_BMAPI_ASYNC), + xfs_bmapi_aflag(fork), XFS_ITRUNC_MAX_EXTENTS, &first_block, &free_list, - NULL, &done); + &done); if (error) { /* * If the bunmapi call encounters an error, @@ -1612,12 +1605,8 @@ xfs_itruncate_finish( */ error = xfs_bmap_finish(tp, &free_list, &committed); ntp = *tp; - if (committed) { - /* link the inode into the next xact in the chain */ - xfs_trans_ijoin(ntp, ip, - XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); - xfs_trans_ihold(ntp, ip); - } + if (committed) + xfs_trans_ijoin(ntp, ip); if (error) { /* @@ -1646,9 +1635,7 @@ xfs_itruncate_finish( error = xfs_trans_commit(*tp, 0); *tp = ntp; - /* link the inode into the next transaction in the chain */ - xfs_trans_ijoin(ntp, ip, XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); - xfs_trans_ihold(ntp, ip); + xfs_trans_ijoin(ntp, ip); if (error) return error; @@ -1985,7 +1972,7 @@ xfs_ifree_cluster( if (lip->li_type == XFS_LI_INODE) { iip = (xfs_inode_log_item_t *)lip; ASSERT(iip->ili_logged == 1); - lip->li_cb = (void(*)(xfs_buf_t*,xfs_log_item_t*)) xfs_istale_done; + lip->li_cb = xfs_istale_done; xfs_trans_ail_copy_lsn(mp->m_ail, &iip->ili_flush_lsn, &iip->ili_item.li_lsn); @@ -2055,9 +2042,8 @@ xfs_ifree_cluster( xfs_trans_ail_copy_lsn(mp->m_ail, &iip->ili_flush_lsn, &iip->ili_item.li_lsn); - xfs_buf_attach_iodone(bp, - (void(*)(xfs_buf_t*,xfs_log_item_t*)) - xfs_istale_done, (xfs_log_item_t *)iip); + xfs_buf_attach_iodone(bp, xfs_istale_done, + &iip->ili_item); if (ip != free_ip) xfs_iunlock(ip, XFS_ILOCK_EXCL); @@ -2203,7 +2189,7 @@ xfs_iroot_realloc( */ if (ifp->if_broot_bytes == 0) { new_size = (size_t)XFS_BMAP_BROOT_SPACE_CALC(rec_diff); - ifp->if_broot = kmem_alloc(new_size, KM_SLEEP); + ifp->if_broot = kmem_alloc(new_size, KM_SLEEP | KM_NOFS); ifp->if_broot_bytes = (int)new_size; return; } @@ -2219,7 +2205,7 @@ xfs_iroot_realloc( new_size = (size_t)XFS_BMAP_BROOT_SPACE_CALC(new_max); ifp->if_broot = kmem_realloc(ifp->if_broot, new_size, (size_t)XFS_BMAP_BROOT_SPACE_CALC(cur_max), /* old size */ - KM_SLEEP); + KM_SLEEP | KM_NOFS); op = (char *)XFS_BMAP_BROOT_PTR_ADDR(mp, ifp->if_broot, 1, ifp->if_broot_bytes); np = (char *)XFS_BMAP_BROOT_PTR_ADDR(mp, ifp->if_broot, 1, @@ -2245,7 +2231,7 @@ xfs_iroot_realloc( else new_size = 0; if (new_size > 0) { - new_broot = kmem_alloc(new_size, KM_SLEEP); + new_broot = kmem_alloc(new_size, KM_SLEEP | KM_NOFS); /* * First copy over the btree block header. */ @@ -2349,7 +2335,8 @@ xfs_idata_realloc( real_size = roundup(new_size, 4); if (ifp->if_u1.if_data == NULL) { ASSERT(ifp->if_real_bytes == 0); - ifp->if_u1.if_data = kmem_alloc(real_size, KM_SLEEP); + ifp->if_u1.if_data = kmem_alloc(real_size, + KM_SLEEP | KM_NOFS); } else if (ifp->if_u1.if_data != ifp->if_u2.if_inline_data) { /* * Only do the realloc if the underlying size @@ -2360,11 +2347,12 @@ xfs_idata_realloc( kmem_realloc(ifp->if_u1.if_data, real_size, ifp->if_real_bytes, - KM_SLEEP); + KM_SLEEP | KM_NOFS); } } else { ASSERT(ifp->if_real_bytes == 0); - ifp->if_u1.if_data = kmem_alloc(real_size, KM_SLEEP); + ifp->if_u1.if_data = kmem_alloc(real_size, + KM_SLEEP | KM_NOFS); memcpy(ifp->if_u1.if_data, ifp->if_u2.if_inline_data, ifp->if_bytes); } @@ -2731,7 +2719,6 @@ cluster_corrupt_out: * mark it as stale and brelse. */ if (XFS_BUF_IODONE_FUNC(bp)) { - XFS_BUF_CLR_BDSTRAT_FUNC(bp); XFS_BUF_UNDONE(bp); XFS_BUF_STALE(bp); XFS_BUF_ERROR(bp,EIO); @@ -3069,8 +3056,7 @@ xfs_iflush_int( * and unlock the inode's flush lock when the inode is * completely written to disk. */ - xfs_buf_attach_iodone(bp, (void(*)(xfs_buf_t*,xfs_log_item_t*)) - xfs_iflush_done, (xfs_log_item_t *)iip); + xfs_buf_attach_iodone(bp, xfs_iflush_done, &iip->ili_item); ASSERT(XFS_BUF_FSPRIVATE(bp, void *) != NULL); ASSERT(XFS_BUF_IODONE_FUNC(bp) != NULL); @@ -3514,13 +3500,11 @@ xfs_iext_remove_indirect( xfs_extnum_t ext_diff; /* extents to remove in current list */ xfs_extnum_t nex1; /* number of extents before idx */ xfs_extnum_t nex2; /* extents after idx + count */ - int nlists; /* entries in indirection array */ int page_idx = idx; /* index in target extent list */ ASSERT(ifp->if_flags & XFS_IFEXTIREC); erp = xfs_iext_idx_to_irec(ifp, &page_idx, &erp_idx, 0); ASSERT(erp != NULL); - nlists = ifp->if_real_bytes / XFS_IEXT_BUFSZ; nex1 = page_idx; ext_cnt = count; while (ext_cnt) { diff --git a/fs/xfs/xfs_inode.h b/fs/xfs/xfs_inode.h index 78550df13cd6..0898c5417d12 100644 --- a/fs/xfs/xfs_inode.h +++ b/fs/xfs/xfs_inode.h @@ -443,8 +443,6 @@ static inline void xfs_ifunlock(xfs_inode_t *ip) */ int xfs_iget(struct xfs_mount *, struct xfs_trans *, xfs_ino_t, uint, uint, xfs_inode_t **); -void xfs_iput(xfs_inode_t *, uint); -void xfs_iput_new(xfs_inode_t *, uint); void xfs_ilock(xfs_inode_t *, uint); int xfs_ilock_nowait(xfs_inode_t *, uint); void xfs_iunlock(xfs_inode_t *, uint); @@ -452,7 +450,7 @@ void xfs_ilock_demote(xfs_inode_t *, uint); int xfs_isilocked(xfs_inode_t *, uint); uint xfs_ilock_map_shared(xfs_inode_t *); void xfs_iunlock_map_shared(xfs_inode_t *, uint); -void xfs_ireclaim(xfs_inode_t *); +void xfs_inode_free(struct xfs_inode *ip); /* * xfs_inode.c prototypes. diff --git a/fs/xfs/xfs_inode_item.c b/fs/xfs/xfs_inode_item.c index cf8249a60004..fe00777e2796 100644 --- a/fs/xfs/xfs_inode_item.c +++ b/fs/xfs/xfs_inode_item.c @@ -22,30 +22,26 @@ #include "xfs_log.h" #include "xfs_inum.h" #include "xfs_trans.h" -#include "xfs_buf_item.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_trans_priv.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_inode_item.h" -#include "xfs_btree.h" -#include "xfs_ialloc.h" -#include "xfs_rw.h" #include "xfs_error.h" #include "xfs_trace.h" kmem_zone_t *xfs_ili_zone; /* inode log item zone */ +static inline struct xfs_inode_log_item *INODE_ITEM(struct xfs_log_item *lip) +{ + return container_of(lip, struct xfs_inode_log_item, ili_item); +} + + /* * This returns the number of iovecs needed to log the given inode item. * @@ -55,13 +51,11 @@ kmem_zone_t *xfs_ili_zone; /* inode log item zone */ */ STATIC uint xfs_inode_item_size( - xfs_inode_log_item_t *iip) + struct xfs_log_item *lip) { - uint nvecs; - xfs_inode_t *ip; - - ip = iip->ili_inode; - nvecs = 2; + struct xfs_inode_log_item *iip = INODE_ITEM(lip); + struct xfs_inode *ip = iip->ili_inode; + uint nvecs = 2; /* * Only log the data/extents/b-tree root if there is something @@ -212,21 +206,17 @@ xfs_inode_item_size( */ STATIC void xfs_inode_item_format( - xfs_inode_log_item_t *iip, - xfs_log_iovec_t *log_vector) + struct xfs_log_item *lip, + struct xfs_log_iovec *vecp) { + struct xfs_inode_log_item *iip = INODE_ITEM(lip); + struct xfs_inode *ip = iip->ili_inode; uint nvecs; - xfs_log_iovec_t *vecp; - xfs_inode_t *ip; size_t data_bytes; xfs_bmbt_rec_t *ext_buffer; - int nrecs; xfs_mount_t *mp; - ip = iip->ili_inode; - vecp = log_vector; - - vecp->i_addr = (xfs_caddr_t)&iip->ili_format; + vecp->i_addr = &iip->ili_format; vecp->i_len = sizeof(xfs_inode_log_format_t); vecp->i_type = XLOG_REG_TYPE_IFORMAT; vecp++; @@ -277,7 +267,7 @@ xfs_inode_item_format( */ xfs_synchronize_times(ip); - vecp->i_addr = (xfs_caddr_t)&ip->i_d; + vecp->i_addr = &ip->i_d; vecp->i_len = sizeof(struct xfs_icdinode); vecp->i_type = XLOG_REG_TYPE_ICORE; vecp++; @@ -323,18 +313,17 @@ xfs_inode_item_format( ASSERT(ip->i_df.if_u1.if_extents != NULL); ASSERT(ip->i_d.di_nextents > 0); ASSERT(iip->ili_extents_buf == NULL); - nrecs = ip->i_df.if_bytes / - (uint)sizeof(xfs_bmbt_rec_t); - ASSERT(nrecs > 0); + ASSERT((ip->i_df.if_bytes / + (uint)sizeof(xfs_bmbt_rec_t)) > 0); #ifdef XFS_NATIVE_HOST - if (nrecs == ip->i_d.di_nextents) { + if (ip->i_d.di_nextents == ip->i_df.if_bytes / + (uint)sizeof(xfs_bmbt_rec_t)) { /* * There are no delayed allocation * extents, so just point to the * real extents array. */ - vecp->i_addr = - (char *)(ip->i_df.if_u1.if_extents); + vecp->i_addr = ip->i_df.if_u1.if_extents; vecp->i_len = ip->i_df.if_bytes; vecp->i_type = XLOG_REG_TYPE_IEXT; } else @@ -352,7 +341,7 @@ xfs_inode_item_format( ext_buffer = kmem_alloc(ip->i_df.if_bytes, KM_SLEEP); iip->ili_extents_buf = ext_buffer; - vecp->i_addr = (xfs_caddr_t)ext_buffer; + vecp->i_addr = ext_buffer; vecp->i_len = xfs_iextents_copy(ip, ext_buffer, XFS_DATA_FORK); vecp->i_type = XLOG_REG_TYPE_IEXT; @@ -371,7 +360,7 @@ xfs_inode_item_format( if (iip->ili_format.ilf_fields & XFS_ILOG_DBROOT) { ASSERT(ip->i_df.if_broot_bytes > 0); ASSERT(ip->i_df.if_broot != NULL); - vecp->i_addr = (xfs_caddr_t)ip->i_df.if_broot; + vecp->i_addr = ip->i_df.if_broot; vecp->i_len = ip->i_df.if_broot_bytes; vecp->i_type = XLOG_REG_TYPE_IBROOT; vecp++; @@ -389,7 +378,7 @@ xfs_inode_item_format( ASSERT(ip->i_df.if_u1.if_data != NULL); ASSERT(ip->i_d.di_size > 0); - vecp->i_addr = (xfs_caddr_t)ip->i_df.if_u1.if_data; + vecp->i_addr = ip->i_df.if_u1.if_data; /* * Round i_bytes up to a word boundary. * The underlying memory is guaranteed to @@ -437,7 +426,7 @@ xfs_inode_item_format( * Assert that no attribute-related log flags are set. */ if (!XFS_IFORK_Q(ip)) { - ASSERT(nvecs == iip->ili_item.li_desc->lid_size); + ASSERT(nvecs == lip->li_desc->lid_size); iip->ili_format.ilf_size = nvecs; ASSERT(!(iip->ili_format.ilf_fields & (XFS_ILOG_ADATA | XFS_ILOG_ABROOT | XFS_ILOG_AEXT))); @@ -449,21 +438,21 @@ xfs_inode_item_format( ASSERT(!(iip->ili_format.ilf_fields & (XFS_ILOG_ADATA | XFS_ILOG_ABROOT))); if (iip->ili_format.ilf_fields & XFS_ILOG_AEXT) { - ASSERT(ip->i_afp->if_bytes > 0); - ASSERT(ip->i_afp->if_u1.if_extents != NULL); - ASSERT(ip->i_d.di_anextents > 0); #ifdef DEBUG - nrecs = ip->i_afp->if_bytes / + int nrecs = ip->i_afp->if_bytes / (uint)sizeof(xfs_bmbt_rec_t); -#endif ASSERT(nrecs > 0); ASSERT(nrecs == ip->i_d.di_anextents); + ASSERT(ip->i_afp->if_bytes > 0); + ASSERT(ip->i_afp->if_u1.if_extents != NULL); + ASSERT(ip->i_d.di_anextents > 0); +#endif #ifdef XFS_NATIVE_HOST /* * There are not delayed allocation extents * for attributes, so just point at the array. */ - vecp->i_addr = (char *)(ip->i_afp->if_u1.if_extents); + vecp->i_addr = ip->i_afp->if_u1.if_extents; vecp->i_len = ip->i_afp->if_bytes; #else ASSERT(iip->ili_aextents_buf == NULL); @@ -473,7 +462,7 @@ xfs_inode_item_format( ext_buffer = kmem_alloc(ip->i_afp->if_bytes, KM_SLEEP); iip->ili_aextents_buf = ext_buffer; - vecp->i_addr = (xfs_caddr_t)ext_buffer; + vecp->i_addr = ext_buffer; vecp->i_len = xfs_iextents_copy(ip, ext_buffer, XFS_ATTR_FORK); #endif @@ -490,7 +479,7 @@ xfs_inode_item_format( if (iip->ili_format.ilf_fields & XFS_ILOG_ABROOT) { ASSERT(ip->i_afp->if_broot_bytes > 0); ASSERT(ip->i_afp->if_broot != NULL); - vecp->i_addr = (xfs_caddr_t)ip->i_afp->if_broot; + vecp->i_addr = ip->i_afp->if_broot; vecp->i_len = ip->i_afp->if_broot_bytes; vecp->i_type = XLOG_REG_TYPE_IATTR_BROOT; vecp++; @@ -506,7 +495,7 @@ xfs_inode_item_format( ASSERT(ip->i_afp->if_bytes > 0); ASSERT(ip->i_afp->if_u1.if_data != NULL); - vecp->i_addr = (xfs_caddr_t)ip->i_afp->if_u1.if_data; + vecp->i_addr = ip->i_afp->if_u1.if_data; /* * Round i_bytes up to a word boundary. * The underlying memory is guaranteed to @@ -528,7 +517,7 @@ xfs_inode_item_format( break; } - ASSERT(nvecs == iip->ili_item.li_desc->lid_size); + ASSERT(nvecs == lip->li_desc->lid_size); iip->ili_format.ilf_size = nvecs; } @@ -539,12 +528,14 @@ xfs_inode_item_format( */ STATIC void xfs_inode_item_pin( - xfs_inode_log_item_t *iip) + struct xfs_log_item *lip) { - ASSERT(xfs_isilocked(iip->ili_inode, XFS_ILOCK_EXCL)); + struct xfs_inode *ip = INODE_ITEM(lip)->ili_inode; + + ASSERT(xfs_isilocked(ip, XFS_ILOCK_EXCL)); - trace_xfs_inode_pin(iip->ili_inode, _RET_IP_); - atomic_inc(&iip->ili_inode->i_pincount); + trace_xfs_inode_pin(ip, _RET_IP_); + atomic_inc(&ip->i_pincount); } @@ -554,12 +545,12 @@ xfs_inode_item_pin( * * Also wake up anyone in xfs_iunpin_wait() if the count goes to 0. */ -/* ARGSUSED */ STATIC void xfs_inode_item_unpin( - xfs_inode_log_item_t *iip) + struct xfs_log_item *lip, + int remove) { - struct xfs_inode *ip = iip->ili_inode; + struct xfs_inode *ip = INODE_ITEM(lip)->ili_inode; trace_xfs_inode_unpin(ip, _RET_IP_); ASSERT(atomic_read(&ip->i_pincount) > 0); @@ -567,15 +558,6 @@ xfs_inode_item_unpin( wake_up(&ip->i_ipin_wait); } -/* ARGSUSED */ -STATIC void -xfs_inode_item_unpin_remove( - xfs_inode_log_item_t *iip, - xfs_trans_t *tp) -{ - xfs_inode_item_unpin(iip); -} - /* * This is called to attempt to lock the inode associated with this * inode log item, in preparation for the push routine which does the actual @@ -591,19 +573,16 @@ xfs_inode_item_unpin_remove( */ STATIC uint xfs_inode_item_trylock( - xfs_inode_log_item_t *iip) + struct xfs_log_item *lip) { - register xfs_inode_t *ip; - - ip = iip->ili_inode; + struct xfs_inode_log_item *iip = INODE_ITEM(lip); + struct xfs_inode *ip = iip->ili_inode; - if (xfs_ipincount(ip) > 0) { + if (xfs_ipincount(ip) > 0) return XFS_ITEM_PINNED; - } - if (!xfs_ilock_nowait(ip, XFS_ILOCK_SHARED)) { + if (!xfs_ilock_nowait(ip, XFS_ILOCK_SHARED)) return XFS_ITEM_LOCKED; - } if (!xfs_iflock_nowait(ip)) { /* @@ -629,7 +608,7 @@ xfs_inode_item_trylock( if (!XFS_FORCED_SHUTDOWN(ip->i_mount)) { ASSERT(iip->ili_format.ilf_fields != 0); ASSERT(iip->ili_logged == 0); - ASSERT(iip->ili_item.li_flags & XFS_LI_IN_AIL); + ASSERT(lip->li_flags & XFS_LI_IN_AIL); } #endif return XFS_ITEM_SUCCESS; @@ -643,26 +622,18 @@ xfs_inode_item_trylock( */ STATIC void xfs_inode_item_unlock( - xfs_inode_log_item_t *iip) + struct xfs_log_item *lip) { - uint hold; - uint iolocked; - uint lock_flags; - xfs_inode_t *ip; + struct xfs_inode_log_item *iip = INODE_ITEM(lip); + struct xfs_inode *ip = iip->ili_inode; + unsigned short lock_flags; - ASSERT(iip != NULL); ASSERT(iip->ili_inode->i_itemp != NULL); ASSERT(xfs_isilocked(iip->ili_inode, XFS_ILOCK_EXCL)); - ASSERT((!(iip->ili_inode->i_itemp->ili_flags & - XFS_ILI_IOLOCKED_EXCL)) || - xfs_isilocked(iip->ili_inode, XFS_IOLOCK_EXCL)); - ASSERT((!(iip->ili_inode->i_itemp->ili_flags & - XFS_ILI_IOLOCKED_SHARED)) || - xfs_isilocked(iip->ili_inode, XFS_IOLOCK_SHARED)); + /* * Clear the transaction pointer in the inode. */ - ip = iip->ili_inode; ip->i_transp = NULL; /* @@ -686,34 +657,11 @@ xfs_inode_item_unlock( iip->ili_aextents_buf = NULL; } - /* - * Figure out if we should unlock the inode or not. - */ - hold = iip->ili_flags & XFS_ILI_HOLD; - - /* - * Before clearing out the flags, remember whether we - * are holding the inode's IO lock. - */ - iolocked = iip->ili_flags & XFS_ILI_IOLOCKED_ANY; - - /* - * Clear out the fields of the inode log item particular - * to the current transaction. - */ - iip->ili_flags = 0; - - /* - * Unlock the inode if XFS_ILI_HOLD was not set. - */ - if (!hold) { - lock_flags = XFS_ILOCK_EXCL; - if (iolocked & XFS_ILI_IOLOCKED_EXCL) { - lock_flags |= XFS_IOLOCK_EXCL; - } else if (iolocked & XFS_ILI_IOLOCKED_SHARED) { - lock_flags |= XFS_IOLOCK_SHARED; - } - xfs_iput(iip->ili_inode, lock_flags); + lock_flags = iip->ili_lock_flags; + iip->ili_lock_flags = 0; + if (lock_flags) { + xfs_iunlock(iip->ili_inode, lock_flags); + IRELE(iip->ili_inode); } } @@ -725,13 +673,12 @@ xfs_inode_item_unlock( * is the only one that matters. Therefore, simply return the * given lsn. */ -/*ARGSUSED*/ STATIC xfs_lsn_t xfs_inode_item_committed( - xfs_inode_log_item_t *iip, + struct xfs_log_item *lip, xfs_lsn_t lsn) { - return (lsn); + return lsn; } /* @@ -743,13 +690,12 @@ xfs_inode_item_committed( */ STATIC void xfs_inode_item_pushbuf( - xfs_inode_log_item_t *iip) + struct xfs_log_item *lip) { - xfs_inode_t *ip; - xfs_mount_t *mp; - xfs_buf_t *bp; + struct xfs_inode_log_item *iip = INODE_ITEM(lip); + struct xfs_inode *ip = iip->ili_inode; + struct xfs_buf *bp; - ip = iip->ili_inode; ASSERT(xfs_isilocked(ip, XFS_ILOCK_SHARED)); /* @@ -757,14 +703,13 @@ xfs_inode_item_pushbuf( * inode was taken off the AIL. So, just get out. */ if (completion_done(&ip->i_flush) || - ((iip->ili_item.li_flags & XFS_LI_IN_AIL) == 0)) { + !(lip->li_flags & XFS_LI_IN_AIL)) { xfs_iunlock(ip, XFS_ILOCK_SHARED); return; } - mp = ip->i_mount; - bp = xfs_incore(mp->m_ddev_targp, iip->ili_format.ilf_blkno, - iip->ili_format.ilf_len, XBF_TRYLOCK); + bp = xfs_incore(ip->i_mount->m_ddev_targp, iip->ili_format.ilf_blkno, + iip->ili_format.ilf_len, XBF_TRYLOCK); xfs_iunlock(ip, XFS_ILOCK_SHARED); if (!bp) @@ -772,10 +717,8 @@ xfs_inode_item_pushbuf( if (XFS_BUF_ISDELAYWRITE(bp)) xfs_buf_delwri_promote(bp); xfs_buf_relse(bp); - return; } - /* * This is called to asynchronously write the inode associated with this * inode log item out to disk. The inode will already have been locked by @@ -783,14 +726,14 @@ xfs_inode_item_pushbuf( */ STATIC void xfs_inode_item_push( - xfs_inode_log_item_t *iip) + struct xfs_log_item *lip) { - xfs_inode_t *ip; - - ip = iip->ili_inode; + struct xfs_inode_log_item *iip = INODE_ITEM(lip); + struct xfs_inode *ip = iip->ili_inode; ASSERT(xfs_isilocked(ip, XFS_ILOCK_SHARED)); ASSERT(!completion_done(&ip->i_flush)); + /* * Since we were able to lock the inode's flush lock and * we found it on the AIL, the inode must be dirty. This @@ -813,43 +756,34 @@ xfs_inode_item_push( */ (void) xfs_iflush(ip, 0); xfs_iunlock(ip, XFS_ILOCK_SHARED); - - return; } /* * XXX rcc - this one really has to do something. Probably needs * to stamp in a new field in the incore inode. */ -/* ARGSUSED */ STATIC void xfs_inode_item_committing( - xfs_inode_log_item_t *iip, + struct xfs_log_item *lip, xfs_lsn_t lsn) { - iip->ili_last_lsn = lsn; - return; + INODE_ITEM(lip)->ili_last_lsn = lsn; } /* * This is the ops vector shared by all buf log items. */ static struct xfs_item_ops xfs_inode_item_ops = { - .iop_size = (uint(*)(xfs_log_item_t*))xfs_inode_item_size, - .iop_format = (void(*)(xfs_log_item_t*, xfs_log_iovec_t*)) - xfs_inode_item_format, - .iop_pin = (void(*)(xfs_log_item_t*))xfs_inode_item_pin, - .iop_unpin = (void(*)(xfs_log_item_t*))xfs_inode_item_unpin, - .iop_unpin_remove = (void(*)(xfs_log_item_t*, xfs_trans_t*)) - xfs_inode_item_unpin_remove, - .iop_trylock = (uint(*)(xfs_log_item_t*))xfs_inode_item_trylock, - .iop_unlock = (void(*)(xfs_log_item_t*))xfs_inode_item_unlock, - .iop_committed = (xfs_lsn_t(*)(xfs_log_item_t*, xfs_lsn_t)) - xfs_inode_item_committed, - .iop_push = (void(*)(xfs_log_item_t*))xfs_inode_item_push, - .iop_pushbuf = (void(*)(xfs_log_item_t*))xfs_inode_item_pushbuf, - .iop_committing = (void(*)(xfs_log_item_t*, xfs_lsn_t)) - xfs_inode_item_committing + .iop_size = xfs_inode_item_size, + .iop_format = xfs_inode_item_format, + .iop_pin = xfs_inode_item_pin, + .iop_unpin = xfs_inode_item_unpin, + .iop_trylock = xfs_inode_item_trylock, + .iop_unlock = xfs_inode_item_unlock, + .iop_committed = xfs_inode_item_committed, + .iop_push = xfs_inode_item_push, + .iop_pushbuf = xfs_inode_item_pushbuf, + .iop_committing = xfs_inode_item_committing }; @@ -858,10 +792,10 @@ static struct xfs_item_ops xfs_inode_item_ops = { */ void xfs_inode_item_init( - xfs_inode_t *ip, - xfs_mount_t *mp) + struct xfs_inode *ip, + struct xfs_mount *mp) { - xfs_inode_log_item_t *iip; + struct xfs_inode_log_item *iip; ASSERT(ip->i_itemp == NULL); iip = ip->i_itemp = kmem_zone_zalloc(xfs_ili_zone, KM_SLEEP); @@ -899,14 +833,14 @@ xfs_inode_item_destroy( * from the AIL if it has not been re-logged, and unlocking the inode's * flush lock. */ -/*ARGSUSED*/ void xfs_iflush_done( - xfs_buf_t *bp, - xfs_inode_log_item_t *iip) + struct xfs_buf *bp, + struct xfs_log_item *lip) { + struct xfs_inode_log_item *iip = INODE_ITEM(lip); xfs_inode_t *ip = iip->ili_inode; - struct xfs_ail *ailp = iip->ili_item.li_ailp; + struct xfs_ail *ailp = lip->li_ailp; /* * We only want to pull the item from the AIL if it is @@ -917,12 +851,11 @@ xfs_iflush_done( * the lock since it's cheaper, and then we recheck while * holding the lock before removing the inode from the AIL. */ - if (iip->ili_logged && - (iip->ili_item.li_lsn == iip->ili_flush_lsn)) { + if (iip->ili_logged && lip->li_lsn == iip->ili_flush_lsn) { spin_lock(&ailp->xa_lock); - if (iip->ili_item.li_lsn == iip->ili_flush_lsn) { + if (lip->li_lsn == iip->ili_flush_lsn) { /* xfs_trans_ail_delete() drops the AIL lock. */ - xfs_trans_ail_delete(ailp, (xfs_log_item_t*)iip); + xfs_trans_ail_delete(ailp, lip); } else { spin_unlock(&ailp->xa_lock); } @@ -940,8 +873,6 @@ xfs_iflush_done( * Release the inode's flush lock since we're done with it. */ xfs_ifunlock(ip); - - return; } /* @@ -957,10 +888,8 @@ xfs_iflush_abort( xfs_inode_t *ip) { xfs_inode_log_item_t *iip = ip->i_itemp; - xfs_mount_t *mp; iip = ip->i_itemp; - mp = ip->i_mount; if (iip) { struct xfs_ail *ailp = iip->ili_item.li_ailp; if (iip->ili_item.li_flags & XFS_LI_IN_AIL) { @@ -991,10 +920,10 @@ xfs_iflush_abort( void xfs_istale_done( - xfs_buf_t *bp, - xfs_inode_log_item_t *iip) + struct xfs_buf *bp, + struct xfs_log_item *lip) { - xfs_iflush_abort(iip->ili_inode); + xfs_iflush_abort(INODE_ITEM(lip)->ili_inode); } /* @@ -1007,9 +936,8 @@ xfs_inode_item_format_convert( xfs_inode_log_format_t *in_f) { if (buf->i_len == sizeof(xfs_inode_log_format_32_t)) { - xfs_inode_log_format_32_t *in_f32; + xfs_inode_log_format_32_t *in_f32 = buf->i_addr; - in_f32 = (xfs_inode_log_format_32_t *)buf->i_addr; in_f->ilf_type = in_f32->ilf_type; in_f->ilf_size = in_f32->ilf_size; in_f->ilf_fields = in_f32->ilf_fields; @@ -1025,9 +953,8 @@ xfs_inode_item_format_convert( in_f->ilf_boffset = in_f32->ilf_boffset; return 0; } else if (buf->i_len == sizeof(xfs_inode_log_format_64_t)){ - xfs_inode_log_format_64_t *in_f64; + xfs_inode_log_format_64_t *in_f64 = buf->i_addr; - in_f64 = (xfs_inode_log_format_64_t *)buf->i_addr; in_f->ilf_type = in_f64->ilf_type; in_f->ilf_size = in_f64->ilf_size; in_f->ilf_fields = in_f64->ilf_fields; diff --git a/fs/xfs/xfs_inode_item.h b/fs/xfs/xfs_inode_item.h index 9a467958ecdd..d3dee61e6d91 100644 --- a/fs/xfs/xfs_inode_item.h +++ b/fs/xfs/xfs_inode_item.h @@ -103,12 +103,6 @@ typedef struct xfs_inode_log_format_64 { XFS_ILOG_ADATA | XFS_ILOG_AEXT | \ XFS_ILOG_ABROOT) -#define XFS_ILI_HOLD 0x1 -#define XFS_ILI_IOLOCKED_EXCL 0x2 -#define XFS_ILI_IOLOCKED_SHARED 0x4 - -#define XFS_ILI_IOLOCKED_ANY (XFS_ILI_IOLOCKED_EXCL | XFS_ILI_IOLOCKED_SHARED) - static inline int xfs_ilog_fbroot(int w) { return (w == XFS_DATA_FORK ? XFS_ILOG_DBROOT : XFS_ILOG_ABROOT); @@ -137,7 +131,7 @@ typedef struct xfs_inode_log_item { struct xfs_inode *ili_inode; /* inode ptr */ xfs_lsn_t ili_flush_lsn; /* lsn at last flush */ xfs_lsn_t ili_last_lsn; /* lsn at last transaction */ - unsigned short ili_flags; /* misc flags */ + unsigned short ili_lock_flags; /* lock flags */ unsigned short ili_logged; /* flushed logged data */ unsigned int ili_last_fields; /* fields when flushed */ struct xfs_bmbt_rec *ili_extents_buf; /* array of logged @@ -161,8 +155,8 @@ static inline int xfs_inode_clean(xfs_inode_t *ip) extern void xfs_inode_item_init(struct xfs_inode *, struct xfs_mount *); extern void xfs_inode_item_destroy(struct xfs_inode *); -extern void xfs_iflush_done(struct xfs_buf *, xfs_inode_log_item_t *); -extern void xfs_istale_done(struct xfs_buf *, xfs_inode_log_item_t *); +extern void xfs_iflush_done(struct xfs_buf *, struct xfs_log_item *); +extern void xfs_istale_done(struct xfs_buf *, struct xfs_log_item *); extern void xfs_iflush_abort(struct xfs_inode *); extern int xfs_inode_item_format_convert(xfs_log_iovec_t *, xfs_inode_log_format_t *); diff --git a/fs/xfs/xfs_iomap.c b/fs/xfs/xfs_iomap.c index ef14943829da..20576146369f 100644 --- a/fs/xfs/xfs_iomap.c +++ b/fs/xfs/xfs_iomap.c @@ -23,19 +23,14 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" #include "xfs_alloc.h" -#include "xfs_dmapi.h" #include "xfs_quota.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" -#include "xfs_ialloc.h" #include "xfs_btree.h" #include "xfs_bmap.h" #include "xfs_rtalloc.h" @@ -123,7 +118,7 @@ xfs_iomap( error = xfs_bmapi(NULL, ip, offset_fsb, (xfs_filblks_t)(end_fsb - offset_fsb), bmapi_flags, NULL, 0, imap, - nimaps, NULL, NULL); + nimaps, NULL); if (error) goto out; @@ -138,7 +133,7 @@ xfs_iomap( break; } - if (flags & (BMAPI_DIRECT|BMAPI_MMAP)) { + if (flags & BMAPI_DIRECT) { error = xfs_iomap_write_direct(ip, offset, count, flags, imap, nimaps); } else { @@ -247,7 +242,7 @@ xfs_iomap_write_direct( xfs_off_t offset, size_t count, int flags, - xfs_bmbt_irec_t *ret_imap, + xfs_bmbt_irec_t *imap, int *nmaps) { xfs_mount_t *mp = ip->i_mount; @@ -261,7 +256,6 @@ xfs_iomap_write_direct( int quota_flag; int rt; xfs_trans_t *tp; - xfs_bmbt_irec_t imap; xfs_bmap_free_t free_list; uint qblocks, resblks, resrtextents; int committed; @@ -285,10 +279,10 @@ xfs_iomap_write_direct( if (error) goto error_out; } else { - if (*nmaps && (ret_imap->br_startblock == HOLESTARTBLOCK)) + if (*nmaps && (imap->br_startblock == HOLESTARTBLOCK)) last_fsb = MIN(last_fsb, (xfs_fileoff_t) - ret_imap->br_blockcount + - ret_imap->br_startoff); + imap->br_blockcount + + imap->br_startoff); } count_fsb = last_fsb - offset_fsb; ASSERT(count_fsb > 0); @@ -334,20 +328,22 @@ xfs_iomap_write_direct( if (error) goto error1; - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); bmapi_flag = XFS_BMAPI_WRITE; if ((flags & BMAPI_DIRECT) && (offset < ip->i_size || extsz)) bmapi_flag |= XFS_BMAPI_PREALLOC; /* - * Issue the xfs_bmapi() call to allocate the blocks + * Issue the xfs_bmapi() call to allocate the blocks. + * + * From this point onwards we overwrite the imap pointer that the + * caller gave to us. */ xfs_bmap_init(&free_list, &firstfsb); nimaps = 1; error = xfs_bmapi(tp, ip, offset_fsb, count_fsb, bmapi_flag, - &firstfsb, 0, &imap, &nimaps, &free_list, NULL); + &firstfsb, 0, imap, &nimaps, &free_list); if (error) goto error0; @@ -369,12 +365,11 @@ xfs_iomap_write_direct( goto error_out; } - if (!(imap.br_startblock || XFS_IS_REALTIME_INODE(ip))) { - error = xfs_cmn_err_fsblock_zero(ip, &imap); + if (!(imap->br_startblock || XFS_IS_REALTIME_INODE(ip))) { + error = xfs_cmn_err_fsblock_zero(ip, imap); goto error_out; } - *ret_imap = imap; *nmaps = 1; return 0; @@ -425,7 +420,7 @@ xfs_iomap_eof_want_preallocate( imaps = nimaps; firstblock = NULLFSBLOCK; error = xfs_bmapi(NULL, ip, start_fsb, count_fsb, 0, - &firstblock, 0, imap, &imaps, NULL, NULL); + &firstblock, 0, imap, &imaps, NULL); if (error) return error; for (n = 0; n < imaps; n++) { @@ -500,7 +495,7 @@ retry: (xfs_filblks_t)(last_fsb - offset_fsb), XFS_BMAPI_DELAY | XFS_BMAPI_WRITE | XFS_BMAPI_ENTIRE, &firstblock, 1, imap, - &nimaps, NULL, NULL); + &nimaps, NULL); if (error && (error != ENOSPC)) return XFS_ERROR(error); @@ -548,7 +543,7 @@ xfs_iomap_write_allocate( xfs_inode_t *ip, xfs_off_t offset, size_t count, - xfs_bmbt_irec_t *map, + xfs_bmbt_irec_t *imap, int *retmap) { xfs_mount_t *mp = ip->i_mount; @@ -557,7 +552,6 @@ xfs_iomap_write_allocate( xfs_fsblock_t first_block; xfs_bmap_free_t free_list; xfs_filblks_t count_fsb; - xfs_bmbt_irec_t imap; xfs_trans_t *tp; int nimaps, committed; int error = 0; @@ -573,8 +567,8 @@ xfs_iomap_write_allocate( return XFS_ERROR(error); offset_fsb = XFS_B_TO_FSBT(mp, offset); - count_fsb = map->br_blockcount; - map_start_fsb = map->br_startoff; + count_fsb = imap->br_blockcount; + map_start_fsb = imap->br_startoff; XFS_STATS_ADD(xs_xstrat_bytes, XFS_FSB_TO_B(mp, count_fsb)); @@ -602,8 +596,7 @@ xfs_iomap_write_allocate( return XFS_ERROR(error); } xfs_ilock(ip, XFS_ILOCK_EXCL); - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); xfs_bmap_init(&free_list, &first_block); @@ -654,10 +647,15 @@ xfs_iomap_write_allocate( } } - /* Go get the actual blocks */ + /* + * Go get the actual blocks. + * + * From this point onwards we overwrite the imap + * pointer that the caller gave to us. + */ error = xfs_bmapi(tp, ip, map_start_fsb, count_fsb, XFS_BMAPI_WRITE, &first_block, 1, - &imap, &nimaps, &free_list, NULL); + imap, &nimaps, &free_list); if (error) goto trans_cancel; @@ -676,13 +674,12 @@ xfs_iomap_write_allocate( * See if we were able to allocate an extent that * covers at least part of the callers request */ - if (!(imap.br_startblock || XFS_IS_REALTIME_INODE(ip))) - return xfs_cmn_err_fsblock_zero(ip, &imap); + if (!(imap->br_startblock || XFS_IS_REALTIME_INODE(ip))) + return xfs_cmn_err_fsblock_zero(ip, imap); - if ((offset_fsb >= imap.br_startoff) && - (offset_fsb < (imap.br_startoff + - imap.br_blockcount))) { - *map = imap; + if ((offset_fsb >= imap->br_startoff) && + (offset_fsb < (imap->br_startoff + + imap->br_blockcount))) { *retmap = 1; XFS_STATS_INC(xs_xstrat_quick); return 0; @@ -692,8 +689,8 @@ xfs_iomap_write_allocate( * So far we have not mapped the requested part of the * file, just surrounding data, try again. */ - count_fsb -= imap.br_blockcount; - map_start_fsb = imap.br_startoff + imap.br_blockcount; + count_fsb -= imap->br_blockcount; + map_start_fsb = imap->br_startoff + imap->br_blockcount; } trans_cancel: @@ -766,8 +763,7 @@ xfs_iomap_write_unwritten( } xfs_ilock(ip, XFS_ILOCK_EXCL); - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); /* * Modify the unwritten extent state of the buffer. @@ -776,7 +772,7 @@ xfs_iomap_write_unwritten( nimaps = 1; error = xfs_bmapi(tp, ip, offset_fsb, count_fsb, XFS_BMAPI_WRITE|XFS_BMAPI_CONVERT, &firstfsb, - 1, &imap, &nimaps, &free_list, NULL); + 1, &imap, &nimaps, &free_list); if (error) goto error_on_bmapi_transaction; diff --git a/fs/xfs/xfs_iomap.h b/fs/xfs/xfs_iomap.h index 81ac4afd45b3..7748a430f50d 100644 --- a/fs/xfs/xfs_iomap.h +++ b/fs/xfs/xfs_iomap.h @@ -18,17 +18,16 @@ #ifndef __XFS_IOMAP_H__ #define __XFS_IOMAP_H__ -typedef enum { - /* base extent manipulation calls */ - BMAPI_READ = (1 << 0), /* read extents */ - BMAPI_WRITE = (1 << 1), /* create extents */ - BMAPI_ALLOCATE = (1 << 2), /* delayed allocate to real extents */ - /* modifiers */ - BMAPI_IGNSTATE = (1 << 4), /* ignore unwritten state on read */ - BMAPI_DIRECT = (1 << 5), /* direct instead of buffered write */ - BMAPI_MMAP = (1 << 6), /* allocate for mmap write */ - BMAPI_TRYLOCK = (1 << 7), /* non-blocking request */ -} bmapi_flags_t; +/* base extent manipulation calls */ +#define BMAPI_READ (1 << 0) /* read extents */ +#define BMAPI_WRITE (1 << 1) /* create extents */ +#define BMAPI_ALLOCATE (1 << 2) /* delayed allocate to real extents */ + +/* modifiers */ +#define BMAPI_IGNSTATE (1 << 4) /* ignore unwritten state on read */ +#define BMAPI_DIRECT (1 << 5) /* direct instead of buffered write */ +#define BMAPI_MMA (1 << 6) /* allocate for mmap write */ +#define BMAPI_TRYLOCK (1 << 7) /* non-blocking request */ #define BMAPI_FLAGS \ { BMAPI_READ, "READ" }, \ @@ -36,7 +35,6 @@ typedef enum { { BMAPI_ALLOCATE, "ALLOCATE" }, \ { BMAPI_IGNSTATE, "IGNSTATE" }, \ { BMAPI_DIRECT, "DIRECT" }, \ - { BMAPI_MMAP, "MMAP" }, \ { BMAPI_TRYLOCK, "TRYLOCK" } struct xfs_inode; diff --git a/fs/xfs/xfs_itable.c b/fs/xfs/xfs_itable.c index 2b86f8610512..7e3626e5925c 100644 --- a/fs/xfs/xfs_itable.c +++ b/fs/xfs/xfs_itable.c @@ -24,20 +24,17 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_ialloc.h" #include "xfs_itable.h" #include "xfs_error.h" #include "xfs_btree.h" +#include "xfs_trace.h" STATIC int xfs_internal_inum( @@ -143,7 +140,8 @@ xfs_bulkstat_one_int( buf->bs_blocks = dic->di_nblocks + ip->i_delayed_blks; break; } - xfs_iput(ip, XFS_ILOCK_SHARED); + xfs_iunlock(ip, XFS_ILOCK_SHARED); + IRELE(ip); error = formatter(buffer, ubsize, ubused, buf); diff --git a/fs/xfs/xfs_log.c b/fs/xfs/xfs_log.c index 5215abc8023a..925d572bf0f4 100644 --- a/fs/xfs/xfs_log.c +++ b/fs/xfs/xfs_log.c @@ -24,8 +24,6 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_error.h" #include "xfs_log_priv.h" @@ -35,8 +33,6 @@ #include "xfs_ialloc_btree.h" #include "xfs_log_recover.h" #include "xfs_trans_priv.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_rw.h" @@ -337,7 +333,6 @@ xfs_log_reserve( int retval = 0; ASSERT(client == XFS_TRANSACTION || client == XFS_LOG); - ASSERT((flags & XFS_LOG_NOSLEEP) == 0); if (XLOG_FORCED_SHUTDOWN(log)) return XFS_ERROR(EIO); @@ -552,7 +547,7 @@ xfs_log_unmount_write(xfs_mount_t *mp) .magic = XLOG_UNMOUNT_TYPE, }; struct xfs_log_iovec reg = { - .i_addr = (void *)&magic, + .i_addr = &magic, .i_len = sizeof(magic), .i_type = XLOG_REG_TYPE_UNMOUNT, }; @@ -1047,7 +1042,6 @@ xlog_alloc_log(xfs_mount_t *mp, xlog_in_core_t *iclog, *prev_iclog=NULL; xfs_buf_t *bp; int i; - int iclogsize; int error = ENOMEM; uint log2_size = 0; @@ -1127,7 +1121,6 @@ xlog_alloc_log(xfs_mount_t *mp, * with different amounts of memory. See the definition of * xlog_in_core_t in xfs_log_priv.h for details. */ - iclogsize = log->l_iclog_size; ASSERT(log->l_iclog_size >= 4096); for (i=0; i < log->l_iclog_bufs; i++) { *iclogp = kmem_zalloc(sizeof(xlog_in_core_t), KM_MAYFAIL); @@ -1428,11 +1421,8 @@ xlog_sync(xlog_t *log, XFS_BUF_BUSY(bp); XFS_BUF_ASYNC(bp); bp->b_flags |= XBF_LOG_BUFFER; - /* - * Do an ordered write for the log block. - * Its unnecessary to flush the first split block in the log wrap case. - */ - if (!split && (log->l_mp->m_flags & XFS_MOUNT_BARRIER)) + + if (log->l_mp->m_flags & XFS_MOUNT_BARRIER) XFS_BUF_ORDERED(bp); ASSERT(XFS_BUF_ADDR(bp) <= log->l_logBBsize-1); diff --git a/fs/xfs/xfs_log.h b/fs/xfs/xfs_log.h index 04c78e642cc8..916eb7db14d9 100644 --- a/fs/xfs/xfs_log.h +++ b/fs/xfs/xfs_log.h @@ -55,14 +55,10 @@ static inline xfs_lsn_t _lsn_cmp(xfs_lsn_t lsn1, xfs_lsn_t lsn2) /* * Flags to xfs_log_reserve() * - * XFS_LOG_SLEEP: If space is not available, sleep (default) - * XFS_LOG_NOSLEEP: If space is not available, return error * XFS_LOG_PERM_RESERV: Permanent reservation. When writes are * performed against this type of reservation, the reservation * is not decreased. Long running transactions should use this. */ -#define XFS_LOG_SLEEP 0x0 -#define XFS_LOG_NOSLEEP 0x1 #define XFS_LOG_PERM_RESERV 0x2 /* @@ -104,7 +100,7 @@ static inline xfs_lsn_t _lsn_cmp(xfs_lsn_t lsn1, xfs_lsn_t lsn2) #define XLOG_REG_TYPE_MAX 19 typedef struct xfs_log_iovec { - xfs_caddr_t i_addr; /* beginning address of region */ + void *i_addr; /* beginning address of region */ int i_len; /* length in bytes of region */ uint i_type; /* type of region */ } xfs_log_iovec_t; @@ -201,9 +197,4 @@ int xfs_log_commit_cil(struct xfs_mount *mp, struct xfs_trans *tp, bool xfs_log_item_in_current_chkpt(struct xfs_log_item *lip); #endif - - -extern int xlog_debug; /* set to 1 to enable real log */ - - #endif /* __XFS_LOG_H__ */ diff --git a/fs/xfs/xfs_log_cil.c b/fs/xfs/xfs_log_cil.c index bb17cc044bf3..31e4ea2d19ac 100644 --- a/fs/xfs/xfs_log_cil.c +++ b/fs/xfs/xfs_log_cil.c @@ -26,8 +26,6 @@ #include "xfs_log_priv.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_error.h" #include "xfs_alloc.h" @@ -554,7 +552,7 @@ xlog_cil_push( thdr.th_type = XFS_TRANS_CHECKPOINT; thdr.th_tid = tic->t_tid; thdr.th_num_items = num_iovecs; - lhdr.i_addr = (xfs_caddr_t)&thdr; + lhdr.i_addr = &thdr; lhdr.i_len = sizeof(xfs_trans_header_t); lhdr.i_type = XLOG_REG_TYPE_TRANSHDR; tic->t_curr_res -= lhdr.i_len + sizeof(xlog_op_header_t); diff --git a/fs/xfs/xfs_log_recover.c b/fs/xfs/xfs_log_recover.c index 9ac5cfab27b9..6f3f5fa37acf 100644 --- a/fs/xfs/xfs_log_recover.c +++ b/fs/xfs/xfs_log_recover.c @@ -24,15 +24,11 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_error.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_inode_item.h" @@ -1565,9 +1561,7 @@ xlog_recover_reorder_trans( list_splice_init(&trans->r_itemq, &sort_list); list_for_each_entry_safe(item, n, &sort_list, ri_list) { - xfs_buf_log_format_t *buf_f; - - buf_f = (xfs_buf_log_format_t *)item->ri_buf[0].i_addr; + xfs_buf_log_format_t *buf_f = item->ri_buf[0].i_addr; switch (ITEM_TYPE(item)) { case XFS_LI_BUF: @@ -1892,9 +1886,8 @@ xlog_recover_do_inode_buffer( * current di_next_unlinked field. Extract its value * and copy it to the buffer copy. */ - logged_nextp = (xfs_agino_t *) - ((char *)(item->ri_buf[item_index].i_addr) + - (next_unlinked_offset - reg_buf_offset)); + logged_nextp = item->ri_buf[item_index].i_addr + + next_unlinked_offset - reg_buf_offset; if (unlikely(*logged_nextp == 0)) { xfs_fs_cmn_err(CE_ALERT, mp, "bad inode buffer log record (ptr = 0x%p, bp = 0x%p). XFS trying to replay bad (0) inode di_next_unlinked field", @@ -1973,8 +1966,7 @@ xlog_recover_do_reg_buffer( item->ri_buf[i].i_len, __func__); goto next; } - error = xfs_qm_dqcheck((xfs_disk_dquot_t *) - item->ri_buf[i].i_addr, + error = xfs_qm_dqcheck(item->ri_buf[i].i_addr, -1, 0, XFS_QMOPT_DOWARN, "dquot_buf_recover"); if (error) @@ -2187,7 +2179,7 @@ xlog_recover_do_buffer_trans( xlog_recover_item_t *item, int pass) { - xfs_buf_log_format_t *buf_f; + xfs_buf_log_format_t *buf_f = item->ri_buf[0].i_addr; xfs_mount_t *mp; xfs_buf_t *bp; int error; @@ -2197,8 +2189,6 @@ xlog_recover_do_buffer_trans( ushort flags; uint buf_flags; - buf_f = (xfs_buf_log_format_t *)item->ri_buf[0].i_addr; - if (pass == XLOG_RECOVER_PASS1) { /* * In this pass we're only looking for buf items @@ -2319,10 +2309,9 @@ xlog_recover_do_inode_trans( } if (item->ri_buf[0].i_len == sizeof(xfs_inode_log_format_t)) { - in_f = (xfs_inode_log_format_t *)item->ri_buf[0].i_addr; + in_f = item->ri_buf[0].i_addr; } else { - in_f = (xfs_inode_log_format_t *)kmem_alloc( - sizeof(xfs_inode_log_format_t), KM_SLEEP); + in_f = kmem_alloc(sizeof(xfs_inode_log_format_t), KM_SLEEP); need_free = 1; error = xfs_inode_item_format_convert(&item->ri_buf[0], in_f); if (error) @@ -2370,7 +2359,7 @@ xlog_recover_do_inode_trans( error = EFSCORRUPTED; goto error; } - dicp = (xfs_icdinode_t *)(item->ri_buf[1].i_addr); + dicp = item->ri_buf[1].i_addr; if (unlikely(dicp->di_magic != XFS_DINODE_MAGIC)) { xfs_buf_relse(bp); xfs_fs_cmn_err(CE_ALERT, mp, @@ -2461,7 +2450,7 @@ xlog_recover_do_inode_trans( } /* The core is in in-core format */ - xfs_dinode_to_disk(dip, (xfs_icdinode_t *)item->ri_buf[1].i_addr); + xfs_dinode_to_disk(dip, item->ri_buf[1].i_addr); /* the rest is in on-disk format */ if (item->ri_buf[1].i_len > sizeof(struct xfs_icdinode)) { @@ -2578,7 +2567,7 @@ xlog_recover_do_quotaoff_trans( return (0); } - qoff_f = (xfs_qoff_logformat_t *)item->ri_buf[0].i_addr; + qoff_f = item->ri_buf[0].i_addr; ASSERT(qoff_f); /* @@ -2622,9 +2611,8 @@ xlog_recover_do_dquot_trans( if (mp->m_qflags == 0) return (0); - recddq = (xfs_disk_dquot_t *)item->ri_buf[1].i_addr; - - if (item->ri_buf[1].i_addr == NULL) { + recddq = item->ri_buf[1].i_addr; + if (recddq == NULL) { cmn_err(CE_ALERT, "XFS: NULL dquot in %s.", __func__); return XFS_ERROR(EIO); @@ -2654,7 +2642,7 @@ xlog_recover_do_dquot_trans( * The other possibility, of course, is that the quota subsystem was * removed since the last mount - ENOSYS. */ - dq_f = (xfs_dq_logformat_t *)item->ri_buf[0].i_addr; + dq_f = item->ri_buf[0].i_addr; ASSERT(dq_f); if ((error = xfs_qm_dqcheck(recddq, dq_f->qlf_id, @@ -2721,7 +2709,7 @@ xlog_recover_do_efi_trans( return 0; } - efi_formatp = (xfs_efi_log_format_t *)item->ri_buf[0].i_addr; + efi_formatp = item->ri_buf[0].i_addr; mp = log->l_mp; efip = xfs_efi_init(mp, efi_formatp->efi_nextents); @@ -2767,7 +2755,7 @@ xlog_recover_do_efd_trans( return; } - efd_formatp = (xfs_efd_log_format_t *)item->ri_buf[0].i_addr; + efd_formatp = item->ri_buf[0].i_addr; ASSERT((item->ri_buf[0].i_len == (sizeof(xfs_efd_log_format_32_t) + ((efd_formatp->efd_nextents - 1) * sizeof(xfs_extent_32_t)))) || (item->ri_buf[0].i_len == (sizeof(xfs_efd_log_format_64_t) + diff --git a/fs/xfs/xfs_mount.c b/fs/xfs/xfs_mount.c index 69f62d8b2816..aeb9d72ebf6e 100644 --- a/fs/xfs/xfs_mount.c +++ b/fs/xfs/xfs_mount.c @@ -25,13 +25,10 @@ #include "xfs_sb.h" #include "xfs_ag.h" #include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_btree.h" diff --git a/fs/xfs/xfs_mount.h b/fs/xfs/xfs_mount.h index 5761087ee8ea..622da2179a57 100644 --- a/fs/xfs/xfs_mount.h +++ b/fs/xfs/xfs_mount.h @@ -66,65 +66,6 @@ struct xfs_nameops; struct xfs_ail; struct xfs_quotainfo; - -/* - * Prototypes and functions for the Data Migration subsystem. - */ - -typedef int (*xfs_send_data_t)(int, struct xfs_inode *, - xfs_off_t, size_t, int, int *); -typedef int (*xfs_send_mmap_t)(struct vm_area_struct *, uint); -typedef int (*xfs_send_destroy_t)(struct xfs_inode *, dm_right_t); -typedef int (*xfs_send_namesp_t)(dm_eventtype_t, struct xfs_mount *, - struct xfs_inode *, dm_right_t, - struct xfs_inode *, dm_right_t, - const unsigned char *, const unsigned char *, - mode_t, int, int); -typedef int (*xfs_send_mount_t)(struct xfs_mount *, dm_right_t, - char *, char *); -typedef void (*xfs_send_unmount_t)(struct xfs_mount *, struct xfs_inode *, - dm_right_t, mode_t, int, int); - -typedef struct xfs_dmops { - xfs_send_data_t xfs_send_data; - xfs_send_mmap_t xfs_send_mmap; - xfs_send_destroy_t xfs_send_destroy; - xfs_send_namesp_t xfs_send_namesp; - xfs_send_mount_t xfs_send_mount; - xfs_send_unmount_t xfs_send_unmount; -} xfs_dmops_t; - -#define XFS_DMAPI_UNMOUNT_FLAGS(mp) \ - (((mp)->m_dmevmask & (1 << DM_EVENT_UNMOUNT)) ? 0 : DM_FLAGS_UNWANTED) - -#define XFS_SEND_DATA(mp, ev,ip,off,len,fl,lock) \ - (*(mp)->m_dm_ops->xfs_send_data)(ev,ip,off,len,fl,lock) -#define XFS_SEND_MMAP(mp, vma,fl) \ - (*(mp)->m_dm_ops->xfs_send_mmap)(vma,fl) -#define XFS_SEND_DESTROY(mp, ip,right) \ - (*(mp)->m_dm_ops->xfs_send_destroy)(ip,right) -#define XFS_SEND_NAMESP(mp, ev,b1,r1,b2,r2,n1,n2,mode,rval,fl) \ - (*(mp)->m_dm_ops->xfs_send_namesp)(ev,NULL,b1,r1,b2,r2,n1,n2,mode,rval,fl) -#define XFS_SEND_MOUNT(mp,right,path,name) \ - (*(mp)->m_dm_ops->xfs_send_mount)(mp,right,path,name) -#define XFS_SEND_PREUNMOUNT(mp) \ -do { \ - if (mp->m_flags & XFS_MOUNT_DMAPI) { \ - (*(mp)->m_dm_ops->xfs_send_namesp)(DM_EVENT_PREUNMOUNT, mp, \ - (mp)->m_rootip, DM_RIGHT_NULL, \ - (mp)->m_rootip, DM_RIGHT_NULL, \ - NULL, NULL, 0, 0, XFS_DMAPI_UNMOUNT_FLAGS(mp)); \ - } \ -} while (0) -#define XFS_SEND_UNMOUNT(mp) \ -do { \ - if (mp->m_flags & XFS_MOUNT_DMAPI) { \ - (*(mp)->m_dm_ops->xfs_send_unmount)(mp, (mp)->m_rootip, \ - DM_RIGHT_NULL, 0, 0, XFS_DMAPI_UNMOUNT_FLAGS(mp)); \ - } \ -} while (0) - - #ifdef HAVE_PERCPU_SB /* @@ -241,8 +182,6 @@ typedef struct xfs_mount { uint m_chsize; /* size of next field */ struct xfs_chash *m_chash; /* fs private inode per-cluster * hash table */ - struct xfs_dmops *m_dm_ops; /* vector of DMI ops */ - struct xfs_qmops *m_qm_ops; /* vector of XQM ops */ atomic_t m_active_trans; /* number trans frozen */ #ifdef HAVE_PERCPU_SB xfs_icsb_cnts_t __percpu *m_sb_cnts; /* per-cpu superblock counters */ @@ -269,7 +208,6 @@ typedef struct xfs_mount { must be synchronous except for space allocations */ #define XFS_MOUNT_DELAYLOG (1ULL << 1) /* delayed logging is enabled */ -#define XFS_MOUNT_DMAPI (1ULL << 2) /* dmapi is enabled */ #define XFS_MOUNT_WAS_CLEAN (1ULL << 3) #define XFS_MOUNT_FS_SHUTDOWN (1ULL << 4) /* atomic stop of all filesystem operations, typically for @@ -282,8 +220,6 @@ typedef struct xfs_mount { #define XFS_MOUNT_GRPID (1ULL << 9) /* group-ID assigned from directory */ #define XFS_MOUNT_NORECOVERY (1ULL << 10) /* no recovery - dirty fs */ #define XFS_MOUNT_DFLT_IOSIZE (1ULL << 12) /* set default i/o size */ -#define XFS_MOUNT_OSYNCISOSYNC (1ULL << 13) /* o_sync is REALLY o_sync */ - /* osyncisdsync is now default*/ #define XFS_MOUNT_32BITINODES (1ULL << 14) /* do not create inodes above * 32 bits in size */ #define XFS_MOUNT_SMALL_INUMS (1ULL << 15) /* users wants 32bit inodes */ @@ -440,11 +376,6 @@ extern int xfs_sb_validate_fsb_count(struct xfs_sb *, __uint64_t); extern int xfs_dev_is_read_only(struct xfs_mount *, char *); -extern int xfs_dmops_get(struct xfs_mount *); -extern void xfs_dmops_put(struct xfs_mount *); - -extern struct xfs_dmops xfs_dmcore_xfs; - #endif /* __KERNEL__ */ extern void xfs_mod_sb(struct xfs_trans *, __int64_t); diff --git a/fs/xfs/xfs_rename.c b/fs/xfs/xfs_rename.c index fc1cda23b817..8fca957200df 100644 --- a/fs/xfs/xfs_rename.c +++ b/fs/xfs/xfs_rename.c @@ -24,12 +24,9 @@ #include "xfs_sb.h" #include "xfs_ag.h" #include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_da_btree.h" #include "xfs_bmap_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_inode_item.h" @@ -116,20 +113,7 @@ xfs_rename( int spaceres; int num_inodes; - xfs_itrace_entry(src_dp); - xfs_itrace_entry(target_dp); - - if (DM_EVENT_ENABLED(src_dp, DM_EVENT_RENAME) || - DM_EVENT_ENABLED(target_dp, DM_EVENT_RENAME)) { - error = XFS_SEND_NAMESP(mp, DM_EVENT_RENAME, - src_dp, DM_RIGHT_NULL, - target_dp, DM_RIGHT_NULL, - src_name->name, target_name->name, - 0, 0, 0); - if (error) - return error; - } - /* Return through std_return after this point. */ + trace_xfs_rename(src_dp, target_dp, src_name, target_name); new_parent = (src_dp != target_dp); src_is_directory = ((src_ip->i_d.di_mode & S_IFMT) == S_IFDIR); @@ -184,26 +168,14 @@ xfs_rename( /* * Join all the inodes to the transaction. From this point on, * we can rely on either trans_commit or trans_cancel to unlock - * them. Note that we need to add a vnode reference to the - * directories since trans_commit & trans_cancel will decrement - * them when they unlock the inodes. Also, we need to be careful - * not to add an inode to the transaction more than once. + * them. */ - IHOLD(src_dp); - xfs_trans_ijoin(tp, src_dp, XFS_ILOCK_EXCL); - - if (new_parent) { - IHOLD(target_dp); - xfs_trans_ijoin(tp, target_dp, XFS_ILOCK_EXCL); - } - - IHOLD(src_ip); - xfs_trans_ijoin(tp, src_ip, XFS_ILOCK_EXCL); - - if (target_ip) { - IHOLD(target_ip); - xfs_trans_ijoin(tp, target_ip, XFS_ILOCK_EXCL); - } + xfs_trans_ijoin_ref(tp, src_dp, XFS_ILOCK_EXCL); + if (new_parent) + xfs_trans_ijoin_ref(tp, target_dp, XFS_ILOCK_EXCL); + xfs_trans_ijoin_ref(tp, src_ip, XFS_ILOCK_EXCL); + if (target_ip) + xfs_trans_ijoin_ref(tp, target_ip, XFS_ILOCK_EXCL); /* * If we are using project inheritance, we only allow renames @@ -369,26 +341,13 @@ xfs_rename( * trans_commit will unlock src_ip, target_ip & decrement * the vnode references. */ - error = xfs_trans_commit(tp, XFS_TRANS_RELEASE_LOG_RES); - - /* Fall through to std_return with error = 0 or errno from - * xfs_trans_commit */ -std_return: - if (DM_EVENT_ENABLED(src_dp, DM_EVENT_POSTRENAME) || - DM_EVENT_ENABLED(target_dp, DM_EVENT_POSTRENAME)) { - (void) XFS_SEND_NAMESP (mp, DM_EVENT_POSTRENAME, - src_dp, DM_RIGHT_NULL, - target_dp, DM_RIGHT_NULL, - src_name->name, target_name->name, - 0, error, 0); - } - return error; + return xfs_trans_commit(tp, XFS_TRANS_RELEASE_LOG_RES); abort_return: cancel_flags |= XFS_TRANS_ABORT; - /* FALLTHROUGH */ error_return: xfs_bmap_cancel(&free_list); xfs_trans_cancel(tp, cancel_flags); - goto std_return; + std_return: + return error; } diff --git a/fs/xfs/xfs_rtalloc.c b/fs/xfs/xfs_rtalloc.c index a2d32ce335aa..891260fea11e 100644 --- a/fs/xfs/xfs_rtalloc.c +++ b/fs/xfs/xfs_rtalloc.c @@ -25,17 +25,10 @@ #include "xfs_sb.h" #include "xfs_ag.h" #include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" -#include "xfs_btree.h" -#include "xfs_ialloc.h" #include "xfs_alloc.h" #include "xfs_bmap.h" #include "xfs_rtalloc.h" @@ -129,7 +122,7 @@ xfs_growfs_rt_alloc( cancelflags |= XFS_TRANS_ABORT; error = xfs_bmapi(tp, ip, oblocks, nblocks - oblocks, XFS_BMAPI_WRITE | XFS_BMAPI_METADATA, &firstblock, - resblks, &map, &nmap, &flist, NULL); + resblks, &map, &nmap, &flist); if (!error && nmap < 1) error = XFS_ERROR(ENOSPC); if (error) diff --git a/fs/xfs/xfs_rw.c b/fs/xfs/xfs_rw.c index e336742a58a4..56861d5daaef 100644 --- a/fs/xfs/xfs_rw.c +++ b/fs/xfs/xfs_rw.c @@ -24,27 +24,12 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" -#include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" -#include "xfs_inode_item.h" -#include "xfs_itable.h" -#include "xfs_btree.h" -#include "xfs_alloc.h" -#include "xfs_ialloc.h" -#include "xfs_attr.h" -#include "xfs_bmap.h" #include "xfs_error.h" -#include "xfs_buf_item.h" #include "xfs_rw.h" -#include "xfs_trace.h" /* * Force a shutdown of the filesystem instantly while keeping diff --git a/fs/xfs/xfs_trans.c b/fs/xfs/xfs_trans.c index 28547dfce037..fdca7416c754 100644 --- a/fs/xfs/xfs_trans.c +++ b/fs/xfs/xfs_trans.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2000-2003,2005 Silicon Graphics, Inc. + * Copyright (C) 2010 Red Hat, Inc. * All Rights Reserved. * * This program is free software; you can redistribute it and/or @@ -24,16 +25,12 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_error.h" #include "xfs_da_btree.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_btree.h" @@ -47,6 +44,7 @@ #include "xfs_trace.h" kmem_zone_t *xfs_trans_zone; +kmem_zone_t *xfs_log_item_desc_zone; /* @@ -597,8 +595,7 @@ _xfs_trans_alloc( tp->t_magic = XFS_TRANS_MAGIC; tp->t_type = type; tp->t_mountp = mp; - tp->t_items_free = XFS_LIC_NUM_SLOTS; - xfs_lic_init(&(tp->t_items)); + INIT_LIST_HEAD(&tp->t_items); INIT_LIST_HEAD(&tp->t_busy); return tp; } @@ -643,8 +640,7 @@ xfs_trans_dup( ntp->t_magic = XFS_TRANS_MAGIC; ntp->t_type = tp->t_type; ntp->t_mountp = tp->t_mountp; - ntp->t_items_free = XFS_LIC_NUM_SLOTS; - xfs_lic_init(&(ntp->t_items)); + INIT_LIST_HEAD(&ntp->t_items); INIT_LIST_HEAD(&ntp->t_busy); ASSERT(tp->t_flags & XFS_TRANS_PERM_LOG_RES); @@ -1124,6 +1120,108 @@ xfs_trans_unreserve_and_mod_sb( } /* + * Add the given log item to the transaction's list of log items. + * + * The log item will now point to its new descriptor with its li_desc field. + */ +void +xfs_trans_add_item( + struct xfs_trans *tp, + struct xfs_log_item *lip) +{ + struct xfs_log_item_desc *lidp; + + ASSERT(lip->li_mountp = tp->t_mountp); + ASSERT(lip->li_ailp = tp->t_mountp->m_ail); + + lidp = kmem_zone_zalloc(xfs_log_item_desc_zone, KM_SLEEP | KM_NOFS); + + lidp->lid_item = lip; + lidp->lid_flags = 0; + lidp->lid_size = 0; + list_add_tail(&lidp->lid_trans, &tp->t_items); + + lip->li_desc = lidp; +} + +STATIC void +xfs_trans_free_item_desc( + struct xfs_log_item_desc *lidp) +{ + list_del_init(&lidp->lid_trans); + kmem_zone_free(xfs_log_item_desc_zone, lidp); +} + +/* + * Unlink and free the given descriptor. + */ +void +xfs_trans_del_item( + struct xfs_log_item *lip) +{ + xfs_trans_free_item_desc(lip->li_desc); + lip->li_desc = NULL; +} + +/* + * Unlock all of the items of a transaction and free all the descriptors + * of that transaction. + */ +STATIC void +xfs_trans_free_items( + struct xfs_trans *tp, + xfs_lsn_t commit_lsn, + int flags) +{ + struct xfs_log_item_desc *lidp, *next; + + list_for_each_entry_safe(lidp, next, &tp->t_items, lid_trans) { + struct xfs_log_item *lip = lidp->lid_item; + + lip->li_desc = NULL; + + if (commit_lsn != NULLCOMMITLSN) + IOP_COMMITTING(lip, commit_lsn); + if (flags & XFS_TRANS_ABORT) + lip->li_flags |= XFS_LI_ABORTED; + IOP_UNLOCK(lip); + + xfs_trans_free_item_desc(lidp); + } +} + +/* + * Unlock the items associated with a transaction. + * + * Items which were not logged should be freed. Those which were logged must + * still be tracked so they can be unpinned when the transaction commits. + */ +STATIC void +xfs_trans_unlock_items( + struct xfs_trans *tp, + xfs_lsn_t commit_lsn) +{ + struct xfs_log_item_desc *lidp, *next; + + list_for_each_entry_safe(lidp, next, &tp->t_items, lid_trans) { + struct xfs_log_item *lip = lidp->lid_item; + + lip->li_desc = NULL; + + if (commit_lsn != NULLCOMMITLSN) + IOP_COMMITTING(lip, commit_lsn); + IOP_UNLOCK(lip); + + /* + * Free the descriptor if the item is not dirty + * within this transaction. + */ + if (!(lidp->lid_flags & XFS_LID_DIRTY)) + xfs_trans_free_item_desc(lidp); + } +} + +/* * Total up the number of log iovecs needed to commit this * transaction. The transaction itself needs one for the * transaction header. Ask each dirty item in turn how many @@ -1134,30 +1232,27 @@ xfs_trans_count_vecs( struct xfs_trans *tp) { int nvecs; - xfs_log_item_desc_t *lidp; + struct xfs_log_item_desc *lidp; nvecs = 1; - lidp = xfs_trans_first_item(tp); - ASSERT(lidp != NULL); /* In the non-debug case we need to start bailing out if we * didn't find a log_item here, return zero and let trans_commit * deal with it. */ - if (lidp == NULL) + if (list_empty(&tp->t_items)) { + ASSERT(0); return 0; + } - while (lidp != NULL) { + list_for_each_entry(lidp, &tp->t_items, lid_trans) { /* * Skip items which aren't dirty in this transaction. */ - if (!(lidp->lid_flags & XFS_LID_DIRTY)) { - lidp = xfs_trans_next_item(tp, lidp); + if (!(lidp->lid_flags & XFS_LID_DIRTY)) continue; - } lidp->lid_size = IOP_SIZE(lidp->lid_item); nvecs += lidp->lid_size; - lidp = xfs_trans_next_item(tp, lidp); } return nvecs; @@ -1177,7 +1272,7 @@ xfs_trans_fill_vecs( struct xfs_trans *tp, struct xfs_log_iovec *log_vector) { - xfs_log_item_desc_t *lidp; + struct xfs_log_item_desc *lidp; struct xfs_log_iovec *vecp; uint nitems; @@ -1188,14 +1283,11 @@ xfs_trans_fill_vecs( vecp = log_vector + 1; nitems = 0; - lidp = xfs_trans_first_item(tp); - ASSERT(lidp); - while (lidp) { + ASSERT(!list_empty(&tp->t_items)); + list_for_each_entry(lidp, &tp->t_items, lid_trans) { /* Skip items which aren't dirty in this transaction. */ - if (!(lidp->lid_flags & XFS_LID_DIRTY)) { - lidp = xfs_trans_next_item(tp, lidp); + if (!(lidp->lid_flags & XFS_LID_DIRTY)) continue; - } /* * The item may be marked dirty but not log anything. This can @@ -1206,7 +1298,6 @@ xfs_trans_fill_vecs( IOP_FORMAT(lidp->lid_item, vecp); vecp += lidp->lid_size; IOP_PIN(lidp->lid_item); - lidp = xfs_trans_next_item(tp, lidp); } /* @@ -1284,7 +1375,7 @@ xfs_trans_item_committed( * log item flags, if anyone else stales the buffer we do not want to * pay any attention to it. */ - IOP_UNPIN(lip); + IOP_UNPIN(lip, 0); } /* @@ -1301,24 +1392,15 @@ xfs_trans_committed( struct xfs_trans *tp, int abortflag) { - xfs_log_item_desc_t *lidp; - xfs_log_item_chunk_t *licp; - xfs_log_item_chunk_t *next_licp; + struct xfs_log_item_desc *lidp, *next; /* Call the transaction's completion callback if there is one. */ if (tp->t_callback != NULL) tp->t_callback(tp, tp->t_callarg); - for (lidp = xfs_trans_first_item(tp); - lidp != NULL; - lidp = xfs_trans_next_item(tp, lidp)) { + list_for_each_entry_safe(lidp, next, &tp->t_items, lid_trans) { xfs_trans_item_committed(lidp->lid_item, tp->t_lsn, abortflag); - } - - /* free the item chunks, ignoring the embedded chunk */ - for (licp = tp->t_items.lic_next; licp != NULL; licp = next_licp) { - next_licp = licp->lic_next; - kmem_free(licp); + xfs_trans_free_item_desc(lidp); } xfs_trans_free(tp); @@ -1333,16 +1415,14 @@ xfs_trans_uncommit( struct xfs_trans *tp, uint flags) { - xfs_log_item_desc_t *lidp; + struct xfs_log_item_desc *lidp; - for (lidp = xfs_trans_first_item(tp); - lidp != NULL; - lidp = xfs_trans_next_item(tp, lidp)) { + list_for_each_entry(lidp, &tp->t_items, lid_trans) { /* * Unpin all but those that aren't dirty. */ if (lidp->lid_flags & XFS_LID_DIRTY) - IOP_UNPIN_REMOVE(lidp->lid_item, tp); + IOP_UNPIN(lidp->lid_item, 1); } xfs_trans_unreserve_and_mod_sb(tp); @@ -1508,33 +1588,28 @@ STATIC struct xfs_log_vec * xfs_trans_alloc_log_vecs( xfs_trans_t *tp) { - xfs_log_item_desc_t *lidp; + struct xfs_log_item_desc *lidp; struct xfs_log_vec *lv = NULL; struct xfs_log_vec *ret_lv = NULL; - lidp = xfs_trans_first_item(tp); /* Bail out if we didn't find a log item. */ - if (!lidp) { + if (list_empty(&tp->t_items)) { ASSERT(0); return NULL; } - while (lidp != NULL) { + list_for_each_entry(lidp, &tp->t_items, lid_trans) { struct xfs_log_vec *new_lv; /* Skip items which aren't dirty in this transaction. */ - if (!(lidp->lid_flags & XFS_LID_DIRTY)) { - lidp = xfs_trans_next_item(tp, lidp); + if (!(lidp->lid_flags & XFS_LID_DIRTY)) continue; - } /* Skip items that do not have any vectors for writing */ lidp->lid_size = IOP_SIZE(lidp->lid_item); - if (!lidp->lid_size) { - lidp = xfs_trans_next_item(tp, lidp); + if (!lidp->lid_size) continue; - } new_lv = kmem_zalloc(sizeof(*new_lv) + lidp->lid_size * sizeof(struct xfs_log_iovec), @@ -1549,7 +1624,6 @@ xfs_trans_alloc_log_vecs( else lv->lv_next = new_lv; lv = new_lv; - lidp = xfs_trans_next_item(tp, lidp); } return ret_lv; @@ -1708,12 +1782,6 @@ xfs_trans_cancel( int flags) { int log_flags; -#ifdef DEBUG - xfs_log_item_chunk_t *licp; - xfs_log_item_desc_t *lidp; - xfs_log_item_t *lip; - int i; -#endif xfs_mount_t *mp = tp->t_mountp; /* @@ -1732,21 +1800,11 @@ xfs_trans_cancel( xfs_force_shutdown(mp, SHUTDOWN_CORRUPT_INCORE); } #ifdef DEBUG - if (!(flags & XFS_TRANS_ABORT)) { - licp = &(tp->t_items); - while (licp != NULL) { - lidp = licp->lic_descs; - for (i = 0; i < licp->lic_unused; i++, lidp++) { - if (xfs_lic_isfree(licp, i)) { - continue; - } - - lip = lidp->lid_item; - if (!XFS_FORCED_SHUTDOWN(mp)) - ASSERT(!(lip->li_type == XFS_LI_EFD)); - } - licp = licp->lic_next; - } + if (!(flags & XFS_TRANS_ABORT) && !XFS_FORCED_SHUTDOWN(mp)) { + struct xfs_log_item_desc *lidp; + + list_for_each_entry(lidp, &tp->t_items, lid_trans) + ASSERT(!(lidp->lid_item->li_type == XFS_LI_EFD)); } #endif xfs_trans_unreserve_and_mod_sb(tp); @@ -1834,7 +1892,6 @@ xfs_trans_roll( if (error) return error; - xfs_trans_ijoin(trans, dp, XFS_ILOCK_EXCL); - xfs_trans_ihold(trans, dp); + xfs_trans_ijoin(trans, dp); return 0; } diff --git a/fs/xfs/xfs_trans.h b/fs/xfs/xfs_trans.h index e639e8e9a2a9..c13c0f97b494 100644 --- a/fs/xfs/xfs_trans.h +++ b/fs/xfs/xfs_trans.h @@ -161,105 +161,14 @@ typedef struct xfs_trans_header { * the amount of space needed to log the item it describes * once we get to commit processing (see xfs_trans_commit()). */ -typedef struct xfs_log_item_desc { +struct xfs_log_item_desc { struct xfs_log_item *lid_item; - ushort lid_size; - unsigned char lid_flags; - unsigned char lid_index; -} xfs_log_item_desc_t; + ushort lid_size; + unsigned char lid_flags; + struct list_head lid_trans; +}; #define XFS_LID_DIRTY 0x1 -#define XFS_LID_PINNED 0x2 - -/* - * This structure is used to maintain a chunk list of log_item_desc - * structures. The free field is a bitmask indicating which descriptors - * in this chunk's array are free. The unused field is the first value - * not used since this chunk was allocated. - */ -#define XFS_LIC_NUM_SLOTS 15 -typedef struct xfs_log_item_chunk { - struct xfs_log_item_chunk *lic_next; - ushort lic_free; - ushort lic_unused; - xfs_log_item_desc_t lic_descs[XFS_LIC_NUM_SLOTS]; -} xfs_log_item_chunk_t; - -#define XFS_LIC_MAX_SLOT (XFS_LIC_NUM_SLOTS - 1) -#define XFS_LIC_FREEMASK ((1 << XFS_LIC_NUM_SLOTS) - 1) - - -/* - * Initialize the given chunk. Set the chunk's free descriptor mask - * to indicate that all descriptors are free. The caller gets to set - * lic_unused to the right value (0 matches all free). The - * lic_descs.lid_index values are set up as each desc is allocated. - */ -static inline void xfs_lic_init(xfs_log_item_chunk_t *cp) -{ - cp->lic_free = XFS_LIC_FREEMASK; -} - -static inline void xfs_lic_init_slot(xfs_log_item_chunk_t *cp, int slot) -{ - cp->lic_descs[slot].lid_index = (unsigned char)(slot); -} - -static inline int xfs_lic_vacancy(xfs_log_item_chunk_t *cp) -{ - return cp->lic_free & XFS_LIC_FREEMASK; -} - -static inline void xfs_lic_all_free(xfs_log_item_chunk_t *cp) -{ - cp->lic_free = XFS_LIC_FREEMASK; -} - -static inline int xfs_lic_are_all_free(xfs_log_item_chunk_t *cp) -{ - return ((cp->lic_free & XFS_LIC_FREEMASK) == XFS_LIC_FREEMASK); -} - -static inline int xfs_lic_isfree(xfs_log_item_chunk_t *cp, int slot) -{ - return (cp->lic_free & (1 << slot)); -} - -static inline void xfs_lic_claim(xfs_log_item_chunk_t *cp, int slot) -{ - cp->lic_free &= ~(1 << slot); -} - -static inline void xfs_lic_relse(xfs_log_item_chunk_t *cp, int slot) -{ - cp->lic_free |= 1 << slot; -} - -static inline xfs_log_item_desc_t * -xfs_lic_slot(xfs_log_item_chunk_t *cp, int slot) -{ - return &(cp->lic_descs[slot]); -} - -static inline int xfs_lic_desc_to_slot(xfs_log_item_desc_t *dp) -{ - return (uint)dp->lid_index; -} - -/* - * Calculate the address of a chunk given a descriptor pointer: - * dp - dp->lid_index give the address of the start of the lic_descs array. - * From this we subtract the offset of the lic_descs field in a chunk. - * All of this yields the address of the chunk, which is - * cast to a chunk pointer. - */ -static inline xfs_log_item_chunk_t * -xfs_lic_desc_to_chunk(xfs_log_item_desc_t *dp) -{ - return (xfs_log_item_chunk_t*) \ - (((xfs_caddr_t)((dp) - (dp)->lid_index)) - \ - (xfs_caddr_t)(((xfs_log_item_chunk_t*)0)->lic_descs)); -} #define XFS_TRANS_MAGIC 0x5452414E /* 'TRAN' */ /* @@ -275,8 +184,6 @@ xfs_lic_desc_to_chunk(xfs_log_item_desc_t *dp) /* * Values for call flags parameter. */ -#define XFS_TRANS_NOSLEEP 0x1 -#define XFS_TRANS_WAIT 0x2 #define XFS_TRANS_RELEASE_LOG_RES 0x4 #define XFS_TRANS_ABORT 0x8 @@ -438,8 +345,7 @@ typedef struct xfs_item_ops { uint (*iop_size)(xfs_log_item_t *); void (*iop_format)(xfs_log_item_t *, struct xfs_log_iovec *); void (*iop_pin)(xfs_log_item_t *); - void (*iop_unpin)(xfs_log_item_t *); - void (*iop_unpin_remove)(xfs_log_item_t *, struct xfs_trans *); + void (*iop_unpin)(xfs_log_item_t *, int remove); uint (*iop_trylock)(xfs_log_item_t *); void (*iop_unlock)(xfs_log_item_t *); xfs_lsn_t (*iop_committed)(xfs_log_item_t *, xfs_lsn_t); @@ -451,8 +357,7 @@ typedef struct xfs_item_ops { #define IOP_SIZE(ip) (*(ip)->li_ops->iop_size)(ip) #define IOP_FORMAT(ip,vp) (*(ip)->li_ops->iop_format)(ip, vp) #define IOP_PIN(ip) (*(ip)->li_ops->iop_pin)(ip) -#define IOP_UNPIN(ip) (*(ip)->li_ops->iop_unpin)(ip) -#define IOP_UNPIN_REMOVE(ip,tp) (*(ip)->li_ops->iop_unpin_remove)(ip, tp) +#define IOP_UNPIN(ip, remove) (*(ip)->li_ops->iop_unpin)(ip, remove) #define IOP_TRYLOCK(ip) (*(ip)->li_ops->iop_trylock)(ip) #define IOP_UNLOCK(ip) (*(ip)->li_ops->iop_unlock)(ip) #define IOP_COMMITTED(ip, lsn) (*(ip)->li_ops->iop_committed)(ip, lsn) @@ -516,8 +421,7 @@ typedef struct xfs_trans { int64_t t_rblocks_delta;/* superblock rblocks change */ int64_t t_rextents_delta;/* superblocks rextents chg */ int64_t t_rextslog_delta;/* superblocks rextslog chg */ - unsigned int t_items_free; /* log item descs free */ - xfs_log_item_chunk_t t_items; /* first log item desc chunk */ + struct list_head t_items; /* log item descriptors */ xfs_trans_header_t t_header; /* header for in-log trans */ struct list_head t_busy; /* list of busy extents */ unsigned long t_pflags; /* saved process flags state */ @@ -569,8 +473,8 @@ void xfs_trans_dquot_buf(xfs_trans_t *, struct xfs_buf *, uint); void xfs_trans_inode_alloc_buf(xfs_trans_t *, struct xfs_buf *); int xfs_trans_iget(struct xfs_mount *, xfs_trans_t *, xfs_ino_t , uint, uint, struct xfs_inode **); -void xfs_trans_ijoin(xfs_trans_t *, struct xfs_inode *, uint); -void xfs_trans_ihold(xfs_trans_t *, struct xfs_inode *); +void xfs_trans_ijoin_ref(struct xfs_trans *, struct xfs_inode *, uint); +void xfs_trans_ijoin(struct xfs_trans *, struct xfs_inode *); void xfs_trans_log_buf(xfs_trans_t *, struct xfs_buf *, uint, uint); void xfs_trans_log_inode(xfs_trans_t *, struct xfs_inode *, uint); struct xfs_efi_log_item *xfs_trans_get_efi(xfs_trans_t *, uint); @@ -595,6 +499,7 @@ int xfs_trans_ail_init(struct xfs_mount *); void xfs_trans_ail_destroy(struct xfs_mount *); extern kmem_zone_t *xfs_trans_zone; +extern kmem_zone_t *xfs_log_item_desc_zone; #endif /* __KERNEL__ */ diff --git a/fs/xfs/xfs_trans_ail.c b/fs/xfs/xfs_trans_ail.c index e799824f7245..dc9069568ff7 100644 --- a/fs/xfs/xfs_trans_ail.c +++ b/fs/xfs/xfs_trans_ail.c @@ -24,7 +24,6 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_trans_priv.h" #include "xfs_error.h" diff --git a/fs/xfs/xfs_trans_buf.c b/fs/xfs/xfs_trans_buf.c index 63d81a22f4fd..90af025e6839 100644 --- a/fs/xfs/xfs_trans_buf.c +++ b/fs/xfs/xfs_trans_buf.c @@ -24,14 +24,10 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_buf_item.h" @@ -51,36 +47,17 @@ xfs_trans_buf_item_match( xfs_daddr_t blkno, int len) { - xfs_log_item_chunk_t *licp; - xfs_log_item_desc_t *lidp; - xfs_buf_log_item_t *blip; - int i; + struct xfs_log_item_desc *lidp; + struct xfs_buf_log_item *blip; len = BBTOB(len); - for (licp = &tp->t_items; licp != NULL; licp = licp->lic_next) { - if (xfs_lic_are_all_free(licp)) { - ASSERT(licp == &tp->t_items); - ASSERT(licp->lic_next == NULL); - return NULL; - } - - for (i = 0; i < licp->lic_unused; i++) { - /* - * Skip unoccupied slots. - */ - if (xfs_lic_isfree(licp, i)) - continue; - - lidp = xfs_lic_slot(licp, i); - blip = (xfs_buf_log_item_t *)lidp->lid_item; - if (blip->bli_item.li_type != XFS_LI_BUF) - continue; - - if (XFS_BUF_TARGET(blip->bli_buf) == target && - XFS_BUF_ADDR(blip->bli_buf) == blkno && - XFS_BUF_COUNT(blip->bli_buf) == len) - return blip->bli_buf; - } + list_for_each_entry(lidp, &tp->t_items, lid_trans) { + blip = (struct xfs_buf_log_item *)lidp->lid_item; + if (blip->bli_item.li_type == XFS_LI_BUF && + XFS_BUF_TARGET(blip->bli_buf) == target && + XFS_BUF_ADDR(blip->bli_buf) == blkno && + XFS_BUF_COUNT(blip->bli_buf) == len) + return blip->bli_buf; } return NULL; @@ -127,7 +104,7 @@ _xfs_trans_bjoin( /* * Get a log_item_desc to point at the new item. */ - (void) xfs_trans_add_item(tp, (xfs_log_item_t *)bip); + xfs_trans_add_item(tp, &bip->bli_item); /* * Initialize b_fsprivate2 so we can find it with incore_match() @@ -483,7 +460,6 @@ xfs_trans_brelse(xfs_trans_t *tp, { xfs_buf_log_item_t *bip; xfs_log_item_t *lip; - xfs_log_item_desc_t *lidp; /* * Default to a normal brelse() call if the tp is NULL. @@ -514,13 +490,6 @@ xfs_trans_brelse(xfs_trans_t *tp, ASSERT(!(bip->bli_format.blf_flags & XFS_BLF_CANCEL)); ASSERT(atomic_read(&bip->bli_refcount) > 0); - /* - * Find the item descriptor pointing to this buffer's - * log item. It must be there. - */ - lidp = xfs_trans_find_item(tp, (xfs_log_item_t*)bip); - ASSERT(lidp != NULL); - trace_xfs_trans_brelse(bip); /* @@ -536,7 +505,7 @@ xfs_trans_brelse(xfs_trans_t *tp, * If the buffer is dirty within this transaction, we can't * release it until we commit. */ - if (lidp->lid_flags & XFS_LID_DIRTY) + if (bip->bli_item.li_desc->lid_flags & XFS_LID_DIRTY) return; /* @@ -553,7 +522,7 @@ xfs_trans_brelse(xfs_trans_t *tp, /* * Free up the log item descriptor tracking the released item. */ - xfs_trans_free_item(tp, lidp); + xfs_trans_del_item(&bip->bli_item); /* * Clear the hold flag in the buf log item if it is set. @@ -665,7 +634,6 @@ xfs_trans_log_buf(xfs_trans_t *tp, uint last) { xfs_buf_log_item_t *bip; - xfs_log_item_desc_t *lidp; ASSERT(XFS_BUF_ISBUSY(bp)); ASSERT(XFS_BUF_FSPRIVATE2(bp, xfs_trans_t *) == tp); @@ -690,7 +658,7 @@ xfs_trans_log_buf(xfs_trans_t *tp, bip = XFS_BUF_FSPRIVATE(bp, xfs_buf_log_item_t *); ASSERT(atomic_read(&bip->bli_refcount) > 0); XFS_BUF_SET_IODONE_FUNC(bp, xfs_buf_iodone_callbacks); - bip->bli_item.li_cb = (void(*)(xfs_buf_t*,xfs_log_item_t*))xfs_buf_iodone; + bip->bli_item.li_cb = xfs_buf_iodone; trace_xfs_trans_log_buf(bip); @@ -707,11 +675,8 @@ xfs_trans_log_buf(xfs_trans_t *tp, bip->bli_format.blf_flags &= ~XFS_BLF_CANCEL; } - lidp = xfs_trans_find_item(tp, (xfs_log_item_t*)bip); - ASSERT(lidp != NULL); - tp->t_flags |= XFS_TRANS_DIRTY; - lidp->lid_flags |= XFS_LID_DIRTY; + bip->bli_item.li_desc->lid_flags |= XFS_LID_DIRTY; bip->bli_flags |= XFS_BLI_LOGGED; xfs_buf_item_log(bip, first, last); } @@ -740,7 +705,6 @@ xfs_trans_binval( xfs_trans_t *tp, xfs_buf_t *bp) { - xfs_log_item_desc_t *lidp; xfs_buf_log_item_t *bip; ASSERT(XFS_BUF_ISBUSY(bp)); @@ -748,8 +712,6 @@ xfs_trans_binval( ASSERT(XFS_BUF_FSPRIVATE(bp, void *) != NULL); bip = XFS_BUF_FSPRIVATE(bp, xfs_buf_log_item_t *); - lidp = xfs_trans_find_item(tp, (xfs_log_item_t*)bip); - ASSERT(lidp != NULL); ASSERT(atomic_read(&bip->bli_refcount) > 0); trace_xfs_trans_binval(bip); @@ -764,7 +726,7 @@ xfs_trans_binval( ASSERT(!(bip->bli_flags & (XFS_BLI_LOGGED | XFS_BLI_DIRTY))); ASSERT(!(bip->bli_format.blf_flags & XFS_BLF_INODE_BUF)); ASSERT(bip->bli_format.blf_flags & XFS_BLF_CANCEL); - ASSERT(lidp->lid_flags & XFS_LID_DIRTY); + ASSERT(bip->bli_item.li_desc->lid_flags & XFS_LID_DIRTY); ASSERT(tp->t_flags & XFS_TRANS_DIRTY); return; } @@ -797,7 +759,7 @@ xfs_trans_binval( bip->bli_format.blf_flags |= XFS_BLF_CANCEL; memset((char *)(bip->bli_format.blf_data_map), 0, (bip->bli_format.blf_map_size * sizeof(uint))); - lidp->lid_flags |= XFS_LID_DIRTY; + bip->bli_item.li_desc->lid_flags |= XFS_LID_DIRTY; tp->t_flags |= XFS_TRANS_DIRTY; } @@ -853,12 +815,9 @@ xfs_trans_stale_inode_buf( ASSERT(atomic_read(&bip->bli_refcount) > 0); bip->bli_flags |= XFS_BLI_STALE_INODE; - bip->bli_item.li_cb = (void(*)(xfs_buf_t*,xfs_log_item_t*)) - xfs_buf_iodone; + bip->bli_item.li_cb = xfs_buf_iodone; } - - /* * Mark the buffer as being one which contains newly allocated * inodes. We need to make sure that even if this buffer is diff --git a/fs/xfs/xfs_trans_extfree.c b/fs/xfs/xfs_trans_extfree.c index 27cce2a9c7e9..f783d5e9fa70 100644 --- a/fs/xfs/xfs_trans_extfree.c +++ b/fs/xfs/xfs_trans_extfree.c @@ -23,7 +23,6 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_trans_priv.h" #include "xfs_extfree_item.h" @@ -49,9 +48,8 @@ xfs_trans_get_efi(xfs_trans_t *tp, /* * Get a log_item_desc to point at the new item. */ - (void) xfs_trans_add_item(tp, (xfs_log_item_t*)efip); - - return (efip); + xfs_trans_add_item(tp, &efip->efi_item); + return efip; } /* @@ -65,15 +63,11 @@ xfs_trans_log_efi_extent(xfs_trans_t *tp, xfs_fsblock_t start_block, xfs_extlen_t ext_len) { - xfs_log_item_desc_t *lidp; uint next_extent; xfs_extent_t *extp; - lidp = xfs_trans_find_item(tp, (xfs_log_item_t*)efip); - ASSERT(lidp != NULL); - tp->t_flags |= XFS_TRANS_DIRTY; - lidp->lid_flags |= XFS_LID_DIRTY; + efip->efi_item.li_desc->lid_flags |= XFS_LID_DIRTY; next_extent = efip->efi_next_extent; ASSERT(next_extent < efip->efi_format.efi_nextents); @@ -106,9 +100,8 @@ xfs_trans_get_efd(xfs_trans_t *tp, /* * Get a log_item_desc to point at the new item. */ - (void) xfs_trans_add_item(tp, (xfs_log_item_t*)efdp); - - return (efdp); + xfs_trans_add_item(tp, &efdp->efd_item); + return efdp; } /* @@ -122,15 +115,11 @@ xfs_trans_log_efd_extent(xfs_trans_t *tp, xfs_fsblock_t start_block, xfs_extlen_t ext_len) { - xfs_log_item_desc_t *lidp; uint next_extent; xfs_extent_t *extp; - lidp = xfs_trans_find_item(tp, (xfs_log_item_t*)efdp); - ASSERT(lidp != NULL); - tp->t_flags |= XFS_TRANS_DIRTY; - lidp->lid_flags |= XFS_LID_DIRTY; + efdp->efd_item.li_desc->lid_flags |= XFS_LID_DIRTY; next_extent = efdp->efd_next_extent; ASSERT(next_extent < efdp->efd_format.efd_nextents); diff --git a/fs/xfs/xfs_trans_inode.c b/fs/xfs/xfs_trans_inode.c index 2559dfec946b..cdc53a1050c5 100644 --- a/fs/xfs/xfs_trans_inode.c +++ b/fs/xfs/xfs_trans_inode.c @@ -24,20 +24,16 @@ #include "xfs_trans.h" #include "xfs_sb.h" #include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" #include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_btree.h" -#include "xfs_ialloc.h" #include "xfs_trans_priv.h" #include "xfs_inode_item.h" +#include "xfs_trace.h" #ifdef XFS_TRANS_DEBUG STATIC void @@ -47,7 +43,6 @@ xfs_trans_inode_broot_debug( #define xfs_trans_inode_broot_debug(ip) #endif - /* * Get an inode and join it to the transaction. */ @@ -63,77 +58,65 @@ xfs_trans_iget( int error; error = xfs_iget(mp, tp, ino, flags, lock_flags, ipp); - if (!error && tp) - xfs_trans_ijoin(tp, *ipp, lock_flags); + if (!error && tp) { + xfs_trans_ijoin(tp, *ipp); + (*ipp)->i_itemp->ili_lock_flags = lock_flags; + } return error; } /* - * Add the locked inode to the transaction. - * The inode must be locked, and it cannot be associated with any - * transaction. The caller must specify the locks already held - * on the inode. + * Add a locked inode to the transaction. + * + * The inode must be locked, and it cannot be associated with any transaction. */ void xfs_trans_ijoin( - xfs_trans_t *tp, - xfs_inode_t *ip, - uint lock_flags) + struct xfs_trans *tp, + struct xfs_inode *ip) { xfs_inode_log_item_t *iip; ASSERT(ip->i_transp == NULL); ASSERT(xfs_isilocked(ip, XFS_ILOCK_EXCL)); - ASSERT(lock_flags & XFS_ILOCK_EXCL); if (ip->i_itemp == NULL) xfs_inode_item_init(ip, ip->i_mount); iip = ip->i_itemp; - ASSERT(iip->ili_flags == 0); + ASSERT(iip->ili_lock_flags == 0); /* * Get a log_item_desc to point at the new item. */ - (void) xfs_trans_add_item(tp, (xfs_log_item_t*)(iip)); + xfs_trans_add_item(tp, &iip->ili_item); xfs_trans_inode_broot_debug(ip); /* - * If the IO lock is already held, mark that in the inode log item. - */ - if (lock_flags & XFS_IOLOCK_EXCL) { - iip->ili_flags |= XFS_ILI_IOLOCKED_EXCL; - } else if (lock_flags & XFS_IOLOCK_SHARED) { - iip->ili_flags |= XFS_ILI_IOLOCKED_SHARED; - } - - /* * Initialize i_transp so we can find it with xfs_inode_incore() * in xfs_trans_iget() above. */ ip->i_transp = tp; } - - /* - * Mark the inode as not needing to be unlocked when the inode item's - * IOP_UNLOCK() routine is called. The inode must already be locked - * and associated with the given transaction. + * Add a locked inode to the transaction. + * + * + * Grabs a reference to the inode which will be dropped when the transaction + * is commited. The inode will also be unlocked at that point. The inode + * must be locked, and it cannot be associated with any transaction. */ -/*ARGSUSED*/ void -xfs_trans_ihold( - xfs_trans_t *tp, - xfs_inode_t *ip) +xfs_trans_ijoin_ref( + struct xfs_trans *tp, + struct xfs_inode *ip, + uint lock_flags) { - ASSERT(ip->i_transp == tp); - ASSERT(ip->i_itemp != NULL); - ASSERT(xfs_isilocked(ip, XFS_ILOCK_EXCL)); - - ip->i_itemp->ili_flags |= XFS_ILI_HOLD; + xfs_trans_ijoin(tp, ip); + IHOLD(ip); + ip->i_itemp->ili_lock_flags = lock_flags; } - /* * This is called to mark the fields indicated in fieldmask as needing * to be logged when the transaction is committed. The inode must @@ -149,17 +132,12 @@ xfs_trans_log_inode( xfs_inode_t *ip, uint flags) { - xfs_log_item_desc_t *lidp; - ASSERT(ip->i_transp == tp); ASSERT(ip->i_itemp != NULL); ASSERT(xfs_isilocked(ip, XFS_ILOCK_EXCL)); - lidp = xfs_trans_find_item(tp, (xfs_log_item_t*)(ip->i_itemp)); - ASSERT(lidp != NULL); - tp->t_flags |= XFS_TRANS_DIRTY; - lidp->lid_flags |= XFS_LID_DIRTY; + ip->i_itemp->ili_item.li_desc->lid_flags |= XFS_LID_DIRTY; /* * Always OR in the bits from the ili_last_fields field. diff --git a/fs/xfs/xfs_trans_item.c b/fs/xfs/xfs_trans_item.c deleted file mode 100644 index f11d37d06dcc..000000000000 --- a/fs/xfs/xfs_trans_item.c +++ /dev/null @@ -1,441 +0,0 @@ -/* - * Copyright (c) 2000-2002,2005 Silicon Graphics, Inc. - * All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it would be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include "xfs.h" -#include "xfs_fs.h" -#include "xfs_types.h" -#include "xfs_log.h" -#include "xfs_inum.h" -#include "xfs_trans.h" -#include "xfs_trans_priv.h" -/* XXX: from here down needed until struct xfs_trans has its own ailp */ -#include "xfs_bit.h" -#include "xfs_buf_item.h" -#include "xfs_sb.h" -#include "xfs_ag.h" -#include "xfs_dir2.h" -#include "xfs_dmapi.h" -#include "xfs_mount.h" - -STATIC int xfs_trans_unlock_chunk(xfs_log_item_chunk_t *, - int, int, xfs_lsn_t); - -/* - * This is called to add the given log item to the transaction's - * list of log items. It must find a free log item descriptor - * or allocate a new one and add the item to that descriptor. - * The function returns a pointer to item descriptor used to point - * to the new item. The log item will now point to its new descriptor - * with its li_desc field. - */ -xfs_log_item_desc_t * -xfs_trans_add_item(xfs_trans_t *tp, xfs_log_item_t *lip) -{ - xfs_log_item_desc_t *lidp; - xfs_log_item_chunk_t *licp; - int i=0; - - /* - * If there are no free descriptors, allocate a new chunk - * of them and put it at the front of the chunk list. - */ - if (tp->t_items_free == 0) { - licp = (xfs_log_item_chunk_t*) - kmem_alloc(sizeof(xfs_log_item_chunk_t), KM_SLEEP); - ASSERT(licp != NULL); - /* - * Initialize the chunk, and then - * claim the first slot in the newly allocated chunk. - */ - xfs_lic_init(licp); - xfs_lic_claim(licp, 0); - licp->lic_unused = 1; - xfs_lic_init_slot(licp, 0); - lidp = xfs_lic_slot(licp, 0); - - /* - * Link in the new chunk and update the free count. - */ - licp->lic_next = tp->t_items.lic_next; - tp->t_items.lic_next = licp; - tp->t_items_free = XFS_LIC_NUM_SLOTS - 1; - - /* - * Initialize the descriptor and the generic portion - * of the log item. - * - * Point the new slot at this item and return it. - * Also point the log item at its currently active - * descriptor and set the item's mount pointer. - */ - lidp->lid_item = lip; - lidp->lid_flags = 0; - lidp->lid_size = 0; - lip->li_desc = lidp; - lip->li_mountp = tp->t_mountp; - lip->li_ailp = tp->t_mountp->m_ail; - return lidp; - } - - /* - * Find the free descriptor. It is somewhere in the chunklist - * of descriptors. - */ - licp = &tp->t_items; - while (licp != NULL) { - if (xfs_lic_vacancy(licp)) { - if (licp->lic_unused <= XFS_LIC_MAX_SLOT) { - i = licp->lic_unused; - ASSERT(xfs_lic_isfree(licp, i)); - break; - } - for (i = 0; i <= XFS_LIC_MAX_SLOT; i++) { - if (xfs_lic_isfree(licp, i)) - break; - } - ASSERT(i <= XFS_LIC_MAX_SLOT); - break; - } - licp = licp->lic_next; - } - ASSERT(licp != NULL); - /* - * If we find a free descriptor, claim it, - * initialize it, and return it. - */ - xfs_lic_claim(licp, i); - if (licp->lic_unused <= i) { - licp->lic_unused = i + 1; - xfs_lic_init_slot(licp, i); - } - lidp = xfs_lic_slot(licp, i); - tp->t_items_free--; - lidp->lid_item = lip; - lidp->lid_flags = 0; - lidp->lid_size = 0; - lip->li_desc = lidp; - lip->li_mountp = tp->t_mountp; - lip->li_ailp = tp->t_mountp->m_ail; - return lidp; -} - -/* - * Free the given descriptor. - * - * This requires setting the bit in the chunk's free mask corresponding - * to the given slot. - */ -void -xfs_trans_free_item(xfs_trans_t *tp, xfs_log_item_desc_t *lidp) -{ - uint slot; - xfs_log_item_chunk_t *licp; - xfs_log_item_chunk_t **licpp; - - slot = xfs_lic_desc_to_slot(lidp); - licp = xfs_lic_desc_to_chunk(lidp); - xfs_lic_relse(licp, slot); - lidp->lid_item->li_desc = NULL; - tp->t_items_free++; - - /* - * If there are no more used items in the chunk and this is not - * the chunk embedded in the transaction structure, then free - * the chunk. First pull it from the chunk list and then - * free it back to the heap. We didn't bother with a doubly - * linked list here because the lists should be very short - * and this is not a performance path. It's better to save - * the memory of the extra pointer. - * - * Also decrement the transaction structure's count of free items - * by the number in a chunk since we are freeing an empty chunk. - */ - if (xfs_lic_are_all_free(licp) && (licp != &(tp->t_items))) { - licpp = &(tp->t_items.lic_next); - while (*licpp != licp) { - ASSERT(*licpp != NULL); - licpp = &((*licpp)->lic_next); - } - *licpp = licp->lic_next; - kmem_free(licp); - tp->t_items_free -= XFS_LIC_NUM_SLOTS; - } -} - -/* - * This is called to find the descriptor corresponding to the given - * log item. It returns a pointer to the descriptor. - * The log item MUST have a corresponding descriptor in the given - * transaction. This routine does not return NULL, it panics. - * - * The descriptor pointer is kept in the log item's li_desc field. - * Just return it. - */ -/*ARGSUSED*/ -xfs_log_item_desc_t * -xfs_trans_find_item(xfs_trans_t *tp, xfs_log_item_t *lip) -{ - ASSERT(lip->li_desc != NULL); - - return lip->li_desc; -} - - -/* - * Return a pointer to the first descriptor in the chunk list. - * This does not return NULL if there are none, it panics. - * - * The first descriptor must be in either the first or second chunk. - * This is because the only chunk allowed to be empty is the first. - * All others are freed when they become empty. - * - * At some point this and xfs_trans_next_item() should be optimized - * to quickly look at the mask to determine if there is anything to - * look at. - */ -xfs_log_item_desc_t * -xfs_trans_first_item(xfs_trans_t *tp) -{ - xfs_log_item_chunk_t *licp; - int i; - - licp = &tp->t_items; - /* - * If it's not in the first chunk, skip to the second. - */ - if (xfs_lic_are_all_free(licp)) { - licp = licp->lic_next; - } - - /* - * Return the first non-free descriptor in the chunk. - */ - ASSERT(!xfs_lic_are_all_free(licp)); - for (i = 0; i < licp->lic_unused; i++) { - if (xfs_lic_isfree(licp, i)) { - continue; - } - - return xfs_lic_slot(licp, i); - } - cmn_err(CE_WARN, "xfs_trans_first_item() -- no first item"); - return NULL; -} - - -/* - * Given a descriptor, return the next descriptor in the chunk list. - * This returns NULL if there are no more used descriptors in the list. - * - * We do this by first locating the chunk in which the descriptor resides, - * and then scanning forward in the chunk and the list for the next - * used descriptor. - */ -/*ARGSUSED*/ -xfs_log_item_desc_t * -xfs_trans_next_item(xfs_trans_t *tp, xfs_log_item_desc_t *lidp) -{ - xfs_log_item_chunk_t *licp; - int i; - - licp = xfs_lic_desc_to_chunk(lidp); - - /* - * First search the rest of the chunk. The for loop keeps us - * from referencing things beyond the end of the chunk. - */ - for (i = (int)xfs_lic_desc_to_slot(lidp) + 1; i < licp->lic_unused; i++) { - if (xfs_lic_isfree(licp, i)) { - continue; - } - - return xfs_lic_slot(licp, i); - } - - /* - * Now search the next chunk. It must be there, because the - * next chunk would have been freed if it were empty. - * If there is no next chunk, return NULL. - */ - if (licp->lic_next == NULL) { - return NULL; - } - - licp = licp->lic_next; - ASSERT(!xfs_lic_are_all_free(licp)); - for (i = 0; i < licp->lic_unused; i++) { - if (xfs_lic_isfree(licp, i)) { - continue; - } - - return xfs_lic_slot(licp, i); - } - ASSERT(0); - /* NOTREACHED */ - return NULL; /* keep gcc quite */ -} - -/* - * This is called to unlock all of the items of a transaction and to free - * all the descriptors of that transaction. - * - * It walks the list of descriptors and unlocks each item. It frees - * each chunk except that embedded in the transaction as it goes along. - */ -void -xfs_trans_free_items( - xfs_trans_t *tp, - xfs_lsn_t commit_lsn, - int flags) -{ - xfs_log_item_chunk_t *licp; - xfs_log_item_chunk_t *next_licp; - int abort; - - abort = flags & XFS_TRANS_ABORT; - licp = &tp->t_items; - /* - * Special case the embedded chunk so we don't free it below. - */ - if (!xfs_lic_are_all_free(licp)) { - (void) xfs_trans_unlock_chunk(licp, 1, abort, commit_lsn); - xfs_lic_all_free(licp); - licp->lic_unused = 0; - } - licp = licp->lic_next; - - /* - * Unlock each item in each chunk and free the chunks. - */ - while (licp != NULL) { - ASSERT(!xfs_lic_are_all_free(licp)); - (void) xfs_trans_unlock_chunk(licp, 1, abort, commit_lsn); - next_licp = licp->lic_next; - kmem_free(licp); - licp = next_licp; - } - - /* - * Reset the transaction structure's free item count. - */ - tp->t_items_free = XFS_LIC_NUM_SLOTS; - tp->t_items.lic_next = NULL; -} - - - -/* - * This is called to unlock the items associated with a transaction. - * Items which were not logged should be freed. - * Those which were logged must still be tracked so they can be unpinned - * when the transaction commits. - */ -void -xfs_trans_unlock_items(xfs_trans_t *tp, xfs_lsn_t commit_lsn) -{ - xfs_log_item_chunk_t *licp; - xfs_log_item_chunk_t *next_licp; - xfs_log_item_chunk_t **licpp; - int freed; - - freed = 0; - licp = &tp->t_items; - - /* - * Special case the embedded chunk so we don't free. - */ - if (!xfs_lic_are_all_free(licp)) { - freed = xfs_trans_unlock_chunk(licp, 0, 0, commit_lsn); - } - licpp = &(tp->t_items.lic_next); - licp = licp->lic_next; - - /* - * Unlock each item in each chunk, free non-dirty descriptors, - * and free empty chunks. - */ - while (licp != NULL) { - ASSERT(!xfs_lic_are_all_free(licp)); - freed += xfs_trans_unlock_chunk(licp, 0, 0, commit_lsn); - next_licp = licp->lic_next; - if (xfs_lic_are_all_free(licp)) { - *licpp = next_licp; - kmem_free(licp); - freed -= XFS_LIC_NUM_SLOTS; - } else { - licpp = &(licp->lic_next); - } - ASSERT(*licpp == next_licp); - licp = next_licp; - } - - /* - * Fix the free descriptor count in the transaction. - */ - tp->t_items_free += freed; -} - -/* - * Unlock each item pointed to by a descriptor in the given chunk. - * Stamp the commit lsn into each item if necessary. - * Free descriptors pointing to items which are not dirty if freeing_chunk - * is zero. If freeing_chunk is non-zero, then we need to unlock all - * items in the chunk. - * - * Return the number of descriptors freed. - */ -STATIC int -xfs_trans_unlock_chunk( - xfs_log_item_chunk_t *licp, - int freeing_chunk, - int abort, - xfs_lsn_t commit_lsn) -{ - xfs_log_item_desc_t *lidp; - xfs_log_item_t *lip; - int i; - int freed; - - freed = 0; - lidp = licp->lic_descs; - for (i = 0; i < licp->lic_unused; i++, lidp++) { - if (xfs_lic_isfree(licp, i)) { - continue; - } - lip = lidp->lid_item; - lip->li_desc = NULL; - - if (commit_lsn != NULLCOMMITLSN) - IOP_COMMITTING(lip, commit_lsn); - if (abort) - lip->li_flags |= XFS_LI_ABORTED; - IOP_UNLOCK(lip); - - /* - * Free the descriptor if the item is not dirty - * within this transaction and the caller is not - * going to just free the entire thing regardless. - */ - if (!(freeing_chunk) && - (!(lidp->lid_flags & XFS_LID_DIRTY) || abort)) { - xfs_lic_relse(licp, i); - freed++; - } - } - - return freed; -} diff --git a/fs/xfs/xfs_trans_priv.h b/fs/xfs/xfs_trans_priv.h index c6e4f2c8de6e..e2d93d8ead7b 100644 --- a/fs/xfs/xfs_trans_priv.h +++ b/fs/xfs/xfs_trans_priv.h @@ -23,22 +23,8 @@ struct xfs_log_item_desc; struct xfs_mount; struct xfs_trans; -/* - * From xfs_trans_item.c - */ -struct xfs_log_item_desc *xfs_trans_add_item(struct xfs_trans *, - struct xfs_log_item *); -void xfs_trans_free_item(struct xfs_trans *, - struct xfs_log_item_desc *); -struct xfs_log_item_desc *xfs_trans_find_item(struct xfs_trans *, - struct xfs_log_item *); -struct xfs_log_item_desc *xfs_trans_first_item(struct xfs_trans *); -struct xfs_log_item_desc *xfs_trans_next_item(struct xfs_trans *, - struct xfs_log_item_desc *); - -void xfs_trans_unlock_items(struct xfs_trans *tp, xfs_lsn_t commit_lsn); -void xfs_trans_free_items(struct xfs_trans *tp, xfs_lsn_t commit_lsn, - int flags); +void xfs_trans_add_item(struct xfs_trans *, struct xfs_log_item *); +void xfs_trans_del_item(struct xfs_log_item *); void xfs_trans_item_committed(struct xfs_log_item *lip, xfs_lsn_t commit_lsn, int aborted); diff --git a/fs/xfs/xfs_utils.c b/fs/xfs/xfs_utils.c index 4d88616bde91..b7d5769d2df0 100644 --- a/fs/xfs/xfs_utils.c +++ b/fs/xfs/xfs_utils.c @@ -25,18 +25,14 @@ #include "xfs_sb.h" #include "xfs_ag.h" #include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_bmap_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_inode_item.h" #include "xfs_bmap.h" #include "xfs_error.h" #include "xfs_quota.h" -#include "xfs_rw.h" #include "xfs_itable.h" #include "xfs_utils.h" @@ -324,86 +320,3 @@ xfs_bumplink( xfs_trans_log_inode(tp, ip, XFS_ILOG_CORE); return 0; } - -/* - * Try to truncate the given file to 0 length. Currently called - * only out of xfs_remove when it has to truncate a file to free - * up space for the remove to proceed. - */ -int -xfs_truncate_file( - xfs_mount_t *mp, - xfs_inode_t *ip) -{ - xfs_trans_t *tp; - int error; - -#ifdef QUOTADEBUG - /* - * This is called to truncate the quotainodes too. - */ - if (XFS_IS_UQUOTA_ON(mp)) { - if (ip->i_ino != mp->m_sb.sb_uquotino) - ASSERT(ip->i_udquot); - } - if (XFS_IS_OQUOTA_ON(mp)) { - if (ip->i_ino != mp->m_sb.sb_gquotino) - ASSERT(ip->i_gdquot); - } -#endif - /* - * Make the call to xfs_itruncate_start before starting the - * transaction, because we cannot make the call while we're - * in a transaction. - */ - xfs_ilock(ip, XFS_IOLOCK_EXCL); - error = xfs_itruncate_start(ip, XFS_ITRUNC_DEFINITE, (xfs_fsize_t)0); - if (error) { - xfs_iunlock(ip, XFS_IOLOCK_EXCL); - return error; - } - - tp = xfs_trans_alloc(mp, XFS_TRANS_TRUNCATE_FILE); - if ((error = xfs_trans_reserve(tp, 0, XFS_ITRUNCATE_LOG_RES(mp), 0, - XFS_TRANS_PERM_LOG_RES, - XFS_ITRUNCATE_LOG_COUNT))) { - xfs_trans_cancel(tp, 0); - xfs_iunlock(ip, XFS_IOLOCK_EXCL); - return error; - } - - /* - * Follow the normal truncate locking protocol. Since we - * hold the inode in the transaction, we know that its number - * of references will stay constant. - */ - xfs_ilock(ip, XFS_ILOCK_EXCL); - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); - xfs_trans_ihold(tp, ip); - /* - * Signal a sync xaction. The only case where that isn't - * the case is if we're truncating an already unlinked file - * on a wsync fs. In that case, we know the blocks can't - * reappear in the file because the links to file are - * permanently toast. Currently, we're always going to - * want a sync transaction because this code is being - * called from places where nlink is guaranteed to be 1 - * but I'm leaving the tests in to protect against future - * changes -- rcc. - */ - error = xfs_itruncate_finish(&tp, ip, (xfs_fsize_t)0, - XFS_DATA_FORK, - ((ip->i_d.di_nlink != 0 || - !(mp->m_flags & XFS_MOUNT_WSYNC)) - ? 1 : 0)); - if (error) { - xfs_trans_cancel(tp, XFS_TRANS_RELEASE_LOG_RES | - XFS_TRANS_ABORT); - } else { - xfs_ichgtime(ip, XFS_ICHGTIME_MOD | XFS_ICHGTIME_CHG); - error = xfs_trans_commit(tp, XFS_TRANS_RELEASE_LOG_RES); - } - xfs_iunlock(ip, XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); - - return error; -} diff --git a/fs/xfs/xfs_utils.h b/fs/xfs/xfs_utils.h index ef321225d269..f55b9678264f 100644 --- a/fs/xfs/xfs_utils.h +++ b/fs/xfs/xfs_utils.h @@ -18,7 +18,6 @@ #ifndef __XFS_UTILS_H__ #define __XFS_UTILS_H__ -extern int xfs_truncate_file(xfs_mount_t *, xfs_inode_t *); extern int xfs_dir_ialloc(xfs_trans_t **, xfs_inode_t *, mode_t, xfs_nlink_t, xfs_dev_t, cred_t *, prid_t, int, xfs_inode_t **, int *); diff --git a/fs/xfs/xfs_vnodeops.c b/fs/xfs/xfs_vnodeops.c index c1646838898f..3ac137dd531b 100644 --- a/fs/xfs/xfs_vnodeops.c +++ b/fs/xfs/xfs_vnodeops.c @@ -26,19 +26,14 @@ #include "xfs_sb.h" #include "xfs_ag.h" #include "xfs_dir2.h" -#include "xfs_dmapi.h" #include "xfs_mount.h" #include "xfs_da_btree.h" #include "xfs_bmap_btree.h" -#include "xfs_alloc_btree.h" #include "xfs_ialloc_btree.h" -#include "xfs_dir2_sf.h" -#include "xfs_attr_sf.h" #include "xfs_dinode.h" #include "xfs_inode.h" #include "xfs_inode_item.h" #include "xfs_itable.h" -#include "xfs_btree.h" #include "xfs_ialloc.h" #include "xfs_alloc.h" #include "xfs_bmap.h" @@ -73,7 +68,7 @@ xfs_setattr( struct xfs_dquot *udqp, *gdqp, *olddquot1, *olddquot2; int need_iolock = 1; - xfs_itrace_entry(ip); + trace_xfs_setattr(ip); if (mp->m_flags & XFS_MOUNT_RDONLY) return XFS_ERROR(EROFS); @@ -143,16 +138,6 @@ xfs_setattr( goto error_return; } } else { - if (DM_EVENT_ENABLED(ip, DM_EVENT_TRUNCATE) && - !(flags & XFS_ATTR_DMI)) { - int dmflags = AT_DELAY_FLAG(flags) | DM_SEM_FLAG_WR; - code = XFS_SEND_DATA(mp, DM_EVENT_TRUNCATE, ip, - iattr->ia_size, 0, dmflags, NULL); - if (code) { - lock_flags = 0; - goto error_return; - } - } if (need_iolock) lock_flags |= XFS_IOLOCK_EXCL; } @@ -283,8 +268,7 @@ xfs_setattr( commit_flags = XFS_TRANS_RELEASE_LOG_RES; xfs_ilock(ip, XFS_ILOCK_EXCL); - xfs_trans_ijoin(tp, ip, lock_flags); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); /* * Only change the c/mtime if we are changing the size @@ -334,8 +318,7 @@ xfs_setattr( xfs_iflags_set(ip, XFS_ITRUNCATED); } } else if (tp) { - xfs_trans_ijoin(tp, ip, lock_flags); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); } /* @@ -470,17 +453,10 @@ xfs_setattr( return XFS_ERROR(code); } - if (DM_EVENT_ENABLED(ip, DM_EVENT_ATTRIBUTE) && - !(flags & XFS_ATTR_DMI)) { - (void) XFS_SEND_NAMESP(mp, DM_EVENT_ATTRIBUTE, ip, DM_RIGHT_NULL, - NULL, DM_RIGHT_NULL, NULL, NULL, - 0, 0, AT_DELAY_FLAG(flags)); - } return 0; abort_return: commit_flags |= XFS_TRANS_ABORT; - /* FALLTHROUGH */ error_return: xfs_qm_dqrele(udqp); xfs_qm_dqrele(gdqp); @@ -516,7 +492,7 @@ xfs_readlink_bmap( int error = 0; error = xfs_bmapi(NULL, ip, 0, XFS_B_TO_FSB(mp, pathlen), 0, NULL, 0, - mval, &nmaps, NULL, NULL); + mval, &nmaps, NULL); if (error) goto out; @@ -557,7 +533,7 @@ xfs_readlink( int pathlen; int error = 0; - xfs_itrace_entry(ip); + trace_xfs_readlink(ip); if (XFS_FORCED_SHUTDOWN(mp)) return XFS_ERROR(EIO); @@ -613,14 +589,14 @@ xfs_free_eofblocks( */ end_fsb = XFS_B_TO_FSB(mp, ((xfs_ufsize_t)ip->i_size)); last_fsb = XFS_B_TO_FSB(mp, (xfs_ufsize_t)XFS_MAXIOFFSET(mp)); - map_len = last_fsb - end_fsb; - if (map_len <= 0) + if (last_fsb <= end_fsb) return 0; + map_len = last_fsb - end_fsb; nimaps = 1; xfs_ilock(ip, XFS_ILOCK_SHARED); error = xfs_bmapi(NULL, ip, end_fsb, map_len, 0, - NULL, 0, &imap, &nimaps, NULL, NULL); + NULL, 0, &imap, &nimaps, NULL); xfs_iunlock(ip, XFS_ILOCK_SHARED); if (!error && (nimaps != 0) && @@ -675,10 +651,7 @@ xfs_free_eofblocks( } xfs_ilock(ip, XFS_ILOCK_EXCL); - xfs_trans_ijoin(tp, ip, - XFS_IOLOCK_EXCL | - XFS_ILOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); error = xfs_itruncate_finish(&tp, ip, ip->i_size, @@ -750,8 +723,7 @@ xfs_inactive_symlink_rmt( xfs_ilock(ip, XFS_IOLOCK_EXCL | XFS_ILOCK_EXCL); size = (int)ip->i_d.di_size; ip->i_d.di_size = 0; - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); xfs_trans_log_inode(tp, ip, XFS_ILOG_CORE); /* * Find the block(s) so we can inval and unmap them. @@ -761,7 +733,7 @@ xfs_inactive_symlink_rmt( nmaps = ARRAY_SIZE(mval); if ((error = xfs_bmapi(tp, ip, 0, XFS_B_TO_FSB(mp, size), XFS_BMAPI_METADATA, &first_block, 0, mval, &nmaps, - &free_list, NULL))) + &free_list))) goto error0; /* * Invalidate the block(s). @@ -776,7 +748,7 @@ xfs_inactive_symlink_rmt( * Unmap the dead block(s) to the free_list. */ if ((error = xfs_bunmapi(tp, ip, 0, size, XFS_BMAPI_METADATA, nmaps, - &first_block, &free_list, NULL, &done))) + &first_block, &free_list, &done))) goto error1; ASSERT(done); /* @@ -795,8 +767,7 @@ xfs_inactive_symlink_rmt( * Mark it dirty so it will be logged and moved forward in the log as * part of every commit. */ - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); xfs_trans_log_inode(tp, ip, XFS_ILOG_CORE); /* * Get a new, empty transaction to return to our caller. @@ -929,8 +900,7 @@ xfs_inactive_attrs( goto error_cancel; xfs_ilock(ip, XFS_ILOCK_EXCL); - xfs_trans_ijoin(tp, ip, XFS_IOLOCK_EXCL | XFS_ILOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); xfs_idestroy_fork(ip, XFS_ATTR_FORK); ASSERT(ip->i_d.di_anextents == 0); @@ -1035,8 +1005,6 @@ xfs_inactive( int error; int truncate; - xfs_itrace_entry(ip); - /* * If the inode is already free, then there can be nothing * to clean up here. @@ -1060,9 +1028,6 @@ xfs_inactive( mp = ip->i_mount; - if (ip->i_d.di_nlink == 0 && DM_EVENT_ENABLED(ip, DM_EVENT_DESTROY)) - XFS_SEND_DESTROY(mp, ip, DM_RIGHT_NULL); - error = 0; /* If this is a read-only mount, don't do this (would generate I/O) */ @@ -1120,8 +1085,7 @@ xfs_inactive( } xfs_ilock(ip, XFS_ILOCK_EXCL); - xfs_trans_ijoin(tp, ip, XFS_IOLOCK_EXCL | XFS_ILOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); /* * normally, we have to run xfs_itruncate_finish sync. @@ -1154,8 +1118,7 @@ xfs_inactive( return VN_INACTIVE_CACHE; } - xfs_trans_ijoin(tp, ip, XFS_IOLOCK_EXCL | XFS_ILOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); } else { error = xfs_trans_reserve(tp, 0, XFS_IFREE_LOG_RES(mp), @@ -1168,8 +1131,7 @@ xfs_inactive( } xfs_ilock(ip, XFS_ILOCK_EXCL | XFS_IOLOCK_EXCL); - xfs_trans_ijoin(tp, ip, XFS_IOLOCK_EXCL | XFS_ILOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); } /* @@ -1257,7 +1219,7 @@ xfs_lookup( int error; uint lock_mode; - xfs_itrace_entry(dp); + trace_xfs_lookup(dp, name); if (XFS_FORCED_SHUTDOWN(dp->i_mount)) return XFS_ERROR(EIO); @@ -1309,21 +1271,11 @@ xfs_create( uint log_res; uint log_count; - xfs_itrace_entry(dp); + trace_xfs_create(dp, name); if (XFS_FORCED_SHUTDOWN(mp)) return XFS_ERROR(EIO); - if (DM_EVENT_ENABLED(dp, DM_EVENT_CREATE)) { - error = XFS_SEND_NAMESP(mp, DM_EVENT_CREATE, - dp, DM_RIGHT_NULL, NULL, - DM_RIGHT_NULL, name->name, NULL, - mode, 0, 0); - - if (error) - return error; - } - if (dp->i_d.di_flags & XFS_DIFLAG_PROJINHERIT) prid = dp->i_d.di_projid; else @@ -1427,8 +1379,7 @@ xfs_create( * the transaction cancel unlocking dp so don't do it explicitly in the * error path. */ - IHOLD(dp); - xfs_trans_ijoin(tp, dp, XFS_ILOCK_EXCL); + xfs_trans_ijoin_ref(tp, dp, XFS_ILOCK_EXCL); unlock_dp_on_error = B_FALSE; error = xfs_dir_createname(tp, dp, name, ip->i_ino, @@ -1487,16 +1438,7 @@ xfs_create( xfs_qm_dqrele(gdqp); *ipp = ip; - - /* Fallthrough to std_return with error = 0 */ - std_return: - if (DM_EVENT_ENABLED(dp, DM_EVENT_POSTCREATE)) { - XFS_SEND_NAMESP(mp, DM_EVENT_POSTCREATE, dp, DM_RIGHT_NULL, - ip, DM_RIGHT_NULL, name->name, NULL, mode, - error, 0); - } - - return error; + return 0; out_bmap_cancel: xfs_bmap_cancel(&free_list); @@ -1510,8 +1452,8 @@ xfs_create( if (unlock_dp_on_error) xfs_iunlock(dp, XFS_ILOCK_EXCL); - - goto std_return; + std_return: + return error; out_abort_rele: /* @@ -1726,20 +1668,11 @@ xfs_remove( uint resblks; uint log_count; - xfs_itrace_entry(dp); - xfs_itrace_entry(ip); + trace_xfs_remove(dp, name); if (XFS_FORCED_SHUTDOWN(mp)) return XFS_ERROR(EIO); - if (DM_EVENT_ENABLED(dp, DM_EVENT_REMOVE)) { - error = XFS_SEND_NAMESP(mp, DM_EVENT_REMOVE, dp, DM_RIGHT_NULL, - NULL, DM_RIGHT_NULL, name->name, NULL, - ip->i_d.di_mode, 0, 0); - if (error) - return error; - } - error = xfs_qm_dqattach(dp, 0); if (error) goto std_return; @@ -1782,15 +1715,8 @@ xfs_remove( xfs_lock_two_inodes(dp, ip, XFS_ILOCK_EXCL); - /* - * At this point, we've gotten both the directory and the entry - * inodes locked. - */ - IHOLD(ip); - xfs_trans_ijoin(tp, dp, XFS_ILOCK_EXCL); - - IHOLD(dp); - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL); + xfs_trans_ijoin_ref(tp, dp, XFS_ILOCK_EXCL); + xfs_trans_ijoin_ref(tp, ip, XFS_ILOCK_EXCL); /* * If we're removing a directory perform some additional validation. @@ -1877,21 +1803,15 @@ xfs_remove( if (!is_dir && link_zero && xfs_inode_is_filestream(ip)) xfs_filestream_deassociate(ip); - std_return: - if (DM_EVENT_ENABLED(dp, DM_EVENT_POSTREMOVE)) { - XFS_SEND_NAMESP(mp, DM_EVENT_POSTREMOVE, dp, DM_RIGHT_NULL, - NULL, DM_RIGHT_NULL, name->name, NULL, - ip->i_d.di_mode, error, 0); - } - - return error; + return 0; out_bmap_cancel: xfs_bmap_cancel(&free_list); cancel_flags |= XFS_TRANS_ABORT; out_trans_cancel: xfs_trans_cancel(tp, cancel_flags); - goto std_return; + std_return: + return error; } int @@ -1909,25 +1829,13 @@ xfs_link( int committed; int resblks; - xfs_itrace_entry(tdp); - xfs_itrace_entry(sip); + trace_xfs_link(tdp, target_name); ASSERT(!S_ISDIR(sip->i_d.di_mode)); if (XFS_FORCED_SHUTDOWN(mp)) return XFS_ERROR(EIO); - if (DM_EVENT_ENABLED(tdp, DM_EVENT_LINK)) { - error = XFS_SEND_NAMESP(mp, DM_EVENT_LINK, - tdp, DM_RIGHT_NULL, - sip, DM_RIGHT_NULL, - target_name->name, NULL, 0, 0, 0); - if (error) - return error; - } - - /* Return through std_return after this point. */ - error = xfs_qm_dqattach(sip, 0); if (error) goto std_return; @@ -1953,15 +1861,8 @@ xfs_link( xfs_lock_two_inodes(sip, tdp, XFS_ILOCK_EXCL); - /* - * Increment vnode ref counts since xfs_trans_commit & - * xfs_trans_cancel will both unlock the inodes and - * decrement the associated ref counts. - */ - IHOLD(sip); - IHOLD(tdp); - xfs_trans_ijoin(tp, sip, XFS_ILOCK_EXCL); - xfs_trans_ijoin(tp, tdp, XFS_ILOCK_EXCL); + xfs_trans_ijoin_ref(tp, sip, XFS_ILOCK_EXCL); + xfs_trans_ijoin_ref(tp, tdp, XFS_ILOCK_EXCL); /* * If the source has too many links, we can't make any more to it. @@ -2014,27 +1915,14 @@ xfs_link( goto abort_return; } - error = xfs_trans_commit(tp, XFS_TRANS_RELEASE_LOG_RES); - if (error) - goto std_return; - - /* Fall through to std_return with error = 0. */ -std_return: - if (DM_EVENT_ENABLED(sip, DM_EVENT_POSTLINK)) { - (void) XFS_SEND_NAMESP(mp, DM_EVENT_POSTLINK, - tdp, DM_RIGHT_NULL, - sip, DM_RIGHT_NULL, - target_name->name, NULL, 0, error, 0); - } - return error; + return xfs_trans_commit(tp, XFS_TRANS_RELEASE_LOG_RES); abort_return: cancel_flags |= XFS_TRANS_ABORT; - /* FALLTHROUGH */ - error_return: xfs_trans_cancel(tp, cancel_flags); - goto std_return; + std_return: + return error; } int @@ -2074,7 +1962,7 @@ xfs_symlink( ip = NULL; tp = NULL; - xfs_itrace_entry(dp); + trace_xfs_symlink(dp, link_name); if (XFS_FORCED_SHUTDOWN(mp)) return XFS_ERROR(EIO); @@ -2086,17 +1974,6 @@ xfs_symlink( if (pathlen >= MAXPATHLEN) /* total string too long */ return XFS_ERROR(ENAMETOOLONG); - if (DM_EVENT_ENABLED(dp, DM_EVENT_SYMLINK)) { - error = XFS_SEND_NAMESP(mp, DM_EVENT_SYMLINK, dp, - DM_RIGHT_NULL, NULL, DM_RIGHT_NULL, - link_name->name, - (unsigned char *)target_path, 0, 0, 0); - if (error) - return error; - } - - /* Return through std_return after this point. */ - udqp = gdqp = NULL; if (dp->i_d.di_flags & XFS_DIFLAG_PROJINHERIT) prid = dp->i_d.di_projid; @@ -2180,8 +2057,7 @@ xfs_symlink( * transaction cancel unlocking dp so don't do it explicitly in the * error path. */ - IHOLD(dp); - xfs_trans_ijoin(tp, dp, XFS_ILOCK_EXCL); + xfs_trans_ijoin_ref(tp, dp, XFS_ILOCK_EXCL); unlock_dp_on_error = B_FALSE; /* @@ -2215,7 +2091,7 @@ xfs_symlink( error = xfs_bmapi(tp, ip, first_fsb, fs_blocks, XFS_BMAPI_WRITE | XFS_BMAPI_METADATA, &first_block, resblks, mval, &nmaps, - &free_list, NULL); + &free_list); if (error) { goto error1; } @@ -2278,21 +2154,8 @@ xfs_symlink( xfs_qm_dqrele(udqp); xfs_qm_dqrele(gdqp); - /* Fall through to std_return with error = 0 or errno from - * xfs_trans_commit */ -std_return: - if (DM_EVENT_ENABLED(dp, DM_EVENT_POSTSYMLINK)) { - (void) XFS_SEND_NAMESP(mp, DM_EVENT_POSTSYMLINK, - dp, DM_RIGHT_NULL, - error ? NULL : ip, - DM_RIGHT_NULL, link_name->name, - (unsigned char *)target_path, - 0, error, 0); - } - - if (!error) - *ipp = ip; - return error; + *ipp = ip; + return 0; error2: IRELE(ip); @@ -2306,8 +2169,8 @@ std_return: if (unlock_dp_on_error) xfs_iunlock(dp, XFS_ILOCK_EXCL); - - goto std_return; + std_return: + return error; } int @@ -2333,13 +2196,12 @@ xfs_set_dmattrs( return error; } xfs_ilock(ip, XFS_ILOCK_EXCL); - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL); + xfs_trans_ijoin_ref(tp, ip, XFS_ILOCK_EXCL); ip->i_d.di_dmevmask = evmask; ip->i_d.di_dmstate = state; xfs_trans_log_inode(tp, ip, XFS_ILOG_CORE); - IHOLD(ip); error = xfs_trans_commit(tp, 0); return error; @@ -2390,7 +2252,7 @@ xfs_alloc_file_space( int committed; int error; - xfs_itrace_entry(ip); + trace_xfs_alloc_file_space(ip); if (XFS_FORCED_SHUTDOWN(mp)) return XFS_ERROR(EIO); @@ -2412,25 +2274,9 @@ xfs_alloc_file_space( startoffset_fsb = XFS_B_TO_FSBT(mp, offset); allocatesize_fsb = XFS_B_TO_FSB(mp, count); - /* Generate a DMAPI event if needed. */ - if (alloc_type != 0 && offset < ip->i_size && - (attr_flags & XFS_ATTR_DMI) == 0 && - DM_EVENT_ENABLED(ip, DM_EVENT_WRITE)) { - xfs_off_t end_dmi_offset; - - end_dmi_offset = offset+len; - if (end_dmi_offset > ip->i_size) - end_dmi_offset = ip->i_size; - error = XFS_SEND_DATA(mp, DM_EVENT_WRITE, ip, offset, - end_dmi_offset - offset, 0, NULL); - if (error) - return error; - } - /* * Allocate file space until done or until there is an error */ -retry: while (allocatesize_fsb && !error) { xfs_fileoff_t s, e; @@ -2488,8 +2334,7 @@ retry: if (error) goto error1; - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); /* * Issue the xfs_bmapi() call to allocate the blocks @@ -2498,7 +2343,7 @@ retry: error = xfs_bmapi(tp, ip, startoffset_fsb, allocatesize_fsb, bmapi_flag, &firstfsb, 0, imapp, &nimaps, - &free_list, NULL); + &free_list); if (error) { goto error0; } @@ -2527,17 +2372,6 @@ retry: startoffset_fsb += allocated_fsb; allocatesize_fsb -= allocated_fsb; } -dmapi_enospc_check: - if (error == ENOSPC && (attr_flags & XFS_ATTR_DMI) == 0 && - DM_EVENT_ENABLED(ip, DM_EVENT_NOSPACE)) { - error = XFS_SEND_NAMESP(mp, DM_EVENT_NOSPACE, - ip, DM_RIGHT_NULL, - ip, DM_RIGHT_NULL, - NULL, NULL, 0, 0, 0); /* Delay flag intentionally unused */ - if (error == 0) - goto retry; /* Maybe DMAPI app. has made space */ - /* else fall through with error from XFS_SEND_DATA */ - } return error; @@ -2548,7 +2382,7 @@ error0: /* Cancel bmap, unlock inode, unreserve quota blocks, cancel trans */ error1: /* Just cancel transaction */ xfs_trans_cancel(tp, XFS_TRANS_RELEASE_LOG_RES | XFS_TRANS_ABORT); xfs_iunlock(ip, XFS_ILOCK_EXCL); - goto dmapi_enospc_check; + return error; } /* @@ -2598,7 +2432,7 @@ xfs_zero_remaining_bytes( offset_fsb = XFS_B_TO_FSBT(mp, offset); nimap = 1; error = xfs_bmapi(NULL, ip, offset_fsb, 1, 0, - NULL, 0, &imap, &nimap, NULL, NULL); + NULL, 0, &imap, &nimap, NULL); if (error || nimap < 1) break; ASSERT(imap.br_blockcount >= 1); @@ -2661,7 +2495,6 @@ xfs_free_file_space( { int committed; int done; - xfs_off_t end_dmi_offset; xfs_fileoff_t endoffset_fsb; int error; xfs_fsblock_t firstfsb; @@ -2680,7 +2513,7 @@ xfs_free_file_space( mp = ip->i_mount; - xfs_itrace_entry(ip); + trace_xfs_free_file_space(ip); error = xfs_qm_dqattach(ip, 0); if (error) @@ -2691,19 +2524,7 @@ xfs_free_file_space( return error; rt = XFS_IS_REALTIME_INODE(ip); startoffset_fsb = XFS_B_TO_FSB(mp, offset); - end_dmi_offset = offset + len; - endoffset_fsb = XFS_B_TO_FSBT(mp, end_dmi_offset); - - if (offset < ip->i_size && (attr_flags & XFS_ATTR_DMI) == 0 && - DM_EVENT_ENABLED(ip, DM_EVENT_WRITE)) { - if (end_dmi_offset > ip->i_size) - end_dmi_offset = ip->i_size; - error = XFS_SEND_DATA(mp, DM_EVENT_WRITE, ip, - offset, end_dmi_offset - offset, - AT_DELAY_FLAG(attr_flags), NULL); - if (error) - return error; - } + endoffset_fsb = XFS_B_TO_FSBT(mp, offset + len); if (attr_flags & XFS_ATTR_NOLOCK) need_iolock = 0; @@ -2731,7 +2552,7 @@ xfs_free_file_space( if (rt && !xfs_sb_version_hasextflgbit(&mp->m_sb)) { nimap = 1; error = xfs_bmapi(NULL, ip, startoffset_fsb, - 1, 0, NULL, 0, &imap, &nimap, NULL, NULL); + 1, 0, NULL, 0, &imap, &nimap, NULL); if (error) goto out_unlock_iolock; ASSERT(nimap == 0 || nimap == 1); @@ -2746,7 +2567,7 @@ xfs_free_file_space( } nimap = 1; error = xfs_bmapi(NULL, ip, endoffset_fsb - 1, - 1, 0, NULL, 0, &imap, &nimap, NULL, NULL); + 1, 0, NULL, 0, &imap, &nimap, NULL); if (error) goto out_unlock_iolock; ASSERT(nimap == 0 || nimap == 1); @@ -2814,8 +2635,7 @@ xfs_free_file_space( if (error) goto error1; - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); /* * issue the bunmapi() call to free the blocks @@ -2823,7 +2643,7 @@ xfs_free_file_space( xfs_bmap_init(&free_list, &firstfsb); error = xfs_bunmapi(tp, ip, startoffset_fsb, endoffset_fsb - startoffset_fsb, - 0, 2, &firstfsb, &free_list, NULL, &done); + 0, 2, &firstfsb, &free_list, &done); if (error) { goto error0; } @@ -2883,8 +2703,6 @@ xfs_change_file_space( xfs_trans_t *tp; struct iattr iattr; - xfs_itrace_entry(ip); - if (!S_ISREG(ip->i_d.di_mode)) return XFS_ERROR(EINVAL); @@ -2985,8 +2803,7 @@ xfs_change_file_space( xfs_ilock(ip, XFS_ILOCK_EXCL); - xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL); - xfs_trans_ihold(tp, ip); + xfs_trans_ijoin(tp, ip); if ((attr_flags & XFS_ATTR_DMI) == 0) { ip->i_d.di_mode &= ~S_ISUID; diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index 8b1038607831..b0c174012436 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -14,14 +14,19 @@ #ifndef ASMARM_AMBA_H #define ASMARM_AMBA_H +#include <linux/clk.h> #include <linux/device.h> +#include <linux/err.h> #include <linux/resource.h> #define AMBA_NR_IRQS 2 +struct clk; + struct amba_device { struct device dev; struct resource res; + struct clk *pclk; u64 dma_mask; unsigned int periphid; unsigned int irq[AMBA_NR_IRQS]; @@ -59,6 +64,12 @@ struct amba_device *amba_find_device(const char *, struct device *, unsigned int int amba_request_regions(struct amba_device *, const char *); void amba_release_regions(struct amba_device *); +#define amba_pclk_enable(d) \ + (IS_ERR((d)->pclk) ? 0 : clk_enable((d)->pclk)) + +#define amba_pclk_disable(d) \ + do { if (!IS_ERR((d)->pclk)) clk_disable((d)->pclk); } while (0) + #define amba_config(d) (((d)->periphid >> 24) & 0xff) #define amba_rev(d) (((d)->periphid >> 20) & 0x0f) #define amba_manf(d) (((d)->periphid >> 12) & 0xff) diff --git a/include/linux/amba/mmci.h b/include/linux/amba/mmci.h index 7e466fe72025..ca84ce70d5d5 100644 --- a/include/linux/amba/mmci.h +++ b/include/linux/amba/mmci.h @@ -15,9 +15,10 @@ * @ocr_mask: available voltages on the 4 pins from the block, this * is ignored if a regulator is used, see the MMC_VDD_* masks in * mmc/host.h - * @translate_vdd: a callback function to translate a MMC_VDD_* - * mask into a value to be binary or:ed and written into the - * MMCIPWR register of the block + * @vdd_handler: a callback function to translate a MMC_VDD_* + * mask into a value to be binary (or set some other custom bits + * in MMCIPWR) or:ed and written into the MMCIPWR register of the + * block. May also control external power based on the power_mode. * @status: if no GPIO read function was given to the block in * gpio_wp (below) this function will be called to determine * whether a card is present in the MMC slot or not @@ -29,7 +30,8 @@ struct mmci_platform_data { unsigned int f_max; unsigned int ocr_mask; - u32 (*translate_vdd)(struct device *, unsigned int); + u32 (*vdd_handler)(struct device *, unsigned int vdd, + unsigned char power_mode); unsigned int (*status)(struct device *); int gpio_wp; int gpio_cd; diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h index 5a5a7fd62490..e1b634b635f2 100644 --- a/include/linux/amba/serial.h +++ b/include/linux/amba/serial.h @@ -38,10 +38,12 @@ #define UART01x_FR 0x18 /* Flag register (Read only). */ #define UART010_IIR 0x1C /* Interrupt indentification register (Read). */ #define UART010_ICR 0x1C /* Interrupt clear register (Write). */ +#define ST_UART011_LCRH_RX 0x1C /* Rx line control register. */ #define UART01x_ILPR 0x20 /* IrDA low power counter register. */ #define UART011_IBRD 0x24 /* Integer baud rate divisor register. */ #define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */ #define UART011_LCRH 0x2c /* Line control register. */ +#define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */ #define UART011_CR 0x30 /* Control register. */ #define UART011_IFLS 0x34 /* Interrupt fifo level select. */ #define UART011_IMSC 0x38 /* Interrupt mask. */ @@ -84,6 +86,7 @@ #define UART010_CR_TIE 0x0020 #define UART010_CR_RIE 0x0010 #define UART010_CR_MSIE 0x0008 +#define ST_UART011_CR_OVSFACT 0x0008 /* Oversampling factor */ #define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */ #define UART01x_CR_SIREN 0x0002 /* SIR enable */ #define UART01x_CR_UARTEN 0x0001 /* UART enable */ diff --git a/include/linux/cred.h b/include/linux/cred.h index 75c0fa881308..4d2c39573f36 100644 --- a/include/linux/cred.h +++ b/include/linux/cred.h @@ -153,6 +153,7 @@ struct cred { extern void __put_cred(struct cred *); extern void exit_creds(struct task_struct *); extern int copy_creds(struct task_struct *, unsigned long); +extern const struct cred *get_task_cred(struct task_struct *); extern struct cred *cred_alloc_blank(void); extern struct cred *prepare_creds(void); extern struct cred *prepare_exec_creds(void); @@ -273,33 +274,18 @@ static inline void put_cred(const struct cred *_cred) * @task: The task to query * * Access the objective credentials of a task. The caller must hold the RCU - * readlock. + * readlock or the task must be dead and unable to change its own credentials. * - * The caller must make sure task doesn't go away, either by holding a ref on - * task or by holding tasklist_lock to prevent it from being unlinked. + * The result of this function should not be passed directly to get_cred(); + * rather get_task_cred() should be used instead. */ -#define __task_cred(task) \ - ((const struct cred *)(rcu_dereference_check((task)->real_cred, rcu_read_lock_held() || lockdep_tasklist_lock_is_held()))) - -/** - * get_task_cred - Get another task's objective credentials - * @task: The task to query - * - * Get the objective credentials of a task, pinning them so that they can't go - * away. Accessing a task's credentials directly is not permitted. - * - * The caller must make sure task doesn't go away, either by holding a ref on - * task or by holding tasklist_lock to prevent it from being unlinked. - */ -#define get_task_cred(task) \ -({ \ - struct cred *__cred; \ - rcu_read_lock(); \ - __cred = (struct cred *) __task_cred((task)); \ - get_cred(__cred); \ - rcu_read_unlock(); \ - __cred; \ -}) +#define __task_cred(task) \ + ({ \ + const struct task_struct *__t = (task); \ + rcu_dereference_check(__t->real_cred, \ + rcu_read_lock_held() || \ + task_is_dead(__t)); \ + }) /** * get_current_cred - Get the current task's subjective credentials diff --git a/include/linux/fs.h b/include/linux/fs.h index 68ca1b0491af..f91affb7d530 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -415,7 +415,8 @@ struct buffer_head; typedef int (get_block_t)(struct inode *inode, sector_t iblock, struct buffer_head *bh_result, int create); typedef void (dio_iodone_t)(struct kiocb *iocb, loff_t offset, - ssize_t bytes, void *private); + ssize_t bytes, void *private, int ret, + bool is_async); /* * Attribute flags. These should be or-ed together to figure out what diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h new file mode 100644 index 000000000000..2ed4fb8bbd51 --- /dev/null +++ b/include/linux/marvell_phy.h @@ -0,0 +1,20 @@ +#ifndef _MARVELL_PHY_H +#define _MARVELL_PHY_H + +/* Mask used for ID comparisons */ +#define MARVELL_PHY_ID_MASK 0xfffffff0 + +/* Known PHY IDs */ +#define MARVELL_PHY_ID_88E1101 0x01410c60 +#define MARVELL_PHY_ID_88E1112 0x01410c90 +#define MARVELL_PHY_ID_88E1111 0x01410cc0 +#define MARVELL_PHY_ID_88E1118 0x01410e10 +#define MARVELL_PHY_ID_88E1121R 0x01410cb0 +#define MARVELL_PHY_ID_88E1145 0x01410cd0 +#define MARVELL_PHY_ID_88E1240 0x01410e30 + +/* struct phy_device dev_flags definitions */ +#define MARVELL_PHY_M1145_FLAGS_RESISTANCE 0x00000001 +#define MARVELL_PHY_M1118_DNS323_LEDS 0x00000002 + +#endif /* _MARVELL_PHY_H */ diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h index 77c2ae53431c..bad4d121b16e 100644 --- a/include/linux/nfs_fs.h +++ b/include/linux/nfs_fs.h @@ -493,8 +493,15 @@ extern int nfs_wb_all(struct inode *inode); extern int nfs_wb_page(struct inode *inode, struct page* page); extern int nfs_wb_page_cancel(struct inode *inode, struct page* page); #if defined(CONFIG_NFS_V3) || defined(CONFIG_NFS_V4) +extern int nfs_commit_inode(struct inode *, int); extern struct nfs_write_data *nfs_commitdata_alloc(void); extern void nfs_commit_free(struct nfs_write_data *wdata); +#else +static inline int +nfs_commit_inode(struct inode *inode, int how) +{ + return 0; +} #endif static inline int diff --git a/include/linux/omapfb.h b/include/linux/omapfb.h index 9bdd91486b49..7e4cd616bcb5 100644 --- a/include/linux/omapfb.h +++ b/include/linux/omapfb.h @@ -253,7 +253,7 @@ struct omapfb_platform_data { /* in arch/arm/plat-omap/fb.c */ extern void omapfb_set_platform_data(struct omapfb_platform_data *data); extern void omapfb_set_ctrl_platform_data(void *pdata); -extern void omapfb_reserve_sdram(void); +extern void omapfb_reserve_sdram_memblock(void); #endif diff --git a/include/linux/sched.h b/include/linux/sched.h index 747fcaedddb7..0478888c6899 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -214,6 +214,7 @@ extern char ___assert_task_state[1 - 2*!!( #define task_is_traced(task) ((task->state & __TASK_TRACED) != 0) #define task_is_stopped(task) ((task->state & __TASK_STOPPED) != 0) +#define task_is_dead(task) ((task)->exit_state != 0) #define task_is_stopped_or_traced(task) \ ((task->state & (__TASK_STOPPED | __TASK_TRACED)) != 0) #define task_contributes_to_load(task) \ diff --git a/include/linux/virtio_9p.h b/include/linux/virtio_9p.h index 5cf11765146b..395c38a47adb 100644 --- a/include/linux/virtio_9p.h +++ b/include/linux/virtio_9p.h @@ -4,6 +4,7 @@ * compatible drivers/servers. */ #include <linux/virtio_ids.h> #include <linux/virtio_config.h> +#include <linux/types.h> /* The feature bitmap for virtio 9P */ diff --git a/include/net/9p/9p.h b/include/net/9p/9p.h index 156c26bb8bd7..a8de812ccbc8 100644 --- a/include/net/9p/9p.h +++ b/include/net/9p/9p.h @@ -88,8 +88,16 @@ do { \ * enum p9_msg_t - 9P message types * @P9_TSTATFS: file system status request * @P9_RSTATFS: file system status response + * @P9_TSYMLINK: make symlink request + * @P9_RSYMLINK: make symlink response + * @P9_TMKNOD: create a special file object request + * @P9_RMKNOD: create a special file object response + * @P9_TLCREATE: prepare a handle for I/O on an new file for 9P2000.L + * @P9_RLCREATE: response with file access information for 9P2000.L * @P9_TRENAME: rename request * @P9_RRENAME: rename response + * @P9_TMKDIR: create a directory request + * @P9_RMKDIR: create a directory response * @P9_TVERSION: version handshake request * @P9_RVERSION: version handshake response * @P9_TAUTH: request to establish authentication channel @@ -131,8 +139,30 @@ do { \ enum p9_msg_t { P9_TSTATFS = 8, P9_RSTATFS, + P9_TLOPEN = 12, + P9_RLOPEN, + P9_TLCREATE = 14, + P9_RLCREATE, + P9_TSYMLINK = 16, + P9_RSYMLINK, + P9_TMKNOD = 18, + P9_RMKNOD, P9_TRENAME = 20, P9_RRENAME, + P9_TGETATTR = 24, + P9_RGETATTR, + P9_TSETATTR = 26, + P9_RSETATTR, + P9_TXATTRWALK = 30, + P9_RXATTRWALK, + P9_TXATTRCREATE = 32, + P9_RXATTRCREATE, + P9_TREADDIR = 40, + P9_RREADDIR, + P9_TLINK = 70, + P9_RLINK, + P9_TMKDIR = 72, + P9_RMKDIR, P9_TVERSION = 100, P9_RVERSION, P9_TAUTH = 102, @@ -275,6 +305,9 @@ enum p9_qid_t { /* ample room for Twrite/Rread header */ #define P9_IOHDRSZ 24 +/* Room for readdir header */ +#define P9_READDIRHDRSZ 24 + /** * struct p9_str - length prefixed string type * @len: length of the string @@ -357,6 +390,74 @@ struct p9_wstat { u32 n_muid; /* 9p2000.u extensions */ }; +struct p9_stat_dotl { + u64 st_result_mask; + struct p9_qid qid; + u32 st_mode; + u32 st_uid; + u32 st_gid; + u64 st_nlink; + u64 st_rdev; + u64 st_size; + u64 st_blksize; + u64 st_blocks; + u64 st_atime_sec; + u64 st_atime_nsec; + u64 st_mtime_sec; + u64 st_mtime_nsec; + u64 st_ctime_sec; + u64 st_ctime_nsec; + u64 st_btime_sec; + u64 st_btime_nsec; + u64 st_gen; + u64 st_data_version; +}; + +#define P9_STATS_MODE 0x00000001ULL +#define P9_STATS_NLINK 0x00000002ULL +#define P9_STATS_UID 0x00000004ULL +#define P9_STATS_GID 0x00000008ULL +#define P9_STATS_RDEV 0x00000010ULL +#define P9_STATS_ATIME 0x00000020ULL +#define P9_STATS_MTIME 0x00000040ULL +#define P9_STATS_CTIME 0x00000080ULL +#define P9_STATS_INO 0x00000100ULL +#define P9_STATS_SIZE 0x00000200ULL +#define P9_STATS_BLOCKS 0x00000400ULL + +#define P9_STATS_BTIME 0x00000800ULL +#define P9_STATS_GEN 0x00001000ULL +#define P9_STATS_DATA_VERSION 0x00002000ULL + +#define P9_STATS_BASIC 0x000007ffULL /* Mask for fields up to BLOCKS */ +#define P9_STATS_ALL 0x00003fffULL /* Mask for All fields above */ + +/** + * struct p9_iattr_dotl - P9 inode attribute for setattr + * @valid: bitfield specifying which fields are valid + * same as in struct iattr + * @mode: File permission bits + * @uid: user id of owner + * @gid: group id + * @size: File size + * @atime_sec: Last access time, seconds + * @atime_nsec: Last access time, nanoseconds + * @mtime_sec: Last modification time, seconds + * @mtime_nsec: Last modification time, nanoseconds + */ + +struct p9_iattr_dotl { + u32 valid; + u32 mode; + u32 uid; + u32 gid; + u64 size; + u64 atime_sec; + u64 atime_nsec; + u64 mtime_sec; + u64 mtime_nsec; +}; + /* Structures for Protocol Operations */ struct p9_tstatfs { u32 fid; @@ -485,6 +586,18 @@ struct p9_rwrite { u32 count; }; +struct p9_treaddir { + u32 fid; + u64 offset; + u32 count; +}; + +struct p9_rreaddir { + u32 count; + u8 *data; +}; + + struct p9_tclunk { u32 fid; }; diff --git a/include/net/9p/client.h b/include/net/9p/client.h index 7dd3ed85c782..d1aa2cfb30f0 100644 --- a/include/net/9p/client.h +++ b/include/net/9p/client.h @@ -195,6 +195,21 @@ struct p9_fid { struct list_head dlist; /* list of all fids attached to a dentry */ }; +/** + * struct p9_dirent - directory entry structure + * @qid: The p9 server qid for this dirent + * @d_off: offset to the next dirent + * @d_type: type of file + * @d_name: file name + */ + +struct p9_dirent { + struct p9_qid qid; + u64 d_off; + unsigned char d_type; + char d_name[256]; +}; + int p9_client_statfs(struct p9_fid *fid, struct p9_rstatfs *sb); int p9_client_rename(struct p9_fid *fid, struct p9_fid *newdirfid, char *name); int p9_client_version(struct p9_client *); @@ -211,15 +226,31 @@ struct p9_fid *p9_client_walk(struct p9_fid *oldfid, int nwname, char **wnames, int p9_client_open(struct p9_fid *fid, int mode); int p9_client_fcreate(struct p9_fid *fid, char *name, u32 perm, int mode, char *extension); +int p9_client_link(struct p9_fid *fid, struct p9_fid *oldfid, char *newname); +int p9_client_symlink(struct p9_fid *fid, char *name, char *symname, gid_t gid, + struct p9_qid *qid); +int p9_client_create_dotl(struct p9_fid *ofid, char *name, u32 flags, u32 mode, + gid_t gid, struct p9_qid *qid); int p9_client_clunk(struct p9_fid *fid); int p9_client_remove(struct p9_fid *fid); int p9_client_read(struct p9_fid *fid, char *data, char __user *udata, u64 offset, u32 count); int p9_client_write(struct p9_fid *fid, char *data, const char __user *udata, u64 offset, u32 count); +int p9_client_readdir(struct p9_fid *fid, char *data, u32 count, u64 offset); +int p9dirent_read(char *buf, int len, struct p9_dirent *dirent, + int proto_version); struct p9_wstat *p9_client_stat(struct p9_fid *fid); int p9_client_wstat(struct p9_fid *fid, struct p9_wstat *wst); +int p9_client_setattr(struct p9_fid *fid, struct p9_iattr_dotl *attr); + +struct p9_stat_dotl *p9_client_getattr_dotl(struct p9_fid *fid, + u64 request_mask); +int p9_client_mknod_dotl(struct p9_fid *oldfid, char *name, int mode, + dev_t rdev, gid_t gid, struct p9_qid *); +int p9_client_mkdir_dotl(struct p9_fid *fid, char *name, int mode, + gid_t gid, struct p9_qid *); struct p9_req_t *p9_tag_lookup(struct p9_client *, u16); void p9_client_cb(struct p9_client *c, struct p9_req_t *req); @@ -229,5 +260,7 @@ void p9stat_free(struct p9_wstat *); int p9_is_proto_dotu(struct p9_client *clnt); int p9_is_proto_dotl(struct p9_client *clnt); +struct p9_fid *p9_client_xattrwalk(struct p9_fid *, const char *, u64 *); +int p9_client_xattrcreate(struct p9_fid *, const char *, u64, int); #endif /* NET_9P_CLIENT_H */ diff --git a/kernel/cred.c b/kernel/cred.c index a2d5504fbcc2..60bc8b1e32e6 100644 --- a/kernel/cred.c +++ b/kernel/cred.c @@ -209,6 +209,31 @@ void exit_creds(struct task_struct *tsk) } } +/** + * get_task_cred - Get another task's objective credentials + * @task: The task to query + * + * Get the objective credentials of a task, pinning them so that they can't go + * away. Accessing a task's credentials directly is not permitted. + * + * The caller must also make sure task doesn't get deleted, either by holding a + * ref on task or by holding tasklist_lock to prevent it from being unlinked. + */ +const struct cred *get_task_cred(struct task_struct *task) +{ + const struct cred *cred; + + rcu_read_lock(); + + do { + cred = __task_cred((task)); + BUG_ON(!cred); + } while (!atomic_inc_not_zero(&((struct cred *)cred)->usage)); + + rcu_read_unlock(); + return cred; +} + /* * Allocate blank credentials, such that the credentials can be filled in at a * later date without risk of ENOMEM. diff --git a/lib/atomic64_test.c b/lib/atomic64_test.c index 250ed11d3ed2..44524cc8c32a 100644 --- a/lib/atomic64_test.c +++ b/lib/atomic64_test.c @@ -114,7 +114,7 @@ static __init int test_atomic64(void) BUG_ON(v.counter != r); #if defined(CONFIG_X86) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ - defined(CONFIG_S390) || defined(_ASM_GENERIC_ATOMIC64_H) + defined(CONFIG_S390) || defined(_ASM_GENERIC_ATOMIC64_H) || defined(CONFIG_ARM) INIT(onestwos); BUG_ON(atomic64_dec_if_positive(&v) != (onestwos - 1)); r -= one; diff --git a/mm/memory.c b/mm/memory.c index 119b7ccdf39b..bde42c6d3633 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -1394,10 +1394,20 @@ int __get_user_pages(struct task_struct *tsk, struct mm_struct *mm, return i ? : -EFAULT; } if (pages) { - struct page *page = vm_normal_page(gate_vma, start, *pte); + struct page *page; + + page = vm_normal_page(gate_vma, start, *pte); + if (!page) { + if (!(gup_flags & FOLL_DUMP) && + is_zero_pfn(pte_pfn(*pte))) + page = pte_page(*pte); + else { + pte_unmap(pte); + return i ? : -EFAULT; + } + } pages[i] = page; - if (page) - get_page(page); + get_page(page); } pte_unmap(pte); if (vmas) diff --git a/net/9p/client.c b/net/9p/client.c index 37c8da07a80b..dc6f2f26d023 100644 --- a/net/9p/client.c +++ b/net/9p/client.c @@ -460,7 +460,8 @@ static int p9_check_errors(struct p9_client *c, struct p9_req_t *req) return err; } - if (p9_is_proto_dotu(c)) + if (p9_is_proto_dotu(c) || + p9_is_proto_dotl(c)) err = -ecode; if (!err || !IS_ERR_VALUE(err)) @@ -1015,14 +1016,18 @@ int p9_client_open(struct p9_fid *fid, int mode) struct p9_qid qid; int iounit; - P9_DPRINTK(P9_DEBUG_9P, ">>> TOPEN fid %d mode %d\n", fid->fid, mode); - err = 0; clnt = fid->clnt; + P9_DPRINTK(P9_DEBUG_9P, ">>> %s fid %d mode %d\n", + p9_is_proto_dotl(clnt) ? "TLOPEN" : "TOPEN", fid->fid, mode); + err = 0; if (fid->mode != -1) return -EINVAL; - req = p9_client_rpc(clnt, P9_TOPEN, "db", fid->fid, mode); + if (p9_is_proto_dotl(clnt)) + req = p9_client_rpc(clnt, P9_TLOPEN, "dd", fid->fid, mode); + else + req = p9_client_rpc(clnt, P9_TOPEN, "db", fid->fid, mode); if (IS_ERR(req)) { err = PTR_ERR(req); goto error; @@ -1034,10 +1039,9 @@ int p9_client_open(struct p9_fid *fid, int mode) goto free_and_error; } - P9_DPRINTK(P9_DEBUG_9P, "<<< ROPEN qid %x.%llx.%x iounit %x\n", - qid.type, - (unsigned long long)qid.path, - qid.version, iounit); + P9_DPRINTK(P9_DEBUG_9P, "<<< %s qid %x.%llx.%x iounit %x\n", + p9_is_proto_dotl(clnt) ? "RLOPEN" : "ROPEN", qid.type, + (unsigned long long)qid.path, qid.version, iounit); fid->mode = mode; fid->iounit = iounit; @@ -1049,6 +1053,50 @@ error: } EXPORT_SYMBOL(p9_client_open); +int p9_client_create_dotl(struct p9_fid *ofid, char *name, u32 flags, u32 mode, + gid_t gid, struct p9_qid *qid) +{ + int err = 0; + struct p9_client *clnt; + struct p9_req_t *req; + int iounit; + + P9_DPRINTK(P9_DEBUG_9P, + ">>> TLCREATE fid %d name %s flags %d mode %d gid %d\n", + ofid->fid, name, flags, mode, gid); + clnt = ofid->clnt; + + if (ofid->mode != -1) + return -EINVAL; + + req = p9_client_rpc(clnt, P9_TLCREATE, "dsddd", ofid->fid, name, flags, + mode, gid); + if (IS_ERR(req)) { + err = PTR_ERR(req); + goto error; + } + + err = p9pdu_readf(req->rc, clnt->proto_version, "Qd", qid, &iounit); + if (err) { + p9pdu_dump(1, req->rc); + goto free_and_error; + } + + P9_DPRINTK(P9_DEBUG_9P, "<<< RLCREATE qid %x.%llx.%x iounit %x\n", + qid->type, + (unsigned long long)qid->path, + qid->version, iounit); + + ofid->mode = mode; + ofid->iounit = iounit; + +free_and_error: + p9_free_req(clnt, req); +error: + return err; +} +EXPORT_SYMBOL(p9_client_create_dotl); + int p9_client_fcreate(struct p9_fid *fid, char *name, u32 perm, int mode, char *extension) { @@ -1094,6 +1142,59 @@ error: } EXPORT_SYMBOL(p9_client_fcreate); +int p9_client_symlink(struct p9_fid *dfid, char *name, char *symtgt, gid_t gid, + struct p9_qid *qid) +{ + int err = 0; + struct p9_client *clnt; + struct p9_req_t *req; + + P9_DPRINTK(P9_DEBUG_9P, ">>> TSYMLINK dfid %d name %s symtgt %s\n", + dfid->fid, name, symtgt); + clnt = dfid->clnt; + + req = p9_client_rpc(clnt, P9_TSYMLINK, "dssd", dfid->fid, name, symtgt, + gid); + if (IS_ERR(req)) { + err = PTR_ERR(req); + goto error; + } + + err = p9pdu_readf(req->rc, clnt->proto_version, "Q", qid); + if (err) { + p9pdu_dump(1, req->rc); + goto free_and_error; + } + + P9_DPRINTK(P9_DEBUG_9P, "<<< RSYMLINK qid %x.%llx.%x\n", + qid->type, (unsigned long long)qid->path, qid->version); + +free_and_error: + p9_free_req(clnt, req); +error: + return err; +} +EXPORT_SYMBOL(p9_client_symlink); + +int p9_client_link(struct p9_fid *dfid, struct p9_fid *oldfid, char *newname) +{ + struct p9_client *clnt; + struct p9_req_t *req; + + P9_DPRINTK(P9_DEBUG_9P, ">>> TLINK dfid %d oldfid %d newname %s\n", + dfid->fid, oldfid->fid, newname); + clnt = dfid->clnt; + req = p9_client_rpc(clnt, P9_TLINK, "dds", dfid->fid, oldfid->fid, + newname); + if (IS_ERR(req)) + return PTR_ERR(req); + + P9_DPRINTK(P9_DEBUG_9P, "<<< RLINK\n"); + p9_free_req(clnt, req); + return 0; +} +EXPORT_SYMBOL(p9_client_link); + int p9_client_clunk(struct p9_fid *fid) { int err; @@ -1139,9 +1240,8 @@ int p9_client_remove(struct p9_fid *fid) P9_DPRINTK(P9_DEBUG_9P, "<<< RREMOVE fid %d\n", fid->fid); p9_free_req(clnt, req); - p9_fid_destroy(fid); - error: + p9_fid_destroy(fid); return err; } EXPORT_SYMBOL(p9_client_remove); @@ -1302,6 +1402,65 @@ error: } EXPORT_SYMBOL(p9_client_stat); +struct p9_stat_dotl *p9_client_getattr_dotl(struct p9_fid *fid, + u64 request_mask) +{ + int err; + struct p9_client *clnt; + struct p9_stat_dotl *ret = kmalloc(sizeof(struct p9_stat_dotl), + GFP_KERNEL); + struct p9_req_t *req; + + P9_DPRINTK(P9_DEBUG_9P, ">>> TGETATTR fid %d, request_mask %lld\n", + fid->fid, request_mask); + + if (!ret) + return ERR_PTR(-ENOMEM); + + err = 0; + clnt = fid->clnt; + + req = p9_client_rpc(clnt, P9_TGETATTR, "dq", fid->fid, request_mask); + if (IS_ERR(req)) { + err = PTR_ERR(req); + goto error; + } + + err = p9pdu_readf(req->rc, clnt->proto_version, "A", ret); + if (err) { + p9pdu_dump(1, req->rc); + p9_free_req(clnt, req); + goto error; + } + + P9_DPRINTK(P9_DEBUG_9P, + "<<< RGETATTR st_result_mask=%lld\n" + "<<< qid=%x.%llx.%x\n" + "<<< st_mode=%8.8x st_nlink=%llu\n" + "<<< st_uid=%d st_gid=%d\n" + "<<< st_rdev=%llx st_size=%llx st_blksize=%llu st_blocks=%llu\n" + "<<< st_atime_sec=%lld st_atime_nsec=%lld\n" + "<<< st_mtime_sec=%lld st_mtime_nsec=%lld\n" + "<<< st_ctime_sec=%lld st_ctime_nsec=%lld\n" + "<<< st_btime_sec=%lld st_btime_nsec=%lld\n" + "<<< st_gen=%lld st_data_version=%lld", + ret->st_result_mask, ret->qid.type, ret->qid.path, + ret->qid.version, ret->st_mode, ret->st_nlink, ret->st_uid, + ret->st_gid, ret->st_rdev, ret->st_size, ret->st_blksize, + ret->st_blocks, ret->st_atime_sec, ret->st_atime_nsec, + ret->st_mtime_sec, ret->st_mtime_nsec, ret->st_ctime_sec, + ret->st_ctime_nsec, ret->st_btime_sec, ret->st_btime_nsec, + ret->st_gen, ret->st_data_version); + + p9_free_req(clnt, req); + return ret; + +error: + kfree(ret); + return ERR_PTR(err); +} +EXPORT_SYMBOL(p9_client_getattr_dotl); + static int p9_client_statsize(struct p9_wstat *wst, int proto_version) { int ret; @@ -1366,6 +1525,36 @@ error: } EXPORT_SYMBOL(p9_client_wstat); +int p9_client_setattr(struct p9_fid *fid, struct p9_iattr_dotl *p9attr) +{ + int err; + struct p9_req_t *req; + struct p9_client *clnt; + + err = 0; + clnt = fid->clnt; + P9_DPRINTK(P9_DEBUG_9P, ">>> TSETATTR fid %d\n", fid->fid); + P9_DPRINTK(P9_DEBUG_9P, + " valid=%x mode=%x uid=%d gid=%d size=%lld\n" + " atime_sec=%lld atime_nsec=%lld\n" + " mtime_sec=%lld mtime_nsec=%lld\n", + p9attr->valid, p9attr->mode, p9attr->uid, p9attr->gid, + p9attr->size, p9attr->atime_sec, p9attr->atime_nsec, + p9attr->mtime_sec, p9attr->mtime_nsec); + + req = p9_client_rpc(clnt, P9_TSETATTR, "dI", fid->fid, p9attr); + + if (IS_ERR(req)) { + err = PTR_ERR(req); + goto error; + } + P9_DPRINTK(P9_DEBUG_9P, "<<< RSETATTR fid %d\n", fid->fid); + p9_free_req(clnt, req); +error: + return err; +} +EXPORT_SYMBOL(p9_client_setattr); + int p9_client_statfs(struct p9_fid *fid, struct p9_rstatfs *sb) { int err; @@ -1432,3 +1621,187 @@ error: } EXPORT_SYMBOL(p9_client_rename); +/* + * An xattrwalk without @attr_name gives the fid for the lisxattr namespace + */ +struct p9_fid *p9_client_xattrwalk(struct p9_fid *file_fid, + const char *attr_name, u64 *attr_size) +{ + int err; + struct p9_req_t *req; + struct p9_client *clnt; + struct p9_fid *attr_fid; + + err = 0; + clnt = file_fid->clnt; + attr_fid = p9_fid_create(clnt); + if (IS_ERR(attr_fid)) { + err = PTR_ERR(attr_fid); + attr_fid = NULL; + goto error; + } + P9_DPRINTK(P9_DEBUG_9P, + ">>> TXATTRWALK file_fid %d, attr_fid %d name %s\n", + file_fid->fid, attr_fid->fid, attr_name); + + req = p9_client_rpc(clnt, P9_TXATTRWALK, "dds", + file_fid->fid, attr_fid->fid, attr_name); + if (IS_ERR(req)) { + err = PTR_ERR(req); + goto error; + } + err = p9pdu_readf(req->rc, clnt->proto_version, "q", attr_size); + if (err) { + p9pdu_dump(1, req->rc); + p9_free_req(clnt, req); + goto clunk_fid; + } + p9_free_req(clnt, req); + P9_DPRINTK(P9_DEBUG_9P, "<<< RXATTRWALK fid %d size %llu\n", + attr_fid->fid, *attr_size); + return attr_fid; +clunk_fid: + p9_client_clunk(attr_fid); + attr_fid = NULL; +error: + if (attr_fid && (attr_fid != file_fid)) + p9_fid_destroy(attr_fid); + + return ERR_PTR(err); +} +EXPORT_SYMBOL_GPL(p9_client_xattrwalk); + +int p9_client_xattrcreate(struct p9_fid *fid, const char *name, + u64 attr_size, int flags) +{ + int err; + struct p9_req_t *req; + struct p9_client *clnt; + + P9_DPRINTK(P9_DEBUG_9P, + ">>> TXATTRCREATE fid %d name %s size %lld flag %d\n", + fid->fid, name, (long long)attr_size, flags); + err = 0; + clnt = fid->clnt; + req = p9_client_rpc(clnt, P9_TXATTRCREATE, "dsqd", + fid->fid, name, attr_size, flags); + if (IS_ERR(req)) { + err = PTR_ERR(req); + goto error; + } + P9_DPRINTK(P9_DEBUG_9P, "<<< RXATTRCREATE fid %d\n", fid->fid); + p9_free_req(clnt, req); +error: + return err; +} +EXPORT_SYMBOL_GPL(p9_client_xattrcreate); + +int p9_client_readdir(struct p9_fid *fid, char *data, u32 count, u64 offset) +{ + int err, rsize, total; + struct p9_client *clnt; + struct p9_req_t *req; + char *dataptr; + + P9_DPRINTK(P9_DEBUG_9P, ">>> TREADDIR fid %d offset %llu count %d\n", + fid->fid, (long long unsigned) offset, count); + + err = 0; + clnt = fid->clnt; + total = 0; + + rsize = fid->iounit; + if (!rsize || rsize > clnt->msize-P9_READDIRHDRSZ) + rsize = clnt->msize - P9_READDIRHDRSZ; + + if (count < rsize) + rsize = count; + + req = p9_client_rpc(clnt, P9_TREADDIR, "dqd", fid->fid, offset, rsize); + if (IS_ERR(req)) { + err = PTR_ERR(req); + goto error; + } + + err = p9pdu_readf(req->rc, clnt->proto_version, "D", &count, &dataptr); + if (err) { + p9pdu_dump(1, req->rc); + goto free_and_error; + } + + P9_DPRINTK(P9_DEBUG_9P, "<<< RREADDIR count %d\n", count); + + if (data) + memmove(data, dataptr, count); + + p9_free_req(clnt, req); + return count; + +free_and_error: + p9_free_req(clnt, req); +error: + return err; +} +EXPORT_SYMBOL(p9_client_readdir); + +int p9_client_mknod_dotl(struct p9_fid *fid, char *name, int mode, + dev_t rdev, gid_t gid, struct p9_qid *qid) +{ + int err; + struct p9_client *clnt; + struct p9_req_t *req; + + err = 0; + clnt = fid->clnt; + P9_DPRINTK(P9_DEBUG_9P, ">>> TMKNOD fid %d name %s mode %d major %d " + "minor %d\n", fid->fid, name, mode, MAJOR(rdev), MINOR(rdev)); + req = p9_client_rpc(clnt, P9_TMKNOD, "dsdddd", fid->fid, name, mode, + MAJOR(rdev), MINOR(rdev), gid); + if (IS_ERR(req)) + return PTR_ERR(req); + + err = p9pdu_readf(req->rc, clnt->proto_version, "Q", qid); + if (err) { + p9pdu_dump(1, req->rc); + goto error; + } + P9_DPRINTK(P9_DEBUG_9P, "<<< RMKNOD qid %x.%llx.%x\n", qid->type, + (unsigned long long)qid->path, qid->version); + +error: + p9_free_req(clnt, req); + return err; + +} +EXPORT_SYMBOL(p9_client_mknod_dotl); + +int p9_client_mkdir_dotl(struct p9_fid *fid, char *name, int mode, + gid_t gid, struct p9_qid *qid) +{ + int err; + struct p9_client *clnt; + struct p9_req_t *req; + + err = 0; + clnt = fid->clnt; + P9_DPRINTK(P9_DEBUG_9P, ">>> TMKDIR fid %d name %s mode %d gid %d\n", + fid->fid, name, mode, gid); + req = p9_client_rpc(clnt, P9_TMKDIR, "dsdd", fid->fid, name, mode, + gid); + if (IS_ERR(req)) + return PTR_ERR(req); + + err = p9pdu_readf(req->rc, clnt->proto_version, "Q", qid); + if (err) { + p9pdu_dump(1, req->rc); + goto error; + } + P9_DPRINTK(P9_DEBUG_9P, "<<< RMKDIR qid %x.%llx.%x\n", qid->type, + (unsigned long long)qid->path, qid->version); + +error: + p9_free_req(clnt, req); + return err; + +} +EXPORT_SYMBOL(p9_client_mkdir_dotl); diff --git a/net/9p/protocol.c b/net/9p/protocol.c index 149f82160130..3acd3afb20c8 100644 --- a/net/9p/protocol.c +++ b/net/9p/protocol.c @@ -141,6 +141,7 @@ pdu_write_u(struct p9_fcall *pdu, const char __user *udata, size_t size) D - data blob (int32_t size followed by void *, results are not freed) T - array of strings (int16_t count, followed by strings) R - array of qids (int16_t count, followed by qids) + A - stat for 9p2000.L (p9_stat_dotl) ? - if optional = 1, continue parsing */ @@ -340,6 +341,33 @@ p9pdu_vreadf(struct p9_fcall *pdu, int proto_version, const char *fmt, } } break; + case 'A': { + struct p9_stat_dotl *stbuf = + va_arg(ap, struct p9_stat_dotl *); + + memset(stbuf, 0, sizeof(struct p9_stat_dotl)); + errcode = + p9pdu_readf(pdu, proto_version, + "qQdddqqqqqqqqqqqqqqq", + &stbuf->st_result_mask, + &stbuf->qid, + &stbuf->st_mode, + &stbuf->st_uid, &stbuf->st_gid, + &stbuf->st_nlink, + &stbuf->st_rdev, &stbuf->st_size, + &stbuf->st_blksize, &stbuf->st_blocks, + &stbuf->st_atime_sec, + &stbuf->st_atime_nsec, + &stbuf->st_mtime_sec, + &stbuf->st_mtime_nsec, + &stbuf->st_ctime_sec, + &stbuf->st_ctime_nsec, + &stbuf->st_btime_sec, + &stbuf->st_btime_nsec, + &stbuf->st_gen, + &stbuf->st_data_version); + } + break; case '?': if ((proto_version != p9_proto_2000u) && (proto_version != p9_proto_2000L)) @@ -488,6 +516,23 @@ p9pdu_vwritef(struct p9_fcall *pdu, int proto_version, const char *fmt, } } break; + case 'I':{ + struct p9_iattr_dotl *p9attr = va_arg(ap, + struct p9_iattr_dotl *); + + errcode = p9pdu_writef(pdu, proto_version, + "ddddqqqqq", + p9attr->valid, + p9attr->mode, + p9attr->uid, + p9attr->gid, + p9attr->size, + p9attr->atime_sec, + p9attr->atime_nsec, + p9attr->mtime_sec, + p9attr->mtime_nsec); + } + break; case '?': if ((proto_version != p9_proto_2000u) && (proto_version != p9_proto_2000L)) @@ -580,3 +625,30 @@ void p9pdu_reset(struct p9_fcall *pdu) pdu->offset = 0; pdu->size = 0; } + +int p9dirent_read(char *buf, int len, struct p9_dirent *dirent, + int proto_version) +{ + struct p9_fcall fake_pdu; + int ret; + char *nameptr; + + fake_pdu.size = len; + fake_pdu.capacity = len; + fake_pdu.sdata = buf; + fake_pdu.offset = 0; + + ret = p9pdu_readf(&fake_pdu, proto_version, "Qqbs", &dirent->qid, + &dirent->d_off, &dirent->d_type, &nameptr); + if (ret) { + P9_DPRINTK(P9_DEBUG_9P, "<<< p9dirent_read failed: %d\n", ret); + p9pdu_dump(1, &fake_pdu); + goto out; + } + + strcpy(dirent->d_name, nameptr); + +out: + return fake_pdu.offset; +} +EXPORT_SYMBOL(p9dirent_read); diff --git a/net/9p/trans_fd.c b/net/9p/trans_fd.c index 98ce9bcb0e15..c85109d809ca 100644 --- a/net/9p/trans_fd.c +++ b/net/9p/trans_fd.c @@ -948,7 +948,7 @@ p9_fd_create_unix(struct p9_client *client, const char *addr, char *args) csocket = NULL; - if (strlen(addr) > UNIX_PATH_MAX) { + if (strlen(addr) >= UNIX_PATH_MAX) { P9_EPRINTK(KERN_ERR, "p9_trans_unix: address too long: %s\n", addr); return -ENAMETOOLONG; diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c index 86067ee78632..2fc53961054e 100644 --- a/sound/pci/hda/patch_hdmi.c +++ b/sound/pci/hda/patch_hdmi.c @@ -52,6 +52,10 @@ struct hdmi_spec { */ struct hda_multi_out multiout; unsigned int codec_type; + + /* misc flags */ + /* PD bit indicates only the update, not the current state */ + unsigned int old_pin_detect:1; }; @@ -616,6 +620,9 @@ static void hdmi_setup_audio_infoframe(struct hda_codec *codec, hda_nid_t nid, * Unsolicited events */ +static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid, + struct hdmi_eld *eld); + static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) { struct hdmi_spec *spec = codec->spec; @@ -632,6 +639,12 @@ static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) if (index < 0) return; + if (spec->old_pin_detect) { + if (pind) + hdmi_present_sense(codec, tag, &spec->sink_eld[index]); + pind = spec->sink_eld[index].monitor_present; + } + spec->sink_eld[index].monitor_present = pind; spec->sink_eld[index].eld_valid = eldv; diff --git a/sound/pci/hda/patch_nvhdmi.c b/sound/pci/hda/patch_nvhdmi.c index 3c10c0b149f4..b0652acee9b2 100644 --- a/sound/pci/hda/patch_nvhdmi.c +++ b/sound/pci/hda/patch_nvhdmi.c @@ -478,6 +478,7 @@ static int patch_nvhdmi_8ch_89(struct hda_codec *codec) codec->spec = spec; spec->codec_type = HDA_CODEC_NVIDIA_MCP89; + spec->old_pin_detect = 1; if (hdmi_parse_codec(codec) < 0) { codec->spec = NULL; @@ -508,6 +509,7 @@ static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) spec->multiout.max_channels = 8; spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x; spec->codec_type = HDA_CODEC_NVIDIA_MCP7X; + spec->old_pin_detect = 1; codec->patch_ops = nvhdmi_patch_ops_8ch_7x; @@ -528,6 +530,7 @@ static int patch_nvhdmi_2ch(struct hda_codec *codec) spec->multiout.max_channels = 2; spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x; spec->codec_type = HDA_CODEC_NVIDIA_MCP7X; + spec->old_pin_detect = 1; codec->patch_ops = nvhdmi_patch_ops_2ch; diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index ff614dd824c1..596ea2f12cf6 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -1267,11 +1267,11 @@ static int alc_auto_parse_customize_define(struct hda_codec *codec) unsigned nid = 0; struct alc_spec *spec = codec->spec; + spec->cdefine.enable_pcbeep = 1; /* assume always enabled */ + ass = codec->subsystem_id & 0xffff; - if (ass != codec->bus->pci->subsystem_device && (ass & 1)) { - spec->cdefine.enable_pcbeep = 1; /* assume always enabled */ + if (ass != codec->bus->pci->subsystem_device && (ass & 1)) goto do_sku; - } nid = 0x1d; if (codec->vendor_id == 0x10ec0260) @@ -5180,8 +5180,24 @@ static void fillup_priv_adc_nids(struct hda_codec *codec, hda_nid_t *nids, #ifdef CONFIG_SND_HDA_INPUT_BEEP #define set_beep_amp(spec, nid, idx, dir) \ ((spec)->beep_amp = HDA_COMPOSE_AMP_VAL(nid, 3, idx, dir)) + +static struct snd_pci_quirk beep_white_list[] = { + SND_PCI_QUIRK(0x1043, 0x829f, "ASUS", 1), + {} +}; + +static inline int has_cdefine_beep(struct hda_codec *codec) +{ + struct alc_spec *spec = codec->spec; + const struct snd_pci_quirk *q; + q = snd_pci_quirk_lookup(codec->bus->pci, beep_white_list); + if (q) + return q->value; + return spec->cdefine.enable_pcbeep; +} #else #define set_beep_amp(spec, nid, idx, dir) /* NOP */ +#define has_cdefine_beep(codec) 0 #endif /* @@ -10566,10 +10582,12 @@ static int patch_alc882(struct hda_codec *codec) } } - err = snd_hda_attach_beep_device(codec, 0x1); - if (err < 0) { - alc_free(codec); - return err; + if (has_cdefine_beep(codec)) { + err = snd_hda_attach_beep_device(codec, 0x1); + if (err < 0) { + alc_free(codec); + return err; + } } if (board_config != ALC882_AUTO) @@ -10619,7 +10637,7 @@ static int patch_alc882(struct hda_codec *codec) set_capture_mixer(codec); - if (spec->cdefine.enable_pcbeep) + if (has_cdefine_beep(codec)) set_beep_amp(spec, 0x0b, 0x05, HDA_INPUT); if (board_config == ALC882_AUTO) @@ -12435,7 +12453,7 @@ static int patch_alc262(struct hda_codec *codec) } } - if (!spec->no_analog) { + if (!spec->no_analog && has_cdefine_beep(codec)) { err = snd_hda_attach_beep_device(codec, 0x1); if (err < 0) { alc_free(codec); @@ -12486,7 +12504,7 @@ static int patch_alc262(struct hda_codec *codec) } if (!spec->cap_mixer && !spec->no_analog) set_capture_mixer(codec); - if (!spec->no_analog && spec->cdefine.enable_pcbeep) + if (!spec->no_analog && has_cdefine_beep(codec)) set_beep_amp(spec, 0x0b, 0x05, HDA_INPUT); spec->vmaster_nid = 0x0c; @@ -14458,10 +14476,12 @@ static int patch_alc269(struct hda_codec *codec) } } - err = snd_hda_attach_beep_device(codec, 0x1); - if (err < 0) { - alc_free(codec); - return err; + if (has_cdefine_beep(codec)) { + err = snd_hda_attach_beep_device(codec, 0x1); + if (err < 0) { + alc_free(codec); + return err; + } } if (board_config != ALC269_AUTO) @@ -14494,7 +14514,7 @@ static int patch_alc269(struct hda_codec *codec) if (!spec->cap_mixer) set_capture_mixer(codec); - if (spec->cdefine.enable_pcbeep) + if (has_cdefine_beep(codec)) set_beep_amp(spec, 0x0b, 0x04, HDA_INPUT); if (board_config == ALC269_AUTO) @@ -18691,10 +18711,12 @@ static int patch_alc662(struct hda_codec *codec) } } - err = snd_hda_attach_beep_device(codec, 0x1); - if (err < 0) { - alc_free(codec); - return err; + if (has_cdefine_beep(codec)) { + err = snd_hda_attach_beep_device(codec, 0x1); + if (err < 0) { + alc_free(codec); + return err; + } } if (board_config != ALC662_AUTO) @@ -18716,7 +18738,7 @@ static int patch_alc662(struct hda_codec *codec) if (!spec->cap_mixer) set_capture_mixer(codec); - if (spec->cdefine.enable_pcbeep) { + if (has_cdefine_beep(codec)) { switch (codec->vendor_id) { case 0x10ec0662: set_beep_amp(spec, 0x0b, 0x05, HDA_INPUT); diff --git a/tools/perf/arch/arm/Makefile b/tools/perf/arch/arm/Makefile new file mode 100644 index 000000000000..15130b50dfe3 --- /dev/null +++ b/tools/perf/arch/arm/Makefile @@ -0,0 +1,4 @@ +ifndef NO_DWARF +PERF_HAVE_DWARF_REGS := 1 +LIB_OBJS += $(OUTPUT)arch/$(ARCH)/util/dwarf-regs.o +endif diff --git a/tools/perf/arch/arm/util/dwarf-regs.c b/tools/perf/arch/arm/util/dwarf-regs.c new file mode 100644 index 000000000000..fff6450c8c99 --- /dev/null +++ b/tools/perf/arch/arm/util/dwarf-regs.c @@ -0,0 +1,64 @@ +/* + * Mapping of DWARF debug register numbers into register names. + * + * Copyright (C) 2010 Will Deacon, ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <libio.h> +#include <dwarf-regs.h> + +struct pt_regs_dwarfnum { + const char *name; + unsigned int dwarfnum; +}; + +#define STR(s) #s +#define REG_DWARFNUM_NAME(r, num) {.name = r, .dwarfnum = num} +#define GPR_DWARFNUM_NAME(num) \ + {.name = STR(%r##num), .dwarfnum = num} +#define REG_DWARFNUM_END {.name = NULL, .dwarfnum = 0} + +/* + * Reference: + * http://infocenter.arm.com/help/topic/com.arm.doc.ihi0040a/IHI0040A_aadwarf.pdf + */ +static const struct pt_regs_dwarfnum regdwarfnum_table[] = { + GPR_DWARFNUM_NAME(0), + GPR_DWARFNUM_NAME(1), + GPR_DWARFNUM_NAME(2), + GPR_DWARFNUM_NAME(3), + GPR_DWARFNUM_NAME(4), + GPR_DWARFNUM_NAME(5), + GPR_DWARFNUM_NAME(6), + GPR_DWARFNUM_NAME(7), + GPR_DWARFNUM_NAME(8), + GPR_DWARFNUM_NAME(9), + GPR_DWARFNUM_NAME(10), + REG_DWARFNUM_NAME("%fp", 11), + REG_DWARFNUM_NAME("%ip", 12), + REG_DWARFNUM_NAME("%sp", 13), + REG_DWARFNUM_NAME("%lr", 14), + REG_DWARFNUM_NAME("%pc", 15), + REG_DWARFNUM_END, +}; + +/** + * get_arch_regstr() - lookup register name from it's DWARF register number + * @n: the DWARF register number + * + * get_arch_regstr() returns the name of the register in struct + * regdwarfnum_table from it's DWARF register number. If the register is not + * found in the table, this returns NULL; + */ +const char *get_arch_regstr(unsigned int n) +{ + const struct pt_regs_dwarfnum *roff; + for (roff = regdwarfnum_table; roff->name != NULL; roff++) + if (roff->dwarfnum == n) + return roff->name; + return NULL; +} |
