diff options
| -rw-r--r-- | drivers/watchdog/davinci_wdt.c | 45 |
1 files changed, 25 insertions, 20 deletions
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c index 2e1360286732..c51d0b0ea0c4 100644 --- a/drivers/watchdog/davinci_wdt.c +++ b/drivers/watchdog/davinci_wdt.c @@ -24,7 +24,7 @@ #include <linux/spinlock.h> #include <linux/uaccess.h> #include <linux/io.h> -#include <mach/hardware.h> +#include <linux/device.h> #define MODULE_NAME "DAVINCI-WDT: " @@ -75,9 +75,9 @@ static void wdt_service(void) spin_lock(&io_lock); /* put watchdog in service state */ - davinci_writel(WDKEY_SEQ0, wdt_base + WDTCR); + iowrite32(WDKEY_SEQ0, wdt_base + WDTCR); /* put watchdog in active state */ - davinci_writel(WDKEY_SEQ1, wdt_base + WDTCR); + iowrite32(WDKEY_SEQ1, wdt_base + WDTCR); spin_unlock(&io_lock); } @@ -90,29 +90,29 @@ static void wdt_enable(void) spin_lock(&io_lock); /* disable, internal clock source */ - davinci_writel(0, wdt_base + TCR); + iowrite32(0, wdt_base + TCR); /* reset timer, set mode to 64-bit watchdog, and unreset */ - davinci_writel(0, wdt_base + TGCR); + iowrite32(0, wdt_base + TGCR); tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET; - davinci_writel(tgcr, wdt_base + TGCR); + iowrite32(tgcr, wdt_base + TGCR); /* clear counter regs */ - davinci_writel(0, wdt_base + TIM12); - davinci_writel(0, wdt_base + TIM34); + iowrite32(0, wdt_base + TIM12); + iowrite32(0, wdt_base + TIM34); /* set timeout period */ timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) & 0xffffffff); - davinci_writel(timer_margin, wdt_base + PRD12); + iowrite32(timer_margin, wdt_base + PRD12); timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) >> 32); - davinci_writel(timer_margin, wdt_base + PRD34); + iowrite32(timer_margin, wdt_base + PRD34); /* enable run continuously */ - davinci_writel(ENAMODE12_PERIODIC, wdt_base + TCR); + iowrite32(ENAMODE12_PERIODIC, wdt_base + TCR); /* Once the WDT is in pre-active state write to * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are * write protected (except for the WDKEY field) */ /* put watchdog in pre-active state */ - davinci_writel(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR); + iowrite32(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR); /* put watchdog in active state */ - davinci_writel(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR); + iowrite32(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR); spin_unlock(&io_lock); } @@ -197,17 +197,16 @@ static int davinci_wdt_probe(struct platform_device *pdev) { int ret = 0, size; struct resource *res; + struct device *dev = &pdev->dev; if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT) heartbeat = DEFAULT_HEARTBEAT; - printk(KERN_INFO MODULE_NAME - "DaVinci Watchdog Timer: heartbeat %d sec\n", heartbeat); + dev_info(dev, "heartbeat %d sec\n", heartbeat); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res == NULL) { - printk(KERN_INFO MODULE_NAME - "failed to get memory region resource\n"); + dev_err(dev, "failed to get memory region resource\n"); return -ENOENT; } @@ -215,20 +214,26 @@ static int davinci_wdt_probe(struct platform_device *pdev) wdt_mem = request_mem_region(res->start, size, pdev->name); if (wdt_mem == NULL) { - printk(KERN_INFO MODULE_NAME "failed to get memory region\n"); + dev_err(dev, "failed to get memory region\n"); return -ENOENT; } - wdt_base = (void __iomem *)(res->start); + + wdt_base = ioremap(res->start, size); + if (!wdt_base) { + dev_err(dev, "failed to map memory region\n"); + return -ENOMEM; + } ret = misc_register(&davinci_wdt_miscdev); if (ret < 0) { - printk(KERN_ERR MODULE_NAME "cannot register misc device\n"); + dev_err(dev, "cannot register misc device\n"); release_resource(wdt_mem); kfree(wdt_mem); } else { set_bit(WDT_DEVICE_INITED, &wdt_status); } + iounmap(wdt_base); return ret; } |
