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authorJesse Barnes <jbarnes@virtuousgeek.org>2010-04-21 11:39:23 -0700
committerEric Anholt <eric@anholt.net>2010-04-22 14:48:55 -0700
commite552eb7038a36d9b18860f525aa02875e313fe16 (patch)
treebcbab5ec16994d6747794bab8f4bc38780f0157f /usr/Makefile
parent20bf377e679208ba9ae0edcb8c70a8f6d33d17f9 (diff)
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drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge
Since 965, the hardware has supported the PIPE_CONTROL command, which provides fine grained GPU cache flushing control. On recent chipsets, this instruction is required for reliable interrupt and sequence number reporting in the driver. So add support for this instruction, including workarounds, on Ironlake and Sandy Bridge hardware. https://bugs.freedesktop.org/show_bug.cgi?id=27108 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
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