summaryrefslogtreecommitdiffstats
path: root/sound/soc/pxa
diff options
context:
space:
mode:
authorMark Brown <broonie@opensource.wolfsonmicro.com>2009-03-13 14:26:08 +0000
committerMark Brown <broonie@opensource.wolfsonmicro.com>2009-03-14 11:37:46 +0000
commit0ce36c5f7f87632f26c8fbefe68b5116eda152d2 (patch)
tree16c74e694d5b8f418c0384c8079bbc9a8c2689aa /sound/soc/pxa
parent72d7466468b471f99cefae3c5f4a414bbbaa0bdd (diff)
downloadblackbird-op-linux-0ce36c5f7f87632f26c8fbefe68b5116eda152d2.tar.gz
blackbird-op-linux-0ce36c5f7f87632f26c8fbefe68b5116eda152d2.zip
ASoC: Fix non-networked I2S mode for PXA SSP
Two issues are fixed here: - I2S transmits the left frame with the clock low but I don't seem to get LRCLK out without SFRMDLY being set so invert SFRMP and set a delay. - I2S has a clock cycle prior to the first data byte in each channel so we need to delay the data by one cycle. Tested-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/pxa')
-rw-r--r--sound/soc/pxa/pxa-ssp.c19
1 files changed, 14 insertions, 5 deletions
diff --git a/sound/soc/pxa/pxa-ssp.c b/sound/soc/pxa/pxa-ssp.c
index 4dd0d7c57220..b0bf40973d5b 100644
--- a/sound/soc/pxa/pxa-ssp.c
+++ b/sound/soc/pxa/pxa-ssp.c
@@ -1,4 +1,3 @@
-#define DEBUG
/*
* pxa-ssp.c -- ALSA Soc Audio Layer
*
@@ -561,14 +560,15 @@ static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
sscr0 |= SSCR0_PSP;
sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
+ /* See hw_params() */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
+ sspsp |= SSPSP_SFRMP;
break;
case SND_SOC_DAIFMT_NB_IF:
- sspsp |= SSPSP_SFRMP;
break;
case SND_SOC_DAIFMT_IB_IF:
- sspsp |= SSPSP_SFRMP | SSPSP_SCMODE(3);
+ sspsp |= SSPSP_SCMODE(3);
break;
default:
return -EINVAL;
@@ -691,8 +691,17 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
#else
return -EINVAL;
#endif
- } else
- sspsp |= SSPSP_SFRMWDTH(width);
+ } else {
+ /* The frame width is the width the LRCLK is
+ * asserted for; the delay is expressed in
+ * half cycle units. We need the extra cycle
+ * because the data starts clocking out one BCLK
+ * after LRCLK changes polarity.
+ */
+ sspsp |= SSPSP_SFRMWDTH(width + 1);
+ sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
+ sspsp |= SSPSP_DMYSTRT(1);
+ }
ssp_write_reg(ssp, SSPSP, sspsp);
break;
OpenPOWER on IntegriCloud