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authorRob Clark <robdclark@gmail.com>2014-06-25 09:54:36 -0400
committerRob Clark <robdclark@gmail.com>2014-08-04 11:55:28 -0400
commit034fbcc3d8a5dff5d3df5a4ad6bf9cc0b01bd970 (patch)
tree9c27803c6c44f446ed71680fb058927bbc08dd98 /lib/build_OID_registry
parent89301471e6bf942c026d6ebfcbc9a6a937cc6865 (diff)
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drm/msm: hdmi phy 8960 phy pll
On downstream kernel the clk driver directly bangs hdmi phy registers. For upstream kernel, we need to model this as a clock and register with the clock framework. Signed-off-by: Rob Clark <robdclark@gmail.com>
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