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authorPrashant Gaikwad <pgaikwad@nvidia.com>2013-03-20 17:30:34 +0530
committerMike Turquette <mturquette@linaro.org>2013-03-26 12:51:48 -0700
commitece70094f6ab2107d4313fa1802b13dab0234ac5 (patch)
tree0e864397c7e15afe1c3d94d028945187b32d723f /include/linux/clk-provider.h
parentce4f3313b05c836c21a91ac89f87dccf84ce9561 (diff)
downloadblackbird-op-linux-ece70094f6ab2107d4313fa1802b13dab0234ac5.tar.gz
blackbird-op-linux-ece70094f6ab2107d4313fa1802b13dab0234ac5.zip
clk: Add composite clock type
Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'include/linux/clk-provider.h')
-rw-r--r--include/linux/clk-provider.h31
1 files changed, 31 insertions, 0 deletions
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 63ba3b740794..1f0352802794 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -342,6 +342,37 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div);
+/***
+ * struct clk_composite - aggregate clock of mux, divider and gate clocks
+ *
+ * @hw: handle between common and hardware-specific interfaces
+ * @mux_hw: handle between composite and hardware-specifix mux clock
+ * @div_hw: handle between composite and hardware-specifix divider clock
+ * @gate_hw: handle between composite and hardware-specifix gate clock
+ * @mux_ops: clock ops for mux
+ * @div_ops: clock ops for divider
+ * @gate_ops: clock ops for gate
+ */
+struct clk_composite {
+ struct clk_hw hw;
+ struct clk_ops ops;
+
+ struct clk_hw *mux_hw;
+ struct clk_hw *div_hw;
+ struct clk_hw *gate_hw;
+
+ const struct clk_ops *mux_ops;
+ const struct clk_ops *div_ops;
+ const struct clk_ops *gate_ops;
+};
+
+struct clk *clk_register_composite(struct device *dev, const char *name,
+ const char **parent_names, int num_parents,
+ struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
+ struct clk_hw *div_hw, const struct clk_ops *div_ops,
+ struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
+ unsigned long flags);
+
/**
* clk_register - allocate a new clock, register it and return an opaque cookie
* @dev: device that is registering this clock
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