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authorAlim Akhtar <alim.akhtar@samsung.com>2015-09-10 14:14:37 +0530
committerSylwester Nawrocki <s.nawrocki@samsung.com>2015-09-15 11:18:15 +0200
commit7993b3ebec979b23c2d7425959c9d232c452498b (patch)
treed7e25a28d5073a2f55e86dad1c99a4ecd8b94870 /include/dt-bindings/clock/exynos7-clk.h
parentad108e10ae3ce6bc68eb89e788296a3c40801482 (diff)
downloadblackbird-op-linux-7993b3ebec979b23c2d7425959c9d232c452498b.tar.gz
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clk: samsung: exynos7: Add required clock tree for UFS
Adding required mux/div/gate clocks for UFS controller present on Exynos7. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'include/dt-bindings/clock/exynos7-clk.h')
-rw-r--r--include/dt-bindings/clock/exynos7-clk.h24
1 files changed, 22 insertions, 2 deletions
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index acdf2e5e1ac0..10c558611085 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -64,7 +64,14 @@
#define CLK_SCLK_MMC0 8
#define CLK_ACLK_FSYS0_200 9
#define CLK_ACLK_FSYS1_200 10
-#define TOP1_NR_CLK 11
+#define CLK_SCLK_PHY_FSYS1 11
+#define CLK_SCLK_PHY_FSYS1_26M 12
+#define MOUT_SCLK_UFSUNIPRO20 13
+#define DOUT_SCLK_UFSUNIPRO20 14
+#define CLK_SCLK_UFSUNIPRO20 15
+#define DOUT_SCLK_PHY_FSYS1 16
+#define DOUT_SCLK_PHY_FSYS1_26M 17
+#define TOP1_NR_CLK 18
/* CCORE */
#define PCLK_RTC 1
@@ -139,7 +146,20 @@
/* FSYS1 */
#define ACLK_MMC1 1
#define ACLK_MMC0 2
-#define FSYS1_NR_CLK 3
+#define PHYCLK_UFS20_TX0_SYMBOL 3
+#define PHYCLK_UFS20_RX0_SYMBOL 4
+#define PHYCLK_UFS20_RX1_SYMBOL 5
+#define ACLK_UFS20_LINK 6
+#define SCLK_UFSUNIPRO20_USER 7
+#define PHYCLK_UFS20_RX1_SYMBOL_USER 8
+#define PHYCLK_UFS20_RX0_SYMBOL_USER 9
+#define PHYCLK_UFS20_TX0_SYMBOL_USER 10
+#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11
+#define SCLK_COMBO_PHY_EMBEDDED_26M 12
+#define DOUT_PCLK_FSYS1 13
+#define PCLK_GPIO_FSYS1 14
+#define MOUT_FSYS1_PHYCLK_SEL1 15
+#define FSYS1_NR_CLK 16
/* MSCL */
#define USERMUX_ACLK_MSCL_532 1
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