summaryrefslogtreecommitdiffstats
path: root/include/asm-x86/processor.h
diff options
context:
space:
mode:
authorIngo Molnar <mingo@elte.hu>2008-09-05 17:53:05 +0200
committerIngo Molnar <mingo@elte.hu>2008-09-05 17:53:05 +0200
commit28c3cfd5fb998bd3683bebeebbba38baa2101cad (patch)
tree3d325023e6dc56baa6c69fc59dd55bf37ef7967e /include/asm-x86/processor.h
parent04197c83b3e05546d1003cfa3ff43f1639c0057f (diff)
parentb380b0d4f7dffcc235c0facefa537d4655619101 (diff)
downloadblackbird-op-linux-28c3cfd5fb998bd3683bebeebbba38baa2101cad.tar.gz
blackbird-op-linux-28c3cfd5fb998bd3683bebeebbba38baa2101cad.zip
Merge branch 'linus' into x86/tracehook
Diffstat (limited to 'include/asm-x86/processor.h')
-rw-r--r--include/asm-x86/processor.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index 5f58da401b43..4df3e2f6fb56 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -728,6 +728,29 @@ extern unsigned long boot_option_idle_override;
extern unsigned long idle_halt;
extern unsigned long idle_nomwait;
+/*
+ * on systems with caches, caches must be flashed as the absolute
+ * last instruction before going into a suspended halt. Otherwise,
+ * dirty data can linger in the cache and become stale on resume,
+ * leading to strange errors.
+ *
+ * perform a variety of operations to guarantee that the compiler
+ * will not reorder instructions. wbinvd itself is serializing
+ * so the processor will not reorder.
+ *
+ * Systems without cache can just go into halt.
+ */
+static inline void wbinvd_halt(void)
+{
+ mb();
+ /* check for clflush to determine if wbinvd is legal */
+ if (cpu_has_clflush)
+ asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
+ else
+ while (1)
+ halt();
+}
+
extern void enable_sep_cpu(void);
extern int sysenter_setup(void);
OpenPOWER on IntegriCloud