summaryrefslogtreecommitdiffstats
path: root/include/asm-sh/irq.h
diff options
context:
space:
mode:
authorJamie Lenehan <lenehan@twibble.org>2006-12-06 12:05:02 +0900
committerPaul Mundt <lethal@linux-sh.org>2006-12-06 12:05:02 +0900
commitea0f8feaa041f3ccec3d6b8ee51325b177daef06 (patch)
tree261c7d75e5caccbaface63370bae029ecd81b98a /include/asm-sh/irq.h
parentfe9687dec0400c6de7187ab5efa91facd958ca84 (diff)
downloadblackbird-op-linux-ea0f8feaa041f3ccec3d6b8ee51325b177daef06.tar.gz
blackbird-op-linux-ea0f8feaa041f3ccec3d6b8ee51325b177daef06.zip
sh: sh775x/titan fixes for irq header changes.
The following moves the creation of IPR interupts into setup-7750.c and updates a few other things to make it all work after the "Drop CPU subtype IRQ headers" commit. It boots and runs fine on my titan board. - adds an ipr_idx to the ipr_data and uses a function in the subtype code to calculate the address of the IPR registers - adds a function to enable individual interrupt mode for externals in the subtype code and calls that from the titan board code instead of doing it directly. - I changed the shift in the ipr_data to be the actual # of bits to shift, instead of the numnber / 4 - made it easier to match with the manual. Signed-off-by: Jamie Lenehan <lenehan@twibble.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/irq.h')
-rw-r--r--include/asm-sh/irq.h32
1 files changed, 28 insertions, 4 deletions
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index f10cfc10227e..fd576088e47e 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -93,6 +93,12 @@
#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
/*
+ * Convert back and forth between INTEVT and IRQ values.
+ */
+#define evt2irq(evt) (((evt) >> 5) - 16)
+#define irq2evt(irq) (((irq) + 16) << 5)
+
+/*
* Simple Mask Register Support
*/
extern void make_maskreg_irq(unsigned int irq);
@@ -103,18 +109,36 @@ extern unsigned short *irq_mask_register;
*/
void init_IRQ_pint(void);
+/*
+ * The shift value is now the number of bits to shift, not the number of
+ * bits/4. This is to make it easier to read the value directly from the
+ * datasheets. The IPR address, addr, will be set from ipr_idx via the
+ * map_ipridx_to_addr function.
+ */
struct ipr_data {
unsigned int irq;
- unsigned int addr; /* Address of Interrupt Priority Register */
- int shift; /* Shifts of the 16-bit data */
+ int ipr_idx; /* Index for the IPR registered */
+ int shift; /* Number of bits to shift the data */
int priority; /* The priority */
+ unsigned int addr; /* Address of Interrupt Priority Register */
};
/*
+ * Given an IPR IDX, map the value to an IPR register address.
+ */
+unsigned int map_ipridx_to_addr(int idx);
+
+/*
+ * Enable individual interrupt mode for external IPR IRQs.
+ */
+void ipr_irq_enable_irlm(void);
+
+/*
* Function for "on chip support modules".
*/
-extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
-extern void make_imask_irq(unsigned int irq);
+void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
+void make_imask_irq(unsigned int irq);
+void init_IRQ_ipr(void);
struct intc2_data {
unsigned short irq;
OpenPOWER on IntegriCloud