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| author | Grant Grundler <grundler@parisc-linux.org> | 2005-10-21 22:40:07 -0400 |
|---|---|---|
| committer | Kyle McMartin <kyle@parisc-linux.org> | 2005-10-21 22:40:07 -0400 |
| commit | 896a375623c3643a3f189353e7d4828c48a7fdf8 (patch) | |
| tree | bb79535f843110f9b2b199890157fcabb0504b43 /include/asm-parisc/assembly.h | |
| parent | b2c1fe81df7471de9f7e2918877ac04ec9cde35f (diff) | |
| download | blackbird-op-linux-896a375623c3643a3f189353e7d4828c48a7fdf8.tar.gz blackbird-op-linux-896a375623c3643a3f189353e7d4828c48a7fdf8.zip | |
[PARISC] Make sure use of RFI conforms to PA 2.0 and 1.1 arch docs
2.6.12-rc4-pa3 : first pass at making sure use of RFI conforms to
PA 2.0 arch pages F-4 and F-5, PA 1.1 Arch page 3-19 and 3-20.
The discussion revolves around all the rules for clearing PSW Q-bit.
The hard part is meeting all the rules for "relied upon translation".
.align directive is used to guarantee the critical sequence ends more than
8 instructions (32 bytes) from the end of page.
Signed-off-by: Grant Grundler <grundler@parisc-linux.org>
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Diffstat (limited to 'include/asm-parisc/assembly.h')
| -rw-r--r-- | include/asm-parisc/assembly.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/include/asm-parisc/assembly.h b/include/asm-parisc/assembly.h index 30b023411fef..b24a99e3ef9c 100644 --- a/include/asm-parisc/assembly.h +++ b/include/asm-parisc/assembly.h @@ -450,5 +450,30 @@ REST_CR (%cr22, PT_PSW (\regs)) .endm + + /* First step to create a "relied upon translation" + * See PA 2.0 Arch. page F-4 and F-5. + * + * The ssm was originally necessary due to a "PCxT bug". + * But someone decided it needed to be added to the architecture + * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual. + * It's been carried forward into PA 2.0 Arch as well. :^( + * + * "ssm 0,%r0" is a NOP with side effects (prefetch barrier). + * rsm/ssm prevents the ifetch unit from speculatively fetching + * instructions past this line in the code stream. + * PA 2.0 processor will single step all insn in the same QUAD (4 insn). + */ + .macro pcxt_ssm_bug + rsm PSW_SM_I,%r0 + nop /* 1 */ + nop /* 2 */ + nop /* 3 */ + nop /* 4 */ + nop /* 5 */ + nop /* 6 */ + nop /* 7 */ + .endm + #endif /* __ASSEMBLY__ */ #endif |
