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| author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 23:46:07 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 23:46:07 +0100 |
| commit | baf22c1e7aedf264e264b15d2595e5e76564bd4e (patch) | |
| tree | 6983687e9e1a7442247d418207bfb36254167214 /include/asm-mips/mach-ip22 | |
| parent | 21c854dcbd7698bf723676a552968040e2813490 (diff) | |
| download | blackbird-op-linux-baf22c1e7aedf264e264b15d2595e5e76564bd4e.tar.gz blackbird-op-linux-baf22c1e7aedf264e264b15d2595e5e76564bd4e.zip | |
[MIPS] Split up war.h
It was getting a little big, ugly and a primary source for merge conflicts.
Also the old method was a bit too forgiving in that the workaround did
default to off, so now there is an explicit #error forcing platform
maintainers to think if they should enable a workaround for a particular
platform.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-ip22')
| -rw-r--r-- | include/asm-mips/mach-ip22/war.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/include/asm-mips/mach-ip22/war.h b/include/asm-mips/mach-ip22/war.h new file mode 100644 index 000000000000..a44fa9656a82 --- /dev/null +++ b/include/asm-mips/mach-ip22/war.h @@ -0,0 +1,29 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_IP22_WAR_H +#define __ASM_MIPS_MACH_IP22_WAR_H + +/* + * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. + */ + +#define R4600_V1_INDEX_ICACHEOP_WAR 1 +#define R4600_V1_HIT_CACHEOP_WAR 1 +#define R4600_V2_HIT_CACHEOP_WAR 1 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_IP22_WAR_H */ |
