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| author | Arnaud Patard <arnaud.patard@rtp-net.org> | 2005-09-09 13:10:07 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-09-09 14:03:42 -0700 |
| commit | 20fd5767689124a920c1deb9c380304e082f026c (patch) | |
| tree | fe779116d39a1612c80f414f0add8ed2893041d9 /include/asm-arm/arch-s3c2410/regs-lcd.h | |
| parent | 3b4abffbadf728996fb9243b4af1df48dd771e86 (diff) | |
| download | blackbird-op-linux-20fd5767689124a920c1deb9c380304e082f026c.tar.gz blackbird-op-linux-20fd5767689124a920c1deb9c380304e082f026c.zip | |
[PATCH] s3c2410fb: ARM S3C2410 framebuffer driver
This set of two patches add support for the framebuffer of the Samsung S3C2410
ARM SoC. This driver was started about one year ago and is now used on iPAQ
h1930/h1940, Acer n30 and probably other s3c2410-based machines I'm not aware
of. I've also heard yesterday that it's working also on iPAQ rx3715/rx3115
(s3c2440-based machines).
Signed-Off-By: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Antonino Daplas <adaplas@pol.net>
Signed-off-by: Ben Dooks <ben@trinity.fluff.org>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-arm/arch-s3c2410/regs-lcd.h')
| -rw-r--r-- | include/asm-arm/arch-s3c2410/regs-lcd.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h index 7f882ea92b2a..b6b1b4e8bbeb 100644 --- a/include/asm-arm/arch-s3c2410/regs-lcd.h +++ b/include/asm-arm/arch-s3c2410/regs-lcd.h @@ -51,21 +51,32 @@ #define S3C2410_LCDCON1_ENVID (1) +#define S3C2410_LCDCON1_MODEMASK 0x1E + #define S3C2410_LCDCON2_VBPD(x) ((x) << 24) #define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) #define S3C2410_LCDCON2_VFPD(x) ((x) << 6) #define S3C2410_LCDCON2_VSPW(x) ((x) << 0) +#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) +#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) +#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) + #define S3C2410_LCDCON3_HBPD(x) ((x) << 19) #define S3C2410_LCDCON3_WDLY(x) ((x) << 19) #define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) #define S3C2410_LCDCON3_HFPD(x) ((x) << 0) #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) +#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) +#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) + #define S3C2410_LCDCON4_MVAL(x) ((x) << 8) #define S3C2410_LCDCON4_HSPW(x) ((x) << 0) #define S3C2410_LCDCON4_WLH(x) ((x) << 0) +#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) + #define S3C2410_LCDCON5_BPP24BL (1<<12) #define S3C2410_LCDCON5_FRM565 (1<<11) #define S3C2410_LCDCON5_INVVCLK (1<<10) @@ -100,10 +111,16 @@ #define S3C2410_DITHMODE S3C2410_LCDREG(0x4C) #define S3C2410_TPAL S3C2410_LCDREG(0x50) +#define S3C2410_TPAL_EN (1<<24) + /* interrupt info */ #define S3C2410_LCDINTPND S3C2410_LCDREG(0x54) #define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58) #define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C) +#define S3C2410_LCDINT_FIWSEL (1<<2) +#define S3C2410_LCDINT_FRSYNC (1<<1) +#define S3C2410_LCDINT_FICNT (1<<0) + #define S3C2410_LPCSEL S3C2410_LCDREG(0x60) #define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) |
