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| author | Deepak Saxena <dsaxena@plexity.net> | 2006-01-05 20:59:29 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-01-05 20:59:29 +0000 |
| commit | 54e269ead6e672325866037b0617a72edd1396b9 (patch) | |
| tree | 3076c2e0187657daed3054d511b62dc33a4c8f8b /include/asm-arm/arch-ixp4xx/coyote.h | |
| parent | 2b9ac7c15c0c5c9d6057b9e297dabaebd208ffe8 (diff) | |
| download | blackbird-op-linux-54e269ead6e672325866037b0617a72edd1396b9.tar.gz blackbird-op-linux-54e269ead6e672325866037b0617a72edd1396b9.zip | |
[ARM] 3226/1: IXP4xx runtime expansion bus window size configuration
Patch from Deepak Saxena
The expansion bus on the IXP46x NPU can be configured for either 32MiB or
16MiB windows and changing the configuration causes the base address for
each chip select for each region to change. Because of this, we cannot
hardcode the physical base as we currently do. This patch checks the
expansion bus configuration registers at runtime to determine the
appropriate window size. Note that this requires that the bootloader
already configured the device sizes appropriately, but I feel that is
valid assumption to make as the bootloader must configure and access
the flash window, the output display (LCD, LEDs, etc) window, and
other expansion bus devices.
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-ixp4xx/coyote.h')
| -rw-r--r-- | include/asm-arm/arch-ixp4xx/coyote.h | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/include/asm-arm/arch-ixp4xx/coyote.h b/include/asm-arm/arch-ixp4xx/coyote.h index dd0c2d2d8503..7ac9ba2c035c 100644 --- a/include/asm-arm/arch-ixp4xx/coyote.h +++ b/include/asm-arm/arch-ixp4xx/coyote.h @@ -16,9 +16,6 @@ #error "Do not include this directly, instead #include <asm/hardware.h>" #endif -#define COYOTE_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS -#define COYOTE_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE * 2 - /* PCI controller GPIO to IRQ pin mappings */ #define COYOTE_PCI_SLOT0_PIN 6 #define COYOTE_PCI_SLOT1_PIN 11 @@ -26,7 +23,7 @@ #define COYOTE_PCI_SLOT0_DEVID 14 #define COYOTE_PCI_SLOT1_DEVID 15 -#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_CS3_BASE_PHYS +#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3) #define COYOTE_IDE_BASE_VIRT 0xFFFE1000 #define COYOTE_IDE_REGION_SIZE 0x1000 |
