diff options
| author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 15:20:36 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 15:20:36 -0700 |
| commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
| tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-arm/arch-iop3xx | |
| download | blackbird-op-linux-1da177e4c3f41524e886b7f1b8a0c1fc7321cac2.tar.gz blackbird-op-linux-1da177e4c3f41524e886b7f1b8a0c1fc7321cac2.zip | |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'include/asm-arm/arch-iop3xx')
20 files changed, 1432 insertions, 0 deletions
diff --git a/include/asm-arm/arch-iop3xx/debug-macro.S b/include/asm-arm/arch-iop3xx/debug-macro.S new file mode 100644 index 000000000000..cc15f80ebd9a --- /dev/null +++ b/include/asm-arm/arch-iop3xx/debug-macro.S @@ -0,0 +1,48 @@ +/* linux/include/asm-arm/arch-iop3xx/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + + .macro addruart,rx + mov \rx, #0xfe000000 @ physical +#if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244) + orr \rx, \rx, #0x00800000 @ location of the UART +#elif defined(CONFIG_ARCH_IOP331) + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x000fe000 @ Physical Base + movne \rx, #0 + orr \rx, \rx, #0xfe000000 + orr \rx, \rx, #0x00f00000 @ Virtual Base + orr \rx, \rx, #0x00001700 @ location of the UART +#else +#error Unknown IOP3XX implementation +#endif + .endm + + .macro senduart,rd,rx + strb \rd, [\rx] + .endm + + .macro busyuart,rd,rx +1002: ldrb \rd, [\rx, #0x5] + and \rd, \rd, #0x60 + teq \rd, #0x60 + bne 1002b + .endm + + .macro waituart,rd,rx +#if !defined(CONFIG_ARCH_IQ80321) || !defined(CONFIG_ARCH_IQ31244) || !defined(CONFIG_ARCH_IQ80331) +1001: ldrb \rd, [\rx, #0x6] + tst \rd, #0x10 + beq 1001b +#endif + .endm diff --git a/include/asm-arm/arch-iop3xx/dma.h b/include/asm-arm/arch-iop3xx/dma.h new file mode 100644 index 000000000000..797f9e6fc745 --- /dev/null +++ b/include/asm-arm/arch-iop3xx/dma.h @@ -0,0 +1,16 @@ +/* + * linux/include/asm-arm/arch-iop3xx/dma.h + * + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _IOP3XX_DMA_H_P +#define _IOP3XX_DMA_H_P + +#define MAX_DMA_ADDRESS 0xffffffff + +#endif /* _ASM_ARCH_DMA_H_P */ diff --git a/include/asm-arm/arch-iop3xx/entry-macro.S b/include/asm-arm/arch-iop3xx/entry-macro.S new file mode 100644 index 000000000000..e2ce7f5467c8 --- /dev/null +++ b/include/asm-arm/arch-iop3xx/entry-macro.S @@ -0,0 +1,56 @@ +/* + * include/asm-arm/arch-iop3xx/entry-macro.S + * + * Low-level IRQ helper macros for IOP3xx-based platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#if defined(CONFIG_ARCH_IOP321) + .macro disable_fiq + .endm + + /* + * Note: only deal with normal interrupts, not FIQ + */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mov \irqnr, #0 + mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC + cmp \irqstat, #0 + beq 1001f + clz \irqnr, \irqstat + mov \base, #31 + subs \irqnr,\base,\irqnr + add \irqnr,\irqnr,#IRQ_IOP321_DMA0_EOT +1001: + .endm + +#elif defined(CONFIG_ARCH_IOP331) + .macro disable_fiq + .endm + + /* + * Note: only deal with normal interrupts, not FIQ + */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mov \irqnr, #0 + mrc p6, 0, \irqstat, c4, c0, 0 @ Read IINTSRC0 + cmp \irqstat, #0 + bne 1002f + mrc p6, 0, \irqstat, c5, c0, 0 @ Read IINTSRC1 + cmp \irqstat, #0 + beq 1001f + clz \irqnr, \irqstat + rsbs \irqnr,\irqnr,#31 @ recommend by RMK + add \irqnr,\irqnr,#IRQ_IOP331_XINT8 + b 1001f +1002: clz \irqnr, \irqstat + rsbs \irqnr,\irqnr,#31 @ recommend by RMK + add \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT +1001: + .endm + +#endif + diff --git a/include/asm-arm/arch-iop3xx/hardware.h b/include/asm-arm/arch-iop3xx/hardware.h new file mode 100644 index 000000000000..3b138171d086 --- /dev/null +++ b/include/asm-arm/arch-iop3xx/hardware.h @@ -0,0 +1,57 @@ +/* + * linux/include/asm-arm/arch-iop3xx/hardware.h + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/types.h> + +/* + * Note about PCI IO space mappings + * + * To make IO space accesses efficient, we store virtual addresses in + * the IO resources. + * + * The PCI IO space is located at virtual 0xfe000000 from physical + * 0x90000000. The PCI BARs must be programmed with physical addresses, + * but when we read them, we convert them to virtual addresses. See + * arch/arm/mach-iop3xx/iop3xx-pci.c + */ + +#define pcibios_assign_all_busses() 1 + + +/* + * The min PCI I/O and MEM space are dependent on what specific + * chipset/platform we are running on, so instead of hardcoding with + * #ifdefs, we just fill these in the platform level PCI init code. + */ +#ifndef __ASSEMBLY__ +extern unsigned long iop3xx_pcibios_min_io; +extern unsigned long iop3xx_pcibios_min_mem; + +extern unsigned int processor_id; +#endif + +/* + * We just set these to zero since they are really bogus anyways + */ +#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io) +#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem) + +/* + * Generic chipset bits + * + */ +#include "iop321.h" +#include "iop331.h" + +/* + * Board specific bits + */ +#include "iq80321.h" +#include "iq31244.h" +#include "iq80331.h" +#include "iq80332.h" + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-iop3xx/io.h b/include/asm-arm/arch-iop3xx/io.h new file mode 100644 index 000000000000..2761dfd8694d --- /dev/null +++ b/include/asm-arm/arch-iop3xx/io.h @@ -0,0 +1,20 @@ +/* + * linux/include/asm-arm/arch-iop3xx/io.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(p) ((void __iomem *)(p)) +#define __mem_pci(a) (a) +#define __mem_isa(a) (a) + +#endif diff --git a/include/asm-arm/arch-iop3xx/iop321-irqs.h b/include/asm-arm/arch-iop3xx/iop321-irqs.h new file mode 100644 index 000000000000..2fcc1654cb9d --- /dev/null +++ b/include/asm-arm/arch-iop3xx/iop321-irqs.h @@ -0,0 +1,100 @@ +/* + * linux/include/asm-arm/arch-iop3xx/irqs.h + * + * Author: Rory Bolt <rorybolt@pacbell.net> + * Copyright: (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef _IOP321_IRQS_H_ +#define _IOP321_IRQS_H_ + +/* + * IOP80321 chipset interrupts + */ +#define IOP321_IRQ_OFS 0 +#define IOP321_IRQ(x) (IOP321_IRQ_OFS + (x)) + +/* + * On IRQ or FIQ register + */ +#define IRQ_IOP321_DMA0_EOT IOP321_IRQ(0) +#define IRQ_IOP321_DMA0_EOC IOP321_IRQ(1) +#define IRQ_IOP321_DMA1_EOT IOP321_IRQ(2) +#define IRQ_IOP321_DMA1_EOC IOP321_IRQ(3) +#define IRQ_IOP321_RSVD_4 IOP321_IRQ(4) +#define IRQ_IOP321_RSVD_5 IOP321_IRQ(5) +#define IRQ_IOP321_AA_EOT IOP321_IRQ(6) +#define IRQ_IOP321_AA_EOC IOP321_IRQ(7) +#define IRQ_IOP321_CORE_PMON IOP321_IRQ(8) +#define IRQ_IOP321_TIMER0 IOP321_IRQ(9) +#define IRQ_IOP321_TIMER1 IOP321_IRQ(10) +#define IRQ_IOP321_I2C_0 IOP321_IRQ(11) +#define IRQ_IOP321_I2C_1 IOP321_IRQ(12) +#define IRQ_IOP321_MESSAGING IOP321_IRQ(13) +#define IRQ_IOP321_ATU_BIST IOP321_IRQ(14) +#define IRQ_IOP321_PERFMON IOP321_IRQ(15) +#define IRQ_IOP321_CORE_PMU IOP321_IRQ(16) +#define IRQ_IOP321_BIU_ERR IOP321_IRQ(17) +#define IRQ_IOP321_ATU_ERR IOP321_IRQ(18) +#define IRQ_IOP321_MCU_ERR IOP321_IRQ(19) +#define IRQ_IOP321_DMA0_ERR IOP321_IRQ(20) +#define IRQ_IOP321_DMA1_ERR IOP321_IRQ(21) +#define IRQ_IOP321_RSVD_22 IOP321_IRQ(22) +#define IRQ_IOP321_AA_ERR IOP321_IRQ(23) +#define IRQ_IOP321_MSG_ERR IOP321_IRQ(24) +#define IRQ_IOP321_SSP IOP321_IRQ(25) +#define IRQ_IOP321_RSVD_26 IOP321_IRQ(26) +#define IRQ_IOP321_XINT0 IOP321_IRQ(27) +#define IRQ_IOP321_XINT1 IOP321_IRQ(28) +#define IRQ_IOP321_XINT2 IOP321_IRQ(29) +#define IRQ_IOP321_XINT3 IOP321_IRQ(30) +#define IRQ_IOP321_HPI IOP321_IRQ(31) + +#define NR_IOP321_IRQS (IOP321_IRQ(31) + 1) + +#define NR_IRQS NR_IOP321_IRQS + + +/* + * Interrupts available on the IQ80321 board + */ + +/* + * On board devices + */ +#define IRQ_IQ80321_I82544 IRQ_IOP321_XINT0 +#define IRQ_IQ80321_UART IRQ_IOP321_XINT1 + +/* + * PCI interrupts + */ +#define IRQ_IQ80321_INTA IRQ_IOP321_XINT0 +#define IRQ_IQ80321_INTB IRQ_IOP321_XINT1 +#define IRQ_IQ80321_INTC IRQ_IOP321_XINT2 +#define IRQ_IQ80321_INTD IRQ_IOP321_XINT3 + +/* + * Interrupts on the IQ31244 board + */ + +/* + * On board devices + */ +#define IRQ_IQ31244_UART IRQ_IOP321_XINT1 +#define IRQ_IQ31244_I82546 IRQ_IOP321_XINT0 +#define IRQ_IQ31244_SATA IRQ_IOP321_XINT2 +#define IRQ_IQ31244_PCIX_SLOT IRQ_IOP321_XINT3 + +/* + * PCI interrupts + */ +#define IRQ_IQ31244_INTA IRQ_IOP321_XINT0 +#define IRQ_IQ31244_INTB IRQ_IOP321_XINT1 +#define IRQ_IQ31244_INTC IRQ_IOP321_XINT2 +#define IRQ_IQ31244_INTD IRQ_IOP321_XINT3 + +#endif // _IOP321_IRQ_H_ diff --git a/include/asm-arm/arch-iop3xx/iop321.h b/include/asm-arm/arch-iop3xx/iop321.h new file mode 100644 index 000000000000..200621ff3690 --- /dev/null +++ b/include/asm-arm/arch-iop3xx/iop321.h @@ -0,0 +1,345 @@ +/* + * linux/include/asm/arch-iop3xx/iop321.h + * + * Intel IOP321 Chip definitions + * + * Author: Rory Bolt <rorybolt@pacbell.net> + * Copyright (C) 2002 Rory Bolt + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _IOP321_HW_H_ +#define _IOP321_HW_H_ + + +/* + * This is needed for mixed drivers that need to work on all + * IOP3xx variants but behave slightly differently on each. + */ +#ifndef __ASSEMBLY__ +#ifdef CONFIG_ARCH_IOP321 +#define iop_is_321() (((processor_id & 0xfffff5e0) == 0x69052420)) +#else +#define iop_is_321() 0 +#endif +#endif + +/* + * IOP321 I/O and Mem space regions for PCI autoconfiguration + */ +#define IOP321_PCI_IO_WINDOW_SIZE 0x00010000 +#define IOP321_PCI_LOWER_IO_PA 0x90000000 +#define IOP321_PCI_LOWER_IO_VA 0xfe000000 +#define IOP321_PCI_LOWER_IO_BA (*IOP321_OIOWTVR) +#define IOP321_PCI_UPPER_IO_PA (IOP321_PCI_LOWER_IO_PA + IOP321_PCI_IO_WINDOW_SIZE - 1) +#define IOP321_PCI_UPPER_IO_VA (IOP321_PCI_LOWER_IO_VA + IOP321_PCI_IO_WINDOW_SIZE - 1) +#define IOP321_PCI_UPPER_IO_BA (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1) +#define IOP321_PCI_IO_OFFSET (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA) + +//#define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1) +#define IOP321_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */ +#define IOP321_PCI_LOWER_MEM_PA 0x80000000 +#define IOP321_PCI_LOWER_MEM_BA (*IOP321_OMWTVR0) +#define IOP321_PCI_UPPER_MEM_PA (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1) +#define IOP321_PCI_UPPER_MEM_BA (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1) +#define IOP321_PCI_MEM_OFFSET (IOP321_PCI_LOWER_MEM_PA - IOP321_PCI_LOWER_MEM_BA) + + +/* + * IOP321 chipset registers + */ +#define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/ +#define IOP321_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */ +#define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg)) + +/* Reserved 0x00000000 through 0x000000FF */ + +/* Address Translation Unit 0x00000100 through 0x000001FF */ +#define IOP321_ATUVID (volatile u16 *)IOP321_REG_ADDR(0x00000100) +#define IOP321_ATUDID (volatile u16 *)IOP321_REG_ADDR(0x00000102) +#define IOP321_ATUCMD (volatile u16 *)IOP321_REG_ADDR(0x00000104) +#define IOP321_ATUSR (volatile u16 *)IOP321_REG_ADDR(0x00000106) +#define IOP321_ATURID (volatile u8 *)IOP321_REG_ADDR(0x00000108) +#define IOP321_ATUCCR (volatile u32 *)IOP321_REG_ADDR(0x00000109) +#define IOP321_ATUCLSR (volatile u8 *)IOP321_REG_ADDR(0x0000010C) +#define IOP321_ATULT (volatile u8 *)IOP321_REG_ADDR(0x0000010D) +#define IOP321_ATUHTR (volatile u8 *)IOP321_REG_ADDR(0x0000010E) +#define IOP321_ATUBIST (volatile u8 *)IOP321_REG_ADDR(0x0000010F) +#define IOP321_IABAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000110) +#define IOP321_IAUBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000114) +#define IOP321_IABAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000118) +#define IOP321_IAUBAR1 (volatile u32 *)IOP321_REG_ADDR(0x0000011C) +#define IOP321_IABAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000120) +#define IOP321_IAUBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000124) +#define IOP321_ASVIR (volatile u16 *)IOP321_REG_ADDR(0x0000012C) +#define IOP321_ASIR (volatile u16 *)IOP321_REG_ADDR(0x0000012E) +#define IOP321_ERBAR (volatile u32 *)IOP321_REG_ADDR(0x00000130) +/* Reserved 0x00000134 through 0x0000013B */ +#define IOP321_ATUILR (volatile u8 *)IOP321_REG_ADDR(0x0000013C) +#define IOP321_ATUIPR (volatile u8 *)IOP321_REG_ADDR(0x0000013D) +#define IOP321_ATUMGNT (volatile u8 *)IOP321_REG_ADDR(0x0000013E) +#define IOP321_ATUMLAT (volatile u8 *)IOP321_REG_ADDR(0x0000013F) +#define IOP321_IALR0 (volatile u32 *)IOP321_REG_ADDR(0x00000140) +#define IOP321_IATVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000144) +#define IOP321_ERLR (volatile u32 *)IOP321_REG_ADDR(0x00000148) +#define IOP321_ERTVR (volatile u32 *)IOP321_REG_ADDR(0x0000014C) +#define IOP321_IALR1 (volatile u32 *)IOP321_REG_ADDR(0x00000150) +#define IOP321_IALR2 (volatile u32 *)IOP321_REG_ADDR(0x00000154) +#define IOP321_IATVR2 (volatile u32 *)IOP321_REG_ADDR(0x00000158) +#define IOP321_OIOWTVR (volatile u32 *)IOP321_REG_ADDR(0x0000015C) +#define IOP321_OMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000160) +#define IOP321_OUMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000164) +#define IOP321_OMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x00000168) +#define IOP321_OUMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x0000016C) +/* Reserved 0x00000170 through 0x00000177*/ +#define IOP321_OUDWTVR (volatile u32 *)IOP321_REG_ADDR(0x00000178) +/* Reserved 0x0000017C through 0x0000017F*/ +#define IOP321_ATUCR (volatile u32 *)IOP321_REG_ADDR(0x00000180) +#define IOP321_PCSR (volatile u32 *)IOP321_REG_ADDR(0x00000184) +#define IOP321_ATUISR (volatile u32 *)IOP321_REG_ADDR(0x00000188) +#define IOP321_ATUIMR (volatile u32 *)IOP321_REG_ADDR(0x0000018C) +#define IOP321_IABAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000190) +#define IOP321_IAUBAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000194) +#define IOP321_IALR3 (volatile u32 *)IOP321_REG_ADDR(0x00000198) +#define IOP321_IATVR3 (volatile u32 *)IOP321_REG_ADDR(0x0000019C) +/* Reserved 0x000001A0 through 0x000001A3*/ +#define IOP321_OCCAR (volatile u32 *)IOP321_REG_ADDR(0x000001A4) +/* Reserved 0x000001A8 through 0x000001AB*/ +#define IOP321_OCCDR (volatile u32 *)IOP321_REG_ADDR(0x000001AC) +/* Reserved 0x000001B0 through 0x000001BB*/ +#define IOP321_PDSCR (volatile u32 *)IOP321_REG_ADDR(0x000001BC) +#define IOP321_PMCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001C0) +#define IOP321_PMNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001C1) +#define IOP321_APMCR (volatile u16 *)IOP321_REG_ADDR(0x000001C2) +#define IOP321_APMCSR (volatile u16 *)IOP321_REG_ADDR(0x000001C4) +/* Reserved 0x000001C6 through 0x000001DF */ +#define IOP321_PCIXCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001E0) +#define IOP321_PCIXNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001E1) +#define IOP321_PCIXCMD (volatile u16 *)IOP321_REG_ADDR(0x000001E2) +#define IOP321_PCIXSR (volatile u32 *)IOP321_REG_ADDR(0x000001E4) +#define IOP321_PCIIRSR (volatile u32 *)IOP321_REG_ADDR(0x000001EC) + +/* Messaging Unit 0x00000300 through 0x000003FF */ + +/* Reserved 0x00000300 through 0x0000030c */ +#define IOP321_IMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000310) +#define IOP321_IMR1 (volatile u32 *)IOP321_REG_ADDR(0x00000314) +#define IOP321_OMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000318) +#define IOP321_OMR1 (volatile u32 *)IOP321_REG_ADDR(0x0000031C) +#define IOP321_IDR (volatile u32 *)IOP321_REG_ADDR(0x00000320) +#define IOP321_IISR (volatile u32 *)IOP321_REG_ADDR(0x00000324) +#define IOP321_IIMR (volatile u32 *)IOP321_REG_ADDR(0x00000328) +#define IOP321_ODR (volatile u32 *)IOP321_REG_ADDR(0x0000032C) +#define IOP321_OISR (volatile u32 *)IOP321_REG_ADDR(0x00000330) +#define IOP321_OIMR (volatile u32 *)IOP321_REG_ADDR(0x00000334) +/* Reserved 0x00000338 through 0x0000034F */ +#define IOP321_MUCR (volatile u32 *)IOP321_REG_ADDR(0x00000350) +#define IOP321_QBAR (volatile u32 *)IOP321_REG_ADDR(0x00000354) +/* Reserved 0x00000358 through 0x0000035C */ +#define IOP321_IFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000360) +#define IOP321_IFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000364) +#define IOP321_IPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000368) +#define IOP321_IPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000036C) +#define IOP321_OFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000370) +#define IOP321_OFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000374) +#define IOP321_OPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000378) +#define IOP321_OPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000037C) +#define IOP321_IAR (volatile u32 *)IOP321_REG_ADDR(0x00000380) + +#define IOP321_IIxR_MASK 0x7f /* masks all */ +#define IOP321_IIxR_IRI 0x40 /* RC Index Register Interrupt */ +#define IOP321_IIxR_OFQF 0x20 /* RC Output Free Q Full (ERROR) */ +#define IOP321_IIxR_ipq 0x10 /* RC Inbound Post Q (post) */ +#define IOP321_IIxR_ERRDI 0x08 /* RO Error Doorbell Interrupt */ +#define IOP321_IIxR_IDI 0x04 /* RO Inbound Doorbell Interrupt */ +#define IOP321_IIxR_IM1 0x02 /* RC Inbound Message 1 Interrupt */ +#define IOP321_IIxR_IM0 0x01 /* RC Inbound Message 0 Interrupt */ + +/* Reserved 0x00000384 through 0x000003FF */ + +/* DMA Controller 0x00000400 through 0x000004FF */ +#define IOP321_DMA0_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000400) +#define IOP321_DMA0_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000404) +#define IOP321_DMA0_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000040C) +#define IOP321_DMA0_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000410) +#define IOP321_DMA0_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000414) +#define IOP321_DMA0_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000418) +#define IOP321_DMA0_LADR (volatile u32 *)IOP321_REG_ADDR(0X0000041C) +#define IOP321_DMA0_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000420) +#define IOP321_DMA0_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000424) +/* Reserved 0x00000428 through 0x0000043C */ +#define IOP321_DMA1_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000440) +#define IOP321_DMA1_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000444) +#define IOP321_DMA1_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000044C) +#define IOP321_DMA1_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000450) +#define IOP321_DMA1_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000454) +#define IOP321_DMA1_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000458) +#define IOP321_DMA1_LADR (volatile u32 *)IOP321_REG_ADDR(0x0000045C) +#define IOP321_DMA1_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000460) +#define IOP321_DMA1_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000464) +/* Reserved 0x00000468 through 0x000004FF */ + +/* Memory controller 0x00000500 through 0x0005FF */ + +/* Peripheral bus interface unit 0x00000680 through 0x0006FF */ +#define IOP321_PBCR (volatile u32 *)IOP321_REG_ADDR(0x00000680) +#define IOP321_PBISR (volatile u32 *)IOP321_REG_ADDR(0x00000684) +#define IOP321_PBBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000688) +#define IOP321_PBLR0 (volatile u32 *)IOP321_REG_ADDR(0x0000068C) +#define IOP321_PBBAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000690) +#define IOP321_PBLR1 (volatile u32 *)IOP321_REG_ADDR(0x00000694) +#define IOP321_PBBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000698) +#define IOP321_PBLR2 (volatile u32 *)IOP321_REG_ADDR(0x0000069C) +#define IOP321_PBBAR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A0) +#define IOP321_PBLR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A4) +#define IOP321_PBBAR4 (volatile u32 *)IOP321_REG_ADDR(0x000006A8) +#define IOP321_PBLR4 (volatile u32 *)IOP321_REG_ADDR(0x000006AC) +#define IOP321_PBBAR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B0) +#define IOP321_PBLR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B4) +#define IOP321_PBDSCR (volatile u32 *)IOP321_REG_ADDR(0x000006B8) +/* Reserved 0x000006BC */ +#define IOP321_PMBR0 (volatile u32 *)IOP321_REG_ADDR(0x000006C0) +/* Reserved 0x000006C4 through 0x000006DC */ +#define IOP321_PMBR1 (volatile u32 *)IOP321_REG_ADDR(0x000006E0) +#define IOP321_PMBR2 (volatile u32 *)IOP321_REG_ADDR(0x000006E4) + +#define IOP321_PBCR_EN 0x1 + +#define IOP321_PBISR_BOOR_ERR 0x1 + +/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */ +#define IOP321_GTMR (volatile u32 *)IOP321_REG_ADDR(0x00000700) +#define IOP321_ESR (volatile u32 *)IOP321_REG_ADDR(0x00000704) +#define IOP321_EMISR (volatile u32 *)IOP321_REG_ADDR(0x00000708) +/* reserved 0x00000070c */ +#define IOP321_GTSR (volatile u32 *)IOP321_REG_ADDR(0x00000710) +/* PERC0 DOESN'T EXIST - index from 1! */ +#define IOP321_PERCR0 (volatile u32 *)IOP321_REG_ADDR(0x00000710) + +#define IOP321_GTMR_NGCE 0x04 /* (Not) Global Counter Enable */ + +/* Internal arbitration unit 0x00000780 through 0x0007BF */ +#define IOP321_IACR (volatile u32 *)IOP321_REG_ADDR(0x00000780) +#define IOP321_MTTR1 (volatile u32 *)IOP321_REG_ADDR(0x00000784) +#define IOP321_MTTR2 (volatile u32 *)IOP321_REG_ADDR(0x00000788) + +/* General Purpose I/O Registers */ +#define IOP321_GPOE (volatile u32 *)IOP321_REG_ADDR(0x000007C4) +#define IOP321_GPID (volatile u32 *)IOP321_REG_ADDR(0x000007C8) +#define IOP321_GPOD (volatile u32 *)IOP321_REG_ADDR(0x000007CC) + +/* Interrupt Controller */ +#define IOP321_INTCTL (volatile u32 *)IOP321_REG_ADDR(0x000007D0) +#define IOP321_INTSTR (volatile u32 *)IOP321_REG_ADDR(0x000007D4) +#define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8) +#define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC) + +/* Timers */ + +#define IOP321_TU_TMR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E0) +#define IOP321_TU_TMR1 (volatile u32 *)IOP321_REG_ADDR(0x000007E4) + +#ifdef CONFIG_ARCH_IQ80321 +#define IOP321_TICK_RATE 200000000 /* 200 MHz clock */ +#elif defined(CONFIG_ARCH_IQ31244) +#define IOP321_TICK_RATE 198000000 /* 33.000 MHz crystal */ +#endif + +#ifdef CONFIG_ARCH_EP80219 +#undef IOP321_TICK_RATE +#define IOP321_TICK_RATE 200000000 /* 33.333333 Mhz crystal */ +#endif + +#define IOP321_TMR_TC 0x01 +#define IOP321_TMR_EN 0x02 +#define IOP321_TMR_RELOAD 0x04 +#define IOP321_TMR_PRIVILEGED 0x09 + +#define IOP321_TMR_RATIO_1_1 0x00 +#define IOP321_TMR_RATIO_4_1 0x10 +#define IOP321_TMR_RATIO_8_1 0x20 +#define IOP321_TMR_RATIO_16_1 0x30 + +#define IOP321_TU_TCR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E8) +#define IOP321_TU_TCR1 (volatile u32 *)IOP321_REG_ADDR(0x000007EC) +#define IOP321_TU_TRR0 (volatile u32 *)IOP321_REG_ADDR(0x000007F0) +#define IOP321_TU_TRR1 (volatile u32 *)IOP321_REG_ADDR(0x000007F4) +#define IOP321_TU_TISR (volatile u32 *)IOP321_REG_ADDR(0x000007F8) +#define IOP321_TU_WDTCR (volatile u32 *)IOP321_REG_ADDR(0x000007FC) + +/* Application accelerator unit 0x00000800 - 0x000008FF */ +#define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800) +#define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804) +#define IOP321_AAU_ADAR (volatile u32 *)IOP321_REG_ADDR(0x00000808) +#define IOP321_AAU_ANDAR (volatile u32 *)IOP321_REG_ADDR(0x0000080C) +#define IOP321_AAU_SAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000810) +#define IOP321_AAU_SAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000814) +#define IOP321_AAU_SAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000818) +#define IOP321_AAU_SAR4 (volatile u32 *)IOP321_REG_ADDR(0x0000081C) +#define IOP321_AAU_SAR5 (volatile u32 *)IOP321_REG_ADDR(0x0000082C) +#define IOP321_AAU_SAR6 (volatile u32 *)IOP321_REG_ADDR(0x00000830) +#define IOP321_AAU_SAR7 (volatile u32 *)IOP321_REG_ADDR(0x00000834) +#define IOP321_AAU_SAR8 (volatile u32 *)IOP321_REG_ADDR(0x00000838) +#define IOP321_AAU_SAR9 (volatile u32 *)IOP321_REG_ADDR(0x00000840) +#define IOP321_AAU_SAR10 (volatile u32 *)IOP321_REG_ADDR(0x00000844) +#define IOP321_AAU_SAR11 (volatile u32 *)IOP321_REG_ADDR(0x00000848) +#define IOP321_AAU_SAR12 (volatile u32 *)IOP321_REG_ADDR(0x0000084C) +#define IOP321_AAU_SAR13 (volatile u32 *)IOP321_REG_ADDR(0x00000850) +#define IOP321_AAU_SAR14 (volatile u32 *)IOP321_REG_ADDR(0x00000854) +#define IOP321_AAU_SAR15 (volatile u32 *)IOP321_REG_ADDR(0x00000858) +#define IOP321_AAU_SAR16 (volatile u32 *)IOP321_REG_ADDR(0x0000085C) +#define IOP321_AAU_SAR17 (volatile u32 *)IOP321_REG_ADDR(0x00000864) +#define IOP321_AAU_SAR18 (volatile u32 *)IOP321_REG_ADDR(0x00000868) +#define IOP321_AAU_SAR19 (volatile u32 *)IOP321_REG_ADDR(0x0000086C) +#define IOP321_AAU_SAR20 (volatile u32 *)IOP321_REG_ADDR(0x00000870) +#define IOP321_AAU_SAR21 (volatile u32 *)IOP321_REG_ADDR(0x00000874) +#define IOP321_AAU_SAR22 (volatile u32 *)IOP321_REG_ADDR(0x00000878) +#define IOP321_AAU_SAR23 (volatile u32 *)IOP321_REG_ADDR(0x0000087C) +#define IOP321_AAU_SAR24 (volatile u32 *)IOP321_REG_ADDR(0x00000880) +#define IOP321_AAU_SAR25 (volatile u32 *)IOP321_REG_ADDR(0x00000888) +#define IOP321_AAU_SAR26 (volatile u32 *)IOP321_REG_ADDR(0x0000088C) +#define IOP321_AAU_SAR27 (volatile u32 *)IOP321_REG_ADDR(0x00000890) +#define IOP321_AAU_SAR28 (volatile u32 *)IOP321_REG_ADDR(0x00000894) +#define IOP321_AAU_SAR29 (volatile u32 *)IOP321_REG_ADDR(0x00000898) +#define IOP321_AAU_SAR30 (volatile u32 *)IOP321_REG_ADDR(0x0000089C) +#define IOP321_AAU_SAR31 (volatile u32 *)IOP321_REG_ADDR(0x000008A0) +#define IOP321_AAU_SAR32 (volatile u32 *)IOP321_REG_ADDR(0x000008A4) +#define IOP321_AAU_DAR (volatile u32 *)IOP321_REG_ADDR(0x00000820) +#define IOP321_AAU_ABCR (volatile u32 *)IOP321_REG_ADDR(0x00000824) +#define IOP321_AAU_ADCR (volatile u32 *)IOP321_REG_ADDR(0x00000828) +#define IOP321_AAU_EDCR0 (volatile u32 *)IOP321_REG_ADDR(0x0000083c) +#define IOP321_AAU_EDCR1 (volatile u32 *)IOP321_REG_ADDR(0x00000860) +#define IOP321_AAU_EDCR2 (volatile u32 *)IOP321_REG_ADDR(0x00000884) + + +/* SSP serial port unit 0x00001600 - 0x0000167F */ +/* I2C bus interface unit 0x00001680 - 0x000016FF */ +#define IOP321_ICR0 (volatile u32 *)IOP321_REG_ADDR(0x00001680) +#define IOP321_ISR0 (volatile u32 *)IOP321_REG_ADDR(0x00001684) +#define IOP321_ISAR0 (volatile u32 *)IOP321_REG_ADDR(0x00001688) +#define IOP321_IDBR0 (volatile u32 *)IOP321_REG_ADDR(0x0000168C) +/* Reserved 0x00001690 */ +#define IOP321_IBMR0 (volatile u32 *)IOP321_REG_ADDR(0x00001694) +/* Reserved 0x00001698 */ +/* Reserved 0x0000169C */ +#define IOP321_ICR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A0) +#define IOP321_ISR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A4) +#define IOP321_ISAR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A8) +#define IOP321_IDBR1 (volatile u32 *)IOP321_REG_ADDR(0x000016AC) +#define IOP321_IBMR1 (volatile u32 *)IOP321_REG_ADDR(0x000016B4) +/* Reserved 0x000016B8 through 0x000016FC */ + +/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */ + + +#ifndef __ASSEMBLY__ +extern void iop321_map_io(void); +extern void iop321_init_irq(void); +extern void iop321_time_init(void); +#endif + +#endif // _IOP321_HW_H_ diff --git a/include/asm-arm/arch-iop3xx/iop331-irqs.h b/include/asm-arm/arch-iop3xx/iop331-irqs.h new file mode 100644 index 000000000000..8ff73d487222 --- /dev/null +++ b/include/asm-arm/arch-iop3xx/iop331-irqs.h @@ -0,0 +1,136 @@ +/* + * linux/include/asm-arm/arch-iop3xx/irqs.h + * + * Author: Dave Jiang (dave.jiang@intel.com) + * Copyright: (C) 2003 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef _IOP331_IRQS_H_ +#define _IOP331_IRQS_H_ + +/* + * IOP80331 chipset interrupts + */ +#define IOP331_IRQ_OFS 0 +#define IOP331_IRQ(x) (IOP331_IRQ_OFS + (x)) + +/* + * On IRQ or FIQ register + */ +#define IRQ_IOP331_DMA0_EOT IOP331_IRQ(0) +#define IRQ_IOP331_DMA0_EOC IOP331_IRQ(1) +#define IRQ_IOP331_DMA1_EOT IOP331_IRQ(2) +#define IRQ_IOP331_DMA1_EOC IOP331_IRQ(3) +#define IRQ_IOP331_RSVD_4 IOP331_IRQ(4) +#define IRQ_IOP331_RSVD_5 IOP331_IRQ(5) +#define IRQ_IOP331_AA_EOT IOP331_IRQ(6) +#define IRQ_IOP331_AA_EOC IOP331_IRQ(7) +#define IRQ_IOP331_TIMER0 IOP331_IRQ(8) +#define IRQ_IOP331_TIMER1 IOP331_IRQ(9) +#define IRQ_IOP331_I2C_0 IOP331_IRQ(10) +#define IRQ_IOP331_I2C_1 IOP331_IRQ(11) +#define IRQ_IOP331_MSG IOP331_IRQ(12) +#define IRQ_IOP331_MSGIBQ IOP331_IRQ(13) +#define IRQ_IOP331_ATU_BIST IOP331_IRQ(14) +#define IRQ_IOP331_PERFMON IOP331_IRQ(15) +#define IRQ_IOP331_CORE_PMU IOP331_IRQ(16) +#define IRQ_IOP331_RSVD_17 IOP331_IRQ(17) +#define IRQ_IOP331_RSVD_18 IOP331_IRQ(18) +#define IRQ_IOP331_RSVD_19 IOP331_IRQ(19) +#define IRQ_IOP331_RSVD_20 IOP331_IRQ(20) +#define IRQ_IOP331_RSVD_21 IOP331_IRQ(21) +#define IRQ_IOP331_RSVD_22 IOP331_IRQ(22) +#define IRQ_IOP331_RSVD_23 IOP331_IRQ(23) +#define IRQ_IOP331_XINT0 IOP331_IRQ(24) +#define IRQ_IOP331_XINT1 IOP331_IRQ(25) +#define IRQ_IOP331_XINT2 IOP331_IRQ(26) +#define IRQ_IOP331_XINT3 IOP331_IRQ(27) +#define IRQ_IOP331_RSVD_28 IOP331_IRQ(28) +#define IRQ_IOP331_RSVD_29 IOP331_IRQ(29) +#define IRQ_IOP331_RSVD_30 IOP331_IRQ(30) +#define IRQ_IOP331_RSVD_31 IOP331_IRQ(31) +#define IRQ_IOP331_XINT8 IOP331_IRQ(32) // 0 +#define IRQ_IOP331_XINT9 IOP331_IRQ(33) // 1 +#define IRQ_IOP331_XINT10 IOP331_IRQ(34) // 2 +#define IRQ_IOP331_XINT11 IOP331_IRQ(35) // 3 +#define IRQ_IOP331_XINT12 IOP331_IRQ(36) // 4 +#define IRQ_IOP331_XINT13 IOP331_IRQ(37) // 5 +#define IRQ_IOP331_XINT14 IOP331_IRQ(38) // 6 +#define IRQ_IOP331_XINT15 IOP331_IRQ(39) // 7 +#define IRQ_IOP331_RSVD_40 IOP331_IRQ(40) // 8 +#define IRQ_IOP331_RSVD_41 IOP331_IRQ(41) // 9 +#define IRQ_IOP331_RSVD_42 IOP331_IRQ(42) // 10 +#define IRQ_IOP331_RSVD_43 IOP331_IRQ(43) // 11 +#define IRQ_IOP331_RSVD_44 IOP331_IRQ(44) // 12 +#define IRQ_IOP331_RSVD_45 IOP331_IRQ(45) // 13 +#define IRQ_IOP331_RSVD_46 IOP331_IRQ(46) // 14 +#define IRQ_IOP331_RSVD_47 IOP331_IRQ(47) // 15 +#define IRQ_IOP331_RSVD_48 IOP331_IRQ(48) // 16 +#define IRQ_IOP331_RSVD_49 IOP331_IRQ(49) // 17 +#define IRQ_IOP331_RSVD_50 IOP331_IRQ(50) // 18 +#define IRQ_IOP331_UART0 IOP331_IRQ(51) // 19 +#define IRQ_IOP331_UART1 IOP331_IRQ(52) // 20 +#define IRQ_IOP331_PBIE IOP331_IRQ(53) // 21 +#define IRQ_IOP331_ATU_CRW IOP331_IRQ(54) // 22 +#define IRQ_IOP331_ATU_ERR IOP331_IRQ(55) // 23 +#define IRQ_IOP331_MCU_ERR IOP331_IRQ(56) // 24 +#define IRQ_IOP331_DMA0_ERR IOP331_IRQ(57) // 25 +#define IRQ_IOP331_DMA1_ERR IOP331_IRQ(58) // 26 +#define IRQ_IOP331_RSVD_59 IOP331_IRQ(59) // 27 +#define IRQ_IOP331_AA_ERR IOP331_IRQ(60) // 28 +#define IRQ_IOP331_RSVD_61 IOP331_IRQ(61) // 29 +#define IRQ_IOP331_MSG_ERR IOP331_IRQ(62) // 30 +#define IRQ_IOP331_HPI IOP331_IRQ(63) // 31 + +#define NR_IOP331_IRQS (IOP331_IRQ(63) + 1) + +#define NR_IRQS NR_IOP331_IRQS + + +#if defined(CONFIG_ARCH_IQ80331) +/* + * Interrupts available on the IQ80331 board + */ + +/* + * On board devices + */ +#define IRQ_IQ80331_I82544 IRQ_IOP331_XINT0 +#define IRQ_IQ80331_UART0 IRQ_IOP331_UART0 +#define IRQ_IQ80331_UART1 IRQ_IOP331_UART1 + +/* + * PCI interrupts + */ +#define IRQ_IQ80331_INTA IRQ_IOP331_XINT0 +#define IRQ_IQ80331_INTB IRQ_IOP331_XINT1 +#define IRQ_IQ80331_INTC IRQ_IOP331_XINT2 +#define IRQ_IQ80331_INTD IRQ_IOP331_XINT3 + +#elif defined(CONFIG_MACH_IQ80332) +/* + * Interrupts available on the IQ80332 board + */ + +/* + * On board devices + */ +#define IRQ_IQ80332_I82544 IRQ_IOP331_XINT0 +#define IRQ_IQ80332_UART0 IRQ_IOP331_UART0 +#define IRQ_IQ80332_UART1 IRQ_IOP331_UART1 + +/* + * PCI interrupts + */ +#define IRQ_IQ80332_INTA IRQ_IOP331_XINT0 +#define IRQ_IQ80332_INTB IRQ_IOP331_XINT1 +#define IRQ_IQ80332_INTC IRQ_IOP331_XINT2 +#define IRQ_IQ80332_INTD IRQ_IOP331_XINT3 + +#endif + +#endif // _IOP331_IRQ_H_ diff --git a/include/asm-arm/arch-iop3xx/iop331.h b/include/asm-arm/arch-iop3xx/iop331.h new file mode 100644 index 000000000000..96adffd8bad2 --- /dev/null +++ b/include/asm-arm/arch-iop3xx/iop331.h @@ -0,0 +1,363 @@ +/* + * linux/include/asm/arch-iop3xx/iop331.h + * + * Intel IOP331 Chip definitions + * + * Author: Dave Jiang (dave.jiang@intel.com) + * Copyright (C) 2003, 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _IOP331_HW_H_ +#define _IOP331_HW_H_ + + +/* + * This is needed for mixed drivers that need to work on all + * IOP3xx variants but behave slightly differently on each. + */ +#ifndef __ASSEMBLY__ +#ifdef CONFIG_ARCH_IOP331 +/*#define iop_is_331() ((processor_id & 0xffffffb0) == 0x69054090) */ +#define iop_is_331() ((processor_id & 0xffffff30) == 0x69054010) +#else +#define iop_is_331() 0 +#endif +#endif + +/* + * IOP331 I/O and Mem space regions for PCI autoconfiguration + */ +#define IOP331_PCI_IO_WINDOW_SIZE 0x00010000 +#define IOP331_PCI_LOWER_IO_PA 0x90000000 +#define IOP331_PCI_LOWER_IO_VA 0xfe000000 +#define IOP331_PCI_LOWER_IO_BA (*IOP331_OIOWTVR) +#define IOP331_PCI_UPPER_IO_PA (IOP331_PCI_LOWER_IO_PA + IOP331_PCI_IO_WINDOW_SIZE - 1) +#define IOP331_PCI_UPPER_IO_VA (IOP331_PCI_LOWER_IO_VA + IOP331_PCI_IO_WINDOW_SIZE - 1) +#define IOP331_PCI_UPPER_IO_BA (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1) +#define IOP331_PCI_IO_OFFSET (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA) + +/* this can be 128M if OMWTVR1 is set */ +#define IOP331_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */ +//#define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1) +#define IOP331_PCI_LOWER_MEM_PA 0x80000000 +#define IOP331_PCI_LOWER_MEM_BA (*IOP331_OMWTVR0) +#define IOP331_PCI_UPPER_MEM_PA (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1) +#define IOP331_PCI_UPPER_MEM_BA (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1) +#define IOP331_PCI_MEM_OFFSET (IOP331_PCI_LOWER_MEM_PA - IOP331_PCI_LOWER_MEM_BA) + +/* + * IOP331 chipset registers + */ +#define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/ +#define IOP331_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */ +#define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg)) + +/* Reserved 0x00000000 through 0x000000FF */ + +/* Address Translation Unit 0x00000100 through 0x000001FF */ +#define IOP331_ATUVID (volatile u16 *)IOP331_REG_ADDR(0x00000100) +#define IOP331_ATUDID (volatile u16 *)IOP331_REG_ADDR(0x00000102) +#define IOP331_ATUCMD (volatile u16 *)IOP331_REG_ADDR(0x00000104) +#define IOP331_ATUSR (volatile u16 *)IOP331_REG_ADDR(0x00000106) +#define IOP331_ATURID (volatile u8 *)IOP331_REG_ADDR(0x00000108) +#define IOP331_ATUCCR (volatile u32 *)IOP331_REG_ADDR(0x00000109) +#define IOP331_ATUCLSR (volatile u8 *)IOP331_REG_ADDR(0x0000010C) +#define IOP331_ATULT (volatile u8 *)IOP331_REG_ADDR(0x0000010D) +#define IOP331_ATUHTR (volatile u8 *)IOP331_REG_ADDR(0x0000010E) +#define IOP331_ATUBIST (volatile u8 *)IOP331_REG_ADDR(0x0000010F) +#define IOP331_IABAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000110) +#define IOP331_IAUBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000114) +#define IOP331_IABAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000118) +#define IOP331_IAUBAR1 (volatile u32 *)IOP331_REG_ADDR(0x0000011C) +#define IOP331_IABAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000120) +#define IOP331_IAUBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000124) +#define IOP331_ASVIR (volatile u16 *)IOP331_REG_ADDR(0x0000012C) +#define IOP331_ASIR (volatile u16 *)IOP331_REG_ADDR(0x0000012E) +#define IOP331_ERBAR (volatile u32 *)IOP331_REG_ADDR(0x00000130) +#define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134) +/* Reserved 0x00000138 through 0x0000013B */ +#define IOP331_ATUILR (volatile u8 *)IOP331_REG_ADDR(0x0000013C) +#define IOP331_ATUIPR (volatile u8 *)IOP331_REG_ADDR(0x0000013D) +#define IOP331_ATUMGNT (volatile u8 *)IOP331_REG_ADDR(0x0000013E) +#define IOP331_ATUMLAT (volatile u8 *)IOP331_REG_ADDR(0x0000013F) +#define IOP331_IALR0 (volatile u32 *)IOP331_REG_ADDR(0x00000140) +#define IOP331_IATVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000144) +#define IOP331_ERLR (volatile u32 *)IOP331_REG_ADDR(0x00000148) +#define IOP331_ERTVR (volatile u32 *)IOP331_REG_ADDR(0x0000014C) +#define IOP331_IALR1 (volatile u32 *)IOP331_REG_ADDR(0x00000150) +#define IOP331_IALR2 (volatile u32 *)IOP331_REG_ADDR(0x00000154) +#define IOP331_IATVR2 (volatile u32 *)IOP331_REG_ADDR(0x00000158) +#define IOP331_OIOWTVR (volatile u32 *)IOP331_REG_ADDR(0x0000015C) +#define IOP331_OMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000160) +#define IOP331_OUMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000164) +#define IOP331_OMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x00000168) +#define IOP331_OUMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x0000016C) +/* Reserved 0x00000170 through 0x00000177*/ +#define IOP331_OUDWTVR (volatile u32 *)IOP331_REG_ADDR(0x00000178) +/* Reserved 0x0000017C through 0x0000017F*/ +#define IOP331_ATUCR (volatile u32 *)IOP331_REG_ADDR(0x00000180) +#define IOP331_PCSR (volatile u32 *)IOP331_REG_ADDR(0x00000184) +#define IOP331_ATUISR (volatile u32 *)IOP331_REG_ADDR(0x00000188) +#define IOP331_ATUIMR (volatile u32 *)IOP331_REG_ADDR(0x0000018C) +#define IOP331_IABAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000190) +#define IOP331_IAUBAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000194) +#define IOP331_IALR3 (volatile u32 *)IOP331_REG_ADDR(0x00000198) +#define IOP331_IATVR3 (volatile u32 *)IOP331_REG_ADDR(0x0000019C) +/* Reserved 0x000001A0 through 0x000001A3*/ +#define IOP331_OCCAR (volatile u32 *)IOP331_REG_ADDR(0x000001A4) +/* Reserved 0x000001A8 through 0x000001AB*/ +#define IOP331_OCCDR (volatile u32 *)IOP331_REG_ADDR(0x000001AC) +/* Reserved 0x000001B0 through 0x000001BB*/ +#define IOP331_VPDCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001B8) +#define IOP331_VPDNXTP (volatile u8 *)IOP331_REG_ADDR(0x000001B9) +#define IOP331_VPDAR (volatile u16 *)IOP331_REG_ADDR(0x000001BA) +#define IOP331_VPDDR (volatile u32 *)IOP331_REG_ADDR(0x000001BC) +#define IOP331_PMCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001C0) +#define IOP331_PMNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001C1) +#define IOP331_APMCR (volatile u16 *)IOP331_REG_ADDR(0x000001C2) +#define IOP331_APMCSR (volatile u16 *)IOP331_REG_ADDR(0x000001C4) +/* Reserved 0x000001C6 through 0x000001CF */ +#define IOP331_MSICAPID (volatile u8 *)IOP331_REG_ADDR(0x000001D0) +#define IOP331_MSINXTP (volatile u8 *)IOP331_REG_ADDR(0x000001D1) +#define IOP331_MSIMCR (volatile u16 *)IOP331_REG_ADDR(0x000001D2) +#define IOP331_MSIMAR (volatile u32 *)IOP331_REG_ADDR(0x000001D4) +#define IOP331_MSIMUAR (volatile u32 *)IOP331_REG_ADDR(0x000001D8) +#define IOP331_MSIMDR (volatile u32 *)IOP331_REG_ADDR(0x000001DC) +#define IOP331_PCIXCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001E0) +#define IOP331_PCIXNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001E1) +#define IOP331_PCIXCMD (volatile u16 *)IOP331_REG_ADDR(0x000001E2) +#define IOP331_PCIXSR (volatile u32 *)IOP331_REG_ADDR(0x000001E4) +#define IOP331_PCIIRSR (volatile u32 *)IOP331_REG_ADDR(0x000001EC) + +/* Messaging Unit 0x00000300 through 0x000003FF */ + +/* Reserved 0x00000300 through 0x0000030c */ +#define IOP331_IMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000310) +#define IOP331_IMR1 (volatile u32 *)IOP331_REG_ADDR(0x00000314) +#define IOP331_OMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000318) +#define IOP331_OMR1 (volatile u32 *)IOP331_REG_ADDR(0x0000031C) +#define IOP331_IDR (volatile u32 *)IOP331_REG_ADDR(0x00000320) +#define IOP331_IISR (volatile u32 *)IOP331_REG_ADDR(0x00000324) +#define IOP331_IIMR (volatile u32 *)IOP331_REG_ADDR(0x00000328) +#define IOP331_ODR (volatile u32 *)IOP331_REG_ADDR(0x0000032C) +#define IOP331_OISR (volatile u32 *)IOP331_REG_ADDR(0x00000330) +#define IOP331_OIMR (volatile u32 *)IOP331_REG_ADDR(0x00000334) +/* Reserved 0x00000338 through 0x0000034F */ +#define IOP331_MUCR (volatile u32 *)IOP331_REG_ADDR(0x00000350) +#define IOP331_QBAR (volatile u32 *)IOP331_REG_ADDR(0x00000354) +/* Reserved 0x00000358 through 0x0000035C */ +#define IOP331_IFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000360) +#define IOP331_IFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000364) +#define IOP331_IPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000368) +#define IOP331_IPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000036C) +#define IOP331_OFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000370) +#define IOP331_OFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000374) +#define IOP331_OPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000378) +#define IOP331_OPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000037C) +#define IOP331_IAR (volatile u32 *)IOP331_REG_ADDR(0x00000380) +/* Reserved 0x00000384 through 0x000003FF */ + +/* DMA Controller 0x00000400 through 0x000004FF */ +#define IOP331_DMA0_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000400) +#define IOP331_DMA0_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000404) +#define IOP331_DMA0_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000040C) +#define IOP331_DMA0_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000410) +#define IOP331_DMA0_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000414) +#define IOP331_DMA0_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000418) +#define IOP331_DMA0_LADR (volatile u32 *)IOP331_REG_ADDR(0X0000041C) +#define IOP331_DMA0_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000420) +#define IOP331_DMA0_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000424) +/* Reserved 0x00000428 through 0x0000043C */ +#define IOP331_DMA1_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000440) +#define IOP331_DMA1_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000444) +#define IOP331_DMA1_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000044C) +#define IOP331_DMA1_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000450) +#define IOP331_DMA1_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000454) +#define IOP331_DMA1_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000458) +#define IOP331_DMA1_LADR (volatile u32 *)IOP331_REG_ADDR(0x0000045C) +#define IOP331_DMA1_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000460) +#define IOP331_DMA1_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000464) +/* Reserved 0x00000468 through 0x000004FF */ + +/* Memory controller 0x00000500 through 0x0005FF */ + +/* Peripheral bus interface unit 0x00000680 through 0x0006FF */ +#define IOP331_PBCR (volatile u32 *)IOP331_REG_ADDR(0x00000680) +#define IOP331_PBISR (volatile u32 *)IOP331_REG_ADDR(0x00000684) +#define IOP331_PBBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000688) +#define IOP331_PBLR0 (volatile u32 *)IOP331_REG_ADDR(0x0000068C) +#define IOP331_PBBAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000690) +#define IOP331_PBLR1 (volatile u32 *)IOP331_REG_ADDR(0x00000694) +#define IOP331_PBBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000698) +#define IOP331_PBLR2 (volatile u32 *)IOP331_REG_ADDR(0x0000069C) +#define IOP331_PBBAR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A0) +#define IOP331_PBLR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A4) +#define IOP331_PBBAR4 (volatile u32 *)IOP331_REG_ADDR(0x000006A8) +#define IOP331_PBLR4 (volatile u32 *)IOP331_REG_ADDR(0x000006AC) +#define IOP331_PBBAR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B0) +#define IOP331_PBLR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B4) +#define IOP331_PBDSCR (volatile u32 *)IOP331_REG_ADDR(0x000006B8) +/* Reserved 0x000006BC */ +#define IOP331_PMBR0 (volatile u32 *)IOP331_REG_ADDR(0x000006C0) +/* Reserved 0x000006C4 through 0x000006DC */ +#define IOP331_PMBR1 (volatile u32 *)IOP331_REG_ADDR(0x000006E0) +#define IOP331_PMBR2 (volatile u32 *)IOP331_REG_ADDR(0x000006E4) + +#define IOP331_PBCR_EN 0x1 + +#define IOP331_PBISR_BOOR_ERR 0x1 + + + +/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */ +/* Internal arbitration unit 0x00000780 through 0x0007BF */ + +/* Interrupt Controller */ +#define IOP331_INTCTL0 (volatile u32 *)IOP331_REG_ADDR(0x00000790) +#define IOP331_INTCTL1 (volatile u32 *)IOP331_REG_ADDR(0x00000794) +#define IOP331_INTSTR0 (volatile u32 *)IOP331_REG_ADDR(0x00000798) +#define IOP331_INTSTR1 (volatile u32 *)IOP331_REG_ADDR(0x0000079C) +#define IOP331_IINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A0) +#define IOP331_IINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007A4) +#define IOP331_FINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A8) +#define IOP331_FINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007AC) +#define IOP331_IPR0 (volatile u32 *)IOP331_REG_ADDR(0x000007B0) +#define IOP331_IPR1 (volatile u32 *)IOP331_REG_ADDR(0x000007B4) +#define IOP331_IPR2 (volatile u32 *)IOP331_REG_ADDR(0x000007B8) +#define IOP331_IPR3 (volatile u32 *)IOP331_REG_ADDR(0x000007BC) +#define IOP331_INTBASE (volatile u32 *)IOP331_REG_ADDR(0x000007C0) +#define IOP331_INTSIZE (volatile u32 *)IOP331_REG_ADDR(0x000007C4) +#define IOP331_IINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007C8) +#define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC) + + +/* Timers */ + +#define IOP331_TU_TMR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D0) +#define IOP331_TU_TMR1 (volatile u32 *)IOP331_REG_ADDR(0x000007D4) + +#define IOP331_TMR_TC 0x01 +#define IOP331_TMR_EN 0x02 +#define IOP331_TMR_RELOAD 0x04 +#define IOP331_TMR_PRIVILEGED 0x09 + +#define IOP331_TMR_RATIO_1_1 0x00 +#define IOP331_TMR_RATIO_4_1 0x10 +#define IOP331_TMR_RATIO_8_1 0x20 +#define IOP331_TMR_RATIO_16_1 0x30 + +#define IOP331_TU_TCR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D8) +#define IOP331_TU_TCR1 (volatile u32 *)IOP331_REG_ADDR(0x000007DC) +#define IOP331_TU_TRR0 (volatile u32 *)IOP331_REG_ADDR(0x000007E0) +#define IOP331_TU_TRR1 (volatile u32 *)IOP331_REG_ADDR(0x000007E4) +#define IOP331_TU_TISR (volatile u32 *)IOP331_REG_ADDR(0x000007E8) +#define IOP331_TU_WDTCR (volatile u32 *)IOP331_REG_ADDR(0x000007EC) + +#if defined(CONFIG_ARCH_IOP331) +#define IOP331_TICK_RATE 266000000 /* 266 MHz IB clock */ +#endif + +#if defined(CONFIG_IOP331_STEPD) || defined(CONFIG_ARCH_IQ80333) +#undef IOP331_TICK_RATE +#define IOP331_TICK_RATE 333000000 /* 333 Mhz IB clock */ +#endif + +/* Application accelerator unit 0x00000800 - 0x000008FF */ +#define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800) +#define IOP331_AAU_ASR (volatile u32 *)IOP331_REG_ADDR(0x00000804) +#define IOP331_AAU_ADAR (volatile u32 *)IOP331_REG_ADDR(0x00000808) +#define IOP331_AAU_ANDAR (volatile u32 *)IOP331_REG_ADDR(0x0000080C) +#define IOP331_AAU_SAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000810) +#define IOP331_AAU_SAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000814) +#define IOP331_AAU_SAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000818) +#define IOP331_AAU_SAR4 (volatile u32 *)IOP331_REG_ADDR(0x0000081C) +#define IOP331_AAU_SAR5 (volatile u32 *)IOP331_REG_ADDR(0x0000082C) +#define IOP331_AAU_SAR6 (volatile u32 *)IOP331_REG_ADDR(0x00000830) +#define IOP331_AAU_SAR7 (volatile u32 *)IOP331_REG_ADDR(0x00000834) +#define IOP331_AAU_SAR8 (volatile u32 *)IOP331_REG_ADDR(0x00000838) +#define IOP331_AAU_SAR9 (volatile u32 *)IOP331_REG_ADDR(0x00000840) +#define IOP331_AAU_SAR10 (volatile u32 *)IOP331_REG_ADDR(0x00000844) +#define IOP331_AAU_SAR11 (volatile u32 *)IOP331_REG_ADDR(0x00000848) +#define IOP331_AAU_SAR12 (volatile u32 *)IOP331_REG_ADDR(0x0000084C) +#define IOP331_AAU_SAR13 (volatile u32 *)IOP331_REG_ADDR(0x00000850) +#define IOP331_AAU_SAR14 (volatile u32 *)IOP331_REG_ADDR(0x00000854) +#define IOP331_AAU_SAR15 (volatile u32 *)IOP331_REG_ADDR(0x00000858) +#define IOP331_AAU_SAR16 (volatile u32 *)IOP331_REG_ADDR(0x0000085C) +#define IOP331_AAU_SAR17 (volatile u32 *)IOP331_REG_ADDR(0x00000864) +#define IOP331_AAU_SAR18 (volatile u32 *)IOP331_REG_ADDR(0x00000868) +#define IOP331_AAU_SAR19 (volatile u32 *)IOP331_REG_ADDR(0x0000086C) +#define IOP331_AAU_SAR20 (volatile u32 *)IOP331_REG_ADDR(0x00000870) +#define IOP331_AAU_SAR21 (volatile u32 *)IOP331_REG_ADDR(0x00000874) +#define IOP331_AAU_SAR22 (volatile u32 *)IOP331_REG_ADDR(0x00000878) +#define IOP331_AAU_SAR23 (volatile u32 *)IOP331_REG_ADDR(0x0000087C) +#define IOP331_AAU_SAR24 (volatile u32 *)IOP331_REG_ADDR(0x00000880) +#define IOP331_AAU_SAR25 (volatile u32 *)IOP331_REG_ADDR(0x00000888) +#define IOP331_AAU_SAR26 (volatile u32 *)IOP331_REG_ADDR(0x0000088C) +#define IOP331_AAU_SAR27 (volatile u32 *)IOP331_REG_ADDR(0x00000890) +#define IOP331_AAU_SAR28 (volatile u32 *)IOP331_REG_ADDR(0x00000894) +#define IOP331_AAU_SAR29 (volatile u32 *)IOP331_REG_ADDR(0x00000898) +#define IOP331_AAU_SAR30 (volatile u32 *)IOP331_REG_ADDR(0x0000089C) +#define IOP331_AAU_SAR31 (volatile u32 *)IOP331_REG_ADDR(0x000008A0) +#define IOP331_AAU_SAR32 (volatile u32 *)IOP331_REG_ADDR(0x000008A4) +#define IOP331_AAU_DAR (volatile u32 *)IOP331_REG_ADDR(0x00000820) +#define IOP331_AAU_ABCR (volatile u32 *)IOP331_REG_ADDR(0x00000824) +#define IOP331_AAU_ADCR (volatile u32 *)IOP331_REG_ADDR(0x00000828) +#define IOP331_AAU_EDCR0 (volatile u32 *)IOP331_REG_ADDR(0x0000083c) +#define IOP331_AAU_EDCR1 (volatile u32 *)IOP331_REG_ADDR(0x00000860) +#define IOP331_AAU_EDCR2 (volatile u32 *)IOP331_REG_ADDR(0x00000884) + + +#define IOP331_SPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C0) +#define IOP331_PPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C8) +/* SSP serial port unit 0x00001600 - 0x0000167F */ + +/* I2C bus interface unit 0x00001680 - 0x000016FF */ +/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */ + +#define IOP331_ICR0 (volatile u32 *)IOP331_REG_ADDR(0x00001680) +#define IOP331_ISR0 (volatile u32 *)IOP331_REG_ADDR(0x00001684) +#define IOP331_ISAR0 (volatile u32 *)IOP331_REG_ADDR(0x00001688) +#define IOP331_IDBR0 (volatile u32 *)IOP331_REG_ADDR(0x0000168C) +/* Reserved 0x00001690 */ +#define IOP331_IBMR0 (volatile u32 *)IOP331_REG_ADDR(0x00001694) +/* Reserved 0x00001698 */ +/* Reserved 0x0000169C */ +#define IOP331_ICR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A0) +#define IOP331_ISR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A4) +#define IOP331_ISAR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A8) +#define IOP331_IDBR1 (volatile u32 *)IOP331_REG_ADDR(0x000016AC) +#define IOP331_IBMR1 (volatile u32 *)IOP331_REG_ADDR(0x000016B4) +/* Reserved 0x000016B8 through 0x000016FF */ + +/* 0x00001700 through 0x0000172C UART 0 */ + +/* Reserved 0x00001730 through 0x0000173F */ + +/* 0x00001740 through 0x0000176C UART 1 */ + +#define IOP331_UART0_PHYS (IOP331_PHYS_MEM_BASE | 0x00001700) /* UART #1 physical */ +#define IOP331_UART1_PHYS (IOP331_PHYS_MEM_BASE | 0x00001740) /* UART #2 physical */ +#define IOP331_UART0_VIRT (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */ +#define IOP331_UART1_VIRT (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */ + +/* Reserved 0x00001770 through 0x0000177F */ + +/* General Purpose I/O Registers */ +#define IOP331_GPOE (volatile u32 *)IOP331_REG_ADDR(0x00001780) +#define IOP331_GPID (volatile u32 *)IOP331_REG_ADDR(0x00001784) +#define IOP331_GPOD (volatile u32 *)IOP331_REG_ADDR(0x00001788) + +/* Reserved 0x0000178c through 0x000019ff */ + + +#ifndef __ASSEMBLY__ +extern void iop331_map_io(void); +extern void iop331_init_irq(void); +extern void iop331_time_init(void); +#endif + +#endif // _IOP331_HW_H_ diff --git a/include/asm-arm/arch-iop3xx/iq31244.h b/include/asm-arm/arch-iop3xx/iq31244.h new file mode 100644 index 000000000000..4177cfa8100f --- /dev/null +++ b/include/asm-arm/arch-iop3xx/iq31244.h @@ -0,0 +1,24 @@ +/* + * linux/include/asm/arch-iop3xx/iq31244.h + * + * Intel IQ31244 evaluation board registers + */ + +#ifndef _IQ31244_H_ +#define _IQ31244_H_ + +#define IQ31244_FLASHBASE 0xf0000000 /* Flash */ +#define IQ31244_FLASHSIZE 0x00800000 +#define IQ31244_FLASHWIDTH 2 + +#define IQ31244_UART 0xfe800000 /* UART #1 */ +#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */ +#define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ +#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ +#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */ + +#ifndef __ASSEMBLY__ +extern void iq31244_map_io(void); +#endif + +#endif // _IQ31244_H_ diff --git a/include/asm-arm/arch-iop3xx/iq80321.h b/include/asm-arm/arch-iop3xx/iq80321.h new file mode 100644 index 000000000000..cb8725979ffa --- /dev/null +++ b/include/asm-arm/arch-iop3xx/iq80321.h @@ -0,0 +1,24 @@ +/* + * linux/include/asm/arch-iop3xx/iq80321.h + * + * Intel IQ80321 evaluation board registers + */ + +#ifndef _IQ80321_H_ +#define _IQ80321_H_ + +#define IQ80321_FLASHBASE 0xf0000000 /* Flash */ +#define IQ80321_FLASHSIZE 0x00800000 +#define IQ80321_FLASHWIDTH 1 + +#define IQ80321_UART 0xfe800000 /* UART #1 */ +#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */ +#define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ +#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ +#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */ + +#ifndef __ASSEMBLY__ +extern void iq80321_map_io(void); +#endif + +#endif // _IQ80321_H_ diff --git a/include/asm-arm/arch-iop3xx/iq80331.h b/include/asm-arm/arch-iop3xx/iq80331.h new file mode 100644 index 000000000000..0668e78d483e --- /dev/null +++ b/include/asm-arm/arch-iop3xx/iq80331.h @@ -0,0 +1,23 @@ +/* + * linux/include/asm/arch-iop3xx/iq80331.h + * + * Intel IQ80331 evaluation board registers + */ + +#ifndef _IQ80331_H_ +#define _IQ80331_H_ + +#define IQ80331_FLASHBASE 0xc0000000 /* Flash */ +#define IQ80331_FLASHSIZE 0x00800000 +#define IQ80331_FLASHWIDTH 1 + +#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */ +#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ +#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */ +#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */ + +#ifndef __ASSEMBLY__ +extern void iq80331_map_io(void); +#endif + +#endif // _IQ80331_H_ diff --git a/include/asm-arm/arch-iop3xx/iq80332.h b/include/asm-arm/arch-iop3xx/iq80332.h new file mode 100644 index 000000000000..e5fff1775d1a --- /dev/null +++ b/include/asm-arm/arch-iop3xx/iq80332.h @@ -0,0 +1,23 @@ +/* + * linux/include/asm/arch-iop3xx/iq80332.h + * + * Intel IQ80332 evaluation board registers + */ + +#ifndef _IQ80332_H_ +#define _IQ80332_H_ + +#define IQ80332_FLASHBASE 0xc0000000 /* Flash */ +#define IQ80332_FLASHSIZE 0x00800000 +#define IQ80332_FLASHWIDTH 1 + +#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */ +#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ +#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */ +#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */ + +#ifndef __ASSEMBLY__ +extern void iq80332_map_io(void); +#endif + +#endif // _IQ80332_H_ diff --git a/include/asm-arm/arch-iop3xx/irqs.h b/include/asm-arm/arch-iop3xx/irqs.h new file mode 100644 index 000000000000..b2c03f4c269c --- /dev/null +++ b/include/asm-arm/arch-iop3xx/irqs.h @@ -0,0 +1,21 @@ +/* + * linux/include/asm-arm/arch-iop3xx/irqs.h + * + * Copyright: (C) 2001-2003 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/* + * Chipset-specific bits + */ +#ifdef CONFIG_ARCH_IOP321 +#include "iop321-irqs.h" +#endif + +#ifdef CONFIG_ARCH_IOP331 +#include "iop331-irqs.h" +#endif diff --git a/include/asm-arm/arch-iop3xx/memory.h b/include/asm-arm/arch-iop3xx/memory.h new file mode 100644 index 000000000000..dc4735cb0c10 --- /dev/null +++ b/include/asm-arm/arch-iop3xx/memory.h @@ -0,0 +1,41 @@ +/* + * linux/include/asm-arm/arch-iop3xx/memory.h + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#include <linux/config.h> +#include <asm/hardware.h> + +/* + * Physical DRAM offset. + */ +#ifndef CONFIG_ARCH_IOP331 +#define PHYS_OFFSET (0xa0000000UL) +#else +#define PHYS_OFFSET (0x00000000UL) +#endif + +/* + * Virtual view <-> PCI DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ +#if defined(CONFIG_ARCH_IOP321) + +#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0)) +#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2))) + +#elif defined(CONFIG_ARCH_IOP331) + +#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP331_IATVR2)) | ((*IOP331_IABAR2) & 0xfffffff0)) +#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP331_IALR2)) | ( *IOP331_IATVR2))) + +#endif + +#define PFN_TO_NID(addr) (0) + +#endif diff --git a/include/asm-arm/arch-iop3xx/param.h b/include/asm-arm/arch-iop3xx/param.h new file mode 100644 index 000000000000..acf404e87358 --- /dev/null +++ b/include/asm-arm/arch-iop3xx/param.h @@ -0,0 +1,3 @@ +/* + * linux/include/asm-arm/arch-iop3xx/param.h + */ diff --git a/include/asm-arm/arch-iop3xx/system.h b/include/asm-arm/arch-iop3xx/system.h new file mode 100644 index 000000000000..af6ae8cd36c9 --- /dev/null +++ b/include/asm-arm/arch-iop3xx/system.h @@ -0,0 +1,35 @@ +/* + * linux/include/asm-arm/arch-iop3xx/system.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + + +static inline void arch_reset(char mode) +{ +#ifdef CONFIG_ARCH_IOP321 + *IOP321_PCSR = 0x30; +#endif + +#ifdef CONFIG_ARCH_IOP331 + *IOP331_PCSR = 0x30; +#endif + + if ( 1 && mode == 's') { + /* Jump into ROM at address 0 */ + cpu_reset(0); + } else { + /* No on-chip reset capability */ + cpu_reset(0); + } +} + diff --git a/include/asm-arm/arch-iop3xx/timex.h b/include/asm-arm/arch-iop3xx/timex.h new file mode 100644 index 000000000000..d4187fe9a85a --- /dev/null +++ b/include/asm-arm/arch-iop3xx/timex.h @@ -0,0 +1,21 @@ +/* + * linux/include/asm-arm/arch-iop3xx/timex.h + * + * IOP3xx architecture timex specifications + */ +#include <linux/config.h> + + +#if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244) + +#define CLOCK_TICK_RATE IOP321_TICK_RATE + +#elif defined(CONFIG_ARCH_IQ80331) || defined(CONFIG_MACH_IQ80332) + +#define CLOCK_TICK_RATE IOP331_TICK_RATE + +#else + +#error "No IOP3xx timex information for this architecture" + +#endif diff --git a/include/asm-arm/arch-iop3xx/uncompress.h b/include/asm-arm/arch-iop3xx/uncompress.h new file mode 100644 index 000000000000..82b88762c3cc --- /dev/null +++ b/include/asm-arm/arch-iop3xx/uncompress.h @@ -0,0 +1,57 @@ +/* + * linux/include/asm-arm/arch-iop3xx/uncompress.h + */ +#include <linux/config.h> +#include <asm/types.h> +#include <asm/mach-types.h> +#include <linux/serial_reg.h> +#include <asm/hardware.h> + +#ifdef CONFIG_ARCH_IOP321 +#define UTYPE unsigned char * +#elif defined(CONFIG_ARCH_IOP331) +#define UTYPE u32 * +#else +#error "Missing IOP3xx arch type def" +#endif + +static volatile UTYPE uart_base; + +#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) + +static __inline__ void putc(char c) +{ + while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE); + *uart_base = c; +} + +/* + * This does not append a newline + */ +static void putstr(const char *s) +{ + while (*s) { + putc(*s); + if (*s == '\n') + putc('\r'); + s++; + } +} + +static __inline__ void __arch_decomp_setup(unsigned long arch_id) +{ + if(machine_is_iq80321()) + uart_base = (volatile UTYPE)IQ80321_UART; + else if(machine_is_iq31244()) + uart_base = (volatile UTYPE)IQ31244_UART; + else if(machine_is_iq80331() || machine_is_iq80332()) + uart_base = (volatile UTYPE)IOP331_UART0_PHYS; + else + uart_base = (volatile UTYPE)0xfe800000; +} + +/* + * nothing to do + */ +#define arch_decomp_setup() __arch_decomp_setup(arch_id) +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-iop3xx/vmalloc.h b/include/asm-arm/arch-iop3xx/vmalloc.h new file mode 100644 index 000000000000..dc1d2a957164 --- /dev/null +++ b/include/asm-arm/arch-iop3xx/vmalloc.h @@ -0,0 +1,19 @@ +/* + * linux/include/asm-arm/arch-iop3xx/vmalloc.h + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +#define VMALLOC_OFFSET (8*1024*1024) +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) +//#define VMALLOC_END (0xe8000000) +/* increase usable physical RAM to ~992M per RMK */ +#define VMALLOC_END (0xfe000000) + |
