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authorLaxman Dewangan <ldewangan@nvidia.com>2015-06-30 16:24:27 +0530
committerWolfram Sang <wsa@the-dreams.de>2015-08-10 08:37:33 +0200
commitd57f5dedde18253d5c72a823c0a7ff3b20b57560 (patch)
tree24f1c7e3a703883c02d0dcb8bc528997f83a5dcf /drivers/xen
parent6f4664b2e2c2cfa35b48271423c5e602b6970f14 (diff)
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i2c: tegra: add support for fast plus (FM+) mode clock rate
Tegra I2C controller required to configure the clock divisor register inside controller to different value based on the clock speed. The recommended clock divisor for the I2C controller for standard/fast mode is 0x19 and for fast-mode plus is 0x10. Add support to configure clock divisor register of I2C controller based on bus clock rate. This clock divisor is supported form T114 onwards. Signed-off-by: Chaitanya Bandi <bandik@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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