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authorChen-Yu Tsai <wens@csie.org>2014-07-03 22:55:42 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-07-07 10:53:52 +0200
commitcd6eb534fbb8c9c52e6900f6b086d8c95f966449 (patch)
treec562594be8c193d6a37feb14e72aa195e563fb60 /drivers/virtio/Kconfig
parent57a1fbf28424561a080b34fbdd04661282aea40e (diff)
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clk: sunxi: Fix gate indexing for sun6i-a31-apb0-gates
sun6i-a31-apb0-gates supports using clock-indices for holes between individual gates. However, the driver passes the number of gates registered in clk_data->clk_num, which of_clk_src_onecell_get uses to recognize the range of valid indices a consumer can use. This patch makes the driver pass the maximum gate index + 1, so of_clk_src_onecell_get does not complain about indices greater than gates registered. This was tested on the A23 SoC, which has a similar APB0 clock, but has holes for gates to removed IP blocks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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