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authorZhu Yi <yi.zhu@intel.com>2006-01-24 16:36:36 +0800
committerJohn W. Linville <linville@tuxdriver.com>2006-01-30 20:35:32 -0500
commitc8fe6679086a983c4c95a441f3246c7aaecab80a (patch)
treee218762630b2d321e4d970417835b70949fe8c65 /drivers/net/wireless/ipw2200.h
parent71aa122d8a510b79338e28e2d56326574642d000 (diff)
downloadblackbird-op-linux-c8fe6679086a983c4c95a441f3246c7aaecab80a.tar.gz
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[PATCH] ipw2200: Fix indirect SRAM/register 8/16-bit write routines
The indirect SRAM/register 8/16-bit write routines are broken for non-dword-aligned destination addresses. Fortunately, these routines are, so far, not used for non-dword-aligned destinations, but here's a patch that fixes them, anyway. The attached patch also adds comments for all direct/indirect I/O routine variations. Signed-off-by: Ben M Cahill <ben.m.cahill@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ipw2200.h')
-rw-r--r--drivers/net/wireless/ipw2200.h13
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/net/wireless/ipw2200.h b/drivers/net/wireless/ipw2200.h
index e2afa76ad3cd..44ff76386a8e 100644
--- a/drivers/net/wireless/ipw2200.h
+++ b/drivers/net/wireless/ipw2200.h
@@ -1406,13 +1406,6 @@ do { if (ipw_debug_level & (level)) \
* Register bit definitions
*/
-/* Dino control registers bits */
-
-#define DINO_ENABLE_SYSTEM 0x80
-#define DINO_ENABLE_CS 0x40
-#define DINO_RXFIFO_DATA 0x01
-#define DINO_CONTROL_REG 0x00200000
-
#define IPW_INTA_RW 0x00000008
#define IPW_INTA_MASK_R 0x0000000C
#define IPW_INDIRECT_ADDR 0x00000010
@@ -1459,6 +1452,12 @@ do { if (ipw_debug_level & (level)) \
#define IPW_DOMAIN_0_END 0x1000
#define CLX_MEM_BAR_SIZE 0x1000
+
+/* Dino/baseband control registers bits */
+
+#define DINO_ENABLE_SYSTEM 0x80 /* 1 = baseband processor on, 0 = reset */
+#define DINO_ENABLE_CS 0x40 /* 1 = enable ucode load */
+#define DINO_RXFIFO_DATA 0x01 /* 1 = data available */
#define IPW_BASEBAND_CONTROL_STATUS 0X00200000
#define IPW_BASEBAND_TX_FIFO_WRITE 0X00200004
#define IPW_BASEBAND_RX_FIFO_READ 0X00200004
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