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authorRafał Miłecki <zajec5@gmail.com>2013-03-17 19:08:15 +0100
committerRafał Miłecki <zajec5@gmail.com>2013-04-23 12:27:56 +0200
commitfc6ab1e0c032f3ae3f20e405c5ca51f20540b52c (patch)
treeb84c606c6f8080f7b6b0d56f66a331eec5ea47e5 /drivers/net/wireless/b43
parentdc3c4e127168dff9dbef0b22351b592a81fe5bfb (diff)
downloadblackbird-op-linux-fc6ab1e0c032f3ae3f20e405c5ca51f20540b52c.tar.gz
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b43: HT-PHY: define regs for power estimation
In MMIO dumps of ndiswrapper there are following PHY ops: phy_read(0x0118) -> 0x013d phy_read(0x01ed) -> 0x993d phy_read(0x0119) -> 0x012f phy_read(0x01ee) -> 0x992f phy_read(0x011a) -> 0x0139 phy_read(0x0969) -> 0x9939 It matches the code of wlc_phy_txpower_est_power_nphy (from brcm80211), so we know the registers meaning. Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Diffstat (limited to 'drivers/net/wireless/b43')
-rw-r--r--drivers/net/wireless/b43/phy_ht.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/wireless/b43/phy_ht.h b/drivers/net/wireless/b43/phy_ht.h
index 9b2408efb224..6cae370d1018 100644
--- a/drivers/net/wireless/b43/phy_ht.h
+++ b/drivers/net/wireless/b43/phy_ht.h
@@ -23,6 +23,9 @@
#define B43_PHY_HT_SAMP_WAIT_CNT 0x0C5 /* Sample wait count */
#define B43_PHY_HT_SAMP_DEP_CNT 0x0C6 /* Sample depth count */
#define B43_PHY_HT_SAMP_STAT 0x0C7 /* Sample status */
+#define B43_PHY_HT_EST_PWR_C1 0x118
+#define B43_PHY_HT_EST_PWR_C2 0x119
+#define B43_PHY_HT_EST_PWR_C3 0x11A
#define B43_PHY_HT_TSSIMODE 0x122 /* TSSI mode */
#define B43_PHY_HT_TSSIMODE_EN 0x0001 /* TSSI enable */
#define B43_PHY_HT_TSSIMODE_PDEN 0x0002 /* Power det enable */
@@ -53,6 +56,8 @@
#define B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT 0
#define B43_PHY_HT_TXPCTL_TARG_PWR_C2 0xFF00 /* Power 1 */
#define B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT 8
+#define B43_PHY_HT_TX_PCTL_STATUS_C1 0x1ED
+#define B43_PHY_HT_TX_PCTL_STATUS_C2 0x1EE
#define B43_PHY_HT_TXPCTL_CMD_C2 0x222
#define B43_PHY_HT_TXPCTL_CMD_C2_INIT 0x007F
#define B43_PHY_HT_RSSI_C1 0x219
@@ -97,6 +102,7 @@
#define B43_PHY_HT_TXPCTL_TARG_PWR2 B43_PHY_EXTG(0x166) /* TX power control target power */
#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3 0x00FF
#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT 0
+#define B43_PHY_HT_TX_PCTL_STATUS_C3 B43_PHY_EXTG(0x169)
#define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A)
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