diff options
| author | Stephen Hemminger <shemminger@linux-foundation.org> | 2007-08-29 12:58:12 -0700 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2007-10-10 16:50:52 -0700 |
| commit | efcf6e2febbfe5b2ab497421e2f7f188e1741cf9 (patch) | |
| tree | 150fe73fa32b833131c68749f59710d79a283436 /drivers/net/sky2.h | |
| parent | 5b296bc9e1e5570ce60262e62af066f70180cb99 (diff) | |
| download | blackbird-op-linux-efcf6e2febbfe5b2ab497421e2f7f188e1741cf9.tar.gz blackbird-op-linux-efcf6e2febbfe5b2ab497421e2f7f188e1741cf9.zip | |
sky2: document GPHY_CTRL bits
Add documentation of GPHY_CTRL register bits even if driver
is not using them (yet).
Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/sky2.h')
| -rw-r--r-- | drivers/net/sky2.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h index f18f8752118e..3d4f1903d62c 100644 --- a/drivers/net/sky2.h +++ b/drivers/net/sky2.h @@ -1850,6 +1850,28 @@ enum { /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ enum { + GPC_TX_PAUSE = 1<<30, /* Tx pause enabled (ro) */ + GPC_RX_PAUSE = 1<<29, /* Rx pause enabled (ro) */ + GPC_SPEED = 3<<27, /* PHY speed (ro) */ + GPC_LINK = 1<<26, /* Link up (ro) */ + GPC_DUPLEX = 1<<25, /* Duplex (ro) */ + GPC_CLOCK = 1<<24, /* 125Mhz clock stable (ro) */ + + GPC_PDOWN = 1<<23, /* Internal regulator 2.5 power down */ + GPC_TSTMODE = 1<<22, /* Test mode */ + GPC_REG18 = 1<<21, /* Reg18 Power down */ + GPC_REG12SEL = 3<<19, /* Reg12 power setting */ + GPC_REG18SEL = 3<<17, /* Reg18 power setting */ + GPC_SPILOCK = 1<<16, /* SPI lock (ASF) */ + + GPC_LEDMUX = 3<<14, /* LED Mux */ + GPC_INTPOL = 1<<13, /* Interrupt polarity */ + GPC_DETECT = 1<<12, /* Energy detect */ + GPC_1000HD = 1<<11, /* Enable 1000Mbit HD */ + GPC_SLAVE = 1<<10, /* Slave mode */ + GPC_PAUSE = 1<<9, /* Pause enable */ + GPC_LEDCTL = 3<<6, /* GPHY Leds */ + GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */ GPC_RST_SET = 1<<0, /* Set GPHY Reset */ }; |
