diff options
| author | Francesco Virlinzi <francesco.virlinzi@st.com> | 2011-11-16 21:57:58 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2011-11-17 03:13:41 -0500 |
| commit | bbc1754639f771cd2b515fed39b977549b373034 (patch) | |
| tree | 7f5cd57925266ec2484d5f6f2e0fc2d434a2b82a /drivers/net/ethernet/stmicro | |
| parent | d9fa7c86f1fca60693beea187c963cfda4a54a06 (diff) | |
| download | blackbird-op-linux-bbc1754639f771cd2b515fed39b977549b373034.tar.gz blackbird-op-linux-bbc1754639f771cd2b515fed39b977549b373034.zip | |
stmmac: use mdelay on timeout of sw reset
This patch uses an mdelay to manage the timeout on
sw reset to be independant of cpu_clk.
Signed-off-by: Francesco Virlinzi <francesco.virlinzi@st.com>
Reviewed-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/stmicro')
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c | 3 | ||||
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c index da66ac511c4c..4d5402a1d262 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c @@ -39,10 +39,11 @@ static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx, /* DMA SW reset */ value |= DMA_BUS_MODE_SFT_RESET; writel(value, ioaddr + DMA_BUS_MODE); - limit = 15000; + limit = 10; while (limit--) { if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) break; + mdelay(10); } if (limit < 0) return -EBUSY; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c index 627f656b0f3c..bc17fd08b55d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c @@ -41,10 +41,11 @@ static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx, /* DMA SW reset */ value |= DMA_BUS_MODE_SFT_RESET; writel(value, ioaddr + DMA_BUS_MODE); - limit = 15000; + limit = 10; while (limit--) { if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) break; + mdelay(10); } if (limit < 0) return -EBUSY; |
