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| author | Maciej W. Rozycki <macro@linux-mips.org> | 2006-10-23 13:53:17 +0100 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2006-12-02 00:12:01 -0500 |
| commit | b2e68aa337f950e4a8c893a82b95b1755309bc56 (patch) | |
| tree | 4f7696e09d08cb173306e68bfdc4dc98aa97ef0b /drivers/net/defxx.h | |
| parent | c3a9392e4f3b9d97803b067871d66bc143369dbf (diff) | |
| download | blackbird-op-linux-b2e68aa337f950e4a8c893a82b95b1755309bc56.tar.gz blackbird-op-linux-b2e68aa337f950e4a8c893a82b95b1755309bc56.zip | |
[PATCH] defxx: Big-endian hosts support
The PDQ DMA engine requires a different byte-swapping mode for big-endian
hosts; also the MAC address which is read from a register through PIO has
to be byte-swapped. These changes have been verified with DEFPA-DC (PCI)
boards and a Broadcom BCM91250A (MIPS CPU based) host.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/defxx.h')
| -rw-r--r-- | drivers/net/defxx.h | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/net/defxx.h b/drivers/net/defxx.h index 8b1e9a11ca21..2ce8f97253eb 100644 --- a/drivers/net/defxx.h +++ b/drivers/net/defxx.h @@ -25,6 +25,7 @@ * macros to DEFXX.C. * 12-Sep-96 LVS Removed packet request header pointers. * 04 Aug 2003 macro Converted to the DMA API. + * 23 Oct 2006 macro Big-endian host support. */ #ifndef _DEFXX_H_ @@ -1344,7 +1345,7 @@ typedef struct /* Register definition structures are defined for both big and little endian systems */ -#ifndef BIG_ENDIAN +#ifndef __BIG_ENDIAN /* Little endian format of Type 1 Producer register */ @@ -1402,7 +1403,11 @@ typedef union } index; } PI_TYPE_2_CONSUMER; -#else +/* Define swapping required by DMA transfers. */ +#define PI_PDATA_A_INIT_M_BSWAP_INIT \ + (PI_PDATA_A_INIT_M_BSWAP_DATA) + +#else /* __BIG_ENDIAN */ /* Big endian format of Type 1 Producer register */ @@ -1460,7 +1465,11 @@ typedef union } index; } PI_TYPE_2_CONSUMER; -#endif /* #ifndef BIG_ENDIAN */ +/* Define swapping required by DMA transfers. */ +#define PI_PDATA_A_INIT_M_BSWAP_INIT \ + (PI_PDATA_A_INIT_M_BSWAP_DATA | PI_PDATA_A_INIT_M_BSWAP_LITERAL) + +#endif /* __BIG_ENDIAN */ /* Define EISA controller register offsets */ |
