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| author | Robert Richter <robert.richter@amd.com> | 2011-11-08 15:52:15 +0100 |
|---|---|---|
| committer | Robert Richter <robert.richter@amd.com> | 2011-11-08 15:52:15 +0100 |
| commit | de346b6949063aa040ef607943b072835294f4b3 (patch) | |
| tree | 11f5a10b9ab41a10ea26bf8ab1f133b802e7559e /drivers/net/bnx2x/bnx2x_reg.h | |
| parent | dcfce4a095932e6e95d83ad982be3609947963bc (diff) | |
| parent | 9c48f1c629ecfa114850c03f875c6691003214de (diff) | |
| download | blackbird-op-linux-de346b6949063aa040ef607943b072835294f4b3.tar.gz blackbird-op-linux-de346b6949063aa040ef607943b072835294f4b3.zip | |
Merge branch 'perf/core' into oprofile/master
Merge reason: Resolve conflicts with Don's NMI rework:
commit 9c48f1c629ecfa114850c03f875c6691003214de
Author: Don Zickus <dzickus@redhat.com>
Date: Fri Sep 30 15:06:21 2011 -0400
x86, nmi: Wire up NMI handlers to new routines
Conflicts:
arch/x86/oprofile/nmi_timer_int.c
Signed-off-by: Robert Richter <robert.richter@amd.com>
Diffstat (limited to 'drivers/net/bnx2x/bnx2x_reg.h')
| -rw-r--r-- | drivers/net/bnx2x/bnx2x_reg.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h index 750e8445dac4..fc7bd0f23c0b 100644 --- a/drivers/net/bnx2x/bnx2x_reg.h +++ b/drivers/net/bnx2x/bnx2x_reg.h @@ -1384,6 +1384,18 @@ Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8 +/* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped + * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC + * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] + * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 + * parity; [31-10] Reserved; */ +#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688 +/* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped + * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC + * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] + * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 + * parity; [31-10] Reserved; */ +#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu 128 bit vector */ #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000 |
