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authorJaehoon Chung <jh80.chung@samsung.com>2011-02-24 13:46:11 +0900
committerChris Ball <cjb@laptop.org>2011-03-15 13:51:47 -0400
commit41babf753cc82ab6208903625a084bf305c32d06 (patch)
tree1418a029223084fc3860a64683b3a65b0baeec0a /drivers/mmc/host
parente7054ba1f73c0a0e2489251499bdbc21b88b4190 (diff)
downloadblackbird-op-linux-41babf753cc82ab6208903625a084bf305c32d06.tar.gz
blackbird-op-linux-41babf753cc82ab6208903625a084bf305c32d06.zip
mmc: dw_mmc: support DDR mode
This patch adds DDR mode support to dw_mmc. If we set any bit in UHS_REG bit[16:31], the card of that slot is supported for DDR mode. For example, if UHS_REG[16] is set, card number 0 is DDR mode. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Will Newton <will.newton@imgtec.com> Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers/mmc/host')
-rw-r--r--drivers/mmc/host/dw_mmc.c8
-rw-r--r--drivers/mmc/host/dw_mmc.h2
2 files changed, 9 insertions, 1 deletions
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 62c8440ff04b..58476c1bb056 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -662,6 +662,7 @@ static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct dw_mci_slot *slot = mmc_priv(mmc);
+ u32 regs;
/* set default 1 bit mode */
slot->ctype = SDMMC_CTYPE_1BIT;
@@ -678,6 +679,13 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
break;
}
+ /* DDR mode set */
+ if (ios->ddr) {
+ regs = mci_readl(slot->host, UHS_REG);
+ regs |= (0x1 << slot->id) << 16;
+ mci_writel(slot->host, UHS_REG, regs);
+ }
+
if (ios->clock) {
/*
* Use mirror of ios->clock to prevent race with mmc
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 5dd55a75233d..23c662af5616 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -43,6 +43,7 @@
#define SDMMC_USRID 0x068
#define SDMMC_VERID 0x06c
#define SDMMC_HCON 0x070
+#define SDMMC_UHS_REG 0x074
#define SDMMC_BMOD 0x080
#define SDMMC_PLDMND 0x084
#define SDMMC_DBADDR 0x088
@@ -51,7 +52,6 @@
#define SDMMC_DSCADDR 0x094
#define SDMMC_BUFADDR 0x098
#define SDMMC_DATA 0x100
-#define SDMMC_DATA_ADR 0x100
/* shift bit field */
#define _SBF(f, v) ((v) << (f))
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