diff options
| author | Michel Thierry <michel.thierry@intel.com> | 2014-07-07 12:40:17 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-07-07 18:31:14 +0200 |
| commit | b3f9ad93b7621364ed51f9c37b9cf9abc9855991 (patch) | |
| tree | 499e5dcc514ed37b8e4629b2c5a62f376d2103b9 /drivers/gpu | |
| parent | a7de62fe94deda8339c72d03ffd4bd5586aa20cb (diff) | |
| download | blackbird-op-linux-b3f9ad93b7621364ed51f9c37b9cf9abc9855991.tar.gz blackbird-op-linux-b3f9ad93b7621364ed51f9c37b9cf9abc9855991.zip | |
drm/i915/bdw: 3D_CHICKEN3 has write mask bits
The workaround to limit SDE poly depth FIFO to 2 is not applied because
3D Chicken-3 mask bit is not set.
WaLimitSizeOfSDEPolyFifo is only for BDW-A and could be removed.
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 41c1b79959f7..f2a40565ef98 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5375,7 +5375,7 @@ static void gen8_init_clock_gating(struct drm_device *dev) I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE)); I915_WRITE(_3D_CHICKEN3, - _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)); + _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2))); I915_WRITE(COMMON_SLICE_CHICKEN2, _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); |
