drm/radeon/kms: respect TOM on rs100->rs480 IGP variants.

Normally we are free to place VRAM where we want in the GPUs
memory address space, however on IGP chips the VRAM is actual RAM,
and no special translation or aperture is used inside the GPU MC.

So when you move the VRAM aperture away from the TOM register,
you actually move it into main memory and can trash things quite badly.

This commit makes the code respect the TOM location for MC_FB_LOCATION.

Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 4 insertions, 2 deletions

diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 3275de4b6e3b..a18d053065c0 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -235,7 +235,6 @@ int rs400_mc_init(struct radeon_device *rdev)
 	rdev->mc.gtt_location = rdev->mc.vram_size;
 	rdev->mc.gtt_location += (rdev->mc.gtt_size - 1);
 	rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1);
-	rdev->mc.vram_location = 0xFFFFFFFFUL;
 	r = radeon_mc_setup(rdev);
 	if (r) {
 		return r;
@@ -305,7 +304,10 @@ void rs400_vram_info(struct radeon_device *rdev)
 	rdev->mc.vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
 	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
 
-	/* Could aper size report 0 ? */
+	/* RS480 IGPs don't seem to translate to main RAM, they
+	 * just reserve and scan out of it. So setting VRAM location
+	 * to say 0, will actually trash the OS. */
+	rdev->mc.vram_location = (tom & 0xffff) << 16;
 	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 }