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| author | Alex Deucher <alexdeucher@gmail.com> | 2009-10-15 01:33:35 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2009-10-15 15:33:46 +1000 |
| commit | 1b4d7d75ccff38008ccd40f8e2d74e33a087caaa (patch) | |
| tree | 115c2aff76fc4805f63c511a41bbf48268ba5c08 /drivers/gpu/drm/radeon/radeon_legacy_encoders.c | |
| parent | 8c2a6d730400e14bf28ccfa11b9bbf453db775ec (diff) | |
| download | blackbird-op-linux-1b4d7d75ccff38008ccd40f8e2d74e33a087caaa.tar.gz blackbird-op-linux-1b4d7d75ccff38008ccd40f8e2d74e33a087caaa.zip | |
drm/radeon/kms: fix internal tmds setup on legacy display engine
- crtc 0 routing was wrong
- need to clear various timing bits in FP_GEN_CNTL
- need to set FP_H/V2_SYNC_STRT_WID regs for crtc 1
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_legacy_encoders.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c index 3a75b5b6009b..00382122869b 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c @@ -542,6 +542,14 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); + fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | + RADEON_FP_DFP_SYNC_SEL | + RADEON_FP_CRT_SYNC_SEL | + RADEON_FP_CRTC_LOCK_8DOT | + RADEON_FP_USE_SHADOW_EN | + RADEON_FP_CRTC_USE_SHADOW_VEND | + RADEON_FP_CRT_SYNC_ALT); + if (1) /* FIXME rgbBits == 8 */ fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ else @@ -555,7 +563,7 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, else fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; } else - fp_gen_cntl |= RADEON_FP_SEL_CRTC1; + fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; } else { if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; |
