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authorRoy Spliet <r.spliet@student.tudelft.nl>2012-01-09 15:23:07 +1000
committerBen Skeggs <bskeggs@redhat.com>2012-03-13 17:07:50 +1000
commitc7c039fd31be82ecb8d48477955e76badd38141a (patch)
tree0b527eba7fd021ce99c52d9f744d503d0919849c /drivers/gpu/drm/nouveau/nouveau_drv.h
parent03ddf04bdb9cc4cdf8edb231b78f031647498314 (diff)
downloadblackbird-op-linux-c7c039fd31be82ecb8d48477955e76badd38141a.tar.gz
blackbird-op-linux-c7c039fd31be82ecb8d48477955e76badd38141a.zip
drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validation
Roy Spliet: - Implement according to specs - Simplify - Make array for mc latency registers Martin Peres: - squash and split all the commits from Roy - rework following Ben Skeggs comments - add a form of timings validation - store the initial timings for later use Ben Skeggs - merge slightly modified tidy-up patch with this one - remove perflvl-dropping logic for the moment Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_drv.h')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h38
1 files changed, 19 insertions, 19 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index c5105326db7f..f5700418da3f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -432,25 +432,26 @@ struct nouveau_pm_voltage {
int nr_level;
};
+/* Exclusive upper limits */
+#define NV_MEM_CL_DDR2_MAX 8
+#define NV_MEM_WR_DDR2_MAX 9
+#define NV_MEM_CL_DDR3_MAX 17
+#define NV_MEM_WR_DDR3_MAX 17
+#define NV_MEM_CL_GDDR3_MAX 16
+#define NV_MEM_WR_GDDR3_MAX 18
+#define NV_MEM_CL_GDDR5_MAX 21
+#define NV_MEM_WR_GDDR5_MAX 20
+
struct nouveau_pm_memtiming {
int id;
- u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */
- u32 reg_1;
- u32 reg_2;
- u32 reg_3;
- u32 reg_4;
- u32 reg_5;
- u32 reg_6;
- u32 reg_7;
- u32 reg_8;
- /* To be written to 0x1002c0 */
- u8 CL;
- u8 WR;
+
+ u32 reg[9];
+ u32 mr[4];
+
u8 tCWL;
- bool odt;
- bool dll_disable;
- bool ron_pull;
+ u8 odt;
+ u8 drive_strength;
};
struct nouveau_pm_tbl_header {
@@ -527,8 +528,10 @@ struct nouveau_pm_threshold_temp {
struct nouveau_pm_memtimings {
bool supported;
+ struct nouveau_pm_memtiming boot;
struct nouveau_pm_memtiming *timing;
int nr_timing;
+ int nr_timing_valid;
};
struct nouveau_pm_fan {
@@ -796,6 +799,7 @@ struct drm_nouveau_private {
} vram_type;
uint64_t vram_size;
uint64_t vram_sys_base;
+ bool vram_rank_B;
uint64_t fb_available_size;
uint64_t fb_mappable_pages;
@@ -927,10 +931,6 @@ extern void nv10_mem_put_tile_region(struct drm_device *dev,
struct nouveau_fence *fence);
extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
-void nv30_mem_timing_entry(struct drm_device *dev,
- struct nouveau_pm_tbl_header *hdr,
- struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
- struct nouveau_pm_memtiming *timing);
/* nouveau_notifier.c */
extern int nouveau_notifier_init_channel(struct nouveau_channel *);
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